diff options
| -rw-r--r-- | CHANGES | 7 | ||||
| -rw-r--r-- | src/gpgpu-sim/addrdec.cc | 20 | ||||
| -rw-r--r-- | src/gpgpu-sim/addrdec.h | 3 |
3 files changed, 25 insertions, 5 deletions
@@ -36,9 +36,10 @@ Version 3.2.1+edits (development branch) versus 3.2.1 cache banks (sub partitions) in each memory partition. Each memory partition contains a single DRAM scheduler, and one or more L2 cache banks. Each L2 cache bank has an independent port to the interconnection network. The - configuration files are changes to have a larger DRAM return queue to allow - the credit-based arbiter between the sub partitions and the DRAM scheduler to - tolerate the minimum DRAM latency. + address decoder is extended to use the DRAM bank ID to assign the L2 banks + within each memory partition. The configuration files are changes to have a + larger DRAM return queue to allow the credit-based arbiter between the sub + partitions and the DRAM scheduler to tolerate the minimum DRAM latency. - Added a bandwidth model to throttle the cache hit bandwidth. Now accesses that exceed the data port width (but still fit within a cache line) will occupy the cache for multiple cycles. This allows us to decouple the L2 diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc index c1fa6e5..422576d 100644 --- a/src/gpgpu-sim/addrdec.cc +++ b/src/gpgpu-sim/addrdec.cc @@ -67,12 +67,14 @@ void linear_to_raw_address_translation::addrdec_setoption(option_parser_t opp) new_addr_type linear_to_raw_address_translation::partition_address( new_addr_type addr ) const { if (!gap) { - return addrdec_packbits( ~addrdec_mask[CHIP], addr, 64, 0 ); + return addrdec_packbits( ~(addrdec_mask[CHIP] | sub_partition_id_mask), addr, 64, 0 ); } else { // see addrdec_tlx for explanation unsigned long long int partition_addr; partition_addr = ( (addr>>ADDR_CHIP_S) / m_n_channel) << ADDR_CHIP_S; partition_addr |= addr & ((1 << ADDR_CHIP_S) - 1); + // remove the part of address that constributes to the sub partition ID + partition_addr = addrdec_packbits( ~sub_partition_id_mask, partition_addr, 64, 0); return partition_addr; } } @@ -304,6 +306,22 @@ void linear_to_raw_address_translation::init(unsigned int n_channel, unsigned in printf("addr_dec_mask[COL] = %016llx \thigh:%d low:%d\n", addrdec_mask[COL], addrdec_mkhigh[COL], addrdec_mklow[COL] ); printf("addr_dec_mask[BURST] = %016llx \thigh:%d low:%d\n", addrdec_mask[BURST], addrdec_mkhigh[BURST], addrdec_mklow[BURST]); + // create the sub partition ID mask (for removing the sub partition ID from the partition address) + sub_partition_id_mask = 0; + if (m_n_sub_partition_in_channel > 1) { + unsigned n_sub_partition_log2 = LOGB2_32(m_n_sub_partition_in_channel); + unsigned pos=0; + for (unsigned i=addrdec_mklow[BK];i<addrdec_mkhigh[BK];i++) { + if ((addrdec_mask[BK] & ((unsigned long long int)1<<i)) != 0) { + sub_partition_id_mask |= ((unsigned long long int)1<<i); + pos++; + if (pos >= n_sub_partition_log2) + break; + } + } + } + printf("sub_partition_id_mask = %016llx\n", sub_partition_id_mask); + if (run_test) { sweep_test(); } diff --git a/src/gpgpu-sim/addrdec.h b/src/gpgpu-sim/addrdec.h index f16c9b1..fd9af8d 100644 --- a/src/gpgpu-sim/addrdec.h +++ b/src/gpgpu-sim/addrdec.h @@ -78,7 +78,8 @@ private: unsigned char addrdec_mklow[N_ADDRDEC]; unsigned char addrdec_mkhigh[N_ADDRDEC]; new_addr_type addrdec_mask[N_ADDRDEC]; - + new_addr_type sub_partition_id_mask; + unsigned int gap; int m_n_channel; int m_n_sub_partition_in_channel; |