summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--configs/tested-cfgs/SM2_GTX480/gpgpusim.config2
-rw-r--r--configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config2
-rw-r--r--configs/tested-cfgs/SM6_TITANX/gpgpusim.config2
-rw-r--r--configs/tested-cfgs/SM75_RTX2060/gpgpusim.config2
-rw-r--r--configs/tested-cfgs/SM75_RTX2060_S/gpgpusim.config2
-rw-r--r--configs/tested-cfgs/SM7_GV100/gpgpusim.config2
-rw-r--r--configs/tested-cfgs/SM7_QV100/gpgpusim.config2
-rw-r--r--configs/tested-cfgs/SM7_TITANV/gpgpusim.config2
-rw-r--r--configs/tested-cfgs/SM86_RTX3070/gpgpusim.config2
-rw-r--r--src/gpgpu-sim/gpu-cache.h22
10 files changed, 25 insertions, 15 deletions
diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
index 609a9ef..bc01821 100644
--- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
@@ -56,7 +56,7 @@
# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
-gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,S:64:8,8
diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
index c83159f..ef47ddf 100644
--- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
+++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config
@@ -99,7 +99,7 @@
# Greedy then oldest scheduler
-gpgpu_scheduler gto
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
# The defulat is to disable the L1 cache, unless cache modifieres are used
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index 652f0a0..7d3e2d4 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -123,7 +123,7 @@
-gpgpu_dual_issue_diff_exec_units 1
## L1/shared memory configuration
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
# The defulat is to disable the L1 cache, unless cache modifieres are used
diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
index 158b97e..6ff4b6c 100644
--- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
+++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config
@@ -83,7 +83,7 @@
-gpgpu_dual_issue_diff_exec_units 1
## L1/shared memory configuration
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# In adaptive cache, we adaptively assign the remaining shared memory to L1 cache
# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
diff --git a/configs/tested-cfgs/SM75_RTX2060_S/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060_S/gpgpusim.config
index 89435a9..08ac752 100644
--- a/configs/tested-cfgs/SM75_RTX2060_S/gpgpusim.config
+++ b/configs/tested-cfgs/SM75_RTX2060_S/gpgpusim.config
@@ -128,7 +128,7 @@
-gpgpu_num_reg_banks 16
-gpgpu_reg_file_port_throughput 2
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
-gpgpu_adaptive_cache_config 0
-gpgpu_l1_banks 4
diff --git a/configs/tested-cfgs/SM7_GV100/gpgpusim.config b/configs/tested-cfgs/SM7_GV100/gpgpusim.config
index 8d2b101..1595c69 100644
--- a/configs/tested-cfgs/SM7_GV100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_GV100/gpgpusim.config
@@ -137,7 +137,7 @@
-gpgpu_dual_issue_diff_exec_units 1
## L1/shared memory configuration
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# Defualt config is 32KB DL1 and 96KB shared memory
# In Volta, we assign the remaining shared memory to L1 cache
diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
index 1b55aaf..b3384af 100644
--- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
@@ -137,7 +137,7 @@
-gpgpu_dual_issue_diff_exec_units 1
## L1/shared memory configuration
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# Defualt config is 32KB DL1 and 96KB shared memory
# In Volta, we assign the remaining shared memory to L1 cache
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index af561de..c37aaf0 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -107,7 +107,7 @@
-gpgpu_dual_issue_diff_exec_units 1
## L1/shared memory configuration
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# Defualt config is 32KB DL1 and 96KB shared memory
# In Volta, we assign the remaining shared memory to L1 cache
diff --git a/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config b/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config
index aee0130..d26b1a6 100644
--- a/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config
+++ b/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config
@@ -83,7 +83,7 @@
-gpgpu_dual_issue_diff_exec_units 1
## L1/shared memory configuration
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# In adaptive cache, we adaptively assign the remaining shared memory to L1 cache
# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index 4bbf7e2..aa693b5 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -563,10 +563,12 @@ class cache_config {
char ct, rp, wp, ap, mshr_type, wap, sif;
int ntok =
- sscanf(config, "%c:%u:%u:%u,%c:%c:%c:%c:%c,%c:%u:%u,%u:%u,%u", &ct,
- &m_nset, &m_line_sz, &m_assoc, &rp, &wp, &ap, &wap, &sif,
- &mshr_type, &m_mshr_entries, &m_mshr_max_merge,
- &m_miss_queue_size, &m_result_fifo_entries, &m_data_port_width);
+ sscanf(config, "%c:%u:%u:%u,%c:%c:%c:%c:%c,%c:%u:%u,%u:%u,%u",
+ &ct, &m_nset, &m_line_sz, &m_assoc,
+ &rp, &wp, &ap, &wap, &sif,
+ &mshr_type, &m_mshr_entries, &m_mshr_max_merge,
+ &m_miss_queue_size, &m_result_fifo_entries,
+ &m_data_port_width);
if (ntok < 12) {
if (!strcmp(config, "none")) {
@@ -721,9 +723,17 @@ class cache_config {
"Invalid cache configuration: FETCH_ON_WRITE and LAZY_FETCH_ON_READ "
"cannot work properly with ON_FILL policy. Cache must be ON_MISS. ");
}
+
if (m_cache_type == SECTOR) {
- assert(m_line_sz / SECTOR_SIZE == SECTOR_CHUNCK_SIZE &&
- m_line_sz % SECTOR_SIZE == 0);
+ bool cond =
+ m_line_sz / SECTOR_SIZE == SECTOR_CHUNCK_SIZE &&
+ m_line_sz % SECTOR_SIZE == 0;
+ if(!cond){
+ std::cerr<<"error: For sector cache, the simulator uses hard-coded "
+ "SECTOR_SIZE and SECTOR_CHUNCK_SIZE. The line size "
+ "must be product of both values.\n";
+ assert(0);
+ }
}
// default: port to data array width and granularity = line size
generated by cgit v1.3 (git 2.53.0) at 2026-07-10 23:56:50 +0000