diff options
157 files changed, 596 insertions, 41453 deletions
@@ -12,6 +12,7 @@ libcuda/cuobjdump_parser.h libcuda/cuobjdump_parser.output lib/* +doc/doxygen/html cuobjdump_to_ptxplus/elf_lexer.cc cuobjdump_to_ptxplus/elf_parser.cc @@ -31,3 +32,4 @@ cuobjdump_to_ptxplus/sass_parser.hh cuobjdump_to_ptxplus/sass_parser.output build/* +*.swp diff --git a/.travis.yml b/.travis.yml index fabfc5b..7a12a1c 100644 --- a/.travis.yml +++ b/.travis.yml @@ -9,15 +9,35 @@ language: cpp matrix: include: - services: docker - env: CONFIG=configs.gtx480.yml + env: + - CONFIG=configs.gtx480.yml + - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ + - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ # This config is just taking far too long... # - services: docker -# env: CONFIG=configs.gtx750ti.yml +# env: +# - CONFIG=configs.gtx750ti.yml +# - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ +# - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ - services: docker - env: CONFIG=configs.quadro5600.yml + env: + - CONFIG=configs.quadro5600.yml + - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ + - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ - services: docker - env: CONFIG=configs.quadro5800.yml + env: + - CONFIG=configs.quadro5800.yml + - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ + - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ - services: docker - env: CONFIG=configs.teslac2050.yml + env: + - CONFIG=configs.teslac2050.yml + - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ + - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ + - services: docker + env: + - CONFIG=configs.gtx1080ti.yml + - CUDA_INSTALL_PATH=/usr/local/cuda-4.2/ + - PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-9.1/ -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'export CUDA_INSTALL_PATH=$CUDA_INSTALL_PATH && export PTXAS_CUDA_INSTALL_PATH=$PTXAS_CUDA_INSTALL_PATH && source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" @@ -143,7 +143,7 @@ no_opencl_support: @echo "Warning: gpgpu-sim is building without opencl support. Make sure NVOPENCL_LIBDIR and NVOPENCL_INCDIR are set" $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib - g++ -shared -Wl,-soname,libcudart_$(GPGPUSIM_BUILD).so \ + g++ -shared -Wl,-soname,libcudart_$(GPGPUSIM_BUILD).so -Wl,--version-script=linux-so-version.txt\ $(SIM_OBJ_FILES_DIR)/libcuda/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/decuda_pred_table/*.o \ @@ -162,6 +162,7 @@ $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib if [ ! -f $(SIM_LIB_DIR)/libcudart.so.7.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.7.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.8.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.8.0; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.9.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.9.0; fi + if [ ! -f $(SIM_LIB_DIR)/libcudart.so.9.1 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.9.1; fi $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib g++ -dynamiclib -Wl,-headerpad_max_install_names,-undefined,dynamic_lookup,-compatibility_version,1.1,-current_version,1.1\ diff --git a/aerialvision/guiclasses.py b/aerialvision/guiclasses.py index 0a7013b..45fed26 100644 --- a/aerialvision/guiclasses.py +++ b/aerialvision/guiclasses.py @@ -69,7 +69,7 @@ import matplotlib matplotlib.use('TkAgg') from matplotlib.backends.backend_tkagg import FigureCanvasTkAgg, NavigationToolbar2TkAgg from matplotlib.figure import Figure -from matplotlib import mpl +import matplotlib as mpl from matplotlib.colors import colorConverter from matplotlib import pyplot import Pmw diff --git a/bsmad_test/.gdbinit b/bsmad_test/.gdbinit deleted file mode 100644 index b456895..0000000 --- a/bsmad_test/.gdbinit +++ /dev/null @@ -1,97 +0,0 @@ -# Provides some useful debugging macros. To use this file, copy to your home -# directory or to your simulation directory then run GPGPU-Sim in gdb. - -printf "\n ** loading GPGPU-Sim debugging macros... ** \n\n" - -set print pretty -set print array-indexes -set unwindonsignal on - -define dp - call g_the_gpu->dump_pipeline((0x40|0x4|0x1),$arg0,0) -end - -document dp -Usage: dp <index> -Display pipeline state. -<index>: index of shader core you would like to see the pipeline state of - -This function displays the state of the pipeline on a single shader core -(setting different values for the first argument of the call to -dump_pipeline will cause different information to be displayed-- -see the source code for more details) -end - -define dpc - call g_the_gpu->dump_pipeline((0x40|0x4|0x1),$arg0,0) - continue -end - -document dpc -Usage: dpc <index> -Display pipeline state, then continue to next breakpoint. -<index>: index of shader core you would like to see the pipeline state of - -This version is useful if you set a breakpoint where gpu_sim_cycle is -incremented in gpu_sim_loop() in src/gpgpu-sim/gpu-sim.c -repeatly hitting enter will advance to show the pipeline contents on -the next cycle. -end - -define dm - call g_the_gpu->dump_pipeline(0x10000|0x10000000,0,$arg0) -end - -define ptxdis - set $addr=$arg0 - printf "disassemble instructions from 0x%x to 0x%x\n", $arg0, $arg1 - call fflush(stdout) - while ( $addr <= $arg1 ) - printf "0x%04x (%4u) : ", $addr, $addr - call ptx_print_insn( $addr, stdout ) - call fflush(stdout) - set $addr = $addr + ptx_print_insn::size - end -end - -document ptxdis -Usage: ptxdis <start> <end> -Disassemble PTX instructions between <start> and <end> (PCs). -end - -define ptxdis_func - set $sid = $arg0 - set $cluster = g_the_gpu_config.m_shader_config.sid_to_cluster($sid) - set $cid = g_the_gpu_config.m_shader_config.sid_to_cid($sid) - set $ptx_tinfo = g_the_gpu->m_cluster[$cluster]->m_core[$cid]->m_thread[$arg1] - set $finfo = $ptx_tinfo->m_func_info - set $minpc = $finfo->m_start_PC - set $maxpc = $minpc + $finfo->m_instr_mem_size - printf "disassembly of function %s (min pc = %u, max pc = %u):\n", $finfo->m_name.c_str(), $minpc, $maxpc - ptxdis $minpc $maxpc -end - -document ptxdis_func -Usage: ptxdis_func <shd_idx> <tid> (requires debug build) -<shd_idx>: shader core number -<tid>: thread ID -end - -define ptx_tids2pcs - set $i = 0 - while ( $i < $arg1 ) - set $tid = $arg0[$i] - set $cluster = g_the_gpu_config.m_shader_config.sid_to_cluster($sid); - set $cid = g_the_gpu_config.m_shader_config.sid_to_cid($sid); - set $addr = g_the_gpu->m_cluster[$cluster]->m_core[$cid]->m_thread[$tid]->m_PC - printf "%2u : tid = %3u => pc = %d\n", $i, $tid, $addr - set $i = $i + 1 - end -end - -document ptx_tids2pcs -Usage: ptx_tids2pcs <tids> <tidslen> <shd_idx> -<tids>: array of tids -<tidslen>: length of <tids> array -<shd_idx>: shader core number -end diff --git a/bsmad_test/Makefile b/bsmad_test/Makefile deleted file mode 100644 index b841c6b..0000000 --- a/bsmad_test/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -all: bsmad_test.cu - nvcc --gpu-architecture=compute_50 --gpu-code=compute_50 -lcudart -g -o bsmad bsmad_test.cu - -.PHONY: -clean: - rm bsmad diff --git a/bsmad_test/bsmad b/bsmad_test/bsmad Binary files differdeleted file mode 100755 index 56020ff..0000000 --- a/bsmad_test/bsmad +++ /dev/null diff --git a/bsmad_test/bsmad_result.txt b/bsmad_test/bsmad_result.txt deleted file mode 100644 index 968a990..0000000 --- a/bsmad_test/bsmad_result.txt +++ /dev/null @@ -1,333 +0,0 @@ -GNU gdb (GDB) SUSE (7.5.1-2.5.1) -Copyright (C) 2012 Free Software Foundation, Inc. -License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> -This is free software: you are free to change and redistribute it. -There is NO WARRANTY, to the extent permitted by law. Type "show copying" -and "show warranty" for details. -This GDB was configured as "x86_64-suse-linux". -For bug reporting instructions, please see: -<http://www.gnu.org/software/gdb/bugs/>... -Reading symbols from /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad...done. -To enable execution of this file add - add-auto-load-safe-path /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/.gdbinit -line to your configuration file "/home/negargoli93/.gdbinit". -To completely disable this security protection add - set auto-load safe-path / -line to your configuration file "/home/negargoli93/.gdbinit". -For more information about this security protection see the -"Auto-loading safe path" section in the GDB manual. E.g., run from the shell: - info "(gdb)Auto-loading safe path" -(gdb) r^C(gdb) r -Starting program: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad -[Thread debugging using libthread_db enabled] -Using host libthread_db library "/lib64/libthread_db.so.1". - - - *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-0751c1489add70d7494521c7f9d65f462e4391c6_modified_0] *** - - -GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: - 1=functional simulation only, 0=detailed performance simulator) -GPGPU-Sim: Configuration options: - --network_mode 1 # Interconnection network mode --inter_config_file config_fermi_islip.icnt # Interconnection network config file --gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries --gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] --gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus --gpgpu_ptx_force_max_capability 60 # Force maximum compute capability --gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file --gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file --gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output --gpgpu_simd_model 1 # 1 = post-dominator --gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>} --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>} --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) --gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) --n_regfile_gating_group 4 # group of lanes that should be read/written together) --gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations --gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations --gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) --gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) --gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) --gpgpu_n_clusters 28 # number of processing clusters --gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster --gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer --gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer --gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) --gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) --gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check --gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from --gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from --gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) --gpgpu_num_reg_banks 32 # Number of register banks (default = 8) --gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) --gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) --gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) --gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) --gpgpu_num_sched_per_core 2 # Number of warp schedulers per core --gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler --gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) --gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_num_sp_units 4 # Number of SP units (default=1) --gpgpu_num_sfu_units 1 # Number of SF units (default=1) --gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything --gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto --gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) --gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) --gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i --l2_ideal 0 # Use a ideal L2 cache that always hit --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only --gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu --gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module --gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller --gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs --gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip --gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip --gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) --gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) --dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) --gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} --rop_latency 120 # ROP queue latency (default 85) --dram_latency 100 # DRAM latency (default 30) --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>} --gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address --gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits --gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file --power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) --power_per_cycle_dump 0 # Dump detailed power output each cycle --power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) --power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) --steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) --steady_state_definition 8:4 # allowed deviation:number of samples --gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) --gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>} --liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) --gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call --gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call --gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) --gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) --gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) --gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>} --gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU --gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger --visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) --visualizer_outputfile NULL # Specifies the output log file for visualizer --visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) --trace_enabled 0 # Turn on traces --trace_components none # comma seperated list of traces to enable. Complete list found in trace[New Thread 0x7ffff4512700 (LWP 5117)] -[Thread 0x7ffff4512700 (LWP 5117) exited] -[New Thread 0x7ffff4512700 (LWP 5120)] - -Program received signal SIGINT, Interrupt. -0x00007ffff6f78fef in pthread_join () from /lib64/libpthread.so.0 -Missing separate debuginfos, use: zypper install Mesa-libGL1-debuginfo-8.0.4-20.27.1.x86_64 Mesa-libglapi0-debuginfo-8.0.4-20.27.1.x86_64 glibc-debuginfo-2.15-22.17.1.x86_64 libX11-6-debuginfo-1.5.0-2.7.1.x86_64 libX11-xcb1-debuginfo-1.5.0-2.7.1.x86_64 libXau6-debuginfo-1.0.7-2.1.2.x86_64 libXdamage1-debuginfo-1.1.3-2.1.2.x86_64 libXext6-debuginfo-1.3.1-2.4.1.x86_64 libXfixes3-debuginfo-5.0-2.4.1.x86_64 libXxf86vm1-debuginfo-1.1.2-2.7.1.x86_64 libdrm2-debuginfo-2.4.33-2.3.2.x86_64 libgcc47-debuginfo-4.7.1_20120723-1.1.1.x86_64 libstdc++47-debuginfo-4.7.1_20120723-1.1.1.x86_64 libxcb-glx0-debuginfo-1.8.1-2.8.1.x86_64 libxcb1-debuginfo-1.8.1-2.8.1.x86_64 zlib-debuginfo-1.2.7-2.1.2.x86_64 -(gdb) -(gdb) quit -A debugging session is active. - - Inferior 1 [process 5113] will be killed. - -Quit anyway? (y or n) Please answer y or n. -A debugging session is active. - - Inferior 1 [process 5113] will be killed. - -Quit anyway? (y or n) Please answer y or n. -A debugging session is active. - - Inferior 1 [process 5113] will be killed. - -Quit anyway? (y or n) Please answer y or n. -A debugging session is active. - - Inferior 1 [process 5113] will be killed. - -Quit anyway? (y or n) Please answer y or n. -A debugging session is active. - - Inferior 1 [process 5113] will be killed. - -Quit anyway? (y or n) Please answer y or n. -A debugging session is active. - - Inferior 1 [process 5113] will be killed. - -Quit anyway? (y or n) Please answer y or n. -A debugging session is active. - - Inferior 1 [process 5113] will be killed. - -Quit anyway? (y or n) Please answer y or n. -A debugging session is active. - - Inferior 1 [process 5113] will be killed. - -Quit anyway? (y or n) Please answer y or n. -A debugging session is active. - - Inferior 1 [process 5113] will be killed. - -Quit anyway? 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(y or n) EOF [assumed Y] diff --git a/bsmad_test/bsmad_test.cu b/bsmad_test/bsmad_test.cu deleted file mode 100644 index 9be6e74..0000000 --- a/bsmad_test/bsmad_test.cu +++ /dev/null @@ -1,76 +0,0 @@ -#include <stdio.h> -#define SIZE 1024 -#define THREADS_PER_BLOCK 32 -#define PART_THREADS 1 -#define NUM_BLOCKS 1 -#define I_PREC 4 -#define O_PREC 4 - -__global__ void vector_add(int* A, int* B, int* res) -{ - int tid = threadIdx.x + blockIdx.x * blockDim.x; - res[tid] = A[tid] + B[tid]; -} - -__global__ void digit_serial_mad(unsigned* i_buffer, unsigned* i_synapse, unsigned* result, unsigned* accum) -{ - unsigned tid = threadIdx.x + blockIdx.x * blockDim.x; - unsigned buffer; - unsigned synapse; - if (tid < PART_THREADS) - { - buffer = i_buffer[tid]; - synapse = i_synapse[tid]; - } - - asm("/*"); - asm("CPTX_BEGIN"); - asm("bsmad.s32 %0, %1, %2, %3, %4, %5, %6, %7, %8;" : "=r"(result[tid]) : - "r"(I_PREC), "r"(O_PREC), "r"(buffer), "r"(0), "r"(0), "r"(0), "r"(synapse), "r"(accum[tid])); - asm("CPTX_END"); - asm("*/"); -} - -int main() -{ - // host values - unsigned *buffer = (unsigned*)malloc(sizeof(unsigned)); - unsigned *synapse = (unsigned*)malloc(sizeof(unsigned)); - unsigned *result = (unsigned*)calloc(THREADS_PER_BLOCK, sizeof(unsigned)); - unsigned *accum = (unsigned*)calloc(THREADS_PER_BLOCK, sizeof(unsigned)); - // assign host values - *buffer = 0x5000003F; - *synapse = 0x00000002; - *accum = 0; - // device pointers - unsigned *d_buffer; - unsigned *d_synapse; - unsigned *d_result; - unsigned *d_accum; - // allocate device memory - cudaMalloc(&d_buffer, sizeof(unsigned)); - cudaMalloc(&d_synapse, sizeof(unsigned)); - cudaMalloc(&d_result, sizeof(unsigned)); - cudaMalloc(&d_accum, sizeof(unsigned)); - // copy data to device - cudaMemcpy(d_buffer, buffer, sizeof(unsigned), cudaMemcpyHostToDevice); - cudaMemcpy(d_synapse, synapse, sizeof(unsigned), cudaMemcpyHostToDevice); - cudaMemcpy(d_result, result, sizeof(unsigned) * THREADS_PER_BLOCK, cudaMemcpyHostToDevice); - cudaMemcpy(d_accum, accum, sizeof(unsigned) * THREADS_PER_BLOCK, cudaMemcpyHostToDevice); - // call kernel - digit_serial_mad<<<NUM_BLOCKS, THREADS_PER_BLOCK>>>(d_buffer, d_synapse, d_result, d_accum); - // copy data back to host - cudaMemcpy(result, d_result, sizeof(unsigned) * THREADS_PER_BLOCK, cudaMemcpyDeviceToHost); - // read out result - printf("Result: %#X\n", result[0]); - // clean up device memory - cudaFree(d_buffer); - cudaFree(d_synapse); - cudaFree(d_result); - cudaFree(d_accum); - // clean up host memory - free(buffer); - free(synapse); - free(result); - free(accum); -} diff --git a/bsmad_test/bsmadoutput.txt b/bsmad_test/bsmadoutput.txt deleted file mode 100644 index 7c5f9d5..0000000 --- a/bsmad_test/bsmadoutput.txt +++ /dev/null @@ -1,3004 +0,0 @@ - - - *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** - - -GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: - 1=functional simulation only, 0=detailed performance simulator) -GPGPU-Sim: Configuration options: - --network_mode 1 # Interconnection network mode --inter_config_file config_fermi_islip.icnt # Interconnection network config file --gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries --gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] --gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus --gpgpu_ptx_force_max_capability 60 # Force maximum compute capability --gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file --gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file --gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output --gpgpu_simd_model 1 # 1 = post-dominator --gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>} --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>} --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) --gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) --n_regfile_gating_group 4 # group of lanes that should be read/written together) --gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations --gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations --gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) --gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) --gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) --gpgpu_n_clusters 28 # number of processing clusters --gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster --gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer --gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer --gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) --gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) --gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check --gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from --gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from --gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) --gpgpu_num_reg_banks 32 # Number of register banks (default = 8) --gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) --gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) --gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) --gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) --gpgpu_num_sched_per_core 2 # Number of warp schedulers per core --gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler --gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) --gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_num_sp_units 4 # Number of SP units (default=1) --gpgpu_num_sfu_units 1 # Number of SF units (default=1) --gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything --gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto --gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) --gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) --gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i --l2_ideal 0 # Use a ideal L2 cache that always hit --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only --gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu --gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module --gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller --gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs --gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip --gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip --gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) --gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) --dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) --gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} --rop_latency 120 # ROP queue latency (default 85) --dram_latency 100 # DRAM latency (default 30) --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>} --gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address --gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits --gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file --power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) --power_per_cycle_dump 0 # Dump detailed power output each cycle --power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) --power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) --steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) --steady_state_definition 8:4 # allowed deviation:number of samples --gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) --gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>} --liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) --gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call --gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call --gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) --gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) --gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) --gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>} --gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU --gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger --visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) --visualizer_outputfile NULL # Specifies the output log file for visualizer --visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) --trace_enabled 0 # Turn on traces --trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none --trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 --trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) --enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) --ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. --gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 --gpgpu_cdp_enabled 0 # Turn on CDP --save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx --keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs --gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file --ptx_opcode_latency_int 4,13,4,5,145,4 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,19,25,145,1 --ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30 --ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335 --ptx_opcode_initiation_int 1,2,2,2,8,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,4,4,32,1 --ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5 --ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130 --cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600 -DRAM Timing Options: -nbk 16 # number of banks -CCD 2 # column to column delay -RRD 6 # minimal delay between activation of rows in different banks -RCD 12 # row to column delay -RAS 28 # time needed to activate row -RP 12 # time needed to precharge (deactivate) row -RC 40 # row cycle time -CDLR 5 # switching from write to read (changes tWTR) -WR 12 # last data-in to row precharge -CL 12 # CAS latency -WL 4 # Write latency -nbkgrp 1 # number of bank groups -CCDL 0 # column to column delay between accesses to different bank groups -RTPL 0 # read to precharge delay between accesses to different bank groups -Total number of memory sub partition = 22 -addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 -addr_dec_mask[BK] = 0000000000007080 high:15 low:7 -addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 -addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 -addr_dec_mask[BURST] = 000000000000001f high:5 low:0 -sub_partition_id_mask = 0000000000000080 -GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 -GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 -*** Initializing Memory Statistics *** -GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) -GPGPU-Sim uArch: Memory nodes ID start from index: 28 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 -GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) -GPGPU-Sim uArch: Memory nodes start from ID: 28 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 -057a78a8e028f9794c162a7c4e45415d /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad -GPGPU-Sim uArch: performance model initialization complete. -GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default -self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad -Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " -Parsing file _cuobjdump_complete_output_A4Dkbu -######### cuobjdump parser ######## -## Adding new section PTX -Adding ptx filename: _cuobjdump_1.ptx -Adding arch: sm_50 -Adding identifier: default -Done parsing!!! -GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 -WARNING: No guarantee that PTX will be parsed for SM version 50 -GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. -GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... -GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ -GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. -BEGINNING CUSTOM PTX. -ENDING CUSTOM PTX. -GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. -GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... -GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; -GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; -GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ -GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. -GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx -Adding _cuobjdump_1.ptx with cubin handle 1 -GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_3lcy4c" -Running: cat _ptx_3lcy4c | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_6DnMXV -GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_6DnMXV --output-file /dev/null 2> _ptx_3lcy4cinfo" -GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 -GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 -GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_3lcy4c _ptx2_6DnMXV _ptx_3lcy4cinfo" -GPGPU-Sim PTX: loading globals with explicit initializers... -GPGPU-Sim PTX: finished loading globals (0 bytes total). -GPGPU-Sim PTX: loading constants with explicit initializers... done. -GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 -GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes -GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes -GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes -GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes -GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Network latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Flit latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Fragmentation average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Injected packet rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Accepted packet rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Injected flit rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Accepted flit rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Injected packet size average = -nan (1 samples) -Accepted packet size average = -nan (1 samples) -Hops average = -nan (1 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Network latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Flit latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Fragmentation average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Injected packet rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Accepted packet rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Injected flit rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Accepted flit rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Injected packet size average = -nan (2 samples) -Accepted packet size average = -nan (2 samples) -Hops average = -nan (2 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Network latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Flit latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Fragmentation average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Injected packet rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Accepted packet rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Injected flit rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Accepted flit rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Injected packet size average = -nan (3 samples) -Accepted packet size average = -nan (3 samples) -Hops average = -nan (3 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 -GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 - 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) -bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Network latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Flit latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Fragmentation average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Injected packet rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Accepted packet rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Injected flit rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Accepted flit rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Injected packet size average = -nan (4 samples) -Accepted packet size average = -nan (4 samples) -Hops average = -nan (4 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' -GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit -GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) -GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 17:28:53 2017 -GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA -GPGPU-Sim uArch: Shader 1 finished CTA #0 (1081,0), 0 CTAs running -GPGPU-Sim uArch: Shader 1 empty (last released kernel 1 '_Z16digit_serial_madPjS_S_S_'). -GPGPU-Sim uArch: GPU detected kernel 1 '_Z16digit_serial_madPjS_S_S_' finished on shader 1. -Destroy streams for kernel 1: size 0 -kernel_name = _Z16digit_serial_madPjS_S_S_ -kernel_launch_uid = 1 -gpu_sim_cycle = 1082 -gpu_sim_insn = 675 -gpu_ipc = 0.6238 -gpu_tot_sim_cycle = 1082 -gpu_tot_sim_insn = 675 -gpu_tot_ipc = 0.6238 -gpu_tot_issued_cta = 1 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=675 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 13 - L1I_total_cache_misses = 2 - L1I_total_cache_miss_rate = 0.1538 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 4 - L1C_total_cache_misses = 4 - L1C_total_cache_miss_rate = 1.0000 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: - Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 - Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 - Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 800 -gpgpu_n_tot_w_icount = 25 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 3 -gpgpu_n_mem_write_global = 1 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 1 -gpgpu_n_load_insn = 34 -gpgpu_n_store_insn = 32 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 128 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:1902 W0_Scoreboard:294 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 -traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} -traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} -traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} -traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} -traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} -traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} -traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} -traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} -maxmrqlatency = 7 -maxdqlatency = 0 -maxmflatency = 252 -averagemflatency = 250 -max_icnt2mem_latency = 6 -max_icnt2sh_latency = 1081 -mrq_lat_table:7 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 4 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 750 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 759 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 1066 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 1038 0 0 0 0 228 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 2.000000 -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan 1.000000 -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 8/6 = 1.333333 -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 7 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 1 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: 252 none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none 250 none none none none none -dram[2]: none none none none none none none none none none 250 none none none none none -dram[3]: none none none none none none none none none none 122 none none none none none -dram[4]: none none none none none none none none none none 252 none none none none 0 -dram[5]: none none none none none none none none none none none none none none 0 none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 244 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 252 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 -n_activity=40 dram_eff=0.2 -bk0: 4a 1989i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 -n_activity=40 dram_eff=0.2 -bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 4a 1989i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 0a 2007i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 -n_activity=40 dram_eff=0.2 -bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 4a 1989i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 0a 2007i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 3: -Cache L2_bank_006: -MSHR contents -MSHR: tag=0x3e20200, atomic=0 1 entries : 0x7f51d804c750 : mf: uid= 22, sid01:w00, part=3, addr=0x3e20200, load , size=128, unknown status = IN_PARTITION_DRAM (1081), - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2008 n_nop=2000 n_act=1 n_pre=0 n_req=2 n_rd=3 n_write=4 bw_util=0.006972 -n_activity=29 dram_eff=0.4828 -bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 3a 1979i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 0a 2007i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=1 avg=0.0059761 -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2008 n_nop=1998 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007968 -n_activity=80 dram_eff=0.2 -bk0: 0a 2006i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 4a 1989i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 4a 1988i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 -n_activity=40 dram_eff=0.2 -bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2009i bk14: 4a 1989i bk15: 0a 2007i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 -n_activity=0 dram_eff=-nan -bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 -n_activity=0 dram_eff=-nan -bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 -n_activity=0 dram_eff=-nan -bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 -n_activity=0 dram_eff=-nan -bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 -n_activity=0 dram_eff=-nan -bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 7 -L2_total_cache_misses = 7 -L2_total_cache_miss_rate = 1.0000 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: - L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 3 - L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 - L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 1 - L2_cache_stats_breakdown[INST_ACC_R][MISS] = 2 -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.001 - -icnt_total_pkts_mem_to_simt=23 -icnt_total_pkts_simt_to_mem=11 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = 7.42857 - minimum = 6 - maximum = 10 -Network latency average = 7.42857 - minimum = 6 - maximum = 10 -Slowest packet = 1 -Flit latency average = 6 - minimum = 6 - maximum = 6 -Slowest flit = 0 -Fragmentation average = 0 - minimum = 0 - maximum = 0 -Injected packet rate average = 0.00012951 - minimum = 0 (at node 0) - maximum = 0.00323774 (at node 1) -Accepted packet rate average = 0.00012951 - minimum = 0 (at node 0) - maximum = 0.00323774 (at node 1) -Injected flit rate average = 0.000314524 - minimum = 0 (at node 0) - maximum = 0.00508788 (at node 1) -Accepted flit rate average= 0.000314524 - minimum = 0 (at node 0) - maximum = 0.0106383 (at node 1) -Injected packet length average = 2.42857 -Accepted packet length average = 2.42857 -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (5 samples) - minimum = nan (5 samples) - maximum = -nan (5 samples) -Network latency average = -nan (5 samples) - minimum = nan (5 samples) - maximum = -nan (5 samples) -Flit latency average = -nan (5 samples) - minimum = nan (5 samples) - maximum = -nan (5 samples) -Fragmentation average = -nan (5 samples) - minimum = nan (5 samples) - maximum = -nan (5 samples) -Injected packet rate average = -nan (5 samples) - minimum = -nan (5 samples) - maximum = -nan (5 samples) -Accepted packet rate average = -nan (5 samples) - minimum = -nan (5 samples) - maximum = -nan (5 samples) -Injected flit rate average = -nan (5 samples) - minimum = -nan (5 samples) - maximum = -nan (5 samples) -Accepted flit rate average = -nan (5 samples) - minimum = -nan (5 samples) - maximum = -nan (5 samples) -Injected packet size average = -nan (5 samples) -Accepted packet size average = -nan (5 samples) -Hops average = -nan (5 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- - - -gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 1 sec (1 sec) -gpgpu_simulation_rate = 675 (inst/sec) -gpgpu_simulation_rate = 1082 (cycle/sec) -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 1082 -gpu_tot_sim_insn = 675 -gpu_tot_ipc = 0.6238 -gpu_tot_issued_cta = 1 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=675 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 13 - L1I_total_cache_misses = 2 - L1I_total_cache_miss_rate = 0.1538 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 4 - L1C_total_cache_misses = 4 - L1C_total_cache_miss_rate = 1.0000 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: - Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 - Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 - Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 800 -gpgpu_n_tot_w_icount = 25 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 3 -gpgpu_n_mem_write_global = 1 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 1 -gpgpu_n_load_insn = 34 -gpgpu_n_store_insn = 32 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 128 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:1902 W0_Scoreboard:294 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 -traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} -traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} -traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} -traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} -traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} -traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} -traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} -traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} -Result: 0XA000006F diff --git a/bsmad_test/d.log b/bsmad_test/d.log deleted file mode 100644 index 50ba43f..0000000 --- a/bsmad_test/d.log +++ /dev/null @@ -1,3049 +0,0 @@ - - - *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** - - -GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: - 1=functional simulation only, 0=detailed performance simulator) -GPGPU-Sim: Configuration options: - --network_mode 1 # Interconnection network mode --inter_config_file config_fermi_islip.icnt # Interconnection network config file --gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries --gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] --gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus --gpgpu_ptx_force_max_capability 60 # Force maximum compute capability --gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file --gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file --gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output --gpgpu_simd_model 1 # 1 = post-dominator --gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>} --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>} --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) --gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) --n_regfile_gating_group 4 # group of lanes that should be read/written together) --gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations --gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations --gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) --gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) --gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) --gpgpu_n_clusters 28 # number of processing clusters --gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster --gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer --gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer --gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) --gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) --gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check --gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from --gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from --gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) --gpgpu_num_reg_banks 32 # Number of register banks (default = 8) --gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) --gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) --gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) --gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) --gpgpu_num_sched_per_core 2 # Number of warp schedulers per core --gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler --gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) --gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_num_sp_units 4 # Number of SP units (default=1) --gpgpu_num_sfu_units 1 # Number of SF units (default=1) --gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything --gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto --gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) --gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) --gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i --l2_ideal 0 # Use a ideal L2 cache that always hit --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only --gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu --gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module --gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller --gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs --gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip --gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip --gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) --gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) --dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) --gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} --rop_latency 120 # ROP queue latency (default 85) --dram_latency 100 # DRAM latency (default 30) --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>} --gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address --gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits --gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file --power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) --power_per_cycle_dump 0 # Dump detailed power output each cycle --power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) --power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) --steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) --steady_state_definition 8:4 # allowed deviation:number of samples --gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) --gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>} --liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) --gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call --gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call --gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) --gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) --gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) --gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>} --gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU --gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger --visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) --visualizer_outputfile NULL # Specifies the output log file for visualizer --visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) --trace_enabled 0 # Turn on traces --trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none --trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 --trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) --enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) --ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. --gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 --gpgpu_cdp_enabled 0 # Turn on CDP --save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx --keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs --gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file --ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Presicion,BSMAD_lane_width>Default 1,1,19,25,145,1,4 --ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30 --ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335 --ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Precision,BSMAD_lane_width>Default 1,1,4,4,32,1,1 --ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5 --ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130 --cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600 -DRAM Timing Options: -nbk 16 # number of banks -CCD 2 # column to column delay -RRD 6 # minimal delay between activation of rows in different banks -RCD 12 # row to column delay -RAS 28 # time needed to activate row -RP 12 # time needed to precharge (deactivate) row -RC 40 # row cycle time -CDLR 5 # switching from write to read (changes tWTR) -WR 12 # last data-in to row precharge -CL 12 # CAS latency -WL 4 # Write latency -nbkgrp 1 # number of bank groups -CCDL 0 # column to column delay between accesses to different bank groups -RTPL 0 # read to precharge delay between accesses to different bank groups -Total number of memory sub partition = 22 -addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 -addr_dec_mask[BK] = 0000000000007080 high:15 low:7 -addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 -addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 -addr_dec_mask[BURST] = 000000000000001f high:5 low:0 -sub_partition_id_mask = 0000000000000080 -GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 -GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 -*** Initializing Memory Statistics *** -GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) -GPGPU-Sim uArch: Memory nodes ID start from index: 28 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 -GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) -GPGPU-Sim uArch: Memory nodes start from ID: 28 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 -e1ffbb239b1e632822e743b7e0c60b46 /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad -GPGPU-Sim uArch: performance model initialization complete. -GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default -self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad -Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " -Parsing file _cuobjdump_complete_output_8Ypfya -######### cuobjdump parser ######## -## Adding new section PTX -Adding ptx filename: _cuobjdump_1.ptx -Adding arch: sm_50 -Adding identifier: default -Done parsing!!! -GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 -WARNING: No guarantee that PTX will be parsed for SM version 50 -GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. -GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... -GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ -GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. -BEGINNING CUSTOM PTX. -ENDING CUSTOM PTX. -GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. -GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... -GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; -GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; -GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ -GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. -GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx -Adding _cuobjdump_1.ptx with cubin handle 1 -GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_CMkVsP" -Running: cat _ptx_CMkVsP | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_bVrCnu -GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_bVrCnu --output-file /dev/null 2> _ptx_CMkVsPinfo" -GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 -GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 -GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_CMkVsP _ptx2_bVrCnu _ptx_CMkVsPinfo" -GPGPU-Sim PTX: loading globals with explicit initializers... -GPGPU-Sim PTX: finished loading globals (0 bytes total). -GPGPU-Sim PTX: loading constants with explicit initializers... done. -GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 -GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes -GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes -GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes -GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes -GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -Number of Memory Banks Accessed per Memory Operation per Warp (from 0): -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Average # of Memory Banks Accessed per Memory Operation per Warp=-nan - -position of mrq chosen -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -average position of mrq chosen = -nan -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Network latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Flit latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Fragmentation average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Injected packet rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Accepted packet rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Injected flit rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Accepted flit rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Injected packet size average = -nan (1 samples) -Accepted packet size average = -nan (1 samples) -Hops average = -nan (1 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -Number of Memory Banks Accessed per Memory Operation per Warp (from 0): -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Average # of Memory Banks Accessed per Memory Operation per Warp=-nan - -position of mrq chosen -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -average position of mrq chosen = -nan -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Network latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Flit latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Fragmentation average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Injected packet rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Accepted packet rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Injected flit rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Accepted flit rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Injected packet size average = -nan (2 samples) -Accepted packet size average = -nan (2 samples) -Hops average = -nan (2 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -Number of Memory Banks Accessed per Memory Operation per Warp (from 0): -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Average # of Memory Banks Accessed per Memory Operation per Warp=-nan - -position of mrq chosen -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -average position of mrq chosen = -nan -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Network latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Flit latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Fragmentation average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Injected packet rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Accepted packet rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Injected flit rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Accepted flit rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Injected packet size average = -nan (3 samples) -Accepted packet size average = -nan (3 samples) -Hops average = -nan (3 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 - -GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) - -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -Number of Memory Banks Accessed per Memory Operation per Warp (from 0): -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Average # of Memory Banks Accessed per Memory Operation per Warp=-nan - -position of mrq chosen -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -average position of mrq chosen = -nan -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Network latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Flit latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Fragmentation average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Injected packet rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Accepted packet rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Injected flit rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Accepted flit rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Injected packet size average = -nan (4 samples) -Accepted packet size average = -nan (4 samples) -Hops average = -nan (4 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' -GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit -GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) -GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 18:22:19 2017 -GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA -GPGPU-Sim uArch: Shader 1 finished CTA #0 (1079,0), 0 CTAs running -GPGPU-Sim uArch: Shader 1 empty (last released kernel 1 '_Z16digit_serial_madPjS_S_S_'). -GPGPU-Sim uArch: GPU detected kernel 1 '_Z16digit_serial_madPjS_S_S_' finished on shader 1. -Destroy streams for kernel 1: size 0 -kernel_name = _Z16digit_serial_madPjS_S_S_ -kernel_launch_uid = 1 -gpu_sim_cycle = 1080 -gpu_sim_insn = 675 -gpu_ipc = 0.6250 -gpu_tot_sim_cycle = 1080 -gpu_tot_sim_insn = 675 -gpu_tot_ipc = 0.6250 -gpu_tot_issued_cta = 1 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=675 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 13 - L1I_total_cache_misses = 2 - L1I_total_cache_miss_rate = 0.1538 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 4 - L1C_total_cache_misses = 4 - L1C_total_cache_miss_rate = 1.0000 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: - Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 - Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 - Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 800 -gpgpu_n_tot_w_icount = 25 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 3 -gpgpu_n_mem_write_global = 1 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 1 -gpgpu_n_load_insn = 34 -gpgpu_n_store_insn = 32 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 128 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:1900 W0_Scoreboard:292 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 -traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} -traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} -traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} -traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} -traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} -traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} -traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} -traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} -maxmrqlatency = 7 -maxdqlatency = 0 -maxmflatency = 252 -averagemflatency = 250 -max_icnt2mem_latency = 6 -max_icnt2sh_latency = 1079 -mrq_lat_table:7 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 4 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 750 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 759 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 1064 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 1038 0 0 0 0 228 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 2.000000 -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan 1.000000 -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 8/6 = 1.333333 -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 7 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 1 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: 252 none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none 250 none none none none none -dram[2]: none none none none none none none none none none 250 none none none none none -dram[3]: none none none none none none none none none none 122 none none none none none -dram[4]: none none none none none none none none none none 252 none none none none 0 -dram[5]: none none none none none none none none none none none none none none 0 none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 244 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 252 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -Number of Memory Banks Accessed per Memory Operation per Warp (from 0): -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Average # of Memory Banks Accessed per Memory Operation per Warp=-nan - -position of mrq chosen -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -average position of mrq chosen = -nan -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 -n_activity=40 dram_eff=0.2 -bk0: 4a 1985i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 -n_activity=40 dram_eff=0.2 -bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 -n_activity=40 dram_eff=0.2 -bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 3: -Cache L2_bank_006: -MSHR contents -MSHR: tag=0x3e20200, atomic=0 1 entries : 0x7f6d3018f8f0 : mf: uid= 22, sid01:w00, part=3, addr=0x3e20200, load , size=128, unknown status = IN_PARTITION_DRAM (1079), - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=1996 n_act=1 n_pre=0 n_req=2 n_rd=3 n_write=4 bw_util=0.006986 -n_activity=29 dram_eff=0.4828 -bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 3a 1975i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=1 avg=0.00598802 -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=1994 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007984 -n_activity=80 dram_eff=0.2 -bk0: 0a 2002i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 4a 1984i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 -n_activity=40 dram_eff=0.2 -bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2005i bk14: 4a 1985i bk15: 0a 2003i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 -n_activity=0 dram_eff=-nan -bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 -n_activity=0 dram_eff=-nan -bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 -n_activity=0 dram_eff=-nan -bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 -n_activity=0 dram_eff=-nan -bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 -n_activity=0 dram_eff=-nan -bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 7 -L2_total_cache_misses = 7 -L2_total_cache_miss_rate = 1.0000 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: - L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 3 - L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 - L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 1 - L2_cache_stats_breakdown[INST_ACC_R][MISS] = 2 -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.001 - -icnt_total_pkts_mem_to_simt=23 -icnt_total_pkts_simt_to_mem=11 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = 7.42857 - minimum = 6 - maximum = 10 -Network latency average = 7.42857 - minimum = 6 - maximum = 10 -Slowest packet = 1 -Flit latency average = 6 - minimum = 6 - maximum = 6 -Slowest flit = 0 -Fragmentation average = 0 - minimum = 0 - maximum = 0 -Injected packet rate average = 0.00012975 - minimum = 0 (at node 0) - maximum = 0.00324374 (at node 1) -Accepted packet rate average = 0.00012975 - minimum = 0 (at node 0) - maximum = 0.00324374 (at node 1) -Injected flit rate average = 0.000315107 - minimum = 0 (at node 0) - maximum = 0.00509731 (at node 1) -Accepted flit rate average= 0.000315107 - minimum = 0 (at node 0) - maximum = 0.010658 (at node 1) -Injected packet length average = 2.42857 -Accepted packet length average = 2.42857 -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (5 samples) - minimum = nan (5 samples) - maximum = -nan (5 samples) -Network latency average = -nan (5 samples) - minimum = nan (5 samples) - maximum = -nan (5 samples) -Flit latency average = -nan (5 samples) - minimum = nan (5 samples) - maximum = -nan (5 samples) -Fragmentation average = -nan (5 samples) - minimum = nan (5 samples) - maximum = -nan (5 samples) -Injected packet rate average = -nan (5 samples) - minimum = -nan (5 samples) - maximum = -nan (5 samples) -Accepted packet rate average = -nan (5 samples) - minimum = -nan (5 samples) - maximum = -nan (5 samples) -Injected flit rate average = -nan (5 samples) - minimum = -nan (5 samples) - maximum = -nan (5 samples) -Accepted flit rate average = -nan (5 samples) - minimum = -nan (5 samples) - maximum = -nan (5 samples) -Injected packet size average = -nan (5 samples) -Accepted packet size average = -nan (5 samples) -Hops average = -nan (5 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- - - -gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 1 sec (1 sec) -gpgpu_simulation_rate = 675 (inst/sec) -gpgpu_simulation_rate = 1080 (cycle/sec) -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 1080 -gpu_tot_sim_insn = 675 -gpu_tot_ipc = 0.6250 -gpu_tot_issued_cta = 1 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=675 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 13 - L1I_total_cache_misses = 2 - L1I_total_cache_miss_rate = 0.1538 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -Result: 0XA000006F - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 4 - L1C_total_cache_misses = 4 - L1C_total_cache_miss_rate = 1.0000 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: - Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 - Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 - Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 800 -gpgpu_n_tot_w_icount = 25 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 3 -gpgpu_n_mem_write_global = 1 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 1 -gpgpu_n_load_insn = 34 -gpgpu_n_store_insn = 32 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 128 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:1900 W0_Scoreboard:292 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 -traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} -traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} -traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} -traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} -traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} -traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} -traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} -traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} diff --git a/bsmad_test/gpgpu_inst_stats.txt b/bsmad_test/gpgpu_inst_stats.txt deleted file mode 100644 index 96fa69d..0000000 --- a/bsmad_test/gpgpu_inst_stats.txt +++ /dev/null @@ -1,26 +0,0 @@ -kernel line : count latency dram_traffic smem_bk_conflicts smem_warp gmem_access_generated gmem_warp exposed_latency warp_divergence -_1.ptx 92 : 32 160 128 0 0 1 1 0 0 -_1.ptx 90 : 32 448 0 0 0 0 0 0 0 -_1.ptx 67 : 32 186 0 0 0 0 0 0 1 -_1.ptx 66 : 32 224 0 0 0 0 0 0 0 -_1.ptx 65 : 32 416 0 0 0 0 0 0 0 -_1.ptx 88 : 32 192 0 0 0 0 0 0 0 -_1.ptx 64 : 32 192 0 0 0 0 0 0 0 -_1.ptx 87 : 32 192 0 0 0 0 0 0 0 -_1.ptx 63 : 32 192 0 0 0 0 0 0 0 -_1.ptx 86 : 32 8256 128 0 0 1 1 0 0 -_1.ptx 99 : 32 192 0 0 0 0 0 0 0 -_1.ptx 62 : 32 192 0 0 0 0 0 0 0 -_1.ptx 85 : 32 352 0 0 0 0 0 0 0 -_1.ptx 61 : 32 8192 0 0 0 0 0 0 0 -_1.ptx 84 : 32 352 0 0 0 0 0 0 0 -_1.ptx 60 : 32 8192 0 0 0 0 0 0 0 -_1.ptx 83 : 32 320 0 0 0 0 0 0 0 -_1.ptx 59 : 32 8224 0 0 0 0 0 0 0 -_1.ptx 58 : 32 8224 128 0 0 0 0 0 0 -_1.ptx 69 : 1 7 0 0 0 0 0 0 0 -_1.ptx 70 : 1 256 128 0 0 1 1 0 0 -_1.ptx 71 : 1 7 0 0 0 0 0 0 0 -_1.ptx 72 : 1 256 128 0 0 1 1 0 0 -_1.ptx 75 : 32 224 0 0 0 0 0 0 0 -_1.ptx 76 : 32 224 0 0 0 0 0 0 0 diff --git a/bsmad_test/gpuwattch_gtx1080Ti.xml b/bsmad_test/gpuwattch_gtx1080Ti.xml deleted file mode 100755 index 02619ff..0000000 --- a/bsmad_test/gpuwattch_gtx1080Ti.xml +++ /dev/null @@ -1,538 +0,0 @@ -<?xml version="1.0" ?> -<component id="root" name="root"> - <component id="system" name="system"> - <!--McPAT will skip the components if number is set to 0 --> - <param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported --> - <param name="number_of_cores" value="28"/> - <param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined--> - <param name="number_of_L1Directories" value="0"/> - <param name="number_of_L2Directories" value="0"/> - <param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports --> - <param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters --> - <param name="number_of_NoCs" value="1"/> - <param name="homogeneous_cores" value="1"/><!--1 means homo --> - <param name="homogeneous_L2s" value="1"/> - <param name="homogeneous_L1Directorys" value="1"/> - <param name="homogeneous_L2Directorys" value="1"/> - <param name="homogeneous_L3s" value="1"/> - <param name="homogeneous_ccs" value="1"/><!--cache coherece hardware --> - <param name="homogeneous_NoCs" value="1"/> - <param name="core_tech_node" value="23"/><!-- nm --> - <param name="target_core_clockrate" value="1481"/><!--MHz --> - <param name="temperature" value="380"/> <!-- Kelvin --> - <param name="number_cache_levels" value="2"/> - <param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology --> - <param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power) --> - <param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible --> - <param name="machine_bits" value="32"/> - <param name="virtual_address_width" value="32"/> - <param name="physical_address_width" value="32"/> - <param name="virtual_memory_page_size" value="4096"/> - <param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 --> - <!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/--> - <param name="TOT_INST" value="10" /> - <param name="FP_INT" value="10" /> - <param name="IC_H" value="0.001" /> - <param name="IC_M" value="10" /> - <param name="DC_RH" value="1" /> - <param name="DC_RM" value="1" /> - <param name="DC_WH" value="1" /> - <param name="DC_WM" value="1" /> - <param name="TC_H" value="0.001" /> - <param name="TC_M" value="10" /> - <param name="CC_H" value="4.5071" /> - <param name="CC_M" value="10" /> - <param name="SHRD_ACC" value="10" /> - <param name="REG_RD" value="1.6294" /> - <param name="REG_WR" value="0.5031" /> - <param name="NON_REG_OPs" value="0.01" /> - <param name="SP_ACC" value="10" /> - <param name="SFU_ACC" value="0.0082" /> - <param name="FPU_ACC" value="0.4126" /> - <param name="MEM_RD" value="0.1234" /> - <param name="MEM_WR" value="0.001" /> - <param name="MEM_PRE" value="0.001" /> - <param name="L2_RH" value="100" /> - <param name="L2_RM" value="100" /> - <param name="L2_WH" value="100" /> - <param name="L2_WM" value="42.6966" /> - <param name="NOC_A" value="100" /> - <param name="PIPE_A" value="44.8085" /> - <param name="IDLE_CORE_N" value="2.0382"/> - <param name="CONST_DYNAMICN" value="5.0005" /> - <stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period --> - <stat name="total_cycles" value="total_cycles_match_mcpat"/> - <stat name="idle_cycles" value="idle_cycles_match_mcpat"/> - <stat name="busy_cycles" value="busy_cycles_match_mcpat"/> - <!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of - virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank --> - <!-- *********************** cores ******************* --> - <component id="system.core0" name="core0"> - <!-- Core property --> - <param name="clock_rate" value="1481"/> - <param name="instruction_length" value="32"/> - <param name="opcode_width" value="9"/> - <!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller - default value is machine_bits, if not set --> - <param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO--> - <!-- inorder/OoO --> - <param name="number_hardware_threads" value="32"/> - <!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor, - it only may be more than one in SMT processors. BTB ports always equals to fetch ports since - branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> - <param name="fetch_width" value="1"/> - <!-- fetch_width determins the size of cachelines of L1 cache block --> - <param name="number_instruction_fetch_ports" value="1"/> - <param name="decode_width" value="1"/> - <!-- decode_width determins the number of ports of the - renaming table (both RAM and CAM) scheme --> - <param name="issue_width" value="2"/> - <!-- issue_width determins the number of ports of Issue window and other logic - as in the complexity effective proccessors paper; issue_width==dispatch_width --> - <param name="commit_width" value="2"/> - <!-- commit_width determins the number of ports of register files --> - <param name="fp_issue_width" value="1"/> - <param name="prediction_width" value="0"/> - <!-- number of branch instructions can be predicted simultannouesl--> - <!-- Current version of McPAT does not distinguish int and floating point pipelines - Theses parameters are reserved for future use.--> - <param name="pipelines_per_core" value="1,1"/> - <!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared--> - <param name="pipeline_depth" value="8,8"/> - <!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops --> - <!-- issue and exe unit--> - <param name="ALU_per_core" value="32"/> - <!-- contains an adder, a shifter, and a logical unit --> - <param name="MUL_per_core" value="4"/> - <!-- For MUL and Div --> - <param name="FPU_per_core" value="32"/> - <!-- buffer between IF and ID stage --> - <param name="instruction_buffer_size" value="1"/> - <!-- buffer between ID and sche/exe stage --> - <param name="decoded_stream_buffer_size" value="1"/> - <param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED--> - <!-- McPAT support 2 types of OoO cores, RS based and physical reg based--> - <param name="instruction_window_size" value="1"/> - <param name="fp_instruction_window_size" value="1"/> - <!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 --> - <param name="ROB_size" value="0"/> - <!-- each in-flight instruction has an entry in ROB --> - <!-- registers --> - <!-- SM parameters Added by Syed Gilani --> - <param name="rf_banks" value="32"/> - <param name="simd_width" value="32"/> - <param name="collector_units" value="32"/> - <param name="core_clock_ratio" value="2"/> - <param name="warp_size" value="32"/> - - <param name="archi_Regs_IRF_size" value="65536"/> - <param name="archi_Regs_FRF_size" value="32"/> - <!-- if OoO processor, phy_reg number is needed for renaming logic, - renaming logic is for both integer and floating point insts. --> - <param name="phy_Regs_IRF_size" value="32"/> - <param name="phy_Regs_FRF_size" value="32"/> - <!-- rename logic --> - <param name="rename_scheme" value="0"/> - <!-- can be RAM based(0) or CAM based(1) rename scheme - RAM-based scheme will have free list, status table; - CAM-based scheme have the valid bit in the data field of the CAM - both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions; - Detailed RAT Implementation see TR --> - <param name="register_windows_size" value="0"/> - <!-- how many windows in the windowed register file, sun processors; - no register windowing is used when this number is 0 --> - <!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha), - They will always try to exeute out-of-order though. --> - <param name="LSU_order" value="inorder"/> - <param name="store_buffer_size" value="32"/> - <!-- By default, in-order cores do not have load buffers --> - <param name="load_buffer_size" value="32"/> - <!-- number of ports refer to sustainable concurrent memory accesses --> - <param name="memory_ports" value="2"/> - <!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer - as well as the ports of Dcache which is connected to LSU --> - <!-- dual-pumped Dcache can be used to save the extra read/write ports --> - <param name="RAS_size" value="1"/> - <!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check --> - <!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops --> - <stat name="total_instructions" value="total_instructions_match_mcpat"/> - <stat name="int_instructions" value="int_instruction_match_mcpat"/> - <stat name="fp_instructions" value="flt_instruction_match_mcpat"/> - <stat name="branch_instructions" value="branch_instruction_match_mcpat"/> - <stat name="branch_mispredictions" value="0"/> - <stat name="load_instructions" value="load_instruction_match_mcpat"/> - <stat name="store_instructions" value="store_instruction_match_mcpat"/> - <stat name="committed_instructions" value="total_instructions_match_mcpat"/> - <stat name="committed_int_instructions" value="int_instruction_match_mcpat"/> - <stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/> - <stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous --> - <!-- the following cycle stats are used for heterogeneouse cores only, - please ignore them if homogeneouse cores --> - <stat name="total_cycles" value="total_cycles_match_mcpat"/> - <stat name="idle_cycles" value="idle_cycles_match_mcpat"/> - <stat name="busy_cycles" value="busy_cycles_match_mcpat"/> - <!-- instruction buffer stats --> - <!-- ROB stats, both RS and Phy based OoOs have ROB - performance simulator should capture the difference on accesses, - otherwise, McPAT has to guess based on number of commited instructions. --> - <stat name="ROB_reads" value="263886"/> - <stat name="ROB_writes" value="263886"/> - <!-- RAT accesses --> - <stat name="rename_accesses" value="263886"/> - <stat name="fp_rename_accesses" value="263886"/> - <!-- decode and rename stage use this, should be total ic - nop --> - <!-- Inst window stats --> - <stat name="inst_window_reads" value="263886"/> - <stat name="inst_window_writes" value="263886"/> - <stat name="inst_window_wakeup_accesses" value="263886"/> - <stat name="fp_inst_window_reads" value="263886"/> - <stat name="fp_inst_window_writes" value="263886"/> - <stat name="fp_inst_window_wakeup_accesses" value="263886"/> - <!-- RF accesses --> - <stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/> - <stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/> - <stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/> - <stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/> - - <!-- The following stat is for operand collector power - Added by Syed --> - <stat name="non_rf_operands" value="0"/> - - <!-- accesses to the working reg --> - <stat name="function_calls" value="0"/> - <stat name="context_switches" value="0"/> <!--not used in the McPAT --> - <!-- Number of Windowes switches (number of function calls and returns)--> - <!-- Alu stats by default, the processor has one FPU that includes the divider and - multiplier. The fpu accesses should include accesses to multiplier and divider --> - <stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/> - <stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/> - <stat name="mul_accesses" value="mul_accesses_match_mcpat"/> - <stat name="cdb_alu_accesses" value="0"/> - <stat name="cdb_mul_accesses" value="0"/> - <stat name="cdb_fpu_accesses" value="0"/> - <!-- multiple cycle accesses should be counted multiple times, - otherwise, McPAT can use internal counter for different floating point instructions - to get final accesses. But that needs detailed info for floating point inst mix --> - <!-- currently the performance simulator should - make sure all the numbers are final numbers, - including the explicit read/write accesses, - and the implicite accesses such as replacements and etc. - Future versions of McPAT may be able to reason the implicite access - based on param and stats of last level cache - The same rule applies to all cache access stats too! --> - <!-- following is AF for max power computation. - Do not change them, unless you understand them--> - <stat name="IFU_duty_cycle" value="0.25"/> - <stat name="LSU_duty_cycle" value="0.25"/> - <stat name="MemManU_I_duty_cycle" value="1"/> - <stat name="MemManU_D_duty_cycle" value="0.25"/> - <stat name="ALU_duty_cycle" value="0.9"/> - <stat name="MUL_duty_cycle" value="0.5"/> - <stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average --> - <stat name="ALU_cdb_duty_cycle" value="0.9"/> - <stat name="MUL_cdb_duty_cycle" value="0.5"/> - <stat name="FPU_cdb_duty_cycle" value="15"/> - <component id="system.core0.predictor" name="PBT"> - <!-- branch predictor; tournament predictor see Alpha implementation --> - <param name="local_predictor_size" value="10,3"/> - <param name="local_predictor_entries" value="1024"/> - <param name="global_predictor_entries" value="4096"/> - <param name="global_predictor_bits" value="2"/> - <param name="chooser_predictor_entries" value="4096"/> - <param name="chooser_predictor_bits" value="2"/> - <!-- These parameters can be combined like below in next version - <param name="load_predictor" value="10,3,1024"/> - <param name="global_predictor" value="4096,2"/> - <param name="predictor_chooser" value="4096,2"/> - --> - </component> - <component id="system.core0.itlb" name="itlb"> - <param name="number_entries" value="1"/> - <stat name="total_accesses" value="0"/> - <stat name="total_misses" value="0"/> - <stat name="conflicts" value="0"/> - <!-- there is no write requests to itlb although writes happen to itlb after miss, - which is actually a replacement --> - </component> - <component id="system.core0.icache" name="icache"> - <!-- there is no write requests to itlb although writes happen to it after miss, - which is actually a replacement --> - <param name="icache_config" value="16384,128,4,1,1,3,8,0"/> - <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> - <!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate --> - <param name="buffer_sizes" value="16, 16, 16,0"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="total_instructions_match_mcpat"/> - <stat name="read_misses" value="0"/> - <stat name="conflicts" value="0"/> - </component> - <component id="system.core0.dtlb" name="dtlb"> - <param name="number_entries" value="1"/> - <stat name="total_accesses" value="0"/> - <stat name="total_misses" value="0"/> - <stat name="conflicts" value="0"/> - </component> - <component id="system.core0.ccache" name="ccache"> - <!-- all the buffer related are optional --> - <param name="ccache_config" value="16384,64,2,1,1,3,8,0"/> - <param name="buffer_sizes" value="16, 16, 16, 0"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/> - <stat name="write_accesses" value="0"/> - <stat name="read_misses" value="ccache_read_misses_match_mcpat"/> - <stat name="write_misses" value="0"/> - <stat name="conflicts" value="0"/> - </component> - <component id="system.core0.tcache" name="tcache"> - <!-- all the buffer related are optional --> - <param name="tcache_config" value="49152,128,8,1,1,3,8,0"/> - <param name="buffer_sizes" value="16, 16, 16, 0"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/> - <stat name="write_accesses" value="0"/> - <stat name="read_misses" value="tcache_read_misses_match_mcpat"/> - <stat name="write_misses" value="0"/> - <stat name="conflicts" value="0"/> - </component> - <!--model the shared memory by mimicing dcache--> - <component id="system.core0.sharedmemory" name="sharedmemory"> - <!-- all the buffer related are optional --> - <param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/> - <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> - <param name="buffer_sizes" value="16, 16, 16, 16"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/> - <stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/> - <stat name="read_misses" value="0"/> - <stat name="write_misses" value="0"/> - <stat name="conflicts" value="0"/> - </component> - <component id="system.core0.dcache" name="dcache"> - <!-- all the buffer related are optional --> - <param name="dcache_config" value="16384,32,4,1,1,3,8,0"/> - <param name="buffer_sizes" value="16, 16, 16, 0"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="dcache_read_access_match_mcpat"/> - <stat name="write_accesses" value="dcache_write_access_match_mcpat"/> - <stat name="read_misses" value="dcache_read_miss_match_mcpat"/> - <stat name="write_misses" value="dcache_write_miss_match_mcpat"/> - <stat name="conflicts" value="0"/> - </component> - <component id="system.core0.BTB" name="BTB"> - <!-- all the buffer related are optional --> - <param name="BTB_config" value="8192,4,2,1, 1,3"/> - <!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> - </component> - </component> - <component id="system.L1Directory0" name="L1Directory0"> - <param name="Directory_type" value="0"/> - <!--0 cam based shadowed tag. 1 directory cache --> - <param name="Dir_config" value="2048,1,0,1, 4, 4,8"/> - <!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> - <param name="buffer_sizes" value="8, 8, 8, 8"/> - <!-- all the buffer related are optional --> - <param name="clockrate" value="1400"/> - <param name="ports" value="1,1,1"/> - <!-- number of r, w, and rw search ports --> - <param name="device_type" value="0"/> - <!-- altough there are multiple access types, - Performance simulator needs to cast them into reads or writes - e.g. the invalidates can be considered as writes --> - <stat name="read_accesses" value="800000"/> - <stat name="write_accesses" value="27276"/> - <stat name="read_misses" value="1632"/> - <stat name="write_misses" value="183"/> - <stat name="conflicts" value="20"/> - <stat name="duty_cycle" value="0.45"/> - </component> - <component id="system.L2Directory0" name="L2Directory0"> - <param name="Directory_type" value="1"/> - <!--0 cam based shadowed tag. 1 directory cache --> - <param name="Dir_config" value="1048576,16,16,1,2, 100"/> - <!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> - <param name="buffer_sizes" value="8, 8, 8, 8"/> - <!-- all the buffer related are optional --> - <param name="clockrate" value="1400"/> - <param name="ports" value="1,1,1"/> - <!-- number of r, w, and rw search ports --> - <param name="device_type" value="0"/> - <!-- altough there are multiple access types, - Performance simulator needs to cast them into reads or writes - e.g. the invalidates can be considered as writes --> - <stat name="read_accesses" value="0"/> - <stat name="write_accesses" value="0"/> - <stat name="read_misses" value="0"/> - <stat name="write_misses" value="0"/> - <stat name="conflicts" value="0"/> - <stat name="duty_cycle" value="0.45"/> - </component> - <component id="system.L20" name="L20"> - <!-- all the buffer related are optional --> - <param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/> - <!-- consider 4-way bank interleaving for Niagara 1 --> - <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> - <param name="buffer_sizes" value="16, 16, 16, 16"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <param name="clockrate" value="2962"/> - <param name="ports" value="1,1,1"/> - <!-- number of r, w, and rw ports --> - <param name="device_type" value="0"/> - <stat name="read_accesses" value="200000"/> - <stat name="write_accesses" value="0"/> - <stat name="read_misses" value="0"/> - <stat name="write_misses" value="0"/> - <stat name="conflicts" value="0"/> - <stat name="duty_cycle" value="0.5"/> - </component> - -<!--**********************************************************************--> -<component id="system.L30" name="L30"> - <param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/> - <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> - <param name="clockrate" value="3500"/> - <param name="ports" value="1,1,1"/> - <!-- number of r, w, and rw ports --> - <param name="device_type" value="0"/> - <param name="buffer_sizes" value="16, 16, 16, 16"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="58824"/> - <stat name="write_accesses" value="27276"/> - <stat name="read_misses" value="1632"/> - <stat name="write_misses" value="183"/> - <stat name="conflicts" value="0"/> - <stat name="duty_cycle" value="0.35"/> - </component> - - -<!--**********************************************************************--> - <component id="system.NoC0" name="noc0"> - <param name="clockrate" value="700"/> - <param name="type" value="1"/> - <!-- 1 NoC, O bus --> - <param name="horizontal_nodes" value="2"/> - <param name="vertical_nodes" value="1"/> - <param name="has_global_link" value="0"/> - <!-- 1 has global link, 0 does not have global link --> - <param name="link_throughput" value="1"/><!--w.r.t clock --> - <param name="link_latency" value="1"/><!--w.r.t clock --> - <!-- througput >= latency --> - <!-- Router architecture --> - <param name="input_ports" value="6"/> - <param name="output_ports" value="6"/> - <param name="virtual_channel_per_port" value="1"/> - <!-- input buffer; in classic routers only input ports need buffers --> - <param name="flit_bits" value="32"/> - <param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs--> - <param name="chip_coverage" value="1"/> - <!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 --> - <stat name="total_accesses" value="0"/> - <!-- This is the number of total accesses within the whole network not for each router --> - <stat name="duty_cycle" value="0.6"/> - </component> -<!--**********************************************************************--> -<!--**********************************************************************--> - - <component id="system.mem" name="mem"> - <!-- Main memory property --> - <param name="mem_tech_node" value="23"/> - <param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB --> - <param name="peak_transfer_rate" value="3200"/><!--MB/S--> - <param name="internal_prefetch_of_DRAM_chip" value="4"/> - <!-- 2 for DDR, 4 for DDR2, 8 for DDR3...--> - <!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property --> - <!-- above numbers can be easily found from Wikipedia --> - <param name="capacity_per_channel" value="4096"/> <!-- MB --> - <!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank - Current McPAT assumes single DIMMs are used.--> - <param name="number_ranks" value="2"/> - <param name="num_banks_of_DRAM_chip" value="6"/> - <param name="Block_width_of_DRAM_chip" value="64"/> <!-- B --> - <param name="output_width_of_DRAM_chip" value="8"/> - <!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip--> - <!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip--> - <param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 --> - <param name="burstlength_of_DRAM_chip" value="8"/> - <stat name="memory_accesses" value="1052"/> - <stat name="memory_reads" value="1052"/> - <stat name="memory_writes" value="1052"/> - </component> - <component id="system.mc" name="mc"> - <!-- Memeory controllers are for DDR(2,3...) DIMMs --> - <!-- current version of McPAT uses published values for base parameters of memory controller - improvments on MC will be added in later versions. --> - <param name="type" value="0"/> <!-- 1: low power; 0 high performance --> - <param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> - <param name="peak_transfer_rate" value="29568"/><!--MB/S Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs --> - <param name="block_size" value="64"/><!--B--> - <param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers --> - <!-- current McPAT only supports homogeneous memory controllers --> - <param name="memory_channels_per_mc" value="2"/> - <param name="number_ranks" value="1"/> - <param name="withPHY" value="0"/> - <!-- # of ranks of each channel--> - <param name="req_window_size_per_channel" value="16"/> - <param name="IO_buffer_size_per_channel" value="16"/> - <param name="databus_width" value="32"/> - <param name="addressbus_width" value="32"/> - <param name="PRT_entries" value="32"/> - <!-- # of empirical DRAM model parameter --> - <param name="dram_cmd_coeff" value="0"/> - <param name="dram_act_coeff" value="0"/> - <param name="dram_nop_coeff" value="0"/> - <param name="dram_activity_coeff" value="0"/> - <param name="dram_pre_coeff" value="3.8475e-8f"/> - <param name="dram_rd_coeff" value="7.74707143e-8f"/> - <param name="dram_wr_coeff" value="3.54664286e-8f"/> - <param name="dram_req_coeff" value="0"/> - <param name="dram_const_coeff" value="0"/> - - <!-- McPAT will add the control bus width to the addressbus width automatically --> - <stat name="memory_accesses" value="memory_accesses_match_mcpat"/> - <stat name="memory_reads" value="memory_reads_match_mcpat"/> - <stat name="memory_writes" value="memory_writes_match_mcpat"/> - <!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate - the average power per MC or per channel. This is sufficent for most application. - Further trackdown can be easily added in later versions. --> - </component> -<!--**********************************************************************--> - <component id="system.niu" name="niu"> - <!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller --> - <!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. - the low bound of clock rate of a 10Gb MAC is 150Mhz --> - <param name="type" value="0"/> <!-- 1: low power; 0 high performance --> - <param name="clockrate" value="350"/> - <param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port --> - <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 --> - <stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth --> - <!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate - the average power per nic or per channel. This is sufficent for most application. --> - </component> -<!--**********************************************************************--> - <component id="system.pcie" name="pcie"> - <!-- On chip PCIe controller, including Phy--> - <!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. - the low bound of clock rate of a PCIe per lane logic is 120Mhz --> - <param name="type" value="0"/> <!-- 1: low power; 0 high performance --> - <param name="withPHY" value="1"/> - <param name="clockrate" value="350"/> - <param name="number_units" value="0"/> - <param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 --> - <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 --> - <stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth --> - <!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate - the average power per pcie controller or per channel. This is sufficent for most application. --> - </component> -<!--**********************************************************************--> - <component id="system.flashc" name="flashc"> - <param name="number_flashcs" value="0"/> - <param name="type" value="1"/> <!-- 1: low power; 0 high performance --> - <param name="withPHY" value="1"/> - <param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S --> - <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 --> - <stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth --> - <!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate - the average power per fc or per channel. This is sufficent for most application --> - </component> -<!--**********************************************************************--> - - </component> -</component> diff --git a/bsmad_test/out.txt b/bsmad_test/out.txt deleted file mode 100644 index 4e95cb1..0000000 --- a/bsmad_test/out.txt +++ /dev/null @@ -1,1837 +0,0 @@ - - - *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** - - -GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: - 1=functional simulation only, 0=detailed performance simulator) -GPGPU-Sim: Configuration options: - --network_mode 1 # Interconnection network mode --inter_config_file config_fermi_islip.icnt # Interconnection network config file --gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries --gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] --gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus --gpgpu_ptx_force_max_capability 60 # Force maximum compute capability --gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file --gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file --gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output --gpgpu_simd_model 1 # 1 = post-dominator --gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>} --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>} --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) --gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) --n_regfile_gating_group 4 # group of lanes that should be read/written together) --gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations --gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations --gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) --gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) --gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) --gpgpu_n_clusters 28 # number of processing clusters --gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster --gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer --gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer --gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) --gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) --gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check --gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from --gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from --gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) --gpgpu_num_reg_banks 32 # Number of register banks (default = 8) --gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) --gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) --gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) --gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) --gpgpu_num_sched_per_core 2 # Number of warp schedulers per core --gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler --gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) --gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_num_sp_units 4 # Number of SP units (default=1) --gpgpu_num_sfu_units 1 # Number of SF units (default=1) --gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything --gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto --gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) --gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) --gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i --l2_ideal 0 # Use a ideal L2 cache that always hit --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only --gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu --gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module --gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller --gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs --gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip --gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip --gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) --gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) --dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) --gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} --rop_latency 120 # ROP queue latency (default 85) --dram_latency 100 # DRAM latency (default 30) --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>} --gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address --gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits --gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file --power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) --power_per_cycle_dump 0 # Dump detailed power output each cycle --power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) --power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) --steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) --steady_state_definition 8:4 # allowed deviation:number of samples --gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) --gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>} --liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) --gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call --gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call --gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) --gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) --gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) --gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>} --gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU --gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger --visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) --visualizer_outputfile NULL # Specifies the output log file for visualizer --visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) --trace_enabled 0 # Turn on traces --trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none --trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 --trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) --enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) --ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. --gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 --gpgpu_cdp_enabled 0 # Turn on CDP --save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx --keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs --gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file --ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,19,25,145,1 --ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30 --ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335 --ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,4,4,32,1 --ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5 --ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130 --cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600 -DRAM Timing Options: -nbk 16 # number of banks -CCD 2 # column to column delay -RRD 6 # minimal delay between activation of rows in different banks -RCD 12 # row to column delay -RAS 28 # time needed to activate row -RP 12 # time needed to precharge (deactivate) row -RC 40 # row cycle time -CDLR 5 # switching from write to read (changes tWTR) -WR 12 # last data-in to row precharge -CL 12 # CAS latency -WL 4 # Write latency -nbkgrp 1 # number of bank groups -CCDL 0 # column to column delay between accesses to different bank groups -RTPL 0 # read to precharge delay between accesses to different bank groups -Total number of memory sub partition = 22 -addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 -addr_dec_mask[BK] = 0000000000007080 high:15 low:7 -addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 -addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 -addr_dec_mask[BURST] = 000000000000001f high:5 low:0 -sub_partition_id_mask = 0000000000000080 -GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 -GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 -*** Initializing Memory Statistics *** -GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) -GPGPU-Sim uArch: Memory nodes ID start from index: 28 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 -GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) -GPGPU-Sim uArch: Memory nodes start from ID: 28 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 -1739ba94823ccfb8e12f742738e8e16e /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad -GPGPU-Sim uArch: performance model initialization complete. -GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default -self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad -Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " -Parsing file _cuobjdump_complete_output_leydyg -######### cuobjdump parser ######## -## Adding new section PTX -Adding ptx filename: _cuobjdump_1.ptx -Adding arch: sm_50 -Adding identifier: default -Done parsing!!! -GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 -WARNING: No guarantee that PTX will be parsed for SM version 50 -GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. -GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... -GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ -GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. -BEGINNING CUSTOM PTX. -ENDING CUSTOM PTX. -GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. -GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... -GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; -GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; -GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ -GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. -GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx -Adding _cuobjdump_1.ptx with cubin handle 1 -GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_8pgp00" -Running: cat _ptx_8pgp00 | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_ZhKBsL -GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_ZhKBsL --output-file /dev/null 2> _ptx_8pgp00info" -GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 -GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 -GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_8pgp00 _ptx2_ZhKBsL _ptx_8pgp00info" -GPGPU-Sim PTX: loading globals with explicit initializers... -GPGPU-Sim PTX: finished loading globals (0 bytes total). -GPGPU-Sim PTX: loading constants with explicit initializers... done. -GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 -GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes -GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes -GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes -GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes -GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Network latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Flit latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Fragmentation average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Injected packet rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Accepted packet rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Injected flit rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Accepted flit rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Injected packet size average = -nan (1 samples) -Accepted packet size average = -nan (1 samples) -Hops average = -nan (1 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Network latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Flit latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Fragmentation average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Injected packet rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Accepted packet rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Injected flit rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Accepted flit rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Injected packet size average = -nan (2 samples) -Accepted packet size average = -nan (2 samples) -Hops average = -nan (2 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i -GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 -bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Network latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Flit latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Fragmentation average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Injected packet rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Accepted packet rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Injected flit rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Accepted flit rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Injected packet size average = -nan (3 samples) -Accepted packet size average = -nan (3 samples) -Hops average = -nan (3 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) -GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' -GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit -GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) -GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 16:03:17 2017 -GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/bsmad_test/output b/bsmad_test/output deleted file mode 100644 index db0d524..0000000 --- a/bsmad_test/output +++ /dev/null @@ -1,2338 +0,0 @@ - - - *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** - - -GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: - 1=functional simulation only, 0=detailed performance simulator) -GPGPU-Sim: Configuration options: - --network_mode 1 # Interconnection network mode --inter_config_file config_fermi_islip.icnt # Interconnection network config file --gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries --gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] --gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus --gpgpu_ptx_force_max_capability 60 # Force maximum compute capability --gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file --gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file --gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output --gpgpu_simd_model 1 # 1 = post-dominator --gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>} --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>} --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) --gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) --n_regfile_gating_group 4 # group of lanes that should be read/written together) --gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations --gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations --gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) --gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) --gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) --gpgpu_n_clusters 28 # number of processing clusters --gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster --gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer --gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer --gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) --gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) --gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check --gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from --gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from --gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) --gpgpu_num_reg_banks 32 # Number of register banks (default = 8) --gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) --gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) --gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) --gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) --gpgpu_num_sched_per_core 2 # Number of warp schedulers per core --gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler --gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) --gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_num_sp_units 4 # Number of SP units (default=1) --gpgpu_num_sfu_units 1 # Number of SF units (default=1) --gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything --gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto --gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) --gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) --gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i --l2_ideal 0 # Use a ideal L2 cache that always hit --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only --gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu --gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module --gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller --gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs --gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip --gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip --gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) --gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) --dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) --gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} --rop_latency 120 # ROP queue latency (default 85) --dram_latency 100 # DRAM latency (default 30) --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>} --gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address --gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits --gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file --power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) --power_per_cycle_dump 0 # Dump detailed power output each cycle --power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) --power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) --steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) --steady_state_definition 8:4 # allowed deviation:number of samples --gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) --gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>} --liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) --gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call --gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call --gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) --gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) --gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) --gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>} --gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU --gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger --visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) --visualizer_outputfile NULL # Specifies the output log file for visualizer --visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) --trace_enabled 0 # Turn on traces --trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none --trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 --trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) --enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) --ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. --gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 --gpgpu_cdp_enabled 0 # Turn on CDP --save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx --keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs --gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file --ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,19,25,145,1 --ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30 --ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335 --ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,4,4,32,1 --ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5 --ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130 --cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600 -DRAM Timing Options: -nbk 16 # number of banks -CCD 2 # column to column delay -RRD 6 # minimal delay between activation of rows in different banks -RCD 12 # row to column delay -RAS 28 # time needed to activate row -RP 12 # time needed to precharge (deactivate) row -RC 40 # row cycle time -CDLR 5 # switching from write to read (changes tWTR) -WR 12 # last data-in to row precharge -CL 12 # CAS latency -WL 4 # Write latency -nbkgrp 1 # number of bank groups -CCDL 0 # column to column delay between accesses to different bank groups -RTPL 0 # read to precharge delay between accesses to different bank groups -Total number of memory sub partition = 22 -addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 -addr_dec_mask[BK] = 0000000000007080 high:15 low:7 -addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 -addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 -addr_dec_mask[BURST] = 000000000000001f high:5 low:0 -sub_partition_id_mask = 0000000000000080 -GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 -GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 -*** Initializing Memory Statistics *** -GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) -GPGPU-Sim uArch: Memory nodes ID start from index: 28 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 -GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) -GPGPU-Sim uArch: Memory nodes start from ID: 28 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 -733602e7cd2fc7896e7fece60068330a /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad -GPGPU-Sim uArch: performance model initialization complete. -GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default -self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad -Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " -Parsing file _cuobjdump_complete_output_Fvj0UD -######### cuobjdump parser ######## -## Adding new section PTX -Adding ptx filename: _cuobjdump_1.ptx -Adding arch: sm_50 -Adding identifier: default -Done parsing!!! -GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 -WARNING: No guarantee that PTX will be parsed for SM version 50 -GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. -GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... -GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ -GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. -BEGINNING CUSTOM PTX. -ENDING CUSTOM PTX. -GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. -GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... -GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; -GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; -GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ -GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. -GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx -Adding _cuobjdump_1.ptx with cubin handle 1 -GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_qiCCrA" -Running: cat _ptx_qiCCrA | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_zIGfYw -GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_zIGfYw --output-file /dev/null 2> _ptx_qiCCrAinfo" -GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 -GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 -GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_qiCCrA _ptx2_zIGfYw _ptx_qiCCrAinfo" -GPGPU-Sim PTX: loading globals with explicit initializers... -GPGPU-Sim PTX: finished loading globals (0 bytes total). -GPGPU-Sim PTX: loading constants with explicit initializers... done. -GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 -GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes -GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes -GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes -GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes -GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Network latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Flit latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Fragmentation average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Injected packet rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Accepted packet rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Injected flit rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Accepted flit rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Injected packet size average = -nan (1 samples) -Accepted packet size average = -nan (1 samples) -Hops average = -nan (1 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Network latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Flit latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Fragmentation average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Injected packet rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Accepted packet rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Injected flit rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Accepted flit rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Injected packet size average = -nan (2 samples) -Accepted packet size average = -nan (2 samples) -Hops average = -nan (2 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Network latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Flit latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Fragmentation average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Injected packet rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Accepted packet rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Injected flit rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Accepted flit rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Injected packet size average = -nan (3 samples) -Accepted packet size average = -nan (3 samples) -Hops average = -nan (3 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - -GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Network latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Flit latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Fragmentation average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Injected packet rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Accepted packet rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Injected flit rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Accepted flit rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Injected packet size average = -nan (4 samples) -Accepted packet size average = -nan (4 samples) -Hops average = -nan (4 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' -GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit -GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) -GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 13:33:51 2017 -GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/bsmad_test/output.txt b/bsmad_test/output.txt deleted file mode 100644 index 7414f61..0000000 --- a/bsmad_test/output.txt +++ /dev/null @@ -1,2338 +0,0 @@ - - - *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** - - -GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: - 1=functional simulation only, 0=detailed performance simulator) -GPGPU-Sim: Configuration options: - --network_mode 1 # Interconnection network mode --inter_config_file config_fermi_islip.icnt # Interconnection network config file --gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries --gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] --gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus --gpgpu_ptx_force_max_capability 60 # Force maximum compute capability --gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file --gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file --gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output --gpgpu_simd_model 1 # 1 = post-dominator --gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>} --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>} --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) --gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) --n_regfile_gating_group 4 # group of lanes that should be read/written together) --gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations --gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations --gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) --gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) --gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) --gpgpu_n_clusters 28 # number of processing clusters --gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster --gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer --gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer --gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) --gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) --gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check --gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from --gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from --gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) --gpgpu_num_reg_banks 32 # Number of register banks (default = 8) --gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) --gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) --gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) --gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) --gpgpu_num_sched_per_core 2 # Number of warp schedulers per core --gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler --gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) --gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_num_sp_units 4 # Number of SP units (default=1) --gpgpu_num_sfu_units 1 # Number of SF units (default=1) --gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything --gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto --gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) --gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) --gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i --l2_ideal 0 # Use a ideal L2 cache that always hit --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only --gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu --gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module --gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller --gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs --gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip --gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip --gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) --gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) --dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) --gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} --rop_latency 120 # ROP queue latency (default 85) --dram_latency 100 # DRAM latency (default 30) --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>} --gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address --gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits --gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file --power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) --power_per_cycle_dump 0 # Dump detailed power output each cycle --power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) --power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) --steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) --steady_state_definition 8:4 # allowed deviation:number of samples --gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) --gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>} --liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) --gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call --gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call --gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) --gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) --gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) --gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>} --gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU --gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger --visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) --visualizer_outputfile NULL # Specifies the output log file for visualizer --visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) --trace_enabled 0 # Turn on traces --trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none --trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 --trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) --enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) --ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. --gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 --gpgpu_cdp_enabled 0 # Turn on CDP --save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx --keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs --gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file --ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,19,25,145,1 --ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30 --ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335 --ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,4,4,32,1 --ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5 --ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130 --cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600 -DRAM Timing Options: -nbk 16 # number of banks -CCD 2 # column to column delay -RRD 6 # minimal delay between activation of rows in different banks -RCD 12 # row to column delay -RAS 28 # time needed to activate row -RP 12 # time needed to precharge (deactivate) row -RC 40 # row cycle time -CDLR 5 # switching from write to read (changes tWTR) -WR 12 # last data-in to row precharge -CL 12 # CAS latency -WL 4 # Write latency -nbkgrp 1 # number of bank groups -CCDL 0 # column to column delay between accesses to different bank groups -RTPL 0 # read to precharge delay between accesses to different bank groups -Total number of memory sub partition = 22 -addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 -addr_dec_mask[BK] = 0000000000007080 high:15 low:7 -addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 -addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 -addr_dec_mask[BURST] = 000000000000001f high:5 low:0 -sub_partition_id_mask = 0000000000000080 -GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 -GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 -*** Initializing Memory Statistics *** -GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) -GPGPU-Sim uArch: Memory nodes ID start from index: 28 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 -GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) -GPGPU-Sim uArch: Memory nodes start from ID: 28 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 -1739ba94823ccfb8e12f742738e8e16e /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad -GPGPU-Sim uArch: performance model initialization complete. -GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default -self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad -Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " -Parsing file _cuobjdump_complete_output_r35nHZ -######### cuobjdump parser ######## -## Adding new section PTX -Adding ptx filename: _cuobjdump_1.ptx -Adding arch: sm_50 -Adding identifier: default -Done parsing!!! -GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 -WARNING: No guarantee that PTX will be parsed for SM version 50 -GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. -GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... -GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ -GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. -BEGINNING CUSTOM PTX. -ENDING CUSTOM PTX. -GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. -GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... -GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; -GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; -GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ -GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. -GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx -Adding _cuobjdump_1.ptx with cubin handle 1 -GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_hSOoDH" -Running: cat _ptx_hSOoDH | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_FSgqzp -GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_FSgqzp --output-file /dev/null 2> _ptx_hSOoDHinfo" -GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 -GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 -GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_hSOoDH _ptx2_FSgqzp _ptx_hSOoDHinfo" -GPGPU-Sim PTX: loading globals with explicit initializers... -GPGPU-Sim PTX: finished loading globals (0 bytes total). -GPGPU-Sim PTX: loading constants with explicit initializers... done. -GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 -GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes -GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes -GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes -GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes -GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Network latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Flit latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Fragmentation average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Injected packet rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Accepted packet rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Injected flit rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Accepted flit rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Injected packet size average = -nan (1 samples) -Accepted packet size average = -nan (1 samples) -Hops average = -nan (1 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Network latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Flit latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Fragmentation average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Injected packet rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Accepted packet rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Injected flit rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Accepted flit rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Injected packet size average = -nan (2 samples) -Accepted packet size average = -nan (2 samples) -Hops average = -nan (2 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Network latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Flit latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Fragmentation average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Injected packet rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Accepted packet rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Injected flit rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Accepted flit rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Injected packet size average = -nan (3 samples) -Accepted packet size average = -nan (3 samples) -Hops average = -nan (3 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 - -GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) - 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Network latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Flit latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Fragmentation average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Injected packet rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Accepted packet rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Injected flit rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Accepted flit rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Injected packet size average = -nan (4 samples) -Accepted packet size average = -nan (4 samples) -Hops average = -nan (4 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' -GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit -GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) -GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 16:02:01 2017 -GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/bsmad_test/result b/bsmad_test/result deleted file mode 100644 index 210fed9..0000000 --- a/bsmad_test/result +++ /dev/null @@ -1,2338 +0,0 @@ - - - *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** - - -GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: - 1=functional simulation only, 0=detailed performance simulator) -GPGPU-Sim: Configuration options: - --network_mode 1 # Interconnection network mode --inter_config_file config_fermi_islip.icnt # Interconnection network config file --gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries --gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] --gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus --gpgpu_ptx_force_max_capability 60 # Force maximum compute capability --gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file --gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file --gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output --gpgpu_simd_model 1 # 1 = post-dominator --gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>} --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>} --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) --gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) --n_regfile_gating_group 4 # group of lanes that should be read/written together) --gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations --gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations --gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) --gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) --gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) --gpgpu_n_clusters 28 # number of processing clusters --gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster --gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer --gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer --gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) --gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) --gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check --gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from --gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from --gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) --gpgpu_num_reg_banks 32 # Number of register banks (default = 8) --gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) --gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) --gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) --gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) --gpgpu_num_sched_per_core 2 # Number of warp schedulers per core --gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler --gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) --gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_num_sp_units 4 # Number of SP units (default=1) --gpgpu_num_sfu_units 1 # Number of SF units (default=1) --gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything --gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto --gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) --gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) --gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i --l2_ideal 0 # Use a ideal L2 cache that always hit --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only --gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu --gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module --gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller --gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs --gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip --gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip --gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) --gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) --dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) --gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} --rop_latency 120 # ROP queue latency (default 85) --dram_latency 100 # DRAM latency (default 30) --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>} --gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address --gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits --gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file --power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) --power_per_cycle_dump 0 # Dump detailed power output each cycle --power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) --power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) --steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) --steady_state_definition 8:4 # allowed deviation:number of samples --gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) --gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>} --liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) --gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call --gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call --gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) --gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) --gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) --gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>} --gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU --gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger --visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) --visualizer_outputfile NULL # Specifies the output log file for visualizer --visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) --trace_enabled 0 # Turn on traces --trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none --trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 --trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) --enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) --ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. --gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 --gpgpu_cdp_enabled 0 # Turn on CDP --save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx --keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs --gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file --ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,19,25,145,1 --ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30 --ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335 --ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,4,4,32,1 --ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5 --ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130 --cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600 -DRAM Timing Options: -nbk 16 # number of banks -CCD 2 # column to column delay -RRD 6 # minimal delay between activation of rows in different banks -RCD 12 # row to column delay -RAS 28 # time needed to activate row -RP 12 # time needed to precharge (deactivate) row -RC 40 # row cycle time -CDLR 5 # switching from write to read (changes tWTR) -WR 12 # last data-in to row precharge -CL 12 # CAS latency -WL 4 # Write latency -nbkgrp 1 # number of bank groups -CCDL 0 # column to column delay between accesses to different bank groups -RTPL 0 # read to precharge delay between accesses to different bank groups -Total number of memory sub partition = 22 -addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 -addr_dec_mask[BK] = 0000000000007080 high:15 low:7 -addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 -addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 -addr_dec_mask[BURST] = 000000000000001f high:5 low:0 -sub_partition_id_mask = 0000000000000080 -GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 -GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 -*** Initializing Memory Statistics *** -GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) -GPGPU-Sim uArch: Memory nodes ID start from index: 28 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 -GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) -GPGPU-Sim uArch: Memory nodes start from ID: 28 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 -1739ba94823ccfb8e12f742738e8e16e /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad -GPGPU-Sim uArch: performance model initialization complete. -GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default -self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad -Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " -Parsing file _cuobjdump_complete_output_ppZXax -######### cuobjdump parser ######## -## Adding new section PTX -Adding ptx filename: _cuobjdump_1.ptx -Adding arch: sm_50 -Adding identifier: default -Done parsing!!! -GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 -WARNING: No guarantee that PTX will be parsed for SM version 50 -GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. -GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... -GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ -GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. -BEGINNING CUSTOM PTX. -ENDING CUSTOM PTX. -GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. -GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... -GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; -GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; -GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ -GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. -GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx -Adding _cuobjdump_1.ptx with cubin handle 1 -GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_D0f3bm" -Running: cat _ptx_D0f3bm | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_ctl9cb -GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_ctl9cb --output-file /dev/null 2> _ptx_D0f3bminfo" -GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 -GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 -GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_D0f3bm _ptx2_ctl9cb _ptx_D0f3bminfo" -GPGPU-Sim PTX: loading globals with explicit initializers... -GPGPU-Sim PTX: finished loading globals (0 bytes total). -GPGPU-Sim PTX: loading constants with explicit initializers... done. -GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 -GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes -GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes -GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes -GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes -GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Network latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Flit latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Fragmentation average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Injected packet rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Accepted packet rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Injected flit rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Accepted flit rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Injected packet size average = -nan (1 samples) -Accepted packet size average = -nan (1 samples) -Hops average = -nan (1 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Network latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Flit latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Fragmentation average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Injected packet rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Accepted packet rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Injected flit rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Accepted flit rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Injected packet size average = -nan (2 samples) -Accepted packet size average = -nan (2 samples) -Hops average = -nan (2 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Network latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Flit latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Fragmentation average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Injected packet rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Accepted packet rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Injected flit rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Accepted flit rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Injected packet size average = -nan (3 samples) -Accepted packet size average = -nan (3 samples) -Hops average = -nan (3 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - -GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Network latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Flit latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Fragmentation average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Injected packet rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Accepted packet rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Injected flit rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Accepted flit rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Injected packet size average = -nan (4 samples) -Accepted packet size average = -nan (4 samples) -Hops average = -nan (4 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' -GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit -GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) -GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 16:27:07 2017 -GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config index 436cb41..ee90c12 100644 --- a/configs/GTX480/gpgpusim.config +++ b/configs/GTX480/gpgpusim.config @@ -22,6 +22,7 @@ # shader core pipeline config -gpgpu_shader_registers 32768 +-gpgpu_occupancy_sm_number 20 # This implies a maximum of 48 warps/SM -gpgpu_shader_core_pipeline 1536:32 diff --git a/configs/GeForceGTX1080Ti/gpgpusim.config b/configs/GeForceGTX1080Ti/gpgpusim.config index 47c2b6a..fb044c6 100644 --- a/configs/GeForceGTX1080Ti/gpgpusim.config +++ b/configs/GeForceGTX1080Ti/gpgpusim.config @@ -3,7 +3,7 @@ # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 20 +-gpgpu_ptx_force_max_capability 60 # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 @@ -23,6 +23,7 @@ # shader core pipeline config -gpgpu_shader_registers 65536 +-gpgpu_occupancy_sm_number 60 # This implies a maximum of 64 warps/SM -gpgpu_shader_core_pipeline 2048:32 diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index 8b030b6..c675aab 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -21,6 +21,7 @@ # shader core pipeline config -gpgpu_shader_registers 65536 +-gpgpu_occupancy_sm_number 52 # This implies a maximum of 64 warps/SM -gpgpu_shader_core_pipeline 2048:32 diff --git a/bsmad_test/config_fermi_islip.icnt b/configs/Pascal_TITANX/config_fermi_islip.icnt index 2a69ddd..602daee 100644 --- a/bsmad_test/config_fermi_islip.icnt +++ b/configs/Pascal_TITANX/config_fermi_islip.icnt @@ -7,7 +7,7 @@ network_count = 2; // Topology topology = fly; -k = 50; +k = 52; n = 1; // Routing diff --git a/bsmad_test/gpgpusim.config b/configs/Pascal_TITANX/gpgpusim.config index 6b512ba..f78bd02 100644 --- a/bsmad_test/gpgpusim.config +++ b/configs/Pascal_TITANX/gpgpusim.config @@ -1,9 +1,11 @@ -# This config models the Pascal GP102 (GeForceGTX 1080Ti) +# This config models the Pascal GP102 (NVIDIA TITAN X) +# For more info about this card, see Nvidia White paper +# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 60 +-gpgpu_ptx_force_max_capability 61 # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 @@ -12,14 +14,14 @@ # high level architecture configuration -gpgpu_n_clusters 28 -gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 11 +-gpgpu_n_mem 12 -gpgpu_n_sub_partition_per_mchannel 2 # Pascal clock domains #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> # Pascal NVIDIA TITAN X clock domains are adopted from # https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 +-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 # shader core pipeline config -gpgpu_shader_registers 65536 @@ -30,7 +32,7 @@ -gpgpu_simd_model 1 # Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB ## Pascal GP102 has 4 SP SIMD units and 1 SFU unit ## we need to scale the number of pipeline registers to be equal to the number of SP units -gpgpu_pipeline_widths 4,1,1,4,1,1,6 @@ -40,26 +42,31 @@ # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" # SFU is 32-width in pascal, then dp units initiation is 1 cycle --ptx_opcode_latency_int 4,13,4,5,145,4,4 --ptx_opcode_initiation_int 1,2,2,2,8,4,4 +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 1,2,1,1,130 +-ptx_opcode_initiation_dp 4,8,4,4,130 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. # Pascal GP102 has 96KB Shared memory # Pascal GP102 has 64KB L1 cache -# The default is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +# The defulat is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 98304 +-gpgpu_shmem_size_PrefL1 98304 +-gpgpu_shmem_size_PrefShared 98304 -gmem_skip_L1D 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 -gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 # 4 KB Inst. -gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 @@ -79,7 +86,7 @@ -gpgpu_operand_collector_num_out_ports_sfu 1 -gpgpu_operand_collector_num_in_ports_mem 1 -gpgpu_operand_collector_num_out_ports_mem 1 -# gpgpu_num_reg_banks should be increased to 32, but it gives an error! +# gpgpu_num_reg_banks should be increased to 32 -gpgpu_num_reg_banks 32 # shared memory bankconflict detection @@ -108,8 +115,8 @@ -gpgpu_frfcfs_dram_sched_queue_size 64 -gpgpu_dram_return_queue_size 116 -# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) -# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) +# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition # the atom size of GDDR5X (the smallest read request) is 32 bytes -gpgpu_n_mem_per_ctrlr 1 -gpgpu_dram_buswidth 4 @@ -123,8 +130,8 @@ -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" -# Pascal has four schedulers per core --gpgpu_num_sched_per_core 2 +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 4 # Two Level Scheduler with active and pending pools #-gpgpu_scheduler two_level_active:6:0:1 # Loose round robbin scheduler @@ -140,7 +147,7 @@ # power model configs -power_simulation_enabled 1 --gpuwattch_xml_file gpuwattch_gtx1080Ti.xml +-gpuwattch_xml_file gpuwattch_gtx480.xml # tracing functionality #-trace_enabled 1 diff --git a/configs/QuadroFX5600/gpgpusim.config b/configs/QuadroFX5600/gpgpusim.config index cb87b65..6f836ee 100644 --- a/configs/QuadroFX5600/gpgpusim.config +++ b/configs/QuadroFX5600/gpgpusim.config @@ -11,6 +11,9 @@ # shader core pipeline config -gpgpu_shader_registers 16384 +-gpgpu_occupancy_sm_number 12 + +-gpgpu_occupancy_sm_number 12 #8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though) -gpgpu_shader_core_pipeline 768:32 -gpgpu_shader_cta 8 diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index 82243c2..fef1110 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -11,6 +11,8 @@ # shader core pipeline config -gpgpu_shader_registers 16384 +-gpgpu_occupancy_sm_number 13 + -gpgpu_shader_core_pipeline 1024:32 -gpgpu_shader_cta 8 -gpgpu_simd_model 1 diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config index 442ab8b..6ac2c12 100644 --- a/configs/TeslaC2050/gpgpusim.config +++ b/configs/TeslaC2050/gpgpusim.config @@ -25,6 +25,7 @@ # shader core pipeline config -gpgpu_shader_registers 32768 +-gpgpu_occupancy_sm_number 20 # This implies a maximum of 48 warps/SM -gpgpu_shader_core_pipeline 1536:32 diff --git a/cuda-kernels/Makefile b/cuda-kernels/Makefile deleted file mode 100755 index b33519f..0000000 --- a/cuda-kernels/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -all: tensorcore_type32_32.cu - nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o tensor_core tensorcore_type32_32.cu -# nvcc -arch=sm_70 -lcudart -g -o tensor_core tensor_core.cu - -.PHONY: -clean: - rm _cuob* - rm gpgpusim_power* - rm gpgpu_inst_stats.txt - rm gpgpusim_visualizer* -# nvcc -arch=sm_70 --gpu-architecture=compute_50 --gpu-code=compute_50 -lcudart -g -o tensor_core tensor_core.cu diff --git a/cuda-kernels/TensorCoreMatrixCArrangement.xlsx b/cuda-kernels/TensorCoreMatrixCArrangement.xlsx Binary files differdeleted file mode 100644 index 785ecc3..0000000 --- a/cuda-kernels/TensorCoreMatrixCArrangement.xlsx +++ /dev/null diff --git a/cuda-kernels/VPlog/parsing_script.py b/cuda-kernels/VPlog/parsing_script.py deleted file mode 100644 index 627c216..0000000 --- a/cuda-kernels/VPlog/parsing_script.py +++ /dev/null @@ -1,140 +0,0 @@ -import re -import time -from time import strftime - -def main(): -# time_now = str(strftime("%Y-%m-%d %H-%M-%S", time.localtime())) -# file = "\\" + "Parser Output " + time_now + ".txt" - - regexlist=[] - regexlist.append('gpu_sim_cycle.*') - regexlist.append('gpu_ipc.*') - regexlist.append('gpu_tot_issued_cta.*') - regexlist.append('L1I_total_cache_accesses.*' ) - regexlist.append('L1I_total_cache_misses.*') - regexlist.append('L1C_total_cache_accesses.*') - regexlist.append('L1C_total_cache_misses.*') - regexlist.append('Total_core_cache_stats_breakdown\[CONST_ACC_R\]\[HIT\].*') - regexlist.append('Total_core_cache_stats_breakdown\[CONST_ACC_R\]\[MISS\].*') - regexlist.append('Total_core_cache_stats_breakdown\[INST_ACC_R\]\[HIT\].*') - regexlist.append('Total_core_cache_stats_breakdown\[INST_ACC_R\]\[MISS\].*') - regexlist.append('gpgpu_n_tot_thrd_icount.*') - regexlist.append('gpgpu_n_tot_w_icount.*') - regexlist.append('gpgpu_n_stall_shd_mem.*') - regexlist.append('gpgpu_n_mem_read_global.*') - regexlist.append('gpgpu_n_mem_write_global.*') - regexlist.append('gpgpu_n_mem_const.*') - regexlist.append('gpgpu_n_load_insn.*') - regexlist.append('gpgpu_n_store_insn.*') - regexlist.append('gpgpu_n_param_mem_insn.*') - regexlist.append('traffic_breakdown_coretomem\[CONST_ACC_R\].*') - regexlist.append('traffic_breakdown_coretomem\[GLOBAL_ACC_R\].*') - regexlist.append('traffic_breakdown_coretomem\[GLOBAL_ACC_W\].*') - regexlist.append('traffic_breakdown_coretomem\[INST_ACC_R\].*') - regexlist.append('traffic_breakdown_memtocore\[CONST_ACC_R\].*') - regexlist.append('traffic_breakdown_memtocore\[GLOBAL_ACC_R\].*') - regexlist.append('traffic_breakdown_memtocore\[GLOBAL_ACC_W\].*') - regexlist.append('traffic_breakdown_memtocore\[INST_ACC_R\].*') - regexlist.append('L2_total_cache_accesses.*') - regexlist.append('L2_total_cache_misses.*') - regexlist.append('L2_cache_stats_breakdown\[GLOBAL_ACC_R\]\[HIT\].*') - regexlist.append('L2_cache_stats_breakdown\[GLOBAL_ACC_R\]\[MISS\].*') - regexlist.append('L2_cache_stats_breakdown\[CONST_ACC_R\]\[HIT\].*') - regexlist.append('L2_cache_stats_breakdown\[CONST_ACC_R\]\[MISS\].*') - regexlist.append('L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\].*') - regexlist.append('L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[MISS\].*') - regexlist.append('L2_cache_stats_breakdown\[INST_ACC_R\]\[MISS\].*') - - #VP4 - log_file_path = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp4_16_summary" - export_file = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp4_16_parsed" - for regex in regexlist: - parseData(log_file_path, export_file, regex, read_line=True) - log_file_path = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp4_32_summary" - export_file = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp4_32_parsed" - for regex in regexlist: - parseData(log_file_path, export_file, regex, read_line=True) - log_file_path = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp4_64_summary" - export_file = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp4_64_parsed" - for regex in regexlist: - parseData(log_file_path, export_file, regex, read_line=True) - log_file_path = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp4_128_summary" - export_file = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp4_128_parsed" - for regex in regexlist: - parseData(log_file_path, export_file, regex, read_line=True) - log_file_path = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp4_256_summary" - export_file = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp4_256_parsed" - for regex in regexlist: - parseData(log_file_path, export_file, regex, read_line=True) - - - #VP8 - log_file_path = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp8_16_summary" - export_file = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp8_16_parsed" - for regex in regexlist: - parseData(log_file_path, export_file, regex, read_line=True) - log_file_path = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp8_32_summary" - export_file = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp8_32_parsed" - for regex in regexlist: - parseData(log_file_path, export_file, regex, read_line=True) - log_file_path = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp8_64_summary" - export_file = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp8_64_parsed" - for regex in regexlist: - parseData(log_file_path, export_file, regex, read_line=True) - log_file_path = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp8_128_summary" - export_file = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp8_128_parsed" - for regex in regexlist: - parseData(log_file_path, export_file, regex, read_line=True) - log_file_path = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp8_256_summary" - export_file = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp8_256_parsed" - for regex in regexlist: - parseData(log_file_path, export_file, regex, read_line=True) - - #VP16 - log_file_path = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp16_16_summary" - export_file = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp16_16_parsed" - for regex in regexlist: - parseData(log_file_path, export_file, regex, read_line=True) - log_file_path = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp16_32_summary" - export_file = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp16_32_parsed" - for regex in regexlist: - parseData(log_file_path, export_file, regex, read_line=True) - log_file_path = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp16_64_summary" - export_file = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp16_64_parsed" - for regex in regexlist: - parseData(log_file_path, export_file, regex, read_line=True) - log_file_path = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp16_128_summary" - export_file = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp16_128_parsed" - for regex in regexlist: - parseData(log_file_path, export_file, regex, read_line=True) - log_file_path = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp16_256_summary" - export_file = r"/home/araihan/negar-gpgpusim-tensorcore/cuda-kernels/VPlog/vp16_256_parsed" - for regex in regexlist: - parseData(log_file_path, export_file, regex, read_line=True) - -def parseData(log_file_path, export_file, regex, read_line=True): - with open(log_file_path, "r") as file: - match_list = [] - if read_line == True: - for line in file: - for match in re.finditer(regex, line, re.S): - match_text = match.group() - match_text = re.sub('^.*=','',match_text.rstrip()) - match_list.append(match_text+'\n') - print match_text - else: - data = file.read() - for match in re.finditer(regex, data, re.S): - match_text = match.group(); - match_list.append(match_text) - file.close() - - with open(export_file, "a+") as file: - match_list_clean = list(set(match_list)) - for item in xrange(0, len(match_list_clean)): - print match_list_clean[item] - file.write(match_list_clean[item] )#+ "\n") - file.close() - -if __name__ == '__main__': - main() diff --git a/cuda-kernels/config_fermi_islip.icnt b/cuda-kernels/config_fermi_islip.icnt deleted file mode 100755 index 3b8b496..0000000 --- a/cuda-kernels/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 102; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/cuda-kernels/genericMatrixMultiply.cu b/cuda-kernels/genericMatrixMultiply.cu deleted file mode 100644 index 8b96483..0000000 --- a/cuda-kernels/genericMatrixMultiply.cu +++ /dev/null @@ -1,288 +0,0 @@ -/* Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of NVIDIA CORPORATION nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY - * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <stdio.h> -#include <stdlib.h> -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (64) -#define MATRIX_N (64) -#define MATRIX_K (64) - - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - -__global__ void wmma_example(half *a, half *b, float *c, int M, int N, int K, float alpha, float beta) { - // Leading dimensions. Packed with no transpositions. - int lda = M; - int ldb = K; - int ldc = M; - - // Tile using a 2D grid - int warpM = (blockIdx.x * blockDim.x + threadIdx.x) / warpSize; - int warpN = (blockIdx.y * blockDim.y + threadIdx.y); - - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> acc_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - wmma::fill_fragment(acc_frag, 0.0f); - - // Loop over k - for (int i = 0; i < K; i += WMMA_K) { - int aRow = warpM * WMMA_M; - int aCol = i; - - int bRow = i; - int bCol = warpN * WMMA_N; - - // Bounds checking - if (aRow < M && aCol < K && bRow < K && bCol < N) { - // Load the inputs - wmma::load_matrix_sync(a_frag, a + aRow + aCol * lda, lda); - wmma::load_matrix_sync(b_frag, b + bRow + bCol * ldb, ldb); - - // Perform the matrix multiplication - wmma::mma_sync(acc_frag, a_frag, b_frag, acc_frag); - - } - } - - // Load in the current value of c, scale it by beta, and add this our result scaled by alpha - int cRow = warpM * WMMA_M; - int cCol = warpN * WMMA_N; - - if (cRow < M && cCol < N) { - wmma::load_matrix_sync(c_frag, c + cRow + cCol * ldc, ldc, wmma::mem_col_major); - - - for(int i=0; i < c_frag.num_elements; i++) { - c_frag.x[i] = alpha * acc_frag.x[i] + beta * c_frag.x[i]; - } - - // Store the output - wmma::store_matrix_sync(c + cRow + cCol * ldc, c_frag, ldc, wmma::mem_col_major); - } -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -int main(int argc, char* argv[]) { - float *a_fp32; - float *b_fp32; - half *a_fp16; - half *b_fp16; - - float *c; - float *c_wmma; - - float *d_host_wmma; - float *d_cal_host_wmma; - float *a_host_wmma; - float *b_host_wmma; - float *c_host_wmma; - - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - - - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - cudaErrCheck(cudaMalloc((void**)&a_fp32, MATRIX_M * MATRIX_K * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&b_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&a_fp16, MATRIX_M * MATRIX_K * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&b_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - - cudaErrCheck(cudaMalloc((void**)&c, MATRIX_M * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&c_wmma, MATRIX_M * MATRIX_N * sizeof(float))); - - d_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_cal_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - c_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - a_host_wmma = (float*)malloc(MATRIX_M * MATRIX_K * sizeof(float)); - b_host_wmma = (float*)malloc(MATRIX_K * MATRIX_N * sizeof(float)); - - - printf("INITIAL_MATRIX_A\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]= (rand()%3);///3.0; - printf("%.2f ",a_host_wmma[m*MATRIX_K+n]); - } - printf("\n"); - } - printf("INITIAL_MATRIX_B\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]=(rand()%3);///3.0; - printf("%.2f ",b_host_wmma[m*MATRIX_K+n]); - } - printf("\n"); - } - printf("INITIAL_MATRIX_C\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_host_wmma[m*MATRIX_N+n]= (rand()%3);///3.0; - printf("%.2f ",c_host_wmma[m*MATRIX_K+n]); - } - printf("\n"); - } - - cudaErrCheck(cudaMemcpy(a_fp32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_fp32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - - convertFp32ToFp16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_fp16, a_fp32, MATRIX_M * MATRIX_K); - convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); - - cudaErrCheck(cudaMemcpy(c, c_host_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_wmma, c, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToDevice)); - - float alpha = 1.0f; - float beta = 1.0f; - - - printf("\nM = %d, N = %d, K = %d. alpha = %f, beta = %f\n\n", MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta); - - // First: using WMMA - dim3 gridDim; - dim3 blockDim; - - // blockDim.x must be a multple of warpSize - // 128x4 means we have 16 warps and a block computes a 64x64 output tile - blockDim.x = 64; - blockDim.y = 2; - - gridDim.x = (MATRIX_M + (WMMA_M * blockDim.x / 32 - 1)) / (WMMA_M * blockDim.x / 32); - gridDim.y = (MATRIX_N + WMMA_N * blockDim.y - 1) / (WMMA_N * blockDim.y); - printf("GRID:X=%d,Y=%d\n",gridDim.x,gridDim.y); - printf("BLOCK:X=%d,Y=%d\n",blockDim.x,blockDim.y); - - printf("Running with wmma...\n"); - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example <<< gridDim, blockDim >>> (a_fp16, b_fp16, c_wmma, MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - - printf("\nChecking results...\n"); - cudaErrCheck(cudaMemcpy(d_host_wmma, c_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - - int t=200000000; - while(t-->0); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[n*MATRIX_N+m]; - } - } - printf("cal:d\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%.2f ",d_cal_host_wmma[m*MATRIX_K+n]); - } - printf("\n"); - } - printf("wmma:d\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%.2f ",d_host_wmma[m*MATRIX_K+n]); - } - printf("\n"); - } - int suc=1; - float relative_error; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - relative_error=100*abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])/d_host_wmma[m*MATRIX_N+n]; - printf("relative_error=%f\n",relative_error); - if((int)relative_error>1) - { - printf("ERROR:\n"); - suc=0; - printf("ROW=%d,COL=%d:cpu=%f,gpgpusim=%f\n",m,n,d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("COMPLETED_SUCCESSFULLY\n"); - - //int errors = 0; - //for (int i = 0; i < MATRIX_M * MATRIX_N; i++) { - // float v1 = c_host_wmma[i]; - // float v2 = c_host_cublas[i]; - // if (v1 / v2 > 1.0001 || v2 / v1 > 1.0001 || abs(v1 - v2) > 1e-5) { - // errors++; - // if (errors < 10) printf("%f %f\n", v1, v2); - // } - //} - - float wmmaTime; - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma took %fms\n", wmmaTime); - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - cudaErrCheck(cudaFree(a_fp32)); - cudaErrCheck(cudaFree(b_fp32)); - cudaErrCheck(cudaFree(a_fp16)); - cudaErrCheck(cudaFree(b_fp16)); - cudaErrCheck(cudaFree(c)); - cudaErrCheck(cudaFree(c_wmma)); - free(d_host_wmma); - free(c_host_wmma); - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuda-kernels/genericMatrixMultiplyRow.cu b/cuda-kernels/genericMatrixMultiplyRow.cu deleted file mode 100644 index 6194492..0000000 --- a/cuda-kernels/genericMatrixMultiplyRow.cu +++ /dev/null @@ -1,289 +0,0 @@ -/* Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of NVIDIA CORPORATION nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY - * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <stdio.h> -#include <stdlib.h> -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (32) -#define MATRIX_N (32) -#define MATRIX_K (32) - - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - -__global__ void wmma_example(half *a, half *b, float *c, int M, int N, int K, float alpha, float beta) { - // Leading dimensions. Packed with no transpositions. - int lda = M; - int ldb = K; - int ldc = M; - - // Tile using a 2D grid - int warpM = (blockIdx.x * blockDim.x + threadIdx.x) / warpSize; - int warpN = (blockIdx.y * blockDim.y + threadIdx.y); - - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> acc_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - wmma::fill_fragment(acc_frag, 0.0f); - - // Loop over k - for (int i = 0; i < K; i += WMMA_K) { - int aRow = warpM * WMMA_M; - int aCol = i; - - int bRow = i; - int bCol = warpN * WMMA_N; - - // Bounds checking - if (aRow < M && aCol < K && bRow < K && bCol < N) { - // Load the inputs - wmma::load_matrix_sync(a_frag, a + aRow * lda+ aCol , lda); - wmma::load_matrix_sync(b_frag, b + bRow * ldb+ bCol , ldb); - - // Perform the matrix multiplication - wmma::mma_sync(acc_frag, a_frag, b_frag, acc_frag); - - } - } - - // Load in the current value of c, scale it by beta, and add this our result scaled by alpha - int cRow = warpM * WMMA_M; - int cCol = warpN * WMMA_N; - - if (cRow < M && cCol < N) { - wmma::load_matrix_sync(c_frag, c + cRow*ldc + cCol , ldc, wmma::mem_row_major); - - - for(int i=0; i < c_frag.num_elements; i++) { - c_frag.x[i] = alpha * acc_frag.x[i] + beta * c_frag.x[i]; - } - - // Store the output - wmma::store_matrix_sync(c + cRow *ldc + cCol , c_frag, ldc, wmma::mem_row_major); - } -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -int main(int argc, char* argv[]) { - float *a_fp32; - float *b_fp32; - half *a_fp16; - half *b_fp16; - - float *c; - float *c_wmma; - - float *d_host_wmma; - float *d_cal_host_wmma; - float *a_host_wmma; - float *b_host_wmma; - float *c_host_wmma; - - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - - - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - cudaErrCheck(cudaMalloc((void**)&a_fp32, MATRIX_M * MATRIX_K * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&b_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&a_fp16, MATRIX_M * MATRIX_K * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&b_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - - cudaErrCheck(cudaMalloc((void**)&c, MATRIX_M * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&c_wmma, MATRIX_M * MATRIX_N * sizeof(float))); - - d_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_cal_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - c_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - a_host_wmma = (float*)malloc(MATRIX_M * MATRIX_K * sizeof(float)); - b_host_wmma = (float*)malloc(MATRIX_K * MATRIX_N * sizeof(float)); - - - printf("INITIAL_MATRIX_A\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]= (rand()%3);///3.0; - printf("%.2f ",a_host_wmma[m*MATRIX_K+n]); - } - printf("\n"); - } - printf("INITIAL_MATRIX_B\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]=(rand()%3);///3.0; - printf("%.2f ",b_host_wmma[m*MATRIX_K+n]); - } - printf("\n"); - } - printf("INITIAL_MATRIX_C\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_host_wmma[m*MATRIX_N+n]= (rand()%3);///3.0; - printf("%.2f ",c_host_wmma[m*MATRIX_K+n]); - } - printf("\n"); - } - - cudaErrCheck(cudaMemcpy(a_fp32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_fp32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - - convertFp32ToFp16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_fp16, a_fp32, MATRIX_M * MATRIX_K); - convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); - - cudaErrCheck(cudaMemcpy(c, c_host_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_wmma, c, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToDevice)); - - float alpha = 1.0f; - float beta = 1.0f; - - - printf("\nM = %d, N = %d, K = %d. alpha = %f, beta = %f\n\n", MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta); - - // First: using WMMA - dim3 gridDim; - dim3 blockDim; - - // blockDim.x must be a multple of warpSize - // 128x4 means we have 16 warps and a block computes a 64x64 output tile - blockDim.x = 64; - blockDim.y = 2; - - gridDim.x = (MATRIX_M + (WMMA_M * blockDim.x / 32 - 1)) / (WMMA_M * blockDim.x / 32); - gridDim.y = (MATRIX_N + WMMA_N * blockDim.y - 1) / (WMMA_N * blockDim.y); - printf("GRID:X=%d,Y=%d\n",gridDim.x,gridDim.y); - printf("BLOCK:X=%d,Y=%d\n",blockDim.x,blockDim.y); - - printf("Running with wmma...\n"); - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example <<< gridDim, blockDim >>> (a_fp16, b_fp16, c_wmma, MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - - printf("\nChecking results...\n"); - cudaErrCheck(cudaMemcpy(d_host_wmma, c_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - - int t=200000000; - while(t-->0); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - printf("cal:d\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%.2f ",d_cal_host_wmma[m*MATRIX_K+n]); - } - printf("\n"); - } - printf("wmma:d\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%.2f ",d_host_wmma[m*MATRIX_K+n]); - } - printf("\n"); - } - int suc=1; - float relative_error; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - relative_error=100*abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])/d_host_wmma[m*MATRIX_N+n]; - printf("relative_error=%f\n",relative_error); - if((int)relative_error>1) - { - printf("ERROR:\n"); - suc=0; - printf("ROW=%d,COL=%d:cpu=%f,gpgpusim=%f\n",m,n,d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("COMPLETED_SUCCESSFULLY\n"); - - //int errors = 0; - //for (int i = 0; i < MATRIX_M * MATRIX_N; i++) { - // float v1 = c_host_wmma[i]; - // float v2 = c_host_cublas[i]; - // if (v1 / v2 > 1.0001 || v2 / v1 > 1.0001 || abs(v1 - v2) > 1e-5) { - // errors++; - // if (errors < 10) printf("%f %f\n", v1, v2); - // } - //} - - float wmmaTime; - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma took %fms\n", wmmaTime); - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - cudaErrCheck(cudaFree(a_fp32)); - cudaErrCheck(cudaFree(b_fp32)); - cudaErrCheck(cudaFree(a_fp16)); - cudaErrCheck(cudaFree(b_fp16)); - cudaErrCheck(cudaFree(c)); - cudaErrCheck(cudaFree(c_wmma)); - free(d_host_wmma); - free(c_host_wmma); - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuda-kernels/gpgpusim.config b/cuda-kernels/gpgpusim.config deleted file mode 100755 index 5f1be25..0000000 --- a/cuda-kernels/gpgpusim.config +++ /dev/null @@ -1,151 +0,0 @@ -# This config models the Pascal GP102 (GeForceGTX 1080Ti) - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 70 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 80 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 11 --gpgpu_n_sub_partition_per_mchannel 2 - -# Pascal clock domains -#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> -# Pascal NVIDIA TITAN X clock domains are adopted from -# https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 1 SFU unit -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,1,1,1,1,4,1,1,1,1,6 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 1 -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# SFU is 32-width in pascal, then dp units initiation is 1 cycle --ptx_opcode_latency_int 4,13,4,5,145,16,4 --ptx_opcode_initiation_int 1,2,2,2,8,16,4 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 1,2,1,1,130 - -# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP102 has 96KB Shared memory -# Pascal GP102 has 64KB L1 cache -# The default is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 --gpgpu_shmem_size 98304 --gmem_skip_L1D 1 - -# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 --gpgpu_cache:dl2_texture_only 0 - -# 4 KB Inst. --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 -# 12 KB Const --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 - -# enable operand collector -## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units --gpgpu_operand_collector_num_units_sp 20 --gpgpu_operand_collector_num_units_sfu 4 -#-gpgpu_operand_collector_num_units_tensor_core 24 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 -#-gpgpu_operand_collector_num_in_ports_tensor_core 1 -#-gpgpu_operand_collector_num_out_ports_tensor_core 1 --gpgpu_operand_collector_num_in_ports_mem 10 --gpgpu_operand_collector_num_out_ports_mem 10 -# gpgpu_num_reg_banks should be increased to 32, but it gives an error! --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - -## In Pascal, a warp scheduler can issue 2 insts per cycle --gpgpu_max_insn_issue_per_warp 2 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 116 - -# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) -# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition -# the atom size of GDDR5X (the smallest read request) is 32 bytes --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5X is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS - -# Use the same GDDR5 timing from hynix H5GQ1H24AFR -# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" - -# Pascal has four schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 1 - -# power model configs --power_simulation_enabled 1 --gpuwattch_xml_file gpuwattch_gtx1080Ti.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/cuda-kernels/gpuwattch_gtx1080Ti.xml b/cuda-kernels/gpuwattch_gtx1080Ti.xml deleted file mode 100755 index 02619ff..0000000 --- a/cuda-kernels/gpuwattch_gtx1080Ti.xml +++ /dev/null @@ -1,538 +0,0 @@ -<?xml version="1.0" ?> -<component id="root" name="root"> - <component id="system" name="system"> - <!--McPAT will skip the components if number is set to 0 --> - <param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported --> - <param name="number_of_cores" value="28"/> - <param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined--> - <param name="number_of_L1Directories" value="0"/> - <param name="number_of_L2Directories" value="0"/> - <param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports --> - <param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters --> - <param name="number_of_NoCs" value="1"/> - <param name="homogeneous_cores" value="1"/><!--1 means homo --> - <param name="homogeneous_L2s" value="1"/> - <param name="homogeneous_L1Directorys" value="1"/> - <param name="homogeneous_L2Directorys" value="1"/> - <param name="homogeneous_L3s" value="1"/> - <param name="homogeneous_ccs" value="1"/><!--cache coherece hardware --> - <param name="homogeneous_NoCs" value="1"/> - <param name="core_tech_node" value="23"/><!-- nm --> - <param name="target_core_clockrate" value="1481"/><!--MHz --> - <param name="temperature" value="380"/> <!-- Kelvin --> - <param name="number_cache_levels" value="2"/> - <param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology --> - <param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power) --> - <param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible --> - <param name="machine_bits" value="32"/> - <param name="virtual_address_width" value="32"/> - <param name="physical_address_width" value="32"/> - <param name="virtual_memory_page_size" value="4096"/> - <param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 --> - <!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/--> - <param name="TOT_INST" value="10" /> - <param name="FP_INT" value="10" /> - <param name="IC_H" value="0.001" /> - <param name="IC_M" value="10" /> - <param name="DC_RH" value="1" /> - <param name="DC_RM" value="1" /> - <param name="DC_WH" value="1" /> - <param name="DC_WM" value="1" /> - <param name="TC_H" value="0.001" /> - <param name="TC_M" value="10" /> - <param name="CC_H" value="4.5071" /> - <param name="CC_M" value="10" /> - <param name="SHRD_ACC" value="10" /> - <param name="REG_RD" value="1.6294" /> - <param name="REG_WR" value="0.5031" /> - <param name="NON_REG_OPs" value="0.01" /> - <param name="SP_ACC" value="10" /> - <param name="SFU_ACC" value="0.0082" /> - <param name="FPU_ACC" value="0.4126" /> - <param name="MEM_RD" value="0.1234" /> - <param name="MEM_WR" value="0.001" /> - <param name="MEM_PRE" value="0.001" /> - <param name="L2_RH" value="100" /> - <param name="L2_RM" value="100" /> - <param name="L2_WH" value="100" /> - <param name="L2_WM" value="42.6966" /> - <param name="NOC_A" value="100" /> - <param name="PIPE_A" value="44.8085" /> - <param name="IDLE_CORE_N" value="2.0382"/> - <param name="CONST_DYNAMICN" value="5.0005" /> - <stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period --> - <stat name="total_cycles" value="total_cycles_match_mcpat"/> - <stat name="idle_cycles" value="idle_cycles_match_mcpat"/> - <stat name="busy_cycles" value="busy_cycles_match_mcpat"/> - <!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of - virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank --> - <!-- *********************** cores ******************* --> - <component id="system.core0" name="core0"> - <!-- Core property --> - <param name="clock_rate" value="1481"/> - <param name="instruction_length" value="32"/> - <param name="opcode_width" value="9"/> - <!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller - default value is machine_bits, if not set --> - <param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO--> - <!-- inorder/OoO --> - <param name="number_hardware_threads" value="32"/> - <!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor, - it only may be more than one in SMT processors. BTB ports always equals to fetch ports since - branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> - <param name="fetch_width" value="1"/> - <!-- fetch_width determins the size of cachelines of L1 cache block --> - <param name="number_instruction_fetch_ports" value="1"/> - <param name="decode_width" value="1"/> - <!-- decode_width determins the number of ports of the - renaming table (both RAM and CAM) scheme --> - <param name="issue_width" value="2"/> - <!-- issue_width determins the number of ports of Issue window and other logic - as in the complexity effective proccessors paper; issue_width==dispatch_width --> - <param name="commit_width" value="2"/> - <!-- commit_width determins the number of ports of register files --> - <param name="fp_issue_width" value="1"/> - <param name="prediction_width" value="0"/> - <!-- number of branch instructions can be predicted simultannouesl--> - <!-- Current version of McPAT does not distinguish int and floating point pipelines - Theses parameters are reserved for future use.--> - <param name="pipelines_per_core" value="1,1"/> - <!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared--> - <param name="pipeline_depth" value="8,8"/> - <!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops --> - <!-- issue and exe unit--> - <param name="ALU_per_core" value="32"/> - <!-- contains an adder, a shifter, and a logical unit --> - <param name="MUL_per_core" value="4"/> - <!-- For MUL and Div --> - <param name="FPU_per_core" value="32"/> - <!-- buffer between IF and ID stage --> - <param name="instruction_buffer_size" value="1"/> - <!-- buffer between ID and sche/exe stage --> - <param name="decoded_stream_buffer_size" value="1"/> - <param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED--> - <!-- McPAT support 2 types of OoO cores, RS based and physical reg based--> - <param name="instruction_window_size" value="1"/> - <param name="fp_instruction_window_size" value="1"/> - <!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 --> - <param name="ROB_size" value="0"/> - <!-- each in-flight instruction has an entry in ROB --> - <!-- registers --> - <!-- SM parameters Added by Syed Gilani --> - <param name="rf_banks" value="32"/> - <param name="simd_width" value="32"/> - <param name="collector_units" value="32"/> - <param name="core_clock_ratio" value="2"/> - <param name="warp_size" value="32"/> - - <param name="archi_Regs_IRF_size" value="65536"/> - <param name="archi_Regs_FRF_size" value="32"/> - <!-- if OoO processor, phy_reg number is needed for renaming logic, - renaming logic is for both integer and floating point insts. --> - <param name="phy_Regs_IRF_size" value="32"/> - <param name="phy_Regs_FRF_size" value="32"/> - <!-- rename logic --> - <param name="rename_scheme" value="0"/> - <!-- can be RAM based(0) or CAM based(1) rename scheme - RAM-based scheme will have free list, status table; - CAM-based scheme have the valid bit in the data field of the CAM - both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions; - Detailed RAT Implementation see TR --> - <param name="register_windows_size" value="0"/> - <!-- how many windows in the windowed register file, sun processors; - no register windowing is used when this number is 0 --> - <!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha), - They will always try to exeute out-of-order though. --> - <param name="LSU_order" value="inorder"/> - <param name="store_buffer_size" value="32"/> - <!-- By default, in-order cores do not have load buffers --> - <param name="load_buffer_size" value="32"/> - <!-- number of ports refer to sustainable concurrent memory accesses --> - <param name="memory_ports" value="2"/> - <!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer - as well as the ports of Dcache which is connected to LSU --> - <!-- dual-pumped Dcache can be used to save the extra read/write ports --> - <param name="RAS_size" value="1"/> - <!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check --> - <!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops --> - <stat name="total_instructions" value="total_instructions_match_mcpat"/> - <stat name="int_instructions" value="int_instruction_match_mcpat"/> - <stat name="fp_instructions" value="flt_instruction_match_mcpat"/> - <stat name="branch_instructions" value="branch_instruction_match_mcpat"/> - <stat name="branch_mispredictions" value="0"/> - <stat name="load_instructions" value="load_instruction_match_mcpat"/> - <stat name="store_instructions" value="store_instruction_match_mcpat"/> - <stat name="committed_instructions" value="total_instructions_match_mcpat"/> - <stat name="committed_int_instructions" value="int_instruction_match_mcpat"/> - <stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/> - <stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous --> - <!-- the following cycle stats are used for heterogeneouse cores only, - please ignore them if homogeneouse cores --> - <stat name="total_cycles" value="total_cycles_match_mcpat"/> - <stat name="idle_cycles" value="idle_cycles_match_mcpat"/> - <stat name="busy_cycles" value="busy_cycles_match_mcpat"/> - <!-- instruction buffer stats --> - <!-- ROB stats, both RS and Phy based OoOs have ROB - performance simulator should capture the difference on accesses, - otherwise, McPAT has to guess based on number of commited instructions. --> - <stat name="ROB_reads" value="263886"/> - <stat name="ROB_writes" value="263886"/> - <!-- RAT accesses --> - <stat name="rename_accesses" value="263886"/> - <stat name="fp_rename_accesses" value="263886"/> - <!-- decode and rename stage use this, should be total ic - nop --> - <!-- Inst window stats --> - <stat name="inst_window_reads" value="263886"/> - <stat name="inst_window_writes" value="263886"/> - <stat name="inst_window_wakeup_accesses" value="263886"/> - <stat name="fp_inst_window_reads" value="263886"/> - <stat name="fp_inst_window_writes" value="263886"/> - <stat name="fp_inst_window_wakeup_accesses" value="263886"/> - <!-- RF accesses --> - <stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/> - <stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/> - <stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/> - <stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/> - - <!-- The following stat is for operand collector power - Added by Syed --> - <stat name="non_rf_operands" value="0"/> - - <!-- accesses to the working reg --> - <stat name="function_calls" value="0"/> - <stat name="context_switches" value="0"/> <!--not used in the McPAT --> - <!-- Number of Windowes switches (number of function calls and returns)--> - <!-- Alu stats by default, the processor has one FPU that includes the divider and - multiplier. The fpu accesses should include accesses to multiplier and divider --> - <stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/> - <stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/> - <stat name="mul_accesses" value="mul_accesses_match_mcpat"/> - <stat name="cdb_alu_accesses" value="0"/> - <stat name="cdb_mul_accesses" value="0"/> - <stat name="cdb_fpu_accesses" value="0"/> - <!-- multiple cycle accesses should be counted multiple times, - otherwise, McPAT can use internal counter for different floating point instructions - to get final accesses. But that needs detailed info for floating point inst mix --> - <!-- currently the performance simulator should - make sure all the numbers are final numbers, - including the explicit read/write accesses, - and the implicite accesses such as replacements and etc. - Future versions of McPAT may be able to reason the implicite access - based on param and stats of last level cache - The same rule applies to all cache access stats too! --> - <!-- following is AF for max power computation. - Do not change them, unless you understand them--> - <stat name="IFU_duty_cycle" value="0.25"/> - <stat name="LSU_duty_cycle" value="0.25"/> - <stat name="MemManU_I_duty_cycle" value="1"/> - <stat name="MemManU_D_duty_cycle" value="0.25"/> - <stat name="ALU_duty_cycle" value="0.9"/> - <stat name="MUL_duty_cycle" value="0.5"/> - <stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average --> - <stat name="ALU_cdb_duty_cycle" value="0.9"/> - <stat name="MUL_cdb_duty_cycle" value="0.5"/> - <stat name="FPU_cdb_duty_cycle" value="15"/> - <component id="system.core0.predictor" name="PBT"> - <!-- branch predictor; tournament predictor see Alpha implementation --> - <param name="local_predictor_size" value="10,3"/> - <param name="local_predictor_entries" value="1024"/> - <param name="global_predictor_entries" value="4096"/> - <param name="global_predictor_bits" value="2"/> - <param name="chooser_predictor_entries" value="4096"/> - <param name="chooser_predictor_bits" value="2"/> - <!-- These parameters can be combined like below in next version - <param name="load_predictor" value="10,3,1024"/> - <param name="global_predictor" value="4096,2"/> - <param name="predictor_chooser" value="4096,2"/> - --> - </component> - <component id="system.core0.itlb" name="itlb"> - <param name="number_entries" value="1"/> - <stat name="total_accesses" value="0"/> - <stat name="total_misses" value="0"/> - <stat name="conflicts" value="0"/> - <!-- there is no write requests to itlb although writes happen to itlb after miss, - which is actually a replacement --> - </component> - <component id="system.core0.icache" name="icache"> - <!-- there is no write requests to itlb although writes happen to it after miss, - which is actually a replacement --> - <param name="icache_config" value="16384,128,4,1,1,3,8,0"/> - <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> - <!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate --> - <param name="buffer_sizes" value="16, 16, 16,0"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="total_instructions_match_mcpat"/> - <stat name="read_misses" value="0"/> - <stat name="conflicts" value="0"/> - </component> - <component id="system.core0.dtlb" name="dtlb"> - <param name="number_entries" value="1"/> - <stat name="total_accesses" value="0"/> - <stat name="total_misses" value="0"/> - <stat name="conflicts" value="0"/> - </component> - <component id="system.core0.ccache" name="ccache"> - <!-- all the buffer related are optional --> - <param name="ccache_config" value="16384,64,2,1,1,3,8,0"/> - <param name="buffer_sizes" value="16, 16, 16, 0"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/> - <stat name="write_accesses" value="0"/> - <stat name="read_misses" value="ccache_read_misses_match_mcpat"/> - <stat name="write_misses" value="0"/> - <stat name="conflicts" value="0"/> - </component> - <component id="system.core0.tcache" name="tcache"> - <!-- all the buffer related are optional --> - <param name="tcache_config" value="49152,128,8,1,1,3,8,0"/> - <param name="buffer_sizes" value="16, 16, 16, 0"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/> - <stat name="write_accesses" value="0"/> - <stat name="read_misses" value="tcache_read_misses_match_mcpat"/> - <stat name="write_misses" value="0"/> - <stat name="conflicts" value="0"/> - </component> - <!--model the shared memory by mimicing dcache--> - <component id="system.core0.sharedmemory" name="sharedmemory"> - <!-- all the buffer related are optional --> - <param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/> - <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> - <param name="buffer_sizes" value="16, 16, 16, 16"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/> - <stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/> - <stat name="read_misses" value="0"/> - <stat name="write_misses" value="0"/> - <stat name="conflicts" value="0"/> - </component> - <component id="system.core0.dcache" name="dcache"> - <!-- all the buffer related are optional --> - <param name="dcache_config" value="16384,32,4,1,1,3,8,0"/> - <param name="buffer_sizes" value="16, 16, 16, 0"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="dcache_read_access_match_mcpat"/> - <stat name="write_accesses" value="dcache_write_access_match_mcpat"/> - <stat name="read_misses" value="dcache_read_miss_match_mcpat"/> - <stat name="write_misses" value="dcache_write_miss_match_mcpat"/> - <stat name="conflicts" value="0"/> - </component> - <component id="system.core0.BTB" name="BTB"> - <!-- all the buffer related are optional --> - <param name="BTB_config" value="8192,4,2,1, 1,3"/> - <!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> - </component> - </component> - <component id="system.L1Directory0" name="L1Directory0"> - <param name="Directory_type" value="0"/> - <!--0 cam based shadowed tag. 1 directory cache --> - <param name="Dir_config" value="2048,1,0,1, 4, 4,8"/> - <!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> - <param name="buffer_sizes" value="8, 8, 8, 8"/> - <!-- all the buffer related are optional --> - <param name="clockrate" value="1400"/> - <param name="ports" value="1,1,1"/> - <!-- number of r, w, and rw search ports --> - <param name="device_type" value="0"/> - <!-- altough there are multiple access types, - Performance simulator needs to cast them into reads or writes - e.g. the invalidates can be considered as writes --> - <stat name="read_accesses" value="800000"/> - <stat name="write_accesses" value="27276"/> - <stat name="read_misses" value="1632"/> - <stat name="write_misses" value="183"/> - <stat name="conflicts" value="20"/> - <stat name="duty_cycle" value="0.45"/> - </component> - <component id="system.L2Directory0" name="L2Directory0"> - <param name="Directory_type" value="1"/> - <!--0 cam based shadowed tag. 1 directory cache --> - <param name="Dir_config" value="1048576,16,16,1,2, 100"/> - <!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> - <param name="buffer_sizes" value="8, 8, 8, 8"/> - <!-- all the buffer related are optional --> - <param name="clockrate" value="1400"/> - <param name="ports" value="1,1,1"/> - <!-- number of r, w, and rw search ports --> - <param name="device_type" value="0"/> - <!-- altough there are multiple access types, - Performance simulator needs to cast them into reads or writes - e.g. the invalidates can be considered as writes --> - <stat name="read_accesses" value="0"/> - <stat name="write_accesses" value="0"/> - <stat name="read_misses" value="0"/> - <stat name="write_misses" value="0"/> - <stat name="conflicts" value="0"/> - <stat name="duty_cycle" value="0.45"/> - </component> - <component id="system.L20" name="L20"> - <!-- all the buffer related are optional --> - <param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/> - <!-- consider 4-way bank interleaving for Niagara 1 --> - <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> - <param name="buffer_sizes" value="16, 16, 16, 16"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <param name="clockrate" value="2962"/> - <param name="ports" value="1,1,1"/> - <!-- number of r, w, and rw ports --> - <param name="device_type" value="0"/> - <stat name="read_accesses" value="200000"/> - <stat name="write_accesses" value="0"/> - <stat name="read_misses" value="0"/> - <stat name="write_misses" value="0"/> - <stat name="conflicts" value="0"/> - <stat name="duty_cycle" value="0.5"/> - </component> - -<!--**********************************************************************--> -<component id="system.L30" name="L30"> - <param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/> - <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> - <param name="clockrate" value="3500"/> - <param name="ports" value="1,1,1"/> - <!-- number of r, w, and rw ports --> - <param name="device_type" value="0"/> - <param name="buffer_sizes" value="16, 16, 16, 16"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="58824"/> - <stat name="write_accesses" value="27276"/> - <stat name="read_misses" value="1632"/> - <stat name="write_misses" value="183"/> - <stat name="conflicts" value="0"/> - <stat name="duty_cycle" value="0.35"/> - </component> - - -<!--**********************************************************************--> - <component id="system.NoC0" name="noc0"> - <param name="clockrate" value="700"/> - <param name="type" value="1"/> - <!-- 1 NoC, O bus --> - <param name="horizontal_nodes" value="2"/> - <param name="vertical_nodes" value="1"/> - <param name="has_global_link" value="0"/> - <!-- 1 has global link, 0 does not have global link --> - <param name="link_throughput" value="1"/><!--w.r.t clock --> - <param name="link_latency" value="1"/><!--w.r.t clock --> - <!-- througput >= latency --> - <!-- Router architecture --> - <param name="input_ports" value="6"/> - <param name="output_ports" value="6"/> - <param name="virtual_channel_per_port" value="1"/> - <!-- input buffer; in classic routers only input ports need buffers --> - <param name="flit_bits" value="32"/> - <param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs--> - <param name="chip_coverage" value="1"/> - <!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 --> - <stat name="total_accesses" value="0"/> - <!-- This is the number of total accesses within the whole network not for each router --> - <stat name="duty_cycle" value="0.6"/> - </component> -<!--**********************************************************************--> -<!--**********************************************************************--> - - <component id="system.mem" name="mem"> - <!-- Main memory property --> - <param name="mem_tech_node" value="23"/> - <param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB --> - <param name="peak_transfer_rate" value="3200"/><!--MB/S--> - <param name="internal_prefetch_of_DRAM_chip" value="4"/> - <!-- 2 for DDR, 4 for DDR2, 8 for DDR3...--> - <!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property --> - <!-- above numbers can be easily found from Wikipedia --> - <param name="capacity_per_channel" value="4096"/> <!-- MB --> - <!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank - Current McPAT assumes single DIMMs are used.--> - <param name="number_ranks" value="2"/> - <param name="num_banks_of_DRAM_chip" value="6"/> - <param name="Block_width_of_DRAM_chip" value="64"/> <!-- B --> - <param name="output_width_of_DRAM_chip" value="8"/> - <!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip--> - <!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip--> - <param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 --> - <param name="burstlength_of_DRAM_chip" value="8"/> - <stat name="memory_accesses" value="1052"/> - <stat name="memory_reads" value="1052"/> - <stat name="memory_writes" value="1052"/> - </component> - <component id="system.mc" name="mc"> - <!-- Memeory controllers are for DDR(2,3...) DIMMs --> - <!-- current version of McPAT uses published values for base parameters of memory controller - improvments on MC will be added in later versions. --> - <param name="type" value="0"/> <!-- 1: low power; 0 high performance --> - <param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> - <param name="peak_transfer_rate" value="29568"/><!--MB/S Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs --> - <param name="block_size" value="64"/><!--B--> - <param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers --> - <!-- current McPAT only supports homogeneous memory controllers --> - <param name="memory_channels_per_mc" value="2"/> - <param name="number_ranks" value="1"/> - <param name="withPHY" value="0"/> - <!-- # of ranks of each channel--> - <param name="req_window_size_per_channel" value="16"/> - <param name="IO_buffer_size_per_channel" value="16"/> - <param name="databus_width" value="32"/> - <param name="addressbus_width" value="32"/> - <param name="PRT_entries" value="32"/> - <!-- # of empirical DRAM model parameter --> - <param name="dram_cmd_coeff" value="0"/> - <param name="dram_act_coeff" value="0"/> - <param name="dram_nop_coeff" value="0"/> - <param name="dram_activity_coeff" value="0"/> - <param name="dram_pre_coeff" value="3.8475e-8f"/> - <param name="dram_rd_coeff" value="7.74707143e-8f"/> - <param name="dram_wr_coeff" value="3.54664286e-8f"/> - <param name="dram_req_coeff" value="0"/> - <param name="dram_const_coeff" value="0"/> - - <!-- McPAT will add the control bus width to the addressbus width automatically --> - <stat name="memory_accesses" value="memory_accesses_match_mcpat"/> - <stat name="memory_reads" value="memory_reads_match_mcpat"/> - <stat name="memory_writes" value="memory_writes_match_mcpat"/> - <!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate - the average power per MC or per channel. This is sufficent for most application. - Further trackdown can be easily added in later versions. --> - </component> -<!--**********************************************************************--> - <component id="system.niu" name="niu"> - <!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller --> - <!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. - the low bound of clock rate of a 10Gb MAC is 150Mhz --> - <param name="type" value="0"/> <!-- 1: low power; 0 high performance --> - <param name="clockrate" value="350"/> - <param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port --> - <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 --> - <stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth --> - <!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate - the average power per nic or per channel. This is sufficent for most application. --> - </component> -<!--**********************************************************************--> - <component id="system.pcie" name="pcie"> - <!-- On chip PCIe controller, including Phy--> - <!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. - the low bound of clock rate of a PCIe per lane logic is 120Mhz --> - <param name="type" value="0"/> <!-- 1: low power; 0 high performance --> - <param name="withPHY" value="1"/> - <param name="clockrate" value="350"/> - <param name="number_units" value="0"/> - <param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 --> - <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 --> - <stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth --> - <!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate - the average power per pcie controller or per channel. This is sufficent for most application. --> - </component> -<!--**********************************************************************--> - <component id="system.flashc" name="flashc"> - <param name="number_flashcs" value="0"/> - <param name="type" value="1"/> <!-- 1: low power; 0 high performance --> - <param name="withPHY" value="1"/> - <param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S --> - <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 --> - <stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth --> - <!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate - the average power per fc or per channel. This is sufficent for most application --> - </component> -<!--**********************************************************************--> - - </component> -</component> diff --git a/cuda-kernels/scripts b/cuda-kernels/scripts deleted file mode 100755 index a24fb72..0000000 --- a/cuda-kernels/scripts +++ /dev/null @@ -1,139 +0,0 @@ -#!/bin/bash -nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o vp4_16 v4p_genericMatrixMultiply.cu -DSIZE=16 -nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o vp4_32 v4p_genericMatrixMultiply.cu -DSIZE=32 -nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o vp4_64 v4p_genericMatrixMultiply.cu -DSIZE=64 -nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o vp4_128 v4p_genericMatrixMultiply.cu -DSIZE=128 -nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o vp4_256 v4p_genericMatrixMultiply.cu -DSIZE=256 -./vp4_16>vp4_log16 -./vp4_32>vp4_log32 -./vp4_64>vp4_log64 -./vp4_128>vp4_log128 -./vp4_256>vp4_log256 - -#grep "kernel_name.*convertInt32To" -A 589 vp4_log16 >vp4_16_summary -#grep "kernel_name.*convertInt32To" -A 589 vp4_log32 >vp4_32_summary -#grep "kernel_name.*convertInt32To" -A 589 vp4_log64 >vp4_64_summary -#grep "kernel_name.*convertInt32To" -A 589 vp4_log128 >vp4_128_summary -#grep "kernel_name.*convertInt32To" -A 589 vp4_log256 >vp4_256_summary -###grep "kernel_name.*vp_example" -A 589 vp4_log16 >>vp4_16_summary -###grep "kernel_name.*vp_example" -A 589 vp4_log32 >>vp4_32_summary -###grep "kernel_name.*vp_example" -A 589 vp4_log64 >>vp4_64_summary -#grep "kernel_name.*vp_example" -A 589 vp4_log128 >>vp4_128_summary -#grep "kernel_name.*vp_example" -A 589 vp4_log256 >>vp4_256_summary - - -nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o vp8_16 v8p_genericMatrixMultiply.cu -DSIZE=16 -nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o vp8_32 v8p_genericMatrixMultiply.cu -DSIZE=32 -nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o vp8_64 v8p_genericMatrixMultiply.cu -DSIZE=64 -nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o vp8_128 v8p_genericMatrixMultiply.cu -DSIZE=128 -nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o vp8_256 v8p_genericMatrixMultiply.cu -DSIZE=256 -./vp8_16 >vp8_log16 -./vp8_32 >vp8_log32 -./vp8_64 >vp8_log64 -./vp8_128>vp8_log128 -./vp8_256>vp8_log256 - -#grep "kernel_name.*convertInt32To" -A 589 vp8_log16 >vp8_16_summary -#grep "kernel_name.*convertInt32To" -A 589 vp8_log32 >vp8_32_summary -#grep "kernel_name.*convertInt32To" -A 589 vp8_log64 >vp8_64_summary -#grep "kernel_name.*convertInt32To" -A 589 vp8_log128 >vp8_128_summary -#grep "kernel_name.*convertInt32To" -A 589 vp8_log256 >vp8_256_summary -##grep "kernel_name.*vp_example" -A 589 vp8_log16 >>vp8_16_summary -##grep "kernel_name.*vp_example" -A 589 vp8_log32 >>vp8_32_summary -##grep "kernel_name.*vp_example" -A 589 vp8_log64 >>vp8_64_summary -#grep "kernel_name.*vp_example" -A 589 vp8_log128 >>vp8_128_summary -#grep "kernel_name.*vp_example" -A 589 vp8_log256 >>vp8_256_summary - -nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o vp16_16 v16p_genericMatrixMultiply.cu -DSIZE=16 -nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o vp16_32 v16p_genericMatrixMultiply.cu -DSIZE=32 -nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o vp16_64 v16p_genericMatrixMultiply.cu -DSIZE=64 -nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o vp16_128 v16p_genericMatrixMultiply.cu -DSIZE=128 -nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o vp16_256 v16p_genericMatrixMultiply.cu -DSIZE=256 -./vp16_16>vp16_log16 -./vp16_32>vp16_log32 -./vp16_64>vp16_log64 -./vp16_128>vp16_log128 -./vp16_256>vp16_log256 - -#grep "kernel_name.*convertInt32To" -A 589 vp16_log16 >vp16_16_summary -#grep "kernel_name.*convertInt32To" -A 589 vp16_log32 >vp16_32_summary -#grep "kernel_name.*convertInt32To" -A 589 vp16_log64 >vp16_64_summary -#grep "kernel_name.*convertInt32To" -A 589 vp16_log128 >vp16_128_summary -#grep "kernel_name.*convertInt32To" -A 589 vp16_log256 >vp16_256_summary -##grep "kernel_name.*vp_example" -A 589 vp16_log16 >>vp16_16_summary -##grep "kernel_name.*vp_example" -A 589 vp16_log32 >>vp16_32_summary -##grep "kernel_name.*vp_example" -A 589 vp16_log64 >>vp16_64_summary -#grep "kernel_name.*vp_example" -A 589 vp16_log128 >>vp16_128_summary -#grep "kernel_name.*vp_example" -A 589 vp16_log256 >>vp16_256_summary - -###sed -n '/bind.*to.*kernel.*vp_example/,$p' vp4_log16 > kernel_log_vp4_log16 -###sed -n '/bind.*to.*kernel.*vp_example/,$p' vp4_log32 > kernel_log_vp4_log32 -###sed -n '/bind.*to.*kernel.*vp_example/,$p' vp4_log64 > kernel_log_vp4_log64 -####sed -n '/bind.*to.*kernel.*vp_example/,$p' vp4_log128 > kernel_log_vp4_log128 -####sed -n '/bind.*to.*kernel.*vp_example/,$p' vp4_log256 > kernel_log_vp4_log256 -###sed -n '/bind.*to.*kernel.*vp_example/,$p' vp8_log16 > kernel_log_vp8_log16 -###sed -n '/bind.*to.*kernel.*vp_example/,$p' vp8_log32 > kernel_log_vp8_log32 -###sed -n '/bind.*to.*kernel.*vp_example/,$p' vp8_log64 > kernel_log_vp8_log64 -####sed -n '/bind.*to.*kernel.*vp_example/,$p' vp8_log128 > kernel_log_vp8_log128 -####sed -n '/bind.*to.*kernel.*vp_example/,$p' vp8_log256 > kernel_log_vp8_log256 -###sed -n '/bind.*to.*kernel.*vp_example/,$p' vp16_log16 > kernel_log_vp16_log16 -###sed -n '/bind.*to.*kernel.*vp_example/,$p' vp16_log32 > kernel_log_vp16_log32 -###sed -n '/bind.*to.*kernel.*vp_example/,$p' vp16_log64 > kernel_log_vp16_log64 -####sed -n '/bind.*to.*kernel.*vp_example/,$p' vp16_log128 > kernel_log_vp16_log128 -####sed -n '/bind.*to.*kernel.*vp_example/,$p' vp16_log256 > kernel_log_vp16_log256 -### -###grep memtocore:Icnt kernel_log_vp4_log16>memtocore_vp4_log16 -###grep coretomem:Icnt kernel_log_vp4_log16>coretomem_vp4_log16 -###grep MEM_TXN kernel_log_vp4_log16> gen_mem_vp4_log16 -###grep memtocore:Icnt kernel_log_vp4_log32>memtocore_vp4_log32 -###grep coretomem:Icnt kernel_log_vp4_log32>coretomem_vp4_log32 -###grep MEM_TXN kernel_log_vp4_log32> gen_mem_vp4_log32 -###grep memtocore:Icnt kernel_log_vp4_log64>memtocore_vp4_log64 -###grep coretomem:Icnt kernel_log_vp4_log64>coretomem_vp4_log64 -###grep MEM_TXN kernel_log_vp4_log64> gen_mem_vp4_log64 -####grep memtocore:Icnt kernel_log_vp4_log128>memtocore_vp4_log128 -####grep coretomem:Icnt kernel_log_vp4_log128>coretomem_vp4_log128 -####grep MEM_TXN kernel_log_vp4_log128> gen_mem_vp4_log128 -####grep memtocore:Icnt kernel_log_vp4_log256>memtocore_vp4_log256 -####grep coretomem:Icnt kernel_log_vp4_log256>coretomem_vp4_log256 -####grep MEM_TXN kernel_log_vp4_log256> gen_mem_vp4_log256 -### -###grep memtocore:Icnt kernel_log_vp8_log16>memtocore_vp8_log16 -###grep coretomem:Icnt kernel_log_vp8_log16>coretomem_vp8_log16 -###grep MEM_TXN kernel_log_vp8_log16> gen_mem_vp8_log16 -###grep memtocore:Icnt kernel_log_vp8_log32>memtocore_vp8_log32 -###grep coretomem:Icnt kernel_log_vp8_log32>coretomem_vp8_log32 -###grep MEM_TXN kernel_log_vp8_log32> gen_mem_vp8_log32 -###grep memtocore:Icnt kernel_log_vp8_log64>memtocore_vp8_log64 -###grep coretomem:Icnt kernel_log_vp8_log64>coretomem_vp8_log64 -###grep MEM_TXN kernel_log_vp8_log64> gen_mem_vp8_log64 -####grep memtocore:Icnt kernel_log_vp8_log128>memtocore_vp8_log128 -####grep coretomem:Icnt kernel_log_vp8_log128>coretomem_vp8_log128 -####grep MEM_TXN kernel_log_vp8_log128> gen_mem_vp8_log128 -####grep memtocore:Icnt kernel_log_vp8_log256>memtocore_vp8_log256 -####grep coretomem:Icnt kernel_log_vp8_log256>coretomem_vp8_log256 -####grep MEM_TXN kernel_log_vp8_log256> gen_mem_vp8_log256 -### -###grep memtocore:Icnt kernel_log_vp16_log16>memtocore_vp16_log16 -###grep coretomem:Icnt kernel_log_vp16_log16>coretomem_vp16_log16 -###grep MEM_TXN kernel_log_vp16_log16> gen_mem_vp16_log16 -###grep memtocore:Icnt kernel_log_vp16_log32>memtocore_vp16_log32 -###grep coretomem:Icnt kernel_log_vp16_log32>coretomem_vp16_log32 -###grep MEM_TXN kernel_log_vp16_log32> gen_mem_vp16_log32 -###grep memtocore:Icnt kernel_log_vp16_log64>memtocore_vp16_log64 -###grep coretomem:Icnt kernel_log_vp16_log64>coretomem_vp16_log64 -###grep MEM_TXN kernel_log_vp16_log64> gen_mem_vp16_log64 -####grep memtocore:Icnt kernel_log_vp16_log128>memtocore_vp16_log128 -####grep coretomem:Icnt kernel_log_vp16_log128>coretomem_vp16_log128 -####grep MEM_TXN kernel_log_vp16_log128> gen_mem_vp16_log128 -####grep memtocore:Icnt kernel_log_vp16_log256>memtocore_vp16_log256 -####grep coretomem:Icnt kernel_log_vp16_log256>coretomem_vp16_log256 -####grep MEM_TXN kernel_log_vp16_log256> gen_mem_vp16_log256 -### -###mv kernel_* MemTraffic/ -###mv memtocore* MemTraffic/ -###mv coretomem* MemTraffic/ -###mv gen_mem* MemTraffic/ -### -###mv vp* VPlog/ -###make clean diff --git a/cuda-kernels/tensor_core.cu b/cuda-kernels/tensor_core.cu deleted file mode 100644 index b7090c4..0000000 --- a/cuda-kernels/tensor_core.cu +++ /dev/null @@ -1,245 +0,0 @@ -/* Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of NVIDIA CORPORATION nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY - * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <stdio.h> - -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - - - - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (16) -#define MATRIX_N (16) -#define MATRIX_K (16) - - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - - -// Performs an MxNxK GEMM (C=alpha*A*B + beta*C) assuming: -// 1) Matrices are packed in memory. -// 2) M, N and K are multiples of 16. -// 3) Neither A nor B are transposed. -// Note: This is NOT a high performance example but is for demonstration purposes only -// For a high performance code please use the GEMM provided in cuBLAS. -__global__ void wmma_example(half *a, half *b, float *c, int M, int N, int K, float alpha, float beta) { - unsigned int start_time=0,end_time=0; - // Leading dimensions. Packed with no transpositions. - start_time=clock(); - int lda = M; - int ldb = K; - int ldc = M; - - // Tile using a 2D grid/ - int warpM = (blockIdx.x * blockDim.x + threadIdx.x) / warpSize; - int warpN = (blockIdx.y * blockDim.y + threadIdx.y); - - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> acc_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - wmma::fill_fragment(c_frag, 0.0f); - - int i=0; - int aRow = warpM * WMMA_M; - int bCol = warpN * WMMA_N; - int aCol = i; - int bRow = i; - - - // Bounds checking - if (aRow < M && aCol < K && bRow < K && bCol < N) { - wmma::load_matrix_sync(a_frag, a+aRow+aCol*lda, lda); - wmma::load_matrix_sync(b_frag, b+bRow*ldb+bCol, ldb); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - //wmma::mma_sync(acc_frag, a_frag, b_frag, acc_frag); - } - int cRow = warpM * WMMA_M; - int cCol = warpN * WMMA_N; - wmma::store_matrix_sync(c + cRow + cCol * ldc, c_frag, ldc, wmma::mem_col_major); - end_time=clock(); - printf("clock=%d",end_time-start_time); -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -int main(int argc, char* argv[]) { - float *a_fp32; - float *b_fp32; - half *a_fp16; - half *b_fp16; - - float *c; - float *c_cublas; - float *c_wmma; - - float *c_host_cublas; - float *c_host_wmma; - float *a_host_wmma; - float *b_host_wmma; - float *c_init_host_wmma; - - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - - - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - - cudaErrCheck(cudaMalloc((void**)&a_fp32, MATRIX_M * MATRIX_K * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&b_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&a_fp16, MATRIX_M * MATRIX_K * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&b_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - - cudaErrCheck(cudaMalloc((void**)&c, MATRIX_M * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&c_wmma, MATRIX_M * MATRIX_N * sizeof(float))); - - c_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - c_init_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - a_host_wmma = (float*)malloc(MATRIX_M * MATRIX_K * sizeof(float)); - b_host_wmma = (float*)malloc(MATRIX_K * MATRIX_N * sizeof(float)); - -// printf("a_fp32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]=(m*MATRIX_K+n)%10; - } - //printf(";\n"); - } - - // printf("b_fp32\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]=(m*MATRIX_N+n)%10; - // printf("%f ",b_host_wmma[m*MATRIX_N+n]); - } - // printf(";\n"); - } - cudaErrCheck(cudaMemcpy(a_fp32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_fp32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - - // curand doesn't currently support fp16 so we generate in fp32 and convert to fp16. - convertFp32ToFp16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_fp16, a_fp32, MATRIX_M * MATRIX_K); - convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_init_host_wmma[m*MATRIX_N+n]=(m*MATRIX_M+n)%10; - } - } - cudaErrCheck(cudaMemcpy(c, c_init_host_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_wmma, c, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToDevice)); - - float alpha = 1.0f; - float beta = 1.0f; - - - printf("\nM = %d, N = %d, K = %d. alpha = %f, beta = %f\n\n", MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta); - - // First: using WMMA - dim3 gridDim; - dim3 blockDim; - - // blockDim.x must be a multple of warpSize - // 128x4 means we have 16 warps and a block computes a 64x64 output tile - blockDim.x = 128; - blockDim.y = 4; - - gridDim.x = (MATRIX_M + (WMMA_M * blockDim.x / 32 - 1)) / (WMMA_M * blockDim.x / 32); - gridDim.y = (MATRIX_N + WMMA_N * blockDim.y - 1) / (WMMA_N * blockDim.y); - - printf("Running with wmma...\n"); - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example <<< 1, 32>>> (a_fp16, b_fp16, c_wmma, MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta); - // wmma_example <<< gridDim, blockDim >>> (a_fp16, b_fp16, c_wmma, MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta); - cudaErrCheck(cudaEventRecord(stopWMMA)); - - - - - // Error checking - printf("\nChecking results...\n"); - cudaErrCheck(cudaMemcpy(c_host_wmma, c_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - // printf("c_host\n"); - // for(int m=0;m<MATRIX_M;m++){ - //for(int n=0;n<MATRIX_N;n++){ - //printf("%f ",c_host_wmma[m*MATRIX_N+n]); - //} - //printf(";\n"); - // } - - float wmmaTime; - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma took %fms\n", wmmaTime); - //printf("Clock=%d",stopWMMA-startWMMA); - printf("\nFor a faster code using wmma you should check out the cudaTensorCoreGemm sample in the CUDA Toolkit.\nThis code was written as a demo only!\n\n"); - - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - - - cudaErrCheck(cudaFree(a_fp32)); - cudaErrCheck(cudaFree(b_fp32)); - cudaErrCheck(cudaFree(a_fp16)); - cudaErrCheck(cudaFree(b_fp16)); - - cudaErrCheck(cudaFree(c)); - cudaErrCheck(cudaFree(c_wmma)); - - free(c_host_wmma); - - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuda-kernels/tensor_core_ptx b/cuda-kernels/tensor_core_ptx deleted file mode 100644 index 36074cb..0000000 --- a/cuda-kernels/tensor_core_ptx +++ /dev/null @@ -1,171 +0,0 @@ -// -// Generated by NVIDIA NVVM Compiler -// -// Compiler Build ID: CL-22781540 -// Cuda compilation tools, release 9.0, V9.0.176 -// Based on LLVM 3.4svn -// - -.version 6.0 -.target sm_70 -.address_size 64 - - // .globl _Z12wmma_exampleP6__halfS0_Pfiiiff -.extern .func (.param .b32 func_retval0) vprintf -( - .param .b64 vprintf_param_0, - .param .b64 vprintf_param_1 -) -; -.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0}; - -.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff( - .param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0, - .param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1, - .param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2, - .param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3, - .param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4, - .param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5, - .param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6, - .param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7 -) -{ - .local .align 8 .b8 __local_depot0[8]; - .reg .b64 %SP; - .reg .b64 %SPL; - .reg .pred %p<6>; - .reg .f32 %f<34>; - .reg .b32 %r<38>; - .reg .b64 %rd<18>; - - - mov.u64 %rd17, __local_depot0; - cvta.local.u64 %SP, %rd17; - ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0]; - ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1]; - ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2]; - ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3]; - ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4]; - ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5]; - // inline asm - mov.u32 %r6, %clock; - // inline asm - mov.u32 %r8, %ntid.x; - mov.u32 %r9, %ctaid.x; - mov.u32 %r10, %tid.x; - mad.lo.s32 %r11, %r8, %r9, %r10; - mov.u32 %r12, WARP_SZ; - div.u32 %r13, %r11, %r12; - mov.u32 %r14, %ntid.y; - mov.u32 %r15, %ctaid.y; - mov.u32 %r16, %tid.y; - mad.lo.s32 %r17, %r14, %r15, %r16; - shl.b32 %r2, %r13, 4; - shl.b32 %r3, %r17, 4; - setp.lt.s32 %p1, %r2, %r4; - setp.gt.s32 %p2, %r5, 0; - and.pred %p3, %p1, %p2; - setp.lt.s32 %p4, %r3, %r7; - and.pred %p5, %p3, %p4; - mov.f32 %f26, 0f00000000; - mov.f32 %f27, %f26; - mov.f32 %f28, %f26; - mov.f32 %f29, %f26; - mov.f32 %f30, %f26; - mov.f32 %f31, %f26; - mov.f32 %f32, %f26; - mov.f32 %f33, %f26; - @!%p5 bra BB0_2; - bra.uni BB0_1; - -BB0_1: - mul.wide.s32 %rd4, %r2, 2; - add.s64 %rd5, %rd1, %rd4; - wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4; - mul.wide.s32 %rd6, %r3, 2; - add.s64 %rd7, %rd2, %rd6; - wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5; - mov.f32 %f25, 0f00000000; - wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25}; - -BB0_2: - add.u64 %rd8, %SP, 0; - cvta.to.local.u64 %rd9, %rd8; - mul.lo.s32 %r35, %r3, %r4; - cvt.s64.s32 %rd10, %r35; - cvt.s64.s32 %rd11, %r2; - add.s64 %rd12, %rd10, %rd11; - shl.b64 %rd13, %rd12, 2; - add.s64 %rd14, %rd3, %rd13; - wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4; - // inline asm - mov.u32 %r34, %clock; - // inline asm - sub.s32 %r36, %r34, %r6; - st.local.u32 [%rd9], %r36; - mov.u64 %rd15, $str; - cvta.global.u64 %rd16, %rd15; - // Callseq Start 0 - { - .reg .b32 temp_param_reg; - // <end>} - .param .b64 param0; - st.param.b64 [param0+0], %rd16; - .param .b64 param1; - st.param.b64 [param1+0], %rd8; - .param .b32 retval0; - call.uni (retval0), - vprintf, - ( - param0, - param1 - ); - ld.param.b32 %r37, [retval0+0]; - - //{ - }// Callseq End 0 - ret; -} - - // .globl _Z17convertFp32ToFp16P6__halfPfi -.visible .entry _Z17convertFp32ToFp16P6__halfPfi( - .param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0, - .param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1, - .param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2 -) -{ - .reg .pred %p<2>; - .reg .b16 %rs<2>; - .reg .f32 %f<2>; - .reg .b32 %r<6>; - .reg .b64 %rd<9>; - - - ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0]; - ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1]; - ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2]; - mov.u32 %r3, %ntid.x; - mov.u32 %r4, %ctaid.x; - mov.u32 %r5, %tid.x; - mad.lo.s32 %r1, %r4, %r3, %r5; - setp.ge.s32 %p1, %r1, %r2; - @%p1 bra BB1_2; - - cvta.to.global.u64 %rd3, %rd2; - mul.wide.s32 %rd4, %r1, 4; - add.s64 %rd5, %rd3, %rd4; - ld.global.f32 %f1, [%rd5]; - // inline asm - { cvt.rn.f16.f32 %rs1, %f1;} - - // inline asm - cvta.to.global.u64 %rd6, %rd1; - mul.wide.s32 %rd7, %r1, 2; - add.s64 %rd8, %rd6, %rd7; - st.global.u16 [%rd8], %rs1; - -BB1_2: - ret; -} - - diff --git a/cuda-kernels/tensorcore_layout_fp16_fp16.cu b/cuda-kernels/tensorcore_layout_fp16_fp16.cu deleted file mode 100644 index c90874a..0000000 --- a/cuda-kernels/tensorcore_layout_fp16_fp16.cu +++ /dev/null @@ -1,892 +0,0 @@ -#include <stdio.h> -#include <curand.h> -#include <stdlib.h> -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - -#define curandErrCheck(stat) { curandErrCheck_((stat), __FILE__, __LINE__); } -void curandErrCheck_(curandStatus_t stat, const char *file, int line) { - if (stat != CURAND_STATUS_SUCCESS) { - fprintf(stderr, "cuRand Error: %d %s %d\n", stat, file, line); - } -} - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (16) -#define MATRIX_N (16) -#define MATRIX_K (16) - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - -//wmma_example_dLayout_cLayout_bLayout_aLayout - -__global__ void wmma_example_col_col_col_col(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_col_col_row(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_col_row_col(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_col_row_row(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_row_col_col(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_row_col_row(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_row_row_col(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_row_row_row(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_row_col_col_col(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_col_col_row(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_col_row_col(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_col_row_row(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_row_col_col(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_row_col_row(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_row_row_col(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_row_row_row(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} -__global__ void convertFp16ToFp32 (float *out, half *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -int main(int argc, char* argv[]) { - float *a_fp32; - float *b_fp32; - float *c_fp32; - float *d_fp32; - - half *a_fp16; - half *b_fp16; - half *c_fp16; - half *d_fp16; - - float *a_host_wmma; - float *b_host_wmma; - float *c_host_wmma; - float *d_host_wmma; - float *d_cal_host_wmma; - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - - float wmmaTime; - - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - cudaErrCheck(cudaMalloc((void**)&a_fp32, MATRIX_M * MATRIX_K * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&b_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&c_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&d_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&a_fp16, MATRIX_M * MATRIX_K * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&b_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&c_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&d_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - - - a_host_wmma = (float*)malloc(MATRIX_M * MATRIX_K * sizeof(float)); - b_host_wmma = (float*)malloc(MATRIX_K * MATRIX_N * sizeof(float)); - c_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_cal_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - - printf("a_fp32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]=((rand()%9)/3.0); - printf("%f ",a_host_wmma[m*MATRIX_K+n]); - } - printf(";\n"); - } - - printf("b_fp32\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]=((rand()%9)/3.0); - printf("%f ",b_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - - printf("c_fp32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_host_wmma[m*MATRIX_N+n]=((rand()%9)/3.0); - d_cal_host_wmma[m*MATRIX_N+n]=0; - printf("%f ",c_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - - - cudaErrCheck(cudaMemcpy(a_fp32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_fp32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_fp32,c_host_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - - convertFp32ToFp16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_fp16, a_fp32, MATRIX_M * MATRIX_K); - convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); - convertFp32ToFp16 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (c_fp16, c_fp32, MATRIX_K * MATRIX_N); - - printf("\nM = %d, N = %d, K = %d. \n", MATRIX_M, MATRIX_N, MATRIX_K); - - int suc=1; - printf("Running with wmma...\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_col_col_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:1 took %fms\n", wmmaTime); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[n*MATRIX_N+m]; - } - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_COL_COL_COL_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_col_col_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:2 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_COL_COL_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_col_row_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:3 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_COL_ROW_COL_COMPLETED_SUCCESSFULLY\n"); - - - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_col_row_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:4 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_COL_ROW_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_row_col_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:5 took %fms\n", wmmaTime); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_ROW_COL_COL_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_row_col_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:6 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_ROW_COL_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_row_row_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:7 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_ROW_ROW_COL_COMPLETED_SUCCESSFULLY\n"); - - - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_row_row_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:8 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_ROW_ROW_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_col_col_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:9 took %fms\n", wmmaTime); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[n*MATRIX_N+m]; - } - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_COL_COL_COL_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_col_col_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:10 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_COL_COL_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_col_row_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:11 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_COL_ROW_COL_COMPLETED_SUCCESSFULLY\n"); - - - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_col_row_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:12 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_COL_ROW_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_row_col_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:13 took %fms\n", wmmaTime); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_ROW_COL_COL_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_row_col_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:14 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_ROW_COL_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_row_row_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:15 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_ROW_ROW_COL_COMPLETED_SUCCESSFULLY\n"); - - - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_row_row_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:16 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_ROW_ROW_ROW_COMPLETED_SUCCESSFULLY\n"); - - - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - - cudaErrCheck(cudaFree(a_fp32)); - cudaErrCheck(cudaFree(b_fp32)); - cudaErrCheck(cudaFree(c_fp32)); - cudaErrCheck(cudaFree(d_fp32)); - cudaErrCheck(cudaFree(a_fp16)); - cudaErrCheck(cudaFree(b_fp16)); - cudaErrCheck(cudaFree(c_fp16)); - cudaErrCheck(cudaFree(d_fp16)); - - free(a_host_wmma); - free(b_host_wmma); - free(c_host_wmma); - free(d_host_wmma); - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuda-kernels/tensorcore_layout_fp16_fp32.cu b/cuda-kernels/tensorcore_layout_fp16_fp32.cu deleted file mode 100644 index cd0bdf7..0000000 --- a/cuda-kernels/tensorcore_layout_fp16_fp32.cu +++ /dev/null @@ -1,892 +0,0 @@ -#include <stdio.h> -#include <curand.h> -#include <stdlib.h> -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - -#define curandErrCheck(stat) { curandErrCheck_((stat), __FILE__, __LINE__); } -void curandErrCheck_(curandStatus_t stat, const char *file, int line) { - if (stat != CURAND_STATUS_SUCCESS) { - fprintf(stderr, "cuRand Error: %d %s %d\n", stat, file, line); - } -} - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (16) -#define MATRIX_N (16) -#define MATRIX_K (16) - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - -//wmma_example_dLayout_cLayout_bLayout_aLayout - -__global__ void wmma_example_col_col_col_col(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_col_col_row(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_col_row_col(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_col_row_row(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_row_col_col(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_row_col_row(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_row_row_col(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_row_row_row(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_row_col_col_col(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_col_col_row(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_col_row_col(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_col_row_row(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_row_col_col(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_row_col_row(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_row_row_col(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_row_row_row(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(d_frag,a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_row_major); -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} -__global__ void convertFp16ToFp32 (float *out, half *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -int main(int argc, char* argv[]) { - float *a_fp32; - float *b_fp32; - float *c_fp32; - float *d_fp32; - - half *a_fp16; - half *b_fp16; - half *c_fp16; - half *d_fp16; - - float *a_host_wmma; - float *b_host_wmma; - float *c_host_wmma; - float *d_host_wmma; - float *d_cal_host_wmma; - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - - float wmmaTime; - - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - cudaErrCheck(cudaMalloc((void**)&a_fp32, MATRIX_M * MATRIX_K * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&b_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&c_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&d_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&a_fp16, MATRIX_M * MATRIX_K * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&b_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&c_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&d_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - - - a_host_wmma = (float*)malloc(MATRIX_M * MATRIX_K * sizeof(float)); - b_host_wmma = (float*)malloc(MATRIX_K * MATRIX_N * sizeof(float)); - c_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_cal_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - - printf("a_fp32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]=((rand()%9)/3.0); - printf("%f ",a_host_wmma[m*MATRIX_K+n]); - } - printf(";\n"); - } - - printf("b_fp32\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]=((rand()%9)/3.0); - printf("%f ",b_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - - printf("c_fp32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_host_wmma[m*MATRIX_N+n]=((rand()%9)/3.0); - d_cal_host_wmma[m*MATRIX_N+n]=0; - printf("%f ",c_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - - - cudaErrCheck(cudaMemcpy(a_fp32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_fp32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_fp32,c_host_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - - convertFp32ToFp16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_fp16, a_fp32, MATRIX_M * MATRIX_K); - convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); - convertFp32ToFp16 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (c_fp16, c_fp32, MATRIX_K * MATRIX_N); - - printf("\nM = %d, N = %d, K = %d. \n", MATRIX_M, MATRIX_N, MATRIX_K); - - int suc=1; - printf("Running with wmma...\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_col_col_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:1 took %fms\n", wmmaTime); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[n*MATRIX_N+m]; - } - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_COL_COL_COL_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_col_col_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:2 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_COL_COL_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_col_row_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:3 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_COL_ROW_COL_COMPLETED_SUCCESSFULLY\n"); - - - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_col_row_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:4 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_COL_ROW_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_row_col_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:5 took %fms\n", wmmaTime); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_ROW_COL_COL_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_row_col_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:6 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_ROW_COL_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_row_row_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:7 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_ROW_ROW_COL_COMPLETED_SUCCESSFULLY\n"); - - - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_row_row_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:8 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_ROW_ROW_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_col_col_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:9 took %fms\n", wmmaTime); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[n*MATRIX_N+m]; - } - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_COL_COL_COL_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_col_col_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:10 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_COL_COL_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_col_row_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:11 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_COL_ROW_COL_COMPLETED_SUCCESSFULLY\n"); - - - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_col_row_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:12 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_COL_ROW_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_row_col_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:13 took %fms\n", wmmaTime); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_ROW_COL_COL_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_row_col_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:14 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_ROW_COL_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_row_row_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:15 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_ROW_ROW_COL_COMPLETED_SUCCESSFULLY\n"); - - - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_row_row_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:16 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_ROW_ROW_COL_COMPLETED_SUCCESSFULLY\n"); - - - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - - cudaErrCheck(cudaFree(a_fp32)); - cudaErrCheck(cudaFree(b_fp32)); - cudaErrCheck(cudaFree(c_fp32)); - cudaErrCheck(cudaFree(d_fp32)); - cudaErrCheck(cudaFree(a_fp16)); - cudaErrCheck(cudaFree(b_fp16)); - cudaErrCheck(cudaFree(c_fp16)); - cudaErrCheck(cudaFree(d_fp16)); - - free(a_host_wmma); - free(b_host_wmma); - free(c_host_wmma); - free(d_host_wmma); - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuda-kernels/tensorcore_layout_fp32_fp32.cu b/cuda-kernels/tensorcore_layout_fp32_fp32.cu deleted file mode 100644 index c901387..0000000 --- a/cuda-kernels/tensorcore_layout_fp32_fp32.cu +++ /dev/null @@ -1,876 +0,0 @@ -#include <stdio.h> -#include <curand.h> -#include <stdlib.h> -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - -#define curandErrCheck(stat) { curandErrCheck_((stat), __FILE__, __LINE__); } -void curandErrCheck_(curandStatus_t stat, const char *file, int line) { - if (stat != CURAND_STATUS_SUCCESS) { - fprintf(stderr, "cuRand Error: %d %s %d\n", stat, file, line); - } -} - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (16) -#define MATRIX_N (16) -#define MATRIX_K (16) - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - -//wmma_example_dLayout_cLayout_bLayout_aLayout - -__global__ void wmma_example_col_col_col_col(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_col_col_row(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_col_row_col(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_col_row_row(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_row_col_col(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_row_col_row(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_row_row_col(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_col_row_row_row(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); -} -__global__ void wmma_example_row_col_col_col(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_col_col_row(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_col_row_col(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_col_row_row(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_row_col_col(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_row_col_row(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_row_row_col(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} -__global__ void wmma_example_row_row_row_row(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::row_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_row_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_row_major); -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} -__global__ void convertFp16ToFp32 (float *out, half *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -int main(int argc, char* argv[]) { - float *a_fp32; - float *b_fp32; - float *c_fp32; - float *d_fp32; - - half *a_fp16; - half *b_fp16; - // half *c_fp16; - // half *d_fp16; - - float *a_host_wmma; - float *b_host_wmma; - float *c_host_wmma; - float *d_host_wmma; - float *d_cal_host_wmma; - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - - float wmmaTime; - - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - cudaErrCheck(cudaMalloc((void**)&a_fp32, MATRIX_M * MATRIX_K * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&b_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&c_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&d_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&a_fp16, MATRIX_M * MATRIX_K * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&b_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - //cudaErrCheck(cudaMalloc((void**)&c_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - //cudaErrCheck(cudaMalloc((void**)&d_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - - - a_host_wmma = (float*)malloc(MATRIX_M * MATRIX_K * sizeof(float)); - b_host_wmma = (float*)malloc(MATRIX_K * MATRIX_N * sizeof(float)); - c_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_cal_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - - printf("a_fp32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]=((rand()%9)/3.0); - printf("%f ",a_host_wmma[m*MATRIX_K+n]); - } - printf(";\n"); - } - - printf("b_fp32\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]=((rand()%9)/3.0); - printf("%f ",b_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - - printf("c_fp32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_host_wmma[m*MATRIX_N+n]=((rand()%9)/3.0); - d_cal_host_wmma[m*MATRIX_N+n]=0; - printf("%f ",c_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - - - cudaErrCheck(cudaMemcpy(a_fp32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_fp32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_fp32,c_host_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - - convertFp32ToFp16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_fp16, a_fp32, MATRIX_M * MATRIX_K); - convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); - //convertFp32ToFp16 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (c_fp16, c_fp32, MATRIX_K * MATRIX_N); - - printf("\nM = %d, N = %d, K = %d. \n", MATRIX_M, MATRIX_N, MATRIX_K); - - int suc=1; - printf("Running with wmma...\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_col_col_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:1 took %fms\n", wmmaTime); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[n*MATRIX_N+m]; - } - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_COL_COL_COL_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_col_col_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:2 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_COL_COL_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_col_row_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:3 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_COL_ROW_COL_COMPLETED_SUCCESSFULLY\n"); - - - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_col_row_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:4 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_COL_ROW_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_row_col_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:5 took %fms\n", wmmaTime); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_ROW_COL_COL_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_row_col_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:6 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_ROW_COL_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_row_row_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:7 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_ROW_ROW_COL_COMPLETED_SUCCESSFULLY\n"); - - - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_col_row_row_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:8 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[n*MATRIX_N+m]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[n*MATRIX_N+m]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[n*MATRIX_N+m]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_COL_ROW_ROW_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_col_col_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:9 took %fms\n", wmmaTime); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[n*MATRIX_N+m]; - } - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_COL_COL_COL_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_col_col_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:10 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_COL_COL_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_col_row_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:11 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_COL_ROW_COL_COMPLETED_SUCCESSFULLY\n"); - - - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_col_row_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:12 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[n*MATRIX_N+m]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_COL_ROW_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_row_col_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:13 took %fms\n", wmmaTime); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_ROW_COL_COL_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_row_col_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:14 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[n*MATRIX_K+k]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_ROW_COL_ROW_COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_row_row_col <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:15 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[k*MATRIX_K+m]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_ROW_ROW_COL_COMPLETED_SUCCESSFULLY\n"); - - - - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example_row_row_row_row <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma_kernel:16 took %fms\n", wmmaTime); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - d_cal_host_wmma[m*MATRIX_N+n]=0; - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - printf("cpu=%f,gpgpusim=%f\n",d_cal_host_wmma[m*MATRIX_N+n],d_host_wmma[m*MATRIX_N+n]); - } - } - } - if(suc==1) - printf("WMMA_CONFIG_ROW_ROW_ROW_COL_COMPLETED_SUCCESSFULLY\n"); - - - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - - cudaErrCheck(cudaFree(a_fp32)); - cudaErrCheck(cudaFree(b_fp32)); - cudaErrCheck(cudaFree(c_fp32)); - cudaErrCheck(cudaFree(d_fp32)); - cudaErrCheck(cudaFree(a_fp16)); - cudaErrCheck(cudaFree(b_fp16)); - //cudaErrCheck(cudaFree(c_fp16)); - //cudaErrCheck(cudaFree(d_fp16)); - - free(a_host_wmma); - free(b_host_wmma); - free(c_host_wmma); - free(d_host_wmma); - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuda-kernels/tensorcore_type16_16.cu b/cuda-kernels/tensorcore_type16_16.cu deleted file mode 100644 index 2b93bf5..0000000 --- a/cuda-kernels/tensorcore_type16_16.cu +++ /dev/null @@ -1,217 +0,0 @@ -#include <stdio.h> -#include <curand.h> - -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - -#define curandErrCheck(stat) { curandErrCheck_((stat), __FILE__, __LINE__); } -void curandErrCheck_(curandStatus_t stat, const char *file, int line) { - if (stat != CURAND_STATUS_SUCCESS) { - fprintf(stderr, "cuRand Error: %d %s %d\n", stat, file, line); - } -} - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (16) -#define MATRIX_N (16) -#define MATRIX_K (16) - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - -__global__ void wmma_example(half *a, half *b, half *c,half *d_fp16, int M, int N, int K) { - //unsigned int start_time=0,end_time=0; - //start_time=clock(); - - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); - //printf("clock=%d",end_time-start_time); -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} -__global__ void convertFp16ToFp32 (float *out, half *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -int main(int argc, char* argv[]) { - float *a_fp32; - float *b_fp32; - float *c_fp32; - float *d_fp32; - - half *a_fp16; - half *b_fp16; - half *c_fp16; - half *d_fp16; - - float *a_host_wmma; - float *b_host_wmma; - float *c_host_wmma; - float *d_host_wmma; - float *d_cal_host_wmma; - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - - - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - cudaErrCheck(cudaMalloc((void**)&a_fp32, MATRIX_M * MATRIX_K * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&b_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&c_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&d_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&a_fp16, MATRIX_M * MATRIX_K * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&b_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&c_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&d_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - - - a_host_wmma = (float*)malloc(MATRIX_M * MATRIX_K * sizeof(float)); - b_host_wmma = (float*)malloc(MATRIX_K * MATRIX_N * sizeof(float)); - c_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_cal_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - - //printf("a_fp32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]=(m*MATRIX_K+n)%10; - // printf("%f ",a_host_wmma[m*MATRIX_K+n]); - } - //printf(";\n"); - } - - //printf("b_fp32\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]=(m*MATRIX_N+n)%10; - // printf("%f ",b_host_wmma[m*MATRIX_N+n]); - } - // printf(";\n"); - } - - //printf("c_fp32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_host_wmma[m*MATRIX_N+n]=(m*MATRIX_N+n)%10; - d_cal_host_wmma[m*MATRIX_N+n]=0; - // printf("%f ",c_host_wmma[m*MATRIX_N+n]); - } - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - - - cudaErrCheck(cudaMemcpy(a_fp32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_fp32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_fp32,c_host_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - - convertFp32ToFp16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_fp16, a_fp32, MATRIX_M * MATRIX_K); - convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); - convertFp32ToFp16 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (c_fp16, c_fp32, MATRIX_K * MATRIX_N); - - printf("\nM = %d, N = %d, K = %d. \n", MATRIX_M, MATRIX_N, MATRIX_K); - - printf("Running with wmma...\n"); - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - // Error checking - printf("\nChecking results...\n"); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - - printf("Results verified: cublas and WMMA agree.\n\n"); - float wmmaTime; - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma took %fms\n", wmmaTime); - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - - int t=200000; - while(t-->0); - printf("D_CALCULATED\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%.2f,",d_cal_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - printf("D_WMMA\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%.2f,",d_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - int suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - } - } - } - if(suc==1) - printf("COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaFree(a_fp32)); - cudaErrCheck(cudaFree(b_fp32)); - cudaErrCheck(cudaFree(c_fp32)); - cudaErrCheck(cudaFree(d_fp32)); - cudaErrCheck(cudaFree(a_fp16)); - cudaErrCheck(cudaFree(b_fp16)); - cudaErrCheck(cudaFree(c_fp16)); - cudaErrCheck(cudaFree(d_fp16)); - - free(a_host_wmma); - free(b_host_wmma); - free(c_host_wmma); - free(d_host_wmma); - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuda-kernels/tensorcore_type16_32.cu b/cuda-kernels/tensorcore_type16_32.cu deleted file mode 100644 index 9ab86e1..0000000 --- a/cuda-kernels/tensorcore_type16_32.cu +++ /dev/null @@ -1,207 +0,0 @@ -#include <stdio.h> -#include <curand.h> - -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - -#define curandErrCheck(stat) { curandErrCheck_((stat), __FILE__, __LINE__); } -void curandErrCheck_(curandStatus_t stat, const char *file, int line) { - if (stat != CURAND_STATUS_SUCCESS) { - fprintf(stderr, "cuRand Error: %d %s %d\n", stat, file, line); - } -} - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (16) -#define MATRIX_N (16) -#define MATRIX_K (16) - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - -__global__ void wmma_example(half *a, half *b, float *c,half *d_fp16, int M, int N, int K) { - //unsigned int start_time=0,end_time=0; - //start_time=clock(); - - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - -// for(int i=0; i < c_frag.num_elements; i++) { -//// c_frag.x[i]=c_frag.x[i]+c_frag.x[i]; -// float temp=c_frag.x[i]; -// printf("THREAD%d:%d: %f \n",threadIdx.x,i,temp ); -// } - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - for(int i=0; i < c_frag.num_elements; i++) { - d_frag.x[i]=c_frag.x[i]; - } - wmma::store_matrix_sync(d_fp16, d_frag, N, wmma::mem_col_major); - //printf("clock=%d",end_time-start_time); -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} -__global__ void convertFp16ToFp32 (float *out, half *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -int main(int argc, char* argv[]) { - float *a_fp32; - float *b_fp32; - float *c_fp32; - float *d_fp32; - - half *a_fp16; - half *b_fp16; - half *c_fp16; - half *d_fp16; - - float *a_host_wmma; - float *b_host_wmma; - float *c_host_wmma; - float *d_host_wmma; - float *d_cal_host_wmma; - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - - - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - cudaErrCheck(cudaMalloc((void**)&a_fp32, MATRIX_M * MATRIX_K * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&b_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&c_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&d_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&a_fp16, MATRIX_M * MATRIX_K * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&b_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&c_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&d_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - - - a_host_wmma = (float*)malloc(MATRIX_M * MATRIX_K * sizeof(float)); - b_host_wmma = (float*)malloc(MATRIX_K * MATRIX_N * sizeof(float)); - c_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_cal_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - - //printf("a_fp32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]=(m*MATRIX_K+n)%10; - // printf("%f ",a_host_wmma[m*MATRIX_K+n]); - } - //printf(";\n"); - } - - //printf("b_fp32\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]=(m*MATRIX_N+n)%10; - // printf("%f ",b_host_wmma[m*MATRIX_N+n]); - } - // printf(";\n"); - } - - //printf("c_fp32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_host_wmma[m*MATRIX_N+n]=(m*MATRIX_N+n); - d_cal_host_wmma[m*MATRIX_N+n]=0; - // printf("%f ",c_host_wmma[m*MATRIX_N+n]); - } - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - - - cudaErrCheck(cudaMemcpy(a_fp32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_fp32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_fp32,c_host_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - - convertFp32ToFp16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_fp16, a_fp32, MATRIX_M * MATRIX_K); - convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); - - printf("\nM = %d, N = %d, K = %d. \n", MATRIX_M, MATRIX_N, MATRIX_K); - - printf("Running with wmma...\n"); - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp16 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - - convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - // Error checking - printf("\nChecking results...\n"); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - - printf("Results verified: cublas and WMMA agree.\n\n"); - float wmmaTime; - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma took %fms\n", wmmaTime); - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - int t=600000; - while(t-->0); - - printf("D_WMMA\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%.2f,",d_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - printf("Check the result by executing the kernel on volta\n"); - cudaErrCheck(cudaFree(a_fp32)); - cudaErrCheck(cudaFree(b_fp32)); - cudaErrCheck(cudaFree(c_fp32)); - cudaErrCheck(cudaFree(d_fp32)); - cudaErrCheck(cudaFree(a_fp16)); - cudaErrCheck(cudaFree(b_fp16)); - cudaErrCheck(cudaFree(c_fp16)); - cudaErrCheck(cudaFree(d_fp16)); - - free(a_host_wmma); - free(b_host_wmma); - free(c_host_wmma); - free(d_host_wmma); - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuda-kernels/tensorcore_type32_16.cu b/cuda-kernels/tensorcore_type32_16.cu deleted file mode 100644 index c66d8f8..0000000 --- a/cuda-kernels/tensorcore_type32_16.cu +++ /dev/null @@ -1,218 +0,0 @@ -#include <stdio.h> -#include <curand.h> - -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - -#define curandErrCheck(stat) { curandErrCheck_((stat), __FILE__, __LINE__); } -void curandErrCheck_(curandStatus_t stat, const char *file, int line) { - if (stat != CURAND_STATUS_SUCCESS) { - fprintf(stderr, "cuRand Error: %d %s %d\n", stat, file, line); - } -} - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (16) -#define MATRIX_N (16) -#define MATRIX_K (16) - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - -__global__ void wmma_example(half *a, half *b, half *c,float *d_fp32, int M, int N, int K) { - //unsigned int start_time=0,end_time=0; - //start_time=clock(); - - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, half> c_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> d_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(d_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp32, d_frag, N, wmma::mem_col_major); - //printf("clock=%d",end_time-start_time); -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} -__global__ void convertFp16ToFp32 (float *out, half *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -int main(int argc, char* argv[]) { - float *a_fp32; - float *b_fp32; - float *c_fp32; - float *d_fp32; - - half *a_fp16; - half *b_fp16; - half *c_fp16; - half *d_fp16; - - float *a_host_wmma; - float *b_host_wmma; - float *c_host_wmma; - float *d_host_wmma; - float *d_cal_host_wmma; - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - - - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - cudaErrCheck(cudaMalloc((void**)&a_fp32, MATRIX_M * MATRIX_K * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&b_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&c_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&d_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&a_fp16, MATRIX_M * MATRIX_K * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&b_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&c_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&d_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - - - a_host_wmma = (float*)malloc(MATRIX_M * MATRIX_K * sizeof(float)); - b_host_wmma = (float*)malloc(MATRIX_K * MATRIX_N * sizeof(float)); - c_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_cal_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - - //printf("a_fp32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]=(m*MATRIX_K+n)%10; - // printf("%f ",a_host_wmma[m*MATRIX_K+n]); - } - //printf(";\n"); - } - - //printf("b_fp32\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]=(m*MATRIX_N+n)%10; - // printf("%f ",b_host_wmma[m*MATRIX_N+n]); - } - // printf(";\n"); - } - - //printf("c_fp32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_host_wmma[m*MATRIX_N+n]=(m*MATRIX_N+n)%10; - d_cal_host_wmma[m*MATRIX_N+n]=0; - // printf("%f ",c_host_wmma[m*MATRIX_N+n]); - } - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - - - cudaErrCheck(cudaMemcpy(a_fp32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_fp32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_fp32,c_host_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - - convertFp32ToFp16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_fp16, a_fp32, MATRIX_M * MATRIX_K); - convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); - convertFp32ToFp16 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (c_fp16, c_fp32, MATRIX_K * MATRIX_N); - - printf("\nM = %d, N = %d, K = %d. \n", MATRIX_M, MATRIX_N, MATRIX_K); - - printf("Running with wmma...\n"); - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example <<< 1, 32>>> (a_fp16, b_fp16, c_fp16, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - - //convertFp16ToFp32 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (d_fp32, d_fp16, MATRIX_K * MATRIX_N); - // Error checking - printf("\nChecking results...\n"); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - - printf("Results verified: cublas and WMMA agree.\n\n"); - float wmmaTime; - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma took %fms\n", wmmaTime); - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - - int t=600000; - while(t-->0); - printf("D_CALCULATED\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%.2f,",d_cal_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - printf("D_WMMA\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%.2f,",d_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - int suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - } - } - } - if(suc==1) - printf("COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaFree(a_fp32)); - cudaErrCheck(cudaFree(b_fp32)); - cudaErrCheck(cudaFree(c_fp32)); - cudaErrCheck(cudaFree(d_fp32)); - cudaErrCheck(cudaFree(a_fp16)); - cudaErrCheck(cudaFree(b_fp16)); - cudaErrCheck(cudaFree(c_fp16)); - cudaErrCheck(cudaFree(d_fp16)); - - free(a_host_wmma); - free(b_host_wmma); - free(c_host_wmma); - free(d_host_wmma); - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuda-kernels/tensorcore_type32_32.cu b/cuda-kernels/tensorcore_type32_32.cu deleted file mode 100644 index 73386f9..0000000 --- a/cuda-kernels/tensorcore_type32_32.cu +++ /dev/null @@ -1,217 +0,0 @@ -#include <stdio.h> -#include <curand.h> - -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - -#define curandErrCheck(stat) { curandErrCheck_((stat), __FILE__, __LINE__); } -void curandErrCheck_(curandStatus_t stat, const char *file, int line) { - if (stat != CURAND_STATUS_SUCCESS) { - fprintf(stderr, "cuRand Error: %d %s %d\n", stat, file, line); - } -} - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (16) -#define MATRIX_N (16) -#define MATRIX_K (16) - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - -__global__ void wmma_example(half *a, half *b, float *c,float *d_fp16, int M, int N, int K) { - //unsigned int start_time=0,end_time=0; - //start_time=clock(); - - // Declare the fragments - wmma::fragment<wmma::matrix_a, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> a_frag; - wmma::fragment<wmma::matrix_b, WMMA_M, WMMA_N, WMMA_K, half, wmma::col_major> b_frag; - wmma::fragment<wmma::accumulator, WMMA_M, WMMA_N, WMMA_K, float> c_frag; - - // Bounds checking - wmma::load_matrix_sync(a_frag, a, K); - wmma::load_matrix_sync(b_frag, b, K); - wmma::load_matrix_sync(c_frag, c, N,wmma::mem_col_major); - wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); - - wmma::store_matrix_sync(d_fp16, c_frag, N, wmma::mem_col_major); - //printf("clock=%d",end_time-start_time); -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} -__global__ void convertFp16ToFp32 (float *out, half *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -int main(int argc, char* argv[]) { - float *a_fp32; - float *b_fp32; - float *c_fp32; - float *d_fp32; - - half *a_fp16; - half *b_fp16; - // half *c_fp16; - // half *d_fp16; - - float *a_host_wmma; - float *b_host_wmma; - float *c_host_wmma; - float *d_host_wmma; - float *d_cal_host_wmma; - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - - - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - cudaErrCheck(cudaMalloc((void**)&a_fp32, MATRIX_M * MATRIX_K * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&b_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&c_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&d_fp32, MATRIX_K * MATRIX_N * sizeof(float))); - cudaErrCheck(cudaMalloc((void**)&a_fp16, MATRIX_M * MATRIX_K * sizeof(half))); - cudaErrCheck(cudaMalloc((void**)&b_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - //cudaErrCheck(cudaMalloc((void**)&c_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - //cudaErrCheck(cudaMalloc((void**)&d_fp16, MATRIX_K * MATRIX_N * sizeof(half))); - - - a_host_wmma = (float*)malloc(MATRIX_M * MATRIX_K * sizeof(float)); - b_host_wmma = (float*)malloc(MATRIX_K * MATRIX_N * sizeof(float)); - c_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - d_cal_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); - - //printf("a_fp32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]=(m*MATRIX_K+n)%10; - // printf("%f ",a_host_wmma[m*MATRIX_K+n]); - } - //printf(";\n"); - } - - //printf("b_fp32\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]=(m*MATRIX_N+n)%10; - // printf("%f ",b_host_wmma[m*MATRIX_N+n]); - } - // printf(";\n"); - } - - //printf("c_fp32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_host_wmma[m*MATRIX_N+n]=(m*MATRIX_N+n)%10; - d_cal_host_wmma[m*MATRIX_N+n]=0; - // printf("%f ",c_host_wmma[m*MATRIX_N+n]); - } - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - - - cudaErrCheck(cudaMemcpy(a_fp32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_fp32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_fp32,c_host_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyHostToDevice)); - - convertFp32ToFp16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_fp16, a_fp32, MATRIX_M * MATRIX_K); - convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); - //convertFp32ToFp16 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (c_fp16, c_fp32, MATRIX_K * MATRIX_N); - - printf("\nM = %d, N = %d, K = %d. \n", MATRIX_M, MATRIX_N, MATRIX_K); - - printf("Running with wmma...\n"); - cudaErrCheck(cudaEventRecord(startWMMA)); - wmma_example <<< 1, 32>>> (a_fp16, b_fp16, c_fp32, d_fp32 , MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - - // Error checking - printf("\nChecking results...\n"); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_fp32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - - printf("Results verified: cublas and WMMA agree.\n\n"); - float wmmaTime; - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma took %fms\n", wmmaTime); - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - - int t=200000; - while(t-->0); - printf("D_CALCULATED\n"); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%.2f,",d_cal_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - printf("D_WMMA\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%.2f,",d_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - int suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])>1) - { - printf("ERROR:\n"); - suc=0; - } - } - } - if(suc==1) - printf("COMPLETED_SUCCESSFULLY\n"); - - cudaErrCheck(cudaFree(a_fp32)); - cudaErrCheck(cudaFree(b_fp32)); - cudaErrCheck(cudaFree(c_fp32)); - cudaErrCheck(cudaFree(d_fp32)); - cudaErrCheck(cudaFree(a_fp16)); - cudaErrCheck(cudaFree(b_fp16)); - //cudaErrCheck(cudaFree(c_fp16)); - //cudaErrCheck(cudaFree(d_fp16)); - - free(a_host_wmma); - free(b_host_wmma); - free(c_host_wmma); - free(d_host_wmma); - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuda-kernels/v16p_genericMatrixMultiply.cu b/cuda-kernels/v16p_genericMatrixMultiply.cu deleted file mode 100644 index 284bd7e..0000000 --- a/cuda-kernels/v16p_genericMatrixMultiply.cu +++ /dev/null @@ -1,388 +0,0 @@ -#include <stdio.h> -#include <curand.h> -#include <stdlib.h> - -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - -#define curandErrCheck(stat) { curandErrCheck_((stat), __FILE__, __LINE__); } -void curandErrCheck_(curandStatus_t stat, const char *file, int line) { - if (stat != CURAND_STATUS_SUCCESS) { - fprintf(stderr, "cuRand Error: %d %s %d\n", stat, file, line); - } -} - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (SIZE) -#define MATRIX_N (SIZE) -#define MATRIX_K (SIZE) - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - - - -__global__ void vp_example(int *a, int *b, int *c, int M, int N, int K ) { - // Leading dimensions. Packed with no transpositions. - int lda = M; - int ldb = K; - int ldc = M; - - // Tile using a 2D grid - int warpM = (blockIdx.x * blockDim.x + threadIdx.x) / warpSize; - int warpN = (blockIdx.y * blockDim.y + threadIdx.y); - - // Declare the fragments - int a_frag[8]; - int b_frag[8]; - int c_frag[8]; - int acc_frag[8]; - - acc_frag[0]=0; - acc_frag[1]=0; - acc_frag[2]=0; - acc_frag[3]=0; - acc_frag[4]=0; - acc_frag[5]=0; - acc_frag[6]=0; - acc_frag[7]=0; - - // Loop over k - for (int i = 0; i < K; i += WMMA_K) { - int aRow = warpM * WMMA_M; - int aCol = i; - - int bRow = i; - int bCol = warpN * WMMA_N; - - // Bounds checking - if (aRow < M && aCol < K && bRow < K && bCol < N) { - // Load the inputs - // vp::load_matrix_sync(a_frag, a + aRow * lda+ aCol , lda); - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.a.sync.row.m16n16k16.s32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8],%9;" : - "=r"(a_frag[0]), "=r"(a_frag[1]),"=r"(a_frag[2]),"=r"(a_frag[3]), - "=r"(a_frag[4]),"=r"(a_frag[5]),"=r"(a_frag[6]),"=r"(a_frag[7]): - "l"(a+aRow*lda+aCol),"r"(lda) - ); - asm("CPTX_END"); - asm("*/"); - //vp::load_matrix_sync(b_frag, b + bRow * ldb+ bCol , ldb); - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.b16.sync.row.m16n16k16.s32 {%0,%1,%2,%3},[%4],%5;" : - "=r"(b_frag[0]),"=r"(b_frag[1]),"=r"(b_frag[2]),"=r"(b_frag[3]): - "l"(b+bRow*ldb/2+bCol/2),"r"(ldb)//NOTE pointer arithematic is happenning over here so be extracareful - ); - asm("CPTX_END"); - asm("*/"); - - // Perform the matrix multiplication - //vp::mma_sync(acc_frag, a_frag, b_frag, acc_frag); - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.mma16.sync.row.row.m16n16k16.s32 {%0, %1, %2, %3, %4, %5, %6, %7}, {%8, %9, %10, %11, %12, %13, %14, %15}, {%16, %17, %18, %19}, { %20, %21, %22, %23, %24, %25, %26,%27};" : - "=r"(acc_frag[0]), "=r"(acc_frag[1]),"=r"(acc_frag[2]),"=r"(acc_frag[3]), - "=r"(acc_frag[4]),"=r"(acc_frag[5]),"=r"(acc_frag[6]),"=r"(acc_frag[7]): - "r"(a_frag[0]),"r"(a_frag[1]),"r"(a_frag[2]),"r"(a_frag[3]), - "r"(a_frag[4]),"r"(a_frag[5]),"r"(a_frag[6]),"r"(a_frag[7]), - "r"(b_frag[0]),"r"(b_frag[1]),"r"(b_frag[2]),"r"(b_frag[3]), - "r"(acc_frag[0]),"r"(acc_frag[1]),"r"(acc_frag[2]),"r"(acc_frag[3]), - "r"(acc_frag[4]),"r"(acc_frag[5]),"r"(acc_frag[6]),"r"(acc_frag[7]) - ); - asm("CPTX_END"); - asm("*/"); - - } - } - - // Load in the current value of c, scale it by beta, and add this our result scaled by alpha - int cRow = warpM * WMMA_M; - int cCol = warpN * WMMA_N; - - if (cRow < M && cCol < N) { - //vp::load_matrix_sync(c_frag, c + cRow*ldc + cCol , ldc, wmma::mem_row_major); - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.c.sync.row.m16n16k16.s32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8],%9;" : - "=r"(c_frag[0]), "=r"(c_frag[1]),"=r"(c_frag[2]),"=r"(c_frag[3]), - "=r"(c_frag[4]),"=r"(c_frag[5]),"=r"(c_frag[6]),"=r"(c_frag[7]): - "l"(c+cRow*ldc+cCol),"r"(ldc) - ); - asm("CPTX_END"); - asm("*/"); - - - for(int i=0; i < 8; i++) { - c_frag[i] = acc_frag[i] + c_frag[i]; - } - - // Store the output - //vp::store_matrix_sync(c + cRow *ldc + cCol , c_frag, ldc, wmma::mem_row_major); - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.store.d.sync.row.m16n16k16.s32 [%0], {%1,%2,%3,%4,%5,%6,%7,%8},%9;" : - :"l"(c+cRow*ldc+cCol), - "r"(c_frag[0]), "r"(c_frag[1]),"r"(c_frag[2]),"r"(c_frag[3]), - "r"(c_frag[4]),"r"(c_frag[5]),"r"(c_frag[6]),"r"(c_frag[7]), - "r"(ldc) - ); - asm("CPTX_END"); - asm("*/"); - } -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} -__global__ void convertFp16ToFp32 (float *out, half *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -__global__ void convertInt32ToInt4 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/8) { - out[idx] =(in[8*idx]&0xf)|(in[8*idx+1]&0xf)<<4|(in[8*idx+2]&0xf)<<8|(in[8*idx+3]&0xf)<<12| - (in[8*idx+4]&0xf)<<16|(in[8*idx+5]&0xf)<<20|(in[8*idx+6]&0xf)<<24|(in[8*idx+7]&0xf)<<28; - } -} -__global__ void convertInt32ToInt8 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/4) { - out[idx] =(in[4*idx]&0xff)|(in[4*idx+1]&0xff)<<8|(in[4*idx+2]&0xff)<<16|(in[4*idx+3]&0xff)<<24; - } -} -__global__ void convertInt32ToInt16 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/2) { - out[idx] =(in[2*idx]&0xffff)|(in[2*idx+1]&0xffff)<<16; - } -} - -__global__ void convertInt4ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=4*(idx%8); - int shft_mask=0xf<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/8]&shft_mask)>>shft_amt; - } -} -__global__ void convertInt8ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=8*(idx%4); - int shft_mask=0xff<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/4]&shft_mask)>>shft_amt; - } -} -__global__ void convertInt16ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=16*(idx%2); - int shft_mask=0xffff<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/2]&shft_mask)>>shft_amt; - } -} - -int main(int argc, char* argv[]) { - int *a_int32; - int *b_int32; - int *c_int32; - int *d_int32; - - int *a_int4; - int *b_int4; - int *a_int8; - int *b_int8; - int *a_int16; - int *b_int16; - - int *a_host_wmma; - int *b_host_wmma; - int *c_host_wmma; - int *d_host_wmma; - int *d_cal_host_wmma; - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - - srand(time(NULL)); - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - cudaErrCheck(cudaMalloc((void**)&a_int32, MATRIX_M * MATRIX_K * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&b_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&c_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&d_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&a_int4, MATRIX_M * MATRIX_K * sizeof(int)/8)); - cudaErrCheck(cudaMalloc((void**)&b_int4, MATRIX_K * MATRIX_N * sizeof(int)/8)); - cudaErrCheck(cudaMalloc((void**)&a_int8, MATRIX_M * MATRIX_K * sizeof(int)/4)); - cudaErrCheck(cudaMalloc((void**)&b_int8, MATRIX_K * MATRIX_N * sizeof(int)/4)); - cudaErrCheck(cudaMalloc((void**)&a_int16, MATRIX_M * MATRIX_K * sizeof(int)/2)); - cudaErrCheck(cudaMalloc((void**)&b_int16, MATRIX_K * MATRIX_N * sizeof(int)/2)); - - - a_host_wmma = (int *)malloc(MATRIX_M * MATRIX_K * sizeof(int)); - b_host_wmma = (int *)malloc(MATRIX_K * MATRIX_N * sizeof(int)); - c_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - d_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - d_cal_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - - printf("a_int32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]= random()%2; - //a_host_wmma[m*MATRIX_K+n]= m*MATRIX_K+n; - printf("%d ",a_host_wmma[m*MATRIX_K+n]); - } - printf(";\n"); - } - - printf("b_int32\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]= random()%4; - //b_host_wmma[m*MATRIX_N+n]= m*MATRIX_N+n; - printf("%d ",b_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - - printf("c_int32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_host_wmma[m*MATRIX_N+n]= random()%32; - //c_host_wmma[m*MATRIX_N+n]= m*MATRIX_N+n; - d_cal_host_wmma[m*MATRIX_N+n]=0; - printf("%d ",c_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - - - cudaErrCheck(cudaMemcpy(a_int32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(int), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_int32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(int), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_int32,c_host_wmma, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyHostToDevice)); - - #ifdef TEST16 - convertInt32ToInt16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_int16, a_int32, MATRIX_M * MATRIX_K); - convertInt16ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, a_int16, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - #ifdef TEST8 - convertInt32ToInt8 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_int8, a_int32, MATRIX_M * MATRIX_K); - convertInt8ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, a_int8, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - #ifdef TEST4 - convertInt32ToInt4 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (b_int4, b_int32, MATRIX_M * MATRIX_K); - convertInt4ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, b_int4, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - convertInt32ToInt16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (b_int16, b_int32, MATRIX_M * MATRIX_K); - - dim3 gridDim; - dim3 blockDim; - - // blockDim.x must be a multple of warpSize - // 128x4 means we have 16 warps and a block computes a 64x64 output tile - blockDim.x = 64; - blockDim.y = 2; - - gridDim.x = (MATRIX_M + (WMMA_M * blockDim.x / 32 - 1)) / (WMMA_M * blockDim.x / 32); - gridDim.y = (MATRIX_N + WMMA_N * blockDim.y - 1) / (WMMA_N * blockDim.y); - printf("GRID:X=%d,Y=%d\n",gridDim.x,gridDim.y); - printf("BLOCK:X=%d,Y=%d\n",blockDim.x,blockDim.y); - - - printf("Running with wmma...\n"); - cudaErrCheck(cudaEventRecord(startWMMA)); - vp_example <<< gridDim, blockDim >>> (a_int32, b_int16, c_int32, MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - - // Error checking - printf("\nChecking results...\n"); - cudaErrCheck(cudaMemcpy(d_host_wmma, c_int32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - - float wmmaTime; - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma took %fms\n", wmmaTime); - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - - int t=1000000; - while(t-->0); - printf("D_CALCULATED\n"); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%d,",d_cal_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - printf("D_WMMA\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%d,",d_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - int suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])) - { - printf("ERROR:\n"); - suc=0; - } - } - } - if(suc==1) - printf("COMPLETED_SUCCESSFULLY\n"); - - - cudaErrCheck(cudaFree(a_int32)); - cudaErrCheck(cudaFree(b_int32)); - cudaErrCheck(cudaFree(c_int32)); - cudaErrCheck(cudaFree(d_int32)); - cudaErrCheck(cudaFree(a_int8)); - cudaErrCheck(cudaFree(b_int8)); - - free(a_host_wmma); - free(b_host_wmma); - free(c_host_wmma); - free(d_host_wmma); - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuda-kernels/v16p_kernel.cu b/cuda-kernels/v16p_kernel.cu deleted file mode 100644 index d84328f..0000000 --- a/cuda-kernels/v16p_kernel.cu +++ /dev/null @@ -1,359 +0,0 @@ -#include <stdio.h> -#include <curand.h> -#include <stdlib.h> - -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - -#define curandErrCheck(stat) { curandErrCheck_((stat), __FILE__, __LINE__); } -void curandErrCheck_(curandStatus_t stat, const char *file, int line) { - if (stat != CURAND_STATUS_SUCCESS) { - fprintf(stderr, "cuRand Error: %d %s %d\n", stat, file, line); - } -} - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (16) -#define MATRIX_N (16) -#define MATRIX_K (16) - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - -__global__ void v16p_example(int *a_int32, int *b_int4, int *c,int *d_int32, int M, int N, int K) { - - int registers_a[8]; - int registers_b[8]; - int registers_c[8]; - int registers_d[8]; - int register_b; //contains 8 4bit b elements - int idx = blockDim.x * blockIdx.x + threadIdx.x; - - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.a.sync.row.m16n16k16.s32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8],%9;" : - "=r"(registers_a[0]), "=r"(registers_a[1]),"=r"(registers_a[2]),"=r"(registers_a[3]), - "=r"(registers_a[4]),"=r"(registers_a[5]),"=r"(registers_a[6]),"=r"(registers_a[7]): - "l"(a_int32),"r"(M) - ); - asm("CPTX_END"); - asm("*/"); - - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.b16.sync.row.m16n16k16.s32 {%0,%1,%2,%3},[%4],%5;" : - "=r"(registers_b[0]),"=r"(registers_b[1]),"=r"(registers_b[2]),"=r"(registers_b[3]): - "l"(b_int4),"r"(M) - ); - asm("CPTX_END"); - asm("*/"); - - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.c.sync.row.m16n16k16.s32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8],%9;" : - "=r"(registers_c[0]), "=r"(registers_c[1]),"=r"(registers_c[2]),"=r"(registers_c[3]), - "=r"(registers_c[4]),"=r"(registers_c[5]),"=r"(registers_c[6]),"=r"(registers_c[7]): - "l"(c),"r"(M) - ); - asm("CPTX_END"); - asm("*/"); - //B4 - //asm("/*"); - //asm("CPTX_BEGIN"); - //asm("vp.mma.sync.row.row.m16n16k16.s32 {%0, %1, %2, %3, %4, %5, %6, %7}, {%8, %9, %10, %11, %12, %13, %14, %15}, {%16}, {%17, %18, %19, %20, %21, %22, %23, %24};" : - //"=r"(registers_d[0]), "=r"(registers_d[1]),"=r"(registers_d[2]),"=r"(registers_d[3]), - //"=r"(registers_d[4]),"=r"(registers_d[5]),"=r"(registers_d[6]),"=r"(registers_d[7]): - //"r"(registers_a[0]),"r"(registers_a[1]),"r"(registers_a[2]),"r"(registers_a[3]), - //"r"(registers_a[4]),"r"(registers_a[5]),"r"(registers_a[6]),"r"(registers_a[7]), - //"r"(registers_b[0]), - //"r"(registers_c[0]),"r"(registers_c[1]),"r"(registers_c[2]),"r"(registers_c[3]), - //"r"(registers_c[4]),"r"(registers_c[5]),"r"(registers_c[6]),"r"(registers_c[7]) - //); - //asm("CPTX_END"); - //asm("*/"); - - //B8 - //asm("/*"); - //asm("CPTX_BEGIN"); - //asm("vp.mma.sync.row.row.m16n16k16.s32 {%0, %1, %2, %3, %4, %5, %6, %7}, {%8, %9, %10, %11, %12, %13, %14, %15}, {%16, %17}, {%18, %19, %20, %21, %22, %23, %24, %25};" : - //"=r"(registers_d[0]), "=r"(registers_d[1]),"=r"(registers_d[2]),"=r"(registers_d[3]), - //"=r"(registers_d[4]),"=r"(registers_d[5]),"=r"(registers_d[6]),"=r"(registers_d[7]): - //"r"(registers_a[0]),"r"(registers_a[1]),"r"(registers_a[2]),"r"(registers_a[3]), - //"r"(registers_a[4]),"r"(registers_a[5]),"r"(registers_a[6]),"r"(registers_a[7]), - //"r"(registers_b[0]),"r"(registers_b[1]), - //"r"(registers_c[0]),"r"(registers_c[1]),"r"(registers_c[2]),"r"(registers_c[3]), - //"r"(registers_c[4]),"r"(registers_c[5]),"r"(registers_c[6]),"r"(registers_c[7]) - //); - //asm("CPTX_END"); - //asm("*/"); - - //B16 - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.mma16.sync.row.row.m16n16k16.s32 {%0, %1, %2, %3, %4, %5, %6, %7}, {%8, %9, %10, %11, %12, %13, %14, %15}, {%16, %17, %18, %19}, { %20, %21, %22, %23, %24, %25, %26, %27};" : - "=r"(registers_d[0]), "=r"(registers_d[1]),"=r"(registers_d[2]),"=r"(registers_d[3]), - "=r"(registers_d[4]),"=r"(registers_d[5]),"=r"(registers_d[6]),"=r"(registers_d[7]): - "r"(registers_a[0]),"r"(registers_a[1]),"r"(registers_a[2]),"r"(registers_a[3]), - "r"(registers_a[4]),"r"(registers_a[5]),"r"(registers_a[6]),"r"(registers_a[7]), - "r"(registers_b[0]),"r"(registers_b[1]),"r"(registers_b[2]),"r"(registers_b[3]), - "r"(registers_c[0]),"r"(registers_c[1]),"r"(registers_c[2]),"r"(registers_c[3]), - "r"(registers_c[4]),"r"(registers_c[5]),"r"(registers_c[6]),"r"(registers_c[7]) - ); - asm("CPTX_END"); - asm("*/"); - - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.store.d.sync.row.m16n16k16.s32 [%0], {%1,%2,%3,%4,%5,%6,%7,%8},%9;" : - :"l"(d_int32) - "r"(registers_d[0]), "r"(registers_d[1]),"r"(registers_d[2]),"r"(registers_d[3]), - "r"(registers_d[4]),"r"(registers_d[5]),"r"(registers_d[6]),"r"(registers_d[7]), - "r"(M) - ); - asm("CPTX_END"); - asm("*/"); - //d_int32[0]=registers_d[0]; -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} -__global__ void convertFp16ToFp32 (float *out, half *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -__global__ void convertInt32ToInt4 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/8) { - out[idx] =(in[8*idx]&0xf)|(in[8*idx+1]&0xf)<<4|(in[8*idx+2]&0xf)<<8|(in[8*idx+3]&0xf)<<12| - (in[8*idx+4]&0xf)<<16|(in[8*idx+5]&0xf)<<20|(in[8*idx+6]&0xf)<<24|(in[8*idx+7]&0xf)<<28; - } -} -__global__ void convertInt32ToInt8 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/4) { - out[idx] =(in[4*idx]&0xff)|(in[4*idx+1]&0xff)<<8|(in[4*idx+2]&0xff)<<16|(in[4*idx+3]&0xff)<<24; - } -} -__global__ void convertInt32ToInt16 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/2) { - out[idx] =(in[2*idx]&0xffff)|(in[2*idx+1]&0xffff)<<16; - } -} - -__global__ void convertInt4ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=4*(idx%8); - int shft_mask=0xf<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/8]&shft_mask)>>shft_amt; - } -} -__global__ void convertInt8ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=8*(idx%4); - int shft_mask=0xff<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/4]&shft_mask)>>shft_amt; - } -} -__global__ void convertInt16ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=16*(idx%2); - int shft_mask=0xffff<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/2]&shft_mask)>>shft_amt; - } -} - -int main(int argc, char* argv[]) { - int *a_int32; - int *b_int32; - int *c_int32; - int *d_int32; - - int *a_int4; - int *b_int4; - int *a_int8; - int *b_int8; - int *a_int16; - int *b_int16; - - int *a_host_wmma; - int *b_host_wmma; - int *c_host_wmma; - int *d_host_wmma; - int *d_cal_host_wmma; - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - - srand(time(NULL)); - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - cudaErrCheck(cudaMalloc((void**)&a_int32, MATRIX_M * MATRIX_K * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&b_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&c_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&d_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&a_int4, MATRIX_M * MATRIX_K * sizeof(int)/8)); - cudaErrCheck(cudaMalloc((void**)&b_int4, MATRIX_K * MATRIX_N * sizeof(int)/8)); - cudaErrCheck(cudaMalloc((void**)&a_int8, MATRIX_M * MATRIX_K * sizeof(int)/4)); - cudaErrCheck(cudaMalloc((void**)&b_int8, MATRIX_K * MATRIX_N * sizeof(int)/4)); - cudaErrCheck(cudaMalloc((void**)&a_int16, MATRIX_M * MATRIX_K * sizeof(int)/2)); - cudaErrCheck(cudaMalloc((void**)&b_int16, MATRIX_K * MATRIX_N * sizeof(int)/2)); - - - a_host_wmma = (int *)malloc(MATRIX_M * MATRIX_K * sizeof(int)); - b_host_wmma = (int *)malloc(MATRIX_K * MATRIX_N * sizeof(int)); - c_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - d_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - d_cal_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - - printf("a_int32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]= random()%5; - printf("%d ",a_host_wmma[m*MATRIX_K+n]); - } - printf(";\n"); - } - - printf("b_int32\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]=random()%32; - printf("%d ",b_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - - printf("c_int32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_host_wmma[m*MATRIX_N+n]=random()%32; - d_cal_host_wmma[m*MATRIX_N+n]=0; - printf("%d ",c_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - - - cudaErrCheck(cudaMemcpy(a_int32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(int), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_int32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(int), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_int32,c_host_wmma, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyHostToDevice)); - #ifdef TEST16 - convertInt32ToInt16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (b_int16, b_int32, MATRIX_M * MATRIX_K); - convertInt16ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, b_int16, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - #ifdef TEST8 - convertInt32ToInt8 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (b_int8, b_int32, MATRIX_M * MATRIX_K); - convertInt8ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, b_int8, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - #ifdef TEST4 - convertInt32ToInt4 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (b_int4, b_int32, MATRIX_M * MATRIX_K); - convertInt4ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, b_int4, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - convertInt32ToInt16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (b_int16, b_int32, MATRIX_M * MATRIX_K); - - //convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); - //convertFp32ToFp16 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (c_fp16, c_fp32, MATRIX_K * MATRIX_N); - - -//AAMIR printf("\nM = %d, N = %d, K = %d. \n", MATRIX_M, MATRIX_N, MATRIX_K); -//AAMIR -//AAMIR printf("Running with wmma...\n"); - cudaErrCheck(cudaEventRecord(startWMMA)); - v16p_example <<< 1, 32>>> (a_int32, b_int16, c_int32, d_int32, MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - - - // Error checking - printf("\nChecking results...\n"); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - - float wmmaTime; - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma took %fms\n", wmmaTime); - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - - int t=2000000; - while(t-->0); - printf("D_CALCULATED\n"); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%d,",d_cal_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - printf("D_WMMA\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%d,",d_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - int suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])) - { - printf("ERROR:\n"); - suc=0; - } - } - } - if(suc==1) - printf("COMPLETED_SUCCESSFULLY\n"); - - - cudaErrCheck(cudaFree(a_int32)); - cudaErrCheck(cudaFree(b_int32)); - cudaErrCheck(cudaFree(c_int32)); - cudaErrCheck(cudaFree(d_int32)); - cudaErrCheck(cudaFree(a_int8)); - cudaErrCheck(cudaFree(b_int8)); - - free(a_host_wmma); - free(b_host_wmma); - free(c_host_wmma); - free(d_host_wmma); - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuda-kernels/v4p_genericMatrixMultiply.cu b/cuda-kernels/v4p_genericMatrixMultiply.cu deleted file mode 100644 index 42283c4..0000000 --- a/cuda-kernels/v4p_genericMatrixMultiply.cu +++ /dev/null @@ -1,387 +0,0 @@ -#include <stdio.h> -#include <curand.h> -#include<stdlib.h> - -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - -#define curandErrCheck(stat) { curandErrCheck_((stat), __FILE__, __LINE__); } -void curandErrCheck_(curandStatus_t stat, const char *file, int line) { - if (stat != CURAND_STATUS_SUCCESS) { - fprintf(stderr, "cuRand Error: %d %s %d\n", stat, file, line); - } -} - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (SIZE) -#define MATRIX_N (SIZE) -#define MATRIX_K (SIZE) - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - - - -__global__ void vp_example(int *a, int *b, int *c, int M, int N, int K ) { - // Leading dimensions. Packed with no transpositions. - int lda = M; - int ldb = K; - int ldc = M; - - // Tile using a 2D grid - int warpM = (blockIdx.x * blockDim.x + threadIdx.x) / warpSize; - int warpN = (blockIdx.y * blockDim.y + threadIdx.y); - - // Declare the fragments - int a_frag[8]; - int b_frag[8]; - int c_frag[8]; - int acc_frag[8]; - - acc_frag[0]=0; - acc_frag[1]=0; - acc_frag[2]=0; - acc_frag[3]=0; - acc_frag[4]=0; - acc_frag[5]=0; - acc_frag[6]=0; - acc_frag[7]=0; - - // Loop over k - for (int i = 0; i < K; i += WMMA_K) { - int aRow = warpM * WMMA_M; - int aCol = i; - - int bRow = i; - int bCol = warpN * WMMA_N; - - // Bounds checking - if (aRow < M && aCol < K && bRow < K && bCol < N) { - // Load the inputs - // vp::load_matrix_sync(a_frag, a + aRow * lda+ aCol , lda); - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.a.sync.row.m16n16k16.s32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8],%9;" : - "=r"(a_frag[0]), "=r"(a_frag[1]),"=r"(a_frag[2]),"=r"(a_frag[3]), - "=r"(a_frag[4]),"=r"(a_frag[5]),"=r"(a_frag[6]),"=r"(a_frag[7]): - "l"(a+aRow*lda+aCol),"r"(lda) - ); - asm("CPTX_END"); - asm("*/"); - //vp::load_matrix_sync(b_frag, b + bRow * ldb+ bCol , ldb); - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.b4.sync.row.m16n16k16.s32 {%0},[%1],%2;" : - "=r"(b_frag[0]): - "l"(b+bRow*ldb/8+bCol/8),"r"(ldb) - ); - asm("CPTX_END"); - asm("*/"); - - // Perform the matrix multiplication - //vp::mma_sync(acc_frag, a_frag, b_frag, acc_frag); - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.mma4.sync.row.row.m16n16k16.s32 {%0, %1, %2, %3, %4, %5, %6, %7}, {%8, %9, %10, %11, %12, %13, %14, %15}, {%16}, {%17, %18, %19, %20, %21, %22, %23, %24};" : - "=r"(acc_frag[0]), "=r"(acc_frag[1]),"=r"(acc_frag[2]),"=r"(acc_frag[3]), - "=r"(acc_frag[4]),"=r"(acc_frag[5]),"=r"(acc_frag[6]),"=r"(acc_frag[7]): - "r"(a_frag[0]),"r"(a_frag[1]),"r"(a_frag[2]),"r"(a_frag[3]), - "r"(a_frag[4]),"r"(a_frag[5]),"r"(a_frag[6]),"r"(a_frag[7]), - "r"(b_frag[0]), - "r"(acc_frag[0]),"r"(acc_frag[1]),"r"(acc_frag[2]),"r"(acc_frag[3]), - "r"(acc_frag[4]),"r"(acc_frag[5]),"r"(acc_frag[6]),"r"(acc_frag[7]) - ); - asm("CPTX_END"); - asm("*/"); - - } - } - - // Load in the current value of c, scale it by beta, and add this our result scaled by alpha - int cRow = warpM * WMMA_M; - int cCol = warpN * WMMA_N; - - if (cRow < M && cCol < N) { - //vp::load_matrix_sync(c_frag, c + cRow*ldc + cCol , ldc, wmma::mem_row_major); - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.c.sync.row.m16n16k16.s32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8],%9;" : - "=r"(c_frag[0]), "=r"(c_frag[1]),"=r"(c_frag[2]),"=r"(c_frag[3]), - "=r"(c_frag[4]),"=r"(c_frag[5]),"=r"(c_frag[6]),"=r"(c_frag[7]): - "l"(c+cRow*ldc+cCol),"r"(ldc) - ); - asm("CPTX_END"); - asm("*/"); - - - for(int i=0; i < 8; i++) { - c_frag[i] = acc_frag[i] + c_frag[i]; - } - - // Store the output - //vp::store_matrix_sync(c + cRow *ldc + cCol , c_frag, ldc, wmma::mem_row_major); - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.store.d.sync.row.m16n16k16.s32 [%0], {%1,%2,%3,%4,%5,%6,%7,%8},%9;" : - :"l"(c+cRow*ldc+cCol), - "r"(c_frag[0]), "r"(c_frag[1]),"r"(c_frag[2]),"r"(c_frag[3]), - "r"(c_frag[4]),"r"(c_frag[5]),"r"(c_frag[6]),"r"(c_frag[7]), - "r"(ldc) - ); - asm("CPTX_END"); - asm("*/"); - } -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} -__global__ void convertFp16ToFp32 (float *out, half *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -__global__ void convertInt32ToInt4 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/8) { - out[idx] =(in[8*idx]&0xf)|(in[8*idx+1]&0xf)<<4|(in[8*idx+2]&0xf)<<8|(in[8*idx+3]&0xf)<<12| - (in[8*idx+4]&0xf)<<16|(in[8*idx+5]&0xf)<<20|(in[8*idx+6]&0xf)<<24|(in[8*idx+7]&0xf)<<28; - } -} -__global__ void convertInt32ToInt8 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/4) { - out[idx] =(in[4*idx]&0xff)|(in[4*idx+1]&0xff)<<8|(in[4*idx+2]&0xff)<<16|(in[4*idx+3]&0xff)<<24; - } -} -__global__ void convertInt32ToInt16 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/2) { - out[idx] =(in[2*idx]&0xffff)|(in[2*idx+1]&0xffff)<<16; - } -} - -__global__ void convertInt4ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=4*(idx%8); - int shft_mask=0xf<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/8]&shft_mask)>>shft_amt; - } -} -__global__ void convertInt8ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=8*(idx%4); - int shft_mask=0xff<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/4]&shft_mask)>>shft_amt; - } -} -__global__ void convertInt16ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=16*(idx%2); - int shft_mask=0xffff<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/2]&shft_mask)>>shft_amt; - } -} - -int main(int argc, char* argv[]) { - int *a_int32; - int *b_int32; - int *c_int32; - int *d_int32; - - int *a_int4; - int *b_int4; - int *a_int8; - int *b_int8; - int *a_int16; - int *b_int16; - - int *a_host_wmma; - int *b_host_wmma; - int *c_host_wmma; - int *d_host_wmma; - int *d_cal_host_wmma; - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - - - srand (time(NULL)); - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - cudaErrCheck(cudaMalloc((void**)&a_int32, MATRIX_M * MATRIX_K * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&b_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&c_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&d_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&a_int4, MATRIX_M * MATRIX_K * sizeof(int)/8)); - cudaErrCheck(cudaMalloc((void**)&b_int4, MATRIX_K * MATRIX_N * sizeof(int)/8)); - cudaErrCheck(cudaMalloc((void**)&a_int8, MATRIX_M * MATRIX_K * sizeof(int)/4)); - cudaErrCheck(cudaMalloc((void**)&b_int8, MATRIX_K * MATRIX_N * sizeof(int)/4)); - cudaErrCheck(cudaMalloc((void**)&a_int16, MATRIX_M * MATRIX_K * sizeof(int)/2)); - cudaErrCheck(cudaMalloc((void**)&b_int16, MATRIX_K * MATRIX_N * sizeof(int)/2)); - - - a_host_wmma = (int *)malloc(MATRIX_M * MATRIX_K * sizeof(int)); - b_host_wmma = (int *)malloc(MATRIX_K * MATRIX_N * sizeof(int)); - c_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - d_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - d_cal_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - - printf("a_int32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]= random()%4; - //a_host_wmma[m*MATRIX_K+n]=m*MATRIX_K+n; - printf("%d ",a_host_wmma[m*MATRIX_K+n]); - } - printf(";\n"); - } - - printf("b_int32\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]=random()%2; - printf("%d ",b_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - - printf("c_int32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_host_wmma[m*MATRIX_N+n]= random()%64; - d_cal_host_wmma[m*MATRIX_N+n]=0; - printf("%d ",c_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - - - cudaErrCheck(cudaMemcpy(a_int32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(int), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_int32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(int), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_int32,c_host_wmma, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyHostToDevice)); - - #ifdef TEST16 - convertInt32ToInt16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_int16, a_int32, MATRIX_M * MATRIX_K); - convertInt16ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, a_int16, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - #ifdef TEST8 - convertInt32ToInt8 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_int8, a_int32, MATRIX_M * MATRIX_K); - convertInt8ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, a_int8, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - #ifdef TEST4 - convertInt32ToInt4 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (b_int4, b_int32, MATRIX_M * MATRIX_K); - convertInt4ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, b_int4, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - convertInt32ToInt4 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (b_int4, b_int32, MATRIX_M * MATRIX_K); - - dim3 gridDim; - dim3 blockDim; - - // blockDim.x must be a multple of warpSize - // 128x4 means we have 16 warps and a block computes a 64x64 output tile - blockDim.x = 64; - blockDim.y = 2; - - gridDim.x = (MATRIX_M + (WMMA_M * blockDim.x / 32 - 1)) / (WMMA_M * blockDim.x / 32); - gridDim.y = (MATRIX_N + WMMA_N * blockDim.y - 1) / (WMMA_N * blockDim.y); - printf("GRID:X=%d,Y=%d\n",gridDim.x,gridDim.y); - printf("BLOCK:X=%d,Y=%d\n",blockDim.x,blockDim.y); - - - printf("Running with wmma...\n"); - cudaErrCheck(cudaEventRecord(startWMMA)); - vp_example <<< gridDim, blockDim >>> (a_int32, b_int4, c_int32, MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - - // Error checking - printf("\nChecking results...\n"); - cudaErrCheck(cudaMemcpy(d_host_wmma, c_int32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - - float wmmaTime; - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma took %fms\n", wmmaTime); - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - - int t=1000000; - while(t-->0); - printf("D_CALCULATED\n"); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%d,",d_cal_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - printf("D_WMMA\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%d,",d_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - int suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])) - { - printf("ERROR:\n"); - suc=0; - } - } - } - if(suc==1) - printf("COMPLETED_SUCCESSFULLY\n"); - - - cudaErrCheck(cudaFree(a_int32)); - cudaErrCheck(cudaFree(b_int32)); - cudaErrCheck(cudaFree(c_int32)); - cudaErrCheck(cudaFree(d_int32)); - cudaErrCheck(cudaFree(a_int8)); - cudaErrCheck(cudaFree(b_int8)); - - free(a_host_wmma); - free(b_host_wmma); - free(c_host_wmma); - free(d_host_wmma); - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuda-kernels/v4p_kernel.cu b/cuda-kernels/v4p_kernel.cu deleted file mode 100644 index 053c07b..0000000 --- a/cuda-kernels/v4p_kernel.cu +++ /dev/null @@ -1,359 +0,0 @@ -#include <stdio.h> -#include <stdlib.h> -#include <curand.h> - -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - -#define curandErrCheck(stat) { curandErrCheck_((stat), __FILE__, __LINE__); } -void curandErrCheck_(curandStatus_t stat, const char *file, int line) { - if (stat != CURAND_STATUS_SUCCESS) { - fprintf(stderr, "cuRand Error: %d %s %d\n", stat, file, line); - } -} - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (16) -#define MATRIX_N (16) -#define MATRIX_K (16) - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - -__global__ void v4p_example(int *a_int32, int *b_int4, int *c,int *d_int32, int M, int N, int K) { - - int registers_a[8]; - int registers_b[8]; - int registers_c[8]; - int registers_d[8]; - int register_b; //contains 8 4bit b elements - int idx = blockDim.x * blockIdx.x + threadIdx.x; - - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.a.sync.row.m16n16k16.s32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8],%9;" : - "=r"(registers_a[0]), "=r"(registers_a[1]),"=r"(registers_a[2]),"=r"(registers_a[3]), - "=r"(registers_a[4]),"=r"(registers_a[5]),"=r"(registers_a[6]),"=r"(registers_a[7]): - "l"(a_int32),"r"(M) - ); - asm("CPTX_END"); - asm("*/"); - - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.b4.sync.row.m16n16k16.s32 {%0},[%1],%2;" : - "=r"(registers_b[0]): - "l"(b_int4),"r"(M) - ); - asm("CPTX_END"); - asm("*/"); - - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.c.sync.row.m16n16k16.s32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8],%9;" : - "=r"(registers_c[0]), "=r"(registers_c[1]),"=r"(registers_c[2]),"=r"(registers_c[3]), - "=r"(registers_c[4]),"=r"(registers_c[5]),"=r"(registers_c[6]),"=r"(registers_c[7]): - "l"(c),"r"(M) - ); - asm("CPTX_END"); - asm("*/"); - //B4 - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.mma4.sync.row.row.m16n16k16.s32 {%0, %1, %2, %3, %4, %5, %6, %7}, {%8, %9, %10, %11, %12, %13, %14, %15}, {%16}, {%17, %18, %19, %20, %21, %22, %23, %24};" : - "=r"(registers_d[0]), "=r"(registers_d[1]),"=r"(registers_d[2]),"=r"(registers_d[3]), - "=r"(registers_d[4]),"=r"(registers_d[5]),"=r"(registers_d[6]),"=r"(registers_d[7]): - "r"(registers_a[0]),"r"(registers_a[1]),"r"(registers_a[2]),"r"(registers_a[3]), - "r"(registers_a[4]),"r"(registers_a[5]),"r"(registers_a[6]),"r"(registers_a[7]), - "r"(registers_b[0]), - "r"(registers_c[0]),"r"(registers_c[1]),"r"(registers_c[2]),"r"(registers_c[3]), - "r"(registers_c[4]),"r"(registers_c[5]),"r"(registers_c[6]),"r"(registers_c[7]) - ); - asm("CPTX_END"); - asm("*/"); - - //B8 - //asm("/*"); - //asm("CPTX_BEGIN"); - //asm("vp.mma.sync.row.row.m16n16k16.s32 {%0, %1, %2, %3, %4, %5, %6, %7}, {%8, %9, %10, %11, %12, %13, %14, %15}, {%16, %17}, {%18, %19, %20, %21, %22, %23, %24, %25};" : - //"=r"(registers_d[0]), "=r"(registers_d[1]),"=r"(registers_d[2]),"=r"(registers_d[3]), - //"=r"(registers_d[4]),"=r"(registers_d[5]),"=r"(registers_d[6]),"=r"(registers_d[7]): - //"r"(registers_a[0]),"r"(registers_a[1]),"r"(registers_a[2]),"r"(registers_a[3]), - //"r"(registers_a[4]),"r"(registers_a[5]),"r"(registers_a[6]),"r"(registers_a[7]), - //"r"(registers_b[0]),"r"(registers_b[1]), - //"r"(registers_c[0]),"r"(registers_c[1]),"r"(registers_c[2]),"r"(registers_c[3]), - //"r"(registers_c[4]),"r"(registers_c[5]),"r"(registers_c[6]),"r"(registers_c[7]) - //); - //asm("CPTX_END"); - //asm("*/"); - - //B16 - //asm("/*"); - //asm("CPTX_BEGIN"); - //asm("vp.mma.sync.row.row.m16n16k16.s32 {%0, %1, %2, %3, %4, %5, %6, %7}, {%8, %9, %10, %11, %12, %13, %14, %15}, {%16, %17, %18, %19}, { %20, %21, %22, %23, %24, %25, %26, %27};" : - //"=r"(registers_d[0]), "=r"(registers_d[1]),"=r"(registers_d[2]),"=r"(registers_d[3]), - //"=r"(registers_d[4]),"=r"(registers_d[5]),"=r"(registers_d[6]),"=r"(registers_d[7]): - //"r"(registers_a[0]),"r"(registers_a[1]),"r"(registers_a[2]),"r"(registers_a[3]), - //"r"(registers_a[4]),"r"(registers_a[5]),"r"(registers_a[6]),"r"(registers_a[7]), - //"r"(registers_b[0]),"r"(registers_b[1]),"r"(registers_b[2]),"r"(registers_b[3]), - //"r"(registers_c[0]),"r"(registers_c[1]),"r"(registers_c[2]),"r"(registers_c[3]), - //"r"(registers_c[4]),"r"(registers_c[5]),"r"(registers_c[6]),"r"(registers_c[7]) - //); - //asm("CPTX_END"); - //asm("*/"); - - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.store.d.sync.row.m16n16k16.s32 [%0], {%1,%2,%3,%4,%5,%6,%7,%8},%9;" : - :"l"(d_int32) - "r"(registers_d[0]), "r"(registers_d[1]),"r"(registers_d[2]),"r"(registers_d[3]), - "r"(registers_d[4]),"r"(registers_d[5]),"r"(registers_d[6]),"r"(registers_d[7]), - "r"(M) - ); - asm("CPTX_END"); - asm("*/"); - //d_int32[0]=registers_d[0]; -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} -__global__ void convertFp16ToFp32 (float *out, half *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -__global__ void convertInt32ToInt4 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/8) { - out[idx] =(in[8*idx]&0xf)|(in[8*idx+1]&0xf)<<4|(in[8*idx+2]&0xf)<<8|(in[8*idx+3]&0xf)<<12| - (in[8*idx+4]&0xf)<<16|(in[8*idx+5]&0xf)<<20|(in[8*idx+6]&0xf)<<24|(in[8*idx+7]&0xf)<<28; - } -} -__global__ void convertInt32ToInt8 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/4) { - out[idx] =(in[4*idx]&0xff)|(in[4*idx+1]&0xff)<<8|(in[4*idx+2]&0xff)<<16|(in[4*idx+3]&0xff)<<24; - } -} -__global__ void convertInt32ToInt16 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/2) { - out[idx] =(in[2*idx]&0xffff)|(in[2*idx+1]&0xffff)<<16; - } -} - -__global__ void convertInt4ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=4*(idx%8); - int shft_mask=0xf<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/8]&shft_mask)>>shft_amt; - } -} -__global__ void convertInt8ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=8*(idx%4); - int shft_mask=0xff<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/4]&shft_mask)>>shft_amt; - } -} -__global__ void convertInt16ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=16*(idx%2); - int shft_mask=0xffff<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/2]&shft_mask)>>shft_amt; - } -} - -int main(int argc, char* argv[]) { - int *a_int32; - int *b_int32; - int *c_int32; - int *d_int32; - - int *a_int4; - int *b_int4; - int *a_int8; - int *b_int8; - int *a_int16; - int *b_int16; - - int *a_host_wmma; - int *b_host_wmma; - int *c_host_wmma; - int *d_host_wmma; - int *d_cal_host_wmma; - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - - srand (time(NULL)); - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - cudaErrCheck(cudaMalloc((void**)&a_int32, MATRIX_M * MATRIX_K * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&b_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&c_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&d_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&a_int4, MATRIX_M * MATRIX_K * sizeof(int)/8)); - cudaErrCheck(cudaMalloc((void**)&b_int4, MATRIX_K * MATRIX_N * sizeof(int)/8)); - cudaErrCheck(cudaMalloc((void**)&a_int8, MATRIX_M * MATRIX_K * sizeof(int)/4)); - cudaErrCheck(cudaMalloc((void**)&b_int8, MATRIX_K * MATRIX_N * sizeof(int)/4)); - cudaErrCheck(cudaMalloc((void**)&a_int16, MATRIX_M * MATRIX_K * sizeof(int)/2)); - cudaErrCheck(cudaMalloc((void**)&b_int16, MATRIX_K * MATRIX_N * sizeof(int)/2)); - - - a_host_wmma = (int *)malloc(MATRIX_M * MATRIX_K * sizeof(int)); - b_host_wmma = (int *)malloc(MATRIX_K * MATRIX_N * sizeof(int)); - c_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - d_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - d_cal_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - - printf("a_int32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]=random()%64; - printf("%d ",a_host_wmma[m*MATRIX_K+n]); - } - printf(";\n"); - } - - printf("b_int32\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]=random()%16; - printf("%d ",b_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - - printf("c_int32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_host_wmma[m*MATRIX_N+n]= random()%64; - d_cal_host_wmma[m*MATRIX_N+n]=0; - printf("%d ",c_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - - - cudaErrCheck(cudaMemcpy(a_int32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(int), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_int32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(int), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_int32,c_host_wmma, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyHostToDevice)); - - #ifdef TEST16 - convertInt32ToInt16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_int16, a_int32, MATRIX_M * MATRIX_K); - convertInt16ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, a_int16, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - #ifdef TEST8 - convertInt32ToInt8 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_int8, a_int32, MATRIX_M * MATRIX_K); - convertInt8ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, a_int8, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - #ifdef TEST4 - convertInt32ToInt4 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (b_int4, b_int32, MATRIX_M * MATRIX_K); - convertInt4ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, b_int4, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - convertInt32ToInt4 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (b_int4, b_int32, MATRIX_M * MATRIX_K); - //convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); - //convertFp32ToFp16 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (c_fp16, c_fp32, MATRIX_K * MATRIX_N); - - -//AAMIR printf("\nM = %d, N = %d, K = %d. \n", MATRIX_M, MATRIX_N, MATRIX_K); -//AAMIR -//AAMIR printf("Running with wmma...\n"); - cudaErrCheck(cudaEventRecord(startWMMA)); - v4p_example <<< 1, 32>>> (a_int32, b_int4, c_int32, d_int32, MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - - - // Error checking - printf("\nChecking results...\n"); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - - float wmmaTime; - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma took %fms\n", wmmaTime); - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - - int t=200000; - while(t-->0); - printf("D_CALCULATED\n"); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%d,",d_cal_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - printf("D_WMMA\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%d,",d_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - int suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])) - { - printf("ERROR:\n"); - suc=0; - } - } - } - if(suc==1) - printf("COMPLETED_SUCCESSFULLY\n"); - - - cudaErrCheck(cudaFree(a_int32)); - cudaErrCheck(cudaFree(b_int32)); - cudaErrCheck(cudaFree(c_int32)); - cudaErrCheck(cudaFree(d_int32)); - cudaErrCheck(cudaFree(a_int8)); - cudaErrCheck(cudaFree(b_int8)); - - free(a_host_wmma); - free(b_host_wmma); - free(c_host_wmma); - free(d_host_wmma); - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuda-kernels/v8p_genericMatrixMultiply.cu b/cuda-kernels/v8p_genericMatrixMultiply.cu deleted file mode 100644 index d96b07c..0000000 --- a/cuda-kernels/v8p_genericMatrixMultiply.cu +++ /dev/null @@ -1,385 +0,0 @@ -#include <stdio.h> -#include <curand.h> -#include <stdlib.h> - -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - -#define curandErrCheck(stat) { curandErrCheck_((stat), __FILE__, __LINE__); } -void curandErrCheck_(curandStatus_t stat, const char *file, int line) { - if (stat != CURAND_STATUS_SUCCESS) { - fprintf(stderr, "cuRand Error: %d %s %d\n", stat, file, line); - } -} - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (SIZE) -#define MATRIX_N (SIZE) -#define MATRIX_K (SIZE) - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - - - -__global__ void vp_example(int *a, int *b, int *c, int M, int N, int K ) { - // Leading dimensions. Packed with no transpositions. - int lda = M; - int ldb = K; - int ldc = M; - - // Tile using a 2D grid - int warpM = (blockIdx.x * blockDim.x + threadIdx.x) / warpSize; - int warpN = (blockIdx.y * blockDim.y + threadIdx.y); - - // Declare the fragments - int a_frag[8]; - int b_frag[8]; - int c_frag[8]; - int acc_frag[8]; - - acc_frag[0]=0; - acc_frag[1]=0; - acc_frag[2]=0; - acc_frag[3]=0; - acc_frag[4]=0; - acc_frag[5]=0; - acc_frag[6]=0; - acc_frag[7]=0; - - // Loop over k - for (int i = 0; i < K; i += WMMA_K) { - int aRow = warpM * WMMA_M; - int aCol = i; - - int bRow = i; - int bCol = warpN * WMMA_N; - - // Bounds checking - if (aRow < M && aCol < K && bRow < K && bCol < N) { - // Load the inputs - // vp::load_matrix_sync(a_frag, a + aRow * lda+ aCol , lda); - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.a.sync.row.m16n16k16.s32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8],%9;" : - "=r"(a_frag[0]), "=r"(a_frag[1]),"=r"(a_frag[2]),"=r"(a_frag[3]), - "=r"(a_frag[4]),"=r"(a_frag[5]),"=r"(a_frag[6]),"=r"(a_frag[7]): - "l"(a+aRow*lda+aCol),"r"(lda) - ); - asm("CPTX_END"); - asm("*/"); - //vp::load_matrix_sync(b_frag, b + bRow * ldb+ bCol , ldb); - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.b8.sync.row.m16n16k16.s32 {%0,%1},[%2],%3;" : - "=r"(b_frag[0]),"=r"(b_frag[1]): - "l"(b+bRow*ldb/4+bCol/4),"r"(ldb) - ); - asm("CPTX_END"); - asm("*/"); - - // Perform the matrix multiplication - //vp::mma_sync(acc_frag, a_frag, b_frag, acc_frag); - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.mma8.sync.row.row.m16n16k16.s32 {%0, %1, %2, %3, %4, %5, %6, %7}, {%8, %9, %10, %11, %12, %13, %14, %15}, {%16, %17}, {%18, %19, %20, %21, %22, %23, %24, %25};" : - "=r"(acc_frag[0]), "=r"(acc_frag[1]),"=r"(acc_frag[2]),"=r"(acc_frag[3]), - "=r"(acc_frag[4]),"=r"(acc_frag[5]),"=r"(acc_frag[6]),"=r"(acc_frag[7]): - "r"(a_frag[0]),"r"(a_frag[1]),"r"(a_frag[2]),"r"(a_frag[3]), - "r"(a_frag[4]),"r"(a_frag[5]),"r"(a_frag[6]),"r"(a_frag[7]), - "r"(b_frag[0]),"r"(b_frag[1]), - "r"(acc_frag[0]),"r"(acc_frag[1]),"r"(acc_frag[2]),"r"(acc_frag[3]), - "r"(acc_frag[4]),"r"(acc_frag[5]),"r"(acc_frag[6]),"r"(acc_frag[7]) - ); - asm("CPTX_END"); - asm("*/"); - - } - } - - // Load in the current value of c, scale it by beta, and add this our result scaled by alpha - int cRow = warpM * WMMA_M; - int cCol = warpN * WMMA_N; - - if (cRow < M && cCol < N) { - //vp::load_matrix_sync(c_frag, c + cRow*ldc + cCol , ldc, wmma::mem_row_major); - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.c.sync.row.m16n16k16.s32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8],%9;" : - "=r"(c_frag[0]), "=r"(c_frag[1]),"=r"(c_frag[2]),"=r"(c_frag[3]), - "=r"(c_frag[4]),"=r"(c_frag[5]),"=r"(c_frag[6]),"=r"(c_frag[7]): - "l"(c+cRow*ldc+cCol),"r"(ldc) - ); - asm("CPTX_END"); - asm("*/"); - - - for(int i=0; i < 8; i++) { - c_frag[i] = acc_frag[i] + c_frag[i]; - } - - // Store the output - //vp::store_matrix_sync(c + cRow *ldc + cCol , c_frag, ldc, wmma::mem_row_major); - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.store.d.sync.row.m16n16k16.s32 [%0], {%1,%2,%3,%4,%5,%6,%7,%8},%9;" : - :"l"(c+cRow*ldc+cCol), - "r"(c_frag[0]), "r"(c_frag[1]),"r"(c_frag[2]),"r"(c_frag[3]), - "r"(c_frag[4]),"r"(c_frag[5]),"r"(c_frag[6]),"r"(c_frag[7]), - "r"(ldc) - ); - asm("CPTX_END"); - asm("*/"); - } -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} -__global__ void convertFp16ToFp32 (float *out, half *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -__global__ void convertInt32ToInt4 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/8) { - out[idx] =(in[8*idx]&0xf)|(in[8*idx+1]&0xf)<<4|(in[8*idx+2]&0xf)<<8|(in[8*idx+3]&0xf)<<12| - (in[8*idx+4]&0xf)<<16|(in[8*idx+5]&0xf)<<20|(in[8*idx+6]&0xf)<<24|(in[8*idx+7]&0xf)<<28; - } -} -__global__ void convertInt32ToInt8 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/4) { - out[idx] =(in[4*idx]&0xff)|(in[4*idx+1]&0xff)<<8|(in[4*idx+2]&0xff)<<16|(in[4*idx+3]&0xff)<<24; - } -} -__global__ void convertInt32ToInt16 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/2) { - out[idx] =(in[2*idx]&0xffff)|(in[2*idx+1]&0xffff)<<16; - } -} - -__global__ void convertInt4ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=4*(idx%8); - int shft_mask=0xf<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/8]&shft_mask)>>shft_amt; - } -} -__global__ void convertInt8ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=8*(idx%4); - int shft_mask=0xff<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/4]&shft_mask)>>shft_amt; - } -} -__global__ void convertInt16ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=16*(idx%2); - int shft_mask=0xffff<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/2]&shft_mask)>>shft_amt; - } -} - -int main(int argc, char* argv[]) { - int *a_int32; - int *b_int32; - int *c_int32; - int *d_int32; - - int *a_int4; - int *b_int4; - int *a_int8; - int *b_int8; - int *a_int16; - int *b_int16; - - int *a_host_wmma; - int *b_host_wmma; - int *c_host_wmma; - int *d_host_wmma; - int *d_cal_host_wmma; - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - - srand(time(NULL)); - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - cudaErrCheck(cudaMalloc((void**)&a_int32, MATRIX_M * MATRIX_K * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&b_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&c_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&d_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&a_int4, MATRIX_M * MATRIX_K * sizeof(int)/8)); - cudaErrCheck(cudaMalloc((void**)&b_int4, MATRIX_K * MATRIX_N * sizeof(int)/8)); - cudaErrCheck(cudaMalloc((void**)&a_int8, MATRIX_M * MATRIX_K * sizeof(int)/4)); - cudaErrCheck(cudaMalloc((void**)&b_int8, MATRIX_K * MATRIX_N * sizeof(int)/4)); - cudaErrCheck(cudaMalloc((void**)&a_int16, MATRIX_M * MATRIX_K * sizeof(int)/2)); - cudaErrCheck(cudaMalloc((void**)&b_int16, MATRIX_K * MATRIX_N * sizeof(int)/2)); - - - a_host_wmma = (int *)malloc(MATRIX_M * MATRIX_K * sizeof(int)); - b_host_wmma = (int *)malloc(MATRIX_K * MATRIX_N * sizeof(int)); - c_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - d_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - d_cal_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - - printf("a_int32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]=random()%5; - printf("%d ",a_host_wmma[m*MATRIX_K+n]); - } - printf(";\n"); - } - - printf("b_int32\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]=random()%32; - printf("%d ",b_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - - printf("c_int32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_host_wmma[m*MATRIX_N+n]=random()%32; - d_cal_host_wmma[m*MATRIX_N+n]=0; - printf("%d ",c_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - - - cudaErrCheck(cudaMemcpy(a_int32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(int), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_int32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(int), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_int32,c_host_wmma, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyHostToDevice)); - - #ifdef TEST16 - convertInt32ToInt16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_int16, a_int32, MATRIX_M * MATRIX_K); - convertInt16ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, a_int16, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - #ifdef TEST8 - convertInt32ToInt8 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_int8, a_int32, MATRIX_M * MATRIX_K); - convertInt8ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, a_int8, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - #ifdef TEST4 - convertInt32ToInt4 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (b_int4, b_int32, MATRIX_M * MATRIX_K); - convertInt4ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, b_int4, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - convertInt32ToInt8 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (b_int8, b_int32, MATRIX_M * MATRIX_K); - - dim3 gridDim; - dim3 blockDim; - - // blockDim.x must be a multple of warpSize - // 128x4 means we have 16 warps and a block computes a 64x64 output tile - blockDim.x = 64; - blockDim.y = 2; - - gridDim.x = (MATRIX_M + (WMMA_M * blockDim.x / 32 - 1)) / (WMMA_M * blockDim.x / 32); - gridDim.y = (MATRIX_N + WMMA_N * blockDim.y - 1) / (WMMA_N * blockDim.y); - printf("GRID:X=%d,Y=%d\n",gridDim.x,gridDim.y); - printf("BLOCK:X=%d,Y=%d\n",blockDim.x,blockDim.y); - - - printf("Running with wmma...\n"); - cudaErrCheck(cudaEventRecord(startWMMA)); - vp_example <<< gridDim, blockDim >>> (a_int32, b_int8, c_int32, MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - - // Error checking - printf("\nChecking results...\n"); - cudaErrCheck(cudaMemcpy(d_host_wmma, c_int32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - - float wmmaTime; - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma took %fms\n", wmmaTime); - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - - int t=1000000; - while(t-->0); - printf("D_CALCULATED\n"); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%d,",d_cal_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - printf("D_WMMA\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%d,",d_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - int suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])) - { - printf("ERROR:\n"); - suc=0; - } - } - } - if(suc==1) - printf("COMPLETED_SUCCESSFULLY\n"); - - - cudaErrCheck(cudaFree(a_int32)); - cudaErrCheck(cudaFree(b_int32)); - cudaErrCheck(cudaFree(c_int32)); - cudaErrCheck(cudaFree(d_int32)); - cudaErrCheck(cudaFree(a_int8)); - cudaErrCheck(cudaFree(b_int8)); - - free(a_host_wmma); - free(b_host_wmma); - free(c_host_wmma); - free(d_host_wmma); - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuda-kernels/v8p_kernel.cu b/cuda-kernels/v8p_kernel.cu deleted file mode 100644 index 9bfcea7..0000000 --- a/cuda-kernels/v8p_kernel.cu +++ /dev/null @@ -1,359 +0,0 @@ -#include <stdio.h> -#include <curand.h> -#include<stdlib.h> - -// Define some error checking macros. -#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } -void cudaErrCheck_(cudaError_t stat, const char *file, int line) { - if (stat != cudaSuccess) { - fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); - } -} - -#define curandErrCheck(stat) { curandErrCheck_((stat), __FILE__, __LINE__); } -void curandErrCheck_(curandStatus_t stat, const char *file, int line) { - if (stat != CURAND_STATUS_SUCCESS) { - fprintf(stderr, "cuRand Error: %d %s %d\n", stat, file, line); - } -} - -#include <mma.h> -using namespace nvcuda; - -// Must be multiples of 16 for wmma code to work -#define MATRIX_M (16) -#define MATRIX_N (16) -#define MATRIX_K (16) - - -// The only dimensions currently supported by WMMA -const int WMMA_M = 16; -const int WMMA_N = 16; -const int WMMA_K = 16; - -__global__ void v4p_example(int *a_int32, int *b_int4, int *c,int *d_int32, int M, int N, int K) { - - int registers_a[8]; - int registers_b[8]; - int registers_c[8]; - int registers_d[8]; - int register_b; //contains 8 4bit b elements - int idx = blockDim.x * blockIdx.x + threadIdx.x; - - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.a.sync.row.m16n16k16.s32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8],%9;" : - "=r"(registers_a[0]), "=r"(registers_a[1]),"=r"(registers_a[2]),"=r"(registers_a[3]), - "=r"(registers_a[4]),"=r"(registers_a[5]),"=r"(registers_a[6]),"=r"(registers_a[7]): - "l"(a_int32),"r"(M) - ); - asm("CPTX_END"); - asm("*/"); - - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.b8.sync.row.m16n16k16.s32 {%0,%1},[%2],%3;" : - "=r"(registers_b[0]),"=r"(registers_b[1]): - "l"(b_int4),"r"(M) - ); - asm("CPTX_END"); - asm("*/"); - - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.load.c.sync.row.m16n16k16.s32 {%0,%1,%2,%3,%4,%5,%6,%7},[%8],%9;" : - "=r"(registers_c[0]), "=r"(registers_c[1]),"=r"(registers_c[2]),"=r"(registers_c[3]), - "=r"(registers_c[4]),"=r"(registers_c[5]),"=r"(registers_c[6]),"=r"(registers_c[7]): - "l"(c),"r"(M) - ); - asm("CPTX_END"); - asm("*/"); - //B4 - //asm("/*"); - //asm("CPTX_BEGIN"); - //asm("vp.mma.sync.row.row.m16n16k16.s32 {%0, %1, %2, %3, %4, %5, %6, %7}, {%8, %9, %10, %11, %12, %13, %14, %15}, {%16}, {%17, %18, %19, %20, %21, %22, %23, %24};" : - //"=r"(registers_d[0]), "=r"(registers_d[1]),"=r"(registers_d[2]),"=r"(registers_d[3]), - //"=r"(registers_d[4]),"=r"(registers_d[5]),"=r"(registers_d[6]),"=r"(registers_d[7]): - //"r"(registers_a[0]),"r"(registers_a[1]),"r"(registers_a[2]),"r"(registers_a[3]), - //"r"(registers_a[4]),"r"(registers_a[5]),"r"(registers_a[6]),"r"(registers_a[7]), - //"r"(registers_b[0]), - //"r"(registers_c[0]),"r"(registers_c[1]),"r"(registers_c[2]),"r"(registers_c[3]), - //"r"(registers_c[4]),"r"(registers_c[5]),"r"(registers_c[6]),"r"(registers_c[7]) - //); - //asm("CPTX_END"); - //asm("*/"); - - //B8 - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.mma8.sync.row.row.m16n16k16.s32 {%0, %1, %2, %3, %4, %5, %6, %7}, {%8, %9, %10, %11, %12, %13, %14, %15}, {%16, %17}, {%18, %19, %20, %21, %22, %23, %24, %25};" : - "=r"(registers_d[0]), "=r"(registers_d[1]),"=r"(registers_d[2]),"=r"(registers_d[3]), - "=r"(registers_d[4]),"=r"(registers_d[5]),"=r"(registers_d[6]),"=r"(registers_d[7]): - "r"(registers_a[0]),"r"(registers_a[1]),"r"(registers_a[2]),"r"(registers_a[3]), - "r"(registers_a[4]),"r"(registers_a[5]),"r"(registers_a[6]),"r"(registers_a[7]), - "r"(registers_b[0]),"r"(registers_b[1]), - "r"(registers_c[0]),"r"(registers_c[1]),"r"(registers_c[2]),"r"(registers_c[3]), - "r"(registers_c[4]),"r"(registers_c[5]),"r"(registers_c[6]),"r"(registers_c[7]) - ); - asm("CPTX_END"); - asm("*/"); - - //B16 - //asm("/*"); - //asm("CPTX_BEGIN"); - //asm("vp.mma.sync.row.row.m16n16k16.s32 {%0, %1, %2, %3, %4, %5, %6, %7}, {%8, %9, %10, %11, %12, %13, %14, %15}, {%16, %17, %18, %19}, { %20, %21, %22, %23, %24, %25, %26, %27};" : - //"=r"(registers_d[0]), "=r"(registers_d[1]),"=r"(registers_d[2]),"=r"(registers_d[3]), - //"=r"(registers_d[4]),"=r"(registers_d[5]),"=r"(registers_d[6]),"=r"(registers_d[7]): - //"r"(registers_a[0]),"r"(registers_a[1]),"r"(registers_a[2]),"r"(registers_a[3]), - //"r"(registers_a[4]),"r"(registers_a[5]),"r"(registers_a[6]),"r"(registers_a[7]), - //"r"(registers_b[0]),"r"(registers_b[1]),"r"(registers_b[2]),"r"(registers_b[3]), - //"r"(registers_c[0]),"r"(registers_c[1]),"r"(registers_c[2]),"r"(registers_c[3]), - //"r"(registers_c[4]),"r"(registers_c[5]),"r"(registers_c[6]),"r"(registers_c[7]) - //); - //asm("CPTX_END"); - //asm("*/"); - - asm("/*"); - asm("CPTX_BEGIN"); - asm("vp.store.d.sync.row.m16n16k16.s32 [%0], {%1,%2,%3,%4,%5,%6,%7,%8},%9;" : - :"l"(d_int32) - "r"(registers_d[0]), "r"(registers_d[1]),"r"(registers_d[2]),"r"(registers_d[3]), - "r"(registers_d[4]),"r"(registers_d[5]),"r"(registers_d[6]),"r"(registers_d[7]), - "r"(M) - ); - asm("CPTX_END"); - asm("*/"); - //d_int32[0]=registers_d[0]; -} - -__global__ void convertFp32ToFp16 (half *out, float *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} -__global__ void convertFp16ToFp32 (float *out, half *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n) { - out[idx] = in[idx]; - } -} - -__global__ void convertInt32ToInt4 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/8) { - out[idx] =(in[8*idx]&0xf)|(in[8*idx+1]&0xf)<<4|(in[8*idx+2]&0xf)<<8|(in[8*idx+3]&0xf)<<12| - (in[8*idx+4]&0xf)<<16|(in[8*idx+5]&0xf)<<20|(in[8*idx+6]&0xf)<<24|(in[8*idx+7]&0xf)<<28; - } -} -__global__ void convertInt32ToInt8 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/4) { - out[idx] =(in[4*idx]&0xff)|(in[4*idx+1]&0xff)<<8|(in[4*idx+2]&0xff)<<16|(in[4*idx+3]&0xff)<<24; - } -} -__global__ void convertInt32ToInt16 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - if (idx < n/2) { - out[idx] =(in[2*idx]&0xffff)|(in[2*idx+1]&0xffff)<<16; - } -} - -__global__ void convertInt4ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=4*(idx%8); - int shft_mask=0xf<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/8]&shft_mask)>>shft_amt; - } -} -__global__ void convertInt8ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=8*(idx%4); - int shft_mask=0xff<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/4]&shft_mask)>>shft_amt; - } -} -__global__ void convertInt16ToInt32 (int *out, int *in, int n) { - int idx = blockDim.x * blockIdx.x + threadIdx.x; - int shft_amt=16*(idx%2); - int shft_mask=0xffff<<shft_amt; - if (idx < n) { - out[idx]= (in[idx/2]&shft_mask)>>shft_amt; - } -} - -int main(int argc, char* argv[]) { - int *a_int32; - int *b_int32; - int *c_int32; - int *d_int32; - - int *a_int4; - int *b_int4; - int *a_int8; - int *b_int8; - int *a_int16; - int *b_int16; - - int *a_host_wmma; - int *b_host_wmma; - int *c_host_wmma; - int *d_host_wmma; - int *d_cal_host_wmma; - - cudaEvent_t startWMMA; - cudaEvent_t stopWMMA; - srand(time(NULL)); - - cudaErrCheck(cudaEventCreate(&startWMMA)); - cudaErrCheck(cudaEventCreate(&stopWMMA)); - - // Use tensor cores - cudaErrCheck(cudaMalloc((void**)&a_int32, MATRIX_M * MATRIX_K * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&b_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&c_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&d_int32, MATRIX_K * MATRIX_N * sizeof(int))); - cudaErrCheck(cudaMalloc((void**)&a_int4, MATRIX_M * MATRIX_K * sizeof(int)/8)); - cudaErrCheck(cudaMalloc((void**)&b_int4, MATRIX_K * MATRIX_N * sizeof(int)/8)); - cudaErrCheck(cudaMalloc((void**)&a_int8, MATRIX_M * MATRIX_K * sizeof(int)/4)); - cudaErrCheck(cudaMalloc((void**)&b_int8, MATRIX_K * MATRIX_N * sizeof(int)/4)); - cudaErrCheck(cudaMalloc((void**)&a_int16, MATRIX_M * MATRIX_K * sizeof(int)/2)); - cudaErrCheck(cudaMalloc((void**)&b_int16, MATRIX_K * MATRIX_N * sizeof(int)/2)); - - - a_host_wmma = (int *)malloc(MATRIX_M * MATRIX_K * sizeof(int)); - b_host_wmma = (int *)malloc(MATRIX_K * MATRIX_N * sizeof(int)); - c_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - d_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - d_cal_host_wmma = (int *)malloc(MATRIX_M * MATRIX_N * sizeof(int)); - - printf("a_int32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_K;n++){ - a_host_wmma[m*MATRIX_K+n]=random()%10; - printf("%d ",a_host_wmma[m*MATRIX_K+n]); - } - printf(";\n"); - } - - printf("b_int32\n"); - for(int m=0;m<MATRIX_K;m++){ - for(int n=0;n<MATRIX_N;n++){ - b_host_wmma[m*MATRIX_N+n]=random()%5; - printf("%d ",b_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - - printf("c_int32\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - c_host_wmma[m*MATRIX_N+n]=random()%64; - d_cal_host_wmma[m*MATRIX_N+n]=0; - printf("%d ",c_host_wmma[m*MATRIX_N+n]); - } - printf(";\n"); - } - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - for(int k=0;k<MATRIX_K;k++){ - d_cal_host_wmma[m*MATRIX_N+n]+= a_host_wmma[m*MATRIX_K+k]*b_host_wmma[k*MATRIX_K+n]; - } - d_cal_host_wmma[m*MATRIX_N+n]+=c_host_wmma[m*MATRIX_N+n]; - } - } - - - cudaErrCheck(cudaMemcpy(a_int32,a_host_wmma, MATRIX_M * MATRIX_K * sizeof(int), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(b_int32,b_host_wmma, MATRIX_K * MATRIX_N * sizeof(int), cudaMemcpyHostToDevice)); - cudaErrCheck(cudaMemcpy(c_int32,c_host_wmma, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyHostToDevice)); - - #ifdef TEST16 - convertInt32ToInt16 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_int16, a_int32, MATRIX_M * MATRIX_K); - convertInt16ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, a_int16, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - #ifdef TEST8 - convertInt32ToInt8 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (a_int8, a_int32, MATRIX_M * MATRIX_K); - convertInt8ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, a_int8, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - #ifdef TEST4 - convertInt32ToInt4 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (b_int4, b_int32, MATRIX_M * MATRIX_K); - convertInt4ToInt32 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (d_int32, b_int4, MATRIX_M * MATRIX_K); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(int), cudaMemcpyDeviceToHost)); - #endif - convertInt32ToInt8 <<< (MATRIX_M * MATRIX_K + 255) / 256, 256 >>> (b_int8, b_int32, MATRIX_M * MATRIX_K); - //convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); - //convertFp32ToFp16 <<< (MATRIX_M * MATRIX_N + 255) / 256, 256 >>> (c_fp16, c_fp32, MATRIX_K * MATRIX_N); - - -//AAMIR printf("\nM = %d, N = %d, K = %d. \n", MATRIX_M, MATRIX_N, MATRIX_K); -//AAMIR -//AAMIR printf("Running with wmma...\n"); - cudaErrCheck(cudaEventRecord(startWMMA)); - v4p_example <<< 1, 32>>> (a_int32, b_int8, c_int32, d_int32, MATRIX_M, MATRIX_N, MATRIX_K); - cudaErrCheck(cudaEventRecord(stopWMMA)); - cudaErrCheck(cudaEventSynchronize(stopWMMA)); - - - // Error checking - printf("\nChecking results...\n"); - cudaErrCheck(cudaMemcpy(d_host_wmma, d_int32, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); - - float wmmaTime; - cudaErrCheck(cudaEventElapsedTime(&wmmaTime, startWMMA, stopWMMA)); - printf("wmma took %fms\n", wmmaTime); - - cudaErrCheck(cudaEventDestroy(startWMMA)); - cudaErrCheck(cudaEventDestroy(stopWMMA)); - - int t=2000000; - while(t-->0); - printf("D_CALCULATED\n"); - - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%d,",d_cal_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - printf("D_WMMA\n"); - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - printf("%d,",d_host_wmma[m*MATRIX_N+n]); - } - printf("\n"); - } - int suc=1; - for(int m=0;m<MATRIX_M;m++){ - for(int n=0;n<MATRIX_N;n++){ - if(abs(d_cal_host_wmma[m*MATRIX_N+n]-d_host_wmma[m*MATRIX_N+n])) - { - printf("ERROR:\n"); - suc=0; - } - } - } - if(suc==1) - printf("COMPLETED_SUCCESSFULLY\n"); - - - cudaErrCheck(cudaFree(a_int32)); - cudaErrCheck(cudaFree(b_int32)); - cudaErrCheck(cudaFree(c_int32)); - cudaErrCheck(cudaFree(d_int32)); - cudaErrCheck(cudaFree(a_int8)); - cudaErrCheck(cudaFree(b_int8)); - - free(a_host_wmma); - free(b_host_wmma); - free(c_host_wmma); - free(d_host_wmma); - cudaErrCheck(cudaDeviceReset()); - return 0; -} - - diff --git a/cuobjdump_to_ptxplus/cuobjdumpInst.cc b/cuobjdump_to_ptxplus/cuobjdumpInst.cc index c74d2d8..392f829 100644 --- a/cuobjdump_to_ptxplus/cuobjdumpInst.cc +++ b/cuobjdump_to_ptxplus/cuobjdumpInst.cc @@ -2083,7 +2083,7 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list<std::string> labelList, std: else { printf("Unknown Instruction: "); - printf(m_base.c_str()); + printf("%s",m_base.c_str()); printf("\n"); output("Unknown Instruction: "); output(m_base); diff --git a/cutlass-example/Makefile b/cutlass-example/Makefile deleted file mode 100644 index f72b732..0000000 --- a/cutlass-example/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -# Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of NVIDIA CORPORATION nor the names of its -# contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY -# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY -# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -CC = nvcc -src = $(wildcard *.cu) -obj = $(src:.c=.o) -INC_DIR = ./ - - -#LDFLAGS = -g -G --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -I$(INC_DIR) -#LDFLAGS = -O0 -Xcicc -O0 -Xptxas -O0 --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -I$(INC_DIR) -LDFLAGS = --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -I$(INC_DIR) - -myprog: $(obj) - $(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) - -clean: - rm -rf gemm_tt_* - rm -rf host_results_* - rm -rf gpgpusim_power_report__* - rm -rf _cuobjdump* - rm -rf gpgpu_inst_stats.txt - rm -rf myprog - echo Clean done diff --git a/cutlass-example/command_line.h b/cutlass-example/command_line.h deleted file mode 100644 index 8f2b17a..0000000 --- a/cutlass-example/command_line.h +++ /dev/null @@ -1,254 +0,0 @@ -/****************************************************************************** - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are not permitted. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ******************************************************************************/ - -#pragma once - -/** - * \file - * Utility for parsing command line arguments - */ - -#include <iostream> -#include <limits> -#include <sstream> -#include <string> -#include <vector> - -#include <cuda_runtime.h> - -namespace cutlass { - -/****************************************************************************** - * command_line - ******************************************************************************/ - -/** - * Utility for parsing command line arguments - */ -struct CommandLine { - std::vector<std::string> keys; - std::vector<std::string> values; - std::vector<std::string> args; - - /** - * Constructor - */ - CommandLine(int argc, const char** argv) : keys(10), values(10) { - using namespace std; - - for (int i = 1; i < argc; i++) { - string arg = argv[i]; - - if ((arg[0] != '-') || (arg[1] != '-')) { - args.push_back(arg); - continue; - } - - string::size_type pos; - string key, val; - if ((pos = arg.find('=')) == string::npos) { - key = string(arg, 2, arg.length() - 2); - val = ""; - } else { - key = string(arg, 2, pos - 2); - val = string(arg, pos + 1, arg.length() - 1); - } - - keys.push_back(key); - values.push_back(val); - } - } - - /** - * Checks whether a flag "--<flag>" is present in the commandline - */ - bool check_cmd_line_flag(const char* arg_name) const { - using namespace std; - - for (int i = 0; i < int(keys.size()); ++i) { - if (keys[i] == string(arg_name)) return true; - } - return false; - } - - /** - * Returns number of naked (non-flag and non-key-value) commandline parameters - */ - template <typename value_t> - int num_naked_args() const { - return args.size(); - } - - /** - * Returns the commandline parameter for a given index (not including flags) - */ - template <typename value_t> - void get_cmd_line_argument(int index, value_t& val) const { - using namespace std; - if (index < args.size()) { - istringstream str_stream(args[index]); - str_stream >> val; - } - } - - /** - * Returns the commandline parameter for a given index (not including flags) - */ - void get_cmd_line_argument(const char* arg_name, bool& val, bool _default = true) const { - val = _default; - if (check_cmd_line_flag(arg_name)) { - std::string value; - get_cmd_line_argument(arg_name, value); - - val = !(value == "0" || value == "false"); - } - } - - /** - * Returns the value specified for a given commandline parameter --<flag>=<value> - */ - template <typename value_t> - void get_cmd_line_argument(const char* arg_name, - value_t& val, - value_t const& _default = value_t()) const { - using namespace std; - - val = _default; - - for (int i = 0; i < int(keys.size()); ++i) { - if (keys[i] == string(arg_name)) { - istringstream str_stream(values[i]); - str_stream >> val; - } - } - } - - /** - * Returns the values specified for a given commandline parameter --<flag>=<value>,<value>* - */ - template <typename value_t> - void get_cmd_line_arguments(const char* arg_name, - std::vector<value_t>& vals, - char sep = ',') const { - using namespace std; - - if (check_cmd_line_flag(arg_name)) { - // Clear any default values - vals.clear(); - - // Recover from multi-value string - for (int i = 0; i < keys.size(); ++i) { - if (keys[i] == string(arg_name)) { - string val_string(values[i]); - istringstream str_stream(val_string); - string::size_type old_pos = 0; - string::size_type new_pos = 0; - - // Iterate <sep>-delimited values - value_t val; - while ((new_pos = val_string.find(sep, old_pos)) != string::npos) { - if (new_pos != old_pos) { - str_stream.width(new_pos - old_pos); - str_stream >> val; - vals.push_back(val); - } - - // skip over delimiter - str_stream.ignore(1); - old_pos = new_pos + 1; - } - - // Read last value - str_stream >> val; - vals.push_back(val); - } - } - } - } - - /** - * Returns the values specified for a given commandline parameter - * --<flag>=<key:value>,<key:value>* - */ - void get_cmd_line_argument_pairs(const char* arg_name, - std::vector<std::pair<std::string, std::string> >& tokens, - char delim = ',', - char sep = ':') const { - if (check_cmd_line_flag(arg_name)) { - std::string value; - get_cmd_line_argument(arg_name, value); - - tokenize(tokens, value, delim, sep); - } - } - - /** - * The number of pairs parsed - */ - int parsed_argc() const { return (int)keys.size(); } - - //------------------------------------------------------------------------- - // Utility functions - //------------------------------------------------------------------------- - - /// Tokenizes a comma-delimited list of string pairs delimited by ':' - static void tokenize(std::vector<std::pair<std::string, std::string> >& tokens, - std::string const& str, - char delim = ',', - char sep = ':') { - // Home-built to avoid Boost dependency - size_t s_idx = 0; - size_t d_idx = std::string::npos; - while (s_idx < str.size()) { - d_idx = str.find_first_of(delim, s_idx); - - size_t end_idx = (d_idx != std::string::npos ? d_idx : str.size()); - size_t sep_idx = str.find_first_of(sep, s_idx); - size_t offset = 1; - if (sep_idx == std::string::npos || sep_idx >= end_idx) { - sep_idx = end_idx; - offset = 0; - } - - std::pair<std::string, std::string> item( - str.substr(s_idx, sep_idx - s_idx), - str.substr(sep_idx + offset, end_idx - sep_idx - offset)); - - tokens.push_back(item); - s_idx = end_idx + 1; - } - } - - /// Tokenizes a comma-delimited list of string pairs delimited by ':' - static void tokenize(std::vector<std::string>& tokens, - std::string const& str, - char delim = ',', - char sep = ':') { - typedef std::vector<std::pair<std::string, std::string> > TokenVector; - typedef TokenVector::const_iterator token_iterator; - - std::vector<std::pair<std::string, std::string> > token_pairs; - tokenize(token_pairs, str, delim, sep); - for (token_iterator tok = token_pairs.begin(); tok != token_pairs.end(); ++tok) { - tokens.push_back(tok->first); - } - } -}; - -} // namespace cutlass diff --git a/cutlass-example/config_fermi_islip.icnt b/cutlass-example/config_fermi_islip.icnt deleted file mode 100644 index 3b8b496..0000000 --- a/cutlass-example/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 102; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/cutlass-example/cutlass/convert.h b/cutlass-example/cutlass/convert.h deleted file mode 100644 index 933d68a..0000000 --- a/cutlass-example/cutlass/convert.h +++ /dev/null @@ -1,102 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! - \file - \brief Defines conversion operations among Fragments of different base type. -*/ -#pragma once - -#include <cutlass/fragment.h> - -namespace cutlass { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename InputFragment_, typename OutputFragment_> -struct Convert {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename InputScalar_, typename OutputScalar_, int kScalars_> -struct Convert<Fragment<InputScalar_, kScalars_>, Fragment<OutputScalar_, kScalars_> > { - /// The input fragment. - typedef Fragment<InputScalar_, kScalars_> InputFragment; - /// The output fragment. - typedef Fragment<OutputScalar_, kScalars_> OutputFragment; - - /// Ctor. - CUTLASS_DEVICE Convert() {} - - /// Transform a fragment. - CUTLASS_DEVICE void transform(InputFragment const& src, OutputFragment& dst) { - transform(src, 0, dst); - } - - /// Transform a fragment. - template <typename Fragment_> - CUTLASS_DEVICE void transform(Fragment_ const& src, int offset, OutputFragment& dst) { - for (int i = 0; i < kScalars_; ++i) { - dst[i] = static_cast<OutputScalar_>(src[i + offset]); - } - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Fragment_> -struct Copy { - /// The input fragment. - typedef Fragment_ InputFragment; - /// The output fragment. - typedef Fragment_ OutputFragment; - - /// Ctor. - CUTLASS_DEVICE Copy() {} - - /// Transform a fragment. - CUTLASS_DEVICE void transform(Fragment_ const& src, Fragment_& dst) { transform(src, 0, dst); } - - /// Transform a fragment. - template <typename InputFragment_> - CUTLASS_DEVICE void transform(InputFragment_ const& src, int offset, Fragment_& dst) { - if (sizeof(typename Fragment_::Element) == 8) { - uint64_t const* src_ptr = reinterpret_cast<uint64_t const*>(&src[offset]); - uint64_t* dst_ptr = reinterpret_cast<uint64_t*>(&dst[0]); - for (int i = 0; i < sizeof(Fragment_) / 8; ++i) { - dst_ptr[i] = src_ptr[i]; - } - } else { - uint32_t const* src_ptr = reinterpret_cast<uint32_t const*>(&src[offset]); - uint32_t* dst_ptr = reinterpret_cast<uint32_t*>(&dst[0]); - for (int i = 0; i < sizeof(Fragment_) / 4; ++i) { - dst_ptr[i] = src_ptr[i]; - } - } - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace cutlass diff --git a/cutlass-example/cutlass/coord.h b/cutlass-example/cutlass/coord.h deleted file mode 100644 index 431c9bf..0000000 --- a/cutlass-example/cutlass/coord.h +++ /dev/null @@ -1,287 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief A Coord is a coordinate of arbitrary rank into a tensor or matrix -*/ - -#pragma once - -#include <cutlass/cutlass.h> - -namespace cutlass { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Describes identity elements -struct Identity { - /// Enumeration describing identity elements. Value assignments are significant. - /// Feel free to add or multiply by these, respectively. - enum Kind { Additive = 0, Multiplicative = 1 }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Statically-sized array specifying Coords within a tensor -template <int N_> -struct Coord { - // - // Type and constant definitions - // - - static int const N = N_; - - // - // Data members - // - - /// Indices - int idx[N]; - - // - // Methods - // - - /// Default ctor initializes uniformly - CUTLASS_HOST_DEVICE - Coord(int value = 0) { - for (int i = 0; i < N; ++i) { - idx[i] = value; - } - } - - /// Constructs from an array of integers - CUTLASS_HOST_DEVICE - Coord(int _idx[]) { - for (int i = 0; i < N; ++i) { - idx[i] = _idx[i]; - } - } - - /// Element-wise addition - CUTLASS_HOST_DEVICE - Coord operator+(Coord const& b) const { - Coord c; - for (int i = 0; i < N; ++i) { - c.idx[i] = idx[i] + b.idx[i]; - } - return c; - } - - /// Element-wise subtraction - CUTLASS_HOST_DEVICE - Coord operator-(Coord const& b) const { - Coord c; - for (int i = 0; i < N; ++i) { - c.idx[i] = idx[i] - b.idx[i]; - } - return c; - } - - /// Element-wise multiplication - CUTLASS_HOST_DEVICE - Coord operator*(Coord const& b) const { - Coord c; - for (int i = 0; i < N; ++i) { - c.idx[i] = idx[i] * b.idx[i]; - } - return c; - } - - /// Element-wise division - CUTLASS_HOST_DEVICE - Coord operator/(Coord const& b) const { - Coord c; - for (int i = 0; i < N; ++i) { - c.idx[i] = idx[i] / b.idx[i]; - } - return c; - } - - /// In-place addition - CUTLASS_HOST_DEVICE - Coord& operator+=(Coord const& b) { - for (int i = 0; i < N; ++i) { - idx[i] += b.idx[i]; - } - return *this; - } - - /// In-place subtraction - CUTLASS_HOST_DEVICE - Coord& operator-=(Coord const& b) { - for (int i = 0; i < N; ++i) { - idx[i] -= b.idx[i]; - } - return *this; - } - - /// In-place multiplication - CUTLASS_HOST_DEVICE - Coord& operator*=(Coord const& b) { - for (int i = 0; i < N; ++i) { - idx[i] *= b.idx[i]; - } - return *this; - } - - /// In-place division - CUTLASS_HOST_DEVICE - Coord& operator/=(Coord const& b) { - for (int i = 0; i < N; ++i) { - idx[i] /= b.idx[i]; - } - return *this; - } - - /// Member access operator - CUTLASS_HOST_DEVICE int& operator[](int dim) { return idx[dim]; } - - /// Member access operator - CUTLASS_HOST_DEVICE int const& operator[](int dim) const { return idx[dim]; } - - /// Computes the dot product of two Coord instances - template <typename T> - CUTLASS_HOST_DEVICE T dot(Coord const& b, T sum) const { - for (int i = 0; i < N; ++i) { - sum += idx[i] * b.idx[i]; - } - return sum; - } - - /// Computes the dot product of two Coord instances - template <typename T> - CUTLASS_HOST_DEVICE T dot(Coord const& b) const { - T sum = T(0); - for (int i = 0; i < N; ++i) { - sum += idx[i] * b.idx[i]; - } - return sum; - } - - /// Gets the index of a given Coord element - template <int Dim> - CUTLASS_HOST_DEVICE int& at() { - return idx[Dim]; - } - - /// Access via index; may limit unrolling potential - CUTLASS_HOST_DEVICE - int& at(int dim) { return idx[dim]; } - - /// Gets the index of a given Coord element - template <int Dim> - CUTLASS_HOST_DEVICE int const& at() const { - return idx[Dim]; - } - - /// Access via index; may limit unrolling potential - CUTLASS_HOST_DEVICE - int const& at(int dim) const { return idx[dim]; } - - /// Determines if two Coord<> objects are equal - CUTLASS_HOST_DEVICE - bool operator==(Coord<N> const& b) const { - bool equal = true; - for (int i = 0; equal && i < N; ++i) { - equal = (idx[i] == b.idx[i]); - } - return equal; - } - - /// Not equal - CUTLASS_HOST_DEVICE - bool operator!=(Coord<N> const& b) const { return !(*this == b); } - - /// Clamps a coordinate to a range specified by maximum and minimum values - CUTLASS_HOST_DEVICE - Coord& clamp(Coord<N> const& max, Coord<N> const& min = Coord<N>()) { - for (int i = 0; i < N; ++i) { - idx[i] = __NV_STD_MAX(__NV_STD_MIN(idx[i], max.idx[i]), min.idx[i]); - } - return *this; - } - - /// Returns the product of all elements - CUTLASS_HOST_DEVICE - int count() const { - int product = idx[0]; - for (int i = 1; i < N; ++i) { - product *= idx[i]; - } - return product; - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Helper to make a 2-element coordinate -CUTLASS_HOST_DEVICE -Coord<1> make_Coord(int _0) { - int values[1] = {_0}; - return Coord<1>(values); -} - -/// Helper to make a 2-element coordinate -CUTLASS_HOST_DEVICE -Coord<2> make_Coord(int _0, int _1) { - int values[2] = {_0, _1}; - return Coord<2>(values); -} - -/// Helper to make a 3-element coordinate -CUTLASS_HOST_DEVICE -Coord<3> make_Coord(int _0, int _1, int _2) { - int values[3] = {_0, _1, _2}; - return Coord<3>(values); -} - -/// Helper to make a 4-element coordinate -CUTLASS_HOST_DEVICE -Coord<4> make_Coord(int _0, int _1, int _2, int _3) { - int values[4] = {_0, _1, _2, _3}; - return Coord<4>(values); -} - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Getter -CUTLASS_HOST_DEVICE -Coord<2> get_Coord_hw(Coord<3> const& coord) { return make_Coord(coord[1], coord[2]); } - -/// Getter -CUTLASS_HOST_DEVICE -Coord<2> get_Coord_hw(Coord<4> const& coord) { return make_Coord(coord[1], coord[2]); } - -/// Getter -CUTLASS_HOST_DEVICE -Coord<3> get_Coord_hwc(Coord<4> const& coord) { return make_Coord(coord[1], coord[2], coord[3]); } - -/// Getter -CUTLASS_HOST_DEVICE -Coord<3> get_Coord_dhw(Coord<4> const& coord) { return make_Coord(coord[0], coord[1], coord[2]); } - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace cutlass diff --git a/cutlass-example/cutlass/core_io.h b/cutlass-example/cutlass/core_io.h deleted file mode 100644 index cceea4c..0000000 --- a/cutlass-example/cutlass/core_io.h +++ /dev/null @@ -1,44 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -#pragma once - -/*! \file - \brief Helpers for printing cutlass/core objects -*/ - -#pragma once - -#include <iosfwd> -#include <typeinfo> - -#include <cutlass/coord.h> - -template <int Rank> -std::ostream& operator<<(std::ostream& out, cutlass::Coord<Rank> const& coord) { - for (int i = 0; i < Rank; ++i) { - out << (i ? ", " : "") << coord.idx[i]; - } - return out; -} diff --git a/cutlass-example/cutlass/cutlass.h b/cutlass-example/cutlass/cutlass.h deleted file mode 100644 index 19600ec..0000000 --- a/cutlass-example/cutlass/cutlass.h +++ /dev/null @@ -1,73 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ - -/*! \file - \brief Basic include for CUTLASS macros -*/ - -#pragma once - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -#define CUTLASS_MAJOR 1 -#define CUTLASS_MINOR 0 -#define CUTLASS_PATCH 1 -#define CUTLASS_VERSION ((CUTLASS_MAJOR)*100 + (CUTLASS_MINOR)*10 + CUTLASS_PATCH) - -#ifdef __NVCC__ -#define CUTLASS_HOST_DEVICE __forceinline__ __device__ __host__ -#define CUTLASS_DEVICE __forceinline__ __device__ -#elif defined(__CUDACC_RTC__) -#define CUTLASS_HOST_DEVICE __forceinline__ __device__ -#define CUTLASS_DEVICE __forceinline__ __device__ -#else -#define CUTLASS_HOST_DEVICE -// CUTLASS_DEVICE is an error if not compiling device code -#endif - -// CUTLASS_PRAGMA_UNROLL inserts a CUTLASS_PRAGMA_UNROLL if supported by the compiler -#if defined(__CUDA_ARCH__) -#if defined(_MSC_VER) -#define CUTLASS_PRAGMA_UNROLL __pragma("unroll") -#define CUTLASS_PRAGMA_NO_UNROLL __pragma("unroll 1") -#else -#define CUTLASS_PRAGMA_UNROLL _Pragma("unroll") -#define CUTLASS_PRAGMA_NO_UNROLL _Pragma("unroll 1") -#endif -#else -#define CUTLASS_PRAGMA_UNROLL -#define CUTLASS_PRAGMA_NO_UNROLL -#endif - -#define CUTLASS_ASSERT(x) assert(x) - -namespace cutlass { - -/// NVIDIA GPU Warp size -static const int kWarpSize = 32; - -} // namespace cutlass - -//////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/cutlass-example/cutlass/fragment.h b/cutlass-example/cutlass/fragment.h deleted file mode 100644 index 886b114..0000000 --- a/cutlass-example/cutlass/fragment.h +++ /dev/null @@ -1,278 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines Fragment, a statically-sized array for storing parts of matrices within a - thread's registers. -*/ -#pragma once - -#include <assert.h> -#include <cutlass/shape.h> -#include <cutlass/util/cutlass_math.h> -#include <cutlass/vector.h> - -namespace cutlass { - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/*!@defgroup fragment_concept Fragment Concept -@{ - -\ref fragment_concept is a statically sized array for storing parts of tiles held by individual CUDA -threads. - -@par \ref fragment_concept - Types satisfying \ref fragment_concept define the following members - - <b>Element</b> - type of each access held within the fragment - - <b>kElements</b> - number of elements stored by the fragment - - <b>clear()</b> - overwrites the fragment storage with zeros - - <b>Element & operator[](int i)</b> - by-reference access of the ith element - - <b>Element const & operator[](int i) const</b> - const by-reference access of the ith element -@} -*/ - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/*!@defgroup fragment_iterator_concept Fragment Iterator Concept -@{ - -\ref fragment_iterator_concept provides structured access to the elements within a fragment with an -optional bitcast to the desired access type - -@par \ref fragment_iterator_concept - Types satisfying \ref fragment_iterator_concept define the following members - - <b>AccessType& operator[](int i)</b> - provides access to the ith element of the fragment - - <b>AccessType& at(int d, int h, int w, int c)</b> - applies \ref layout_concept to fragment and -provides access to element at (d, h, w, c) - -@} -*/ - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <int kAlignment_> -struct StorageType { - typedef uint64_t Type; -}; -template <> -struct StorageType<4> { - typedef uint32_t Type; -}; -template <> -struct StorageType<2> { - typedef uint16_t Type; -}; -template <> -struct StorageType<1> { - typedef uint8_t Type; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/** -* @brief A template defining \ref fragment_concept -* @concept{fragment_concept} -*/ -template <typename Element_, int kElements_, size_t kAlignment_ = 16> -struct Fragment : public AlignedStruct<kAlignment_> { - /// Make sure the alignment makes sense wrt the size of elements. - static_assert(kAlignment_ == 16 || kAlignment_ >= sizeof(Element_), "Alignment is too small"); - /// Alignment must be a power of two - static_assert(is_pow2<kAlignment_>::value, "Alignment must be a power of two"); - - /// This class. - typedef Fragment<Element_, kElements_> This_; - /// The element. - typedef Element_ Element; - /// The number of elements. - static int const kElements = kElements_; - - /// Clear a fragment. - CUTLASS_DEVICE void clear() { - // Avoid element-wise access for sub 32b element type - if (kAlignment_ >= 8 && (kElements * sizeof(Element)) % 8 == 0) { - uint64_t* ptr = reinterpret_cast<uint64_t*>(storage); - for (int i = 0; i < (kElements * sizeof(Element)) / 8; ++i) { - ptr[i] = uint64_t(0); - } - } else if (kAlignment_ >= 4 && (kElements * sizeof(Element)) % 4 == 0) { - uint32_t* ptr = reinterpret_cast<uint32_t*>(storage); - for (int i = 0; i < (kElements * sizeof(Element)) / 4; ++i) { - ptr[i] = uint32_t(0); - } - } else if (kAlignment_ >= 2 && (kElements * sizeof(Element)) % 2 == 0) { - uint16_t* ptr = reinterpret_cast<uint16_t*>(storage); - for (int i = 0; i < (kElements * sizeof(Element)) / 2; ++i) { - ptr[i] = uint16_t(0); - } - } else { - for (int i = 0; i < kElements; ++i) { - storage[i] = 0; - } - } - } - - /// The accessor. - CUTLASS_DEVICE Element& operator[](int i) { - assert(i < kElements_); - return reinterpret_cast<Element*>(storage)[i]; - } - - /// The accessor. - CUTLASS_DEVICE Element const& operator[](int i) const { - assert(i < kElements_); - return reinterpret_cast<Element const*>(storage)[i]; - } - - private: - /// Storage type to use for Elements - typedef typename StorageType<kAlignment_>::Type StorageType; - - /// Number of elements in the storage - static int const kStorageCount = - (sizeof(Element_) * kElements_ + sizeof(StorageType) - 1) / sizeof(StorageType); - /// The storage. - StorageType storage[kStorageCount]; - - /// Ensure that there's enough storage for all elements - static_assert(sizeof(StorageType) <= kAlignment_, "StorageType is too big for given alignment"); -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/** -* @brief A template defining \ref fragment_iterator_concept -* @concept{fragment_iterator_concept} -*/ -template <typename Fragment_, typename Iterations_, typename AccessType_> -struct FragmentIterator { - /// This class. - typedef FragmentIterator<Fragment_, Iterations_, AccessType_> This_; - /// The fragment. - typedef Fragment_ Fragment; - /// The number of iterations. - typedef Iterations_ Iterations; - /// The access type. - typedef AccessType_ AccessType; - - /// The element. - typedef typename Fragment::Element Element; - /// The number of elements per access. - static int const kElementsPerAccess = (int)(sizeof(AccessType) / sizeof(Element)); - /// The shape of the the fragment. - typedef typename ShapeMul<Iterations, Shape<1, 1, 1, kElementsPerAccess> >::Shape FragmentShape; - /// The linear strides for iterations. - typedef typename ShapeStrides<FragmentShape, kElementsPerAccess>::Shape Strides; - - /// Ctor. - template <typename OtherFragment_> - CUTLASS_DEVICE FragmentIterator(OtherFragment_& fragment, int offset = 0) - : pointer(reinterpret_cast<Element*>(&fragment[offset])) { - static_assert(OtherFragment_::kElements >= Fragment::kElements, ""); - } - - /// The accessor. - CUTLASS_DEVICE AccessType const& at(int d, int h, int w, int c = 0) const { - int const imm = ComputeOffsetFromStrides<Strides>::get(d, h, w, c); - return reinterpret_cast<AccessType const&>(pointer[imm]); - } - - /// The accessor. - CUTLASS_DEVICE AccessType& at(int d, int h, int w, int c = 0) { - int const imm = ComputeOffsetFromStrides<Strides>::get(d, h, w, c); - return reinterpret_cast<AccessType&>(pointer[imm]); - } - - /// The accessor. - CUTLASS_DEVICE AccessType const& operator[](int i) const { - return reinterpret_cast<AccessType const&>(pointer[i * kElementsPerAccess]); - } - - /// The accessor. - CUTLASS_DEVICE AccessType& operator[](int i) { - return reinterpret_cast<AccessType&>(pointer[i * kElementsPerAccess]); - } - - /// Is the iterator valid? - CUTLASS_DEVICE bool valid(int d, int h, int w, int c) const { return true; } - - /// The pointer. - Element* pointer; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Fragment_, typename Iterations_, typename AccessType_> -struct FragmentConstIterator { - /// This class. - typedef FragmentIterator<Fragment_, Iterations_, AccessType_> This_; - /// The fragment. - typedef Fragment_ Fragment; - /// The number of iterations. - typedef Iterations_ Iterations; - /// The access type. - typedef AccessType_ AccessType; - - /// The element. - typedef typename Fragment::Element Element; - /// The number of elements per access. - static int const kElementsPerAccess = (int)(sizeof(AccessType) / sizeof(Element)); - /// The shape of the the fragment. - typedef typename ShapeMul<Iterations, Shape<1, 1, 1, kElementsPerAccess> >::Shape FragmentShape; - /// The linear strides for iterations. - typedef typename ShapeStrides<FragmentShape, kElementsPerAccess>::Shape IterationsStrides; - - /// Ctor. - template <typename OtherFragment_> - CUTLASS_DEVICE FragmentConstIterator(OtherFragment_& fragment, int offset = 0) - : pointer(reinterpret_cast<Element const*>(&fragment[offset])) { - static_assert(OtherFragment_::kElements >= Fragment::kElements, ""); - } - /// Create from non-constant FragmentIterator - CUTLASS_DEVICE FragmentConstIterator( - FragmentIterator<Fragment_, Iterations_, AccessType_> const& rhs_) - : pointer(reinterpret_cast<Element const*>(rhs_.offset)) {} - - /// The accessor. - CUTLASS_DEVICE AccessType const& at(int d, int h, int w, int c = 0) const { - int const imm = ComputeOffsetFromStrides<IterationsStrides>::get(d, h, w, c); - return reinterpret_cast<AccessType const&>(pointer[imm]); - } - - /// The accessor. - CUTLASS_DEVICE AccessType const& operator[](int i) const { - return reinterpret_cast<AccessType const&>(pointer[i * kElementsPerAccess]); - } - - /// Is the iterator valid? - CUTLASS_DEVICE bool valid(int d, int h, int w, int c) const { return true; } - - /// The pointer. - Element const* pointer; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace cutlass diff --git a/cutlass-example/cutlass/fragment_load_store.h b/cutlass-example/cutlass/fragment_load_store.h deleted file mode 100644 index a7d272e..0000000 --- a/cutlass-example/cutlass/fragment_load_store.h +++ /dev/null @@ -1,135 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines accessors for loading and storing fragments to memory efficiently. -*/ -#pragma once - -#include <cutlass/load_store.h> -#include <cutlass/vector.h> - -namespace cutlass { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <IteratorFragment::Kind kIteratorFragment, - int kAccessSize, - typename Scalar_, - MemorySpace::Kind Memory_, - typename FragmentElement_, - int kStride> -struct FragmentLoad {}; - -template <int kAccessSize, - typename Scalar_, - MemorySpace::Kind Memory_, - typename FragmentElement_, - int kStride> -struct FragmentLoad<IteratorFragment::kWmmaMatrix, - kAccessSize, - Scalar_, - Memory_, - FragmentElement_, - kStride> { - /// The output type. - typedef FragmentElement_ AccessType; - - /// The load function. - static CUTLASS_DEVICE void load(AccessType& value, Scalar_ const* pointer, int offset) { - value.load(&pointer[offset], kStride); - } -}; - -template <int kAccessSize, - typename Scalar_, - MemorySpace::Kind Memory_, - typename FragmentElement_, - int kStride> -struct FragmentLoad<IteratorFragment::kScalar, - kAccessSize, - Scalar_, - Memory_, - FragmentElement_, - kStride> { - /// The output type. - typedef typename Vectorize<Scalar_, kAccessSize>::Type AccessType; - - /// The load function. - static CUTLASS_DEVICE void load(AccessType& value, Scalar_ const* pointer, int offset) { - Load<Scalar_, kAccessSize, Memory_>::load(value, pointer, offset); - } -}; - -template <IteratorFragment::Kind kIteratorFragment, - int kAccessSize, - typename Scalar_, - MemorySpace::Kind Memory_, - typename FragmentElement_, - int kStride> -struct FragmentStore {}; - -template <int kAccessSize, - typename Scalar_, - MemorySpace::Kind Memory_, - typename FragmentElement_, - int kStride> -struct FragmentStore<IteratorFragment::kWmmaMatrix, - kAccessSize, - Scalar_, - Memory_, - FragmentElement_, - kStride> { - /// The input type. - typedef FragmentElement_ AccessType; - - /// The store function. - static CUTLASS_DEVICE void store(AccessType const& value, Scalar_* pointer, int offset) { - value.store(&pointer[offset], kStride); - } -}; - -template <int kAccessSize, - typename Scalar_, - MemorySpace::Kind Memory_, - typename FragmentElement_, - int kStride> -struct FragmentStore<IteratorFragment::kScalar, - kAccessSize, - Scalar_, - Memory_, - FragmentElement_, - kStride> { - /// The input type. - typedef typename Vectorize<Scalar_, kAccessSize>::Type AccessType; - - /// The store function. - static CUTLASS_DEVICE void store(AccessType const& value, Scalar_* pointer, int offset) { - Store<Scalar_, kAccessSize, Memory_>::store(value, pointer, offset); - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} /// namespace cutlass diff --git a/cutlass-example/cutlass/fragment_multiply_add.h b/cutlass-example/cutlass/fragment_multiply_add.h deleted file mode 100644 index 36a4d6f..0000000 --- a/cutlass-example/cutlass/fragment_multiply_add.h +++ /dev/null @@ -1,149 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines multiply-add operations on fragments within a thread. -*/ -#pragma once - -#include <cutlass/fragment.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_> -struct FragmentMultiplyAdd { - /// The shape of the instruction. - typedef Shape<1, 1, 1, 1> InstructionShape; - /// The type for A. - typedef Scalar_ ScalarA; - /// The type for B. - typedef Scalar_ ScalarB; - /// The type for C and D. - typedef Scalar_ ScalarC; - - /// Ctor. - CUTLASS_DEVICE FragmentMultiplyAdd() {} - - /// Multiply : d = a*b. - template <typename FragmentB_, typename FragmentCd_> - CUTLASS_DEVICE void multiply(Scalar_ a, FragmentB_ const& b, FragmentCd_& d) { - int const kReduction = FragmentB_::kElements / FragmentCd_::kElements; - for (int j = 0; j < FragmentCd_::kElements; ++j) { - d[j] = a * b[j * kReduction + 0]; - for (int k = 1; k < kReduction; ++k) { - d[j] += a * b[j * kReduction + k]; - } - } - } - - /// Multiply : d = a*b + c. - template <typename FragmentB_, typename FragmentCd_> - CUTLASS_DEVICE void multiply_add(Scalar_ a, - FragmentB_ const& b, - FragmentCd_ const& c, - FragmentCd_& d) { - int const kReduction = FragmentB_::kElements / FragmentCd_::kElements; - for (int j = 0; j < FragmentCd_::kElements; ++j) { - d[j] = a * b[j * kReduction + 0] + c[j]; - for (int k = 1; k < kReduction; ++k) { - d[j] += a * b[j * kReduction + k]; - } - } - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -#if !defined(__CUDACC_RTC__) || defined(CUTLASS_NVRTC_HAS_FP16) -template <> -struct FragmentMultiplyAdd<half> { - /// The shape of the instruction. - typedef Shape<1, 1, 2, 1> InstructionShape; - /// The type for A. - typedef half ScalarA; - /// The type for B. - typedef half ScalarB; - /// The type for C and D. - typedef half ScalarC; - - /// Ctor. - CUTLASS_DEVICE FragmentMultiplyAdd() {} - - /// Multiply : d = a*b. - template <typename FragmentB_, typename FragmentCd_> - CUTLASS_DEVICE void multiply(half a, FragmentB_ const& b, FragmentCd_& d) { -#if defined(__CUDACC__) && __CUDA_ARCH__ >= 530 - - // Assemble a half2 from a. - __half2 const a_half2 = __half2half2(a); - // The input. - __half2 const* b_half2 = reinterpret_cast<__half2 const*>(&b[0]); - // The output. - __half2* d_half2 = reinterpret_cast<__half2*>(&d[0]); - - int const kReduction = FragmentB_::kElements / FragmentCd_::kElements; - for (int j = 0; j < FragmentCd_::kElements / 2; ++j) { - d_half2[j] = __hmul2(a_half2, b_half2[j * kReduction + 0]); - for (int k = 1; k < kReduction; ++k) { - d_half2[j] = __hfma2(a_half2, b_half2[j * kReduction + k], d_half2[j]); - } - } -#endif - } - - /// Multiply : d = a*b + c. - template <typename FragmentB_, typename FragmentCd_> - CUTLASS_DEVICE void multiply_add(half a, - FragmentB_ const& b, - FragmentCd_ const& c, - FragmentCd_& d) { -#if defined(__CUDACC__) && __CUDA_ARCH__ >= 530 - // Assemble a half2 from a. - __half2 const a_half2 = __half2half2(a); - // The inputs. - __half2 const* b_half2 = reinterpret_cast<__half2 const*>(&b[0]); - __half2 const* c_half2 = reinterpret_cast<__half2 const*>(&c[0]); - // The output. - __half2* d_half2 = reinterpret_cast<__half2*>(&d[0]); - - int const kReduction = (FragmentB_::kElements / FragmentCd_::kElements); - for (int j = 0; j < FragmentCd_::kElements / 2; ++j) { - d_half2[j] = __hfma2(a_half2, b_half2[j * kReduction + 0], c_half2[j]); - for (int k = 1; k < kReduction; ++k) { - d_half2[j] = __hfma2(a_half2, b_half2[j * kReduction + k], d_half2[j]); - } - } -#endif - } -}; - -#endif - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/clear_accumulators.h b/cutlass-example/cutlass/gemm/clear_accumulators.h deleted file mode 100644 index 441370f..0000000 --- a/cutlass-example/cutlass/gemm/clear_accumulators.h +++ /dev/null @@ -1,57 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines abstractions for efficiently clearing accumulator tiles. -*/ -#pragma once - -#include <cutlass/vector.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, int kLanes_ = 1> -struct ClearAccumulators { - /// The shared storage. - struct SharedStorage {}; - - /// Ctor. - CUTLASS_DEVICE ClearAccumulators() {} - /// Ctor. - CUTLASS_DEVICE ClearAccumulators(SharedStorage& shared_storage) {} - - /// Clear the fragment. - template <typename Fragment_> - CUTLASS_DEVICE void clear(Fragment_& fragment) { - fragment.clear(); - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/dgemm_traits.h b/cutlass-example/cutlass/gemm/dgemm_traits.h deleted file mode 100644 index 0bbc221..0000000 --- a/cutlass-example/cutlass/gemm/dgemm_traits.h +++ /dev/null @@ -1,127 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines structural traits of double-precision GEMM. -*/ -#pragma once - -#include <cutlass/gemm/gemm.h> -#include <cutlass/gemm/gemm_epilogue.h> -#include <cutlass/gemm/gemm_epilogue_traits.h> -#include <cutlass/gemm/gemm_global_tile.h> -#include <cutlass/gemm/gemm_shared_tile.h> -#include <cutlass/gemm/gemm_traits.h> -#include <cutlass/gemm/thread_multiply_add.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The tile size for the GEMM KxNxM. - typename OutputTile_, - /// The number of accumulators per thread. - typename AccumulatorsPerThread_, - /// The number of scalars per LDG for A. - int kScalarsPerLdgA_ = 1, - /// The number of scalars per LDG for B. - int kScalarsPerLdgB_ = 1> -struct DgemmConfig - : public GemmConfig< - /// The scalar type for A. - double, - /// The scalar type for B. - double, - /// The scalar type for C. - double, - /// The scalar type for D. - double, - /// The tile size for the GEMM KxNxM. - OutputTile_, - /// The functor to do the math in the main loop. - ThreadMultiplyAdd<AccumulatorsPerThread_, Shape<1, 4, 8>, double, double, double>, - /// The number of scalars per LDG for A. - kScalarsPerLdgA_, - /// The number of scalars per STS for A. - kScalarsPerLdgA_, - /// The number of scalars per LDS for A. - 2, - /// The number of scalars per LDG for B. - kScalarsPerLdgB_, - /// The number of scalars per STS for B. - kScalarsPerLdgB_, - /// The number of scalars per LDS for B. - 2, - /// The number of scalars per LDG for C and STG for D. - 1, - /// The number of scalars per STS for D. - 2, - /// The number of scalars per LDS for D. - 1, - /// The number of stages in shared memory. - 2> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The layout for A. - MatrixLayout::Kind kLayoutA_, - /// The layout for B. - MatrixLayout::Kind kLayoutB_, - /// The output tile. - typename OutputTile_ = Shape<8, 64, 128>, - /// The functor to use in the epilogue. - typename EpilogueFunctor_ = LinearScaling<double>, - /// The number of accumulators per thread. - typename AccumulatorsPerThread_ = Shape<8, 8, 8>, - /// The number of doubles loaded in one LDG for A. - int kScalarsPerLdgA_ = 1, - /// The number of doubles loaded in one LDG for B. - int kScalarsPerLdgB_ = 1, - /// The index. - typename Index_ = int, - /// The DGEMM config. - typename GemmConfig_ = - DgemmConfig<OutputTile_, AccumulatorsPerThread_, kScalarsPerLdgA_, kScalarsPerLdgB_>, - /// The traits class for the epilogue. - typename GemmEpilogueTraits_ = - SimplifiedGemmEpilogueTraits<GemmConfig_, EpilogueFunctor_, Index_> > -struct DgemmTraits : public SimplifiedGemmTraits< - // The layout for A. - kLayoutA_, - // The layout for B. - kLayoutB_, - // The config. - GemmConfig_, - // The epilogue. - GemmEpilogue<GemmEpilogueTraits_>, - // The index. - Index_> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/gemm.h b/cutlass-example/cutlass/gemm/gemm.h deleted file mode 100644 index c50a3f0..0000000 --- a/cutlass-example/cutlass/gemm/gemm.h +++ /dev/null @@ -1,344 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Implements a software-pipelined efficient GEMM. -*/ -#pragma once - -#if !defined(__CUDACC_RTC__) -#include <cuda.h> -#endif - -#include <cutlass/coord.h> -#include <cutlass/util/platform.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Gemm_> -__global__ /*__launch_bounds__(Gemm_::kThreads)*/ void gemm_kernel(typename Gemm_::Params params) { - // Declare shared memory. - __shared__ typename Gemm_::SharedStorage shared_storage; - - // Construct the GEMM object. - Gemm_ gemm(params, shared_storage); - // Run GEMM. - gemm.multiply_add(); -} - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, typename Index_ = int> -struct GemmDesc { - /// The dimensions of the GEMM. - Index_ m, n, k; - /// The alpha/beta scaling values. - Scalar_ alpha, beta; - /// The source matrix A. - void const* d_a; - /// The stride for A. - Index_ lda; - /// The source matrix B. - void const* d_b; - /// The stride for B. - Index_ ldb; - /// The source matrix C. - void const* d_c; - /// The stride for C. - Index_ ldc; - /// The destination matrix D. - void* d_d; - /// The stride for D. - Index_ ldd; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmTraits_> -struct Gemm { - /// This class. - typedef Gemm<GemmTraits_> This_; - /// The traits. - typedef GemmTraits_ Traits; - /// The shared storage. - typedef typename Traits::SharedStorage SharedStorage; - - /// The scalar for A. - typedef typename Traits::ScalarA ScalarA; - /// The scalar for B. - typedef typename Traits::ScalarB ScalarB; - /// The scalar in the epilogue. - typedef typename Traits::Epilogue::Scalar ScalarEpilogue; - /// The scalar for C. - typedef typename Traits::Epilogue::ScalarC ScalarC; - /// The scalar for D. - typedef typename Traits::Epilogue::ScalarD ScalarD; - /// The index. - typedef typename Traits::Index Index; - - /// The number of threads. - static int const kThreads = Traits::GemmConfig::kThreads; - - /// The params. - struct Params : public Traits::Params { - CUTLASS_HOST_DEVICE int initialize(Index m, - Index n, - Index k, - ScalarEpilogue alpha, - ScalarA const* d_a, - Index lda, - ScalarB const* d_b, - Index ldb, - ScalarEpilogue beta, - ScalarC const* d_c, - Index ldc, - ScalarD* d_d, - Index ldd) { - GemmDesc<ScalarEpilogue, Index> desc; - desc.m = m; - desc.n = n; - desc.k = k; - desc.alpha = alpha; - desc.beta = beta; - desc.d_a = reinterpret_cast<void const*>(d_a); - desc.lda = lda; - desc.d_b = reinterpret_cast<void const*>(d_b); - desc.ldb = ldb; - desc.d_c = reinterpret_cast<void const*>(d_c); - desc.ldc = ldc; - desc.d_d = reinterpret_cast<void*>(d_d); - desc.ldd = ldd; - return Traits::Params::initialize(desc); - } - }; - -#if !defined(__CUDACC_RTC__) - /// Launch the kernel. - static __host__ cudaError_t launch(Params const& params, - cudaStream_t stream = cudaStreamDefault) { - // Setup the grid. - dim3 grid; - grid.x = (params.m + Traits::OutputTile::kW - 1) / Traits::OutputTile::kW; - grid.y = (params.n + Traits::OutputTile::kH - 1) / Traits::OutputTile::kH; - - // The number of threads. - dim3 block; - block.x = kThreads; - - // Launch the kernel. - void const* params_ = reinterpret_cast<void const*>(¶ms); - - return cudaLaunchKernel(reinterpret_cast<void*>(&gemm_kernel<This_>), - grid, - block, - const_cast<void**>(¶ms_), - 0, - stream); - } - - /// Launch the kernel. - static __host__ cudaError_t launch(CUfunction kernel, - Params const& params, - CUstream stream = CU_STREAM_LEGACY) { - // Setup the grid. - dim3 grid; - grid.x = (params.m + Traits::OutputTile::kW - 1) / Traits::OutputTile::kW; - grid.y = (params.n + Traits::OutputTile::kH - 1) / Traits::OutputTile::kH; - - // The number of threads. - dim3 block; - block.x = kThreads; - - // Launch the kernel. - void* params_[] = {const_cast<void*>(reinterpret_cast<void const*>(¶ms))}; - - // return cudaLaunchKernel(reinterpret_cast<void*>(&gemm_kernel<This_>), grid, block, - // const_cast<void**>(¶ms_), 0, stream); - CUresult result = cuLaunchKernel( - kernel, grid.x, grid.y, grid.z, block.x, block.y, block.z, 0, stream, params_, 0); - - if (result != CUDA_SUCCESS) { - return cudaErrorLaunchFailure; - } - return cudaSuccess; - } - -#endif - - /// Ctor. - CUTLASS_DEVICE Gemm(Params const& params_, SharedStorage& shared_storage_) - : params(params_), shared_storage(shared_storage_) {} - - /// Consume a single iteration of the loop. - template <bool kIsLastIteration> - CUTLASS_DEVICE void consume_tile(typename Traits::GlobalLoadStream& global_stream, - typename Traits::SharedLoadStream& shared_load_stream, - typename Traits::MultiplyAdd::Accumulators& accumulators, - Index outer_k) { - // If that's the last "load iteration" update the predicates. - if (!kIsLastIteration) { - global_stream.move_to_residue<false>(outer_k); - } - - // Load data for the next iteration of the main loop. - if (!kIsLastIteration) { - global_stream.copy(); - } - - // The unrolling steps for the main loop. - int const kUnrollingSteps = - Traits::MultiplyAdd::AccumulatorsPerWarp::kD / Traits::MultiplyAdd::InstructionShape::kD; - - CUTLASS_PRAGMA_UNROLL - for (int step = 0; step < kUnrollingSteps - 1; ++step) { - // Trigger the copy from shared memory for the next A/B values. - shared_load_stream.copy(step + 1); - // Make sure the values are available for the current iteration to do the multiply-add. - shared_load_stream.commit(step); - - // Do the math on the fragments of the current iteration. - typename Traits::MultiplyAdd multiply_add; - multiply_add.multiply_add(shared_load_stream.fragment_a(step), - shared_load_stream.fragment_b(step), - accumulators, - accumulators); - } - - // Make sure the data from shared memory has been entirely consumed. - Traits::shared_load_fence(true); - - // Commit the data in shared memory for A/B. - if (!kIsLastIteration) { - global_stream.commit(); - } - - // Make sure the data is in shared memory. - Traits::shared_store_fence(true); - - // Trigger the loads for the next iteration (if needed). - if (!kIsLastIteration) { - // Move to the next stage for the load (if it makes sense). - shared_load_stream.inc_stage(); - // Trigger the copy from shared memory for the next loop iteration. - shared_load_stream.copy(0); - } - - // Make sure the values are available for the current iteration to do the multiply-add. - shared_load_stream.commit(kUnrollingSteps - 1); - - // Do the math on the fragments of the current iteration. - typename Traits::MultiplyAdd multiply_add; - multiply_add.multiply_add(shared_load_stream.fragment_a(kUnrollingSteps - 1), - shared_load_stream.fragment_b(kUnrollingSteps - 1), - accumulators, - accumulators); - } - - /// Do the GEMM. - CUTLASS_DEVICE void multiply_add() { - // Swizzle the IDs of the block (to enable better cache behavior). - typename Traits::BlockSwizzle block_swizzle; - dim3 block = block_swizzle.swizzle(); - - // Scale the id. - block.x *= Traits::OutputTile::kW; - block.y *= Traits::OutputTile::kH; - - // We may want to use shared memory to clear the registers. - typedef typename Traits::ClearAccumulators ClearAccumulators; - - // The streams to read A/B from global memory to shared memory. - typename Traits::GlobalLoadStream global_stream(params, shared_storage, block); - - // Create the accumulator clear. - ClearAccumulators clear(shared_storage.main_loop.clear); - - // By how much we unroll the main loop. - Index const kUnroll = static_cast<Index>(Traits::OutputTile::kD); - - // If we do not have enough steps in the main loop, trigger the residue code. - global_stream.move_to_residue<true>(params.k); - - // Fetch the fragments for A and B from global memory. - global_stream.copy(); - - // Copy the elements to shared memory (after transformation if needed). - global_stream.commit(); - - // Make sure the data is in shared memory. - Traits::shared_store_fence(false); - - // Rollback to the beginning of the GEMM-K dimension. It may have no impact. - global_stream.rollback(); - - // The unrolling steps for the main loop. - int const kUnrollingSteps = - Traits::MultiplyAdd::AccumulatorsPerWarp::kD / Traits::MultiplyAdd::InstructionShape::kD; - - // Make sure we have at least 2 unrolling steps or our pipeling is not going to work. - static_assert(kUnrollingSteps >= 2, "The pipelining assumes at least two steps"); - - // The stream of data from shared memory to fragments. - typename Traits::SharedLoadStream shared_load_stream(params, shared_storage); - - // Trigger the copy from shared memory for the 1st stream. - shared_load_stream.copy(0); - - // Allocate the accumulators. - typename Traits::MultiplyAdd::Accumulators accumulators; - // Clear the accumulators. - clear.clear(accumulators); - - // The loop index. - Index outer_k = params.k - kUnroll; - - // Enter the main loop and iterate. - for (; outer_k > 0; outer_k -= kUnroll) { - consume_tile<false>(global_stream, shared_load_stream, accumulators, outer_k); - } - - // Residual loop. - for (; outer_k > -kUnroll; outer_k -= kUnroll) { - consume_tile<true>(global_stream, shared_load_stream, accumulators, outer_k); - } - - // Epilogue. - typedef typename Traits::Epilogue Epilogue; - Epilogue epilogue(params.epilogue, shared_storage.epilogue, params.m, params.n); - epilogue.epilogue(cutlass::make_Coord(0, block.y, block.x), accumulators); - } - - /// The params. - Params const& params; - /// The shared storage. - SharedStorage& shared_storage; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/gemm_epilogue.h b/cutlass-example/cutlass/gemm/gemm_epilogue.h deleted file mode 100644 index bc25307..0000000 --- a/cutlass-example/cutlass/gemm/gemm_epilogue.h +++ /dev/null @@ -1,231 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Implements the epilogue phase of the GEMM kernel that efficiently updates global memory - with - the computed matrix product. -*/ -#pragma once - -#include <cutlass/convert.h> -#include <cutlass/coord.h> -#include <cutlass/fragment.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename T> -CUTLASS_DEVICE bool is_zero(T x) { - return x == T(0); -} - -#if !defined(__CUDACC_RTC__) || defined(CUTLASS_NVRTC_HAS_FP16) -CUTLASS_DEVICE bool is_zero(half x) { return reinterpret_cast<int16_t&>(x) == int16_t(0); } -#endif - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmEpilogueTraits_> -struct GemmEpilogue { - /// The traits class. - typedef GemmEpilogueTraits_ Traits; - /// The params. - typedef typename Traits::Params Params; - /// The shared storage. - typedef typename Traits::SharedStorage SharedStorage; - - /// The output tile. - typedef typename Traits::OutputTile OutputTile; - /// The number of iterations. - typedef typename Traits::Iterations Iterations; - /// The accumulators. - typedef typename Traits::Accumulators Accumulators; - /// The scalar. - typedef typename Traits::Scalar Scalar; - /// The functor in charge of the math. - typedef typename Traits::Functor Functor; - - /// We do not support 3D or 4D shapes. - static_assert(Iterations::kD == 1 && Iterations::kC == 1, "Unsupported 3D/4D shapes"); - - /// The iterator for C in global memory. - typedef typename Traits::GlobalLoadIteratorC GlobalLoadIteratorC; - /// The transformer for C. - typedef typename Traits::GlobalTransformerC GlobalTransformerC; - /// The transformer for D. - typedef typename Traits::GlobalTransformerD GlobalTransformerD; - /// The iterator for D in global memory. - typedef typename Traits::GlobalStoreIteratorD GlobalStoreIteratorD; - /// The iterator to store D in shared memory. - typedef typename Traits::SharedStoreIteratorD SharedStoreIteratorD; - /// The shared store transformer for D. - typedef typename Traits::SharedStoreTransformerD SharedStoreTransformerD; - /// The iterator to load D in shared memory. - typedef typename Traits::SharedLoadIteratorD SharedLoadIteratorD; - /// The shared load transformer for D. - typedef Copy<typename SharedLoadIteratorD::Fragment> SharedLoadTransformerD; - - /// The index. - typedef typename Traits::Index Index; - - /// The scalar for C. - typedef typename GlobalLoadIteratorC::Scalar ScalarC; - /// The scalar for D. - typedef typename GlobalStoreIteratorD::Scalar ScalarD; - - /// Ctor. - CUTLASS_DEVICE GemmEpilogue(Params const& params_, - SharedStorage& shared_storage_, - Index m_, - Index n_) - : params(params_), shared_storage(shared_storage_), m(m_), n(n_) {} - - /// Execute the epilogue. - CUTLASS_DEVICE void epilogue(Coord<3> const& block, Accumulators& accumulators) { - if (is_zero(params.functor.beta)) { - epilogue_with_or_without_beta<true>(block, accumulators); - } else { - epilogue_with_or_without_beta<false>(block, accumulators); - } - } - - template <bool kBetaIsZero_> - CUTLASS_DEVICE void epilogue_with_or_without_beta(Coord<3> const& block, - Accumulators& accumulators) { - - // The problem size. - Coord<3> const bounds = cutlass::make_Coord(0, n, m); - - // The functor. - Functor functor(params.functor); - // The C fragment. - typename GlobalLoadIteratorC::Fragment fragment_c; - // The transformed C fragment. - typename GlobalTransformerC::OutputFragment transformed_c; - - CUTLASS_PRAGMA_UNROLL - for (int h = 0; h < Iterations::kH; ++h) { - // Compute pointer and predicate offsets for C and D global iterators. - int const pointer_offset = - ((params.iterator_d.inc_h * (GlobalStoreIteratorD::Iterations::kH - 1) + - params.iterator_d.inc_advance) * - Iterations::kW + - params.stride_h) * - h; - int const predicate_offset = - ((params.iterator_d.predicate_inc_h * (GlobalStoreIteratorD::Iterations::kH - 1) + - params.iterator_d.predicate_inc_advance) * - Iterations::kW + - Traits::Delta::kH) * - h; - - // The iterator to load the elements of the C matrix. - GlobalLoadIteratorC global_load_iterator( - params.iterator_c, bounds, block, pointer_offset, predicate_offset); - // The transformer for C. - GlobalTransformerC transformer_c; - // The transformer for D. - GlobalTransformerD transformer_d; - // The iterator to store into the D matrix. - GlobalStoreIteratorD global_store_iterator( - params.iterator_d, bounds, block, pointer_offset, predicate_offset); - - // The transformer to transform before storing to shared memory. - SharedStoreTransformerD shared_store_transformer; - typename SharedStoreTransformerD::OutputFragment shared_store_transformed_d; - - // The iterator to store to shared memory. - SharedStoreIteratorD shared_store_iterator(params.shared_store_iterator_d, - shared_storage.shared_stream.store); - - // The iterator to load from shared memory. TODO: Use a stream. - SharedLoadIteratorD shared_load_iterator(params.shared_load_iterator_d, - shared_storage.shared_stream.load); - - CUTLASS_PRAGMA_UNROLL - for (int w = 0; w < Iterations::kW; ++w) { - // Load the C matrix into fragment. - if (!kBetaIsZero_) { - iterator_load(global_load_iterator, fragment_c); - } - - // Make sure we can write to shared memory. - shared_load_fence(); - - // Copy the accumulators to shared memory. - int const offset = (h * Iterations::kW + w) * SharedStoreIteratorD::Fragment::kElements; - - shared_store_transformer.transform(accumulators, offset, shared_store_transformed_d); - shared_iterator_store(shared_store_iterator, shared_store_transformed_d); - - // Make sure the data is in shared memory. - shared_store_fence(); - - // Copy the accumulators back to registers from shared memory. - typename SharedLoadIteratorD::Fragment fetched_d; - shared_iterator_load(shared_load_iterator, fetched_d); - - // Do the math. - typename GlobalTransformerD::InputFragment fragment_d; - - if (kBetaIsZero_) { - functor.evaluate(fetched_d, fragment_d); - } else { - // Transform C fragment. - transformer_c.transform(fragment_c, transformed_c); - // Do the math. - functor.evaluate(fetched_d, transformed_c, fragment_d); - } - - // Transform D fragment. - typename GlobalTransformerD::OutputFragment transformed_d; - transformer_d.transform(fragment_d, transformed_d); - - // Copy the results to global memory. - iterator_store(global_store_iterator, transformed_d); - } - } - } - - /// The memory fence for shared loads. - CUTLASS_DEVICE void shared_load_fence() { __syncthreads(); } - - /// The memory fence for shared stores. - CUTLASS_DEVICE void shared_store_fence() { __syncthreads(); } - - /// The params. - Params const& params; - /// The shared storage. - SharedStorage& shared_storage; - /// The dimensions of the GEMM. - Index m, n; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/gemm_epilogue_traits.h b/cutlass-example/cutlass/gemm/gemm_epilogue_traits.h deleted file mode 100644 index c06fc25..0000000 --- a/cutlass-example/cutlass/gemm/gemm_epilogue_traits.h +++ /dev/null @@ -1,331 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines structural properties of the GEMM epilogue. -*/ -#pragma once - -#include <cutlass/convert.h> -#include <cutlass/coord.h> -#include <cutlass/gemm/gemm_global_stream.h> -#include <cutlass/gemm/gemm_shared_stream.h> -#include <cutlass/gemm/linear_scaling.h> -#include <cutlass/reshape_tile.h> -#include <cutlass/tile_iterator.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The output tile. - typename OutputTile_, - /// The accumulators. - typename Accumulators_, - /// The iterator to load C from global memory. - typename GlobalLoadIteratorC_, - /// The transformer for C. - typename GlobalTransformerC_, - /// The transformer for D. - typename GlobalTransformerD_, - /// The iterator to store D to global memory. - typename GlobalStoreIteratorD_, - /// The iterator to store D to shared memory. - typename SharedStoreIteratorD_, - /// The shared store transformer for D. - typename SharedStoreTransformerD_, - /// The iterator to load D from shared memory. - typename SharedLoadIteratorD_, - /// The number of iterations in the epilogue. - typename Iterations_, - /// The iterations strides. - typename Delta_, - /// The functor to be used in the epilogue. - typename Functor_, - /// The index. - typename Index_ = int> -struct GemmEpilogueTraits { - // - /// The output tile. - typedef OutputTile_ OutputTile; - /// The number of iterations. - /// The accumulators. - typedef Accumulators_ Accumulators; - /// The iterator for C in global memory. - typedef GlobalLoadIteratorC_ GlobalLoadIteratorC; - /// The transformer for C. - typedef GlobalTransformerC_ GlobalTransformerC; - /// The transformer for D. - typedef GlobalTransformerD_ GlobalTransformerD; - /// The iterator for D in global memory. - typedef GlobalStoreIteratorD_ GlobalStoreIteratorD; - /// The iterator to store D in shared memory. - typedef SharedStoreIteratorD_ SharedStoreIteratorD; - /// The shared store transformer for D. - typedef SharedStoreTransformerD_ SharedStoreTransformerD; - /// The iterator to store D in shared memory. - typedef SharedLoadIteratorD_ SharedLoadIteratorD; - /// typedef typename GemmConfig::EpilogueIterations Iterations; - typedef Iterations_ Iterations; - /// The iterations strides. - typedef Delta_ Delta; - - /// The functor in charge of the math. - typedef Functor_ Functor; - /// The index. - typedef Index_ Index; - - /// We do not support 3D or 4D shapes. - static_assert(Iterations::kD == 1 && Iterations::kC == 1, "Unsupported 3D/4D shapes"); - - /// The scalar. - typedef typename Functor::Scalar Scalar; - /// The scalar for C. - typedef typename GlobalLoadIteratorC::Scalar ScalarC; - /// The scalar for D. - typedef typename GlobalStoreIteratorD::Scalar ScalarD; - - /// The params. - struct Params { - /// The strides for H and W in the different iterations of the epilogue. - Index stride_h, stride_w; - /// The params for the C iterator. - typename GlobalLoadIteratorC::Params iterator_c; - /// The params for the D global iterator. - typename GlobalStoreIteratorD::Params iterator_d; - /// The params for the D shared store iterator. - typename SharedStoreIteratorD::Params shared_store_iterator_d; - /// The params for the D shared load iterator. - typename SharedLoadIteratorD::Params shared_load_iterator_d; - /// The functor params. - typename Functor::Params functor; - - /// Setup the params. - template <typename GemmDesc_> - CUTLASS_HOST_DEVICE int initialize(GemmDesc_ const& desc) { - // The parameters for the functor. - int error_code = functor.initialize(desc); - if (error_code) { - return error_code; - } - - // At the end of the H iteration, we jump over a number of columns. - this->stride_h = desc.ldd * Delta::kH; - // Nothing to do here. - this->stride_w = 0; - - // Setup the params for the global memory iterator for C. - error_code = iterator_c.initialize( - reinterpret_cast<ScalarC const*>(desc.d_c), desc.ldc, desc.n, stride_w, Delta::kW); - if (error_code) { - return error_code; - } - - // Setup the params for the global memory iterator for D. - return iterator_d.initialize( - reinterpret_cast<ScalarD*>(desc.d_d), desc.ldd, desc.n, stride_w, Delta::kW); - } - }; - - /// The shared memory storage to exchange data. - union StreamSharedStorage { - // The storage for the store iterator. - typename SharedStoreIteratorD::SharedStorage store; - // The storage for the store iterator. - typename SharedLoadIteratorD::SharedStorage load; - }; - - /// The shared memory to swizzle the data in the epilogue. - struct SharedStorage { - // The storage for the shared stream D. - StreamSharedStorage shared_stream; - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_, typename EpilogueFunctor_, typename Index_ = int> -struct GemmEpilogueTraitsHelper { - /// The scalar. - typedef typename EpilogueFunctor_::Scalar Scalar; - /// The output tile. - typedef typename GemmConfig_::OutputTile OutputTile; - - /// The number of iterations in the epilogue. - typedef Shape<1, - GemmConfig_::MultiplyAdd::AccumulatorsPerThread::kH / - GemmConfig_::kAccumulatorsPerLdsB, - GemmConfig_::kAccumulatorsPerLdsB> - Iterations; - // The iteration strides in the H/W dimension. - typedef Shape<0, - GemmConfig_::kAccumulatorsPerLdsB*( - GemmConfig_::Warps::kH* GemmConfig_::MultiplyAdd::ThreadsPerWarp::kH - 1), - 0> - Delta; - /// The functor to do the math in the epilogue. - typedef EpilogueFunctor_ Functor; - - /// The traits class to build the iterator to store to shared memory for D. - typedef GemmSharedStoreTileDTraits< - // The pointer is float. - typename Functor::Scalar, - // The output tile size. - typename GemmConfig_::OutputTile, - // The number of warps. - typename GemmConfig_::Warps, - // The number of threads per warp. - typename GemmConfig_::MultiplyAdd::ThreadsPerWarp, - // The number of scalars per STS. - GemmConfig_::kScalarsPerStsD, - // The skew -- 128 / sizeof(ScalarD) / kScalarsPerStsD is the number of threads involved in - // a single STS. We divide by 2 as our objective is to add a skew to the odd threads to - // avoid bank conflicts between odd and even threads. - 128 / sizeof(typename GemmConfig_::ScalarD) / GemmConfig_::kScalarsPerStsD / 2 * - GemmConfig_::kScalarsPerStsD> - SharedStoreTileTraits; - - /// The iterator to store D to shared memory. - typedef TileStoreIterator<SharedStoreTileTraits, - typename SharedStoreTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedStoreIteratorD; - - /// The shared store transformer for D. - typedef Copy<typename SharedStoreIteratorD::Fragment> SharedStoreTransformerD; - - /// The traits class to build the iterator to load from shared memory for D. - typedef GemmSharedLoadTileDTraits< - // The pointer is float. - typename Functor::Scalar, - // The output tile size. - typename GemmConfig_::OutputTile, - // The number of warps. - typename GemmConfig_::Warps, - // The number of threads per warp. - typename GemmConfig_::MultiplyAdd::ThreadsPerWarp, - // The number of columns of the output tile written by iteration. - GemmConfig_::OutputTile::kH / ShapeCount<Iterations>::kCount, - // The number of scalars per LDS. - GemmConfig_::kScalarsPerLdsD, - // The skew. - SharedStoreTileTraits::kSkew> - SharedLoadTileTraits; - - /// The iterator to load D from shared memory. - typedef TileLoadIterator<SharedLoadTileTraits, - typename SharedLoadTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedLoadIteratorD; - - /// The traits class to build the iterator to load data from global memory for C^N. - typedef GemmGlobalTileCdTraits< - // The pointer is float const. - typename GemmConfig_::ScalarC const, - // The tile has size (N / Iterations)xM in GEMM's terminology. - Shape<1, - GemmConfig_::OutputTile::kH / ShapeCount<Iterations>::kCount, - GemmConfig_::OutputTile::kW>, - // The threads are distributed as warps x 32 (the traits may reorganize). - Shape<1, ShapeCount<typename GemmConfig_::Warps>::kCount, GemmConfig_::kWarpSize>, - // How many elements do we jump over at each iteration? - Iterations::kW, - // The number of scalars per LDG (LDG.32 or LDG.128, etc). - GemmConfig_::kScalarsPerLdgC> - GlobalLoadTileTraits; - - /// The iterator to load C. - typedef GemmGlobalIteratorCd<GlobalLoadTileTraits, Index_> GlobalLoadIteratorC; - /// The transformer for C. - typedef Copy<typename GlobalLoadIteratorC::Fragment> GlobalTransformerC; - - /// The traits class to build the iterator to store data to global memory for D^N. - typedef GemmGlobalTileCdTraits< - // The pointer is float. - typename GemmConfig_::ScalarD, - // The tile has size (N / Iterations)xM in GEMM's terminology. - Shape<1, - GemmConfig_::OutputTile::kH / ShapeCount<Iterations>::kCount, - GemmConfig_::OutputTile::kW>, - // The threads are distributed as warps x 32 (the traits may reorganize). - Shape<1, ShapeCount<typename GemmConfig_::Warps>::kCount, GemmConfig_::kWarpSize>, - // How many elements do we jump over at each iteration? - Iterations::kW, - // The number of scalars per LDG (LDG.32 or LDG.128, etc). - GemmConfig_::kScalarsPerStgD> - GlobalStoreTileTraits; - - /// The iterator to store D. - typedef GemmGlobalIteratorCd<GlobalStoreTileTraits, Index_> GlobalStoreIteratorD; - /// The transformer for D. - typedef Copy<typename GlobalStoreIteratorD::Fragment> GlobalTransformerD; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The GEMM config. - typename GemmConfig_, - /// The epilogue functor to do the math in the epilogue. - typename EpilogueFunctor_, - /// The index. - typename Index_ = int, - /// The helper to create the traits class. - typename Helper_ = GemmEpilogueTraitsHelper<GemmConfig_, EpilogueFunctor_, Index_> > -struct SimplifiedGemmEpilogueTraits : public GemmEpilogueTraits< - // The output tile. - typename GemmConfig_::OutputTile, - // The accumulators. - typename GemmConfig_::Accumulators, - // The global iterator for C. - typename Helper_::GlobalLoadIteratorC, - // The transformer for C. - typename Helper_::GlobalTransformerC, - // The transformer for D. - typename Helper_::GlobalTransformerD, - // The global iterator for D. - typename Helper_::GlobalStoreIteratorD, - // The iterator to store D to shared memory. - typename Helper_::SharedStoreIteratorD, - // The shared store transformer for D. - typename Helper_::SharedStoreTransformerD, - // The iterator to load D from shared memory. - typename Helper_::SharedLoadIteratorD, - // The number of iterations. - typename Helper_::Iterations, - // The strides between iterations. - typename Helper_::Delta, - // The functor to be used in the epilogue. - EpilogueFunctor_, - // The index. - Index_> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/gemm_global_stream.h b/cutlass-example/cutlass/gemm/gemm_global_stream.h deleted file mode 100644 index ec675a3..0000000 --- a/cutlass-example/cutlass/gemm/gemm_global_stream.h +++ /dev/null @@ -1,182 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Implements efficient loading of the thread block-level tile from global memory and - storing - to shared memory. -*/ -#pragma once - -#include <cutlass/convert.h> -#include <cutlass/gemm/gemm_global_tile.h> -#include <cutlass/iterator_access.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The load iterator. - typename LoadIterator_, - /// The store iterator to copy to shared memory. - typename StoreIterator_, - /// The transformer to be applied after the data has been copied from global memory. - typename Transformer_> - -struct GlobalLoadStreamBase { - /// The load iterator. - typedef LoadIterator_ LoadIterator; - /// The transformer. - typedef Transformer_ Transformer; - /// The store iterator to write to shared memory. - typedef StoreIterator_ StoreIterator; - - /// The fragment that is copied from shared memory. - typedef typename LoadIterator::Fragment FetchedFragment; - /// The fragment that is obtained after the transformation by the transformer. - typedef typename Transformer::OutputFragment TransformedFragment; - /// Make sure the fragments match. - static_assert((platform::is_same<FetchedFragment, typename Transformer::InputFragment>::value), - ""); - /// The output fragment. - typedef TransformedFragment Fragment; - /// Make sure the transformed fragment is the same as the store fragment. - static_assert((platform::is_same<TransformedFragment, typename StoreIterator::Fragment>::value), - ""); - - /// The layout. - static MatrixLayout::Kind const kLayout = LoadIterator::kLayout; - /// The scalar type of the iterator. - typedef typename LoadIterator::Scalar Scalar; - /// The pointer. - typedef typename LoadIterator::Pointer Pointer; - /// The index. - typedef typename LoadIterator::Index Index; - - /// The params. - struct Params { - // The load iterator. - typename LoadIterator::Params load_iterator; - // The store iterator. - typename StoreIterator::Params store_iterator; - - /// Setup the params. - template <typename GemmDesc_> - CUTLASS_HOST_DEVICE int initialize(GemmDesc_ const& desc, Pointer pointer, Index ld) { - int error_code = load_iterator.initialize(desc, pointer, ld); - if (error_code) { - return error_code; - } - - return store_iterator.initialize(); - } - }; - - /// The amount of storage in shared memory needed to store the tile. - typedef typename StoreIterator::SharedStorage SharedStoreStorage; - - /// The storage in shared memory needed by that stream. - union SharedStorage { - // The load iterator. - typename LoadIterator::SharedStorage load_iterator; - // The store iterator. - SharedStoreStorage store_iterator; - }; - - /// Ctor. - CUTLASS_DEVICE GlobalLoadStreamBase(Params const& params, - SharedStorage& shared_storage, - Coord<3> const bounds, - Coord<3> const& block) - : load_iterator(params.load_iterator, bounds, block), - transformer(), - store_iterator(params.store_iterator, shared_storage.store_iterator) - - { - fetched_fragment.clear(); - } - - /// Load the data from shared memory to the fetch fragment. - CUTLASS_DEVICE void copy() { iterator_load(load_iterator, fetched_fragment); } - - /// Commit the data. - CUTLASS_DEVICE void commit() { - transformer.transform(fetched_fragment, transformed_fragment); - iterator_store(store_iterator, transformed_fragment); - store_iterator.inc_stage(); - } - - /// Move to the beginning of the residue code. That's a new code path in CUTLASS 1.0.1. - CUTLASS_DEVICE void move_to_residue(Index k) { load_iterator.move_to_residue(k); } - - /// Execute the residue code. - CUTLASS_DEVICE void residue(Index k, bool skip_clear = false) { - load_iterator.residue(k); - if (!skip_clear) { - fetched_fragment.clear(); - } - } - - /// Rollback to the beginning of the GEMM-k dimension. - CUTLASS_DEVICE void rollback() { load_iterator.rollback(); } - - /// The iterator. - LoadIterator load_iterator; - /// The fragment to fetch from shared memory. - FetchedFragment fetched_fragment; - /// The transformer. - Transformer transformer; - /// The fragment to convert the data after it has been fetched from shared memory. - TransformedFragment transformed_fragment; - /// The store iterator. - StoreIterator store_iterator; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The load iterator. - typename LoadIterator_, - /// The store iterator to copy to shared memory. - typename StoreIterator_, - /// The transformer to be applied after the data has been copied from global memory. - typename Transformer_ = Copy<typename LoadIterator_::Fragment> > - -struct GlobalLoadStream : public GlobalLoadStreamBase<LoadIterator_, StoreIterator_, Transformer_> { - /// The base class. - typedef GlobalLoadStreamBase<LoadIterator_, StoreIterator_, Transformer_> Base; - - /// Ctor. - CUTLASS_DEVICE GlobalLoadStream(typename Base::Params const& params, - typename Base::SharedStorage& shared_storage, - Coord<3> const& bounds, - Coord<3> const& block) - : Base(params, shared_storage, bounds, block) {} -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/gemm_global_tile.h b/cutlass-example/cutlass/gemm/gemm_global_tile.h deleted file mode 100644 index 1cc3b33..0000000 --- a/cutlass-example/cutlass/gemm/gemm_global_tile.h +++ /dev/null @@ -1,541 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines iterators for efficiently loading and storing to global memory. -*/ -#pragma once - -#include <cutlass/coord.h> -#include <cutlass/util/platform.h> - -#include <cutlass/gemm/gemm_operand.h> -#include <cutlass/matrix_traits.h> -#include <cutlass/predicate_vector.h> -#include <cutlass/reshape_tile.h> -#include <cutlass/tile_iterator.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -// The following functor reshapes a tile of threads to match a tile of data. The idea is that when -// the user wants to build the iterator traits, he/she may want to specify the tile independently -// from the number of scalars loaded/stored per instruction. For example, in the row-major version -// with a tile of size 128x8 - the user may want to that the iterator works with 32x8 threads if -// each thread loads 1 scalar per LDG. If the user changes to 4 scalars per LDG, then the tile of -// threads has to change. The code below detects that and correct the code automatically - it is -// a helper when the user does not specify the right configuration. - -template <typename Tile_, typename Threads_, bool = (Tile_::kW < Threads_::kW)> -struct ReshapeThreads { - typedef Threads_ Threads; -}; - -template <typename Tile_, typename Threads_> -struct ReshapeThreads<Tile_, Threads_, true> { - typedef Shape<Threads_::kD, Threads_::kH * Threads_::kW / Tile_::kW, Tile_::kW, 1> Threads; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <GemmOperand::Kind kOperand_, - MatrixLayout::Kind kLayout_, - typename Scalar_, - typename Tile_, - typename Threads_, - int kAccessSize_> -struct GemmGlobalTileTraits { - /// Identity of the operand - static GemmOperand::Kind const kOperand = kOperand_; - /// The layout. - static MatrixLayout::Kind const kLayout = kLayout_; - /// The scalar. - typedef typename platform::remove_const<Scalar_>::type Scalar; - /// The pointer. - typedef Scalar_* Pointer; - /// The number of scalars per LDG/STG. - static int const kAccessSize = kAccessSize_; - /// The memory space. - static MemorySpace::Kind const kMemorySpace = MemorySpace::kGlobal; - - /// The tile shape - typedef typename ReshapeTile<Tile_, kAccessSize_>::Tile Tile; - /// The threads shape - typedef typename ReshapeThreads<Tile, Threads_>::Threads Threads; - /// The relative offset between two elements in the H/W dimension in adjacent threads. - typedef Shape<1, 1, Tile::kC> ThreadsDelta; - - /// The strides in each dimension between different loads/stores. - typedef Shape<0, Threads::kH, Threads::kW * kAccessSize> Delta; - /// Strides for immediate offset computation - typedef Shape<0, 0, Threads::kW * ThreadsDelta::kW, kAccessSize> ImmediateOffsetStrides; - /// The number of iterations needed to load/store the tile. - typedef Shape<1, Tile::kH / Threads::kH, Tile::kW / Threads::kW, Tile::kC / kAccessSize> - Iterations; - - typedef GemmMultiplicandTraits<Tile, kOperand, kLayout> MultiplicandTraits; - - /// Computes the thread offset in (H, W) based on thread ID - struct ThreadOffset { - CUTLASS_HOST_DEVICE - Coord<4> operator()() const { - int thread_offset_h = threadIdx.x / Threads::kW * ThreadsDelta::kH; - int thread_offset_w = threadIdx.x % Threads::kW * ThreadsDelta::kW; - - return make_Coord(0, thread_offset_h, thread_offset_w, 0); - } - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, typename Tile_, typename Threads_, int kStrideH_, int kAccessSize_> -struct GemmGlobalTileCdTraits : public GemmGlobalTileTraits<GemmOperand::kC, - MatrixLayout::kColumnMajor, - Scalar_, - Tile_, - Threads_, - kAccessSize_> { - /// The base class. - typedef GemmGlobalTileTraits<GemmOperand::kC, - MatrixLayout::kColumnMajor, - Scalar_, - Tile_, - Threads_, - kAccessSize_> - Base; - - /// The stride in the H dimension. - static int const kStrideH = kStrideH_; - /// Override the strides in each dimension between different loads/stores. - typedef Shape<0, 0, Base::Delta::kW, Base::Delta::kC> Delta; - - typedef typename Base::Iterations Iterations; - - typedef typename Base::Threads Threads; - - typedef typename Base::ThreadsDelta ThreadsDelta; - - typedef typename Base::ImmediateOffsetStrides ImmediateOffsetStrides; - - /// Computes the thread offset in (H, W) based on thread ID - struct ThreadOffset { - CUTLASS_HOST_DEVICE - Coord<4> operator()() const { - int thread_offset_h = threadIdx.x / Threads::kW * kStrideH * Iterations::kH; - int thread_offset_w = threadIdx.x % Threads::kW * ThreadsDelta::kW; - - return make_Coord(0, thread_offset_h, thread_offset_w, 0); - } - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename TileTraits_, typename Index_ = int> -struct GemmGlobalIteratorAb - : public TileLoadIterator<TileTraits_, - typename TileTraits_::Scalar, - TileTraits_::MultiplicandTraits::kKstrided ? IteratorAdvance::kH - : IteratorAdvance::kW, - MemorySpace::kGlobal, - Index_> { - /// This class. - typedef GemmGlobalIteratorAb<TileTraits_, Index_> This_; /// The base class. - - typedef TileLoadIterator<TileTraits_, - typename TileTraits_::Scalar, - TileTraits_::MultiplicandTraits::kKstrided ? IteratorAdvance::kH - : IteratorAdvance::kW, - MemorySpace::kGlobal, - Index_> - Base; - /// The layout. - static MatrixLayout::Kind const kLayout = TileTraits_::kLayout; - /// Fragment type loaded by the iterator - typedef typename Base::Fragment Fragment; - /// The scalar. - typedef typename TileTraits_::Scalar Scalar; - /// The threads. - typedef typename TileTraits_::Threads Threads; - /// The index. - typedef Index_ Index; - /// The thread offset - typedef typename TileTraits_::ThreadOffset ThreadOffset; - /// Specifies in which dimension post-increment accesses advance. - static IteratorAdvance::Kind const kAdvance = Base::kAdvance; - - typedef cutlass::PredicateVector<ShapeCount<typename Base::Iterations>::kCount> PredicateVector; - - /// Iterator parameters type - typedef typename Base::Params BaseParams; - - struct Params : public BaseParams { - /// Initializes params to load a strip-mined tile, given pointer and stride_h. - template <typename GemmDesc_> - CUTLASS_HOST_DEVICE int initialize(GemmDesc_ const& desc, Scalar const* ptr, Index stride_h) { - Index inc_d = 0; - Index inc_advance = 0; - // Move by some columns for each iteration in the H dimension. - Index inc_h = Base::Delta::kH * stride_h; - - // Move by some more columns in the number of iterations if the D dimension is > 1. - if (Base::Delta::kD > 0) { - inc_d = Base::Delta::kD * stride_h - (Base::Iterations::kH - 1) * inc_h; - } - - // Move to the beginning of the next iteration. - if (kAdvance == IteratorAdvance::kH && Base::Delta::kD > 0) { - inc_advance = inc_d; - } else if (kAdvance == IteratorAdvance::kH) { - inc_advance = inc_h; - } else if (Base::Delta::kD > 0) { - inc_advance = (Base::Iterations::kW + 0) * ShapeCount<typename Base::Delta>::kWc - - (Base::Iterations::kH - 1) * inc_h - - (Base::Iterations::kD - 1) * Base::Delta::kD * stride_h; - } else { - inc_advance = (Base::Iterations::kW + 0) * ShapeCount<typename Base::Delta>::kWc - - (Base::Iterations::kH - 1) * inc_h; - } - - // The dimensions of the tile. - int const kH = TileTraits_::Tile::kH; - int const kW = TileTraits_::Tile::kW * TileTraits_::kAccessSize; - - // Move to the residue. - Index const kBlock = kAdvance == IteratorAdvance::kH ? kH : kW; - // The jump in the gemm-k dimension. - Index const stride = kAdvance == IteratorAdvance::kH ? stride_h : 1; - - // Compute the offset to the residue and how to "come" back. - Index const kResidue = desc.k % kBlock; - if (kResidue > 0) { - move_to_residue_offset = (desc.k - kResidue) * stride; - } else { - move_to_residue_offset = (desc.k - kBlock) * stride; - } - - Base::Params::initialize(ptr, 0, stride_h, 1, inc_d, inc_h, 0, inc_advance); - return 0; - } - - // The extra offset to control moving to the residue. - Index move_to_residue_offset; - }; - - /// Ctor. - CUTLASS_DEVICE GemmGlobalIteratorAb(Params const& _params, - const Coord<3>& bounds, - const Coord<3>& block, - ThreadOffset thread_offset_func = ThreadOffset()) - : params(_params) { - thread_offset = thread_offset_func(); - // The column. - Index block_h = thread_offset[1]; - // The contiguous dimension. - Index block_w = thread_offset[2]; - - // Add the blocks indices. - if (kAdvance == IteratorAdvance::kH) { - block_h += block[1]; - block_w += block[2]; - - } else { - block_h += block[2]; - block_w += block[1]; - } - - // Setup the pointer. - params.pointer += (block_h * params.stride_h + block_w); - - // Initialize predicates - initialize_predicates(bounds, make_Coord(0, block_h, block_w)); - } - - /// The accessor. - CUTLASS_DEVICE void get(typename Base::AccessType& value, int d, int h, int w, int c) const { - int const imm = - ComputeOffsetFromStrides<typename Base::ImmediateOffsetStrides>::get(0, 0, w, c); - Load<Scalar, TileTraits_::kAccessSize, MemorySpace::kGlobal>::load(value, params.pointer, imm); - } - - /// Increment the pointer in the H dimension. - CUTLASS_DEVICE void inc_h() { params.pointer += params.inc_h; } - /// Increment the pointer in the D dimension. - CUTLASS_DEVICE void inc_d() { params.pointer += params.inc_d; } - /// Increment the pointer to move to the next iteration. - CUTLASS_DEVICE void inc_advance() { params.pointer += params.inc_advance; } - - /// Initialize the predicates. - CUTLASS_DEVICE void initialize_predicates(const Coord<3>& bounds, const Coord<3>& block) { - // Setup the masks to control loads. - predicates.fill(0); - - int bounds_h, bounds_w; - if (kAdvance == IteratorAdvance::kH) { - bounds_w = bounds[2] - block[2]; - bounds_h = bounds[1]; - - } else { - bounds_w = bounds[1]; - bounds_h = bounds[2] - block[1]; - } - - // Fill in the bits of the predicate vector. - for (int d = 0; d < Base::Iterations::kD; ++d) { - for (int h = 0; h < Base::Iterations::kH; ++h) { - for (int w = 0; w < Base::Iterations::kW; ++w) { - for (int c = 0; c < Base::Iterations::kC; ++c) { - bool flag = w * Base::Delta::kW < bounds_w; - if (kAdvance == IteratorAdvance::kH) { - flag = flag && (h * Base::Delta::kH + d * Base::Delta::kD) < bounds_h; - } else { - flag = flag && (h * Base::Delta::kH) < bounds_h; - } - int const bit = ComputeOffsetFromShape<typename Base::Iterations>::get(d, h, w, c); - predicates.set(bit, flag); - } - } - } - } - } - - /// Move to residue portion. - CUTLASS_DEVICE void move_to_residue(Index k) { - // Store the pointer and the predicates. - stored_pointer = params.pointer; - stored_predicates = predicates; - - // Move the pointer to the residue. - params.pointer += params.move_to_residue_offset; - - // The dimensions of the tile. - int const kH = TileTraits_::Tile::kH; - int const kW = TileTraits_::Tile::kW * TileTraits_::kAccessSize; - - // The unrolling factor. - int const kUnroll = kAdvance == IteratorAdvance::kH ? kH : kW; - - // Clear the predicates for the residue. TODO: We can do something smarter. - int const kResidue = (int)(k % (Index)kUnroll); - if (kResidue > 0) { - residue(kResidue); - } - } - - /// That's the residue! Update the predicates. - CUTLASS_DEVICE void residue(Index k) { - // The coordinates of the thread. - Index block_h = thread_offset[1]; - // The contiguous dimension. - Index block_w = thread_offset[2]; - - // Update the predicate vector. - for (int d = 0; d < Base::Iterations::kD; ++d) { - for (int h = 0; h < Base::Iterations::kH; ++h) { - for (int w = 0; w < Base::Iterations::kW; ++w) { - for (int c = 0; c < Base::Iterations::kC; ++c) { - Index offset = 0; - if (kAdvance == IteratorAdvance::kH) { - offset += block_h + h * Base::Delta::kH + d * Base::Delta::kD; - } else { - offset += block_w + w * Base::Delta::kW; - } - - int const bit = ComputeOffsetFromShape<typename Base::Iterations>::get(d, h, w, c); - if (offset >= k) { - predicates.set(bit, false); - } - } - } - } - } - } - - /// Rollback to beginning of first tile and initialize predicates. - CUTLASS_DEVICE void rollback() { - params.pointer = stored_pointer; - predicates = stored_predicates; - } - - /// Is the iterator valid? - CUTLASS_DEVICE bool valid(int d, int h, int w, int c) const { - int const bit = ComputeOffsetFromShape<typename Base::Iterations>::get(d, h, w, c); - return predicates[bit]; - } - - /// Offset of an individual lane from the start of the tile - Coord<4> thread_offset; - /// The parameters - Params params; - /// The pointer. - typename Base::Scalar const* stored_pointer; - /// The predicates. - PredicateVector predicates, stored_predicates; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename TileTraits_, typename Index_ = int> -struct GemmGlobalIteratorCd : public TileIteratorBase<TileTraits_, - typename TileTraits_::Scalar, - IteratorAdvance::kH, - MemorySpace::kGlobal, - Index_> { - /// This class. - typedef GemmGlobalIteratorCd<TileTraits_, Index_> This_; - /// The base class. - typedef TileIteratorBase<TileTraits_, - typename TileTraits_::Scalar, - IteratorAdvance::kH, - MemorySpace::kGlobal, - Index_> - Base; - - /// The layout. - static MatrixLayout::Kind const kLayout = TileTraits_::kLayout; - - /// The scalar. - typedef typename TileTraits_::Scalar Scalar; - /// The pointer. - typedef typename TileTraits_::Pointer Pointer; - /// The threads. - typedef typename TileTraits_::Threads Threads; - /// The index. - typedef Index_ Index; - /// The thread offset - typedef typename TileTraits_::ThreadOffset ThreadOffset; - - /// The params. - struct Params { - /// The pointer. - Pointer pointer; - /// The stride in the H dimension to setup the thread in the block. - Index stride_h; - /// The strides to increment the pointer. - Index inc_advance, inc_h; - /// The strides to increment the predicate offset - Index predicate_inc_advance, predicate_inc_h; - /// The column offset to compute the predicate for the columns. - Index predicate_offset; - - /// Setup the params. - CUTLASS_HOST_DEVICE int initialize( - Pointer pointer, Index ld, Index bound, Index epilogue_stride_w, Index epilogue_delta_w) { - // The pointer. - this->pointer = pointer; - // Each column of the matrix. - stride_h = TileTraits_::ThreadsDelta::kH * ld; - // Each thread output 1 column per iteration. The stride between columns is given by the - // number of scalars that are loaded per LDS for B. - inc_h = ld * TileTraits_::kStrideH; - inc_advance = - (ld - ld * TileTraits_::kStrideH * (Base::Iterations::kH - 1)) + epilogue_stride_w; - - predicate_offset = bound; - predicate_inc_h = TileTraits_::kStrideH; - predicate_inc_advance = - -((TileTraits_::kStrideH * (Base::Iterations::kH - 1) - 1) + epilogue_delta_w); - - return 0; - } - }; - - Params params; - /// Offset of an individual lane from the start of the tile - Coord<4> thread_offset; - - /// Ctor. - CUTLASS_DEVICE GemmGlobalIteratorCd() {} - - /// Ctor. - CUTLASS_DEVICE GemmGlobalIteratorCd(Params const& params, - const Coord<3>& bounds, - const Coord<3>& block, - int offset = 0, - int pred_offset = 0, - ThreadOffset thread_offset_func = ThreadOffset()) - : params(params) { - thread_offset = thread_offset_func(); - // Each warp works on a different column of the tile. - int const h = thread_offset[1] + block[1]; - // Each lane writes a different element. - int const w = thread_offset[2] + block[2]; - // Setup the pointer. - this->params.pointer += ((h * params.stride_h + w) + offset); - - // Prepare the vector of predicates. - for (int i = 0; i < Base::Iterations::kW; ++i) { - predicates.set(i, w + i * Base::Delta::kW < bounds[2]); - } - this->params.predicate_offset -= (h + pred_offset); - } - - /// The accessor. - CUTLASS_DEVICE void get(typename Base::AccessType& value, int d, int h, int w, int c) const { - int const imm = - ComputeOffsetFromStrides<typename Base::ImmediateOffsetStrides>::get(0, 0, w, c); - Load<Scalar, TileTraits_::kAccessSize, MemorySpace::kGlobal>::load(value, params.pointer, imm); - } - - /// Increment the pointer in the C dimension. - CUTLASS_DEVICE void inc_c() {} - /// Increment the pointer in the W dimension. - CUTLASS_DEVICE void inc_w() {} - /// Increment the pointer in the H dimension. - CUTLASS_DEVICE void inc_h() { - params.pointer += params.inc_h; - params.predicate_offset -= params.predicate_inc_h; - } - /// Increment the pointer in the D dimension. - CUTLASS_DEVICE void inc_d() {} - /// Increment the pointer to move to the next iteration. - CUTLASS_DEVICE void inc_advance() { - params.pointer += params.inc_advance; - this->params.predicate_offset -= params.predicate_inc_advance; - } - - /// The accessor. - CUTLASS_DEVICE void set(typename Base::AccessType const& value, int d, int h, int w, int c) { - int const imm = - ComputeOffsetFromStrides<typename Base::ImmediateOffsetStrides>::get(0, 0, w, c); - Store<Scalar, TileTraits_::kAccessSize, MemorySpace::kGlobal>::store( - value, params.pointer, imm); - } - - /// Test the validity of the iterator. - CUTLASS_DEVICE bool valid(int d, int h, int w, int c) const { - return predicates.at(w) && params.predicate_offset > 0; - } - - /// The predicates for the row. - cutlass::PredicateVector<Base::Iterations::kW> predicates; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/gemm_operand.h b/cutlass-example/cutlass/gemm/gemm_operand.h deleted file mode 100644 index 737f993..0000000 --- a/cutlass-example/cutlass/gemm/gemm_operand.h +++ /dev/null @@ -1,141 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines constant expressions for mapping GEMM problem size and strides onto pitch-linear - memory. -*/ -#pragma once - -#include <cutlass/matrix_traits.h> -#include <cutlass/reshape_tile.h> -#include <cutlass/util/platform.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Helper to describe attributes of GEMM matrix operands -template <GemmOperand::Kind kOperand_, MatrixLayout::Kind kLayout_> -struct GemmOperandTraitsAb { - static const bool Congruous = - (kOperand_ == GemmOperand::kA ^ kLayout_ == MatrixLayout::kRowMajor); -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmOperand::Kind kOperand_, typename Tile_> -struct GetExtent; - -template <typename Tile_> -struct GetExtent<GemmOperand::kA, Tile_> { - static const int kExtent = Tile_::kW; -}; - -template <typename Tile_> -struct GetExtent<GemmOperand::kB, Tile_> { - static const int kExtent = Tile_::kH; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Determines the shape of a multiplicand tile in terms of strided (H) and contiguous (W) -/// dimensions -template <typename ThreadBlockTile_, GemmOperand::Kind Usage, MatrixLayout::Kind Layout> -struct GemmMultiplicandTraits { - // Only defined for A or B - static_assert(Usage == GemmOperand::kA || Usage == GemmOperand::kB, - "MultiplicandTileShape defined only for A or B operands."); - - /// Shape of GEMM thread block tile (K, N, M) - typedef ThreadBlockTile_ ThreadBlockTile; - - /// Identifies multiplicand - static GemmOperand::Kind const kUsage = Usage; - - /// Layout of tile - static MatrixLayout::Kind const kLayout = Layout; - - // True if K is the strided dimension - static bool const kKstrided = (kUsage == GemmOperand::kA ^ kLayout == MatrixLayout::kRowMajor); - - /// Map the ThreadBlockShape onto (kH, kW) dimensions for A and B operand - typedef typename platform::conditional< - kKstrided, - Shape<1, ThreadBlockTile::kD, GetExtent<Usage, ThreadBlockTile>::kExtent>, - Shape<1, GetExtent<Usage, ThreadBlockTile>::kExtent, ThreadBlockTile::kD> >::type Shape; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Project's a coordinate (K, N, M) onto inner and outer dimensions defined for each -/// operand. -template <GemmOperand::Kind operand, bool Kstrided = true> -struct ProjectOperand; - -/// Project A operand - (0, K, M) -template <bool Kstrided> -struct ProjectOperand<GemmOperand::kA, Kstrided> { - CUTLASS_HOST_DEVICE - static Coord<3> project(Coord<3> const &coord) { - if (Kstrided) { - return make_Coord(0, coord[0], coord[2]); - } else { - return make_Coord(0, coord[2], coord[0]); - } - } -}; - -/// Project B operand - (0, K, N) -template <bool Kstrided> -struct ProjectOperand<GemmOperand::kB, Kstrided> { - CUTLASS_HOST_DEVICE - static Coord<3> project(Coord<3> const &coord) { - if (Kstrided) { - return make_Coord(0, coord[0], coord[1]); - } else { - return make_Coord(0, coord[1], coord[0]); - } - } -}; - -/// Project C operand - (0, N, M) -template <> -struct ProjectOperand<GemmOperand::kC, true> { - CUTLASS_HOST_DEVICE - static Coord<3> project(Coord<3> const &coord) { return make_Coord(0, coord[1], coord[2]); } -}; - -/// Project D operand - (0, N, M) -template <> -struct ProjectOperand<GemmOperand::kD, true> { - CUTLASS_HOST_DEVICE - static Coord<3> project(Coord<3> const &coord) { return make_Coord(0, coord[1], coord[2]); } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/gemm_shared_stream.h b/cutlass-example/cutlass/gemm/gemm_shared_stream.h deleted file mode 100644 index c6ff7bd..0000000 --- a/cutlass-example/cutlass/gemm/gemm_shared_stream.h +++ /dev/null @@ -1,113 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines abstractions for managing loading and storing fragments to shared memory in the - efficient GEMM pipeline. -*/ -#pragma once - -#include <cutlass/gemm/gemm_shared_tile.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The load iterator. - typename Iterator_, - /// The transformer to be applied after the data has been copied from shared memory. - typename Transformer_ = Copy<typename Iterator_::Fragment> > - -struct SharedLoadStream { - /// The load iterator. - typedef Iterator_ Iterator; - /// The transformer. - typedef Transformer_ Transformer; - - /// The fragment that is copied from shared memory. - typedef typename Iterator::Fragment FetchedFragment; - /// The fragment that is obtained after the transformation by the transformer. - typedef typename Transformer::OutputFragment TransformedFragment; - /// Make sure the fragments match. - static_assert((platform::is_same<FetchedFragment, typename Transformer::InputFragment>::value), - ""); - /// The output fragment. - typedef TransformedFragment Fragment; - - /// The params. - struct Params { - /// The iterator params. - typename Iterator::Params iterator; - - /// Setup the params. - CUTLASS_HOST_DEVICE int initialize() { return iterator.initialize(); } - }; - - /// The storage in shared memory needed by that stream. - typedef typename Iterator::Storage SharedStorage; - - /// Ctor. - CUTLASS_DEVICE SharedLoadStream() {} - - /// Ctor. - CUTLASS_DEVICE SharedLoadStream(Params const ¶ms, SharedStorage &shared_storage) { - this->initialize(params, shared_storage); - } - - /// Initialize the stream. - CUTLASS_DEVICE void initialize(Params const ¶ms, SharedStorage &shared_storage) { - // The iterator. - iterator = Iterator(params.iterator, shared_storage); - // The transformer. - transformer = Transformer(); - } - - /// Load the data from shared memory to the fetch fragment. - CUTLASS_DEVICE void copy(FetchedFragment &fetched) { shared_iterator_load(iterator, fetched); } - - /// Load the data from shared memory to the fetch fragment. - CUTLASS_DEVICE void copy(int d, FetchedFragment &fetched) { - shared_iterator_load(iterator, fetched, d); - } - - /// Commit the data. - CUTLASS_DEVICE void commit(FetchedFragment &fetched, TransformedFragment &transformed) { - transformer.transform(fetched, transformed); - } - - /// Increment the stage. - CUTLASS_DEVICE void inc_stage() { iterator.inc_stage(); } - - /// The iterator. - Iterator iterator; - /// The transformer. - Transformer transformer; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/gemm_shared_tile.h b/cutlass-example/cutlass/gemm/gemm_shared_tile.h deleted file mode 100644 index 7c61e02..0000000 --- a/cutlass-example/cutlass/gemm/gemm_shared_tile.h +++ /dev/null @@ -1,417 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines iterators for efficiently loading and storing tiles to and from shared memory. -*/ -#pragma once - -#include <cutlass/gemm/gemm_operand.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, typename Tile_, typename Threads_, int kScalarsPerSts_> -struct GemmSharedStoreTileAbTraits { - /// The scalar. - typedef typename platform::remove_const<Scalar_>::type Scalar; - /// The pointer. - typedef Scalar_* Pointer; - /// The tile. - typedef typename ReshapeTile<Tile_, kScalarsPerSts_>::Tile Tile; - /// The threads. - typedef Threads_ Threads; - /// The strides to compute the base position of the thread. - typedef Shape<0, ShapeCount<Tile>::kWc, Tile::kC, kScalarsPerSts_> ThreadsStrides; - /// The skew. - static int const kSkew = 0; - /// The number of scalars per LDG/STG. - static int const kAccessSize = kScalarsPerSts_; - /// The memory space. - static MemorySpace::Kind const kMemorySpace = MemorySpace::kShared; - - /// The number of iterations needed to load/store the tile. - typedef Shape<1, - Tile::kH / Threads::kH, - Tile::kW / Threads::kW, - Tile::kC / Threads::kC / kAccessSize> - Iterations; - /// The strides in each dimension between different loads/stores. - typedef Shape<0, Threads::kH * ShapeCount<Tile>::kWc, Threads::kW * kAccessSize> Delta; - /// The strides in each dimension between different loads/stores. - typedef Shape<0, Threads::kH * ShapeCount<Tile>::kWc, Threads::kW * kAccessSize> - ImmediateOffsetStrides; - - struct ThreadOffset { - CUTLASS_HOST_DEVICE - Coord<4> operator()() const { - int offset = ComputeThreadOffsetFromStrides<Threads, ThreadsStrides>::get(); - return make_Coord(0, 0, offset, 0); - } - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, typename Tile_, typename Threads_, int kScalarsPerSts_, int kSkew_> -struct GemmSharedStoreWithSkewTileAbTraits { - /// The scalar. - typedef typename platform::remove_const<Scalar_>::type Scalar; - /// The pointer. - typedef Scalar_* Pointer; - /// The tile without skews. - typedef typename ReshapeTile<Tile_, kScalarsPerSts_>::Tile TileWithoutSkew; - /// The tile. - typedef typename ReshapeTile<Shape<Tile_::kD, Tile_::kH, Tile_::kW + kSkew_>, - kScalarsPerSts_>::Tile Tile; - /// The threads. - typedef Threads_ Threads; - /// The skew. - static int const kSkew = kSkew_; - /// The number of scalars per STS. - static int const kAccessSize = kScalarsPerSts_; - /// The memory space. - static MemorySpace::Kind const kMemorySpace = MemorySpace::kShared; - - /// The number of iterations needed to load/store the tile. - typedef Shape<1, TileWithoutSkew::kH / Threads::kW, TileWithoutSkew::kW / Threads::kH> Iterations; - /// The strides in each dimension between different loads/stores. - typedef Shape<0, ShapeCount<Tile>::kWc, Threads::kH * kAccessSize> Delta; - /// The strides in each dimension between different loads/stores. - typedef Shape<0, ShapeCount<Tile>::kWc, Threads::kH * kAccessSize> ImmediateOffsetStrides; - - struct ThreadOffset { - CUTLASS_HOST_DEVICE Coord<4> operator()() const { - int offset = ComputeThreadOffsetFromStrides<Threads, ThreadsStrides>::get(); - return make_Coord(0, 0, offset, 0); - } - }; - - protected: - /// The strides to compute the base position of the thread. - typedef Shape<0, kScalarsPerSts_, ShapeCount<Tile>::kHwc / Threads::kW> ThreadsStrides; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, - typename OutputTile_, - typename Warps_, - typename ThreadsPerWarp_, - typename InstructionShape_, - int kStages_, - int kScalarsPerLds_, - int kSkew_ = 0> -struct GemmSharedLoadTileATraits { - static GemmOperand::Kind const kOperand = GemmOperand::kA; - /// The scalar. - typedef typename platform::remove_const<Scalar_>::type Scalar; - /// The pointer. - typedef Scalar_* Pointer; - /// The tile without skew. - typedef Shape<kStages_, - OutputTile_::kD / InstructionShape_::kD, - GetExtent<kOperand, OutputTile_>::kExtent * InstructionShape_::kD> - TileWithoutSkew_; - /// The tile with skew. - typedef Shape<kStages_, TileWithoutSkew_::kH, TileWithoutSkew_::kW + kSkew_> TileWithSkew; - /// The tile without skew after reshaping. - typedef typename ReshapeTile<TileWithoutSkew_, kScalarsPerLds_>::Tile TileWithoutSkew; - /// The tile. - typedef typename ReshapeTile<TileWithSkew, kScalarsPerLds_>::Tile Tile; - /// The number of warps. - typedef Warps_ Warps; - /// The threads in a warp. - typedef ThreadsPerWarp_ ThreadsPerWarp; - /// The number of scalars per LDG/STG. - // static int const kScalarsPerLds = kScalarsPerLds_; - static int const kAccessSize = kScalarsPerLds_; - /// The skew. - static int const kSkew = kSkew_; - /// The memory space. - static MemorySpace::Kind const kMemorySpace = MemorySpace::kShared; - - /// The number of warps. - static int const kWarps = GetExtent<kOperand, Warps>::kExtent; - /// The number of threads in one dimension of the warp. - static int const kThreadsPerWarp = GetExtent<kOperand, ThreadsPerWarp>::kExtent; - - /// The number of iterations needed to load/store the tile. - typedef Shape<1, 1, TileWithoutSkew::kW / kWarps / kThreadsPerWarp /* / kScalarsPerLds*/> - Iterations; - /// The strides in each dimension between different loads/stores. - typedef Shape<TileWithSkew::kW * Warps::kD, 0, kWarps * kThreadsPerWarp * kAccessSize, 0> - ImmediateOffsetStrides; - typedef Shape<TileWithSkew::kW * Warps::kD, 0, kWarps * kThreadsPerWarp * kAccessSize, 0> Delta; - - /// Computes the thread offset in (H, W) based on thread ID - struct ThreadOffset { - CUTLASS_HOST_DEVICE Coord<4> operator()() const { - // Extract the warp. - int const warp = threadIdx.x / kWarpSize; - // Extract the slice. - int const slice = warp / (Warps::kH * Warps::kW); - // Compute the row offset for each warp. - int const warp_row = warp % Warps::kW; - // Compute the row offset for each thread. - int const lane_row = (threadIdx.x & 0x0e) / 2; - // The offset. - int const offset = - slice * Tile::kW * Tile::kC + (warp_row * ThreadsPerWarp::kW + lane_row) * kAccessSize; - // Embed the offset in a 4D coordinate vector. - return make_Coord(0, 0, offset, 0); - } - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, - typename OutputTile_, - typename Warps_, - typename ThreadsPerWarp_, - typename InstructionShape_, - int kStages_, - int kScalarsPerLds_, - int kSkew_ = 0> -struct GemmSharedLoadTileBTraits { - static GemmOperand::Kind const kOperand = GemmOperand::kB; - /// The scalar. - typedef typename platform::remove_const<Scalar_>::type Scalar; - /// The pointer. - typedef Scalar_* Pointer; - /// The tile without skew. - typedef Shape<kStages_, - OutputTile_::kD / InstructionShape_::kD, - GetExtent<kOperand, OutputTile_>::kExtent * InstructionShape_::kD> - TileWithoutSkew_; - /// The tile with skew. - typedef Shape<kStages_, TileWithoutSkew_::kH, TileWithoutSkew_::kW + kSkew_> TileWithSkew; - /// The tile without skew after reshaping. - typedef typename ReshapeTile<TileWithoutSkew_, kScalarsPerLds_>::Tile TileWithoutSkew; - /// The tile. - typedef typename ReshapeTile<TileWithSkew, kScalarsPerLds_>::Tile Tile; - /// The number of warps. - typedef Warps_ Warps; - /// The threads in a warp. - typedef ThreadsPerWarp_ ThreadsPerWarp; - /// The number of scalars per LDG/STG. - static int const kAccessSize = kScalarsPerLds_; - /// The skew. - static int const kSkew = kSkew_; - /// The memory space. - static MemorySpace::Kind const kMemorySpace = MemorySpace::kShared; - - /// The number of warps. - static int const kWarps = GetExtent<kOperand, Warps>::kExtent; - /// The number of threads in one dimension of the warp. - static int const kThreadsPerWarp = GetExtent<kOperand, ThreadsPerWarp>::kExtent; - - /// The number of iterations needed to load/store the tile. - typedef Shape<1, 1, TileWithoutSkew::kW / kWarps / kThreadsPerWarp /* / kAccessSize*/> Iterations; - /// The strides in each dimension between different loads/stores. - typedef Shape<TileWithSkew::kW * Warps::kD, 0, kWarps * kThreadsPerWarp * kAccessSize, 0> - ImmediateOffsetStrides; - typedef Shape<TileWithSkew::kW * Warps::kD, 0, kWarps * kThreadsPerWarp * kAccessSize, 0> Delta; - - /// Computes the thread offset in (H, W) based on thread ID - struct ThreadOffset { - CUTLASS_HOST_DEVICE Coord<4> operator()() const { - // Extract the warp. - int const warp = threadIdx.x / kWarpSize; - // Extract the slice. - int const slice = warp / (Warps::kH * Warps::kW); - // The warp in the slice. - int const warp_in_slice = warp % (Warps::kH * Warps::kW); - // Compute the row offset for each warp. - int const warp_col = warp_in_slice / Warps::kW; - // Compute the row offset for each thread. - int const lane_col = (threadIdx.x & 0x10) / 8 + (threadIdx.x & 0x01); - // The offset. - int const offset = - slice * Tile::kW * Tile::kC + (warp_col * ThreadsPerWarp::kH + lane_col) * kAccessSize; - // Embed the offset in a 4D coordinate. - return make_Coord(0, 0, offset, 0); - } - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, - typename OutputTile_, - typename Warps_, - typename ThreadsPerWarp_, - int kScalarsPerSts_, - int kSkew_ = 0> -struct GemmSharedStoreTileDTraits { - /// The scalar. - typedef typename platform::remove_const<Scalar_>::type Scalar; - /// The pointer. - typedef Scalar_* Pointer; - /// The dimension of the output tile. - typedef OutputTile_ OutputTile; - /// The warps in the tile. - typedef Warps_ Warps; - /// The threads in the warps. - typedef ThreadsPerWarp_ ThreadsPerWarp; - /// The number of scalars per LDG/STG. - static int const kAccessSize = kScalarsPerSts_; - /// The skew. - static int const kSkew = kSkew_; - /// The memory space. - static MemorySpace::Kind const kMemorySpace = MemorySpace::kShared; - - /// The number of scalars per thread. - static int const kScalarsPerThread = OutputTile_::kW / Warps::kW / ThreadsPerWarp::kW; - /// The number of threads. - static int const kThreads = ShapeCount<Warps>::kCount * kWarpSize; - /// The number of scalars per row. We build a tile with 2 rows (to avoid bank conflicts). - static int const kScalarsPerRow = kThreads / 2 * kScalarsPerThread + kSkew; - - /// The tile. - typedef Shape<1, 2, kScalarsPerRow / kAccessSize, kAccessSize> Tile; - /// The number of iterations needed to store the tile. - typedef Shape<1, 1, kScalarsPerThread / kAccessSize> Iterations; - /// The strides in each dimension between different loads/stores. - typedef Shape<0, 0, Warps::kW * ThreadsPerWarp::kW * kAccessSize> Delta; - /// The strides in each dimension between different loads/stores. - typedef Shape<0, 0, Warps::kW * ThreadsPerWarp::kW * kAccessSize> ImmediateOffsetStrides; - - /// Computes the thread offset in (H, W) based on thread ID - struct ThreadOffset { - CUTLASS_HOST_DEVICE Coord<4> operator()() const { - // The warp. - int const warp = threadIdx.x / kWarpSize; - - // The position of the warp in the 2D tile. - int const warp_row = warp % Warps::kW; - int const warp_col = warp / Warps::kW; - - // We assume that the elements are distributed in a warps as 4 columns of 8 elements. The - // columns are stored in threads col0=[0, 2, 4, 6, 8, 10, 12, 14], col1=[1, 3, 5, 7, .., 15], - // col2=[16, 18, 20, ..., 30] and col3=[17, 19, ..., 31]. - int hi_halfwarp_offset = ((threadIdx.x >> 4) & 0x1) * OutputTile::kW; - int lo_halfwarp_offset = ((threadIdx.x >> 1) & 0x7) + ThreadsPerWarp::kW * warp_row; - - // Odd threads go to the second half of shared memory. - int const row = threadIdx.x & 0x01; - int col = warp_col * (ThreadsPerWarp::kH / 2) * OutputTile::kW + - lo_halfwarp_offset * kAccessSize + hi_halfwarp_offset; - // Embed the offset in a 4D coords. - return make_Coord(0, 0, row * kScalarsPerRow + col, 0); - } - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, - typename OutputTile_, - typename Warps_, - typename ThreadsPerWarp_, - int kTileH_, - int kScalarsPerLds_, - int kSkew_ = 0> -struct GemmSharedLoadTileDTraits { - /// The scalar. - typedef typename platform::remove_const<Scalar_>::type Scalar; - /// The pointer. - typedef Scalar_* Pointer; - /// The dimension of the output tile. - typedef OutputTile_ OutputTile; - /// The warps in the tile. - typedef Warps_ Warps; - /// The threads in the warps. - typedef ThreadsPerWarp_ ThreadsPerWarp; - /// The number of scalars per LDG/STG. - static int const kAccessSize = kScalarsPerLds_; - /// The skew. - static int const kSkew = kSkew_; - /// The memory space. - static MemorySpace::Kind const kMemorySpace = MemorySpace::kShared; - - /// The number of scalars per thread. - static int const kScalarsPerThread = OutputTile_::kW / Warps::kW / ThreadsPerWarp::kW; - /// The number of threads. - static int const kThreads = ShapeCount<Warps>::kCount * kWarpSize; - /// The number of scalars per row. We build a tile with 2 rows (to avoid bank conflicts). - static int const kScalarsPerRow = kThreads / 2 * kScalarsPerThread + kSkew; - - /// The tile. We have 2 rows of scalars. We use those two rows to make sure we do not have bank - /// conflicts in the epilogue. - typedef Shape<1, 2, kScalarsPerRow / kAccessSize, kAccessSize> Tile; - - // Compute the number of iterations per warp in the Tile::kH dimension. - static int const kIterationsInHPerWarp = kTileH_ / ShapeCount<Warps>::kCount; - - // As explained above, the shared memory tile is composed of 2 rows and each rows is made of - // kScalarsPerRow. A warp is expected to read from the 1st row, then move to the 2nd row and go - // back to the 1st row. To model that scheme we define the Iterations shape as Shape<X, 2, ...>. - // However, in some cases, we have only 1 iteration per warp. In that case, we must define the - // shape as Shape<1, 1, ...>. The following code does that except that we hijack the kH dimension - // to keep the number of elements to reduce for split-K. - static int const kIterationsH = kIterationsInHPerWarp == 1 ? 1 : 2; - // As soon as we know kIterationsH, it is trivial to compute kIterationsD: - static int const kIterationsD = kIterationsInHPerWarp / kIterationsH; - - // If we have split-K enabled, we have to jump over the elements from the "odd/even" column of - // threads to grab the other elements. - static int const kSplitK = OutputTile::kW * ThreadsPerWarp::kH / 2 * Warps::kH; - - /// The number of iterations needed to store the tile. - typedef Shape<kIterationsD, kIterationsH, OutputTile::kW / kWarpSize / kAccessSize, Warps::kD> - Iterations; - /// The strides in each dimension between different loads/stores. - typedef Shape<OutputTile::kW, kScalarsPerRow, kWarpSize * kAccessSize, kSplitK> - ImmediateOffsetStrides; - /// The strides in each dimension between different loads/stores. - typedef Shape<OutputTile::kW, kScalarsPerRow, kWarpSize * kAccessSize, kSplitK> Delta; - - /// Computes the thread offset in (H, W) based on thread ID - struct ThreadOffset { - CUTLASS_HOST_DEVICE Coord<4> operator()() const { - // Each warp works on a different column. - int const h = threadIdx.x / kWarpSize; - // Compute the row. - int const w = (threadIdx.x & (kWarpSize - 1)) * kAccessSize; - int offset = 0; - if (Iterations::kH == 1) { - int const row = h & 0x1; - int const col = h / 2; - offset = row * ShapeCount<Tile>::kWc + col * OutputTile::kW * Iterations::kD + w; - } else { - offset = h * OutputTile::kW * Iterations::kD + w; - } - return make_Coord(0, 0, offset, 0); - } - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/gemm_traits.h b/cutlass-example/cutlass/gemm/gemm_traits.h deleted file mode 100644 index cb57c4d..0000000 --- a/cutlass-example/cutlass/gemm/gemm_traits.h +++ /dev/null @@ -1,818 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines structural properties of complete GEMM computation. -*/ -#pragma once - -#include <cutlass/convert.h> -#include <cutlass/gemm/clear_accumulators.h> -#include <cutlass/gemm/gemm_global_stream.h> -#include <cutlass/gemm/gemm_operand.h> -#include <cutlass/gemm/gemm_shared_stream.h> -#include <cutlass/gemm/identity_block_swizzle.h> -#include <cutlass/matrix_traits.h> -#include <cutlass/reshape_tile.h> -#include <cutlass/tile_iterator.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The scalar type for A. - typename ScalarA_, - /// The scalar type for B. - typename ScalarB_, - /// The scalar type for C. - typename ScalarC_, - /// The scalar type for D. - typename ScalarD_, - /// The output tile size for the GEMM KxNxM. - typename OutputTile_, - /// The functor to do the math. - typename MultiplyAdd_, - /// The number of scalars per LDG for A. - int kScalarsPerLdgA_, - /// The number of scalars per STS for A. - int kScalarsPerStsA_, - /// The number of scalars per LDG for A. - int kScalarsPerLdsA_, - /// The number of scalars per LDG for B. - int kScalarsPerLdgB_, - /// The number of scalars per STS for B. - int kScalarsPerStsB_, - /// The number of scalars per LDS for B. - int kScalarsPerLdsB_, - /// The number of scalars per LDG for C and STG for D. - int kScalarsPerLdgCAndStgD_, - /// The number of scalars per STS for D. - int kScalarsPerStsD_, - /// The number of scalars per LDS for D. - int kScalarsPerLdsD_, - /// The number of stages in shared memory to do single/double/triple-buffering. - int kStages_, - /// Do we do the residue in the prologue? - bool kResidueInPrologue_ = false> - -struct GemmConfig { - // - /// The scalar for A. - typedef ScalarA_ ScalarA; - /// The scalar for B. - typedef ScalarB_ ScalarB; - /// The scalar for C. - typedef ScalarC_ ScalarC; - /// The scalar for D. - typedef ScalarD_ ScalarD; - - /// The tile. - typedef OutputTile_ OutputTile; - /// The functor to do D = A*B + C. - typedef MultiplyAdd_ MultiplyAdd; - /// The shape of the instruction. - typedef typename MultiplyAdd::InstructionShape InstructionShape; - /// The number of accumulators per warp. - typedef typename MultiplyAdd::AccumulatorsPerWarp AccumulatorsPerWarp; - /// The accumulators. - typedef typename MultiplyAdd::Accumulators Accumulators; - - /// The number of warps. - typedef typename ShapeDiv<OutputTile, AccumulatorsPerWarp>::Shape Warps; - /// The default warp size (32 threads per warp). - static int const kWarpSize = cutlass::kWarpSize; - /// The numnber of threads. - static int const kThreads = ShapeCount<Warps>::kCount * kWarpSize; - - /// The number of scalars per LDG/STS/LDS for A. - static int const kScalarsPerLdgA = kScalarsPerLdgA_; - static int const kScalarsPerStsA = kScalarsPerStsA_; - static int const kScalarsPerLdsA = kScalarsPerLdsA_; - - /// The number of scalars per LDG/STS/LDS for B. - static int const kScalarsPerLdgB = kScalarsPerLdgB_; - static int const kScalarsPerStsB = kScalarsPerStsB_; - static int const kScalarsPerLdsB = kScalarsPerLdsB_; - - /// The number of scalars per LDG for C. - static int const kScalarsPerLdgC = kScalarsPerLdgCAndStgD_; - - /// The number of scalars per STS/LDS/STG for D. - static int const kScalarsPerStgD = kScalarsPerLdgCAndStgD_; - static int const kScalarsPerStsD = kScalarsPerStsD_; - static int const kScalarsPerLdsD = kScalarsPerLdsD_; - - /// The number of accumulators that are going to be fed from one LDS A/B. - static int const kAccumulatorsPerLdsA = kScalarsPerLdsA / InstructionShape::kD; - static int const kAccumulatorsPerLdsB = kScalarsPerLdsB / InstructionShape::kD; - - /// The number of stages in shared memory to implement double, triple, more-buffering. - static int const kStages = kStages_; - - /// Do we do the residue in the prologue? - static bool const kResidueInPrologue = kResidueInPrologue_; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <enum MatrixLayout::Kind, typename GemmConfig_> -struct GemmTileTraitsHelperA {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_> -struct GemmTileTraitsHelperA<MatrixLayout::kColumnMajor, GemmConfig_> { - /// The layout. - static MatrixLayout::Kind const kLayout = MatrixLayout::kColumnMajor; - - /// The input scalar. - typedef typename GemmConfig_::ScalarA Scalar; - /// The scalar stored in shared memory. - typedef typename GemmConfig_::MultiplyAdd::ScalarA MultiplyAddScalar; - - /// The traits class to build the iterator to load data from global memory for A^N. - typedef GemmGlobalTileTraits< - // That's A. - GemmOperand::kA, - // A is column-major. - MatrixLayout::kColumnMajor, - // The pointer is float const. - Scalar const, - // The tile has size KxM in GEMM's terminology. - Shape<1, GemmConfig_::OutputTile::kD, GemmConfig_::OutputTile::kW>, - // The threads are distributed as warps x 32 (the traits may reorganize). - Shape<1, ShapeCount<typename GemmConfig_::Warps>::kCount, GemmConfig_::kWarpSize>, - // The number of scalars per LDG (LDG.32 or LDG.128, etc). - GemmConfig_::kScalarsPerLdgA> - GlobalTileTraits; - - /// The traits class to build the iterator to store data to shared memory for A^N. - typedef GemmSharedStoreTileAbTraits< - // The pointer is float. - MultiplyAddScalar, - // The tile has size KxM in GEMM's terminology. - Shape<GemmConfig_::kStages, - GemmConfig_::OutputTile::kD / GemmConfig_::InstructionShape::kD, - GemmConfig_::OutputTile::kW * GemmConfig_::InstructionShape::kD>, - // The threads are distributed as warps x 32 (the traits may reorganize). - typename GlobalTileTraits::Threads, - // The number of scalars per STS (STS.32 or STS.128, etc). - GemmConfig_::kScalarsPerStsA> - SharedStoreTileTraits; - - /// The traits class to build the iterator to load from shared memory for A^N. - typedef GemmSharedLoadTileATraits< - // The pointer is float const. - MultiplyAddScalar const, - // The output tile size. - typename GemmConfig_::OutputTile, - // The number of warps. - typename GemmConfig_::Warps, - // The number of threads per warp. - typename GemmConfig_::MultiplyAdd::ThreadsPerWarp, - // The shape of the FMA instruction. - typename GemmConfig_::InstructionShape, - // The number of stages. - GemmConfig_::kStages, - // The number of scalars per LDS. - GemmConfig_::kScalarsPerLdsA, - // The skew. - 0> - SharedLoadTileTraits; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_> -struct GemmTileTraitsHelperA<MatrixLayout::kRowMajor, GemmConfig_> { - /// The layout. - static MatrixLayout::Kind const kLayout = MatrixLayout::kRowMajor; - - /// The input scalar. - typedef typename GemmConfig_::ScalarA Scalar; - /// The scalar stored in shared memory. - typedef typename GemmConfig_::MultiplyAdd::ScalarA MultiplyAddScalar; - - /// The traits class to build the iterator to load data from global memory for A^T. - typedef GemmGlobalTileTraits< - // That's A. - GemmOperand::kA, - // A is row-major. - MatrixLayout::kRowMajor, - // The pointer is float const. - Scalar const, - // The tile has size MxK in GEMM's terminology. - Shape<1, GemmConfig_::OutputTile::kW, GemmConfig_::OutputTile::kD>, - // The threads are distributed as (threads / K) x K (the traits may reorganize). - Shape<1, GemmConfig_::kThreads / GemmConfig_::OutputTile::kD, GemmConfig_::OutputTile::kD>, - // The number of scalars per LDG (LDG.32 or LDG.128, etc). - GemmConfig_::kScalarsPerLdgA> - GlobalTileTraits; - - /// The number of scalars in 4B. - static int const kScalarsIn4B = sizeof(MultiplyAddScalar) > 4 ? 1 : 4 / sizeof(MultiplyAddScalar); - /// The skew for A. - static int const kSkewA = 128 / sizeof(MultiplyAddScalar) / GemmConfig_::kScalarsPerStsA / - GlobalTileTraits::Threads::kW * kScalarsIn4B; - - /// The traits class to build the iterator to store data to shared memory for A^T. - typedef GemmSharedStoreWithSkewTileAbTraits < - // The pointer is float. - MultiplyAddScalar, - // The tile has size KxM in GEMM's terminology. - Shape<GemmConfig_::kStages, - GemmConfig_::OutputTile::kD / GemmConfig_::InstructionShape::kD, - GemmConfig_::OutputTile::kW * GemmConfig_::InstructionShape::kD>, - // The threads are distributed as (threads / K) x K (the traits may reorganize). - typename GlobalTileTraits::Threads, - // The number of scalars per STS. - GemmConfig_::kScalarsPerStsA, - // The skew to avoid bank conflicts added in the tile W dimension. - kSkewA<GemmConfig_::kScalarsPerLdsA ? GemmConfig_::kScalarsPerLdsA : kSkewA> - SharedStoreTileTraits; - - /// The traits class to build the iterator to load from shared memory for A^T. - typedef GemmSharedLoadTileATraits< - // The pointer is float const. - MultiplyAddScalar const, - // The output tile size. - typename GemmConfig_::OutputTile, - // The number of warps. - typename GemmConfig_::Warps, - // The number of threads per warp. - typename GemmConfig_::MultiplyAdd::ThreadsPerWarp, - // The shape of the FMA instruction. - typename GemmConfig_::InstructionShape, - // The number of stages. - GemmConfig_::kStages, - // The number of scalars per LDS. - GemmConfig_::kScalarsPerLdsA, - // The skew. - SharedStoreTileTraits::kSkew> - SharedLoadTileTraits; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <enum MatrixLayout::Kind, typename GemmConfig_> -struct GemmTileTraitsHelperB {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_> -struct GemmTileTraitsHelperB<MatrixLayout::kColumnMajor, GemmConfig_> { - /// The layout. - static MatrixLayout::Kind const kLayout = MatrixLayout::kColumnMajor; - - /// The input scalar. - typedef typename GemmConfig_::ScalarB Scalar; - /// The scalar stored in shared memory. - typedef typename GemmConfig_::MultiplyAdd::ScalarB MultiplyAddScalar; - - /// The traits class to build the iterator to load data from global memory for B^N. - typedef GemmGlobalTileTraits< - // That's B. - GemmOperand::kB, - // B is column-major. - MatrixLayout::kColumnMajor, - // The pointer is float const. - Scalar const, - // The tile has size MxK in GEMM's terminology. - Shape<1, GemmConfig_::OutputTile::kH, GemmConfig_::OutputTile::kD>, - // The threads are distributed as (threads / K) x K (the traits may reorganize). - Shape<1, GemmConfig_::kThreads / GemmConfig_::OutputTile::kD, GemmConfig_::OutputTile::kD>, - // The number of scalars per LDG (LDG.32 or LDG.128, etc). - GemmConfig_::kScalarsPerLdgB> - GlobalTileTraits; - - /// The number of scalars in 4B. - static int const kScalarsIn4B = sizeof(MultiplyAddScalar) > 4 ? 1 : 4 / sizeof(MultiplyAddScalar); - /// The skew for B. - static int const kSkewB = 128 / sizeof(MultiplyAddScalar) / GemmConfig_::kScalarsPerStsB / - GlobalTileTraits::Threads::kW * kScalarsIn4B; - - /// The traits class to build the iterator to store data to shared memory for B^N. - typedef GemmSharedStoreWithSkewTileAbTraits < - // The pointer is float. - MultiplyAddScalar, - // The tile has size KxN in GEMM's terminology. - Shape<GemmConfig_::kStages, - GemmConfig_::OutputTile::kD / GemmConfig_::InstructionShape::kD, - GemmConfig_::OutputTile::kH * GemmConfig_::InstructionShape::kD>, - // The threads are distributed as (threads / K) x K (the traits may reorganize). - typename GlobalTileTraits::Threads, - // The number of scalars per STS. - GemmConfig_::kScalarsPerStsB, - // The skew to avoid bank conflicts added in the tile W dimension. - kSkewB<GemmConfig_::kScalarsPerLdsB ? GemmConfig_::kScalarsPerLdsB : kSkewB> - SharedStoreTileTraits; - - /// The traits class to build the iterator to load from shared memory for B^N. - typedef GemmSharedLoadTileBTraits< - // The pointer is float const. - MultiplyAddScalar const, - // The output tile size. - typename GemmConfig_::OutputTile, - // The number of warps. - typename GemmConfig_::Warps, - // The number of threads per warp. - typename GemmConfig_::MultiplyAdd::ThreadsPerWarp, - // The shape of the FMA instruction. - typename GemmConfig_::InstructionShape, - // The number of stages. - GemmConfig_::kStages, - // The number of scalars per LDS. - GemmConfig_::kScalarsPerLdsB, - // The skew. - SharedStoreTileTraits::kSkew> - SharedLoadTileTraits; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_> -struct GemmTileTraitsHelperB<MatrixLayout::kRowMajor, GemmConfig_> { - /// The layout. - static MatrixLayout::Kind const kLayout = MatrixLayout::kRowMajor; - - /// The input scalar. - typedef typename GemmConfig_::ScalarB Scalar; - /// The scalar stored in shared memory. - typedef typename GemmConfig_::MultiplyAdd::ScalarB MultiplyAddScalar; - - /// The traits class to build the iterator to load data from global memory for B^T. - typedef GemmGlobalTileTraits< - // That's B. - GemmOperand::kB, - // B is row-major. - MatrixLayout::kRowMajor, - // The pointer is float const. - Scalar const, - // The tile has size KxN in GEMM's terminology. - Shape<1, GemmConfig_::OutputTile::kD, GemmConfig_::OutputTile::kH>, - // The threads are distributed as warps x 32 (the traits may reorganize). - Shape<1, ShapeCount<typename GemmConfig_::Warps>::kCount, GemmConfig_::kWarpSize>, - // The number of scalars per LDG (LDG.32 or LDG.128, etc). - GemmConfig_::kScalarsPerLdgB> - GlobalTileTraits; - - /// The traits class to build the iterator to store data to shared memory for B^T. - typedef GemmSharedStoreTileAbTraits< - // The pointer is float. - MultiplyAddScalar, - // The tile has size KxN in GEMM's terminology. - Shape<GemmConfig_::kStages, - GemmConfig_::OutputTile::kD / GemmConfig_::InstructionShape::kD, - GemmConfig_::OutputTile::kH * GemmConfig_::InstructionShape::kD>, - // The threads are distributed as warps x 32 (the traits may reorganize). - typename GlobalTileTraits::Threads, - // The number of scalars per STS (STS.32 or STS.128, etc). - GemmConfig_::kScalarsPerStsB> - SharedStoreTileTraits; - - /// The traits class to build the iterator to load from shared memory for B^T. - typedef GemmSharedLoadTileBTraits< - // The pointer is float const. - MultiplyAddScalar const, - // The output tile size. - typename GemmConfig_::OutputTile, - // The number of warps. - typename GemmConfig_::Warps, - // The number of threads per warp. - typename GemmConfig_::MultiplyAdd::ThreadsPerWarp, - // The shape of the FMA instruction. - typename GemmConfig_::InstructionShape, - // The number of stages. - GemmConfig_::kStages, - // The number of scalars per LDS. - GemmConfig_::kScalarsPerLdsB, - // The skew. - 0> - SharedLoadTileTraits; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmTraits_, bool kResidueInPrologue_ = GemmTraits_::kResidueInPrologue> -struct GemmResidue { - /// Move to residue portion. - template <bool kIsPrologue> - static CUTLASS_DEVICE void move_to_residue(typename GemmTraits_::GlobalLoadStreamA& stream_a, - typename GemmTraits_::GlobalLoadStreamB& stream_b, - typename GemmTraits_::Index k) { - // The new code path in CUTLASS 1.0.1: We treat the residue in the prologue so we can have - // complete main loops after that. It helps simplify the logic in the main loop. - if (kIsPrologue) { - stream_a.move_to_residue(k); - stream_b.move_to_residue(k); - } - } - - /// Rollback to beginning of first tile and initialize predicates. - static CUTLASS_DEVICE void rollback(typename GemmTraits_::GlobalLoadStreamA& stream_a, - typename GemmTraits_::GlobalLoadStreamB& stream_b) { - stream_a.rollback(); - stream_b.rollback(); - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmTraits_> -struct GemmResidue<GemmTraits_, false> { - /// Move to residue portion. - template <bool kIsPrologue> - static CUTLASS_DEVICE void move_to_residue(typename GemmTraits_::GlobalLoadStreamA& stream_a, - typename GemmTraits_::GlobalLoadStreamB& stream_b, - typename GemmTraits_::Index k) { - // The index. - typedef typename GemmTraits_::Index Index; - // By how much we unroll the main loop. - Index const kUnroll = static_cast<Index>(GemmTraits_::OutputTile::kD); - - // Call the residue code. That's the same path as CUTLASS 1.0.0. - if (kIsPrologue && k < kUnroll) { - stream_a.residue(k, true); - stream_b.residue(k, true); - } else if (k <= kUnroll) { - stream_a.residue(k, false); - stream_b.residue(k, false); - } - } - - /// Rollback to beginning of first tile and initialize predicates. - static CUTLASS_DEVICE void rollback(typename GemmTraits_::GlobalLoadStreamA& stream_a, - typename GemmTraits_::GlobalLoadStreamB& stream_b) {} -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The GEMM configuration. - typename GemmConfig_, - /// The stream to load A from global memory to shared memory. - typename GlobalLoadStreamA_, - /// The stream to load B from global memory to shared memory. - typename GlobalLoadStreamB_, - /// The stream to load A from shared memory. - typename SharedLoadStreamA_, - /// The stream to load B from shared memory. - typename SharedLoadStreamB_, - /// The epilogue. - typename Epilogue_, - /// The block swizzle to reorganize the grid. - typename BlockSwizzle_ = IdentityBlockSwizzle, - /// The index. - typename Index_ = int, - /// The tool used to clear accumulators. - typename ClearAccumulators_ = ClearAccumulators<typename GemmConfig_::Accumulators::Scalar> > - -struct GemmTraits { - /// This class. - typedef GemmTraits<GemmConfig_, - GlobalLoadStreamA_, - GlobalLoadStreamB_, - SharedLoadStreamA_, - SharedLoadStreamB_, - Epilogue_, - BlockSwizzle_, - Index_, - ClearAccumulators_> - This_; - - /// The configuration. - typedef GemmConfig_ GemmConfig; - /// The output tile. - typedef typename GemmConfig::OutputTile OutputTile; - /// Is the residue treated in the prologue? - static bool const kResidueInPrologue = GemmConfig::kResidueInPrologue; - - /// The stream to load A from global memory to shared memory. - typedef GlobalLoadStreamA_ GlobalLoadStreamA; - /// The layout of A. - static MatrixLayout::Kind const kLayoutA = GlobalLoadStreamA::kLayout; - /// The scalar for A. - typedef typename GlobalLoadStreamA_::Scalar ScalarA; - - /// The stream to load B from global memory to shared memory. - typedef GlobalLoadStreamB_ GlobalLoadStreamB; - /// The layout of B. - static MatrixLayout::Kind const kLayoutB = GlobalLoadStreamB::kLayout; - /// The scalar for B. - typedef typename GlobalLoadStreamB_::Scalar ScalarB; - - /// The iterator for A to load from shared memory. - typedef SharedLoadStreamA_ SharedLoadStreamA; - /// The iterator for B to load from shared memory. - typedef SharedLoadStreamB_ SharedLoadStreamB; - - /// The multiply-add functor. - typedef typename GemmConfig::MultiplyAdd MultiplyAdd; - /// The epilogue. - typedef Epilogue_ Epilogue; - /// The scalars in the epilogue. - typedef typename Epilogue::ScalarC ScalarC; - typedef typename Epilogue::ScalarD ScalarD; - - /// The block swizzle to reorganize the grid. - typedef BlockSwizzle_ BlockSwizzle; - /// The index. - typedef Index_ Index; - /// Clear the accumulators. - typedef ClearAccumulators_ ClearAccumulators; - - /// The params. - struct Params { - /// The dimensions of the GEMM. - Index m, n, k; - /// The params for the A stream. - typename GlobalLoadStreamA::Params global_stream_a; - /// The params for the B stream. - typename GlobalLoadStreamB::Params global_stream_b; - /// The params for the A stream from shared memory. - typename SharedLoadStreamA::Params shared_stream_a; - /// The params for the B stream from shared memory. - typename SharedLoadStreamB::Params shared_stream_b; - /// The params for the epilogue. - typename Epilogue::Params epilogue; - - /// Initialize the parameters. - template <typename GemmDesc_> - CUTLASS_HOST_DEVICE int initialize(GemmDesc_ const& desc) { - // Set the problem size. - this->m = desc.m; - this->n = desc.n; - this->k = desc.k; - - // Initialize the iterator for A. - int error_code = - global_stream_a.initialize(desc, reinterpret_cast<ScalarA const*>(desc.d_a), desc.lda); - - if (error_code) { - return error_code; - } - - // Initialize the iterator for B. - error_code = - global_stream_b.initialize(desc, reinterpret_cast<ScalarB const*>(desc.d_b), desc.ldb); - - if (error_code) { - return error_code; - } - - // The epilogue. - return epilogue.initialize(desc); - } - }; - - // The storage for A. - template <typename GlobalLoadStream_, typename SharedLoadStream_> - union StreamSharedStorage { - // The storage needed by the global stream. - typename GlobalLoadStream_::SharedStorage global; - // The storage needed by the shared stream. - typename SharedLoadStream_::SharedStorage shared; - }; - - // The storage for the main loop + prologue. - struct MainLoopSharedStorage { - // The storage to shuffle the A matrix in shared memory. - StreamSharedStorage<GlobalLoadStreamA, SharedLoadStreamA> stream_a; - // The storage to shuffle the B matrix in shared memory. - StreamSharedStorage<GlobalLoadStreamB, SharedLoadStreamB> stream_b; - // The storage to clear the accumulators if needed. - typename ClearAccumulators::SharedStorage clear; - }; - - /// The storage in shared memory. - union SharedStorage { - // The storage for the main loop. - MainLoopSharedStorage main_loop; - // The storage for the epilogue. - typename Epilogue::SharedStorage epilogue; - }; - - /// Assemble the global load streams for A/B. - struct GlobalLoadStream { - /// Ctor. - CUTLASS_DEVICE GlobalLoadStream(Params const& params, - SharedStorage& shared_storage, - dim3 const& block) - : stream_a(params.global_stream_a, - shared_storage.main_loop.stream_a.global, - cutlass::make_Coord(0, params.k, params.m), - cutlass::make_Coord(0, 0, block.x)), - stream_b(params.global_stream_b, - shared_storage.main_loop.stream_b.global, - cutlass::make_Coord(0, params.k, params.n), - make_Coord(0, 0, block.y)) {} - - /// Trigger the copies from shared memory to registers. - CUTLASS_DEVICE void copy() { - stream_a.copy(); - stream_b.copy(); - } - - /// Commit the data. - CUTLASS_DEVICE void commit() { - stream_a.commit(); - stream_b.commit(); - } - - /// Move to residue portion. - template <bool kIsPrologue> - CUTLASS_DEVICE void move_to_residue(Index k) { - GemmResidue<This_>::move_to_residue<kIsPrologue>(stream_a, stream_b, k); - } - - /// Rollback to beginning of first tile and initialize predicates. - CUTLASS_DEVICE void rollback() { GemmResidue<This_>::rollback(stream_a, stream_b); } - - /// The stream for A. - GlobalLoadStreamA stream_a; - /// The stream for B. - GlobalLoadStreamB stream_b; - }; - - /// Assemble the shared load stream for A/B. - struct SharedLoadStream { - /// Ctor. - CUTLASS_DEVICE SharedLoadStream(Params const& params, SharedStorage& shared_storage) { - stream_a.initialize(params.shared_stream_a, shared_storage.main_loop.stream_a.shared); - stream_b.initialize(params.shared_stream_b, shared_storage.main_loop.stream_b.shared); - } - - /// Trigger the copies from shared memory to registers. - CUTLASS_DEVICE void copy(int step) { - stream_a.copy(step, fetched_a[step % 2]); - stream_b.copy(step, fetched_b[step % 2]); - } - - /// Commit the data. - CUTLASS_DEVICE void commit(int step) { - stream_a.commit(fetched_a[step % 2], transformed_a[step % 2]); - stream_b.commit(fetched_b[step % 2], transformed_b[step % 2]); - } - - /// The fragment A. - CUTLASS_DEVICE typename SharedLoadStreamA::Fragment const& fragment_a(int step) const { - return transformed_a[step % 2]; - } - - /// The fragment B. - CUTLASS_DEVICE typename SharedLoadStreamB::Fragment const& fragment_b(int step) const { - return transformed_b[step % 2]; - } - - /// Increment the stage. - CUTLASS_DEVICE void inc_stage() { - stream_a.inc_stage(); - stream_b.inc_stage(); - } - - /// The stream for A. - SharedLoadStreamA stream_a; - /// The fragments to fetch A. - typename SharedLoadStreamA::FetchedFragment fetched_a[2]; - /// The fragments to transform A. - typename SharedLoadStreamA::TransformedFragment transformed_a[2]; - /// The stream for B. - SharedLoadStreamB stream_b; - /// The fragments to fetch B. - typename SharedLoadStreamB::FetchedFragment fetched_b[2]; - /// The fragments to transform B. - typename SharedLoadStreamB::TransformedFragment transformed_b[2]; - }; - - /// The memory fence for shared loads. - static CUTLASS_DEVICE void shared_load_fence(bool in_loop) { - if (SharedLoadStreamA::Iterator::kRequiresLoadFence || - SharedLoadStreamB::Iterator::kRequiresLoadFence) { - __syncthreads(); - } - } - - /// The memory fence for shared stores. - static CUTLASS_DEVICE void shared_store_fence(bool in_loop) { __syncthreads(); } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmTileTraitsHelperA_, typename GemmTileTraitsHelperB_, typename Index_> -struct SimplifiedGemmTraitsHelper { - /// The global iterator to load A from global memory. - typedef GemmGlobalIteratorAb<typename GemmTileTraitsHelperA_::GlobalTileTraits, Index_> - GlobalLoadIteratorA; - /// The data converter for A before storing to shared memory. - typedef Copy<typename GlobalLoadIteratorA::Fragment> GlobalTransformerA; - /// The iterator to store A to shared memory. - typedef TileStoreIterator<typename GemmTileTraitsHelperA_::SharedStoreTileTraits, - typename GemmTileTraitsHelperA_::SharedStoreTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedStoreIteratorA; - /// The stream to load A from global memory to shared memory. - typedef GlobalLoadStream<GlobalLoadIteratorA, SharedStoreIteratorA, GlobalTransformerA> - GlobalLoadStreamA; - - /// The global iterator to load B from global memory. - typedef GemmGlobalIteratorAb<typename GemmTileTraitsHelperB_::GlobalTileTraits, Index_> - GlobalLoadIteratorB; - /// The data converter for B before storing to shared memory. - typedef Copy<typename GlobalLoadIteratorB::Fragment> GlobalTransformerB; - /// The iterator to store B to shared memory. - typedef TileStoreIterator<typename GemmTileTraitsHelperB_::SharedStoreTileTraits, - typename GemmTileTraitsHelperB_::SharedStoreTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedStoreIteratorB; - /// The stream to load B from global memory to shared memory. - typedef GlobalLoadStream<GlobalLoadIteratorB, SharedStoreIteratorB, GlobalTransformerB> - GlobalLoadStreamB; - - /// The iterator to load A from shared memory. - typedef TileLoadIterator<typename GemmTileTraitsHelperA_::SharedLoadTileTraits, - typename GemmTileTraitsHelperA_::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedLoadIteratorA; - /// The stream to load A from shared memory. - typedef SharedLoadStream<SharedLoadIteratorA> SharedLoadStreamA; - /// The iterator to load B from shared memory. - typedef TileLoadIterator<typename GemmTileTraitsHelperB_::SharedLoadTileTraits, - typename GemmTileTraitsHelperB_::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedLoadIteratorB; - /// The stream to load B from shared memory. - typedef SharedLoadStream<SharedLoadIteratorB> SharedLoadStreamB; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The layout for A. - MatrixLayout::Kind kLayoutA_, - /// The layout for B. - MatrixLayout::Kind kLayoutB_, - /// The config for the GEMM. - typename GemmConfig_, - /// The epilogue. - typename Epilogue_, - /// The index. - typename Index_ = int, - // The configuration for the A matrix. - typename GemmTileTraitsHelperA_ = GemmTileTraitsHelperA<kLayoutA_, GemmConfig_>, - // The configuration for the B matrix. - typename GemmTileTraitsHelperB_ = GemmTileTraitsHelperB<kLayoutB_, GemmConfig_>, - // The helper class to create the streams and iterators. - typename Helper_ = - SimplifiedGemmTraitsHelper<GemmTileTraitsHelperA_, GemmTileTraitsHelperB_, Index_> > -struct SimplifiedGemmTraits : public GemmTraits< - // The config. - GemmConfig_, - // The stream to load A from global memory to shared memory. - typename Helper_::GlobalLoadStreamA, - // The stream to load B from global memory to shared memory. - typename Helper_::GlobalLoadStreamB, - // The stream to load A from shared memory. - typename Helper_::SharedLoadStreamA, - // The stream to load B from shared memory. - typename Helper_::SharedLoadStreamB, - // The epilogue. - Epilogue_, - // The block swizzle to reorganize the grid. - IdentityBlockSwizzle, - // The index. - Index_, - // The tool used to clear accumulators. - ClearAccumulators<typename GemmConfig_::Accumulators::Element> > { -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/hgemm_global_tile.h b/cutlass-example/cutlass/gemm/hgemm_global_tile.h deleted file mode 100644 index f14dbb3..0000000 --- a/cutlass-example/cutlass/gemm/hgemm_global_tile.h +++ /dev/null @@ -1,90 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Tile traits used to construct global tile iterator for HGEMM. This is intended to - partition the thread block-level tile into 2D subtiles loaded by the threads and facilitate - memory accesses larger than 16 bits. -*/ -#pragma once - -#include <cutlass/coord.h> -#include <cutlass/gemm/gemm_global_tile.h> -#include <cutlass/matrix_traits.h> -#include <cutlass/reshape_tile.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <GemmOperand::Kind kOperand_, - MatrixLayout::Kind kLayout_, - typename Scalar_, - typename Tile_, - typename Threads_, - int kAccessSize_> -struct HgemmCrosswiseGlobalTileTraits : public GemmGlobalTileTraits< - // Which GEMM operand? - kOperand_, - // The layout. - kLayout_, - // The scalar. - Scalar_, - // The tile. - Tile_, - // The threads. - Threads_, - // The number of scalars per LDG/STG. - kAccessSize_> { - /// The base class. - typedef GemmGlobalTileTraits<kOperand_, kLayout_, Scalar_, Tile_, Threads_, kAccessSize_> Base; - /// The threads. - typedef typename Base::Threads Threads; - /// The threads strides. - typedef Shape<1, 2, Base::Tile::kC> ThreadsDelta; - /// The strides in each dimension between different loads/stores. - typedef Shape<Base::Threads::kH * 2, 1, Base::Threads::kW, Base::kAccessSize> Delta; - /// The number of iterations needed to load/store the tile. - typedef Shape<Base::Tile::kH / Base::Threads::kH / 2, - 2, - Base::Tile::kW / Base::Threads::kW, - Base::Tile::kC / Base::kAccessSize> - Iterations; - /// Computes the thread offset in (H, W) based on thread ID - struct ThreadOffset { - CUTLASS_HOST_DEVICE - Coord<4> operator()() const { - int thread_offset_h = threadIdx.x / Threads::kW * ThreadsDelta::kH; - int thread_offset_w = threadIdx.x % Threads::kW * ThreadsDelta::kW; - - return make_Coord(0, thread_offset_h, thread_offset_w, 0); - } - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/hgemm_multiply_add.h b/cutlass-example/cutlass/gemm/hgemm_multiply_add.h deleted file mode 100644 index ebbdd06..0000000 --- a/cutlass-example/cutlass/gemm/hgemm_multiply_add.h +++ /dev/null @@ -1,104 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Specialization implementing multiply-add operation on half-precision floating point - fragments. -*/ -#pragma once - -#include <cutlass/fragment.h> - -#include <cutlass/gemm/thread_multiply_add.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Template performing matrix multiply-add operation within a thread -template <typename AccumulatorsPerThread_, typename ThreadsPerWarp_> -struct ThreadMultiplyAdd<AccumulatorsPerThread_, ThreadsPerWarp_, half, half, half> { - /// The shape of the instruction. - typedef Shape<1, 1, 2, 1> InstructionShape; - /// The number of accumulators per thread. - typedef AccumulatorsPerThread_ AccumulatorsPerThread; - /// The number of threads per warp. - typedef ThreadsPerWarp_ ThreadsPerWarp; - /// The number of accumulators per warp. - typedef typename ShapeMul<AccumulatorsPerThread, ThreadsPerWarp>::Shape AccumulatorsPerWarp; - /// The type for A. - typedef half ScalarA; - /// The fragment for A. - typedef Fragment<ScalarA, AccumulatorsPerThread::kW> FragmentA; - /// The type for B. - typedef half ScalarB; - /// The fragment for B. - typedef Fragment<ScalarB, AccumulatorsPerThread::kH> FragmentB; - /// The type for C and D. - typedef half ScalarC; - /// The accumulators. - typedef Fragment<half, AccumulatorsPerThread::kH * AccumulatorsPerThread::kW> Accumulators; - - /// Make sure there's an even number of elements in both dimensions. - static_assert(AccumulatorsPerThread::kH % 2 == 0, "Invalid size"); - static_assert(AccumulatorsPerThread::kW % 2 == 0, "Invalid size"); - - /// Ctor. - CUTLASS_DEVICE ThreadMultiplyAdd() {} - - /// Multiply : d = a*b + c. - CUTLASS_DEVICE void multiply_add(FragmentA const& a, - FragmentB const& b, - Accumulators const& c, - Accumulators& d) { -#if defined(__CUDACC__) && __CUDA_ARCH__ >= 530 - // The inputs. - __half2 const* a_half2 = reinterpret_cast<__half2 const*>(&a[0]); - __half2 const* b_half2 = reinterpret_cast<__half2 const*>(&b[0]); - __half2 const* c_half2 = reinterpret_cast<__half2 const*>(&c[0]); - - // The output. - __half2* d_half2 = reinterpret_cast<__half2*>(&d[0]); - - for (int j = 0; j < AccumulatorsPerThread::kH / 2; ++j) { - for (int i = 0; i < AccumulatorsPerThread::kW / 2; ++i) { - // The offsets in the output fragment. - int const k0 = (2 * j + 0) * (AccumulatorsPerThread::kW / 2) + i; - int const k1 = (2 * j + 1) * (AccumulatorsPerThread::kW / 2) + i; - - // Compute the product a[i] * b[j].H0_H0. - d_half2[k0] = __hfma2(a_half2[i], __low2half2(b_half2[j]), c_half2[k0]); - // Compute the product a[i] * b[j].H1_H1. - d_half2[k1] = __hfma2(a_half2[i], __high2half2(b_half2[j]), c_half2[k1]); - } - } -#endif - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/hgemm_swizzle.h b/cutlass-example/cutlass/gemm/hgemm_swizzle.h deleted file mode 100644 index ebec0d4..0000000 --- a/cutlass-example/cutlass/gemm/hgemm_swizzle.h +++ /dev/null @@ -1,94 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Transposes a tile of 16b elements. Used by HGEMM to construct a K-strided layout in - shared memory for multiplicands. -*/ -#pragma once - -#include <cuda_fp16.h> -#include <cutlass/fragment.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GlobalIterator_> -struct HgemmSwizzle { - /// The global iterator. - typedef GlobalIterator_ GlobalIterator; - /// The source fragment. - typedef typename GlobalIterator::Fragment Fragment; - /// The shape of the source fragment. - typedef typename GlobalIterator::FragmentShape FragmentShape; - - /// The input fragment. - typedef Fragment InputFragment; - /// The output fragment. - typedef Fragment OutputFragment; - - /// The src/dst must be half fragments. - static_assert((platform::is_same<typename Fragment::Element, half>::value), "Works on half"); - - /// The number of elements must be a multiple of 2. - static_assert(FragmentShape::kH == 2 && ShapeCount<FragmentShape>::kWc == 2, "Not multiple of 2"); - - /// Ctor. - CUTLASS_DEVICE HgemmSwizzle() {} - - /// Transform a fragment. - CUTLASS_DEVICE void transform(Fragment const& src, Fragment& dst) { - // Expose src/dst as int arrays. - int const* src_int = reinterpret_cast<int const*>(&src[0]); - int* dst_int = reinterpret_cast<int*>(&dst[0]); - - // Transpose the data. - for (int d = 0; d < FragmentShape::kD; ++d) { - // The indices to read two consecutive "rows". - int const i0 = 2 * d + 0; - int const i1 = 2 * d + 1; - - int a0 = src_int[i0]; - int a1 = src_int[i1]; - - int b0, b1; - asm volatile("prmt.b32 %0, %1, %2, 0x5410;" : "=r"(b0) : "r"(a0), "r"(a1)); - asm volatile("prmt.b32 %0, %1, %2, 0x7632;" : "=r"(b1) : "r"(a0), "r"(a1)); - - // The indices to store with "strides". - int const j0 = 0 * (ShapeCount<FragmentShape>::kDhw / 2) + d; - int const j1 = 1 * (ShapeCount<FragmentShape>::kDhw / 2) + d; - - dst_int[j0] = b0; - dst_int[j1] = b1; - } - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/hgemm_traits.h b/cutlass-example/cutlass/gemm/hgemm_traits.h deleted file mode 100644 index b08645b..0000000 --- a/cutlass-example/cutlass/gemm/hgemm_traits.h +++ /dev/null @@ -1,397 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defies structural properties of half-precision GEMM computation. -*/ -#pragma once - -#include <cutlass/convert.h> -#include <cutlass/reshape_tile.h> - -#include <cutlass/gemm/gemm.h> -#include <cutlass/gemm/gemm_epilogue.h> -#include <cutlass/gemm/gemm_epilogue_traits.h> -#include <cutlass/gemm/gemm_global_tile.h> -#include <cutlass/gemm/gemm_shared_tile.h> -#include <cutlass/gemm/gemm_traits.h> -#include <cutlass/gemm/hgemm_global_tile.h> -#include <cutlass/gemm/hgemm_multiply_add.h> -#include <cutlass/gemm/hgemm_swizzle.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The tile size for the GEMM KxNxM. - typename OutputTile_, - /// The number of accumulators per thread. - typename AccumulatorsPerThread_, - /// The number of scalars per LDG for A. - int kScalarsPerLdgA_ = 2, - /// The number of scalars per LDG for B. - int kScalarsPerLdgB_ = 2> -struct HgemmConfig - : public GemmConfig< - /// The scalar type for A. - half, - /// The scalar type for B. - half, - /// The scalar type for C. - half, - /// The scalar type for D. - half, - /// The tile size for the GEMM KxNxM. - OutputTile_, - /// The functor to do the math in the main loop. - ThreadMultiplyAdd<AccumulatorsPerThread_, Shape<1, 4, 8>, half, half, half>, - /// The number of scalars per LDG for A. - kScalarsPerLdgA_, - /// The number of scalars per STS for A. - kScalarsPerLdgA_, - /// The number of scalars per LDS for A. - 8, - /// The number of scalars per LDG for B. - kScalarsPerLdgB_, - /// The number of scalars per STS for B. - kScalarsPerLdgB_, - /// The number of scalars per LDS for B. - 8, - /// The number of scalars per LDG for C and STG for D. - 2, - /// The number of scalars per STS for D. - 8, - /// The number of scalars per LDS for D. - 2, - /// The number of stages in shared memory. - 2> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <enum MatrixLayout::Kind kLayout_, typename Iterator_> -struct HgemmTransformerA {}; - -template <typename Iterator_> -struct HgemmTransformerA<MatrixLayout::kColumnMajor, Iterator_> { - typedef Convert<typename Iterator_::Fragment, typename Iterator_::Fragment> Transformer; -}; - -template <typename Iterator_> -struct HgemmTransformerA<MatrixLayout::kRowMajor, Iterator_> { - typedef HgemmSwizzle<Iterator_> Transformer; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <enum MatrixLayout::Kind kLayout_, typename Iterator_> -struct HgemmTransformerB {}; - -template <typename Iterator_> -struct HgemmTransformerB<MatrixLayout::kRowMajor, Iterator_> { - typedef Convert<typename Iterator_::Fragment, typename Iterator_::Fragment> Transformer; -}; - -template <typename Iterator_> -struct HgemmTransformerB<MatrixLayout::kColumnMajor, Iterator_> { - typedef HgemmSwizzle<Iterator_> Transformer; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <enum MatrixLayout::Kind kLayout_, typename GemmConfig_> -struct HgemmTileTraitsHelperA : public GemmTileTraitsHelperA<kLayout_, GemmConfig_> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_> -struct HgemmTileTraitsHelperA<MatrixLayout::kRowMajor, GemmConfig_> - : public GemmTileTraitsHelperA<MatrixLayout::kRowMajor, GemmConfig_> { - /// The base config. - typedef GemmTileTraitsHelperA<MatrixLayout::kRowMajor, GemmConfig_> Base; - - /// The traits class to build the iterator to load data from global memory for A^T. - typedef HgemmCrosswiseGlobalTileTraits< - GemmOperand::kA, - // The layout. - MatrixLayout::kRowMajor, - // The pointer. - half const, - // The tile has size MxK in GEMM's terminology. - Shape<1, GemmConfig_::OutputTile::kW, GemmConfig_::OutputTile::kD>, - // The threads are distributed as (threads / K ) x K (the traits may reorganize). - Shape<1, GemmConfig_::kThreads / GemmConfig_::OutputTile::kD, GemmConfig_::OutputTile::kD>, - // The number of scalars per LDG (LDG.32 or LDG.128, etc) - GemmConfig_::kScalarsPerLdgA> - GlobalTileTraits; - - /// The skew. - static int const kSkewA = 128 / sizeof(half) / GlobalTileTraits::Threads::kW / 2; - - /// The traits class to build the iterator to store data to shared memory for A^T. - typedef GemmSharedStoreWithSkewTileAbTraits < - // The pointer. - half, - // The tile has size KxM in GEMM's terminology. - Shape<GemmConfig_::kStages, - GemmConfig_::OutputTile::kD / GemmConfig_::InstructionShape::kD, - GemmConfig_::OutputTile::kW * GemmConfig_::InstructionShape::kD>, - // The threads are distributed as warps x 32(the traits may reorganize). - typename GlobalTileTraits::Threads, - // The number of scalars per STS (STS.32 or STS.128, etc). - 2, - // The skew to avoid bank conflicts added in the tile W dimension. - kSkewA<GemmConfig_::kScalarsPerLdsA ? GemmConfig_::kScalarsPerLdsA : kSkewA> - SharedStoreTileTraits; - - /// The traits class to build the iterator to load from shared memory for A^T. - typedef GemmSharedLoadTileATraits< - // The pointer. - half const, - // The output tile size. - typename GemmConfig_::OutputTile, - // The number of warps. - typename GemmConfig_::Warps, - // The number of threads per warp. - typename GemmConfig_::MultiplyAdd::ThreadsPerWarp, - // The shape of the FMA instruction. - typename GemmConfig_::InstructionShape, - // The number of stages. - GemmConfig_::kStages, - // The number of scalars per LDS. - 8, - // The skew. - SharedStoreTileTraits::kSkew> - SharedLoadTileTraits; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <enum MatrixLayout::Kind kLayout_, typename GemmConfig_> -struct HgemmTileTraitsHelperB : public GemmTileTraitsHelperB<kLayout_, GemmConfig_> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_> -struct HgemmTileTraitsHelperB<MatrixLayout::kColumnMajor, GemmConfig_> - : public GemmTileTraitsHelperB<MatrixLayout::kColumnMajor, GemmConfig_> { - /// The base config. - typedef GemmTileTraitsHelperB<MatrixLayout::kColumnMajor, GemmConfig_> Base; - - /// The traits class to build the iterator to load data from global memory for B^N. - typedef HgemmCrosswiseGlobalTileTraits< - GemmOperand::kB, - // The layout. - MatrixLayout::kColumnMajor, - // The pointer. - half const, - // The tile has size KxN in GEMM's terminology. - Shape<1, GemmConfig_::OutputTile::kH, GemmConfig_::OutputTile::kD>, - // The threads are distributed as (threads / K) x K (the traits may reorganize). - Shape<1, GemmConfig_::kThreads / GemmConfig_::OutputTile::kD, GemmConfig_::OutputTile::kD>, - // The number of scalars per LDG (LDG.32 or LDG.128, etc) - GemmConfig_::kScalarsPerLdgB> - GlobalTileTraits; - - /// The skew for B. - static int const kSkewB = 128 / sizeof(half) / GlobalTileTraits::Threads::kW / 2; - - /// The traits class to build the iterator to store data to shared memory for B^N. - typedef GemmSharedStoreWithSkewTileAbTraits < - // The pointer. - half, - // The tile has size KxN in GEMM's terminology. - Shape<GemmConfig_::kStages, - GemmConfig_::OutputTile::kD / GemmConfig_::InstructionShape::kD, - GemmConfig_::OutputTile::kH * GemmConfig_::InstructionShape::kD>, - // The threads are distributed as (threads / K) x K (the traits may reorganize). - typename GlobalTileTraits::Threads, - // The number of scalars per STS (STS.32 or STS.128, etc). - 2, - // The skew to avoid bank conflicts added in the tile W dimension. - kSkewB<GemmConfig_::kScalarsPerLdsB ? GemmConfig_::kScalarsPerLdsB : kSkewB> - SharedStoreTileTraits; - - /// The traits class to build the iterator to load from shared memory for B^N. - typedef GemmSharedLoadTileBTraits< - // The pointer. - half const, - // The output tile size. - typename GemmConfig_::OutputTile, - // The number of warps. - typename GemmConfig_::Warps, - // The number of threads per warp. - typename GemmConfig_::MultiplyAdd::ThreadsPerWarp, - // The shape of the FMA instruction. - typename GemmConfig_::InstructionShape, - // The number of stages. - GemmConfig_::kStages, - // The number of scalars per LDS. - 8, - // The skew. - SharedStoreTileTraits::kSkew> - SharedLoadTileTraits; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The layout for A. - MatrixLayout::Kind kLayoutA_, - /// The layout for B. - MatrixLayout::Kind kLayoutB_, - /// The output tile. - typename OutputTile_, - /// The functor to do the math in the epilogue. - typename EpilogueFunctor_, - /// The number of accumulators per thread. - typename AccumulatorsPerThread_ = Shape<8, 8, 16>, - /// The number of halfs loaded in one LDG for A. - int kScalarsPerLdgA_ = 2, - /// The number of halfs loaded in one LDG for B. - int kScalarsPerLdgB_ = 2, - /// The index. - typename Index_ = int> -struct HgemmTraitsHelper { - /// The HGEMM config. - typedef HgemmConfig<OutputTile_, AccumulatorsPerThread_, kScalarsPerLdgA_, kScalarsPerLdgB_> - GemmConfig; - /// The GEMM config for A. - typedef HgemmTileTraitsHelperA<kLayoutA_, GemmConfig> GemmTileTraitsHelperA; - /// The GEMM config for B. - typedef HgemmTileTraitsHelperB<kLayoutB_, GemmConfig> GemmTileTraitsHelperB; - - /// The iterator to load A from global memory. - typedef GemmGlobalIteratorAb<typename GemmTileTraitsHelperA::GlobalTileTraits, Index_> - GlobalLoadIteratorA; - /// The default transformer for A. - typedef typename HgemmTransformerA<GemmTileTraitsHelperA::kLayout, - GlobalLoadIteratorA>::Transformer GlobalTransformerA; - /// The iterator to store A to shared memory. - typedef TileStoreIterator<typename GemmTileTraitsHelperA::SharedStoreTileTraits, - typename GemmTileTraitsHelperA::SharedStoreTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedStoreIteratorA; - /// The stream to load A from global memory to shared memory. - typedef GlobalLoadStream<GlobalLoadIteratorA, SharedStoreIteratorA, GlobalTransformerA> - GlobalLoadStreamA; - - /// The iterator to load B from global memory. - typedef GemmGlobalIteratorAb<typename GemmTileTraitsHelperB::GlobalTileTraits, Index_> - GlobalLoadIteratorB; - // The default transformer for B. - typedef typename HgemmTransformerB<GemmTileTraitsHelperB::kLayout, - GlobalLoadIteratorB>::Transformer GlobalTransformerB; - /// The iterator to store B to shared memory. - typedef TileStoreIterator<typename GemmTileTraitsHelperB::SharedStoreTileTraits, - typename GemmTileTraitsHelperB::SharedStoreTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedStoreIteratorB; - /// The stream to load B from global memory to shared memory. - typedef GlobalLoadStream<GlobalLoadIteratorB, SharedStoreIteratorB, GlobalTransformerB> - GlobalLoadStreamB; - - /// The iterator to load A from shared memory - typedef TileLoadIterator<typename GemmTileTraitsHelperA::SharedLoadTileTraits, - typename GemmTileTraitsHelperA::SharedLoadTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedLoadIteratorA; - /// The stream to load A from shared memory. - typedef SharedLoadStream<SharedLoadIteratorA> SharedLoadStreamA; - /// The iterator to load B from shared memory. - typedef TileLoadIterator<typename GemmTileTraitsHelperB::SharedLoadTileTraits, - typename GemmTileTraitsHelperB::SharedLoadTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedLoadIteratorB; - /// The stream to load B from shared memory. - typedef SharedLoadStream<SharedLoadIteratorB> SharedLoadStreamB; - - /// The functor to do the multiply-add in the main loop. - typedef typename GemmConfig::MultiplyAdd MultiplyAdd; - /// The object to clear accumulators. - typedef ClearAccumulators<typename MultiplyAdd::ScalarC> ClearAccumulators; - - /// The traits class for the epilogue. - typedef SimplifiedGemmEpilogueTraits<GemmConfig, EpilogueFunctor_, Index_> GemmEpilogueTraits; - /// The epilogue. - typedef GemmEpilogue<GemmEpilogueTraits> Epilogue; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The layout for A. - MatrixLayout::Kind kLayoutA_, - /// The layout for B. - MatrixLayout::Kind kLayoutB_, - /// The output tile. - typename OutputTile_ = Shape<8, 128, 128>, - /// The functor to do the math in the epilogue. - typename EpilogueFunctor_ = LinearScaling<half>, - /// The number of accumulators per thread. - typename AccumulatorsPerThread_ = Shape<8, 8, 16>, - /// The number of halfs loaded in one LDG for A. - int kScalarsPerLdgA_ = 2, - /// The number of halfs loaded in one LDG for B. - int kScalarsPerLdgB_ = 2, - /// The index. - typename Index_ = int, - /// The helper class. - typename Helper_ = HgemmTraitsHelper<kLayoutA_, - kLayoutB_, - OutputTile_, - EpilogueFunctor_, - AccumulatorsPerThread_, - kScalarsPerLdgA_, - kScalarsPerLdgB_, - Index_> > -struct HgemmTraits : public GemmTraits< - // The config. - typename Helper_::GemmConfig, - // The stream to load A from global memory to shared memory. - typename Helper_::GlobalLoadStreamA, - // The stream to load B from global memory to shared memory. - typename Helper_::GlobalLoadStreamB, - // The stream to load A from shared memory. - typename Helper_::SharedLoadStreamA, - // The stream to load B from shared memory. - typename Helper_::SharedLoadStreamB, - // The epilogue. - typename Helper_::Epilogue, - // The block swizzle to reorganize the grid. - IdentityBlockSwizzle, - // The index. - Index_, - // The tool used to clear accumulators. - typename Helper_::ClearAccumulators> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/identity_block_swizzle.h b/cutlass-example/cutlass/gemm/identity_block_swizzle.h deleted file mode 100644 index e1bdb2e..0000000 --- a/cutlass-example/cutlass/gemm/identity_block_swizzle.h +++ /dev/null @@ -1,48 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defies functors for mapping blockIdx to partitions of the GEMM computation. - - Currently, we only implement an identity mapping. -*/ -#pragma once - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -struct IdentityBlockSwizzle { - /// Ctor. - CUTLASS_DEVICE IdentityBlockSwizzle() {} - - /// Swizzle the block index. - CUTLASS_DEVICE dim3 swizzle() { return blockIdx; } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/igemm_epilogue.h b/cutlass-example/cutlass/gemm/igemm_epilogue.h deleted file mode 100644 index 0d69980..0000000 --- a/cutlass-example/cutlass/gemm/igemm_epilogue.h +++ /dev/null @@ -1,320 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines the epilogue phase of the GEMM computation for IGEMM, supporting integer and - floating-point output matrix formats. -*/ -#pragma once - -#include <cutlass/convert.h> -#include <cutlass/fragment.h> -#include <cutlass/gemm/gemm_global_stream.h> -#include <cutlass/gemm/gemm_shared_stream.h> -#include <cutlass/gemm/igemm_global_tile.h> -#include <cutlass/reshape_tile.h> -#include <cutlass/tile_iterator.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <int kElements_> -struct IgemmFloatToInt8Converter { - /// The input fragment. - typedef Fragment<float, kElements_> InputFragment; - /// The output fragment. - typedef Fragment<int8_t, kElements_> OutputFragment; - - // We are packing 4 floats into int32 registers so we need kElements to be multiple of 4. - static_assert(kElements_ % 4 == 0, "kElements must be multiple of 4"); - - /// Ctor. - CUTLASS_DEVICE IgemmFloatToInt8Converter() {} - - /// Transform a fragment. - CUTLASS_DEVICE void transform(InputFragment const& src, OutputFragment& dst) { - transform(src, 0, dst); - } - - /// Transform a fragment. - template <typename Fragment_> - CUTLASS_DEVICE void transform(Fragment_ const& src, int offset, OutputFragment& dst) { - // The inputs. - float4 const* src_f4 = reinterpret_cast<float4 const*>(&src[0]); - // The outputs. - int* dst_int = reinterpret_cast<int*>(&dst[0]); - - // Iterate over the floats and pack them together to produce ints. - for (int i = 0; i < kElements_ / 4; ++i) { - // Read the float4. - float4 f4 = src_f4[i]; - - // Clamp the 4 elements of the floats to the [-128, +127] range. - float x = fmaxf(-128.f, fminf(127.f, f4.x)); - float y = fmaxf(-128.f, fminf(127.f, f4.y)); - float z = fmaxf(-128.f, fminf(127.f, f4.z)); - float w = fmaxf(-128.f, fminf(127.f, f4.w)); - - // Convert to integers. - int ix = (int)x; - int iy = (int)y; - int iz = (int)z; - int iw = (int)w; - - // Extract the lower bytes to build an int32 with 4 int8. - asm volatile("prmt.b32 %0, %0, %1, 0x1140;" : "+r"(ix) : "r"(iy)); - asm volatile("prmt.b32 %0, %0, %1, 0x1140;" : "+r"(iz) : "r"(iw)); - asm volatile("prmt.b32 %0, %0, %1, 0x5410;" : "+r"(ix) : "r"(iz)); - - // Store the int. - dst_int[i] = ix; - } - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename InputScalar_, typename OutputFragment_> -struct IgemmGlobalStoreTransformer { - typedef Convert<Fragment<InputScalar_, OutputFragment_::kElements>, OutputFragment_> Transformer; -}; - -template <int kElements_> -struct IgemmGlobalStoreTransformer<float, Fragment<int8_t, kElements_> > { - typedef IgemmFloatToInt8Converter<kElements_> Transformer; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <int kElements_> -struct IgemmInt8ToFloatConverter { - /// The input fragment. - typedef Fragment<int8_t, kElements_> InputFragment; - /// The output fragment. - typedef Fragment<float, kElements_> OutputFragment; - - // We are unpacking 4 int8s from int32. - static_assert(kElements_ % 4 == 0, "kElements must be multiple of 4"); - - /// Ctor. - CUTLASS_DEVICE IgemmInt8ToFloatConverter() {} - - /// Transform a fragment. - CUTLASS_DEVICE void transform(InputFragment const& src, OutputFragment& dst) { - transform(src, 0, dst); - } - - /// Transform a fragment. - template <typename Fragment_> - CUTLASS_DEVICE void transform(Fragment_ const& src, int offset, OutputFragment& dst) { - // The inputs. - int const* src_int = reinterpret_cast<int const*>(&src[0]); - // The outputs. - float4* dst_f4 = reinterpret_cast<float4*>(&dst[0]); - - // Iterate over the int8 and unpack them together to produce floats. - for (int i = 0; i < kElements_ / 4; ++i) { - // Read the int. - int ix, iy, iz, iw = src_int[i]; - - // Extract the 4 bytes. - asm volatile("prmt.b32 %0, 0x0, %1, 0x4440;" : "=r"(ix) : "r"(iw)); - asm volatile("prmt.b32 %0, 0x0, %1, 0x4441;" : "=r"(iy) : "r"(iw)); - asm volatile("prmt.b32 %0, 0x0, %1, 0x4442;" : "=r"(iz) : "r"(iw)); - asm volatile("prmt.b32 %0, 0x0, %1, 0x4443;" : "=r"(iw) : "r"(iw)); - - // The floats. - float fx, fy, fz, fw; - - // Convert to floats (make sure we generate I2F.F32.S8). - asm volatile("cvt.rn.f32.s8 %0, %1;" : "=f"(fx) : "r"(ix)); - asm volatile("cvt.rn.f32.s8 %0, %1;" : "=f"(fy) : "r"(iy)); - asm volatile("cvt.rn.f32.s8 %0, %1;" : "=f"(fz) : "r"(iz)); - asm volatile("cvt.rn.f32.s8 %0, %1;" : "=f"(fw) : "r"(iw)); - - // Store the float4. - dst_f4[i] = make_float4(fx, fy, fz, fw); - } - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename InputFragment_, typename OutputScalar_> -struct IgemmGlobalLoadTransformer { - typedef Convert<InputFragment_, Fragment<OutputScalar_, InputFragment_::kElements> > Transformer; -}; - -template <int kElements_> -struct IgemmGlobalLoadTransformer<Fragment<int8_t, kElements_>, float> { - typedef IgemmInt8ToFloatConverter<kElements_> Transformer; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename InputScalar_, typename OutputFragment_> -struct IgemmSharedStoreTransformer { - typedef Convert<Fragment<InputScalar_, OutputFragment_::kElements>, OutputFragment_> Transformer; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename IgemmConfig_, typename EpilogueFunctor_, typename Index_> -struct IgemmEpilogueTraitsHelper - : public GemmEpilogueTraitsHelper<IgemmConfig_, EpilogueFunctor_, Index_> { - /// The base class. - typedef GemmEpilogueTraitsHelper<IgemmConfig_, EpilogueFunctor_, Index_> Base; - /// The config. - typedef IgemmConfig_ IgemmConfig; - - /// The scalar type of the epilogue. - typedef typename Base::Scalar Scalar; - /// The iterations. - typedef typename Base::Iterations Iterations; - /// The iterations strides. - typedef typename Base::Delta Delta; - - /// The traits class for the iterator. - typedef typename Base::GlobalLoadTileTraits GlobalLoadTileTraits; - /// The iterator to store to shared memory. - typedef GemmGlobalIteratorCd<GlobalLoadTileTraits> GlobalLoadIteratorC; - /// The fragment that needs to be produced by the load iterator. - typedef typename GlobalLoadIteratorC::Fragment GlobalFragmentC; - /// The transformer from loaded data to math fragment. - typedef - typename IgemmGlobalLoadTransformer<GlobalFragmentC, Scalar>::Transformer GlobalTransformerC; - - /// The traits class for the iterator. - typedef typename Base::GlobalStoreTileTraits GlobalStoreTileTraits; - /// The iterator to store to shared memory. - typedef GemmGlobalIteratorCd<GlobalStoreTileTraits> GlobalStoreIteratorD; - /// The fragment that needs to be passed to that store iterator. - typedef typename GlobalStoreIteratorD::Fragment GlobalFragmentD; - /// The transformer from accumulators to shared memory fragments. - typedef - typename IgemmGlobalStoreTransformer<Scalar, GlobalFragmentD>::Transformer GlobalTransformerD; - - /// The traits class for the shared iterator to store D to shared memory. - typedef typename Base::SharedStoreTileTraits SharedStoreTileTraits; - /// The shared iterator to store D to shared memory. - typedef TileStoreIterator<SharedStoreTileTraits, - typename SharedStoreTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kGlobal> - SharedStoreIteratorD; - /// The fragment that needs to be passed to that store iterator. - typedef typename SharedStoreIteratorD::Fragment SharedStoreFragmentD; - /// The transformer from accumulators to shared memory fragments. - typedef typename IgemmSharedStoreTransformer<typename IgemmConfig::Accumulators::Element, - SharedStoreFragmentD>::Transformer - SharedStoreTransformerD; - /// The traits class for the shared iterator to load D from shared memory. - typedef typename Base::SharedLoadTileTraits SharedLoadTileTraits; - /// The shared iterator to load D from shared memory. - typedef TileLoadIterator<SharedLoadTileTraits, - typename SharedLoadTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedLoadIteratorD; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The config. - typename IgemmConfig_, - /// The functor to do the math in the epilogue. - typename EpilogueFunctor_, - /// The index. - typename Index_ = int, - /// The helper class to assemble the traits. - typename Helper_ = IgemmEpilogueTraitsHelper<IgemmConfig_, EpilogueFunctor_, Index_> > -struct IgemmEpilogueTraits : public GemmEpilogueTraits< - // The output tile. - typename IgemmConfig_::OutputTile, - // The accumulators. - typename IgemmConfig_::Accumulators, - // The global iterator for C. - typename Helper_::GlobalLoadIteratorC, - // The transformer for C. - typename Helper_::GlobalTransformerC, - // The transformer for D. - typename Helper_::GlobalTransformerD, - // The global iterator for D. - typename Helper_::GlobalStoreIteratorD, - // The iterator to store D to shared memory. - typename Helper_::SharedStoreIteratorD, - // The shared store transformer for D. - typename Helper_::SharedStoreTransformerD, - // The iterator to load D from shared memory. - typename Helper_::SharedLoadIteratorD, - // The iterations. - typename Helper_::Iterations, - // The strides between iterations. - typename Helper_::Delta, - // The functor to be used in the epilogue. - EpilogueFunctor_, - // The index. - Index_> { - /// Do we output in int8? - static bool const kInt8Output = - platform::is_same<typename IgemmConfig_::ScalarC, int8_t>::value != 0; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmEpilogueTraits_, bool = GemmEpilogueTraits_::kInt8Output> -struct IgemmEpilogue : public GemmEpilogue<GemmEpilogueTraits_> { - /// The base class. - typedef GemmEpilogue<GemmEpilogueTraits_> Base; - - /// Ctor. - CUTLASS_DEVICE IgemmEpilogue(typename Base::Params const& params_, - typename Base::SharedStorage& shared_storage_, - typename Base::Index m_, - typename Base::Index n_) - : Base(params_, shared_storage_, m_, n_) {} -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmEpilogueTraits_> -struct IgemmEpilogue<GemmEpilogueTraits_, true> : public GemmEpilogue<GemmEpilogueTraits_> { - /// The base class. - typedef GemmEpilogue<GemmEpilogueTraits_> Base; - - /// Ctor. - CUTLASS_DEVICE IgemmEpilogue(typename Base::Params const& params_, - typename Base::SharedStorage& shared_storage_, - typename Base::Index m_, - typename Base::Index n_) - : Base(params_, shared_storage_, m_, n_) {} -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/igemm_global_tile.h b/cutlass-example/cutlass/gemm/igemm_global_tile.h deleted file mode 100644 index 3f594ac..0000000 --- a/cutlass-example/cutlass/gemm/igemm_global_tile.h +++ /dev/null @@ -1,161 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Implements tile iterators to partition the thread block tile into 2D subtiles and - efficiently load each. Applies permute transformation to construct 'interleaved K-strided' - data layout in which 4-element dot products from the same K index are arranged in consecutive - locations within shared memory. - - Supports efficient loads from shared memory to target the DP4A instruction. -*/ -#pragma once - -#include <cutlass/coord.h> -#include <cutlass/gemm/gemm_global_tile.h> -#include <cutlass/matrix_traits.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <GemmOperand::Kind kOperand_, - MatrixLayout::Kind kLayout_, - typename Scalar_, - typename Tile_, - typename Threads_, - int kAccessSize_> -struct IgemmGlobalTileTraits : public GemmGlobalTileTraits< - // Which GEMM operand? - kOperand_, - // The layout. - kLayout_, - // The scalar. - Scalar_, - // The tile. - Tile_, - // The threads. - Threads_, - // The number of scalars per LDG/STG. - kAccessSize_> { - /// The base class. - typedef GemmGlobalTileTraits<kOperand_, kLayout_, Scalar_, Tile_, Threads_, kAccessSize_> Base; - /// The threads. - typedef typename Base::Threads Threads; - /// The strides in each dimension between different loads/stores. - typedef Shape<Base::Threads::kH * 4, 1, Base::Threads::kW, Base::kAccessSize> Delta; - /// The number of iterations needed to load/store the tile. - typedef Shape<Base::Tile::kH / Base::Threads::kH / 4, - 4, - Base::Tile::kW / Base::Threads::kW, - Base::Tile::kC / Base::kAccessSize> - Iterations; - - /// Computes the thread offset in (H, W) based on thread ID - struct ThreadOffset { - CUTLASS_HOST_DEVICE - Coord<4> operator()() const { - int thread_offset_h = threadIdx.x / Threads::kW * ThreadsDelta::kH; - int thread_offset_w = threadIdx.x % Threads::kW * ThreadsDelta::kW; - - return make_Coord(0, thread_offset_h, thread_offset_w, 0); - } - }; - - public: - /// The threads strides. - typedef Shape<1, 4, Base::Tile::kC> ThreadsDelta; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Deprecated. Please use IgemmGlobalTileTraits instead. - -template <GemmOperand::Kind kOperand_, - MatrixLayout::Kind kLayout_, - typename Scalar_, - typename Tile_, - typename Threads_, - int kAccessSize_> -struct IgemmContiguousGlobalTileTraits - : public IgemmGlobalTileTraits<kOperand_, kLayout_, Scalar_, Tile_, Threads_, kAccessSize_> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename TileTraits_, typename Index_ = int> -struct IgemmGlobalIteratorAb : public GemmGlobalIteratorAb<TileTraits_, Index_> { - /// The base class. - typedef GemmGlobalIteratorAb<TileTraits_, Index_> Base; - /// The functor to compute the thread offset. - typedef typename TileTraits_::ThreadOffset ThreadOffset; - - /// Constructor. - CUTLASS_DEVICE IgemmGlobalIteratorAb(typename Base::Params const& _params, - const Coord<3>& bounds, - const Coord<3>& block, - ThreadOffset thread_offset_func = ThreadOffset()) - : Base(_params, bounds, block, thread_offset_func), in_residue_(false), mask_(0xffffffff) { - // The number of elements read in a single iteration. - int const kBlock = TileTraits_::Tile::kW * TileTraits_::kAccessSize; - // The residue. - int const kResidue = (int)(bounds[1] % kBlock); - - // Compute the number of elements that are valid. - int const left = kResidue - Base::thread_offset[2]; - if (left > 0 && left < 4) { - mask_ = (1u << (8 * left)) - 1u; - } - } - - /// The accessor. - CUTLASS_DEVICE void get(typename Base::AccessType& value, int d, int h, int w, int c) const { - Base::get(value, d, h, w, c); - if (in_residue_) { - reinterpret_cast<uint32_t&>(value) &= mask_; - } - } - - /// Move to residue portion. - CUTLASS_DEVICE void move_to_residue(typename Base::Index k) { - Base::move_to_residue(k); - in_residue_ = true; - } - - /// Move back to the beginning of the first tile. - CUTLASS_DEVICE void rollback() { - Base::rollback(); - in_residue_ = false; - } - - /// Are we in the residue? - bool in_residue_; - /// The mask to clean up the values. - uint32_t mask_; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/igemm_multiply_add.h b/cutlass-example/cutlass/gemm/igemm_multiply_add.h deleted file mode 100644 index 5a8baec..0000000 --- a/cutlass-example/cutlass/gemm/igemm_multiply_add.h +++ /dev/null @@ -1,89 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Implements matrix multiply accumulate operation of 8-bit integer data using DP4A - instruction. -*/ -#pragma once - -#include <cutlass/fragment.h> - -#include <cutlass/gemm/thread_multiply_add.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Template performing matrix multiply-add operation within a thread -template <typename AccumulatorsPerThread_, typename ThreadsPerWarp_> -struct ThreadMultiplyAdd<AccumulatorsPerThread_, ThreadsPerWarp_, int8_t, int8_t, int> { - /// The shape of the instruction. - typedef Shape<4, 1, 1> InstructionShape; - /// The number of accumulators per thread. - typedef AccumulatorsPerThread_ AccumulatorsPerThread; - /// The number of threads per warp. - typedef ThreadsPerWarp_ ThreadsPerWarp; - /// The number of accumulators per warp. - typedef typename ShapeMul<AccumulatorsPerThread, ThreadsPerWarp>::Shape AccumulatorsPerWarp; - /// The type for A. - typedef int8_t ScalarA; - /// The fragment for A. - typedef Fragment<ScalarA, AccumulatorsPerThread::kW * 4> FragmentA; - /// The type for B. - typedef int8_t ScalarB; - /// The fragment for B. - typedef Fragment<ScalarB, AccumulatorsPerThread::kH * 4> FragmentB; - /// The type for C and D. - typedef int ScalarC; - /// The accumulators. - typedef Fragment<ScalarC, AccumulatorsPerThread::kH * AccumulatorsPerThread::kW> Accumulators; - - /// Ctor. - CUTLASS_DEVICE ThreadMultiplyAdd() {} - - /// Multiply : d = a*b + c. - CUTLASS_DEVICE void multiply_add(FragmentA const& a, - FragmentB const& b, - Accumulators const& c, - Accumulators& d) { - // The inputs. - int const* a_int = reinterpret_cast<int const*>(&a[0]); - int const* b_int = reinterpret_cast<int const*>(&b[0]); - - for (int j = 0; j < AccumulatorsPerThread::kH; ++j) { - for (int i = 0; i < AccumulatorsPerThread::kW; ++i) { - asm volatile("dp4a.s32.s32 %0, %1, %2, %3;" - : "=r"(d[j * AccumulatorsPerThread::kW + i]) - : "r"(a_int[i]), "r"(b_int[j]), "r"(c[j * AccumulatorsPerThread::kW + i])); - } - } - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/igemm_swizzle.h b/cutlass-example/cutlass/gemm/igemm_swizzle.h deleted file mode 100644 index 77cf711..0000000 --- a/cutlass-example/cutlass/gemm/igemm_swizzle.h +++ /dev/null @@ -1,115 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Transposes a fragment of data containing packed 8-bit integer elements. -*/ -#pragma once - -#include <cutlass/fragment.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GlobalIterator_> -struct IgemmSwizzle { - /// The global iterator. - typedef GlobalIterator_ GlobalIterator; - /// The source fragment. - typedef typename GlobalIterator::Fragment Fragment; - /// The shape of the source fragment. - typedef typename GlobalIterator::FragmentShape FragmentShape; - - /// The source fragment. - typedef Fragment InputFragment; - /// The destination fragment. - typedef Fragment OutputFragment; - - /// The src/dst must be int8 fragments. - static_assert((platform::is_same<typename Fragment::Element, int8_t>::value), "Works on int8"); - - /// The number of elements must be a multiple of 4. - static_assert(FragmentShape::kH % 4 == 0 && ShapeCount<FragmentShape>::kWc % 4 == 0, - "Not multiple of 4"); - - /// Ctor. - CUTLASS_DEVICE IgemmSwizzle() {} - - /// Transform a fragment. - CUTLASS_DEVICE void transform(Fragment const& src, Fragment& dst) { - // Expose src/dst as int arrays. - int const* src_int = reinterpret_cast<int const*>(&src[0]); - int* dst_int = reinterpret_cast<int*>(&dst[0]); - - // Transpose the data. - for (int d = 0; d < FragmentShape::kD; ++d) { - for (int h = 0; h < FragmentShape::kH / 4; ++h) { - for (int w = 0; w < ShapeCount<FragmentShape>::kWc / 4; ++w) { - int const i0 = d * (ShapeCount<FragmentShape>::kHwc / 4) + - (4 * h + 0) * (ShapeCount<FragmentShape>::kWc / 4) + w; - int const i1 = d * (ShapeCount<FragmentShape>::kHwc / 4) + - (4 * h + 1) * (ShapeCount<FragmentShape>::kWc / 4) + w; - int const i2 = d * (ShapeCount<FragmentShape>::kHwc / 4) + - (4 * h + 2) * (ShapeCount<FragmentShape>::kWc / 4) + w; - int const i3 = d * (ShapeCount<FragmentShape>::kHwc / 4) + - (4 * h + 3) * (ShapeCount<FragmentShape>::kWc / 4) + w; - - int a0 = src_int[i0]; - int a1 = src_int[i1]; - int a2 = src_int[i2]; - int a3 = src_int[i3]; - - int b0, b1, b2, b3, c0; - asm volatile("prmt.b32 %0, %1, %2, 0x0040;" : "=r"(b0) : "r"(a0), "r"(a1)); - asm volatile("prmt.b32 %0, %1, %2, 0x0040;" : "=r"(c0) : "r"(a2), "r"(a3)); - asm volatile("prmt.b32 %0, %1, %2, 0x5410;" : "=r"(b0) : "r"(b0), "r"(c0)); - - asm volatile("prmt.b32 %0, %1, %2, 0x0051;" : "=r"(b1) : "r"(a0), "r"(a1)); - asm volatile("prmt.b32 %0, %1, %2, 0x0051;" : "=r"(c0) : "r"(a2), "r"(a3)); - asm volatile("prmt.b32 %0, %1, %2, 0x5410;" : "=r"(b1) : "r"(b1), "r"(c0)); - - asm volatile("prmt.b32 %0, %1, %2, 0x0062;" : "=r"(b2) : "r"(a0), "r"(a1)); - asm volatile("prmt.b32 %0, %1, %2, 0x0062;" : "=r"(c0) : "r"(a2), "r"(a3)); - asm volatile("prmt.b32 %0, %1, %2, 0x5410;" : "=r"(b2) : "r"(b2), "r"(c0)); - - asm volatile("prmt.b32 %0, %1, %2, 0x0073;" : "=r"(b3) : "r"(a0), "r"(a1)); - asm volatile("prmt.b32 %0, %1, %2, 0x0073;" : "=r"(c0) : "r"(a2), "r"(a3)); - asm volatile("prmt.b32 %0, %1, %2, 0x5410;" : "=r"(b3) : "r"(b3), "r"(c0)); - - dst_int[i0] = b0; - dst_int[i1] = b1; - dst_int[i2] = b2; - dst_int[i3] = b3; - } - } - } - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/igemm_traits.h b/cutlass-example/cutlass/gemm/igemm_traits.h deleted file mode 100644 index 82f8de5..0000000 --- a/cutlass-example/cutlass/gemm/igemm_traits.h +++ /dev/null @@ -1,539 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defies structural properties of mixed-precision integer GEMM. Multiplicands are assumed - to be packed 8bit integers, accumulators are assumed to be 32b signed integers, and output - formats vary. -*/ -#pragma once - -#include <cutlass/convert.h> -#include <cutlass/gemm/gemm.h> -#include <cutlass/gemm/gemm_epilogue.h> -#include <cutlass/gemm/gemm_epilogue_traits.h> -#include <cutlass/gemm/gemm_global_tile.h> -#include <cutlass/gemm/gemm_shared_tile.h> -#include <cutlass/gemm/gemm_traits.h> -#include <cutlass/gemm/igemm_epilogue.h> -#include <cutlass/gemm/igemm_global_tile.h> -#include <cutlass/gemm/igemm_multiply_add.h> -#include <cutlass/gemm/igemm_swizzle.h> -#include <cutlass/reshape_tile.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The tile size for the GEMM KxNxM. - typename OutputTile_, - /// The output type. - typename ScalarD_, - /// The number of accumulators per thread. - typename AccumulatorsPerThread_> -struct IgemmConfig - : public GemmConfig< - /// The scalar type for A. - int8_t, - /// The scalar type for B. - int8_t, - /// The scalar type for C. - ScalarD_, - /// The scalar type for D. - ScalarD_, - /// The tile size for the GEMM KxNxM. - OutputTile_, - /// The functor to do the math in the main loop. - ThreadMultiplyAdd<AccumulatorsPerThread_, Shape<1, 4, 8>, int8_t, int8_t, int>, - /// The number of scalars per LDG for A. - 4, - /// The number of scalars per STS for A. - 4, - /// The number of scalars per LDS for A. - 16, - /// The number of scalars per LDG for B. - 4, - /// The number of scalars per STS for B. - 4, - /// The number of scalars per LDS for B. - 16, - /// The number of scalars per LDG for C and STG for D. - 1, - /// The number of scalars per STS for D. - 4, - /// The number of scalars per LDS for D. - 1, - /// The number of stages in shared memory. - 2, - /// Enable the code path that deals with the residue in epilogue. - true> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename OutputTile_, typename AccumulatorsPerThread_> -struct IgemmConfig<OutputTile_, int8_t, AccumulatorsPerThread_> - : public GemmConfig< - /// The scalar type for A. - int8_t, - /// The scalar type for B. - int8_t, - /// The scalar type for C. - int8_t, - /// The scalar type for D. - int8_t, - /// The tile size for the GEMM KxNxM. - OutputTile_, - /// The functor to do the math in the main loop. - ThreadMultiplyAdd<AccumulatorsPerThread_, Shape<1, 4, 8>, int8_t, int8_t, int>, - /// The number of scalars per LDG for A. - 4, - /// The number of scalars per STS for A. - 4, - /// The number of scalars per LDS for A. - 16, - /// The number of scalars per LDG for B. - 4, - /// The number of scalars per STS for B. - 4, - /// The number of scalars per LDS for B. - 16, - /// The number of scalars per LDG for C and STG for D. - 4, - /// The number of scalars per STS for D. - 4, - /// The number of scalars per LDS for D. - 4, - /// The number of stages in shared memory. - 2, - /// Enable the code path that deals with the residue in epilogue. - true> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <enum MatrixLayout::Kind kLayout_, typename GemmConfig_, typename Index_> -struct IgemmTileTraitsHelperA : public GemmTileTraitsHelperA<kLayout_, GemmConfig_> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_, typename Index_> -struct IgemmTileTraitsHelperA<MatrixLayout::kColumnMajor, GemmConfig_, Index_> - : public GemmTileTraitsHelperA<MatrixLayout::kColumnMajor, GemmConfig_> { - /// The base config. - typedef GemmTileTraitsHelperA<MatrixLayout::kColumnMajor, GemmConfig_> Base; - - /// The number of scalars per LDG/STS/LDS for A. - static int const kScalarsPerStsA = 16; - - /// The traits class to build the iterator to load data from global memory for A^N. - typedef IgemmGlobalTileTraits< - GemmOperand::kA, - // The layout. - MatrixLayout::kColumnMajor, - // The pointer is float const. - int8_t const, - // The tile has size KxM in GEMM's terminology. - Shape<1, GemmConfig_::OutputTile::kD, GemmConfig_::OutputTile::kW>, - // The threads are distributed as warps x 32 (the traits may reorganize). - Shape<1, ShapeCount<typename GemmConfig_::Warps>::kCount, GemmConfig_::kWarpSize>, - // The number of scalars per LDG (LDG.32 or LDG.128, etc). - GemmConfig_::kScalarsPerLdgA> - GlobalTileTraits; - - // The iterator. - typedef GemmGlobalIteratorAb<GlobalTileTraits, Index_> GlobalLoadIterator; - - /// The traits class to build the iterator to store data to shared memory for A^N. - typedef GemmSharedStoreTileAbTraits< - // The pointer is float. - int8_t, - // The tile has size KxM in GEMM's terminology. - Shape<GemmConfig_::kStages, GemmConfig_::OutputTile::kD / 4, GemmConfig_::OutputTile::kW * 4>, - // The threads are distributed as warps x 32 (the traits may reorganize). - typename GlobalTileTraits::Threads, - // The number of scalars per STS (STS.32 or STS.128, etc). - kScalarsPerStsA> - SharedStoreTileTraits; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_, typename Index_> -struct IgemmTileTraitsHelperA<MatrixLayout::kRowMajor, GemmConfig_, Index_> { - /// The layout. - static MatrixLayout::Kind const kLayout = MatrixLayout::kRowMajor; - - /// The input scalar. - typedef int8_t Scalar; - /// The scalar stored in shared memory. - typedef int8_t MultiplyAddScalar; - - /// The number of scalars per LDG/STS/LDS for A. - static int const kScalarsPerStsA = 16; - - /// The traits class to build the iterator to load data from global memory for A^T. - typedef IgemmGlobalTileTraits< - GemmOperand::kA, - // The layout. - MatrixLayout::kRowMajor, - // The pointer is float const. - int8_t const, - // The tile has size NxK in GEMM's terminology. - Shape<1, GemmConfig_::OutputTile::kW, GemmConfig_::OutputTile::kD>, - // The threads are distributed as warps x 32 (the traits may reorganize). - Shape<1, ShapeCount<typename GemmConfig_::Warps>::kCount, GemmConfig_::kWarpSize>, - // The number of scalars per LDG (LDG.32 or LDG.128, etc). - GemmConfig_::kScalarsPerLdgA> - GlobalTileTraits; - - // The iterator. - typedef IgemmGlobalIteratorAb<GlobalTileTraits, Index_> GlobalLoadIterator; - - /// The traits class to build the iterator to store data to shared memory for A^N. - typedef GemmSharedStoreWithSkewTileAbTraits< - // The pointer is int8. - int8_t, - // The tile has size KxN in GEMM's terminology. - Shape<GemmConfig_::kStages, GemmConfig_::OutputTile::kD / 4, GemmConfig_::OutputTile::kW * 4>, - // The threads are distributed as (threads / K) x K (the traits may reorganize). - typename GlobalTileTraits::Threads, - // The number of scalars per STS. - kScalarsPerStsA, - // The skew to avoid bank conflicts added in the tile W dimension. - 16> - SharedStoreTileTraits; - - /// The traits class to build the iterator to load from shared memory for A^N. - typedef GemmSharedLoadTileATraits< - // The pointer is float const. - int8_t const, - // The output tile size. - typename GemmConfig_::OutputTile, - // The number of warps. - typename GemmConfig_::Warps, - // The number of threads per warp. - typename GemmConfig_::MultiplyAdd::ThreadsPerWarp, - // The shape of the FMA instruction. - typename GemmConfig_::InstructionShape, - // The number of stages. - GemmConfig_::kStages, - // The number of scalars per LDS. - 16, - // The skew. - SharedStoreTileTraits::kSkew> - SharedLoadTileTraits; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <enum MatrixLayout::Kind kLayout_, typename GemmConfig_, typename Index_> -struct IgemmTileTraitsHelperB : public GemmTileTraitsHelperB<kLayout_, GemmConfig_> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_, typename Index_> -struct IgemmTileTraitsHelperB<MatrixLayout::kColumnMajor, GemmConfig_, Index_> { - /// The layout. - static MatrixLayout::Kind const kLayout = MatrixLayout::kColumnMajor; - - /// The input scalar. - typedef int8_t Scalar; - /// The scalar stored in shared memory. - typedef int8_t MultiplyAddScalar; - - /// The number of scalars per LDG/STS/LDS for B. - static int const kScalarsPerStsB = 16; - - /// The traits class to build the iterator to load data from global memory for B^T. - typedef IgemmGlobalTileTraits< - GemmOperand::kB, - // The layout. - MatrixLayout::kColumnMajor, - // The pointer is float const. - int8_t const, - // The tile has size NxK in GEMM's terminology. - Shape<1, GemmConfig_::OutputTile::kH, GemmConfig_::OutputTile::kD>, - // The threads are distributed as warps x 32 (the traits may reorganize). - Shape<1, ShapeCount<typename GemmConfig_::Warps>::kCount, GemmConfig_::kWarpSize>, - // The number of scalars per LDG (LDG.32 or LDG.128, etc). - GemmConfig_::kScalarsPerLdgB> - GlobalTileTraits; - - // The iterator. - typedef IgemmGlobalIteratorAb<GlobalTileTraits, Index_> GlobalLoadIterator; - - /// The traits class to build the iterator to store data to shared memory for B^N. - typedef GemmSharedStoreWithSkewTileAbTraits< - // The pointer is int8. - int8_t, - // The tile has size KxN in GEMM's terminology. - Shape<GemmConfig_::kStages, GemmConfig_::OutputTile::kD / 4, GemmConfig_::OutputTile::kH * 4>, - // The threads are distributed as (threads / K) x K (the traits may reorganize). - typename GlobalTileTraits::Threads, - // The number of scalars per STS. - kScalarsPerStsB, - // The skew to avoid bank conflicts added in the tile W dimension. - 16> - SharedStoreTileTraits; - - /// The traits class to build the iterator to load from shared memory for B^N. - typedef GemmSharedLoadTileBTraits< - // The pointer is float const. - int8_t const, - // The output tile size. - typename GemmConfig_::OutputTile, - // The number of warps. - typename GemmConfig_::Warps, - // The number of threads per warp. - typename GemmConfig_::MultiplyAdd::ThreadsPerWarp, - // The shape of the FMA instruction. - typename GemmConfig_::InstructionShape, - // The number of stages. - GemmConfig_::kStages, - // The number of scalars per LDS. - 16, - // The skew. - SharedStoreTileTraits::kSkew> - SharedLoadTileTraits; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_, typename Index_> -struct IgemmTileTraitsHelperB<MatrixLayout::kRowMajor, GemmConfig_, Index_> - : public GemmTileTraitsHelperB<MatrixLayout::kRowMajor, GemmConfig_> { - /// The base config. - typedef GemmTileTraitsHelperB<MatrixLayout::kRowMajor, GemmConfig_> Base; - - /// The number of scalars per LDG/STS/LDS for B. - static int const kScalarsPerStsB = 16; - - /// The traits class to build the iterator to load data from global memory for B^T. - typedef IgemmGlobalTileTraits< - GemmOperand::kB, - // The layout. - MatrixLayout::kRowMajor, - // The pointer is float const. - int8_t const, - // The tile has size KxM in GEMM's terminology. - Shape<1, GemmConfig_::OutputTile::kD, GemmConfig_::OutputTile::kH>, - // The threads are distributed as warps x 32 (the traits may reorganize). - Shape<1, ShapeCount<typename GemmConfig_::Warps>::kCount, GemmConfig_::kWarpSize>, - // The number of scalars per LDG (LDG.32 or LDG.128, etc). - GemmConfig_::kScalarsPerLdgB> - GlobalTileTraits; - - // The iterator. - typedef GemmGlobalIteratorAb<GlobalTileTraits, Index_> GlobalLoadIterator; - - /// The traits class to build the iterator to store data to shared memory for B^N. - typedef GemmSharedStoreTileAbTraits< - // The pointer is float. - int8_t, - // The tile has size KxM in GEMM's terminology. - Shape<GemmConfig_::kStages, GemmConfig_::OutputTile::kD / 4, GemmConfig_::OutputTile::kH * 4>, - // The threads are distributed as warps x 32 (the traits may reorganize). - typename GlobalTileTraits::Threads, - // The number of scalars per STS (STS.32 or STS.128, etc). - kScalarsPerStsB> - SharedStoreTileTraits; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <enum MatrixLayout::Kind kLayout_, typename Iterator_> -struct IgemmTransformerA {}; - -template <typename Iterator_> -struct IgemmTransformerA<MatrixLayout::kRowMajor, Iterator_> { - typedef Copy<typename Iterator_::Fragment> Transformer; -}; - -template <typename Iterator_> -struct IgemmTransformerA<MatrixLayout::kColumnMajor, Iterator_> { - typedef IgemmSwizzle<Iterator_> Transformer; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <enum MatrixLayout::Kind kLayout_, typename Iterator_> -struct IgemmTransformerB {}; - -template <typename Iterator_> -struct IgemmTransformerB<MatrixLayout::kColumnMajor, Iterator_> { - typedef Copy<typename Iterator_::Fragment> Transformer; -}; - -template <typename Iterator_> -struct IgemmTransformerB<MatrixLayout::kRowMajor, Iterator_> { - typedef IgemmSwizzle<Iterator_> Transformer; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The layout for A. - MatrixLayout::Kind kLayoutA_, - /// The layout for B. - MatrixLayout::Kind kLayoutB_, - /// The output tile. - typename OutputTile_, - /// The output type. - typename ScalarD_, - /// The functor to do the math in the epilogue. - typename EpilogueFunctor_, - /// The number of accumulators per thread. - typename AccumulatorsPerThread_ = Shape<32, 8, 8>, - /// The index. - typename Index_ = int> -struct IgemmTraitsHelper { - /// The IGEMM config. - typedef IgemmConfig<OutputTile_, ScalarD_, AccumulatorsPerThread_> GemmConfig; - /// The GEMM config for A. - typedef IgemmTileTraitsHelperA<kLayoutA_, GemmConfig, Index_> GemmTileTraitsHelperA; - /// The GEMM config for B. - typedef IgemmTileTraitsHelperB<kLayoutB_, GemmConfig, Index_> GemmTileTraitsHelperB; - - /// The iterator to load A from global memory. - typedef typename GemmTileTraitsHelperA::GlobalLoadIterator GlobalLoadIteratorA; - - /// The default transformer for A. - typedef typename IgemmTransformerA<GemmTileTraitsHelperA::kLayout, - GlobalLoadIteratorA>::Transformer GlobalTransformerA; - /// The iterator to store A to shared memory. - typedef TileStoreIterator<typename GemmTileTraitsHelperA::SharedStoreTileTraits, - typename GemmTileTraitsHelperA::SharedStoreTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedStoreIteratorA; - /// The stream to load A from global memory to shared memory. - typedef GlobalLoadStream<GlobalLoadIteratorA, SharedStoreIteratorA, GlobalTransformerA> - GlobalLoadStreamA; - - /// The iterator to load B from global memory. - typedef typename GemmTileTraitsHelperB::GlobalLoadIterator GlobalLoadIteratorB; - - // The default transformer for B. - typedef typename IgemmTransformerB<GemmTileTraitsHelperB::kLayout, - GlobalLoadIteratorB>::Transformer GlobalTransformerB; - /// The iterator to store B to shared memory. - typedef TileStoreIterator<typename GemmTileTraitsHelperB::SharedStoreTileTraits, - typename GemmTileTraitsHelperB::SharedStoreTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedStoreIteratorB; - /// The stream to load B from global memory to shared memory. - typedef GlobalLoadStream<GlobalLoadIteratorB, SharedStoreIteratorB, GlobalTransformerB> - GlobalLoadStreamB; - - /// The iterator to load A from shared memory. - typedef TileLoadIterator<typename GemmTileTraitsHelperA::SharedLoadTileTraits, - typename GemmTileTraitsHelperA::SharedLoadTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedLoadIteratorA; - /// The stream to load A from shared memory. - typedef SharedLoadStream<SharedLoadIteratorA, Copy<typename SharedLoadIteratorA::Fragment> > - SharedLoadStreamA; - /// The iterator to load B from shared memory. - typedef TileLoadIterator<typename GemmTileTraitsHelperB::SharedLoadTileTraits, - typename GemmTileTraitsHelperB::SharedLoadTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedLoadIteratorB; - /// The stream to load B from shared memory. - typedef SharedLoadStream<SharedLoadIteratorB, Copy<typename SharedLoadIteratorB::Fragment> > - SharedLoadStreamB; - - /// The multiply-add functor. - typedef typename GemmConfig::MultiplyAdd MultiplyAdd; - /// The object to clear accumulators. - typedef ClearAccumulators<typename MultiplyAdd::ScalarC> ClearAccumulators; - - /// The epilogue. - typedef IgemmEpilogue<IgemmEpilogueTraits<GemmConfig, EpilogueFunctor_> > Epilogue; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename ScalarD_> -struct IgemmEpilogueScalar { - typedef float Scalar; -}; - -template <> -struct IgemmEpilogueScalar<int> { - typedef int Scalar; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The layout for A. - MatrixLayout::Kind kLayoutA_, - /// The layout for B. - MatrixLayout::Kind kLayoutB_, - /// The output tile. - typename OutputTile_ = Shape<32, 128, 128>, - /// The output type. - typename ScalarD_ = int, - /// The functor to do the math in the epilogue. - typename EpilogueFunctor_ = LinearScaling<typename IgemmEpilogueScalar<ScalarD_>::Scalar>, - /// The number of accumulators per thread. - typename AccumulatorsPerThread_ = Shape<32, 8, 8>, - /// The index. - typename Index_ = int, - /// The helper class. - typename Helper_ = IgemmTraitsHelper<kLayoutA_, - kLayoutB_, - OutputTile_, - ScalarD_, - EpilogueFunctor_, - AccumulatorsPerThread_, - Index_> > -struct IgemmTraits : public GemmTraits< - // The config. - typename Helper_::GemmConfig, - // The stream to load A from global memory to shared memory. - typename Helper_::GlobalLoadStreamA, - // The stream to load B from global memory to shared memory. - typename Helper_::GlobalLoadStreamB, - // The stream to load A from shared memory. - typename Helper_::SharedLoadStreamA, - // The stream to load B from shared memory. - typename Helper_::SharedLoadStreamB, - // The epilogue. - typename Helper_::Epilogue, - // The block swizzle to reorganize the grid. - IdentityBlockSwizzle, - // The index. - Index_, - // The tool used to clear accumulators. - typename Helper_::ClearAccumulators> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/linear_scaling.h b/cutlass-example/cutlass/gemm/linear_scaling.h deleted file mode 100644 index 979c93f..0000000 --- a/cutlass-example/cutlass/gemm/linear_scaling.h +++ /dev/null @@ -1,85 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Implements the BLAS linear scaling function alpha*AB + beta*C -*/ -#pragma once - -#include <cutlass/fragment_multiply_add.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Functor to compute linear combination of fragments -template <typename Scalar_, typename FragmentMultiplyAdd_ = FragmentMultiplyAdd<Scalar_> > -struct LinearScaling { - // The scalar. - typedef Scalar_ Scalar; - // The adapater. - typedef FragmentMultiplyAdd_ FragmentMultiplyAdd; - - /// The parameters. - struct Params { - /// The alpha/beta scaling params. - Scalar alpha, beta; - - /// Initialize the parameters. - template <typename GemmDesc_> - CUTLASS_HOST_DEVICE int initialize(GemmDesc_ const& desc) { - alpha = desc.alpha; - beta = desc.beta; - return 0; - } - }; - - /// Ctor. - CUTLASS_DEVICE LinearScaling(Params const& params) : alpha(params.alpha), beta(params.beta) {} - - /// Evaluate the functor. - template <typename FragmentA_, typename FragmentB_> - CUTLASS_DEVICE void evaluate(FragmentA_ const& accum, FragmentB_& output) { - FragmentMultiplyAdd mad; - mad.multiply(alpha, accum, output); - } - - /// Evaluate the functor. - template <typename FragmentA_, typename FragmentB_> - CUTLASS_DEVICE void evaluate(FragmentA_ const& accum, FragmentB_ const& old, FragmentB_& output) { - FragmentMultiplyAdd mad; - FragmentB_ tmp; - mad.multiply(beta, old, tmp); - mad.multiply_add(alpha, accum, tmp, output); - } - - /// The alpha/beta scaling factors. - Scalar alpha, beta; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/sgemm_traits.h b/cutlass-example/cutlass/gemm/sgemm_traits.h deleted file mode 100644 index 66b7677..0000000 --- a/cutlass-example/cutlass/gemm/sgemm_traits.h +++ /dev/null @@ -1,127 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defies structural properties of single-precision GEMM. -*/ -#pragma once - -#include <cutlass/gemm/gemm.h> -#include <cutlass/gemm/gemm_epilogue.h> -#include <cutlass/gemm/gemm_epilogue_traits.h> -#include <cutlass/gemm/gemm_global_tile.h> -#include <cutlass/gemm/gemm_shared_tile.h> -#include <cutlass/gemm/gemm_traits.h> -#include <cutlass/gemm/thread_multiply_add.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The tile size for the GEMM KxNxM. - typename OutputTile_, - /// The number of accumulators per thread. - typename AccumulatorsPerThread_, - /// The number of scalars per LDG for A. - int kScalarsPerLdgA_ = 1, - /// The number of scalars per LDG for B. - int kScalarsPerLdgB_ = 1> -struct SgemmConfig - : public GemmConfig< - /// The scalar type for A. - float, - /// The scalar type for B. - float, - /// The scalar type for C. - float, - /// The scalar type for D. - float, - /// The tile size for the GEMM KxNxM. - OutputTile_, - /// The functor to do the math in the main loop. - ThreadMultiplyAdd<AccumulatorsPerThread_, Shape<1, 4, 8>, float, float, float>, - /// The number of scalars per LDG for A. - kScalarsPerLdgA_, - /// The number of scalars per STS for A. - kScalarsPerLdgA_, - /// The number of scalars per LDS for A. - 4, - /// The number of scalars per LDG for B. - kScalarsPerLdgB_, - /// The number of scalars per STS for B. - kScalarsPerLdgB_, - /// The number of scalars per LDS for B. - 4, - /// The number of scalars per LDG for C and STG for D. - 1, - /// The number of scalars per STS for D. - 4, - /// The number of scalars per LDS for D. - 1, - /// The number of stages in shared memory. - 2> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The layout for A. - MatrixLayout::Kind kLayoutA_, - /// The layout for B. - MatrixLayout::Kind kLayoutB_, - /// The output tile. - typename OutputTile_ = Shape<8, 128, 128>, - /// The functor to use in the epilogue. - typename EpilogueFunctor_ = LinearScaling<float>, - /// The number of accumulators per thread. - typename AccumulatorsPerThread_ = Shape<8, 8, 8>, - /// The number of floats loaded in one LDG for A. - int kScalarsPerLdgA_ = 1, - /// The number of floats loaded in one LDG for B. - int kScalarsPerLdgB_ = 1, - /// The index. - typename Index_ = int, - /// The SGEMM config. - typename GemmConfig_ = - SgemmConfig<OutputTile_, AccumulatorsPerThread_, kScalarsPerLdgA_, kScalarsPerLdgB_>, - /// The traits class for the epilogue. - typename GemmEpilogueTraits_ = - SimplifiedGemmEpilogueTraits<GemmConfig_, EpilogueFunctor_, Index_> > -struct SgemmTraits : public SimplifiedGemmTraits< - // The layout for A. - kLayoutA_, - // The layout for B. - kLayoutB_, - // The config. - GemmConfig_, - // The epilogue. - GemmEpilogue<GemmEpilogueTraits_>, - // The index. - Index_> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/thread_multiply_add.h b/cutlass-example/cutlass/gemm/thread_multiply_add.h deleted file mode 100644 index 20dca15..0000000 --- a/cutlass-example/cutlass/gemm/thread_multiply_add.h +++ /dev/null @@ -1,84 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Template implementing matrix multiply-add operations on fragments. -*/ -#pragma once - -#include <cutlass/fragment.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Template performing matrix multiply-add operation within a thread -template <typename AccumulatorsPerThread_, - typename ThreadsPerWarp_, - typename ScalarA_, - typename ScalarB_, - typename ScalarC_> -struct ThreadMultiplyAdd { - /// The shape of the instruction. - typedef Shape<1, 1, 1, 1> InstructionShape; - /// The number of accumulators per thread. - typedef AccumulatorsPerThread_ AccumulatorsPerThread; - /// The number of threads per warp. - typedef ThreadsPerWarp_ ThreadsPerWarp; - /// The number of accumulators per warp. - typedef typename ShapeMul<AccumulatorsPerThread, ThreadsPerWarp>::Shape AccumulatorsPerWarp; - /// The type for A. - typedef ScalarA_ ScalarA; - /// The fragment for A. - typedef Fragment<ScalarA, AccumulatorsPerThread::kW> FragmentA; - /// The type for B. - typedef ScalarB_ ScalarB; - /// The fragment for B. - typedef Fragment<ScalarB, AccumulatorsPerThread::kH> FragmentB; - /// The type for C and D. - typedef ScalarC_ ScalarC; - /// The accumulators. - typedef Fragment<ScalarC, AccumulatorsPerThread::kH * AccumulatorsPerThread::kW, 16> Accumulators; - - /// Ctor. - CUTLASS_DEVICE ThreadMultiplyAdd() {} - - /// Multiply : d = a*b + c. - CUTLASS_DEVICE void multiply_add(FragmentA const& a, - FragmentB const& b, - Accumulators const& c, - Accumulators& d) { - for (int j = 0; j < AccumulatorsPerThread::kH; ++j) { - for (int i = 0; i < AccumulatorsPerThread::kW; ++i) { - d[j * AccumulatorsPerThread::kW + i] = a[i] * b[j] + c[j * AccumulatorsPerThread::kW + i]; - } - } - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/wmma_gemm_epilogue_traits.h b/cutlass-example/cutlass/gemm/wmma_gemm_epilogue_traits.h deleted file mode 100644 index 0fafacf..0000000 --- a/cutlass-example/cutlass/gemm/wmma_gemm_epilogue_traits.h +++ /dev/null @@ -1,161 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines structural properties of WMMA GEMM's epilogue phase. -*/ -#pragma once - -#include <cutlass/wmma_matrix.h> -#ifdef CUTLASS_USE_WMMA_API - -#include <cutlass/convert.h> -#include <cutlass/coord.h> -#include <cutlass/gemm/gemm_global_stream.h> -#include <cutlass/gemm/gemm_shared_stream.h> -#include <cutlass/gemm/linear_scaling.h> -#include <cutlass/gemm/wmma_gemm_global_tile.h> -#include <cutlass/gemm/wmma_gemm_shared_tile.h> -#include <cutlass/reshape_tile.h> -#include <cutlass/tile_iterator.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_, typename EpilogueFunctor_, typename Index_ = int> -struct WmmaGemmEpilogueTraitsHelper { - /// The scalar. - typedef typename EpilogueFunctor_::Scalar Scalar; - /// The output tile. - typedef typename GemmConfig_::OutputTile OutputTile; - - /// The number of WMMAs in the H dimension. - static int const kWmmasPerH = - GemmConfig_::AccumulatorsPerWarp::kH / GemmConfig_::InstructionShape::kH; - /// The number of iterations in the epilogue. That's the number of "horizontal" WMMAs. - typedef Shape<1, 1, kWmmasPerH> Iterations; - // The iteration strides in the H/W dimension. - typedef Shape<0, 0, 0> Delta; - /// The functor to do the math in the epilogue. - typedef EpilogueFunctor_ Functor; - - /// The traits class to build the iterator to store to shared memory for D. - typedef WmmaGemmSharedStoreTileDTraits< - // The output layout. - MatrixLayout::kColumnMajor, - // The pointer is float. - typename Functor::Scalar, - // The output tile size. - typename GemmConfig_::OutputTile, - // The number of warps. - typename GemmConfig_::Warps, - // The shape of the instruction. - typename GemmConfig_::InstructionShape> - SharedStoreTileTraits; - - typedef WmmaMatrix<GemmOperand::kC, - MatrixLayout::kColumnMajor, - Scalar, - typename GemmConfig_::InstructionShape> - WmmaMatrix; - - /// The iterator to store D to shared memory. - typedef TileStoreIterator<SharedStoreTileTraits, - typename SharedStoreTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared, - Index_, - WmmaMatrix, - IteratorFragment::kWmmaMatrix> - SharedStoreIteratorD; - - /// The shared store transformer for D. - typedef Copy<typename SharedStoreIteratorD::Fragment> SharedStoreTransformerD; - - /// The traits class to build the iterator to load from shared memory for D. - typedef WmmaGemmSharedLoadTileDTraits< - // The pointer. - typename Functor::Scalar, - // The tile size. - typename SharedStoreIteratorD::Tile, - // The number of threads. - Shape<1, ShapeCount<typename GemmConfig_::Warps>::kCount, GemmConfig_::kWarpSize>, - // The number of scalars per LDS. - GemmConfig_::kScalarsPerLdsD> - SharedLoadTileTraits; - - /// The iterator to load D from shared memory. - typedef TileLoadIterator<SharedLoadTileTraits, - typename SharedLoadTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedLoadIteratorD; - - /// The traits class to build the iterator to load data from global memory for C^N. - typedef WmmaGemmGlobalIteratorCdTraits< - // The pointer is float const. - typename GemmConfig_::ScalarC const, - // The tile has size (N / Iterations)xM in GEMM's terminology. - Shape<1, - GemmConfig_::OutputTile::kH / ShapeCount<Iterations>::kCount, - GemmConfig_::OutputTile::kW>, - // The threads are distributed as warps x 32 (the traits may reorganize). - Shape<1, ShapeCount<typename GemmConfig_::Warps>::kCount, GemmConfig_::kWarpSize>, - // The number of scalars per LDG (LDG.32 or LDG.128, etc). - GemmConfig_::kScalarsPerLdgC> - GlobalLoadTileTraits; - - /// The iterator to load C. - typedef WmmaGemmGlobalIteratorCd<GlobalLoadTileTraits, Index_> GlobalLoadIteratorC; - /// The transformer for C. - typedef Copy<typename GlobalLoadIteratorC::Fragment> GlobalTransformerC; - - /// The traits class to build the iterator to store data to global memory for D^N. - typedef WmmaGemmGlobalIteratorCdTraits< - // The pointer is float. - typename GemmConfig_::ScalarD, - // The tile has size (N / Iterations)xM in GEMM's terminology. - Shape<1, - GemmConfig_::OutputTile::kH / ShapeCount<Iterations>::kCount, - GemmConfig_::OutputTile::kW>, - // The threads are distributed as warps x 32 (the traits may reorganize). - Shape<1, ShapeCount<typename GemmConfig_::Warps>::kCount, GemmConfig_::kWarpSize>, - // The number of scalars per LDG (LDG.32 or LDG.128, etc). - GemmConfig_::kScalarsPerStgD> - GlobalStoreTileTraits; - - /// The iterator to store D. - typedef WmmaGemmGlobalIteratorCd<GlobalStoreTileTraits, Index_> GlobalStoreIteratorD; - /// The transformer for D. - typedef Copy<typename GlobalStoreIteratorD::Fragment> GlobalTransformerD; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass - -#endif // defined CUTLASS_USE_WMMA_API diff --git a/cutlass-example/cutlass/gemm/wmma_gemm_global_tile.h b/cutlass-example/cutlass/gemm/wmma_gemm_global_tile.h deleted file mode 100644 index dbd57f6..0000000 --- a/cutlass-example/cutlass/gemm/wmma_gemm_global_tile.h +++ /dev/null @@ -1,211 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines tile iterator traits for loading thread block-level tile from global memory. -*/ -#pragma once - -#include <cutlass/gemm/gemm_global_tile.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, typename Tile_, typename Threads_, int kAccessSize_> -struct WmmaGemmGlobalIteratorCdTraits : public GemmGlobalTileTraits<GemmOperand::kC, - MatrixLayout::kColumnMajor, - Scalar_, - Tile_, - Threads_, - kAccessSize_> { - /// The base class. - typedef GemmGlobalTileTraits<GemmOperand::kC, - MatrixLayout::kColumnMajor, - Scalar_, - Tile_, - Threads_, - kAccessSize_> - Base; - - /// Override the strides in each dimension between different loads/stores. - typedef Shape<0, 0, Base::Delta::kW, Base::Delta::kC> Delta; - - /// Computes the thread offset in (H, W) based on thread ID - struct ThreadOffset { - CUTLASS_HOST_DEVICE - Coord<4> operator()() const { - int thread_offset_h = threadIdx.x / Base::Threads::kW; - int thread_offset_w = threadIdx.x % Base::Threads::kW * Base::ThreadsDelta::kW; - - return make_Coord(0, thread_offset_h, thread_offset_w, 0); - } - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename TileTraits_, typename Index_ = int> -struct WmmaGemmGlobalIteratorCd : public TileIteratorBase<TileTraits_, - typename TileTraits_::Scalar, - IteratorAdvance::kH, - MemorySpace::kGlobal, - Index_> { - /// This class. - typedef WmmaGemmGlobalIteratorCd<TileTraits_, Index_> This_; - /// The traits. - typedef TileTraits_ Traits; - /// The base class. - typedef TileIteratorBase<Traits, - typename TileTraits_::Scalar, - IteratorAdvance::kH, - MemorySpace::kGlobal, - Index_> - Base; - /// Override the strides in each dimension between different loads/stores. - typedef Shape<0, 0, Base::Delta::kW, Base::Delta::kC> ImmediateOffsetStrides; - /// The layout. - static MatrixLayout::Kind const kLayout = TileTraits_::kLayout; - - /// The scalar. - typedef typename TileTraits_::Scalar Scalar; - /// The pointer. - typedef typename TileTraits_::Pointer Pointer; - /// The threads. - typedef typename TileTraits_::Threads Threads; - /// The index. - typedef Index_ Index; - /// The thread offset functor. - typedef typename TileTraits_::ThreadOffset ThreadOffset; - - /// The params. - struct Params { - /// The pointer. - Pointer pointer; - /// The stride in the H dimension to setup the thread in the block. - Index stride_h; - /// The strides to increment the pointer. - Index inc_h, inc_advance; - /// The column offset to compute the predicate for the columns. - Index predicate_offset; - /// The strides to increment the predicate offset. - Index predicate_inc_h, predicate_inc_advance; - - /// Setup the params. - CUTLASS_HOST_DEVICE int initialize( - Pointer pointer, Index ld, Index n, Index epilogue_stride_w, Index epilogue_delta_w) { - // The pointer. - this->pointer = pointer; - // Setup the base stride. One "group of threads" per column. - stride_h = ld; - // Each thread output 1 column per iteration. . - inc_h = ld * TileTraits_::Threads::kH; - inc_advance = inc_h + epilogue_stride_w; - - predicate_offset = n; - predicate_inc_h = TileTraits_::Threads::kH; - predicate_inc_advance = predicate_inc_h + epilogue_delta_w; - - // It worked. - return 0; - } - }; - - Params params; - - Coord<4> thread_offset; - - /// Ctor. - CUTLASS_DEVICE WmmaGemmGlobalIteratorCd() {} - - /// Ctor. - CUTLASS_DEVICE WmmaGemmGlobalIteratorCd(Params const& params, - const Coord<3>& bounds, - const Coord<3>& block, - int const pointer_offset = 0, - int const pred_offset = 0, - ThreadOffset thread_offset_func = ThreadOffset()) - - : params(params) { - thread_offset = thread_offset_func(); - // Each warp works on a different column of the tile. - int const h = thread_offset[1] + block[1]; - // Each lane writes a different element. - int const w = thread_offset[2] + block[2]; - // Setup the pointer. - this->params.pointer += ((h * params.stride_h + w) + pointer_offset); - - // Prepare the vector of predicates. - for (int i = 0; i < Base::Iterations::kW; ++i) { - predicates.set(i, w + i * Base::Delta::kW < bounds[2]); - } - this->params.predicate_offset -= (h + pred_offset); - } - - /// The accessor. - CUTLASS_DEVICE void get(typename Base::AccessType& value, int d, int h, int w, int c) const { - int const imm = - ComputeOffsetFromStrides<typename Base::ImmediateOffsetStrides>::get(0, 0, w, c); - Load<Scalar, TileTraits_::kAccessSize, MemorySpace::kGlobal>::load(value, params.pointer, imm); - } - - /// Increment the pointer in the C dimension. - CUTLASS_DEVICE void inc_c() {} - /// Increment the pointer in the W dimension. - CUTLASS_DEVICE void inc_w() {} - /// Increment the pointer in the H dimension. - CUTLASS_DEVICE void inc_h() { - params.pointer += params.inc_h; - params.predicate_offset -= params.predicate_inc_h; - } - /// Increment the pointer in the D dimension. - CUTLASS_DEVICE void inc_d() {} - /// Increment the pointer to move to the next iteration. - CUTLASS_DEVICE void inc_advance() { - params.pointer += params.inc_advance; - params.predicate_offset -= params.predicate_inc_advance; - } - - /// The accessor. - CUTLASS_DEVICE void set(typename Base::AccessType const& value, int d, int h, int w, int c) { - int const imm = - ComputeOffsetFromStrides<typename Base::ImmediateOffsetStrides>::get(d, h, w, 0); - Store<Scalar, TileTraits_::kAccessSize, MemorySpace::kGlobal>::store( - value, params.pointer, imm); - } - - /// Test the predicate. - CUTLASS_DEVICE bool valid(int d, int h, int w, int c) const { - return predicates.at(w) && params.predicate_offset > 0; - } - - /// The predicates for the row. - cutlass::PredicateVector<Base::Iterations::kW> predicates; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass diff --git a/cutlass-example/cutlass/gemm/wmma_gemm_multiply_add.h b/cutlass-example/cutlass/gemm/wmma_gemm_multiply_add.h deleted file mode 100644 index 5968350..0000000 --- a/cutlass-example/cutlass/gemm/wmma_gemm_multiply_add.h +++ /dev/null @@ -1,108 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Implements warp-level matrix multiply-accumulate operation using CUDA WMMA API. -*/ -#pragma once - -#include <cutlass/wmma_matrix.h> -#ifdef CUTLASS_USE_WMMA_API -#include <cutlass/fragment.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <MatrixLayout::Kind kLayoutA_, - typename ScalarA_, - MatrixLayout::Kind kLayoutB_, - typename ScalarB_, - MatrixLayout::Kind kLayoutC_, - typename ScalarC_, - typename AccumulatorsPerWarp_, - typename InstructionShape_> -struct WmmaGemmMultiplyAdd { - /// The shape of the instruction. - typedef InstructionShape_ InstructionShape; - /// The number of threads per warp. That's a dummy configuration. - typedef Shape<1, InstructionShape_::kH, InstructionShape_::kW> ThreadsPerWarp; - /// The dimensions. - typedef AccumulatorsPerWarp_ AccumulatorsPerWarp; - /// The type for A. - typedef ScalarA_ ScalarA; - /// The type for B. - typedef ScalarB_ ScalarB; - /// The type for C and D. - typedef ScalarC_ ScalarC; - /// The number of iterations. - typedef typename ShapeDiv<AccumulatorsPerWarp, InstructionShape>::Shape Iterations; - - /// The element for A. - typedef WmmaMatrix<GemmOperand::kA, kLayoutA_, ScalarA, InstructionShape> ElementA; - /// The fragment for A. - typedef Fragment<ElementA, Iterations::kW> FragmentA; - - /// The element for B. - typedef WmmaMatrix<GemmOperand::kB, kLayoutB_, ScalarB, InstructionShape> ElementB; - /// The fragment for B. - typedef Fragment<ElementB, Iterations::kH> FragmentB; - - /// The element for C. - typedef WmmaMatrix<GemmOperand::kC, kLayoutC_, ScalarC, InstructionShape> ElementC; - /// The fragment for C. - typedef Fragment<ElementC, Iterations::kH * Iterations::kW> Accumulators; - - /// Ctor. - CUTLASS_DEVICE WmmaGemmMultiplyAdd() {} - - /// Multiply : d = a*b. - CUTLASS_DEVICE void multiply_add(FragmentA const& a, - FragmentB const& b, - Accumulators const& c, - Accumulators& d) { - for (int j = 0; j < Iterations::kH; ++j) { - for (int i = 0; i < Iterations::kW; ++i) { - // The input elements. - ElementA const& elt_a = a[i]; - ElementB const& elt_b = b[j]; - ElementC const& elt_c = c[j * Iterations::kW + i]; - - // The output element. - ElementC& elt_d = d[j * Iterations::kW + i]; - - // The wmma instruction. - nvcuda::wmma::mma_sync(elt_d, elt_a, elt_b, elt_c); - } - } - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass - -#endif // defined CUTLASS_USE_WMMA_API diff --git a/cutlass-example/cutlass/gemm/wmma_gemm_shared_tile.h b/cutlass-example/cutlass/gemm/wmma_gemm_shared_tile.h deleted file mode 100644 index 7d15b26..0000000 --- a/cutlass-example/cutlass/gemm/wmma_gemm_shared_tile.h +++ /dev/null @@ -1,240 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines iterator traits for efficiently loading and storing fragment to and from shared - memory, specialized for WMMA GEMM. -*/ -#pragma once - -#include <cutlass/wmma_matrix.h> -#ifdef CUTLASS_USE_WMMA_API - -#include <cutlass/gemm/gemm_operand.h> -#include <cutlass/reshape_tile.h> - -namespace cutlass { -namespace gemm { - -template <class> -struct Debug {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <MatrixLayout::Kind kLayout_, - typename Scalar_, - typename Tile_, - typename Warps_, - int kWarpStride_, - typename Iterations_, - typename Delta_, - typename WmmaShape_> -struct WmmaGemmSharedLoadTileATraits { - /// The operand. - static GemmOperand::Kind const kOperand = GemmOperand::kA; - /// The layout. - static MatrixLayout::Kind const kLayout = kLayout_; - /// The scalar. - typedef Scalar_ Scalar; - /// The pointer. - typedef Scalar const* Pointer; - /// The access size - static int const kAccessSize = 1; - /// The tile with skew. - typedef Tile_ Tile; - /// The number of warps. - typedef Warps_ Warps; - /// The warps strides. - static int const kWarpStride = kWarpStride_; - /// The number of iterations. - typedef Iterations_ Iterations; - /// The strides between iterations. - typedef Delta_ Delta; - /// The strides between iterations. - typedef Delta_ ImmediateOffsetStrides; - /// The shape of the WMMA instruction. - typedef WmmaShape_ WmmaShape; - /// The memory space. - static MemorySpace::Kind const kMemorySpace = MemorySpace::kShared; - /// ThreadOffset - struct ThreadOffset { - CUTLASS_HOST_DEVICE - Coord<4> operator()() const { - // The warp id. - int const warp = threadIdx.x / kWarpSize; - // The offset. - int const offset = warp % Warps::kW * kWarpStride; - return make_Coord(0, 0, offset, 0); - } - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <MatrixLayout::Kind kLayout_, - typename Scalar_, - typename Tile_, - typename Warps_, - int kWarpStride_, - typename Iterations_, - typename Delta_, - typename WmmaShape_> -struct WmmaGemmSharedLoadTileBTraits { - /// The operand. - static GemmOperand::Kind const kOperand = GemmOperand::kB; - /// The layout. - static MatrixLayout::Kind const kLayout = kLayout_; - /// The scalar. - typedef Scalar_ Scalar; - /// The pointer. - typedef Scalar const* Pointer; - /// The access size - static int const kAccessSize = 1; - /// The tile with skew. - typedef Tile_ Tile; - /// The number of warps. - typedef Warps_ Warps; - /// The warps strides. - static int const kWarpStride = kWarpStride_; - /// The number of iterations. - typedef Iterations_ Iterations; - /// The strides between iterations. - typedef Delta_ Delta; - /// The strides between iterations. - typedef Delta_ ImmediateOffsetStrides; - /// The shape of the WMMA instruction. - typedef WmmaShape_ WmmaShape; - /// The memory space. - static MemorySpace::Kind const kMemorySpace = MemorySpace::kShared; - /// ThreadOffset - struct ThreadOffset { - CUTLASS_HOST_DEVICE - Coord<4> operator()() const { - // The warp id. - int const warp = threadIdx.x / kWarpSize; - // The offset. - int const offset = warp / Warps::kW * kWarpStride; - return make_Coord(0, 0, offset, 0); - } - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <MatrixLayout::Kind kLayout_, - typename Scalar_, - typename OutputTile_, - typename Warps_, - typename WmmaShape_, - int kSkew_ = 0> -struct WmmaGemmSharedStoreTileDTraits { - /// The operand. - static GemmOperand::Kind const kOperand = GemmOperand::kC; - /// The layout. - static MatrixLayout::Kind const kLayout = kLayout_; - /// The scalar. - typedef Scalar_ Scalar; - // The access size - static int const kAccessSize = 1; - /// The pointer. - typedef Scalar* Pointer; - /// The number of warps. - typedef Warps_ Warps; - /// The shape of the WMMA instruction. - typedef WmmaShape_ WmmaShape; - /// The skew. - static int const kSkew = kSkew_; - /// The memory space. - static MemorySpace::Kind const kMemorySpace = MemorySpace::kShared; - /// The tile with skew. - typedef Shape<1, Warps_::kH * WmmaShape_::kH, OutputTile_::kW + kSkew_> Tile; - /// The number of iterations needed to store the tile. - typedef Shape<1, 1, OutputTile_::kW / Warps::kW / WmmaShape_::kW> Iterations; - /// The strides in each dimension between different loads/stores. - typedef Shape<0, 0, Warps::kW * WmmaShape_::kW, 0> Delta; - /// The strides in each dimension between different loads/stores. - typedef Shape<0, 0, Warps::kW * WmmaShape_::kW, 0> ImmediateOffsetStrides; - - /// ThreadOffset - struct ThreadOffset { - CUTLASS_HOST_DEVICE - Coord<4> operator()() const { - // The warp id. - int const warp = threadIdx.x / kWarpSize; - // The starting column. - int const h = warp / Warps::kW * WmmaShape::kH; - // The w. - int const w = warp % Warps::kW * WmmaShape::kW; - // The offset. - int const offset = h * Tile::kW + w; - return make_Coord(0, 0, offset, 0); - } - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, typename Tile_, typename Threads_, int kScalarsPerLds_> -struct WmmaGemmSharedLoadTileDTraits { - /// The scalar. - typedef Scalar_ Scalar; - /// The pointer. - typedef Scalar const* Pointer; - /// The access size - static int const kAccessSize = kScalarsPerLds_; - /// The tile. - typedef typename ReshapeTile<Tile_, kScalarsPerLds_>::Tile Tile; - /// The threads. - typedef typename ReshapeThreads<Tile, Threads_>::Threads Threads; - /// The threads strides. - typedef Shape<1, Tile::kW * Tile::kC, Tile::kC> ThreadsStrides; - /// The memory space. - static MemorySpace::Kind const kMemorySpace = MemorySpace::kShared; - - /// The strides in each dimension between different loads/stores. - typedef Shape<0, Threads::kH * ShapeCount<Tile>::kWc, Threads::kW * kScalarsPerLds_> Delta; - /// The strides in each dimension between different loads/stores. - typedef Shape<0, Threads::kH * ShapeCount<Tile>::kWc, Threads::kW * kScalarsPerLds_> - ImmediateOffsetStrides; - /// The number of iterations needed to load/store the tile. - typedef Shape<1, Tile::kH / Threads::kH, Tile::kW / Threads::kW, Tile::kC / kScalarsPerLds_> - Iterations; - - /// ThreadOffset - struct ThreadOffset { - CUTLASS_HOST_DEVICE - Coord<4> operator()() const { - // The offset. - int const offset = ComputeThreadOffsetFromStrides<Threads, ThreadsStrides>::get(); - return make_Coord(0, 0, offset, 0); - } - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass - -#endif // defined CUTLASS_USE_WMMA_API diff --git a/cutlass-example/cutlass/gemm/wmma_gemm_traits.h b/cutlass-example/cutlass/gemm/wmma_gemm_traits.h deleted file mode 100644 index 7901201..0000000 --- a/cutlass-example/cutlass/gemm/wmma_gemm_traits.h +++ /dev/null @@ -1,574 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defies structural properties of GEMM targeting WMMA API in CUDA. -*/ -#pragma once - -#include <cutlass/wmma_matrix.h> -#ifdef CUTLASS_USE_WMMA_API - -#include <cutlass/convert.h> -#include <cutlass/gemm/gemm.h> -#include <cutlass/gemm/gemm_epilogue.h> -#include <cutlass/gemm/gemm_epilogue_traits.h> -#include <cutlass/gemm/gemm_global_tile.h> -#include <cutlass/gemm/gemm_shared_tile.h> -#include <cutlass/gemm/gemm_traits.h> -#include <cutlass/gemm/wmma_gemm_epilogue_traits.h> -#include <cutlass/gemm/wmma_gemm_global_tile.h> -#include <cutlass/gemm/wmma_gemm_multiply_add.h> - -namespace cutlass { -namespace gemm { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The layout for A. - MatrixLayout::Kind kLayoutA_, - /// The layout for B. - MatrixLayout::Kind kLayoutB_, - /// The tile size for the GEMM KxNxM. - typename OutputTile_, - /// The output type. - typename ScalarC_, - /// The accumulator type. - typename Accumulator_, - /// The number of accumulators per warp. - typename AccumulatorsPerWarp_, - /// The shape of the WMMA instruction. - typename InstructionShape_, - /// The number of scalars per LDG for A. - int kScalarsPerLdgA_, - /// The number of scalars per LDG for B. - int kScalarsPerLdgB_> -struct WmmaGemmConfig : public GemmConfig< - /// The scalar type for A. - half, - /// The scalar type for B. - half, - /// The scalar type for C. - ScalarC_, - /// The scalar type for D. - ScalarC_, - /// The tile size for the GEMM KxNxM. - OutputTile_, - /// The functor to do the math in the main loop. - WmmaGemmMultiplyAdd<kLayoutA_, - half, - kLayoutB_, - half, - MatrixLayout::kColumnMajor, - Accumulator_, - AccumulatorsPerWarp_, - InstructionShape_>, - /// The number of scalars per LDG for A. - kScalarsPerLdgA_, - /// The number of scalars per STS for A. - kScalarsPerLdgA_, - /// The number of scalars per LDS for A. - 8, - /// The number of scalars per LDG for B. - kScalarsPerLdgB_, - /// The number of scalars per STS for B. - kScalarsPerLdgB_, - /// The number of scalars per LDS for B. - 8, - /// The number of scalars per LDG for C and STG for D. - 16 / sizeof(ScalarC_), - /// The number of scalars per STS for D. - 16 / sizeof(ScalarC_), - /// The number of scalars per LDS for D. - 16 / sizeof(ScalarC_), - /// The number of stages in shared memory. - 1> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <enum MatrixLayout::Kind kLayout_, typename GemmConfig_> -struct WmmaGemmTileTraitsHelperA {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_> -struct WmmaGemmTileTraitsHelperA<MatrixLayout::kColumnMajor, GemmConfig_> - : public GemmTileTraitsHelperA<MatrixLayout::kColumnMajor, GemmConfig_> { - /// The base config. - typedef GemmTileTraitsHelperA<MatrixLayout::kColumnMajor, GemmConfig_> Base; - - /// The skew. - static int const kSkew = 16 / sizeof(typename Base::MultiplyAddScalar); - /// The shared tile size. - typedef Shape<GemmConfig_::kStages, - GemmConfig_::OutputTile::kD, - GemmConfig_::OutputTile::kW + kSkew> - Tile; - - /// WMMA matrix - typedef WmmaMatrix<GemmOperand::kA, - MatrixLayout::kColumnMajor, - typename Base::MultiplyAddScalar, - typename GemmConfig_::InstructionShape> - WmmaMatrix; - - /// The traits class to build the iterator to store data to shared memory for A^N. - typedef GemmSharedStoreTileAbTraits< - // The pointer. - typename Base::MultiplyAddScalar, - // The tile has size KxM in GEMM's terminology. - Tile, - // The threads are distributed as warps x 32 (the traits may reorganize). - typename Base::GlobalTileTraits::Threads, - // The number of scalars per STS (STS.32 or STS.128, etc). - GemmConfig_::kScalarsPerStsA> - SharedStoreTileTraits; - - /// The number of elements loaded in one LDG. - static int const kScalarsPerW = GemmConfig_::InstructionShape::kW * GemmConfig_::Warps::kW; - /// The number of scalars loaded per iteration. - static int const kScalarsPerIteration = Tile::kW * GemmConfig_::InstructionShape::kD; - /// The traits class to build the iterator to load from shared memory for A. - typedef WmmaGemmSharedLoadTileATraits< - // The layout of the matrix. - MatrixLayout::kColumnMajor, - // The pointer. - typename Base::MultiplyAddScalar, - // The output tile size. - Tile, - // The number of warps. - typename GemmConfig_::Warps, - // The strides between warps. - GemmConfig_::InstructionShape::kW, - // The number of iterations to load the data. - Shape<1, 1, GemmConfig_::OutputTile::kW / kScalarsPerW>, - // The stride between iterations. - Shape<kScalarsPerIteration, 0, kScalarsPerW, 0>, - // The shape of the instruction. - typename GemmConfig_::InstructionShape> - SharedLoadTileTraits; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_> -struct WmmaGemmTileTraitsHelperA<MatrixLayout::kRowMajor, GemmConfig_> { - /// The layout. - static MatrixLayout::Kind const kLayout = MatrixLayout::kRowMajor; - - /// The input scalar. - typedef typename GemmConfig_::ScalarA Scalar; - /// The scalar stored in shared memory. - typedef typename GemmConfig_::MultiplyAdd::ScalarA MultiplyAddScalar; - - /// WMMA matrix - typedef WmmaMatrix<GemmOperand::kA, - MatrixLayout::kRowMajor, - MultiplyAddScalar, - typename GemmConfig_::InstructionShape> - WmmaMatrix; - - /// The traits class to build the iterator to load data from global memory for A^T. - typedef GemmGlobalTileTraits< - // That's A. - GemmOperand::kA, - // A is row-major. - MatrixLayout::kRowMajor, - // The pointer is float const. - Scalar const, - // The tile has size KxM in GEMM's terminology. - Shape<1, GemmConfig_::OutputTile::kW, GemmConfig_::OutputTile::kD>, - // The threads are distributed as warps x 32 (the traits may reorganize). - Shape<1, GemmConfig_::kThreads / GemmConfig_::OutputTile::kD, GemmConfig_::OutputTile::kD>, - // The number of scalars per LDG (LDG.32 or LDG.128, etc). - GemmConfig_::kScalarsPerLdgA> - GlobalTileTraits; - - /// The skew. - static int const kSkew = 16 / sizeof(MultiplyAddScalar); - /// The tile. - typedef Shape<GemmConfig_::kStages, - GemmConfig_::OutputTile::kW, - GemmConfig_::OutputTile::kD + kSkew> - Tile; - - /// The traits class to build the iterator to store data to shared memory for A^N. - typedef GemmSharedStoreTileAbTraits< - // The pointer. - MultiplyAddScalar, - // The tile has size KxM in GEMM's terminology. - Tile, - // The threads are distributed as warps x 32 (the traits may reorganize). - typename GlobalTileTraits::Threads, - // The number of scalars per STS (STS.32 or STS.128, etc). - GemmConfig_::kScalarsPerStsA> - SharedStoreTileTraits; - - /// The number of elements loaded in one LDG. - static int const kScalarsPerW = GemmConfig_::InstructionShape::kW * GemmConfig_::Warps::kW; - /// The traits class to build the iterator to load from shared memory for A. - typedef WmmaGemmSharedLoadTileATraits< - // The layout of the matrix. - MatrixLayout::kRowMajor, - // The pointer. - MultiplyAddScalar, - // The tile in shared memory. - Tile, - // The number of warps. - typename GemmConfig_::Warps, - // The strides between warps. - GemmConfig_::InstructionShape::kW * Tile::kW, - // The number of iterations to load the data. - Shape<1, 1, GemmConfig_::OutputTile::kW / kScalarsPerW>, - // The stride between iterations. - Shape<GemmConfig_::InstructionShape::kD, 0, kScalarsPerW * Tile::kW>, - // The shape of the instruction. - typename GemmConfig_::InstructionShape> - SharedLoadTileTraits; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <enum MatrixLayout::Kind kLayout_, typename GemmConfig_> -struct WmmaGemmTileTraitsHelperB {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_> -struct WmmaGemmTileTraitsHelperB<MatrixLayout::kRowMajor, GemmConfig_> - : public GemmTileTraitsHelperB<MatrixLayout::kRowMajor, GemmConfig_> { - /// The base config. - typedef GemmTileTraitsHelperB<MatrixLayout::kRowMajor, GemmConfig_> Base; - - /// The skew. - static int const kSkew = 16 / sizeof(typename Base::MultiplyAddScalar); - /// The shared tile size. - typedef Shape<GemmConfig_::kStages, - GemmConfig_::OutputTile::kD, - GemmConfig_::OutputTile::kH + kSkew> - Tile; - - /// WMMA matrix - typedef WmmaMatrix<GemmOperand::kB, - MatrixLayout::kRowMajor, - typename Base::MultiplyAddScalar, - typename GemmConfig_::InstructionShape> - WmmaMatrix; - - /// The traits class to build the iterator to store data to shared memory for B^T. - typedef GemmSharedStoreTileAbTraits< - // The pointer. - typename Base::MultiplyAddScalar, - // The tile has size KxM in GEMM's terminology. - Tile, - // The threads are distributed as warps x 32 (the traits may reorganize). - typename Base::GlobalTileTraits::Threads, - // The number of scalars per STS (STS.32 or STS.128, etc). - GemmConfig_::kScalarsPerStsB> - SharedStoreTileTraits; - - /// The number of elements loaded in one LDG. - static int const kScalarsPerW = GemmConfig_::InstructionShape::kH * GemmConfig_::Warps::kH; - /// The number of scalars loaded per iteration. - static int const kScalarsPerIteration = Tile::kW * GemmConfig_::InstructionShape::kD; - /// The traits class to build the iterator to load from shared memory for B. - typedef WmmaGemmSharedLoadTileBTraits< - // The layout of the matrix. - MatrixLayout::kRowMajor, - // The pointer. - typename Base::MultiplyAddScalar, - // The output tile size. - Tile, - // The number of warps. - typename GemmConfig_::Warps, - // The strides between warps. - GemmConfig_::InstructionShape::kH, - // The number of iterations to load the data. - Shape<1, 1, GemmConfig_::OutputTile::kH / kScalarsPerW>, - // The stride between iterations. - Shape<kScalarsPerIteration, 0, kScalarsPerW, 0>, - // The shape of the instruction. - typename GemmConfig_::InstructionShape> - SharedLoadTileTraits; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmConfig_> -struct WmmaGemmTileTraitsHelperB<MatrixLayout::kColumnMajor, GemmConfig_> { - /// The layout. - static MatrixLayout::Kind const kLayout = MatrixLayout::kColumnMajor; - - /// The input scalar. - typedef typename GemmConfig_::ScalarB Scalar; - /// The scalar stored in shared memory. - typedef typename GemmConfig_::MultiplyAdd::ScalarB MultiplyAddScalar; - - /// WMMA matrix - typedef WmmaMatrix<GemmOperand::kB, - MatrixLayout::kColumnMajor, - MultiplyAddScalar, - typename GemmConfig_::InstructionShape> - WmmaMatrix; - - /// The traits class to build the iterator to load data from global memory for B^N. - typedef GemmGlobalTileTraits< - // That's B. - GemmOperand::kB, - // A is row-major. - MatrixLayout::kColumnMajor, - // The pointer is float const. - Scalar const, - // The tile has size KxM in GEMM's terminology. - Shape<1, GemmConfig_::OutputTile::kH, GemmConfig_::OutputTile::kD>, - // The threads are distributed as warps x 32 (the traits may reorganize). - Shape<1, GemmConfig_::kThreads / GemmConfig_::OutputTile::kD, GemmConfig_::OutputTile::kD>, - // The number of scalars per LDG (LDG.32 or LDG.128, etc). - GemmConfig_::kScalarsPerLdgB> - GlobalTileTraits; - - /// The skew. - static int const kSkew = 16 / sizeof(MultiplyAddScalar); - /// The tile. - typedef Shape<GemmConfig_::kStages, - GemmConfig_::OutputTile::kH, - GemmConfig_::OutputTile::kD + kSkew> - Tile; - - /// The traits class to build the iterator to store data to shared memory for B^N. - typedef GemmSharedStoreTileAbTraits< - // The pointer. - MultiplyAddScalar, - // The tile has size KxM in GEMM's terminology. - Tile, - // The threads are distributed as warps x 32 (the traits may reorganize). - typename GlobalTileTraits::Threads, - // The number of scalars per STS (STS.32 or STS.128, etc). - GemmConfig_::kScalarsPerStsB> - SharedStoreTileTraits; - - /// The number of elements loaded in one LDG. - static int const kScalarsPerW = GemmConfig_::InstructionShape::kH * GemmConfig_::Warps::kH; - /// The traits class to build the iterator to load from shared memory for B. - typedef WmmaGemmSharedLoadTileBTraits< - // The layout of the matrix. - MatrixLayout::kColumnMajor, - // The pointer. - MultiplyAddScalar, - // The tile in shared memory. - Tile, - // The number of warps. - typename GemmConfig_::Warps, - // The strides between warps. - GemmConfig_::InstructionShape::kH * Tile::kW, - // The number of iterations to load the data. - Shape<1, 1, GemmConfig_::OutputTile::kH / kScalarsPerW>, - // The stride between iterations. - Shape<GemmConfig_::InstructionShape::kD, 0, kScalarsPerW * Tile::kW>, - // The shape of the instruction. - typename GemmConfig_::InstructionShape> - SharedLoadTileTraits; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The layout for A. - MatrixLayout::Kind kLayoutA_, - /// The layout for B. - MatrixLayout::Kind kLayoutB_, - /// The output tile. - typename OutputTile_, - /// The output type. - typename ScalarC_, - /// The accumulator type. - typename Accumulator_, - /// The functor to do the math in the epilogue. - typename EpilogueFunctor_, - /// The number of accumulators per warp. - typename AccumulatorsPerWarp_, - /// The shape of the WMMA instruction. - typename InstructionShape_, - /// The number of halfs loaded in one LDG for A. - int kScalarsPerLdgA_, - /// The number of halfs loaded in one LDG for B. - int kScalarsPerLdgB_, - /// The index. - typename Index_> -struct WmmaGemmTraitsHelper { - /// The WMMA GEMM config. - typedef WmmaGemmConfig<kLayoutA_, - kLayoutB_, - OutputTile_, - ScalarC_, - Accumulator_, - AccumulatorsPerWarp_, - InstructionShape_, - kScalarsPerLdgA_, - kScalarsPerLdgB_> - GemmConfig; - - /// The GEMM config for A. - typedef WmmaGemmTileTraitsHelperA<kLayoutA_, GemmConfig> GemmTileTraitsHelperA; - /// The GEMM config for B. - typedef WmmaGemmTileTraitsHelperB<kLayoutB_, GemmConfig> GemmTileTraitsHelperB; - - /// The iterator to load A from global memory. - typedef GemmGlobalIteratorAb<typename GemmTileTraitsHelperA::GlobalTileTraits, Index_> - GlobalLoadIteratorA; - /// The default transformer for A. - typedef Copy<typename GlobalLoadIteratorA::Fragment> GlobalTransformerA; - /// The iterator to store A to shared memory. - typedef TileStoreIterator<typename GemmTileTraitsHelperA::SharedStoreTileTraits, - typename GemmTileTraitsHelperA::SharedStoreTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedStoreIteratorA; - /// The stream to load A from global memory to shared memory. - typedef GlobalLoadStream<GlobalLoadIteratorA, SharedStoreIteratorA, GlobalTransformerA> - GlobalLoadStreamA; - - /// The iterator to load B from global memory. - typedef GemmGlobalIteratorAb<typename GemmTileTraitsHelperB::GlobalTileTraits, Index_> - GlobalLoadIteratorB; - // The default transformer for B. - typedef Copy<typename GlobalLoadIteratorB::Fragment> GlobalTransformerB; - /// The iterator to store B to shared memory. - typedef TileStoreIterator<typename GemmTileTraitsHelperB::SharedStoreTileTraits, - typename GemmTileTraitsHelperB::SharedStoreTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared> - SharedStoreIteratorB; - /// The stream to load B from global memory to shared memory. - typedef GlobalLoadStream<GlobalLoadIteratorB, SharedStoreIteratorB, GlobalTransformerB> - GlobalLoadStreamB; - - /// The iterator to load A from shared memory. - typedef TileLoadIterator<typename GemmTileTraitsHelperA::SharedLoadTileTraits, - typename GemmTileTraitsHelperA::SharedLoadTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared, - Index_, - typename GemmTileTraitsHelperA::WmmaMatrix, - IteratorFragment::kWmmaMatrix> - SharedLoadIteratorA; - /// The stream to load A from shared memory. - typedef SharedLoadStream<SharedLoadIteratorA> SharedLoadStreamA; - /// The iterator to load B from shared memory. - typedef TileLoadIterator<typename GemmTileTraitsHelperB::SharedLoadTileTraits, - typename GemmTileTraitsHelperB::SharedLoadTileTraits::Scalar, - IteratorAdvance::kH, - MemorySpace::kShared, - Index_, - typename GemmTileTraitsHelperB::WmmaMatrix, - IteratorFragment::kWmmaMatrix> - SharedLoadIteratorB; - /// The stream to load B from shared memory. - typedef SharedLoadStream<SharedLoadIteratorB> SharedLoadStreamB; - - /// The functor to do the multiply-add in the main loop. - typedef typename GemmConfig::MultiplyAdd MultiplyAdd; - /// The object to clear accumulators. - typedef ClearAccumulators<typename MultiplyAdd::ScalarC> ClearAccumulators; - - /// The helper to create the epilogue traits. - typedef WmmaGemmEpilogueTraitsHelper<GemmConfig, EpilogueFunctor_, Index_> EpilogueTraitsHelper; - /// The traits class for the epilogue. - typedef SimplifiedGemmEpilogueTraits<GemmConfig, EpilogueFunctor_, Index_, EpilogueTraitsHelper> - GemmEpilogueTraits; - /// The epilogue. - typedef GemmEpilogue<GemmEpilogueTraits> Epilogue; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename OutputTile_, typename DefaultShape_ = Shape<64, 32, 64> > -struct WmmaGemmAccumulatorsPerWarp { - typedef typename ShapeMin<OutputTile_, DefaultShape_>::Shape Shape; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template < - /// The layout for A. - MatrixLayout::Kind kLayoutA_, - /// The layout for B. - MatrixLayout::Kind kLayoutB_, - /// The tile size for the GEMM KxNxM. - typename OutputTile_ = Shape<64, 128, 128>, - /// The output type. - typename ScalarC_ = float, - /// The functor to do the math in the epilogue. - typename EpilogueFunctor_ = LinearScaling<ScalarC_>, - /// The accumulator type. - typename Accumulator_ = ScalarC_, - /// The number of accumulators per warp. - typename AccumulatorsPerWarp_ = typename WmmaGemmAccumulatorsPerWarp<OutputTile_>::Shape, - /// The shape of the WMMA instruction. - typename InstructionShape_ = Shape<16, 16, 16>, - /// The number of scalars per LDG for A. - int kScalarsPerLdgA_ = 8, - /// The number of scalars per LDG for B. - int kScalarsPerLdgB_ = 8, - /// The index. - typename Index_ = int, - /// The helper class. - typename Helper_ = WmmaGemmTraitsHelper<kLayoutA_, - kLayoutB_, - OutputTile_, - ScalarC_, - Accumulator_, - EpilogueFunctor_, - AccumulatorsPerWarp_, - InstructionShape_, - kScalarsPerLdgA_, - kScalarsPerLdgB_, - Index_> > -struct WmmaGemmTraits : public GemmTraits< - // The config. - typename Helper_::GemmConfig, - // The stream to load A from global memory to shared memory. - typename Helper_::GlobalLoadStreamA, - // The stream to load B from global memory to shared memory. - typename Helper_::GlobalLoadStreamB, - // The stream to load A from shared memory. - typename Helper_::SharedLoadStreamA, - // The stream to load B from shared memory. - typename Helper_::SharedLoadStreamB, - // The epilogue. - typename Helper_::Epilogue, - // The block swizzle to reorganize the grid. - IdentityBlockSwizzle, - // The index. - Index_, - // The tool used to clear accumulators. - typename Helper_::ClearAccumulators> {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace gemm -} // namespace cutlass - -#endif // defined CUTLASS_USE_WMMA_API diff --git a/cutlass-example/cutlass/iterator_access.h b/cutlass-example/cutlass/iterator_access.h deleted file mode 100644 index e94beb7..0000000 --- a/cutlass-example/cutlass/iterator_access.h +++ /dev/null @@ -1,318 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Free functions for loading and storing to implementations of tile iteartor concepts. -*/ -#pragma once - -#include <cutlass/fragment_load_store.h> -#include <cutlass/load_store.h> -#include <cutlass/predicate_vector.h> -#include <cutlass/shape.h> - -namespace cutlass { - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Loads a fragment from an input iterator -template <typename InputIterator, typename Fragment> -CUTLASS_HOST_DEVICE void iterator_load(InputIterator &iterator, Fragment &fragment) { - typename InputIterator::FragmentIterator frag_iterator(fragment); - for (int d = 0; d < InputIterator::Iterations::kD; ++d) { - for (int h = 0; h < InputIterator::Iterations::kH; ++h) { - for (int w = 0; w < InputIterator::Iterations::kW; ++w) { - for (int c = 0; c < InputIterator::Iterations::kC; ++c) { - if (iterator.valid(d, h, w, c)) { - iterator.get(reinterpret_cast<typename InputIterator::AccessType &>( - frag_iterator.at(d, h, w, c)), - d, - h, - w, - c); - } - } - if (w < InputIterator::Iterations::kW - 1) { - iterator.inc_w(); - } - } - if (h < InputIterator::Iterations::kH - 1) { - iterator.inc_h(); - } - } - if (d < InputIterator::Iterations::kD - 1) { - iterator.inc_d(); - } - } - iterator.inc_advance(); -} - -/// Loads a fragment from a shared memory input iterator -template <typename InputIterator, typename Fragment> -CUTLASS_DEVICE void shared_iterator_load(InputIterator &iterator, Fragment &fragment) { - typename InputIterator::FragmentIterator frag_iterator(fragment); - for (int d = 0; d < InputIterator::Iterations::kD; ++d) { - for (int h = 0; h < InputIterator::Iterations::kH; ++h) { - for (int w = 0; w < InputIterator::Iterations::kW; ++w) { - for (int c = 0; c < InputIterator::Iterations::kC; ++c) { - int const offset = - ComputeOffsetFromStrides<typename InputIterator::ImmediateOffsetStrides>::get( - d, h, w, c); - - FragmentLoad<InputIterator::kIteratorFragment, - InputIterator::Tile::kC, - typename InputIterator::Scalar, - InputIterator::kMemorySpace, - typename InputIterator::FragmentElement, - InputIterator::Tile::kW>::load(frag_iterator.at(d, h, w, c), - iterator.data(), - offset); - } - } - } - } -} - -/// Loads a fragment from a shared memory input iterator -template <typename InputIterator, typename Fragment> -CUTLASS_DEVICE void shared_iterator_load(InputIterator &iterator, Fragment &fragment, int d) { - typename InputIterator::FragmentIterator frag_iterator(fragment); - for (int h = 0; h < InputIterator::Iterations::kH; ++h) { - for (int w = 0; w < InputIterator::Iterations::kW; ++w) { - for (int c = 0; c < InputIterator::Iterations::kC; ++c) { - int const offset = - ComputeOffsetFromStrides<typename InputIterator::ImmediateOffsetStrides>::get( - d, h, w, c); - - FragmentLoad<InputIterator::kIteratorFragment, - InputIterator::Tile::kC, - typename InputIterator::Scalar, - InputIterator::kMemorySpace, - typename InputIterator::FragmentElement, - InputIterator::Tile::kW>::load(frag_iterator.at(0, h, w, c), - iterator.data(), - offset); - } - } - } -} - -/// Loads a fragment from an input iterator, masked by a predicate iterator -template <typename InputIterator, typename Fragment, typename ConstPredicateAdapter> -CUTLASS_HOST_DEVICE void iterator_load_post_increment(InputIterator &iterator, - Fragment &fragment, - typename InputIterator::Index offset, - ConstPredicateAdapter predicate_adapter) { - for (int d = 0; d < InputIterator::Iterations::kD; ++d, iterator.inc_d()) { - for (int h = 0; h < InputIterator::Iterations::kH; ++h, iterator.inc_h()) { - for (int w = 0; w < InputIterator::Iterations::kW; ++w, iterator.inc_w()) { - if (predicate_adapter.at(d, h, w, 0)) { - int idx = InputIterator::Tile::kC * - (w + InputIterator::Iterations::kW * (h + InputIterator::Iterations::kH * d)); - - Load<typename Fragment::Element, InputIterator::Tile::kC, InputIterator::kMemorySpace>:: - load(reinterpret_cast<typename InputIterator::AccessType &>(fragment[idx]), - iterator.data(), - offset); - } - } - } - } -} - -/// Loads a fragment from an input iterator -template <typename InputIterator, typename Fragment> -CUTLASS_HOST_DEVICE void iterator_load_post_increment(InputIterator &iterator, - Fragment &fragment, - typename InputIterator::Index offset = 0) { - TrivialPredicateTileAdapter pred; - iterator_load_post_increment(iterator, fragment, offset, pred); -} - -/// Loads a fragment from an input iterator -template <typename InputIterator, typename Fragment, typename ConstPredicateAdapter> -CUTLASS_HOST_DEVICE void iterator_load_post_increment(InputIterator &iterator, - Fragment &fragment, - ConstPredicateAdapter pred_it) { - iterator_load_post_increment(iterator, fragment, 0, pred_it); -} - -template <typename InputIterator, typename Fragment, typename ConstPredicateAdapter> -CUTLASS_HOST_DEVICE void iterator_load(InputIterator const &_iterator, - Fragment &fragment, - typename InputIterator::Index offset, - ConstPredicateAdapter predicate_adapter) { - InputIterator iterator(_iterator); - iterator_load_post_increment(iterator, fragment, offset, predicate_adapter); -} - -/// Loads a fragment from an input iterator -template <typename InputIterator, typename Fragment> -CUTLASS_HOST_DEVICE void iterator_load(InputIterator const &iterator, - Fragment &fragment, - typename InputIterator::Index offset = 0) { - TrivialPredicateTileAdapter pred; - iterator_load(iterator, fragment, offset, pred); -} - -/// Loads a fragment from an input iterator -template <typename InputIterator, typename Fragment, typename ConstPredicateAdapter> -CUTLASS_HOST_DEVICE void iterator_load(InputIterator const &iterator, - Fragment &fragment, - ConstPredicateAdapter pred_it) { - iterator_load(iterator, fragment, 0, pred_it); -} - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Stores a fragment to an output iterator -template <typename OutputIterator, typename Fragment> -CUTLASS_HOST_DEVICE void iterator_store(OutputIterator &iterator, Fragment &fragment) { - typename OutputIterator::FragmentIterator frag_iterator(fragment); - for (int d = 0; d < OutputIterator::Iterations::kD; ++d) { - for (int h = 0; h < OutputIterator::Iterations::kH; ++h) { - for (int w = 0; w < OutputIterator::Iterations::kW; ++w) { - if (iterator.valid(d, h, w, 0)) { - iterator.set(reinterpret_cast<typename OutputIterator::AccessType const &>( - frag_iterator.at(d, h, w, 0)), - d, - h, - w, - 0); - } - if (w < OutputIterator::Iterations::kW - 1) { - iterator.inc_w(); - } - } - if (h < OutputIterator::Iterations::kH - 1) { - iterator.inc_h(); - } - } - if (d < OutputIterator::Iterations::kD - 1) { - iterator.inc_d(); - } - } - iterator.inc_advance(); -} - -/// Stores a fragment to a shared memory output iterator -template <typename OutputIterator, typename Fragment> -CUTLASS_DEVICE void shared_iterator_store(OutputIterator &iterator, Fragment const &fragment) { - typename OutputIterator::FragmentConstIterator frag_iterator(fragment); - for (int d = 0; d < OutputIterator::Iterations::kD; ++d) { - for (int h = 0; h < OutputIterator::Iterations::kH; ++h) { - for (int w = 0; w < OutputIterator::Iterations::kW; ++w) { - for (int c = 0; c < OutputIterator::Iterations::kC; ++c) { - int const offset = - ComputeOffsetFromStrides<typename OutputIterator::ImmediateOffsetStrides>::get( - d, h, w, c); - - FragmentStore<OutputIterator::kIteratorFragment, - OutputIterator::Tile::kC, - typename OutputIterator::Scalar, - OutputIterator::kMemorySpace, - typename OutputIterator::FragmentElement, - OutputIterator::Tile::kW>::store(frag_iterator.at(d, h, w, c), - iterator.data(), - offset); - } - } - } - } -} - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Stores a fragment to an output iterator, masked by a predicate iterator -template <typename OutputIterator, typename Fragment, typename ConstPredicateAdapter> -CUTLASS_HOST_DEVICE void iterator_store_post_increment(OutputIterator &iterator, - Fragment const &fragment, - typename OutputIterator::Index offset, - ConstPredicateAdapter predicate_adapter) { - for (int d = 0; d < OutputIterator::Iterations::kD; ++d, iterator.inc_d()) { - for (int h = 0; h < OutputIterator::Iterations::kH; ++h, iterator.inc_h()) { - for (int w = 0; w < OutputIterator::Iterations::kW; ++w, iterator.inc_w()) { - if (predicate_adapter.at(d, h, w, 0)) { - int idx = OutputIterator::Tile::kC * - (w + OutputIterator::Iterations::kW * (h + OutputIterator::Iterations::kH * d)); - - Store<typename Fragment::Element, - OutputIterator::Tile::kC, - OutputIterator::kMemorySpace>:: - store(reinterpret_cast<typename OutputIterator::AccessType const &>(fragment[idx]), - iterator.data(), - offset); - } - } - } - } -} - -/// Stores a fragment to an output iterator -template <typename OutputIterator, typename Fragment> -CUTLASS_HOST_DEVICE void iterator_store_post_increment(OutputIterator &iterator, - Fragment const &fragment, - typename OutputIterator::Index offset = 0) { - TrivialPredicateTileAdapter pred; - iterator_store_post_increment(iterator, fragment, offset, pred); -} - -/// Stores a fragment to an output iterator -template <typename OutputIterator, typename Fragment, typename ConstPredicateAdapter> -CUTLASS_HOST_DEVICE void iterator_store_post_increment(OutputIterator &iterator, - Fragment const &fragment, - ConstPredicateAdapter pred_it) { - iterator_store_post_increment(iterator, fragment, 0, pred_it); -} - -/// Stores a fragment to an output iterator, masked by a predicate iterator -template <typename OutputIterator, typename Fragment, typename ConstPredicateAdapter> -CUTLASS_HOST_DEVICE void iterator_store(OutputIterator const &_iterator, - Fragment const &fragment, - typename OutputIterator::Index offset, - ConstPredicateAdapter predicate_adapter) { - OutputIterator iterator(_iterator); - iterator_store_post_increment(iterator, fragment, offset, predicate_adapter); -} - -/// Stores a fragment to an output iterator -template <typename OutputIterator, typename Fragment> -CUTLASS_HOST_DEVICE void iterator_store(OutputIterator const &iterator, - Fragment const &fragment, - typename OutputIterator::Index offset = 0) { - TrivialPredicateTileAdapter pred; - iterator_store(iterator, fragment, offset, pred); -} - -/// Stores a fragment to an output iterator -template <typename OutputIterator, typename Fragment, typename ConstPredicateAdapter> -CUTLASS_HOST_DEVICE void iterator_store(OutputIterator const &iterator, - Fragment const &fragment, - ConstPredicateAdapter pred_it) { - iterator_store(iterator, fragment, 0, pred_it); -} - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace cutlass diff --git a/cutlass-example/cutlass/load_store.h b/cutlass-example/cutlass/load_store.h deleted file mode 100644 index 5cb5eb6..0000000 --- a/cutlass-example/cutlass/load_store.h +++ /dev/null @@ -1,222 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines abstractions for efficiently loading and storing vectors to memory. -*/ -#pragma once - -#include <cutlass/vector.h> - -namespace cutlass { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/** -* @brief Enum to specify which memory space data resides in. -*/ -struct MemorySpace { - enum Kind { - kGeneric, // Data accessed through pointer dereferencing - kShared, // Data resides in shared memory - kGlobal // Data resides in global memory - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, - int Lanes_, - MemorySpace::Kind Memory_, - bool = (Lanes_ > 1), - size_t = (sizeof(Scalar_) * Lanes_)> -struct Load { - /// The output type. - typedef typename Vectorize<Scalar_, Lanes_>::Type AccessType; - - /// The load function. - static CUTLASS_DEVICE void load(AccessType& dst, Scalar_ const* pointer, int offset) { - dst = reinterpret_cast<AccessType const*>(&pointer[offset])[0]; - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, int Lanes_, MemorySpace::Kind Memory_> -struct Load<Scalar_, Lanes_, Memory_, true, 4> { - /// The output type. - typedef typename Vectorize<Scalar_, Lanes_>::Type AccessType; - - /// The store function. - static CUTLASS_DEVICE void load(AccessType& dst, Scalar_ const* pointer, int offset) { - dst.registers[0] = reinterpret_cast<uint32_t const*>(&pointer[offset])[0]; - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, int Lanes_, MemorySpace::Kind Memory_> -struct Load<Scalar_, Lanes_, Memory_, true, 8> { - /// The output type. - typedef typename Vectorize<Scalar_, Lanes_>::Type AccessType; - - /// The store function. - static CUTLASS_DEVICE void load(AccessType& dst, Scalar_ const* pointer, int offset) { - uint2 tmp = reinterpret_cast<uint2 const*>(&pointer[offset])[0]; - dst.registers[0] = tmp.x; - dst.registers[1] = tmp.y; - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <MemorySpace::Kind Memory_> -struct Load<double, 2, Memory_, true, 16> { - /// The output type. - typedef typename Vectorize<double, 2>::Type AccessType; - - /// The store function. - static CUTLASS_DEVICE void load(AccessType& dst, double const* pointer, int offset) { - double2 tmp = reinterpret_cast<double2 const*>(&pointer[offset])[0]; - dst[0] = tmp.x; - dst[1] = tmp.y; - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -#if defined(__CUDACC_VERSION_MAJOR) && __CUDACC_VERSION_MAJOR < 10 -// WAR bug in NVCC where the upper and lower half of the register end up being the same -template <MemorySpace::Kind Memory_> -struct Load<half, 8, Memory_, true, 16> { - /// The output type. - typedef typename Vectorize<half, 8>::Type AccessType; - - /// The store function. - static CUTLASS_DEVICE void load(AccessType& dst, half const* pointer, int offset) { - int2 tmp = reinterpret_cast<int2 const*>(&pointer[offset])[0]; - dst.registers[0] = tmp.x; - dst.registers[1] = tmp.y; - - tmp = reinterpret_cast<int2 const*>(&pointer[offset + 4])[0]; - dst.registers[2] = tmp.x; - dst.registers[3] = tmp.y; - } -}; - -#endif - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, int Lanes_, MemorySpace::Kind Memory_> -struct Load<Scalar_, Lanes_, Memory_, true, 16> { - /// The output type. - typedef typename Vectorize<Scalar_, Lanes_>::Type AccessType; - - /// The store function. - static CUTLASS_DEVICE void load(AccessType& dst, Scalar_ const* pointer, int offset) { - uint4 tmp = reinterpret_cast<uint4 const*>(&pointer[offset])[0]; - dst.registers[0] = tmp.x; - dst.registers[1] = tmp.y; - dst.registers[2] = tmp.z; - dst.registers[3] = tmp.w; - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, - int Lanes_, - MemorySpace::Kind Memory_, - bool = (Lanes_ > 1), - size_t = (sizeof(Scalar_) * Lanes_)> -struct Store { - /// The output type. - typedef typename Vectorize<Scalar_, Lanes_>::Type AccessType; - - /// The store function. - static CUTLASS_DEVICE void store(AccessType const& src, Scalar_* pointer, int offset) { - pointer[offset] = src; - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, int Lanes_, MemorySpace::Kind Memory_> -struct Store<Scalar_, Lanes_, Memory_, true, 4> { - /// The output type. - typedef typename Vectorize<Scalar_, Lanes_>::Type AccessType; - - /// The store function. - static CUTLASS_DEVICE void store(AccessType const& src, Scalar_* pointer, int offset) { - uint32_t* addr = reinterpret_cast<uint32_t*>(&pointer[offset]); - addr[0] = src.registers[0]; - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, int Lanes_, MemorySpace::Kind Memory_> -struct Store<Scalar_, Lanes_, Memory_, true, 8> { - /// The output type. - typedef typename Vectorize<Scalar_, Lanes_>::Type AccessType; - - /// The store function. - static CUTLASS_DEVICE void store(AccessType const& src, Scalar_* pointer, int offset) { - uint2* addr = reinterpret_cast<uint2*>(&pointer[offset]); - addr[0] = make_uint2(src.registers[0], src.registers[1]); - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <MemorySpace::Kind Memory_> -struct Store<double, 2, Memory_, true, 16> { - /// The output type. - typedef typename Vectorize<double, 2>::Type AccessType; - - /// The store function. - static CUTLASS_DEVICE void store(AccessType const& src, double* pointer, int offset) { - double2* addr = reinterpret_cast<double2*>(&pointer[offset]); - addr[0] = make_double2(src[0], src[1]); - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, int Lanes_, MemorySpace::Kind Memory_> -struct Store<Scalar_, Lanes_, Memory_, true, 16> { - /// The output type. - typedef typename Vectorize<Scalar_, Lanes_>::Type AccessType; - - /// The store function. - static CUTLASS_DEVICE void store(AccessType const& src, Scalar_* pointer, int offset) { - uint4* addr = reinterpret_cast<uint4*>(&pointer[offset]); - addr[0] = make_uint4(src.registers[0], src.registers[1], src.registers[2], src.registers[3]); - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace cutlass diff --git a/cutlass-example/cutlass/matrix_traits.h b/cutlass-example/cutlass/matrix_traits.h deleted file mode 100644 index 77e8b70..0000000 --- a/cutlass-example/cutlass/matrix_traits.h +++ /dev/null @@ -1,48 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines properties of matrices used to denote layout and operands to GEMM kernels. -*/ -#pragma once - -namespace cutlass { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Describes layouts of matrices -struct MatrixLayout { - enum Kind { kRowMajor, kColumnMajor }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Gemm operand - D = A * B + C -struct GemmOperand { - enum Kind { kA, kB, kC, kD }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace cutlass diff --git a/cutlass-example/cutlass/predicate_vector.h b/cutlass-example/cutlass/predicate_vector.h deleted file mode 100644 index 8166857..0000000 --- a/cutlass-example/cutlass/predicate_vector.h +++ /dev/null @@ -1,493 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines container classes and iterators for managing a statically sized vector - of boolean predicates. -*/ -#pragma once - -#include <stdint.h> - -#include <cutlass/cutlass.h> -#include <cutlass/shape.h> - -#include <cutlass/util/platform.h> - -namespace cutlass { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/*!@defgroup predicate_vector_concept Predicate Vector Concept -@{ - -Implementations of \ref predicate_vector_concept contain an ordered set of boolean predicates which -may be used as conditionals in other device-side operations. Both random access and iterators -offering sequential access are provided. - -@par Predicate Vector - A \ref predicate_vector_concept satisfies the following expressions - - <b>at(int idx)</b> - returns the value of the indexed predicate - - <b>set(int idx, bool value)</b> - sets the value of the indexed predicate - - <b>begin()</b> - returns a \ref predicate_iterator_concept pointing to the first predicate - -@} -*/ - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/*!@defgroup predicate_iterator_concept Predicate Iterator Concept -@{ - -Implementations of \ref predicate_iterator_concept enables accessing and traversing elements of a -bit vector. - -@par Const Predicate Iterator - A const \ref predicate_iterator_concept satisfies the following expressions - - <b>++it</b> increments the iterator to the next predicate - - <b>*it</b> returns the value of the currently pointed-to predicate - -@par Mutable Predicate Iterator - A \ref predicate_iterator_concept that is non-const <b>also</b> satisfies the following expressions - - <b>it.set(bool value)</b> sets the value of the currently pointed-to predicate - -@} -*/ - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/*!@defgroup predicate_tile_adapter Predicate Tile Adapter Concept -@{ - -Implementations of \ref predicate_tile_adapter provide a mapping between a the elements of a \ref -tile_traits_concept and a \ref predicate_vector_concept. - -@par Predicate Tile Adapter - A \ref predicate_tile_adapter satisfies the following expressions - - <b>at(int d, int h, int w, int c)</b> - returns the value of a predicate corresponding to the - access (d, h, w, c) within the tile. - -@} -*/ - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Statically sized array of bits implementing @concept{predicate_vector_concept}. -template < - /// Number of predicates conatined in predicate vector - int kPredicates_, - /// Number of predicates contained in each byte of internal storage - int kPredicatesPerByte_ = 4, - /// Location of first predicate within byte of internal storage - int kPredicateStart_ = 0> -struct PredicateVector { - /// Number of bits stored by the PredicateVector - static int const kPredicates = kPredicates_; - - /// Number of bits stored within each byte of the predicate bit vector - static int const kPredicatesPerByte = kPredicatesPerByte_; - - /// First bit withing each byte containing predicates - static int const kPredicateStart = kPredicateStart_; - - // Make sure no one tries to put more than 8 bits in a byte :) - static_assert(kPredicatesPerByte <= 8, "kPredicatesPerByte must fit within an actual byte"); - // Make sure the "offsetted" bits fit in one byte. - static_assert(kPredicateStart + kPredicatesPerByte < 8, - "The offsetted predicates must fit within an actual byte."); - - /// Storage type of individual elements - typedef uint32_t Storage; - - /// Number of bytes needed - static int const kBytes = (kPredicates + kPredicatesPerByte - 1) / kPredicatesPerByte; - - /// Number of storage elements needed - static int const kWordCount = (kBytes + sizeof(Storage) - 1) / sizeof(Storage); - - private: - // - // Data members - // - - /// Words of bit vector - Storage storageData[kWordCount]; - - // - // Methods - // - - /// Computes the word and bit corresponding to a logical predicate index - CUTLASS_HOST_DEVICE void computeStorageOffset(int &word, int &bit, int idx) const { - CUTLASS_ASSERT(idx < kPredicates); - - int byte = (idx / kPredicatesPerByte); - int bit_offset = (idx % kPredicatesPerByte); - - word = byte / sizeof(Storage); - int byte_offset = (byte % sizeof(Storage)); - - bit = byte_offset * 8 + bit_offset + kPredicateStart; - } - - /// Accesses a given word with optional assertions - CUTLASS_HOST_DEVICE Storage &storage(int word) { - CUTLASS_ASSERT(word < kWordCount); - return storageData[word]; - } - - /// Accesses a given word with optional assertions - CUTLASS_HOST_DEVICE Storage const &storage(int word) const { - CUTLASS_ASSERT(word < kWordCount); - return storageData[word]; - } - - public: - // - // Iterator - // - - /** - * @brief A const iterator implementing \ref predicate_iterator_concept enabling sequential - * read-only access to prediactes. - * @concept{predicate_iterator_concept} - */ - class ConstIterator { - /// Reference to PredicateVector instance - PredicateVector const &vec_; - - /// Index into PredicateVector - int bit_; - - public: - /// Copy constructor - CUTLASS_HOST_DEVICE - ConstIterator(ConstIterator const &it) : vec_(it.vec_), bit_(it.bit_) {} - - /// - CUTLASS_HOST_DEVICE - ConstIterator(PredicateVector const &_vec, int _start = 0) : vec_(_vec), bit_(_start) {} - - /// Pre-increment - CUTLASS_HOST_DEVICE - ConstIterator &operator++() { - ++bit_; - return *this; - } - - /// Pre-decrement - CUTLASS_HOST_DEVICE - ConstIterator &operator--() { - --bit_; - return *this; - } - - /// Post-increment - CUTLASS_HOST_DEVICE - ConstIterator operator++(int) { - ConstIterator ret(*this); - ret.bit_++; - return ret; - } - - /// Post-decrement - CUTLASS_HOST_DEVICE - ConstIterator operator--(int) { - ConstIterator ret(*this); - ret.bit_--; - return ret; - } - - /// Returns true if iterators point to the same bit - CUTLASS_HOST_DEVICE - bool operator==(ConstIterator const &it) const { return bit_ == it.bit_; } - - /// Returns false if iterators point to the same bit - CUTLASS_HOST_DEVICE - bool operator!=(ConstIterator const &it) const { return bit_ != it.bit_; } - - /// Dereferences iterator - CUTLASS_HOST_DEVICE - bool operator*() const { return vec_[bit_]; } - }; - - /** - * @brief An iterator implementing \ref predicate_iterator_concept enabling sequential - * read and write access to predicates. - * @concept{predicate_iterator_concept} - */ - class Iterator { - /// Reference to PredicateVector instance - PredicateVector &vec_; - - /// Index into PredicateVector - int bit_; - - public: - /// Copy constructor - CUTLASS_HOST_DEVICE - Iterator(Iterator const &it) : vec_(it.vec_), bit_(it.bit_) {} - - /// Constructs an iterator from a PredicateVector - CUTLASS_HOST_DEVICE - Iterator(PredicateVector &_vec, int _start = 0) : vec_(_vec), bit_(_start) {} - - /// Pre-increment - CUTLASS_HOST_DEVICE - Iterator &operator++() { - ++bit_; - return *this; - } - - /// Pre-decrement - CUTLASS_HOST_DEVICE - Iterator &operator--() { - --bit_; - return *this; - } - - /// Post-increment - CUTLASS_HOST_DEVICE - Iterator operator++(int) { - Iterator ret(*this); - ret.bit_++; - return ret; - } - - /// Post-decrement - CUTLASS_HOST_DEVICE - Iterator operator--(int) { - Iterator ret(*this); - ret.bit_--; - return ret; - } - - /// Returns true if iterators point to the same bit - CUTLASS_HOST_DEVICE - bool operator==(Iterator const &it) const { return bit_ == it.bit_; } - - /// Returns false if iterators point to the same bit - CUTLASS_HOST_DEVICE - bool operator!=(Iterator const &it) const { return bit_ != it.bit_; } - - /// Gets the bit at the pointed to location - CUTLASS_HOST_DEVICE - bool get() { return vec_[bit_]; } - - /// Dereferences iterator - CUTLASS_HOST_DEVICE - bool operator*() const { return vec_[bit_]; } - - /// Sets the bit at the pointed to location - CUTLASS_HOST_DEVICE - void set(bool value = true) { vec_.set(bit_, value); } - }; - - /// Iterator that always returns true - struct TrivialIterator { - /// Constructor - CUTLASS_HOST_DEVICE - TrivialIterator() {} - - /// Copy constructor - CUTLASS_HOST_DEVICE - TrivialIterator(Iterator const &it) {} - - /// Constructs an iterator from a PredicateVector - CUTLASS_HOST_DEVICE - TrivialIterator(PredicateVector const &_vec) {} - - /// Pre-increment - CUTLASS_HOST_DEVICE - TrivialIterator &operator++() { return *this; } - - /// Post-increment - CUTLASS_HOST_DEVICE - TrivialIterator operator++(int) { return *this; } - - /// Dereferences iterator - CUTLASS_HOST_DEVICE - bool operator*() const { return true; } - }; - - public: - // - // Methods - // - - /// Initialize the predicate vector - CUTLASS_HOST_DEVICE PredicateVector(bool value = true) { fill(value); } - - /// Fills all predicates with a given value - CUTLASS_HOST_DEVICE void fill(bool value = true) { - Storage item = (value ? ~Storage(0) : Storage(0)); - - CUTLASS_PRAGMA_UNROLL - for (int i = 0; i < kWordCount; ++i) { - storage(i) = item; - } - } - - /// Accesses a bit within the predicate vector. - CUTLASS_HOST_DEVICE bool operator[](int idx) const { return at(idx); } - - /// Accesses a bit within the predicate vector. - CUTLASS_HOST_DEVICE bool at(int idx) const { - int bit, word; - computeStorageOffset(word, bit, idx); - - return ((storage(word) >> bit) & 1); - } - - /// Set a bit within the predicate vector. - CUTLASS_HOST_DEVICE void set(int idx, bool value = true) { - int bit, word; - computeStorageOffset(word, bit, idx); - - Storage disable_mask = (~(Storage(1) << bit)); - Storage enable_mask = (Storage(value) << bit); - - storage(word) = ((storage(word) & disable_mask) | enable_mask); - } - - /// Computes the intersection of two identical predicate vectors. - CUTLASS_HOST_DEVICE PredicateVector &operator&=(PredicateVector const &predicates) { - CUTLASS_PRAGMA_UNROLL - for (int i = 0; i < kWordCount; ++i) { - storage(i) = (storage(i) & predicates.storage(i)); - } - return *this; - } - - /// Computes the union of two identical predicate vectors. - CUTLASS_HOST_DEVICE PredicateVector &operator|=(PredicateVector const &predicates) { - CUTLASS_PRAGMA_UNROLL - for (int i = 0; i < kWordCount; ++i) { - storage(i) = (storage(i) | predicates.storage(i)); - } - return *this; - } - - /// Returns true if entire predicate array is zero. - CUTLASS_HOST_DEVICE bool is_zero() const { - Storage mask(0); - for (int byte = 0; byte < sizeof(Storage); ++byte) { - Storage byte_mask = (((1 << kPredicatesPerByte) - 1) << kPredicateStart); - mask |= (byte_mask << (byte * 8)); - } - uint32_t result = 0; - for (int word = 0; word < kWordCount; ++word) { - result |= storage(word); - } - return result == 0; - } - - /// Returns an iterator to the start of the bit vector - CUTLASS_DEVICE - Iterator begin() { return Iterator(*this); } - - /// Returns an iterator - CUTLASS_DEVICE - Iterator end() { return Iterator(*this, kPredicates); } - - /// Returns a ConstIterator - CUTLASS_DEVICE - ConstIterator const_begin() const { return ConstIterator(*this); } - - /// Returns a ConstIterator - CUTLASS_DEVICE - ConstIterator const_end() const { return ConstIterator(*this, kPredicates); } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Always returns true predicate. -struct TrivialPredicateTileAdapter { - /// Ctor. - CUTLASS_HOST_DEVICE TrivialPredicateTileAdapter() {} - - /// The value at location (d, h, w, c). - CUTLASS_HOST_DEVICE bool at(int, int, int, int) const { return true; } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Adapter to enable random access to predicates via logical coordinate within a tile. -template <typename PredicateVector_, typename Iterations_> -struct PredicateTileAdapter { - /// The vector of predicates. - typedef PredicateVector_ PredicateVector; - /// The iterations. - typedef Iterations_ Iterations; - - private: - /// The predicates. - PredicateVector &predicates; - - public: - /// Ctor. - CUTLASS_DEVICE PredicateTileAdapter(PredicateVector &predicates_) : predicates(predicates_) {} - - /// Get the value at location (d, h, w, c). - CUTLASS_DEVICE bool at(int d, int h, int w, int c) const { - int const bit = ComputeOffsetFromShape<Iterations>::get(d, h, w, c); - return predicates.at(bit); - } - - /// Set the value at location (d, h, w, c). - CUTLASS_DEVICE void set(int d, int h, int w, int c, bool value) { - int const bit = ComputeOffsetFromShape<Iterations>::get(d, h, w, c); - predicates.set(bit, value); - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Adapter to enable random access to predicates via logical coordinate within a tile. -template <typename PredicateVector_, typename Iterations_> -struct ConstPredicateTileAdapter { - /// The vector of predicates. - typedef PredicateVector_ PredicateVector; - /// The iterations. - typedef Iterations_ Iterations; - - private: - /// The predicates. - PredicateVector const &predicates; - - public: - /// Ctor. - CUTLASS_DEVICE ConstPredicateTileAdapter(PredicateVector const &predicates_) - : predicates(predicates_) {} - - /// Get the value at location (d, h, w, c). - CUTLASS_DEVICE bool at(int d, int h, int w, int c) const { - int const bit = ComputeOffsetFromShape<Iterations>::get(d, h, w, c); - return predicates.at(bit); - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace cutlass diff --git a/cutlass-example/cutlass/reshape_tile.h b/cutlass-example/cutlass/reshape_tile.h deleted file mode 100644 index 55aebfc..0000000 --- a/cutlass-example/cutlass/reshape_tile.h +++ /dev/null @@ -1,58 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines a type for restructuring a tile. -*/ -#pragma once - -#include <cutlass/shape.h> - -namespace cutlass { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -// The following functor reshapes a tile of data. The goal is to have at least kAccessSize in -// the inner-most dimension. If the user respects that constraint, there is nothing to be done. If -// that's not the case, this functor will correct that and "extract" the right number of elements -// from the next dimension. - -template <typename Tile_, int kAccessSize_, bool = (Tile_::kC < kAccessSize_)> -struct ReshapeTile { - typedef Tile_ Tile; -}; - -template <typename Tile_, int kAccessSize_> -struct ReshapeTile<Tile_, kAccessSize_, true> { - // Make sure the W dimension of the tile is large enough. - static_assert(Tile_::kW >= kAccessSize_, "The W dimension is too small"); - // Make sure the dimension can be divided by the number of scalars. - static_assert(Tile_::kW % kAccessSize_ == 0, "Not supported"); - // Collapse the W dimension. - typedef Shape<Tile_::kD, Tile_::kH, Tile_::kW / kAccessSize_, kAccessSize_> Tile; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace cutlass diff --git a/cutlass-example/cutlass/shape.h b/cutlass-example/cutlass/shape.h deleted file mode 100644 index 4f6b222..0000000 --- a/cutlass-example/cutlass/shape.h +++ /dev/null @@ -1,305 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines Shape implementing the Layout concept for representing a 4D hypercube of objects. -*/ -#pragma once - -#include <cutlass/cutlass.h> - -namespace cutlass { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/*!@defgroup layout_concept Layout Concept -* @{ -* @par Implementations of \ref layout_concept are used to describe a cube with DxHxW elements and C -scalars per element. - A HxW slice of a cube is called an image and a cube consists of D images. -* -* @par Notations -* Let Layout be an implementation of the \ref layout_concept. -* -* @par Valid Expressions -* - <b>Layout::D</b> specifies the depth of a cube -* - <b>Layout::H</b> specifies the height of a cube -* - <b>Layout::W</b> specifies the height of a cube -* - <b>Layout::C</b> specifies the number of channels of each element in a cube -* - <b>Layout::W_c</b> specifies the number of scalars of each row in one image of a cube. -* - <b>Layout::H_w</b> specifies the number of elements in an image slice. -* - <b>Layout::H_w_c</b>_specifies the number of scalars in an image slice. -* - <b>Layout::D_h_w</b> specifies the number of elements in a cube. -* - <b>Layout::D_h_w_c</b> specifies the number of scalars in a cube. -* - <b>Layout::Strides</b> is a \ref layout_concept specifying the strides. -* @} -*/ - -/** -* @brief A Shape implementing \ref layout_concept describing the dimensions of a cube. -* @concept{layout_concept} -*/ -template <int kD_ = 1, int kH_ = 1, int kW_ = 1, int kC_ = 1> -struct Shape { - /// The depth of the cube. - static int const kD = kD_; - /// The height of the cube. - static int const kH = kH_; - /// The width of the cube. - static int const kW = kW_; - /// The number of scalars per element. - static int const kC = kC_; -}; - -/** -* @brief Compute derived counted of a \ref layout_concept based class -*/ -template <typename Shape> -struct ShapeCount { - /// The number of elements per row. - static int const kWc = Shape::kW * Shape::kC; - /// The number of pixels per image. - static int const kHw = Shape::kH * Shape::kW; - /// The number of elements per image. - static int const kHwc = Shape::kH * kWc; - /// The number of pixels per cube. - static int const kDhw = Shape::kD * kHw; - /// The number of elements in the 4D space. - static int const kDhwc = Shape::kD * kHwc; - /// The number of elements in the 4D space. - static int const kCount = kDhwc; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename A_, int kScale_> -struct ShapeScale { - typedef Shape<A_::kD * kScale_, A_::kH * kScale_, A_::kW * kScale_, A_::kC * kScale_> Shape; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename A_, typename B_> -struct ShapeAdd { - typedef Shape<A_::kD + B_::kD, A_::kH + B_::kH, A_::kW + B_::kW, A_::kC + B_::kC> Shape; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename A_, typename B_> -struct ShapeSub { - typedef Shape<A_::kD - B_::kD, A_::kH - B_::kH, A_::kW - B_::kW, A_::kC - B_::kC> Shape; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename A_, typename B_> -struct ShapeMul { - typedef Shape<A_::kD * B_::kD, A_::kH * B_::kH, A_::kW * B_::kW, A_::kC * B_::kC> Shape; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename A_, typename B_> -struct ShapeDiv { - typedef Shape<A_::kD / B_::kD, A_::kH / B_::kH, A_::kW / B_::kW, A_::kC / B_::kC> Shape; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename A_, typename B_> -struct ShapeMax { - typedef Shape<(A_::kD > B_::kD ? A_::kD : B_::kD), - (A_::kH > B_::kH ? A_::kH : B_::kH), - (A_::kW > B_::kW ? A_::kW : B_::kW), - (A_::kC > B_::kC ? A_::kC : B_::kC)> - Shape; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename A_, typename B_> -struct ShapeMin { - typedef Shape<(A_::kD < B_::kD ? A_::kD : B_::kD), - (A_::kH < B_::kH ? A_::kH : B_::kH), - (A_::kW < B_::kW ? A_::kW : B_::kW), - (A_::kC < B_::kC ? A_::kC : B_::kC)> - Shape; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Shape_, int kElementsPerAccess> -struct ShapeStrides { - typedef Shape<Shape_::kH * Shape_::kW * Shape_::kC, - Shape_::kW * Shape_::kC, - Shape_::kC, - kElementsPerAccess> - Shape; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/** -* @brief Compute the offset for the given coordinates in a cube -* @tparam A \ref layout_concept where each dimension of the cube specifies the corresponding stride. -*/ -template <typename Shape_> -struct ComputeOffsetFromShape { - static CUTLASS_DEVICE int get(int d, int h, int w, int c) { - // clang-format off - return d * Shape_::kH * Shape_::kW * Shape_::kC + - h * Shape_::kW * Shape_::kC + - w * Shape_::kC + - c; - // clang-format on - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/** -* @brief Compute the offset for the given coordinates in a cube with a depth of 1 -* @tparam kSh Elements in the H dimension -* @tparam kSw Elements in the W dimension -* @tparam kSc Separation between two elements in "elements" -*/ -template <int kSh_, int kSw_, int kSc_> -struct ComputeOffsetFromShape<Shape<1, kSh_, kSw_, kSc_> > { - static CUTLASS_DEVICE int get(int d, int h, int w, int c) { - return h * kSw_ * kSc_ + w * kSc_ + c; - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/** -* @brief Compute the offset for the given coordinates in a cube with one channel and a depth of 1 -* @tparam kSh Elements in the H dimension -* @tparam kSw Elements in the W dimension -*/ -template <int kSh_, int kSw_> -struct ComputeOffsetFromShape<Shape<1, kSh_, kSw_, 1> > { - static CUTLASS_DEVICE int get(int d, int h, int w, int c) { return h * kSw_ + w; } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/** -* @brief Compute the offset for the given coordinates in a cube -* @tparam A \ref layout_concept where each dimension of the cube specifies the corresponding stride. -*/ -template <typename Strides_> -struct ComputeOffsetFromStrides { - static CUTLASS_DEVICE int get(int d, int h, int w, int c) { - return d * Strides_::kD + h * Strides_::kH + w * Strides_::kW + c * Strides_::kC; - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/** -* @brief Compute the offset for the given coordinates in a cube with a depth of 1 -* @tparam S_h Stride in the H dimension in scalars -* @tparam S_w Stride in the W dimension in scalars -* @tparam S_c Stride between two scalars. -*/ -template <int S_h_, int S_w_, int S_c_> -struct ComputeOffsetFromStrides<Shape<1, S_h_, S_w_, S_c_> > { - static CUTLASS_DEVICE int get(int d, int h, int w, int c) { - return h * S_h_ + w * S_w_ + c * S_c_; - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/** -* @brief Compute the offset for the given coordinates in a cube with one channel and a depth of 1 -* @tparam S_h Stride in the H dimension in scalars -* @tparam S_w Stride in the W dimension in scalars -*/ -template <int S_h_, int S_w_> -struct ComputeOffsetFromStrides<Shape<1, S_h_, S_w_, 1> > { - static CUTLASS_DEVICE int get(int d, int h, int w, int c) { return h * S_h_ + w * S_w_; } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/** -* @brief Decompose threadId.x into coordinate of a cube whose dimensions are specified by Threads_. -* Afterwards compute the offset of those coordinates using Strides_ -* @tparam Threads_ The dimension of the cube the threadIdx.x value is mapped on -* @tparam Strides_ The strides to use when compute the offsets based on the coordinates of the cube. -*/ -template <typename Threads_, typename Strides_> -struct ComputeThreadOffsetFromStrides { - static CUTLASS_DEVICE int get() { - // Decompose the thread index. - int c = threadIdx.x % Threads_::kC; - int w = threadIdx.x / Threads_::kC % Threads_::kW; - int h = threadIdx.x / Threads_::kC / Threads_::kW % Threads_::kH; - int d = threadIdx.x / Threads_::kC / Threads_::kW / Threads_::kH; - - // Compute the offset. - return d * Strides_::kD + h * Strides_::kH + w * Strides_::kW + c * Strides_::kC; - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// -/** -*@brief Specialization for D=1 -*/ -template <int T_h_, int T_w_, int T_c_, int S_h_, int S_w_, int S_c_> -struct ComputeThreadOffsetFromStrides<Shape<1, T_h_, T_w_, T_c_>, Shape<1, S_h_, S_w_, S_c_> > { - static CUTLASS_DEVICE int get() { - // Decompose the thread index. - int c = threadIdx.x % T_c_; - int w = threadIdx.x / T_c_ % T_w_; - int h = threadIdx.x / T_c_ / T_w_ % T_h_; - - // Compute the offset. - return h * S_h_ + w * S_w_ + c * S_c_; - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/** -*@brief Specialization for D=1 and C=1 -*/ -template <int T_h_, int T_w_, int S_h_, int S_w_> -struct ComputeThreadOffsetFromStrides<Shape<1, T_h_, T_w_, 1>, Shape<1, S_h_, S_w_, 1> > { - static CUTLASS_DEVICE int get() { - // Decompose the thread index. - int w = threadIdx.x % T_w_; - int h = threadIdx.x / T_w_; - - // Compute the offset. - return h * S_h_ + w * S_w_; - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace cutlass diff --git a/cutlass-example/cutlass/tensor_ref.h b/cutlass-example/cutlass/tensor_ref.h deleted file mode 100644 index 8ef31e3..0000000 --- a/cutlass-example/cutlass/tensor_ref.h +++ /dev/null @@ -1,151 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines a structure containing strides, bounds, and a pointer to tensor data. -*/ -#pragma once - -#include <typeinfo> - -#include <cutlass/coord.h> -#include <cutlass/cutlass.h> -#include <cutlass/vector.h> - -namespace cutlass { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Structure modeling a pointer and stride into a tensor -template <typename Storage_, int Rank_> -class TensorRef { - public: - /// Data type of individual access - typedef Storage_ Storage; - - /// Rank of tensor - static int const Rank = Rank_; - - private: - // - // Data members - // - - /// Pointer to storage element - Storage* ptr_; - - /// Stride information - Coord<Rank> stride_; - - public: - // - // Methods - // - - /// Default ctor - CUTLASS_HOST_DEVICE - TensorRef() : ptr_(nullptr) {} - - /// Constructs from a pointer, size, and stride - CUTLASS_HOST_DEVICE - TensorRef(Storage* ptr, Coord<Rank> stride) : ptr_(ptr), stride_(stride) {} - - /// Updates the pointer, stride, and location within a TensorRef - CUTLASS_HOST_DEVICE - void reset(Storage* ptr = nullptr, Coord<Rank> stride = Coord<Rank>(0)) { - ptr_ = ptr; - stride_ = stride; - } - - /// Conversion function - template <typename T> - TensorRef<T, Rank> convert() { - Coord<Rank> converted_stride; - for (int i = 0; i < Rank - 1; ++i) { - converted_stride[i] = stride_[i] * Extent<Storage>::kValue / Extent<T>::kValue; - } - converted_stride[Rank - 1] = stride_[Rank - 1]; - - return TensorRef<T, Rank>(reinterpret_cast<T*>(ptr_), converted_stride); - } - - /// Returns true if the TensorRef may be safely accessed - CUTLASS_HOST_DEVICE - bool good() const { return ptr_ != nullptr; } - - /// Returns the pointer to referenced data - CUTLASS_HOST_DEVICE - Storage* data() const { return ptr_; } - - /// Returns the stride of the tensor - CUTLASS_HOST_DEVICE - Coord<Rank> const& stride() const { return stride_; } - - /// Returns the stride of the tensor in the given dimension - CUTLASS_HOST_DEVICE - int const& stride(int dim) const { return stride_.at(dim); } - - /// Returns the maximum stride element as the 'leading dimension' - CUTLASS_HOST_DEVICE - int leading_dim() const { return __NV_STD_MAX(stride_[1], stride_[2]); } - - /// Computes the offset of an index from the origin of the tensor - CUTLASS_HOST_DEVICE - long long offset(Coord<Rank> const& coord) const { - return stride_.template dot<long long>(coord); - } - - /// Returns a reference to the element at a given Coord - CUTLASS_HOST_DEVICE - Storage& at(Coord<Rank> const& coord) const { return ptr_[offset(coord)]; } - - /// Element-wise accessor - Storage& operator[](Coord<Rank> const& coord) const { return at(coord); } - - /// Returns a reference to the element at a given Coord - CUTLASS_HOST_DEVICE - Storage& at(int idx) const { return ptr_[idx]; } - - /// Element-wise accessor - Storage& operator[](int idx) const { return at(idx); } - - /// Adds an offset to the pointer - CUTLASS_HOST_DEVICE - TensorRef& advance(Coord<Rank> const& b) { - ptr_ += offset(b); - return *this; - } - - /// Returns a TensorRef offset by a given amount - CUTLASS_HOST_DEVICE - TensorRef operator+(Coord<Rank> const& b) const { return TensorRef(ptr_ + offset(b), stride_); } - - /// Returns a TensorRef offset by a given amount - CUTLASS_HOST_DEVICE - TensorRef operator-(Coord<Rank> const& b) const { return TensorRef(ptr_ - offset(b), stride_); } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace cutlass diff --git a/cutlass-example/cutlass/tensor_view.h b/cutlass-example/cutlass/tensor_view.h deleted file mode 100644 index 89c6bd5..0000000 --- a/cutlass-example/cutlass/tensor_view.h +++ /dev/null @@ -1,172 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines a structure containing strides and a pointer to tensor data. -*/ - -#pragma once - -#include <cmath> - -#include <cutlass/cutlass.h> -#include <cutlass/tensor_ref.h> - -namespace cutlass { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Host-side reference implementation of tensor operations -template <typename T> -class TensorView : public TensorRef<T, 4> { - public: - /// Reference and stride - typedef TensorRef<T, 4> Base; - - /// Reference and stride - typedef Base TensorRef_t; - - /// Reference to constant type - typedef TensorRef<T const, 4> ConstTensorRef_t; - - /// Rank of tensor - static int const Rank = TensorRef_t::Rank; - - /// Type used to compute the offset of an element to the base of a tensor - typedef int Offset_t; - - /// Coordinate into tensor - typedef Coord<Rank> Coord_t; - - private: - // - // Data members - // - - /// Pointer to pitch-linear memory - TensorRef_t ref_; - - /// Dimensions of coordinate (independent of stride) - Coord_t size_; - - public: - // - // Device and Host Methods - // - - /// Default constructor - CUTLASS_HOST_DEVICE - TensorView() {} - - /// Constructs a Tensor_view from a TensorRef and size - CUTLASS_HOST_DEVICE - TensorView(TensorRef_t const& _ref, Coord_t const& _size) : Base(_ref), size_(_size) {} - - /// Returns true if the Tensor_view is bound to some memory - CUTLASS_HOST_DEVICE - bool good() const { return ref().good(); } - - /// Returns a pointer to data - CUTLASS_HOST_DEVICE - T* data() const { return ref().data(); } - - /// Updates the reference and size of a Tensor_view object - CUTLASS_HOST_DEVICE - void reset(TensorRef_t const& _ref = TensorRef_t(0), Coord_t const& _size = Coord_t()) { - Base::operator=(_ref); - size_ = _size; - } - - /// Accesses the tensor reference pointing to data - CUTLASS_HOST_DEVICE - TensorRef_t& ref() { return *this; } - - /// - CUTLASS_HOST_DEVICE - ConstTensorRef_t const_ref() { return ConstTensorRef_t(data(), stride()); } - - /// Accesses the tensor reference pointing to data - CUTLASS_HOST_DEVICE - TensorRef_t const& ref() const { return *this; } - - /// Accesses the size - CUTLASS_HOST_DEVICE - Coord_t const& size() const { return size_; } - - /// Accesses the size - CUTLASS_HOST_DEVICE - int size(int dim) const { return size_.at(dim); } - - /// Accesses the stride - CUTLASS_HOST_DEVICE - Coord_t const& stride() const { return ref().stride(); } - - /// Accesses the stride - CUTLASS_HOST_DEVICE - int const& stride(int dim) const { return ref().stride(dim); } - - /// Assigns the Tensor_view - CUTLASS_HOST_DEVICE - TensorView& operator=(TensorView const& _tensor) { - Base::operator=(_tensor._ref); - size_ = _tensor.size_; - return *this; - } - - /// Returns the index of an element - CUTLASS_HOST_DEVICE - Offset_t offset(Coord_t const& coord) const { return ref().offset(coord); } - - /// Determines whether a location is within a tensor - CUTLASS_HOST_DEVICE - bool contains(Coord_t const& coord) const { - for (int dim = 0; dim < Rank; ++dim) { - if (coord.at(dim) >= size_.at(dim)) { - return false; - } - } - return true; - } - - /// Element-wise accessor - CUTLASS_HOST_DEVICE - T& at(Coord_t const& coord) const { return ref().at(coord); } - - /// Element-wise accessor - T& operator[](Coord<Rank> const& coord) const { return at(coord); } - - /// Element-wise accessor - CUTLASS_HOST_DEVICE - T& at(Offset_t idx) const { return ref().at(idx); } - - /// Returns a Tensor_view given location and size quantities - CUTLASS_HOST_DEVICE - TensorView<T> subview(Coord_t const& location, Coord_t size) const { - return TensorView<T>(ref() + location, size.clamp(size_ - location)); - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace cutlass diff --git a/cutlass-example/cutlass/tile_iterator.h b/cutlass-example/cutlass/tile_iterator.h deleted file mode 100644 index 5d39c4f..0000000 --- a/cutlass-example/cutlass/tile_iterator.h +++ /dev/null @@ -1,899 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines the Tile Traits concept and iterators for loading and storing to tiles - efficiently. -*/ -#pragma once - -#include <cutlass/fragment.h> -#include <cutlass/load_store.h> -#include <cutlass/predicate_vector.h> -#include <cutlass/vector.h> - -namespace cutlass { - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/*!@defgroup tile_traits_concept Tile Traits Concept -@{ - -\ref tile_traits_concept is a type definining the shape of a tile and the distribution of accesses -by individual entities, either threads or other. - -@par Tile Traits Concept - Types satisfying \ref tile_traits_concept define the following members - - <b>Tile</b> - a type satisfying \ref layout_concept describing the dimensions of the tile - - <b>Delta</b> - a type satisfying \ref layout_concept describing the increments between accesses -along each dimension - - <b>Iterations</b> - a type satisfying \ref layout_concept describing the number of accesses -along each dimension - - <b>Offset</b> - the type of a <i>functor</i> computing the offset of each participating entity -as a Coord<4>. -@} -*/ - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Specifies dimension in which post-increment accesses advance -struct IteratorAdvance { - enum Kind { kD, kH, kW }; -}; - -/// Specifies whether iterator storage fragment consists of Scalar values or WMMA matrix -struct IteratorFragment { - enum Kind { kScalar, kWmmaMatrix }; -}; - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/** -* @brief A template defining \ref tile_traits_concept -* @concept{tile_traits_concept} -*/ -template <typename Tile_, - typename Delta_, - typename Iterations_, - typename ThreadOffset_, - int kAccessSize> -struct TileTraits { - /// Shape of the tile - typedef Tile_ Tile; - - /// Number of steps between accesses along each dimension - typedef Delta_ Delta; - - /// Number of accesses performed - typedef Iterations_ Iterations; - - /// Functor that returns the logical coordinate of each entity's initial offset in the tile - typedef ThreadOffset_ ThreadOffset; -}; - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Iterator for accessing a stripmined tile in memory -template <typename Traits_, - typename Scalar_, - IteratorAdvance::Kind Advance_ = IteratorAdvance::kH, - MemorySpace::Kind MemorySpace = MemorySpace::kGeneric, - typename Index_ = int, - typename FragmentElement_ = Scalar_, - IteratorFragment::Kind IteratorFragment_ = IteratorFragment::kScalar, - typename Skew_ = Shape<0, 0, 0, 0> > -struct TileIteratorBase { - /// concept TileTraits - typedef Traits_ Traits; - - /// Scalar element - typedef Scalar_ Scalar; - - /// Fragment element - typedef FragmentElement_ FragmentElement; - - /// Specifies dimension in which post-increment accesses advance. - static IteratorAdvance::Kind const kAdvance = Advance_; - - /// Specifies iterator storage fragment type (Scalar or WmmaMatrix) - static IteratorFragment::Kind const kIteratorFragment = IteratorFragment_; - - /// Source or destination memory space - static MemorySpace::Kind const kMemorySpace = MemorySpace; - - /// Index type - typedef Index_ Index; - - /// Skew quantity - typedef Skew_ Skew; - - /// Tile shape - typedef typename Traits::Tile Tile; - - /// Distance along each dimension - typedef typename Traits::Delta Delta; - - /// The strides in each dimension between different loads/stores. - typedef typename Traits::ImmediateOffsetStrides ImmediateOffsetStrides; - - /// Iterations - typedef typename Traits::Iterations Iterations; - - /// Thread offset - typedef typename Traits::ThreadOffset ThreadOffset; - - /// The number of scalars accessed per load/store. - static int const kAccessSize = Tile::kC; - - /// The elements loaded/store by one instruction. - typedef typename Vectorize<FragmentElement, kAccessSize>::Type AccessType; - - /// The size of storage needed per fragment - static int const kFragmentSize = - (kIteratorFragment == IteratorFragment::kWmmaMatrix ? 16 : sizeof(AccessType)); - /// The storage. - typedef Fragment<Scalar, ShapeCount<Tile>::kCount, kFragmentSize> Storage; - /// The fragment. - typedef Fragment<FragmentElement, ShapeCount<Iterations>::kCount * kAccessSize> Fragment; - /// The fragment iterator. - typedef FragmentIterator<Fragment, Iterations, AccessType> FragmentIterator; - /// The fragment const iterator. - typedef FragmentConstIterator<Fragment, Iterations, AccessType> FragmentConstIterator; - /// The shape of the fragment. - typedef typename FragmentIterator::FragmentShape FragmentShape; - - /// Default predicate mask type - typedef PredicateVector<ShapeCount<Iterations>::kCount> PredicateVector; - - // - // Params struct - // - - /// Parameters to the iterator - struct Params { - Index stride_d; - Index stride_h; - Index stride_w; - - Index inc_d; - Index inc_h; - Index inc_w; - - Index inc_advance; - - /// Initializes params - CUTLASS_HOST_DEVICE - int initialize(Index _stride_d, - Index _stride_h, - Index _stride_w, - Index _inc_d, - Index _inc_h, - Index _inc_w, - Index _inc_advance) { - stride_d = _stride_d; - stride_h = _stride_h; - stride_w = _stride_w; - - inc_d = _inc_d; - inc_h = _inc_h; - inc_w = _inc_w; - inc_advance = _inc_advance; - - return 0; - } - - CUTLASS_HOST_DEVICE - int initialize(Index _stride_d, Index _stride_h, Index _stride_w) { - stride_d = _stride_d; - stride_h = _stride_h; - stride_w = _stride_w; - - inc_w = stride_w * Delta::kW; - inc_h = stride_h * Delta::kH - stride_w * Delta::kW * (Iterations::kW - 1); - - if (kAdvance == IteratorAdvance::kH) { - // Advance in the H dimension. - inc_d = 0; - } else if (kAdvance == IteratorAdvance::kW) { - // Advance in the W dimension. - inc_d = stride_w * Tile::kW - stride_h * Tile::kH; - } else { - // Advance in the D dimension. - inc_d = stride_d; - } - - inc_advance = 0; - - return 0; - } - - CUTLASS_HOST_DEVICE int initialize() { - stride_d = 0; - stride_h = 0; - stride_w = 1; - - inc_d = inc_h = inc_w = inc_advance = 0; - - return 0; - } - }; - - /// Is the iterator valid? - CUTLASS_DEVICE bool valid(int d, int h, int w, int c) const { return true; } - - // - // Static function members - // - - /// Initializes a predicate vector - template <typename PredicateIterator> - CUTLASS_DEVICE static void initialize_predicates(PredicateIterator predicate_it, - Coord<3> const &bounds, - Coord<3> const &offset = make_Coord(0, 0, 0)) { - for (int d = 0; d < Iterations::kD; ++d) { - bool enable_d = (d * Delta::kD + offset[0] < bounds[0]); - for (int h = 0; h < Iterations::kH; ++h) { - bool enable_h = (h * Delta::kH + offset[1] < bounds[1]); - for (int w = 0; w < Iterations::kW; ++w) { - bool enable_w = (w * Tile::kC * Delta::kW + offset[2] < bounds[2]); - predicate_it.set(d, h, w, 0, enable_d && enable_h && enable_w); - } - } - } - } -}; - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/*!@defgroup tile_load_iterator_concept Tile Load Iterator Concept -@{ - -\ref tile_load_iterator_concept enables loading a tile from addressable memory into a fragment - -@par Tile Load Iterator Concept - Types satisfying \ref tile_load_iterator_concept define the following members - - <b>PredicateVector</b> - a \ref predicate_vector_concept with sufficient predicate storage for -each access implied by the tile traits - - <b>Fragment</b> - the destination fragment type satisfying \ref fragment_concept - - <b>initialize_predicates(pred_it, bounds, block_offset)</b> - function initializing a predicate -vector according to externally specified bounds - - <b>load_post_increment(fragment, pred_it)</b> - a method that loads a fragment and increments -the iterator to the next tile, guarded by a \ref predicate_iterator_concept - - <b>load_post_increment(fragment)</b> - a method that loads a fragment and increments the -iterator to the next tile - - <b>load(fragment, pred_it)</b> - a const method that loads a fragment, guarded by a \ref -predicate_iterator_concept - - <b>load(fragment)</b> - a method that loads a fragment - -@} -*/ - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/** -* @brief An iterator implementing \ref tile_load_iterator_concept for loading a tile from memory -* @concept{tile_load_iterator_concept} -*/ -template <typename Traits_, - typename Scalar_, - IteratorAdvance::Kind Advance_ = IteratorAdvance::kH, - MemorySpace::Kind MemorySpace = MemorySpace::kGeneric, - typename Index_ = int, - typename FragmentElement_ = Scalar_, - IteratorFragment::Kind IteratorFragment_ = IteratorFragment::kScalar, - typename Skew_ = Shape<0, 0, 0, 0> > -struct TileLoadIterator : public TileIteratorBase<Traits_, - Scalar_, - Advance_, - MemorySpace, - Index_, - FragmentElement_, - IteratorFragment_, - Skew_> { - /// Base class - typedef TileIteratorBase<Traits_, - Scalar_, - Advance_, - MemorySpace, - Index_, - FragmentElement_, - IteratorFragment_, - Skew_> - Base; - - /// concept TileTraits - typedef typename Base::Traits Traits; - - /// Scalar element - typedef typename Base::Scalar Scalar; - - /// Fragment element - typedef typename Base::FragmentElement FragmentElement; - - /// Specifies in which dimension post-increment accesses advance. - static IteratorAdvance::Kind const kAdvance = Base::kAdvance; - - /// Specifies type of iterator fragment storage (Salar or WmmaMatrix) - static IteratorFragment::Kind const kIteratorFragment = Base::kIteratorFragment; - - /// Source or destination memory space - static MemorySpace::Kind const kMemorySpace = Base::kMemorySpace; - - /// Index type - typedef typename Base::Index Index; - - /// Skew quantity - typedef typename Base::Skew Skew; - - /// Tile shape - typedef typename Base::Tile Tile; - - /// Delta - typedef typename Base::Delta Delta; - - /// Iterations - typedef typename Base::Iterations Iterations; - - /// ThreadOffset functor - typedef typename Base::ThreadOffset ThreadOffset; - - /// Fragment type - typedef typename Base::FragmentShape FragmentShape; - - /// Memory access type - typedef typename Base::AccessType AccessType; - - /// Fragment definition - typedef typename Base::Fragment Fragment; - - /// Fragment iterator definition - typedef typename Base::FragmentIterator FragmentIterator; - - /// Fragment const iterator definition - typedef typename Base::FragmentConstIterator FragmentConstIterator; - - /// Default predicate mask type - typedef typename Base::PredicateVector PredicateVector; - - /// Storage object that may be loaded from - typedef typename Base::Storage SharedStorage; - - /// IteratorBase parameters - typedef typename Base::Params BaseParams; - - /// Do we require a fence? - enum { kRequiresLoadFence = Tile::kD == 1 }; - - /// The pointer type - typedef Scalar const *Pointer; - - /// Parameters - struct Params : public BaseParams { - /// Pointer to memory - Scalar const *pointer; - - /// Initialize params to access storage object - CUTLASS_HOST_DEVICE - int initialize(SharedStorage const &storage) { - pointer = &storage[0]; - return 0; - } - - /// Initializes params to access a raw pointer - CUTLASS_HOST_DEVICE - int initialize(Scalar const *ptr, Index stride_d, Index stride_h, Index stride_w) { - Base::Params::initialize(stride_d, stride_h, stride_w); - pointer = ptr; - return 0; - } - - /// Initializes params - CUTLASS_HOST_DEVICE - int initialize(Scalar const *ptr, - Index _stride_d, - Index _stride_h, - Index _stride_w, - Index _inc_d, - Index _inc_h, - Index _inc_w, - Index _inc_advance) { - pointer = ptr; - Base::Params::initialize( - _stride_d, _stride_h, _stride_w, _inc_d, _inc_h, _inc_w, _inc_advance); - return 0; - } - - // Initializes params to default values - CUTLASS_HOST_DEVICE - int initialize() { return Base::Params::initialize(); } - }; - - // - // Data members - // - - /// Parameters structure - Params params; - - /// Offset of an individual lane from the start of the tile - Coord<4> thread_offset; - - /// Stage argument enables wrapping after some number of tiles have been loaded. - int stage; - - // - // Static member functions - // - - /// Initializes a predicate vector - template <typename PredicateIterator> - CUTLASS_HOST_DEVICE void initialize_predicates(PredicateIterator predicate_it, - Coord<3> const &bounds, - Coord<3> const &block_offset = make_Coord(0, - 0, - 0)) { - Base::initialize_predicates( - predicate_it, - bounds, - block_offset + make_Coord(0, thread_offset[1], thread_offset[2] * Tile::kC)); - } - - // - // Methods - // - - /// Default constructor - CUTLASS_HOST_DEVICE - TileLoadIterator() {} - - /// Constructs a tile load iterator - CUTLASS_HOST_DEVICE - TileLoadIterator(Params const &_params, - Coord<3> const &block_offset = make_Coord(0, 0, 0), - ThreadOffset thread_offset_func = ThreadOffset()) - : params(_params), stage(0) { - thread_offset = thread_offset_func(); - - Index block_offset_h = 0; - Index block_offset_w = 0; - if (kAdvance == IteratorAdvance::kH) { - block_offset_h = block_offset[1]; - block_offset_w = block_offset[2]; - } else { - block_offset_h = block_offset[2]; - block_offset_w = block_offset[1]; - } - - params.pointer += block_offset[0] * params.stride_d + - (block_offset_h + thread_offset[1]) * params.stride_h + - (block_offset_w + thread_offset[2] * Tile::kC) / Tile::kC * params.stride_w; - } - - /// Constructs a tile load iterator - CUTLASS_HOST_DEVICE - TileLoadIterator(Params const &, - SharedStorage &shared_storage, - Coord<3> const &block_offset = make_Coord(0, 0, 0), - ThreadOffset thread_offset_func = ThreadOffset()) - : stage(0) { - int const offset = thread_offset_func()[2]; - params.pointer = &shared_storage[offset]; - } - - /// Returns the current pointer - CUTLASS_HOST_DEVICE - Scalar const *data() const { return params.pointer; } - - /// The accessor. - CUTLASS_DEVICE void get(AccessType &value, int d, int h, int w, int c) const { - int const imm = - ComputeOffsetFromStrides<typename Base::ImmediateOffsetStrides>::get(d, h, w, c); - Load<Scalar, Base::kAccessSize, kMemorySpace>::load(value, params.pointer, imm); - } - - /// Increment in the D dimension - CUTLASS_HOST_DEVICE void inc_d() { params.pointer += params.inc_d; } - - /// Increment in the H dimension - CUTLASS_HOST_DEVICE void inc_h() { params.pointer += params.inc_h; } - - /// Increment in the W dimension - CUTLASS_HOST_DEVICE void inc_w() { params.pointer += params.inc_w; } - - /// Increment in the next dimension - CUTLASS_HOST_DEVICE void inc_advance() { params.pointer += params.inc_advance; } - - /// Increment the stage. - CUTLASS_DEVICE void inc_stage() { - if (Tile::kD > 1) { - int const kStageSize = Tile::kH * Tile::kW * Tile::kC; - if (stage == Tile::kD - 1) { - params.pointer -= (Tile::kD - 1) * kStageSize; - stage = 0; - } else { - params.pointer += kStageSize; - stage = stage + 1; - } - } - } - - public: - /// Loads a fragment and advances the iterator to the next tile. - template <typename Fragment, typename PredicateIterator> - CUTLASS_HOST_DEVICE void load_post_increment(Fragment &fragment, PredicateIterator pred_it) { - FragmentIterator frag_iterator(fragment); - - for (int d = 0; d < Iterations::kD; ++d) { - for (int h = 0; h < Iterations::kH; ++h) { - for (int w = 0; w < Iterations::kW; ++w, ++pred_it) { - if (*pred_it) { - Load<typename Fragment::Element, Tile::kC, kMemorySpace>::load( - reinterpret_cast<AccessType &>(frag_iterator.at(d, h, w, 0)), data(), 0); - } - - if (w < Iterations::kW - 1) { - inc_w(); - } - } - if (h < Iterations::kH - 1) { - inc_h(); - } - } - if (d < Iterations::kD - 1) { - inc_d(); - } - } - inc_advance(); - } - - /// Loads a fragment and advances the iterator to the next tile. - template <typename Fragment> - CUTLASS_HOST_DEVICE void load_post_increment(Fragment &fragment) { - typename PredicateVector::TrivialIterator pred_it; - load_post_increment(fragment, pred_it); - } - - /// Loads a fragment without advancing the iterator.. - template <typename Fragment, typename PredicateIterator> - CUTLASS_HOST_DEVICE void load(Fragment &fragment, PredicateIterator pred_it) const { - TileLoadIterator _load_it(*this); - _load_it.load_post_increment(fragment, pred_it); - } - - /// Loads a fragment without advancing the iterator.. - template <typename Fragment> - CUTLASS_HOST_DEVICE void load(Fragment &fragment) const { - typename PredicateVector::TrivialIterator pred_it; - load(fragment, pred_it); - } -}; - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/*!@defgroup tile_store_iterator_concept Tile Store Iterator Concept -@{ - -\ref tile_store_iterator_concept enables storing a tile to addressable memory - -@par Tile Store Iterator Concept - Types satisfying \ref tile_load_iterator_concept define the following members - - <b>PredicateVector</b> - a \ref predicate_vector_concept with sufficient predicate storage for -each access implied by the tile traits - - <b>Fragment</b> - the destination fragment type satisfying \ref fragment_concept - - <b>initialize_predicates(pred_it, bounds, block_offset)</b> - function initializing a predicate -vector according to externally specified bounds - - <b>store_post_increment(fragment, pred_it)</b> - a method that stores a fragment and increments -the iterator to the next tile, guarded by a \ref predicate_iterator_concept - - <b>store_post_increment(fragment)</b> - a method that stores a fragment and increments the -iterator to the next tile - - <b>store(fragment, pred_it)</b> - a const method that stores a fragment, guarded by a \ref -predicate_iterator_concept - - <b>store(fragment)</b> - a method that loads a fragment - -@} -*/ - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/** -* @brief An iterator implementing \ref tile_store_iterator_concept for storing a tile to memory -* @concept{tile_store_iterator_concept} -*/ -template <typename Traits_, - typename Scalar_, - IteratorAdvance::Kind Advance_ = IteratorAdvance::kH, - MemorySpace::Kind MemorySpace = MemorySpace::kGeneric, - typename Index_ = int, - typename FragmentElement_ = Scalar_, - IteratorFragment::Kind IteratorFragment_ = IteratorFragment::kScalar, - typename Skew_ = Shape<0, 0, 0, 0> > -struct TileStoreIterator : public TileIteratorBase<Traits_, - Scalar_, - Advance_, - MemorySpace, - Index_, - FragmentElement_, - IteratorFragment_, - Skew_> { - /// Base class - typedef TileIteratorBase<Traits_, - Scalar_, - Advance_, - MemorySpace, - Index_, - FragmentElement_, - IteratorFragment_, - Skew_> - Base; - - /// concept TileTraits - typedef typename Base::Traits Traits; - - /// Scalar element - typedef typename Base::Scalar Scalar; - - /// Fragment element - typedef typename Base::FragmentElement FragmentElement; - - /// Specifies in which dimension post-increment accesses advance. - static IteratorAdvance::Kind const kAdvance = Base::kAdvance; - - /// Specifies type of iterator fragment storage (Salar or WmmaMatrix) - static IteratorFragment::Kind const kIteratorFragment = Base::kIteratorFragment; - - /// Source or destination memory space - static MemorySpace::Kind const kMemorySpace = Base::kMemorySpace; - - /// Index type - typedef typename Base::Index Index; - - /// Skew quantity - typedef typename Base::Skew Skew; - - /// Tile shape - typedef typename Base::Tile Tile; - - /// Delta - typedef typename Base::Delta Delta; - - /// Iterations - typedef typename Base::Iterations Iterations; - - /// ThreadOffset functor - typedef typename Base::ThreadOffset ThreadOffset; - - /// Fragment type - typedef typename Base::FragmentShape FragmentShape; - - /// Memory access type - typedef typename Base::AccessType AccessType; - - /// Fragment definition - typedef typename Base::Fragment Fragment; - - /// Fragment iterator definition - typedef typename Base::FragmentIterator FragmentIterator; - - /// Fragment const iterator definition - typedef typename Base::FragmentConstIterator FragmentConstIterator; - - /// Default predicate mask type - typedef typename Base::PredicateVector PredicateVector; - - /// Storage object which may be stored to - typedef typename Base::Storage SharedStorage; - - /// IteratorBase parameters - typedef typename Base::Params BaseParams; - - /// Parameters - struct Params : public BaseParams { - /// Pointer to memory - Scalar *pointer; - - /// Initialize params to access storage object - CUTLASS_HOST_DEVICE - int initialize(SharedStorage &storage) { - pointer = &storage[0]; - return 0; - } - - /// Initializes params to access a raw pointer - CUTLASS_HOST_DEVICE - int initialize(Scalar *ptr, Index stride_d, Index stride_h, Index stride_w) { - Base::Params::initialize(stride_d, stride_h, stride_w); - pointer = ptr; - return 0; - } - - /// Initializes params - CUTLASS_HOST_DEVICE - int initialize(Scalar *ptr, - Index _stride_d, - Index _stride_h, - Index _stride_w, - Index _inc_d, - Index _inc_h, - Index _inc_w, - Index _inc_advance) { - pointer = ptr; - Base::Params::initialize( - _stride_d, _stride_h, _stride_w, _inc_d, _inc_h, _inc_w, _inc_advance); - return 0; - } - - /// Initializes params to default values - CUTLASS_HOST_DEVICE - int initialize() { return Base::Params::initialize(); } - }; - - // - // Data members - // - - /// Parameters structure - Params params; - - /// Offset of an individual lane from the start of the tile - Coord<4> thread_offset; - - /// The stage. - int stage; - - // - // Static member functions - // - - /// Initializes a predicate vector - template <typename PredicateIterator> - CUTLASS_HOST_DEVICE void initialize_predicates(PredicateIterator predicate_it, - Coord<3> const &bounds, - Coord<3> const &block_offset = make_Coord(0, - 0, - 0)) { - Base::initialize_predicates( - predicate_it, - bounds, - block_offset + make_Coord(0, thread_offset[1], thread_offset[2] * Tile::kC)); - } - - // - // Methods - // - - /// Default constructor - CUTLASS_HOST_DEVICE - TileStoreIterator() {} - - /// Constructs a tile store iterator - CUTLASS_HOST_DEVICE - TileStoreIterator(Params const &_params, - Coord<3> const &block_offset = make_Coord(0, 0, 0), - ThreadOffset thread_offset_func = ThreadOffset()) - : params(_params), stage(0) { - thread_offset = thread_offset_func(); - - params.pointer += block_offset[0] * params.stride_d + - (block_offset[1] + thread_offset[1]) * params.stride_h + - (block_offset[2] + thread_offset[2] * Tile::kC) / Tile::kC * params.stride_w; - } - - /// Constructs a tile store iterator - CUTLASS_HOST_DEVICE - TileStoreIterator(Params const &, - SharedStorage &shared_storage, - Coord<3> const &block_offset = make_Coord(0, 0, 0), - ThreadOffset thread_offset_func = ThreadOffset()) - : stage(0) { - int const offset = thread_offset_func()[2]; - params.pointer = &shared_storage[offset]; - } - - /// Returns the current pointer - CUTLASS_HOST_DEVICE - Scalar *data() const { return params.pointer; } - - /// Increment in the D dimension - CUTLASS_HOST_DEVICE void inc_d() { params.pointer += params.inc_d; } - - /// Increment in the H dimension - CUTLASS_HOST_DEVICE void inc_h() { params.pointer += params.inc_h; } - - /// Increment in the W dimension - CUTLASS_HOST_DEVICE void inc_w() { params.pointer += params.inc_w; } - - /// Increment in the next dimension - CUTLASS_HOST_DEVICE void inc_advance() {} - - /// Increment the stage. - CUTLASS_DEVICE void inc_stage() { - if (Tile::kD > 1) { - int const kStageSize = Tile::kH * Tile::kW * Tile::kC; - if (stage == Tile::kD - 1) { - params.pointer -= (Tile::kD - 1) * kStageSize; - stage = 0; - } else { - params.pointer += kStageSize; - stage = stage + 1; - } - } - } - - /// The accessor. - CUTLASS_DEVICE void set(AccessType const &value, int d, int h, int w, int c) { - int const imm = - ComputeOffsetFromStrides<typename Base::ImmediateOffsetStrides>::get(d, h, w, c); - Store<Scalar, Base::kAccessSize, kMemorySpace>::store(value, params.pointer, imm); - } - - public: - /// Stores a fragment and advances to the next tile. - template <typename Fragment, typename PredicateIterator> - CUTLASS_HOST_DEVICE void store_post_increment(Fragment &fragment, PredicateIterator pred_it) { - FragmentIterator frag_iterator(fragment); - - for (int d = 0; d < Iterations::kD; ++d) { - for (int h = 0; h < Iterations::kH; ++h) { - for (int w = 0; w < Iterations::kW; ++w, ++pred_it) { - if (*pred_it) { - Store<typename Fragment::Element, Tile::kC, kMemorySpace>::store( - reinterpret_cast<AccessType &>(frag_iterator.at(d, h, w, 0)), data(), 0); - } - if (w < Iterations::kW - 1) { - inc_w(); - } - } - if (h < Iterations::kH - 1) { - inc_h(); - } - } - if (d < Iterations::kD - 1) { - inc_d(); - } - } - inc_advance(); - } - - /// Stores a fragment and advances to the next tile. - template <typename Fragment> - CUTLASS_HOST_DEVICE void store_post_increment(Fragment &fragment) { - typename PredicateVector::TrivialIterator pred_it; - store_post_increment(fragment, pred_it); - } - - /// Stores a fragment without advancing the iterator. - template <typename Fragment, typename PredicateIterator> - CUTLASS_HOST_DEVICE void store(Fragment &fragment, PredicateIterator pred_it) const { - TileStoreIterator _store_it(*this); - _store_it.store_post_increment(fragment, pred_it); - } - - /// Stores a fragment without advancing the iterator. - template <typename Fragment> - CUTLASS_HOST_DEVICE void store(Fragment &fragment) const { - typename PredicateVector::TrivialIterator pred_it; - store(fragment, pred_it); - } -}; -} diff --git a/cutlass-example/cutlass/tile_traits_standard.h b/cutlass-example/cutlass/tile_traits_standard.h deleted file mode 100644 index 14ecd01..0000000 --- a/cutlass-example/cutlass/tile_traits_standard.h +++ /dev/null @@ -1,238 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines tile traits for several tile partitioning arrangements of threads expected to - achieve efficient streaming performance. -*/ -#pragma once - -#include <cutlass/tile_iterator.h> - -namespace cutlass { - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Basic thread offset function computed from a thread shape -template <typename ThreadShape> -struct TiledThreadOffset { - /// Computes the logical coordinate from thread shape - CUTLASS_HOST_DEVICE - Coord<4> operator()() const { - Coord<4> thread_offset; - - int index = threadIdx.x; - - thread_offset[3] = (index % ThreadShape::kC); - index = (index / ThreadShape::kC); - - thread_offset[2] = (index % ThreadShape::kW); - index = (index / ThreadShape::kW); - - thread_offset[1] = (index % ThreadShape::kH); - index = (index / ThreadShape::kH); - - thread_offset[0] = index; - - return thread_offset; - } -}; - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Tiling in which the number of threads is greater than the -/// contiguous dimension of the tile. -template <typename Tile_, int Threads> -struct TileTraitsStrideMajor { - /// Shape of tile - typedef Tile_ Tile; - - /// Number of participating threads - static int const kThreads = Threads; - - // Static assertions - static_assert(!(ShapeCount<Tile>::kDhw % kThreads), - "Tiling undefined if elements not divisible by threads."); - - static_assert(Tile::kW <= kThreads, - "This specialization assumes there are more threads than the contiguous dimension " - "of the tile."); - - /// Shape of threads - typedef Shape<1, kThreads / Tile::kW, Tile::kW, 1> ThreadShape; - - /// Delta along each dimension - typedef Shape<1, ThreadShape::kH, 1, 1> Delta; - - /// Number of iterations - typedef Shape<1, Tile::kH / ThreadShape::kH, 1, 1> Iterations; - - /// Computes the initial offset - typedef TiledThreadOffset<ThreadShape> ThreadOffset; -}; - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Tiling in which the number of threads is fewer than the tile size -/// in the contiguous dimension. -template <typename Tile_, int Threads> -struct TileTraitsContiguousMajor { - /// Shape of tile - typedef Tile_ Tile; - - /// Number of participating threads - static int const kThreads = Threads; - - // Static assertions - static_assert(Tile::kW >= kThreads, - "This specialization assumes there are more threads than the contiguous dimension " - "of the tile."); - - static_assert(!(ShapeCount<Tile>::kDhw % kThreads), - "Tiling undefined if elements not divisible by threads."); - - static_assert(!(Tile::kW % kThreads), - "The contiguous size of the tile must be divisible by the number of threads."); - - /// Thread shape - typedef Shape<1, 1, kThreads> ThreadShape; - - /// Delta between each thread's access - typedef Shape<1, 1, kThreads> Delta; - - /// Number of iterations - typedef Shape<1, Tile::kH, Tile::kW / kThreads> Iterations; - - /// Computes the initial offset - typedef TiledThreadOffset<ThreadShape> ThreadOffset; -}; - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Tiling in which warps rake across the contiguous dimension -template <typename Tile_, int Threads> -struct TileTraitsWarpRake { - /// Shape of tile - typedef Tile_ Tile; - - /// Number of participating threads - static int const kThreads = Threads; - - /// Hard-coded warp size - static int const kWarpSize = 32; - - /// Number of participating warps - static int const kWarpCount = kThreads / kWarpSize; - - // Static assertions - static_assert(!(ShapeCount<Tile>::kDhw % kThreads), - "Tiling undefined if elements not divisible by threads."); - - static_assert(!(kThreads % kWarpSize), "Number of threads must be divisible by the warp size."); - - static_assert(!(Tile::kW % kWarpSize), "Contiguous dimension must be divisible by the warp size"); - - /// Warps strip-mined across strided dimension - static int const kWarpsStrided = __NV_STD_MIN(kWarpCount, Tile::kH); - - /// Warps stripmined contiguous dimension - static int const kWarpsContiguous = kWarpCount / kWarpsStrided; - - /// Arrangement of threads - typedef Shape<1, kWarpsStrided, kWarpsContiguous * kWarpSize> ThreadShape; - - /// The same warp rakes along the contiguous dimension - typedef Shape<1, kWarpsStrided, kWarpSize> Delta; - - /// Number of iterations - typedef Shape<1, Tile::kH / Delta::kH, Tile::kW / ThreadShape::kW> Iterations; - - /// Computes the thread offset in (H, W) based on thread ID - struct ThreadOffset { - /// Basic thread offset function computed from a thread shape - CUTLASS_HOST_DEVICE - Coord<4> operator()() const { - int tid = threadIdx.x; - int warp = (tid / kWarpSize); - int lane = (tid % kWarpSize); - - static int const kWarpSpanContiguous = kWarpSize * Iterations::kW; - - int warp_w = (warp % kWarpsContiguous); - int warp_h = (warp / kWarpsContiguous); - - return make_Coord(0, warp_h, lane + kWarpSpanContiguous * warp_w, 0); - } - }; -}; - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Chooses 'best' shape to enable warp raking along contiguous dimension if possible. -template <typename Tile_, int Threads> -struct TileTraitsStandard { - /// Shape of tile - typedef Tile_ Tile; - - /// Number of participating threads - static int const kThreads = Threads; - - /// Hard-coded warp size - static int const kWarpSize = 32; - - /// Number of participating warps - static int const kWarpCount = kThreads / kWarpSize; - - // Static assertions - static_assert(!(ShapeCount<Tile>::kDhw % kThreads), - "Tiling undefined if elements not divisible by threads."); - - /// Choose the stride-major contiguous tiling if the contiguous dimension is - /// smaller than the warp size. Otherwise, if it is divisible by the warp size, - /// choose the warp rake arrangement. - typedef typename platform::conditional < - Tile::kW<kWarpSize, - TileTraitsStrideMajor<Tile, Threads>, - typename platform::conditional<!(Tile::kW % kWarpSize), - TileTraitsWarpRake<Tile, Threads>, - TileTraitsContiguousMajor<Tile, Threads> >::type>:: - type Traits; - - /// Delta between accesses - typedef typename Traits::Delta Delta; - - /// Delta between each thread's access - /// TODO MTA this is wrong for sure, but Delta is used for stride computation at the moment - typedef Delta ImmediateOffsetStrides; - - /// Number of accesses - typedef typename Traits::Iterations Iterations; - - /// Thread offset functor - typedef typename Traits::ThreadOffset ThreadOffset; -}; - -/////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace cutlass diff --git a/cutlass-example/cutlass/util/cutlass_math.h b/cutlass-example/cutlass/util/cutlass_math.h deleted file mode 100644 index 0ecdc43..0000000 --- a/cutlass-example/cutlass/util/cutlass_math.h +++ /dev/null @@ -1,131 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ - -#pragma once - -/** - * \file - * \brief Math utilities - */ - -#include <cutlass/util/platform.h> - -namespace cutlass { - -/****************************************************************************** - * Static math utilities - ******************************************************************************/ - -/** - * Statically determine if N is a power-of-two - */ -template <int N> -struct is_pow2 : platform::integral_constant<bool, (N & (N - 1)) == 0> {}; - -/** - * Statically determine log2(N), rounded down - */ -template <int N, int CurrentVal = N, int Count = 0> -struct log2_down { - /// Static logarithm value - enum { value = log2_down<N, (CurrentVal >> 1), Count + 1>::value }; -}; - -// Base case -template <int N, int Count> -struct log2_down<N, 1, Count> { - enum { value = Count }; -}; - -/** - * Statically determine log2(N), rounded up - */ -template <int N, int CurrentVal = N, int Count = 0> -struct log2_up { - /// Static logarithm value - enum { value = log2_up<N, (CurrentVal >> 1), Count + 1>::value }; -}; - -// Base case -template <int N, int Count> -struct log2_up<N, 1, Count> { - enum { value = ((1 << Count) < N) ? Count + 1 : Count }; -}; - -/** - * Statically estimate sqrt(N) to the nearest power-of-two - */ -template <int N> -struct sqrt_est { - enum { value = 1 << (log2_up<N>::value / 2) }; -}; - -/** - * For performing a constant-division with a compile-time assertion that the - * Divisor evenly-divides the Dividend. - */ -template <int Dividend, int Divisor> -struct divide_assert { - enum { value = Dividend / Divisor }; - - static_assert((Dividend % Divisor == 0), "Not an even multiple"); -}; - -/****************************************************************************** - * Rounding - ******************************************************************************/ - -/** - * Round dividend up to the nearest multiple of divisor - */ -template <typename dividend_t, typename divisor_t> -CUTLASS_HOST_DEVICE dividend_t round_nearest(dividend_t dividend, divisor_t divisor) { - return ((dividend + divisor - 1) / divisor) * divisor; -} - -/** - * Greatest common divisor - */ -template <typename value_t> -CUTLASS_HOST_DEVICE value_t gcd(value_t a, value_t b) { - for (;;) { - if (a == 0) return b; - b %= a; - if (b == 0) return a; - a %= b; - } -} - -/** - * Least common multiple - */ -template <typename value_t> -CUTLASS_HOST_DEVICE value_t lcm(value_t a, value_t b) { - value_t temp = gcd(a, b); - - return temp ? (a / temp * b) : 0; -} - -} // namespace cutlass diff --git a/cutlass-example/cutlass/util/debug.h b/cutlass-example/cutlass/util/debug.h deleted file mode 100644 index 6055e3f..0000000 --- a/cutlass-example/cutlass/util/debug.h +++ /dev/null @@ -1,122 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ - -#pragma once - -/** - * \file - * \brief Debugging and logging functionality - */ - -#include <stdio.h> - -namespace cutlass { - -/****************************************************************************** - * Debug and logging macros - ******************************************************************************/ - -/** - * Formats and prints the given message to stdout - */ -#if !defined(CUDA_LOG) -#if !defined(__CUDA_ARCH__) -#define CUDA_LOG(format, ...) printf(format, __VA_ARGS__) -#else -#define CUDA_LOG(format, ...) \ - printf("[block (%d,%d,%d), thread (%d,%d,%d)]: " format, \ - blockIdx.x, \ - blockIdx.y, \ - blockIdx.z, \ - threadIdx.x, \ - threadIdx.y, \ - threadIdx.z, \ - __VA_ARGS__); -#endif -#endif - -/** - * Formats and prints the given message to stdout only if DEBUG is defined - */ -#if !defined(CUDA_LOG_DEBUG) -#ifdef DEBUG -#define CUDA_LOG_DEBUG(format, ...) CUDA_LOG(format, __VA_ARGS__) -#else -#define CUDA_LOG_DEBUG(format, ...) -#endif -#endif - -/** - * \brief The corresponding error message is printed to \p stderr (or \p stdout in device code) - * along with the supplied source context. - * - * \return The CUDA error. - */ -__host__ CUTLASS_DEVICE cudaError_t cuda_perror_impl(cudaError_t error, - const char* filename, - int line) { - (void)filename; - (void)line; - if (error) { -#if !defined(__CUDA_ARCH__) - fprintf( - stderr, "CUDA error %d [%s, %d]: %s\n", error, filename, line, cudaGetErrorString(error)); - fflush(stderr); -#else - printf("CUDA error %d [%s, %d]\n", error, filename, line); -#endif - } - return error; -} - -/** - * \brief Perror macro - */ -#ifndef CUDA_PERROR -#define CUDA_PERROR(e) cuda_perror_impl((cudaError_t)(e), __FILE__, __LINE__) -#endif - -/** - * \brief Perror macro with exit - */ -#ifndef CUDA_PERROR_EXIT -#define CUDA_PERROR_EXIT(e) \ - if (cuda_perror_impl((cudaError_t)(e), __FILE__, __LINE__)) { \ - exit(1); \ - } -#endif - -/** - * \brief Perror macro only if DEBUG is defined - */ -#ifndef CUDA_PERROR_DEBUG -#ifdef DEBUG -#define CUDA_PERROR_DEBUG(e) CUDA_PERROR(e) -#else -#define CUDA_PERROR_DEBUG(e) (e) -#endif -#endif - -} // namespace cutlass diff --git a/cutlass-example/cutlass/util/platform.h b/cutlass-example/cutlass/util/platform.h deleted file mode 100644 index 2a44c10..0000000 --- a/cutlass-example/cutlass/util/platform.h +++ /dev/null @@ -1,801 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ - -#pragma once - -/** - * \file - * \brief C++ features that may be otherwise unimplemented for CUDA device functions. - * - * This file has three components: - * - * (1) Macros: - * - Empty macro defines for C++ keywords not supported by the current - * version of C++. These simply allow compilation to proceed (but do - * not provide the added semantics). - * - \p noexcept - * - \p constexpr - * - \p nullptr - * - \p static_assert - * - * - Macro functions that we need in constant expressions because the - * C++ equivalents require constexpr compiler support. These are - * prefixed with \p __NV_STD_* - * - \p __NV_STD_MAX - * - \p __NV_STD_MIN - * - * (2) Re-implementations of STL functions and types: - * - C++ features that need the \p __device__ annotation. These are - * placed into the \p platform namespace. - * - \p plus - * - \p less - * - \p greater - * - \p min - * - \p max - * - \p methods on std::pair (==, !=, <, <=, >, >=, and make_pair()) - * - * (3) Stop-gap implementations of unsupported STL functions and types: - * - STL functions and types defined by C++ 11/14/17/etc. that are not - * provided by the current version of C++. These are placed into the - * \p platform namespace - * - \p integral_constant - * - \p nullptr_t - * - \p true_type - * - \p false_type - * - \p bool_constant - * - \p enable_if - * - \p conditional - * - \p is_same - * - \p is_base_of - * - \p remove_const - * - \p remove_volatile - * - \p remove_cv - * - \p is_volatile - * - \p is_pointer - * - \p is_void - * - \p is_integral - * - \p is_floating_point - * - \p is_arithmetic - * - \p is_fundamental - * - \p is_trivially_copyable - * - \p alignment_of - * - \p aligned_storage - * - * (4) Functions and types that are STL-like (but aren't in the STL): - * - \p TODO: min and max functors? - * - * The idea is that, as we drop support for older compilers, we can simply #define - * the \p __NV_STD_XYZ macros and \p platform namespace to alias their C++ - * counterparts (or trivially find-and-replace their occurrences in code text). - */ - -//----------------------------------------------------------------------------- -// Dependencies -//----------------------------------------------------------------------------- - -#include <stdint.h> - -#if !defined(__CUDACC_RTC__) -//----------------------------------------------------------------------------- -// Include STL files that platform provides functionality for -//----------------------------------------------------------------------------- - -#include <algorithm> // Minimum/maximum operations -#include <cstddef> // nullptr_t -#include <functional> // Arithmetic operations -#include <utility> // For methods on std::pair -#if (!defined(_MSC_VER) && (__cplusplus >= 201103L)) || (defined(_MSC_VER) && (_MS_VER >= 1500)) -#include <type_traits> // For integral constants, conditional metaprogramming, and type traits -#endif - -#include <cutlass/cutlass.h> - -#endif -/****************************************************************************** - * Macros - ******************************************************************************/ -//----------------------------------------------------------------------------- -// Keywords -//----------------------------------------------------------------------------- - -/// noexcept, constexpr -#if (!defined(_MSC_VER) && (__cplusplus < 201103L)) || (defined(_MSC_VER) && (_MSC_VER < 1900)) -#ifndef noexcept -#define noexcept -#endif -#ifndef constexpr -#define constexpr -#endif -#endif - -/// nullptr -#if (!defined(_MSC_VER) && (__cplusplus < 201103L)) || (defined(_MSC_VER) && (_MSC_VER < 1310)) -#ifndef nullptr -#define nullptr 0 -#endif -#endif - -/// static_assert -#if (!defined(_MSC_VER) && (__cplusplus < 201103L)) || (defined(_MSC_VER) && (_MSC_VER < 1600)) -#ifndef static_assert -#define __platform_cat_(a, b) a##b -#define __platform_cat(a, b) __platform_cat_(a, b) -#define static_assert(__e, __m) typedef int __platform_cat(AsSeRt, __LINE__)[(__e) ? 1 : -1] -#endif -#endif - -//----------------------------------------------------------------------------- -// Functions -//----------------------------------------------------------------------------- - -/// Select maximum(a, b) -#ifndef __NV_STD_MAX -#define __NV_STD_MAX(a, b) (((b) > (a)) ? (b) : (a)) -#endif - -/// Select minimum(a, b) -#ifndef __NV_STD_MIN -#define __NV_STD_MIN(a, b) (((b) < (a)) ? (b) : (a)) -#endif - -/****************************************************************************** - * Re-implementations - ******************************************************************************/ -namespace cutlass { -namespace platform { - -//----------------------------------------------------------------------------- -// Arithmetic operations, comparisons <functional> -//----------------------------------------------------------------------------- - -/// platform::plus -template <typename T> -struct plus { - CUTLASS_HOST_DEVICE constexpr T operator()(const T& lhs, const T& rhs) const { return lhs + rhs; } -}; - -/// std::less -template <typename T> -struct less { - CUTLASS_HOST_DEVICE constexpr bool operator()(const T& lhs, const T& rhs) const { - return lhs < rhs; - } -}; - -/// std::greater -template <typename T> -struct greater { - CUTLASS_HOST_DEVICE constexpr bool operator()(const T& lhs, const T& rhs) const { - return lhs > rhs; - } -}; - -//----------------------------------------------------------------------------- -// Minimum/maximum operations <algorithm> -//----------------------------------------------------------------------------- - -/// std::min -template <typename T> -CUTLASS_HOST_DEVICE constexpr const T& min(const T& a, const T& b) { - return (b < a) ? b : a; -} - -/// std::max -template <typename T> -CUTLASS_HOST_DEVICE constexpr const T& max(const T& a, const T& b) { - return (a < b) ? b : a; -} - -#if !defined(__CUDACC_RTC__) -//----------------------------------------------------------------------------- -// Methods on std::pair -//----------------------------------------------------------------------------- - -using std::pair; - -template <class T1, class T2> -CUTLASS_HOST_DEVICE constexpr bool operator==(const pair<T1, T2>& lhs, const pair<T1, T2>& rhs) { - return (lhs.first == rhs.first) && (lhs.second == rhs.second); -} - -template <class T1, class T2> -CUTLASS_HOST_DEVICE constexpr bool operator!=(const pair<T1, T2>& lhs, const pair<T1, T2>& rhs) { - return (lhs.first != rhs.first) && (lhs.second != rhs.second); -} - -template <class T1, class T2> -CUTLASS_HOST_DEVICE constexpr bool operator<(const pair<T1, T2>& lhs, const pair<T1, T2>& rhs) { - return (lhs.first < rhs.first) ? true : (rhs.first < lhs.first) ? false - : (lhs.second < rhs.second); -} - -template <class T1, class T2> -CUTLASS_HOST_DEVICE constexpr bool operator<=(const pair<T1, T2>& lhs, const pair<T1, T2>& rhs) { - return !(rhs < lhs); -} - -template <class T1, class T2> -CUTLASS_HOST_DEVICE constexpr bool operator>(const pair<T1, T2>& lhs, const pair<T1, T2>& rhs) { - return (rhs < lhs); -} - -template <class T1, class T2> -CUTLASS_HOST_DEVICE constexpr bool operator>=(const pair<T1, T2>& lhs, const pair<T1, T2>& rhs) { - return !(lhs < rhs); -} - -template <class T1, class T2> -CUTLASS_HOST_DEVICE std::pair<T1, T2> make_pair(T1 t, T2 u) { - std::pair<T1, T2> retval; - retval.first = t; - retval.second = u; - return retval; -} -#endif - -} // namespace platform - -/****************************************************************************** - * Implementations of C++ 11/14/17/... STL features - ******************************************************************************/ - -namespace platform { - -//----------------------------------------------------------------------------- -// Integral constant helper types <type_traits> -//----------------------------------------------------------------------------- - -#if (!defined(_MSC_VER) && (__cplusplus < 201103L)) || (defined(_MSC_VER) && (_MSC_VER < 1500)) - -/// std::integral_constant -template <typename value_t, value_t V> -struct integral_constant; - -/// std::integral_constant -template <typename value_t, value_t V> -struct integral_constant { - static const value_t value = V; - - typedef value_t value_type; - typedef integral_constant<value_t, V> type; - - CUTLASS_HOST_DEVICE operator value_type() const { return value; } - - CUTLASS_HOST_DEVICE const value_type operator()() const { return value; } -}; - -#else - -using std::integral_constant; -using std::pair; - -#endif - -/// The type used as a compile-time boolean with true value. -typedef integral_constant<bool, true> true_type; - -/// The type used as a compile-time boolean with false value. -typedef integral_constant<bool, false> false_type; - -#if (!defined(_MSC_VER) && (__cplusplus <= 201402L)) || (defined(_MSC_VER) && (_MSC_VER < 1900)) - -/// std::bool_constant -template <bool V> -struct bool_constant : platform::integral_constant<bool, V> {}; - -#else - -using std::bool_constant; - -#endif - -#if (!defined(_MSC_VER) && (__cplusplus < 201103L)) || (defined(_MSC_VER) && (_MSC_VER < 1700)) - -/// std::nullptr_t -struct nullptr_t {}; - -#else - -using std::nullptr_t; - -#endif - -//----------------------------------------------------------------------------- -// Conditional metaprogramming <type_traits> -//----------------------------------------------------------------------------- - -#if (!defined(_MSC_VER) && (__cplusplus < 201103L)) || (defined(_MSC_VER) && (_MSC_VER < 1600)) - -/// std::enable_if (true specialization) -template <bool C, typename T = void> -struct enable_if { - typedef T type; -}; - -/// std::enable_if (false specialization) -template <typename T> -struct enable_if<false, T> {}; - -/// std::conditional (true specialization) -template <bool B, class T, class F> -struct conditional { - typedef T type; -}; - -/// std::conditional (false specialization) -template <class T, class F> -struct conditional<false, T, F> { - typedef F type; -}; - -#else - -using std::enable_if; -using std::conditional; - -#endif - -//----------------------------------------------------------------------------- -// Const/volatility specifiers <type_traits> -//----------------------------------------------------------------------------- - -#if (!defined(_MSC_VER) && (__cplusplus < 201103L)) || (defined(_MSC_VER) && (_MSC_VER < 1500)) - -/// std::remove_const (non-const specialization) -template <typename T> -struct remove_const { - typedef T type; -}; - -/// std::remove_const (const specialization) -template <typename T> -struct remove_const<const T> { - typedef T type; -}; - -/// std::remove_volatile (non-volatile specialization) -template <typename T> -struct remove_volatile { - typedef T type; -}; - -/// std::remove_volatile (volatile specialization) -template <typename T> -struct remove_volatile<volatile T> { - typedef T type; -}; - -/// std::remove_cv -template <typename T> -struct remove_cv { - typedef typename remove_volatile<typename remove_const<T>::type>::type type; -}; - -#else - -using std::remove_const; -using std::remove_volatile; -using std::remove_cv; - -#endif - -//----------------------------------------------------------------------------- -// Type relationships <type_traits> -//----------------------------------------------------------------------------- - -#if (!defined(_MSC_VER) && (__cplusplus < 201103L)) || (defined(_MSC_VER) && (_MSC_VER < 1500)) - -/// std::is_same (false specialization) -template <typename A, typename B> -struct is_same : false_type {}; - -/// std::is_same (true specialization) -template <typename A> -struct is_same<A, A> : true_type {}; - -/// Helper for std::is_base_of -template <typename BaseT, typename DerivedT> -struct is_base_of_helper { - typedef char (&yes)[1]; - typedef char (&no)[2]; - - template <typename B, typename D> - struct dummy { - CUTLASS_HOST_DEVICE operator B*() const; - CUTLASS_HOST_DEVICE operator D*(); - }; - - template <typename T> - CUTLASS_HOST_DEVICE static yes check(DerivedT*, T); - - CUTLASS_HOST_DEVICE static no check(BaseT*, int); - - static const bool value = sizeof(check(dummy<BaseT, DerivedT>(), int())) == sizeof(yes); -}; - -/// std::is_base_of -template <typename BaseT, typename DerivedT> -struct is_base_of - : integral_constant<bool, - (is_base_of_helper<typename remove_cv<BaseT>::type, - typename remove_cv<DerivedT>::type>::value) || - (is_same<typename remove_cv<BaseT>::type, - typename remove_cv<DerivedT>::type>::value)> {}; - -#else - -using std::is_same; -using std::is_base_of; - -#endif - -//----------------------------------------------------------------------------- -// Type properties <type_traits> -//----------------------------------------------------------------------------- - -#if (!defined(_MSC_VER) && (__cplusplus < 201103L)) || (defined(_MSC_VER) && (_MSC_VER < 1500)) - -/// std::is_volatile -template <typename T> -struct is_volatile : false_type {}; -template <typename T> -struct is_volatile<volatile T> : true_type {}; - -/// Helper for std::is_pointer (false specialization) -template <typename T> -struct is_pointer_helper : false_type {}; - -/// Helper for std::is_pointer (true specialization) -template <typename T> -struct is_pointer_helper<T*> : true_type {}; - -/// std::is_pointer -template <typename T> -struct is_pointer : is_pointer_helper<typename remove_cv<T>::type> {}; - -/// std::is_void -template <typename T> -struct is_void : is_same<void, typename remove_cv<T>::type> {}; - -/// std::is_integral -template <typename T> -struct is_integral : false_type {}; -template <> -struct is_integral<char> : true_type {}; -template <> -struct is_integral<signed char> : true_type {}; -template <> -struct is_integral<unsigned char> : true_type {}; -template <> -struct is_integral<short> : true_type {}; -template <> -struct is_integral<unsigned short> : true_type {}; -template <> -struct is_integral<int> : true_type {}; -template <> -struct is_integral<unsigned int> : true_type {}; -template <> -struct is_integral<long> : true_type {}; -template <> -struct is_integral<unsigned long> : true_type {}; -template <> -struct is_integral<long long> : true_type {}; -template <> -struct is_integral<unsigned long long> : true_type {}; -template <typename T> -struct is_integral<volatile T> : is_integral<T> {}; -template <typename T> -struct is_integral<const T> : is_integral<T> {}; -template <typename T> -struct is_integral<const volatile T> : is_integral<T> {}; - -/// std::is_floating_point -template <typename T> -struct is_floating_point - : integral_constant<bool, - (is_same<float, typename remove_cv<T>::type>::value || - is_same<double, typename remove_cv<T>::type>::value)> {}; - -/// std::is_arithmetic -template <typename T> -struct is_arithmetic - : integral_constant<bool, (is_integral<T>::value || is_floating_point<T>::value)> {}; - -/// std::is_fundamental -template <typename T> -struct is_fundamental - : integral_constant<bool, - (is_arithmetic<T>::value || is_void<T>::value || - is_same<nullptr_t, typename remove_cv<T>::type>::value)> {}; - -#else - -using std::is_volatile; -using std::is_pointer; -using std::is_void; -using std::is_integral; -using std::is_floating_point; -using std::is_arithmetic; -using std::is_fundamental; - -#endif - -#if (!defined(_MSC_VER) && (__cplusplus < 201103L)) || (defined(_MSC_VER) && (_MSC_VER < 1800)) || \ - (defined(__GNUG__) && (__GNUC__ < 5)) - -/** - * std::is_trivially_copyable - * - * This implementation only evaluates true if T is fundamental or pointer - * - * Without help from partial template specializations provided by the user for - * a specific class or struct, this trait will never report that the specified - * class or struct is trivially-copyable ; this is always safe, - * if possibly sub-optimal. - */ -template <typename T> -struct is_trivially_copyable - : integral_constant<bool, (is_fundamental<T>::value || is_pointer<T>::value)> {}; - -#else - -using std::is_trivially_copyable; - -#endif - -//----------------------------------------------------------------------------- -// Alignment and layout utilities -//----------------------------------------------------------------------------- - -#if (!defined(_MSC_VER) && (__cplusplus < 201103L)) || (defined(_MSC_VER) && (_MSC_VER < 1500)) - -/// std::alignment_of -template <typename value_t> -struct alignment_of { - struct pad { - value_t val; - char byte; - }; - - enum { value = sizeof(pad) - sizeof(value_t) }; -}; - -#else - -template <typename value_t> -struct alignment_of : std::alignment_of<value_t> {}; - -#endif - -/* 16B specializations where 32-bit Win32 host compiler disagrees with device compiler */ -template <> -struct alignment_of<int4> { - enum { value = 16 }; -}; -template <> -struct alignment_of<uint4> { - enum { value = 16 }; -}; -template <> -struct alignment_of<float4> { - enum { value = 16 }; -}; -template <> -struct alignment_of<long4> { - enum { value = 16 }; -}; -template <> -struct alignment_of<ulong4> { - enum { value = 16 }; -}; -template <> -struct alignment_of<longlong2> { - enum { value = 16 }; -}; -template <> -struct alignment_of<ulonglong2> { - enum { value = 16 }; -}; -template <> -struct alignment_of<double2> { - enum { value = 16 }; -}; -template <> -struct alignment_of<longlong4> { - enum { value = 16 }; -}; -template <> -struct alignment_of<ulonglong4> { - enum { value = 16 }; -}; -template <> -struct alignment_of<double4> { - enum { value = 16 }; -}; - -// Specializations for volatile/const qualified types -template <typename value_t> -struct alignment_of<volatile value_t> : alignment_of<value_t> {}; -template <typename value_t> -struct alignment_of<const value_t> : alignment_of<value_t> {}; -template <typename value_t> -struct alignment_of<const volatile value_t> : alignment_of<value_t> {}; - -#if (!defined(_MSC_VER) && (__cplusplus < 201103L)) || (defined(_MSC_VER) && (_MSC_VER < 1800)) - -template <size_t Align> -struct aligned_chunk; -template <> -struct __align__(1) aligned_chunk<1> { - uint8_t buff; -}; -template <> -struct __align__(2) aligned_chunk<2> { - uint16_t buff; -}; -template <> -struct __align__(4) aligned_chunk<4> { - uint32_t buff; -}; -template <> -struct __align__(8) aligned_chunk<8> { - uint32_t buff[2]; -}; -template <> -struct __align__(16) aligned_chunk<16> { - uint32_t buff[4]; -}; -template <> -struct __align__(32) aligned_chunk<32> { - uint32_t buff[8]; -}; -template <> -struct __align__(64) aligned_chunk<64> { - uint32_t buff[16]; -}; -template <> -struct __align__(128) aligned_chunk<128> { - uint32_t buff[32]; -}; -template <> -struct __align__(256) aligned_chunk<256> { - uint32_t buff[64]; -}; -template <> -struct __align__(512) aligned_chunk<512> { - uint32_t buff[128]; -}; -template <> -struct __align__(1024) aligned_chunk<1024> { - uint32_t buff[256]; -}; -template <> -struct __align__(2048) aligned_chunk<2048> { - uint32_t buff[512]; -}; -template <> -struct __align__(4096) aligned_chunk<4096> { - uint32_t buff[1024]; -}; - -/// std::aligned_storage -template <size_t Len, size_t Align> -struct aligned_storage { - typedef aligned_chunk<Align> type[Len / sizeof(aligned_chunk<Align>)]; -}; - -#else - -using std::aligned_storage; - -#endif - -#if !defined(__CUDACC_RTC__) -/// Default deleter -template <typename T> -struct default_delete { - void operator()(T* ptr) const { delete ptr; } -}; - -/// Partial specialization for deleting array types -template <typename T> -struct default_delete<T[]> { - void operator()(T* ptr) const { delete[] ptr; } -}; - -/// std::unique_ptr -template <class T, class Deleter = default_delete<T> > -class unique_ptr { - public: - typedef T* pointer; - typedef T element_type; - typedef Deleter deleter_type; - - private: - /// Pointer to memory - pointer _ptr; - - /// Deleter - deleter_type _deleter; - - public: - unique_ptr() : _ptr(nullptr) {} - unique_ptr(pointer p) : _ptr(p) {} - - ~unique_ptr() { - if (_ptr) { - _deleter(_ptr); - } - } - /// Returns a pointer to the managed object or nullptr if no object is owned. - pointer get() const noexcept { return _ptr; } - - /// Releases ownership of the managed object, if any - pointer release() noexcept { - pointer p(_ptr); - _ptr = nullptr; - return p; - } - - /// Replaces the managed object, deleting the old object. - void reset(pointer p = pointer()) noexcept { - pointer old_ptr = _ptr; - _ptr = p; - if (old_ptr != nullptr) { - get_deleter()(old_ptr); - } - } - - /// Swaps the managed objects with *this and another unique_ptr - void swap(unique_ptr& other) noexcept { std::swap(_ptr, other._ptr); } - - /// Returns the deleter object - Deleter& get_deleter() noexcept { return _deleter; } - - /// Returns the deleter object - Deleter const& get_deleter() const noexcept { return _deleter; } - - /// Checks whether an object is owned - operator bool() const noexcept { return _ptr != nullptr; } - - /// Dereferences the unique_ptr - T& operator*() const { return *_ptr; } - - /// Returns a pointer to the managed object - pointer operator->() const noexcept { return _ptr; } - - /// Array access to managed object - T& operator[](size_t i) const { return _ptr[i]; } -}; - -/// Specializes the swap algorithm -template <typename T, typename Deleter> -void swap(unique_ptr<T, Deleter>& lhs, unique_ptr<T, Deleter>& rhs) noexcept { - lhs.swap(rhs); -} -#endif - -}; // namespace platform -}; // namespace cutlass diff --git a/cutlass-example/cutlass/vector.h b/cutlass-example/cutlass/vector.h deleted file mode 100644 index a66dfde..0000000 --- a/cutlass-example/cutlass/vector.h +++ /dev/null @@ -1,229 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Defines a 1D vector of elements held in the registers of each thread. -*/ -#pragma once - -#if !defined(__CUDACC_RTC__) || defined(CUTLASS_NVRTC_HAS_FP16) -#include <cuda_fp16.h> -#endif - -#include <cutlass/util/platform.h> - -namespace cutlass { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <size_t kAlignment_> -struct AlignedStruct {}; - -template <> -struct __align__(1) AlignedStruct<1>{}; -template <> -struct __align__(2) AlignedStruct<2>{}; -template <> -struct __align__(4) AlignedStruct<4>{}; -template <> -struct __align__(8) AlignedStruct<8>{}; -template <> -struct __align__(16) AlignedStruct<16>{}; -template <> -struct __align__(32) AlignedStruct<32>{}; -template <> -struct __align__(64) AlignedStruct<64>{}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, int kLanes_> -union Vector { - /// The scalar type. - typedef Scalar_ Scalar; - - /// The number of elements in the vector. - enum { kLanes = kLanes_ }; - /// The size of the vector. - enum { kVectorSize = kLanes * (int)sizeof(Scalar) }; - /// The number of registers needed to store the vector. - enum { kRegisters = kVectorSize < 4 ? 1 : kVectorSize / 4 }; - - // Make sure that the vector type makes sense. - static_assert(kVectorSize <= 16, "Vector type is too large"); - - /// The aligned storage to make sure we have good alignment. - AlignedStruct<kVectorSize> aligned_; - /// The associated array of scalars. - Scalar scalars[kLanes]; - /// The data in registers. - uint32_t registers[kRegisters]; - - /// Accessor to the ith lane. - CUTLASS_DEVICE Scalar const& operator[](uint32_t i) const { return scalars[i]; } - /// Accessor to the ith lane. - CUTLASS_DEVICE Scalar& operator[](uint32_t i) { return scalars[i]; } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -#if !defined(__CUDACC_RTC__) || defined(CUTLASS_NVRTC_HAS_FP16) - -template <int kLanes_> -union Vector<half, kLanes_> { - /// The scalar type. - typedef half Scalar; - - /// The number of elements in the vector. - enum { kLanes = kLanes_ }; - /// The size of the vector. - enum { kVectorSize = kLanes * (int)sizeof(Scalar) }; - /// The number of registers needed to store the vector. - enum { kRegisters = kVectorSize < 4 ? 1 : kVectorSize / 4 }; - - // Make sure that the vector type makes sense. - static_assert(kVectorSize <= size_t(16), "Vector type is too large"); - - /// The aligned storage to make sure we have good alignment. - AlignedStruct<kVectorSize> aligned_; - /// The associated array of scalars. - uint16_t scalars[kLanes]; - /// The data in registers. - uint32_t registers[kRegisters]; - - /// Accessor to the ith lane. - CUTLASS_DEVICE Scalar const& operator[](uint32_t i) const { - return reinterpret_cast<Scalar const&>(scalars[i]); - } - /// Accessor to the ith lane. - CUTLASS_DEVICE Scalar& operator[](uint32_t i) { return reinterpret_cast<Scalar&>(scalars[i]); } -}; - -#endif - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_> -CUTLASS_DEVICE void make_zero(Scalar_& x) { - x = Scalar_(0); -} - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Element_, int kLanes_ = 1> -struct Vectorize { - typedef Vector<Element_, kLanes_> Type; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Element_> -struct Vectorize<Element_, 1> { - typedef Element_ Type; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename Scalar_, int kLanes_> -CUTLASS_DEVICE void make_zero(Vector<Scalar_, kLanes_>& vec) { - for (int i = 0; i < Vector<Scalar_, kLanes_>::kRegisters; ++i) { - vec.registers[i] = 0; - } -} - -//////////////////////////////////////////////////////////////////////////////////////////////////// -// -// cutlass::Extent similar to std::extent but applicable to CUTLASS types -// - -/// Returns the extent of a scalar or vector -template <typename T> -struct Extent { - static size_t const kValue = 1; -}; - -/// Returns the number of lanes of a vector if need be -template <typename T, int Lanes> -struct Extent<Vector<T, Lanes> > { - static size_t const kValue = Lanes; -}; - -/// Returns the number of lanes of a vector if need be -template <typename T, int Lanes> -struct Extent<Vector<T, Lanes> const> { - static size_t const kValue = Lanes; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Traits describing properties of vectors and scalar-as-vectors -template <typename T> -struct VectorTraits { - /// Scalar type - typedef T Scalar; - - /// Number of lanes of vector - static int const kLanes = 1; - - /// True if the type is actually a cutlass::Vector, otherwise false - static bool const IsVector = false; - - /// Type that is always a vector - typedef Vector<T, 1> Vector; -}; - -/// Partial specialization for actual cutlass::Vector -template <typename T, int Lanes> -struct VectorTraits<Vector<T, Lanes> > { - /// Scalar type - typedef T Scalar; - - /// Number of lanes of vector - static int const kLanes = Lanes; - - /// Type is actually a cutlass::Vector - static bool const IsVector = true; - - /// Type that is always a Vector - typedef Vector<T, Lanes> Vector; -}; - -/// Partial specialization for actual cutlass::Vector -template <typename T, int Lanes> -struct VectorTraits<Vector<T, Lanes> const> { - /// Scalar type - typedef T Scalar; - - /// Number of lanes of vector - static int const kLanes = Lanes; - - /// Type is actually a cutlass::Vector - static bool const IsVector = true; - - /// Type that is always a Vector - typedef Vector<T, Lanes> Vector; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace cutlass diff --git a/cutlass-example/cutlass/wmma_matrix.h b/cutlass-example/cutlass/wmma_matrix.h deleted file mode 100644 index c4d8a0b..0000000 --- a/cutlass-example/cutlass/wmma_matrix.h +++ /dev/null @@ -1,193 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Abstractions for loading and storing matrices using the CUDA WMMA API. -*/ -#pragma once - -#if defined(__CUDACC__) && (!defined(__CUDA_ARCH__) || __CUDA_ARCH__ >= 700) - -// Dependent header files should use the following macro to guard all code using -// nvcuda::wmma:: to enable compilation for CUDA Compute Capabilities < sm_70. -// Earlier shader models not support Tensor Cores. -#define CUTLASS_USE_WMMA_API - -#include "stdio.h" - -#include <crt/mma.h> -#include <cutlass/fragment.h> -#include <cutlass/load_store.h> -#include <cutlass/matrix_traits.h> -#include <cutlass/shape.h> -#include <cutlass/vector.h> - -namespace cutlass { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Statically maps cutlass::MatrixLayout => nvcuda::wmma layout tags -template <MatrixLayout::Kind kLayout_> -struct WmmaLayout { - typedef nvcuda::wmma::col_major Layout; -}; - -/// Statically maps cutlass::MatrixLayout => nvcuda::wmma layout tags -template <> -struct WmmaLayout<MatrixLayout::kRowMajor> { - typedef nvcuda::wmma::row_major Layout; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Adapter to nvcuda::wmma fragment load and store operations -template <GemmOperand::Kind kOperand_, - MatrixLayout::Kind kLayout_, - typename Scalar_, - typename WmmaShape_> -struct WmmaMatrix {}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Adapter to nvcuda::wmma fragment accessors for A operand -template <MatrixLayout::Kind kLayout_, typename Scalar_, typename WmmaShape_> -struct WmmaMatrix<GemmOperand::kA, kLayout_, Scalar_, WmmaShape_> - : public nvcuda::wmma::fragment< - /// The nvcuda::wmma operand name. - nvcuda::wmma::matrix_a, - /// The dimensions. - WmmaShape_::kW, - WmmaShape_::kH, - WmmaShape_::kD, - /// The scalar. - Scalar_, - /// The layout. - typename WmmaLayout<kLayout_>::Layout> { - /// This type. - typedef WmmaMatrix<GemmOperand::kA, kLayout_, Scalar_, WmmaShape_> This_; - - /// Fill-in the element. - CUTLASS_DEVICE This_& operator=(Scalar_ const& x) { - nvcuda::wmma::fill_fragment(*this, x); - return *this; - } - - /// Load from memory. - CUTLASS_DEVICE void load(Scalar_ const* pointer, int const stride) { - nvcuda::wmma::load_matrix_sync(*this, pointer, stride); - } - - /// Store to memory. - CUTLASS_DEVICE void store(Scalar_* pointer, int const stride) const { - nvcuda::wmma::store_matrix_sync(pointer, *this, stride); - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Adapter to nvcuda::wmma fragment accessors for B operand -template <MatrixLayout::Kind kLayout_, typename Scalar_, typename WmmaShape_> -struct WmmaMatrix<GemmOperand::kB, kLayout_, Scalar_, WmmaShape_> - : public nvcuda::wmma::fragment< - /// The nvcuda::wmma operand name. - nvcuda::wmma::matrix_b, - /// The dimensions. - WmmaShape_::kW, - WmmaShape_::kH, - WmmaShape_::kD, - /// The scalar. - Scalar_, - /// The layout. - typename WmmaLayout<kLayout_>::Layout> { - /// This type. - typedef WmmaMatrix<GemmOperand::kB, kLayout_, Scalar_, WmmaShape_> This_; - - /// Fill-in the element. - CUTLASS_DEVICE This_& operator=(Scalar_ const& x) { - nvcuda::wmma::fill_fragment(*this, x); - return *this; - } - - /// Load from memory. - CUTLASS_DEVICE void load(Scalar_ const* pointer, int const stride) { - nvcuda::wmma::load_matrix_sync(*this, pointer, stride); - } - - /// Store to memory. - CUTLASS_DEVICE void store(Scalar_* pointer, int const stride) const { - nvcuda::wmma::store_matrix_sync(pointer, *this, stride); - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -/// Adapter to nvcuda::wmma fragment accessors for C operand -template <MatrixLayout::Kind kLayout_, typename Scalar_, typename WmmaShape_> -struct WmmaMatrix<GemmOperand::kC, kLayout_, Scalar_, WmmaShape_> - : public nvcuda::wmma::fragment< - /// The nvcuda::wmma operand name. - nvcuda::wmma::accumulator, - /// The dimensions. - WmmaShape_::kW, - WmmaShape_::kH, - WmmaShape_::kD, - /// The scalar. - Scalar_> { - /// This type. - typedef WmmaMatrix<GemmOperand::kC, kLayout_, Scalar_, WmmaShape_> This_; - /// The layout. - static MatrixLayout::Kind const kLayout = kLayout_; - - /// Fill-in the element. - CUTLASS_DEVICE This_& operator=(Scalar_ const& x) { - nvcuda::wmma::fill_fragment(*this, x); - return *this; - } - - /// Load from memory. - CUTLASS_DEVICE void load(Scalar_ const* pointer, int const stride) { - bool const kIsRowMajor = kLayout == MatrixLayout::kRowMajor; - nvcuda::wmma::load_matrix_sync( - *this, - pointer, - stride, - kIsRowMajor ? nvcuda::wmma::mem_row_major : nvcuda::wmma::mem_col_major); - } - - /// Store to memory. - CUTLASS_DEVICE void store(Scalar_* pointer, int const stride) const { - bool const kIsRowMajor = kLayout == MatrixLayout::kRowMajor; - nvcuda::wmma::store_matrix_sync( - pointer, - *this, - stride, - kIsRowMajor ? nvcuda::wmma::mem_row_major : nvcuda::wmma::mem_col_major); - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace cutlass - -#endif // defined CUTLASS_USE_WMMA_API diff --git a/cutlass-example/cutlass_example.cu b/cutlass-example/cutlass_example.cu deleted file mode 100644 index 0e5722c..0000000 --- a/cutlass-example/cutlass_example.cu +++ /dev/null @@ -1,355 +0,0 @@ -//added by me -#include <cutlass/wmma_matrix.h> -#include <cutlass/gemm/gemm.h> -#include <cutlass/gemm/wmma_gemm_traits.h> -#include <gemm_testbed.h> -#include <gemm.h> - -int main(int argc, char* argv[]) { - -#ifdef WMMA_GEMM_16x16x16_NT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(16, 16, 16); -#endif - -#ifdef WMMA_GEMM_16x16x32_NT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(16, 16, 32); -#endif - -#ifdef WMMA_GEMM_16x16x16_NN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(16, 16, 16); -#endif - - -#ifdef WMMA_GEMM_16x16x32_NN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(16, 16, 32); -#endif - -#ifdef WMMA_GEMM_16x16x16_TT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(16, 16, 16); -#endif - -#ifdef WMMA_GEMM_16x16x32_TT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(16, 16, 32); -#endif - -#ifdef WMMA_GEMM_16x16x16_TN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(16, 16, 16); -#endif - -#ifdef WMMA_GEMM_16x16x32_TN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(16, 16, 32); -#endif - -#ifdef WMMA_GEMM_32x32x32_NT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(32, 32, 32); -#endif -#ifdef WMMA_GEMM_32x32x32_NN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(32, 32, 32); -#endif -#ifdef WMMA_GEMM_32x32x32_TT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(32, 32, 32); -#endif -#ifdef WMMA_GEMM_32x32x32_TN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(32, 32, 32); -#endif - -#ifdef WMMA_GEMM_128x128x128_NT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(128, 128, 128); -#endif -#ifdef WMMA_GEMM_128x128x128_NN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(128, 128, 128); -#endif -#ifdef WMMA_GEMM_128x128x128_TT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(128, 128, 128); -#endif -#ifdef WMMA_GEMM_128x128x128_TN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<32, 16, 16> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(128, 128, 128); -#endif - -#ifdef WMMA_16x16x16_GEMM_256x256x128_NT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<32, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(256, 256, 128); -#endif - -#ifdef WMMA_16x16x16_GEMM_256x256x128_NN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<32, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(256, 256, 128); -#endif - -#ifdef WMMA_16x16x16_GEMM_256x256x128_TT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<32, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(256, 256, 128); -#endif - -#ifdef WMMA_16x16x16_GEMM_256x256x128_TN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<32, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(256, 256, 128); -#endif - -#ifdef WMMA_GEMM_256x256x256_NT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(256, 256, 256); -#endif - -#ifdef WMMA_GEMM_256x256x256_NN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(256, 256, 256); -#endif - -#ifdef WMMA_GEMM_256x256x256_TT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(256, 256, 256); -#endif - -#ifdef WMMA_GEMM_256x256x256_TN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(256, 256, 256); -#endif -#ifdef WMMA_GEMM_512x512x512_NT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(512, 512, 512); -#endif - -#ifdef WMMA_GEMM_512x512x512_NN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(512, 512, 512); -#endif - -#ifdef WMMA_GEMM_512x512x512_TT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(512, 512, 512); -#endif - -#ifdef WMMA_GEMM_512x512x512_TN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(512, 512, 512); -#endif - -#ifdef WMMA_GEMM_768x768x768_NT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(768, 768, 768); -#endif -#ifdef WMMA_GEMM_768x768x768_NN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(768, 768, 768); -#endif - -#ifdef WMMA_GEMM_768x768x768_TT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(768, 768, 768); -#endif - -#ifdef WMMA_GEMM_768x768x768_TN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(768, 768, 768); -#endif - - -#ifdef WMMA_GEMM_1024x1024x1024_NT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(1024, 1024, 1024); -#endif - -#ifdef WMMA_GEMM_1024x1024x1024_NN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(1024, 1024, 1024); -#endif - -#ifdef WMMA_GEMM_1024x1024x1024_TT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(1024, 1024, 1024); -#endif - -#ifdef WMMA_GEMM_1024x1024x1024_TN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(1024, 1024, 1024); -#endif -#ifdef WMMA_GEMM_2048x2048x2048_NT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(2048, 2048, 2048); -#endif - -#ifdef WMMA_GEMM_2048x2048x2048_NN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(2048, 2048, 2048); -#endif - -#ifdef WMMA_GEMM_2048x2048x2048_TT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(2048, 2048, 2048); -#endif - -#ifdef WMMA_GEMM_2048x2048x2048_TN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(2048, 2048, 2048); -#endif -#ifdef WMMA_GEMM_4096x4096x4096_NT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(4096, 4096, 4096); -#endif - -#ifdef WMMA_GEMM_4096x4096x4096_NN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kColumnMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(4096, 4096, 4096); -#endif - -#ifdef WMMA_GEMM_4096x4096x4096_TT - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kRowMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(4096, 4096, 4096); -#endif - -#ifdef WMMA_GEMM_4096x4096x4096_TN - typedef cutlass::gemm::WmmaGemmTraits<cutlass::MatrixLayout::kRowMajor, - cutlass::MatrixLayout::kColumnMajor, - cutlass::Shape<64, 128, 128> > - WmmaGemmTraits; - run_gemm<WmmaGemmTraits>(4096, 4096, 4096); -#endif -} - - diff --git a/cutlass-example/device_memory.h b/cutlass-example/device_memory.h deleted file mode 100644 index ab561d8..0000000 --- a/cutlass-example/device_memory.h +++ /dev/null @@ -1,178 +0,0 @@ -/****************************************************************************** - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are not permitted. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ******************************************************************************/ - -#pragma once - -/** - * \file - * \brief C++ interface to CUDA device memory management functions. - */ - -#include <memory> - -#include <cutlass/util/debug.h> -#include <cutlass/util/platform.h> -#include <exceptions.h> - -namespace cutlass { -namespace device_memory { - -/****************************************************************************** - * Allocation lifetime - ******************************************************************************/ - -/// Allocate a buffer of \p count elements of type \p T on the current CUDA device -template <typename T> -T* allocate(size_t count = 1) { - T* ptr = 0; - size_t bytes = sizeof(T) * count; - - cudaError_t cuda_error = CUDA_PERROR(cudaMalloc((void**)&ptr, bytes)); - if (cuda_error != cudaSuccess) { - throw cuda_exception("Failed to allocate memory", cuda_error); - } - - return ptr; -} - -/// Free the buffer pointed to by \p ptr -template <typename T> -void free(T* ptr) { - if (ptr) { - cudaError_t cuda_error = CUDA_PERROR(cudaFree(ptr)); - if (cuda_error != cudaSuccess) { - throw cuda_exception("Failed to free device memory", cuda_error); - } - } -} - -/****************************************************************************** - * Data movement - ******************************************************************************/ - -template <typename T> -void copy(T* dst, T const* src, size_t count, cudaMemcpyKind kind) { - size_t bytes = count * sizeof(T); - - cudaError_t cuda_error = CUDA_PERROR(cudaMemcpy(dst, src, bytes, kind)); - if (cuda_error != cudaSuccess) { - throw cuda_exception("cudaMemcpy() failed", cuda_error); - } -} - -template <typename T> -void copy_to_device(T* dst, T const* src, size_t count = 1) { - copy(dst, src, count, cudaMemcpyHostToDevice); -} - -template <typename T> -void copy_to_host(T* dst, T const* src, size_t count = 1) { - copy(dst, src, count, cudaMemcpyDeviceToHost); -} - -template <typename T> -void copy_device_to_device(T* dst, T const* src, size_t count = 1) { - copy(dst, src, count, cudaMemcpyDeviceToDevice); -} - -/// Copies elements from device memory to host-side range -template <typename OutputIterator, typename T> -void insert_to_host(OutputIterator begin, OutputIterator end, T const* device_begin) { - size_t elements = end - begin; - copy_to_host(&*begin, device_begin, elements); -} - -/// Copies elements to device memory from host-side range -template <typename T, typename InputIterator> -void insert_to_device(T* device_begin, InputIterator begin, InputIterator end) { - size_t elements = end - begin; - copy_to_device(device_begin, &*begin, elements); -} - -/****************************************************************************** - * "Smart" device memory allocation - ******************************************************************************/ - -/// Device allocation abstraction that tracks size and capacity -template <typename T> -struct allocation { - /// Delete functor for CUDA device memory - struct deleter { - void operator()(T* ptr) { - cudaError_t cuda_error = CUDA_PERROR(cudaFree(ptr)); - if (cuda_error != cudaSuccess) { - // noexcept - // throw cuda_exception("cudaFree() failed", cuda_error); - return; - } - } - }; - - /// Number of elements of T allocated on the current CUDA device - size_t capacity; - - /// Smart pointer - platform::unique_ptr<T, deleter> smart_ptr; - - // - // - // - - /// Constructor: allocates no memory - allocation() : capacity(0) {} - - /// Constructor: allocates \p capacity elements on the current CUDA device - allocation(size_t _capacity) : smart_ptr(allocate<T>(_capacity)), capacity(_capacity) {} - - /// Destructor - ~allocation() { reset(); } - - /// Returns a pointer to the managed object - T* get() const { return smart_ptr.get(); } - - /// Releases the ownership of the managed object (without deleting) and resets capacity to zero - T* release() { - capacity = 0; - return smart_ptr.release(); - } - - /// Deletes the managed object and resets capacity to zero - void reset() { - capacity = 0; - smart_ptr.reset(); - } - - /// Deletes managed object, if owned, and replaces its reference with a given pointer and capacity - void reset(T* _ptr, size_t _capacity) { - smart_ptr.reset(_ptr); - capacity = _capacity; - } - - /// Returns a pointer to the object owned by *this - T* operator->() const { return smart_ptr.get(); } - - /// Returns the deleter object which would be used for destruction of the managed object. - deleter& get_deleter() { return smart_ptr.get_deleter(); } - - /// Returns the deleter object which would be used for destruction of the managed object (const) - const deleter& get_deleter() const { return smart_ptr.get_deleter(); } -}; - -} // namespace device_memory -} // namespace cutlass diff --git a/cutlass-example/exceptions.h b/cutlass-example/exceptions.h deleted file mode 100644 index 72d99fe..0000000 --- a/cutlass-example/exceptions.h +++ /dev/null @@ -1,62 +0,0 @@ -/****************************************************************************** - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are not permitted. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ******************************************************************************/ - -#pragma once - -/** - * \file - * \brief C++ exception semantics for CUDA error codes - */ - -#include <cuda_runtime.h> -#include <iosfwd> -#include <stdexcept> - -#include <cutlass/util/platform.h> - -namespace cutlass { - -/// C++ exception wrapper for CUDA \p cudaError_t -class cuda_exception : public std::exception { - public: - /// Constructor - cuda_exception(const char* msg = "", cudaError_t err = cudaErrorUnknown) : msg(msg), err(err) {} - - /// Returns the underlying CUDA \p cudaError_t - cudaError_t cudaError() const { return err; } - - protected: - /// Explanatory string - const char* msg; - - /// Underlying CUDA \p cudaError_t - cudaError_t err; -}; - -/// Writes a cudaError_t to an output stream -inline std::ostream& operator<<(std::ostream& out, cudaError_t result) { - return out << cudaGetErrorString(result); -} - -/// Writes a cuda_exception instance to an output stream -inline std::ostream& operator<<(std::ostream& out, cuda_exception const& e) { - return out << e.what() << ": " << e.cudaError(); -} - -} // namespace cutlass diff --git a/cutlass-example/executionFlow b/cutlass-example/executionFlow deleted file mode 100644 index 356afed..0000000 --- a/cutlass-example/executionFlow +++ /dev/null @@ -1,262 +0,0 @@ -mov.b64%rd33, _ZN7cutlass4gemm11gemm_kernelINS0_4GemmINS0_14WmmaGemmTraitsILNS_12MatrixLayout4KindE1ELS5_0ENS_5ShapeILi32ELi16ELi16ELi1EEEfNS0_13LinearScalingIfNS0_19FragmentMultiplyAddIfEEEEfS7_NS6_ILi16ELi16ELi16ELi1EEELi8ELi8EiNS0_20WmmaGemmTraitsHelperILS5_1ELS5_0ES7_ffSB_S7_SC_Li8ELi8EiEEEEEEEEvNT_6ParamsE_param_0; -mov.u64 %rd1, %rd33; -ld.param.u64 %rd34, [_ZN7cutlass4gemm11gemm_kernelINS0_4GemmINS0_14WmmaGemmTraitsILNS_12MatrixLayout4KindE1ELS5_0ENS_5ShapeILi32ELi16ELi16ELi1EEEfNS0_13LinearScalingIfNS0_19FragmentMultiplyAddIfEEEEfS7_NS6_ILi16ELi16ELi16ELi1EEELi8ELi8EiNS0_20WmmaGemmTraitsHelperILS5_1ELS5_0ES7_ffSB_S7_SC_Li8ELi8EiEEEEEEEEvNT_6ParamsE_param_0+48]; -cvta.to.global.u64 %rd2, %rd34; -mov.u32 %r301, %ctaid.x; -shl.b32 %r1, %r301, 4; -ld.param.u64 %rd36, [_ZN7cutlass4gemm11gemm_kernelINS0_4GemmINS0_14WmmaGemmTraitsILNS_12MatrixLayout4KindE1ELS5_0ENS_5ShapeILi32ELi16ELi16ELi1EEEfNS0_13LinearScalingIfNS0_19FragmentMultiplyAddIfEEEEfS7_NS6_ILi16ELi16ELi16ELi1EEELi8ELi8EiNS0_20WmmaGemmTraitsHelperILS5_1ELS5_0ES7_ffSB_S7_SC_Li8ELi8EiEEEEEEEEvNT_6ParamsE_param_0+136]; -cvta.to.global.u64 %rd4, %rd36; -mov.u32 %r302, %ctaid.y; -shl.b32 %r2, %r302, 4; -mov.u32 %r3, %tid.x; -shr.u32 %r4, %r3, 1; -and.b32 %r303, %r3, 1; -shl.b32 %r5, %r303, 3; -add.s32 %r6, %r5, %r1; -ld.param.u32 %r7, [_ZN7cutlass4gemm11gemm_kernelINS0_4GemmINS0_14WmmaGemmTraitsILNS_12MatrixLayout4KindE1ELS5_0ENS_5ShapeILi32ELi16ELi16ELi1EEEfNS0_13LinearScalingIfNS0_19FragmentMultiplyAddIfEEEEfS7_NS6_ILi16ELi16ELi16ELi1EEELi8ELi8EiNS0_20WmmaGemmTraitsHelperILS5_1ELS5_0ES7_ffSB_S7_SC_Li8ELi8EiEEEEEEEEvNT_6ParamsE_param_0+20]; -mad.lo.s32 %r304, %r7, %r4, %r6; -cvt.s64.s32%rd5, %r304; -mul.wide.s32 %rd37, %r304, 2; -add.s64 %rd6, %rd2, %rd37; -ld.param.u32 %r8, [_ZN7cutlass4gemm11gemm_kernelINS0_4GemmINS0_14WmmaGemmTraitsILNS_12MatrixLayout4KindE1ELS5_0ENS_5ShapeILi32ELi16ELi16ELi1EEEfNS0_13LinearScalingIfNS0_19FragmentMultiplyAddIfEEEEfS7_NS6_ILi16ELi16ELi16ELi1EEELi8ELi8EiNS0_20WmmaGemmTraitsHelperILS5_1ELS5_0ES7_ffSB_S7_SC_Li8ELi8EiEEEEEEEEvNT_6ParamsE_param_0]; -sub.s32 %r305, %r8, %r6; -ld.param.u32 %r9, [_ZN7cutlass4gemm11gemm_kernelINS0_4GemmINS0_14WmmaGemmTraitsILNS_12MatrixLayout4KindE1ELS5_0ENS_5ShapeILi32ELi16ELi16ELi1EEEfNS0_13LinearScalingIfNS0_19FragmentMultiplyAddIfEEEEfS7_NS6_ILi16ELi16ELi16ELi1EEELi8ELi8EiNS0_20WmmaGemmTraitsHelperILS5_1ELS5_0ES7_ffSB_S7_SC_Li8ELi8EiEEEEEEEEvNT_6ParamsE_param_0+8]; -setp.gt.s32%p2, %r9, 0; -setp.gt.s32%p3, %r305, 0; -and.pred %p4, %p3, %p2; -selp.u32%r306, 1, 0, %p4; -setp.gt.s32%p5, %r9, 16; -and.pred %p6, %p3, %p5; -selp.u16%rs1, 1, 0, %p6; -mul.wide.u16 %r10, %rs1, 2; -selp.u32%r307, -1, 0, %p6; -bfi.b32 %r481, %r307, %r306, 1, 1; -bfe.u32 %r308, %r3, 1, 4; -mad.lo.s32 %r12, %r308, 24, %r5; -setp.lt.s32%p7, %r12, 768; -@%p7 bra BB0_2; -ld.param.u32 %r310, [%rd1+4]; -ld.param.u32 %r13, [%rd1+108]; -add.s32 %r16, %r5, %r2; -mad.lo.s32 %r311, %r13, %r4, %r16; -cvt.s64.s32%rd7, %r311; -mul.wide.s32 %rd45, %r311, 2; -add.s64 %rd8, %rd4, %rd45; -sub.s32 %r312, %r310, %r16; -setp.gt.s32%p9, %r312, 0; -and.pred %p11, %p9, %p2; -selp.u32%r313, 1, 0, %p11; -and.pred %p13, %p9, %p5; -selp.u16%rs2, 1, 0, %p13; -mul.wide.u16 %r17, %rs2, 2; -selp.u32%r314, -1, 0, %p13; -bfi.b32 %r480, %r314, %r313, 1, 1; -@%p7 bra BB0_4; -setp.lt.s32%p14, %r9, 32; -@%p14 bra BB0_7; -setp.lt.s32%p18, %r4, %r9; -selp.b32%r321, %r481, %r10, %p18; -add.s32 %r322, %r4, 16; -setp.lt.s32%p19, %r322, %r9; -and.b32 %r323, %r321, 1; -selp.b32%r481, %r321, %r323, %p19; -selp.b32%r324, %r480, %r17, %p18; -and.b32 %r325, %r324, 1; -selp.b32%r480, %r324, %r325, %p19; -bra.uni BB0_8; -and.b32 %r330, %r481, 1; -setp.eq.b32%p20, %r330, 1; -mov.u32 %r571, 0; -mov.u32 %r559, %r571; -mov.u32 %r560, %r571; -mov.u32 %r561, %r571; -mov.u32 %r562, %r571; -@!%p20 bra BB0_10; -bra.uni BB0_9; -ld.global.v4.u32 {%r561, %r562, %r559, %r560}, [%rd6]; -ld.param.u32 %r33, [%rd1+32]; -cvt.s64.s32%rd53, %r33; -add.s64 %rd9, %rd5, %rd53; -shl.b64 %rd54, %rd9, 1; -add.s64 %rd10, %rd2, %rd54; -and.b32 %r339, %r481, 2; -setp.eq.s32%p21, %r339, 0; -mov.u32 %r563, %r571; -mov.u32 %r564, %r571; -mov.u32 %r565, %r571; -mov.u32 %r566, %r571; -@%p21 bra BB0_12; -and.b32 %r348, %r480, 1; -setp.eq.b32%p22, %r348, 1; -mov.u32 %r567, %r571; -mov.u32 %r568, %r571; -mov.u32 %r569, %r571; -mov.u32 %r570, %r571; -@!%p22 bra BB0_14; -bra.uni BB0_13; -ld.global.v4.u32 {%r569, %r570, %r567, %r568}, [%rd8]; -ld.param.u32 %r50, [%rd1+120]; -cvt.s64.s32%rd55, %r50; -add.s64 %rd56, %rd7, %rd55; -shl.b64 %rd57, %rd56, 1; -add.s64 %rd11, %rd4, %rd57; -and.b32 %r357, %r480, 2; -setp.eq.s32%p23, %r357, 0; -mov.u32 %r572, %r571; -mov.u32 %r573, %r571; -mov.u32 %r574, %r571; -@%p23 bra BB0_16; -shl.b32 %r362, %r12, 1; -mov.u32 %r363, _ZN7cutlass4gemm11gemm_kernelINS0_4GemmINS0_14WmmaGemmTraitsILNS_12MatrixLayout4KindE1ELS5_0ENS_5ShapeILi32ELi16ELi16ELi1EEEfNS0_13LinearScalingIfNS0_19FragmentMultiplyAddIfEEEEfS7_NS6_ILi16ELi16ELi16ELi1EEELi8ELi8EiNS0_20WmmaGemmTraitsHelperILS5_1ELS5_0ES7_ffSB_S7_SC_Li8ELi8EiEEEEEEEEvNT_6ParamsE$__cuda_local_var_29658_57_non_const_shared_storage; -add.s32 %r59, %r363, %r362; -st.shared.v4.u32 [%r59], {%r561, %r562, %r559, %r560}; -st.shared.v4.u32 [%r59+768], {%r565, %r566, %r563, %r564}; -st.shared.v4.u32 [%r59+1536], {%r569, %r570, %r567, %r568}; -st.shared.v4.u32 [%r59+2304], {%r573, %r574, %r571, %r572}; -bar.sync 0; -shr.u32 %r60, %r3, 5; -shl.b32 %r61, %r60, 4; -setp.lt.u32%p24, %r61, 768; -@%p24 bra BB0_18; -mul.wide.s32 %rd65, %r61, 2; -cvt.u64.u32 %temp, %r363; -cvta.shared.u64 %rd66, %temp; -add.s64 %rd67, %rd66, %rd65; -add.s64 %rd12, %rd67, 1536; -mov.u32 %r374, 24; -wmma.load.a.sync.col.m16n16k16.f16 {%r590, %r589, %r588, %r587, %r586, %r585, %r584, %r583}, [%rd66], %r374; -wmma.load.b.sync.row.m16n16k16.f16 {%r582, %r581, %r580, %r579, %r578, %r577, %r576, %r575}, [%rd12], %r374; -add.s32 %r599, %r9, -32; -mov.u32 %r609, 0; -setp.lt.s32%p25, %r599, 1; -@%p25 bra BB0_19; -mov.u32 %r610, %r609; -mov.u32 %r611, %r609; -mov.u32 %r612, %r609; -mov.u32 %r613, %r609; -mov.u32 %r614, %r609; -mov.u32 %r615, %r609; -mov.u32 %r616, %r609; -setp.lt.s32%p34, %r599, -31; -@%p34 bra BB0_35; -mov.u32 %r477, %tid.x; -shr.u32 %r476, %r477, 5; -shl.b32 %r475, %r476, 4; -add.s32 %r434, %r475, 384; -mul.wide.s32 %rd96, %r434, 2; -add.s64 %rd97, %rd66, %rd96; -add.s64 %rd26, %rd97, 1536; -add.s64 %rd99, %rd66, 768; -wmma.load.a.sync.col.m16n16k16.f16 {%r257, %r256, %r255, %r254, %r250, %r251, %r253, %r252}, [%rd99], %r374; -wmma.load.b.sync.row.m16n16k16.f16 {%r265, %r264, %r263, %r262, %r258, %r259, %r261, %r260}, [%rd26], %r374; -mov.b32 %f63, %r615; -mov.b32 %f64, %r616; -mov.b32 %f65, %r613; -mov.b32 %f66, %r614; -mov.b32 %f67, %r611; -mov.b32 %f68, %r612; -mov.b32 %f69, %r609; -mov.b32 %f70, %r610; -wmma.mma.sync.col.row.m16n16k16.f32.f32 {%f10, %f11, %f12, %f13, %f14, %f15, %f16, %f17}, {%r590, %r589, %r588, %r587, %r586, %r585, %r584, %r583}, {%r582, %r581, %r580, %r579, %r578, %r577, %r576, %r575}, {%f70, %f69, %f68, %f67, %f66, %f65, %f64, %f63}; -bar.sync 0; -bar.sync 0; -wmma.mma.sync.col.row.m16n16k16.f32.f32 {%f71, %f72, %f73, %f74, %f75, %f76, %f77, %f78}, {%r257, %r256, %r255, %r254, %r250, %r251, %r253, %r252}, {%r265, %r264, %r263, %r262, %r258, %r259, %r261, %r260}, {%f10, %f11, %f12, %f13, %f14, %f15, %f16, %f17}; -mov.b32 %r610, %f71; -mov.b32 %r609, %f72; -mov.b32 %r612, %f73; -mov.b32 %r611, %f74; -mov.b32 %r614, %f75; -mov.b32 %r613, %f76; -mov.b32 %r616, %f77; -mov.b32 %r615, %f78; -add.s32 %r599, %r599, -32; -setp.gt.s32%p35, %r599, -32; -@%p35 bra BB0_34; -mov.b64%rd145, _ZN7cutlass4gemm11gemm_kernelINS0_4GemmINS0_14WmmaGemmTraitsILNS_12MatrixLayout4KindE1ELS5_0ENS_5ShapeILi32ELi16ELi16ELi1EEEfNS0_13LinearScalingIfNS0_19FragmentMultiplyAddIfEEEEfS7_NS6_ILi16ELi16ELi16ELi1EEELi8ELi8EiNS0_20WmmaGemmTraitsHelperILS5_1ELS5_0ES7_ffSB_S7_SC_Li8ELi8EiEEEEEEEEvNT_6ParamsE_param_0; -mov.u64 %rd144, %rd145; -mov.u32 %r472, %tid.x; -ld.param.f32 %f145, [%rd144+428]; -ld.param.u32 %r471, [%rd144+324]; -shr.u32 %r470, %r472, 5; -ld.param.u32 %r469, [%rd144+332]; -mov.u32 %r468, %ctaid.x; -shl.b32 %r467, %r468, 4; -mov.u32 %r466, _ZN7cutlass4gemm11gemm_kernelINS0_4GemmINS0_14WmmaGemmTraitsILNS_12MatrixLayout4KindE1ELS5_0ENS_5ShapeILi32ELi16ELi16ELi1EEEfNS0_13LinearScalingIfNS0_19FragmentMultiplyAddIfEEEEfS7_NS6_ILi16ELi16ELi16ELi1EEELi8ELi8EiNS0_20WmmaGemmTraitsHelperILS5_1ELS5_0ES7_ffSB_S7_SC_Li8ELi8EiEEEEEEEEvNT_6ParamsE$__cuda_local_var_29658_57_non_const_shared_storage; -mov.u32 %r465, %ctaid.y; -shl.b32 %r464, %r465, 4; -ld.param.v2.u32 {%r438, %r439}, [%rd144+288]; -ld.param.u32 %r284, [%rd144+300]; -ld.param.u32 %r440, [%rd144+320]; -ld.param.u32 %r285, [%rd144+336]; -ld.param.f32 %f18, [%rd144+424]; -ld.param.u32 %r287, [%rd144+304]; -ld.param.u64 %rd100, [%rd144+312]; -cvta.to.global.u64 %rd101, %rd100; -and.b32 %r441, %r472, 3; -shl.b32 %r288, %r441, 2; -shr.u32 %r289, %r472, 2; -add.s32 %r290, %r289, %r464; -add.s32 %r291, %r288, %r467; -mad.lo.s32 %r442, %r290, %r440, %r291; -cvt.s64.s32%rd102, %r442; -mul.wide.s32 %rd103, %r442, 4; -add.s64 %rd27, %rd101, %rd103; -sub.s32 %r292, %r469, %r290; -shl.b32 %r293, %r470, 8; -shl.b32 %r443, %r289, 4; -add.s32 %r294, %r443, %r288; -shl.b32 %r444, %r294, 2; -add.s32 %r295, %r466, %r444; -cvt.s64.s32%rd104, %r471; -add.s64 %rd105, %rd102, %rd104; -shl.b64 %rd106, %rd105, 2; -add.s64 %rd28, %rd101, %rd106; -setp.eq.f32%p36, %f145, 0f00000000; -@%p36 bra BB0_48; -setp.lt.s32%p51, %r293, 256; -@%p51 bra BB0_50; -setp.lt.s32%p52, %r294, 256; -@%p52 bra BB0_52; -ld.param.u32 %r474, [_ZN7cutlass4gemm11gemm_kernelINS0_4GemmINS0_14WmmaGemmTraitsILNS_12MatrixLayout4KindE1ELS5_0ENS_5ShapeILi32ELi16ELi16ELi1EEEfNS0_13LinearScalingIfNS0_19FragmentMultiplyAddIfEEEEfS7_NS6_ILi16ELi16ELi16ELi1EEELi8ELi8EiNS0_20WmmaGemmTraitsHelperILS5_1ELS5_0ES7_ffSB_S7_SC_Li8ELi8EiEEEEEEEEvNT_6ParamsE_param_0]; -mul.wide.s32 %rd142, %r293, 4; -add.s64 %rd32, %rd66, %rd142; -setp.lt.s32%p1, %r291, %r474; -bar.sync 0; -mov.b32 %f121, %r610; -mov.b32 %f122, %r609; -mov.b32 %f123, %r612; -mov.b32 %f124, %r611; -mov.b32 %f125, %r614; -mov.b32 %f126, %r613; -mov.b32 %f127, %r616; -mov.b32 %f128, %r615; -mov.u32 %r458, 16; -wmma.store.d.sync.col.m16n16k16.f32 [%rd32], {%f121, %f122, %f123, %f124, %f125, %f126, %f127, %f128}, %r458; -bar.sync 0; -ld.shared.v4.u32 {%r459, %r460, %r461, %r462}, [%r295+512]; -setp.gt.s32%p53, %r292, 0; -and.pred %p54, %p1, %p53; -@!%p54 bra BB0_54; -bra.uni BB0_53; -ld.shared.v4.f32 {%f129, %f130, %f131, %f132}, [%r295]; -mul.f32 %f137, %f18, %f132; -mul.f32 %f138, %f18, %f131; -mul.f32 %f139, %f18, %f130; -mul.f32 %f140, %f18, %f129; -st.global.v4.f32 [%rd27], {%f140, %f139, %f138, %f137}; -mov.b32 %f141, %r459; -mul.f32 %f43, %f18, %f141; -mov.b32 %f142, %r460; -mul.f32 %f44, %f18, %f142; -mov.b32 %f143, %r461; -mul.f32 %f45, %f18, %f143; -mov.b32 %f144, %r462; -mul.f32 %f46, %f18, %f144; -sub.s32 %r463, %r292, %r285; -setp.gt.s32%p56, %r463, 0; -and.pred %p57, %p1, %p56; -@!%p57 bra BB0_56; -bra.uni BB0_55; -st.global.v4.f32 [%rd28], {%f43, %f44, %f45, %f46}; -bra.uni BB0_56; -ret; diff --git a/cutlass-example/gemm.h b/cutlass-example/gemm.h deleted file mode 100644 index 18dfdf6..0000000 --- a/cutlass-example/gemm.h +++ /dev/null @@ -1,152 +0,0 @@ -/*************************************************************************************************** -* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without modification, are permitted -* provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright notice, this list of -* conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright notice, this list of -* conditions and the following disclaimer in the documentation and/or other materials -* provided with the distribution. -* * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used -* to endorse or promote products derived from this software without specific prior written -* permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -* STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -**************************************************************************************************/ - -#include <cutlass/cutlass.h> -#include <gemm_testbed.h> - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmTraits_> -static void run_gemm( - int m, - int n, - int k, - int lda, - int ldb, - int ldc, - typename test::GemmTestbedTraits<typename GemmTraits_::Epilogue::Scalar>::host_type alpha = - typename test::GemmTestbedTraits<typename GemmTraits_::Epilogue::Scalar>::host_type(1), - typename test::GemmTestbedTraits<typename GemmTraits_::Epilogue::Scalar>::host_type beta = - typename test::GemmTestbedTraits<typename GemmTraits_::Epilogue::Scalar>::host_type(0)) { - typedef cutlass::gemm::Gemm<GemmTraits_> Gemm; - typename Gemm::Params params; - - printf("run_gemm-2:m=%d\n",m); - printf("run_gemm-2:n=%d\n",n); - printf("run_gemm-2:k=%d\n",k); - printf("run_gemm-2:lda=%d\n",lda); - printf("run_gemm-2:ldb=%d\n",ldb); - printf("run_gemm-2:ldc=%d\n",ldc); - printf("run_gemm-2:alpha=%.2f\n",alpha); - printf("run_gemm-2:beta=%.2f\n",beta); - - test::GemmTestbed< - typename test::GemmTestbedTraits< - typename GemmTraits_::GemmConfig::ScalarA>::host_type, // AType - typename test::GemmTestbedTraits< - typename GemmTraits_::GemmConfig::ScalarB>::host_type, // BType - typename test::GemmTestbedTraits< - typename GemmTraits_::Epilogue::ScalarC>::host_type, // CType - typename test::GemmTestbedTraits< - typename GemmTraits_::Epilogue::Accumulators::Element>::host_type, // Accumulator - typename test::GemmTestbedTraits<typename GemmTraits_::Epilogue::Scalar>::host_type // Scalar - > - testbed(m, - n, - k, - lda, - ldb, - ldc, - cutlass::convert(GemmTraits_::kLayoutA), - cutlass::convert(GemmTraits_::kLayoutB), - alpha, - beta); - - testbed.initialize(); - - // if (testbed.has_cublas_support()) { - // EXPECT_TRUE(testbed.verify_host_with_cublas()); - // } - - params.initialize(testbed.M(), - testbed.N(), - testbed.K(), - testbed.alpha, - testbed.ptr_A(), - testbed.lda(), - testbed.ptr_B(), - testbed.ldb(), - testbed.beta, - testbed.ptr_C_initial(), - testbed.ldc(), - testbed.ptr_computed(), - testbed.ldc()); - - printf("SIZE_OF_PARAM=%lu\n",sizeof(params)); - void *ptr =¶ms; - for(int kk=0;kk<108;kk++){ - printf("KERNELPARAM:%d:%08x\n",kk,*((((int *) ptr)+kk))); - } - printf("m=%lu\n",sizeof(params.m)); - printf("n=%lu\n",sizeof(params.n)); - printf("k=%lu\n",sizeof(params.k)); -// printf("alpha=%d\n",sizeof(params.alpha)); -// printf("beta=%d\n",sizeof(params.beta)); -// printf("d_a=%d\n",sizeof(params.d_a)); -// printf("lda=%d\n",sizeof(params.lda)); -// printf("d_b=%d\n",sizeof(params.d_b)); -// printf("ldb=%d\n",sizeof(params.ldb)); -// printf("d_c=%d\n",sizeof(params.d_c)); -// printf("ldc=%d\n",sizeof(params.ldc)); -// printf("d_d=%d\n",sizeof(params.d_d)); -// printf("ldd=%d\n",sizeof(params.ldd)); - Gemm::launch(params); - - cudaError_t result = cudaDeviceSynchronize(); - if(result==cudaSuccess){ - printf("Successfully Launched\n"); - } - int save=1; - int myval=testbed.verify_with_host(save,save); - if(myval==1){ - printf("Result Verified\n"); - } - -} - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename GemmTraits_> -static void run_gemm( - int m, - int n, - int k, - typename test::GemmTestbedTraits<typename GemmTraits_::Epilogue::Scalar>::host_type alpha = - typename test::GemmTestbedTraits<typename GemmTraits_::Epilogue::Scalar>::host_type(1), - typename test::GemmTestbedTraits<typename GemmTraits_::Epilogue::Scalar>::host_type beta = - typename test::GemmTestbedTraits<typename GemmTraits_::Epilogue::Scalar>::host_type(0)) { - int lda = GemmTraits_::kLayoutA == cutlass::MatrixLayout::kColumnMajor ? m : k; - int ldb = GemmTraits_::kLayoutB == cutlass::MatrixLayout::kColumnMajor ? k : n; - printf("run_gemm-1:m=%d\n",m); - printf("run_gemm-1:n=%d\n",n); - printf("run_gemm-1:k=%d\n",k); - printf("run_gemm-1:alpha=%.2f\n",alpha); - printf("run_gemm-1:beta=%.2f\n",beta); - printf("run_gemm-1:lda=%d\n",lda); - printf("run_gemm-1:ldb=%d\n",ldb); - run_gemm<GemmTraits_>(m, n, k, lda, ldb, m, alpha, beta); -} - -//////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/cutlass-example/gemm_testbed.h b/cutlass-example/gemm_testbed.h deleted file mode 100644 index 97409b1..0000000 --- a/cutlass-example/gemm_testbed.h +++ /dev/null @@ -1,462 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Test environment for GEMM -*/ - -#pragma once - -#include <fstream> -#include <iomanip> -#include <sstream> -#include <string> - -#include <cutlass/matrix_traits.h> -#include <cutlass/util/platform.h> - -#include <host_tensor.h> -#include <tensor_view_io.h> -#include <type_traits.h> - -namespace cutlass { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <cutlass::GemmOperand::Kind kOperand_, - cutlass::MatrixLayout::Kind kLayout_, - typename Scalar_, - typename WmmaShape_> -struct WmmaMatrix; -} - -namespace test { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename T> -struct GemmTestbedTraits : public cutlass::TypeTraits<T> {}; - -template <cutlass::GemmOperand::Kind kOperand_, - cutlass::MatrixLayout::Kind kLayout_, - typename Scalar_, - typename WmmaShape_> -struct GemmTestbedTraits<cutlass::WmmaMatrix<kOperand_, kLayout_, Scalar_, WmmaShape_> > { - static cudaDataType_t const cublas_type = cutlass::TypeTraits<Scalar_>::cublas_type; - typedef Scalar_ host_type; - typedef Scalar_ device_type; - static inline double remove_negative_zero(double x) { return x == -0.0 ? 0.0 : x; } - static inline double to_print(double x) { return x; } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// -template <typename AType, typename BType, typename CType, typename Accumulator, typename Scalar> -struct GemmTestbed { - // - // Type definitions - // - - /// Host tensor for operand A - typedef cutlass::HostTensor<AType> HostTensorA; - - /// Host tensor for operand B - typedef cutlass::HostTensor<BType> HostTensorB; - - /// Host tensor for operand C - typedef cutlass::HostTensor<CType> HostTensorC; - - /// Functor to print errors - struct PrintErrors { - /// Equivalently sized integer type - typedef typename GemmTestbedTraits<CType>::integer_type integer_t; - - /// Output stream to write to - std::ostream& out; - - /// Reference tensor view - cutlass::HostTensorView<CType> const& reference; - - /// Computed tensor view - cutlass::HostTensorView<CType> const& experimental; - - /// Errors greater than or this amount result in printing - integer_t ulps_threshold; - - /// - PrintErrors(std::ostream& _out, - cutlass::HostTensorView<CType> const& _reference, - cutlass::HostTensorView<CType> const& _experimental, - integer_t _ulps_threshold = 1) - : out(_out), - reference(_reference), - experimental(_experimental), - ulps_threshold(_ulps_threshold) {} - - /// Compares one element - void operator()(CType const& element, typename HostTensorC::Coord_t coord) { - CType exp = experimental.at(coord); - CType ref = reference.at(coord); - - int64_t int_exp = 0; - int64_t int_ref = 0; - - *reinterpret_cast<CType*>(&int_exp) = exp; - *reinterpret_cast<CType*>(&int_ref) = ref; - - integer_t ulps = integer_t(int_exp - int_ref); - - if (std::abs(ulps) >= ulps_threshold) { - // width in hexadecimal digits of value - int const width = sizeof(integer_t) * 2; - - double relative = double(exp) - double(ref); - if (ref != CType(0)) { - relative /= double(ref); - } - - out << "[" << coord << "] expected: " << GemmTestbedTraits<CType>::to_print(ref) << " (0x" - << std::hex << std::setw(width) << std::setfill('0') << integer_t(int_ref) << std::dec - << ")" - << ", got: " << GemmTestbedTraits<CType>::to_print(exp) << " (0x" << std::hex - << std::setw(width) << std::setfill('0') << integer_t(int_exp) << std::dec << ")" - << " relative error: " << relative << ", ulps: " << ulps << "\n"; - } - } - }; - - /// Generates random elements - template <typename T> - struct RandomGenerator { - RandomGenerator(int seed = -1, bool only_ones_ = false) : only_ones(only_ones_) { srand(seed); } - - T operator()() { - if (only_ones) { - return T(1); - } else { - int val = (rand() % 16) - 8; - return T(val); - } - } - - bool only_ones; - }; - - // - // Data members - // - - /// Status - //cublasStatus_t status; - - /// cuBLAS handle - //cublasHandle_t handle; - - /// cuBLAS GEMM algorithm selector - //cublasGemmAlgo_t algorithm; - - /// A matrix operand - HostTensorA A; - - /// Layout of A matrix - //cublasOperation_t layout_A; - - /// B matrix operand - HostTensorB B; - - /// Layout of B matrix - //cublasOperation_t layout_B; - - /// C matrix operand - HostTensorC C_initial; - - /// Reference result computed on the host - cutlass::HostTensor<CType, false> ref_host; - - - /// Computed result - HostTensorC computed; - - /// Linear scalaring factor - Scalar alpha; - - /// Linear scaling factor - Scalar beta; - - // - // Static helpers - // - //template <typename T, bool DeviceBacked> - //static void resize(cutlass::HostTensor<T, DeviceBacked>& tensor, - // int rows, - // int columns, - // cublasOperation_t layout, - // int ldm = 0) { - // if (!ldm) { - // ldm = (layout == CUBLAS_OP_N ? rows : columns); - // } - - // typedef cutlass::Coord<cutlass::HostTensor<T>::Rank> Coord_t; - - // size_t matrix_stride = layout == CUBLAS_OP_N ? columns * ldm : rows * ldm; - // // TODO: Remove that (int) cast. - // Coord_t stride = cutlass::make_Coord( - // (int)matrix_stride, layout == CUBLAS_OP_N ? 1 : ldm, layout == CUBLAS_OP_N ? ldm : 1, 1); - // Coord_t size = cutlass::make_Coord(1, rows, columns, 1); - // tensor.reset(stride, size); - //} - - /// Helper to resize a matrix with a given size and layout - template <typename T, bool DeviceBacked> - static void resize(cutlass::HostTensor<T, DeviceBacked>& tensor, - int rows, - int columns, - int layout, - int ldm = 0) { - if (!ldm) { - ldm = (layout ? rows : columns); - } - - typedef cutlass::Coord<cutlass::HostTensor<T>::Rank> Coord_t; - size_t matrix_stride = layout ? columns * ldm : rows * ldm; - // TODO: Remove that (int) cast. - Coord_t stride = cutlass::make_Coord( - (int)matrix_stride, layout ? 1 : ldm, layout? ldm : 1, 1); - Coord_t size = cutlass::make_Coord(1, rows, columns, 1); - tensor.reset(stride, size); - } - - // - // Methods - // - - /// Constructs a workspace for verifying GEMM. - GemmTestbed(int M_, - int N_, - int K_, - int lda, - int ldb, - int ldc, - int layout_a, - int layout_b, - Scalar alpha_ = Scalar(1), - Scalar beta_ = Scalar(0)) - //cublasGemmAlgo_t algorithm_ = CUBLAS_GEMM_DEFAULT, - //cublasOperation_t layout_c = CUBLAS_OP_N) - : alpha(alpha_), beta(beta_) { - //status = cublasCreate(&handle); - //if (status != CUBLAS_STATUS_SUCCESS) { - // throw cutlass::cuda_exception("Failed to create CUBLAS handle"); - //} - printf("GemmTestbed:alpha=%f\n",alpha_); - printf("GemmTestbed:beta=%f\n",beta_); - printf("GemmTestbed:lda=%d\n",lda); - printf("GemmTestbed:ldb=%d\n",ldb); - printf("GemmTestbed:ldc=%d\n",ldc); - - resize(A, M_, K_,layout_a, lda); - resize(B, K_, N_,layout_b, ldb); - resize(C_initial, M_, N_,1, ldc); - resize(ref_host, M_, N_,1, ldc); - resize(computed, M_, N_,1, ldc); - } - - /// Returns a pointer to the A operand - typename HostTensorA::DeviceType* ptr_A() const { - return A.device_data(); - } - - /// Stride of A matrix - int lda() const { - printf("lda()=%d\n",std::max(A.stride(HostTensorA::Dim_H), A.stride(HostTensorA::Dim_W))); - return std::max(A.stride(HostTensorA::Dim_H), A.stride(HostTensorA::Dim_W)); - } - - /// Returns a pointer to the B operand - typename HostTensorB::DeviceType* ptr_B() const { - return B.device_data(); - } - - /// Stride of B matrix - int ldb() const { - printf("ldb()=%d\n",std::max(B.stride(HostTensorB::Dim_H), B.stride(HostTensorB::Dim_W))); - return std::max(B.stride(HostTensorB::Dim_H), B.stride(HostTensorB::Dim_W)); - } - - /// Returns a pointer to the initial state of the result tensor in device memory - typename HostTensorC::DeviceType* ptr_C_initial() const { - return C_initial.device_data(); - } - - /// Returns a pointer to the result tensor in device memory - typename HostTensorC::DeviceType* ptr_computed() const { - return computed.device_data(); - } - - /// Stride of C matrix - int ldc() const { - printf("ldc()=%d\n",std::max(C_initial.stride(HostTensorC::Dim_H), C_initial.stride(HostTensorC::Dim_W))); - return std::max(C_initial.stride(HostTensorC::Dim_H), C_initial.stride(HostTensorC::Dim_W)); - } - - /// Returns the number of flops implied by the computation (1 multiply-accumulate = 2 flops) - uint64_t flops() const { return uint64_t(M()) * uint64_t(N()) * uint64_t(K()) * 2ULL; } - - /// Computes the speed of the computation in GFLOPs/s - double GFLOPs_per_sec(double runtime_ms) const { return double(flops()) / runtime_ms / 1.0e6; } - - /// Number of rows of problem - int M() const { - printf("M()=%d\n", C_initial.size(HostTensorC::Dim_H)); - return C_initial.size(HostTensorC::Dim_H); - } - - /// Number of columns of problem - int N() const { - printf("N()=%d\n", C_initial.size(HostTensorC::Dim_W)); - return C_initial.size(HostTensorC::Dim_W); - } - - /// Number of columns of problem - int K() const { - printf("K()=%d\n",A.size(HostTensorA::Dim_W)); - return A.size(HostTensorA::Dim_W); - } - - /// Initializes data, randomly - void initialize(int seed = -1) { - A.fill_random(RandomGenerator<AType>(seed)); - B.fill_random(RandomGenerator<BType>(seed + 11)); - C_initial.fill_random(RandomGenerator<CType>(seed + 13,1)); - } - - /// Computes the matrix product on the host - void compute_host() { - ref_host.fill(C_initial); - - std::string results_name = "host_results_before.txt"; - std::ofstream results(results_name.c_str()); - write(results); - - ref_host.template gemm<AType, BType, Accumulator, Scalar>(A, B, alpha, beta); - results_name = "host_results_after.txt"; - std::ofstream results2(results_name.c_str()); - write(results2); - } - - /// Names a probelm based on data type and problem size - std::string workspace_name() const { - std::stringstream ss; - ss << "gemm_" << "t" - << "t" << "_" << typeid(AType).name() << "_" - << typeid(BType).name() << "_" << typeid(CType).name() << "_" << typeid(Accumulator).name() - << "_" << typeid(Scalar).name() << "_" << M() << "x" << N() << "x" << K(); - - return ss.str(); - } - - /// Writes the workspace to an ostream - std::ostream& write(std::ostream& out) const { - out << "A = " << A << "\nB = " << B << "\nC_initial = " << C_initial - << "\ncomputed = " << computed - << "\nref_host= " << ref_host<< std::endl; - - return out; - } - - /// Outputs each mismatching element - std::ostream& write_errors(std::ostream& out, - cutlass::HostTensorView<CType> const& experimental, - cutlass::HostTensorView<CType> const& ref) const { - PrintErrors printer(out, ref, experimental); - - computed.visit(printer); - - return out; - } - - /// Sync's all input tensors to device - void sync_device() { - A.sync_device(); - B.sync_device(); - C_initial.sync_device(); - - ref_host.fill(C_initial); - computed.fill(C_initial); - - computed.sync_device(); - } - - /// Sync's all output tensors to host - void sync_host() { - computed.sync_host(); - } - - /// Saves the workspace to files - void save_workspace(cutlass::HostTensorView<CType> const& experimental, - cutlass::HostTensorView<CType> const& ref) { - std::string name = workspace_name(); - - std::string results_name = name + "_results.txt"; - std::string errors_name = name + "_errors.txt"; - - std::ofstream results(results_name.c_str()); - std::ofstream errors(errors_name.c_str()); - - write(results); - write_errors(errors, experimental, ref); - } - - /// Verifies the contents of C equal the host-side reference - bool verify_with_host(bool save_on_error = true, bool always_print = false) { - compute_host(); - computed.sync_host(); - - bool passed = computed.bit_equals(ref_host); - - if ((!passed && save_on_error) || always_print) { - save_workspace(computed, ref_host); - } - return passed; - } -}; - -} // namespace test - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -namespace cutlass { -inline int convert(cutlass::MatrixLayout::Kind layout) { - switch (layout) { - case cutlass::MatrixLayout::kRowMajor: - return 0;//CUBLAS_OP_T; - case cutlass::MatrixLayout::kColumnMajor: - return 1;//CUBLAS_OP_N; - default: - break; - } - return 1;//CUBLAS_OP_N; -} - -//////////////////////////////////////////////////////////////////////////////////////////////////// -} diff --git a/cutlass-example/gpgpusim.config b/cutlass-example/gpgpusim.config deleted file mode 100644 index 3daa539..0000000 --- a/cutlass-example/gpgpusim.config +++ /dev/null @@ -1,151 +0,0 @@ -# This config models the Pascal GP102 (GeForceGTX 1080Ti) - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 70 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 80 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 11 --gpgpu_n_sub_partition_per_mchannel 2 - -# Pascal clock domains -#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> -# Pascal NVIDIA TITAN X clock domains are adopted from -# https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 1 SFU unit -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,1,1,1,1,4,1,1,1,1,6 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 1 -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# SFU is 32-width in pascal, then dp units initiation is 1 cycle --ptx_opcode_latency_int 4,13,4,5,145,16,4 --ptx_opcode_initiation_int 1,2,2,2,8,16,4 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 1,2,1,1,130 - -# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP102 has 96KB Shared memory -# Pascal GP102 has 64KB L1 cache -# The default is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 --gpgpu_shmem_size 98304 --gmem_skip_L1D 1 - -# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 --gpgpu_cache:dl2_texture_only 0 - -# 4 KB Inst. --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 -# 12 KB Const --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 - -# enable operand collector -## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units --gpgpu_operand_collector_num_units_sp 20 --gpgpu_operand_collector_num_units_sfu 4 -#-gpgpu_operand_collector_num_units_tensor_core 24 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 -#-gpgpu_operand_collector_num_in_ports_tensor_core 1 -#-gpgpu_operand_collector_num_out_ports_tensor_core 1 --gpgpu_operand_collector_num_in_ports_mem 10 --gpgpu_operand_collector_num_out_ports_mem 10 -# gpgpu_num_reg_banks should be increased to 32, but it gives an error! --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - -## In Pascal, a warp scheduler can issue 2 insts per cycle --gpgpu_max_insn_issue_per_warp 2 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 116 - -# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) -# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition -# the atom size of GDDR5X (the smallest read request) is 32 bytes --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5X is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS - -# Use the same GDDR5 timing from hynix H5GQ1H24AFR -# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" - -# Pascal has four schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs --power_simulation_enabled 1 --gpuwattch_xml_file gpuwattch_gtx1080Ti.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/cutlass-example/gpuwattch_gtx1080Ti.xml b/cutlass-example/gpuwattch_gtx1080Ti.xml deleted file mode 100755 index 02619ff..0000000 --- a/cutlass-example/gpuwattch_gtx1080Ti.xml +++ /dev/null @@ -1,538 +0,0 @@ -<?xml version="1.0" ?> -<component id="root" name="root"> - <component id="system" name="system"> - <!--McPAT will skip the components if number is set to 0 --> - <param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported --> - <param name="number_of_cores" value="28"/> - <param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined--> - <param name="number_of_L1Directories" value="0"/> - <param name="number_of_L2Directories" value="0"/> - <param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports --> - <param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters --> - <param name="number_of_NoCs" value="1"/> - <param name="homogeneous_cores" value="1"/><!--1 means homo --> - <param name="homogeneous_L2s" value="1"/> - <param name="homogeneous_L1Directorys" value="1"/> - <param name="homogeneous_L2Directorys" value="1"/> - <param name="homogeneous_L3s" value="1"/> - <param name="homogeneous_ccs" value="1"/><!--cache coherece hardware --> - <param name="homogeneous_NoCs" value="1"/> - <param name="core_tech_node" value="23"/><!-- nm --> - <param name="target_core_clockrate" value="1481"/><!--MHz --> - <param name="temperature" value="380"/> <!-- Kelvin --> - <param name="number_cache_levels" value="2"/> - <param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology --> - <param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power) --> - <param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible --> - <param name="machine_bits" value="32"/> - <param name="virtual_address_width" value="32"/> - <param name="physical_address_width" value="32"/> - <param name="virtual_memory_page_size" value="4096"/> - <param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 --> - <!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/--> - <param name="TOT_INST" value="10" /> - <param name="FP_INT" value="10" /> - <param name="IC_H" value="0.001" /> - <param name="IC_M" value="10" /> - <param name="DC_RH" value="1" /> - <param name="DC_RM" value="1" /> - <param name="DC_WH" value="1" /> - <param name="DC_WM" value="1" /> - <param name="TC_H" value="0.001" /> - <param name="TC_M" value="10" /> - <param name="CC_H" value="4.5071" /> - <param name="CC_M" value="10" /> - <param name="SHRD_ACC" value="10" /> - <param name="REG_RD" value="1.6294" /> - <param name="REG_WR" value="0.5031" /> - <param name="NON_REG_OPs" value="0.01" /> - <param name="SP_ACC" value="10" /> - <param name="SFU_ACC" value="0.0082" /> - <param name="FPU_ACC" value="0.4126" /> - <param name="MEM_RD" value="0.1234" /> - <param name="MEM_WR" value="0.001" /> - <param name="MEM_PRE" value="0.001" /> - <param name="L2_RH" value="100" /> - <param name="L2_RM" value="100" /> - <param name="L2_WH" value="100" /> - <param name="L2_WM" value="42.6966" /> - <param name="NOC_A" value="100" /> - <param name="PIPE_A" value="44.8085" /> - <param name="IDLE_CORE_N" value="2.0382"/> - <param name="CONST_DYNAMICN" value="5.0005" /> - <stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period --> - <stat name="total_cycles" value="total_cycles_match_mcpat"/> - <stat name="idle_cycles" value="idle_cycles_match_mcpat"/> - <stat name="busy_cycles" value="busy_cycles_match_mcpat"/> - <!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of - virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank --> - <!-- *********************** cores ******************* --> - <component id="system.core0" name="core0"> - <!-- Core property --> - <param name="clock_rate" value="1481"/> - <param name="instruction_length" value="32"/> - <param name="opcode_width" value="9"/> - <!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller - default value is machine_bits, if not set --> - <param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO--> - <!-- inorder/OoO --> - <param name="number_hardware_threads" value="32"/> - <!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor, - it only may be more than one in SMT processors. BTB ports always equals to fetch ports since - branch information in consective branch instructions in the same fetch group can be read out from BTB once.--> - <param name="fetch_width" value="1"/> - <!-- fetch_width determins the size of cachelines of L1 cache block --> - <param name="number_instruction_fetch_ports" value="1"/> - <param name="decode_width" value="1"/> - <!-- decode_width determins the number of ports of the - renaming table (both RAM and CAM) scheme --> - <param name="issue_width" value="2"/> - <!-- issue_width determins the number of ports of Issue window and other logic - as in the complexity effective proccessors paper; issue_width==dispatch_width --> - <param name="commit_width" value="2"/> - <!-- commit_width determins the number of ports of register files --> - <param name="fp_issue_width" value="1"/> - <param name="prediction_width" value="0"/> - <!-- number of branch instructions can be predicted simultannouesl--> - <!-- Current version of McPAT does not distinguish int and floating point pipelines - Theses parameters are reserved for future use.--> - <param name="pipelines_per_core" value="1,1"/> - <!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared--> - <param name="pipeline_depth" value="8,8"/> - <!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops --> - <!-- issue and exe unit--> - <param name="ALU_per_core" value="32"/> - <!-- contains an adder, a shifter, and a logical unit --> - <param name="MUL_per_core" value="4"/> - <!-- For MUL and Div --> - <param name="FPU_per_core" value="32"/> - <!-- buffer between IF and ID stage --> - <param name="instruction_buffer_size" value="1"/> - <!-- buffer between ID and sche/exe stage --> - <param name="decoded_stream_buffer_size" value="1"/> - <param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED--> - <!-- McPAT support 2 types of OoO cores, RS based and physical reg based--> - <param name="instruction_window_size" value="1"/> - <param name="fp_instruction_window_size" value="1"/> - <!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 --> - <param name="ROB_size" value="0"/> - <!-- each in-flight instruction has an entry in ROB --> - <!-- registers --> - <!-- SM parameters Added by Syed Gilani --> - <param name="rf_banks" value="32"/> - <param name="simd_width" value="32"/> - <param name="collector_units" value="32"/> - <param name="core_clock_ratio" value="2"/> - <param name="warp_size" value="32"/> - - <param name="archi_Regs_IRF_size" value="65536"/> - <param name="archi_Regs_FRF_size" value="32"/> - <!-- if OoO processor, phy_reg number is needed for renaming logic, - renaming logic is for both integer and floating point insts. --> - <param name="phy_Regs_IRF_size" value="32"/> - <param name="phy_Regs_FRF_size" value="32"/> - <!-- rename logic --> - <param name="rename_scheme" value="0"/> - <!-- can be RAM based(0) or CAM based(1) rename scheme - RAM-based scheme will have free list, status table; - CAM-based scheme have the valid bit in the data field of the CAM - both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions; - Detailed RAT Implementation see TR --> - <param name="register_windows_size" value="0"/> - <!-- how many windows in the windowed register file, sun processors; - no register windowing is used when this number is 0 --> - <!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha), - They will always try to exeute out-of-order though. --> - <param name="LSU_order" value="inorder"/> - <param name="store_buffer_size" value="32"/> - <!-- By default, in-order cores do not have load buffers --> - <param name="load_buffer_size" value="32"/> - <!-- number of ports refer to sustainable concurrent memory accesses --> - <param name="memory_ports" value="2"/> - <!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer - as well as the ports of Dcache which is connected to LSU --> - <!-- dual-pumped Dcache can be used to save the extra read/write ports --> - <param name="RAS_size" value="1"/> - <!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check --> - <!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops --> - <stat name="total_instructions" value="total_instructions_match_mcpat"/> - <stat name="int_instructions" value="int_instruction_match_mcpat"/> - <stat name="fp_instructions" value="flt_instruction_match_mcpat"/> - <stat name="branch_instructions" value="branch_instruction_match_mcpat"/> - <stat name="branch_mispredictions" value="0"/> - <stat name="load_instructions" value="load_instruction_match_mcpat"/> - <stat name="store_instructions" value="store_instruction_match_mcpat"/> - <stat name="committed_instructions" value="total_instructions_match_mcpat"/> - <stat name="committed_int_instructions" value="int_instruction_match_mcpat"/> - <stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/> - <stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous --> - <!-- the following cycle stats are used for heterogeneouse cores only, - please ignore them if homogeneouse cores --> - <stat name="total_cycles" value="total_cycles_match_mcpat"/> - <stat name="idle_cycles" value="idle_cycles_match_mcpat"/> - <stat name="busy_cycles" value="busy_cycles_match_mcpat"/> - <!-- instruction buffer stats --> - <!-- ROB stats, both RS and Phy based OoOs have ROB - performance simulator should capture the difference on accesses, - otherwise, McPAT has to guess based on number of commited instructions. --> - <stat name="ROB_reads" value="263886"/> - <stat name="ROB_writes" value="263886"/> - <!-- RAT accesses --> - <stat name="rename_accesses" value="263886"/> - <stat name="fp_rename_accesses" value="263886"/> - <!-- decode and rename stage use this, should be total ic - nop --> - <!-- Inst window stats --> - <stat name="inst_window_reads" value="263886"/> - <stat name="inst_window_writes" value="263886"/> - <stat name="inst_window_wakeup_accesses" value="263886"/> - <stat name="fp_inst_window_reads" value="263886"/> - <stat name="fp_inst_window_writes" value="263886"/> - <stat name="fp_inst_window_wakeup_accesses" value="263886"/> - <!-- RF accesses --> - <stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/> - <stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/> - <stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/> - <stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/> - - <!-- The following stat is for operand collector power - Added by Syed --> - <stat name="non_rf_operands" value="0"/> - - <!-- accesses to the working reg --> - <stat name="function_calls" value="0"/> - <stat name="context_switches" value="0"/> <!--not used in the McPAT --> - <!-- Number of Windowes switches (number of function calls and returns)--> - <!-- Alu stats by default, the processor has one FPU that includes the divider and - multiplier. The fpu accesses should include accesses to multiplier and divider --> - <stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/> - <stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/> - <stat name="mul_accesses" value="mul_accesses_match_mcpat"/> - <stat name="cdb_alu_accesses" value="0"/> - <stat name="cdb_mul_accesses" value="0"/> - <stat name="cdb_fpu_accesses" value="0"/> - <!-- multiple cycle accesses should be counted multiple times, - otherwise, McPAT can use internal counter for different floating point instructions - to get final accesses. But that needs detailed info for floating point inst mix --> - <!-- currently the performance simulator should - make sure all the numbers are final numbers, - including the explicit read/write accesses, - and the implicite accesses such as replacements and etc. - Future versions of McPAT may be able to reason the implicite access - based on param and stats of last level cache - The same rule applies to all cache access stats too! --> - <!-- following is AF for max power computation. - Do not change them, unless you understand them--> - <stat name="IFU_duty_cycle" value="0.25"/> - <stat name="LSU_duty_cycle" value="0.25"/> - <stat name="MemManU_I_duty_cycle" value="1"/> - <stat name="MemManU_D_duty_cycle" value="0.25"/> - <stat name="ALU_duty_cycle" value="0.9"/> - <stat name="MUL_duty_cycle" value="0.5"/> - <stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average --> - <stat name="ALU_cdb_duty_cycle" value="0.9"/> - <stat name="MUL_cdb_duty_cycle" value="0.5"/> - <stat name="FPU_cdb_duty_cycle" value="15"/> - <component id="system.core0.predictor" name="PBT"> - <!-- branch predictor; tournament predictor see Alpha implementation --> - <param name="local_predictor_size" value="10,3"/> - <param name="local_predictor_entries" value="1024"/> - <param name="global_predictor_entries" value="4096"/> - <param name="global_predictor_bits" value="2"/> - <param name="chooser_predictor_entries" value="4096"/> - <param name="chooser_predictor_bits" value="2"/> - <!-- These parameters can be combined like below in next version - <param name="load_predictor" value="10,3,1024"/> - <param name="global_predictor" value="4096,2"/> - <param name="predictor_chooser" value="4096,2"/> - --> - </component> - <component id="system.core0.itlb" name="itlb"> - <param name="number_entries" value="1"/> - <stat name="total_accesses" value="0"/> - <stat name="total_misses" value="0"/> - <stat name="conflicts" value="0"/> - <!-- there is no write requests to itlb although writes happen to itlb after miss, - which is actually a replacement --> - </component> - <component id="system.core0.icache" name="icache"> - <!-- there is no write requests to itlb although writes happen to it after miss, - which is actually a replacement --> - <param name="icache_config" value="16384,128,4,1,1,3,8,0"/> - <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> - <!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate --> - <param name="buffer_sizes" value="16, 16, 16,0"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="total_instructions_match_mcpat"/> - <stat name="read_misses" value="0"/> - <stat name="conflicts" value="0"/> - </component> - <component id="system.core0.dtlb" name="dtlb"> - <param name="number_entries" value="1"/> - <stat name="total_accesses" value="0"/> - <stat name="total_misses" value="0"/> - <stat name="conflicts" value="0"/> - </component> - <component id="system.core0.ccache" name="ccache"> - <!-- all the buffer related are optional --> - <param name="ccache_config" value="16384,64,2,1,1,3,8,0"/> - <param name="buffer_sizes" value="16, 16, 16, 0"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/> - <stat name="write_accesses" value="0"/> - <stat name="read_misses" value="ccache_read_misses_match_mcpat"/> - <stat name="write_misses" value="0"/> - <stat name="conflicts" value="0"/> - </component> - <component id="system.core0.tcache" name="tcache"> - <!-- all the buffer related are optional --> - <param name="tcache_config" value="49152,128,8,1,1,3,8,0"/> - <param name="buffer_sizes" value="16, 16, 16, 0"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/> - <stat name="write_accesses" value="0"/> - <stat name="read_misses" value="tcache_read_misses_match_mcpat"/> - <stat name="write_misses" value="0"/> - <stat name="conflicts" value="0"/> - </component> - <!--model the shared memory by mimicing dcache--> - <component id="system.core0.sharedmemory" name="sharedmemory"> - <!-- all the buffer related are optional --> - <param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/> - <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> - <param name="buffer_sizes" value="16, 16, 16, 16"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/> - <stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/> - <stat name="read_misses" value="0"/> - <stat name="write_misses" value="0"/> - <stat name="conflicts" value="0"/> - </component> - <component id="system.core0.dcache" name="dcache"> - <!-- all the buffer related are optional --> - <param name="dcache_config" value="16384,32,4,1,1,3,8,0"/> - <param name="buffer_sizes" value="16, 16, 16, 0"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="dcache_read_access_match_mcpat"/> - <stat name="write_accesses" value="dcache_write_access_match_mcpat"/> - <stat name="read_misses" value="dcache_read_miss_match_mcpat"/> - <stat name="write_misses" value="dcache_write_miss_match_mcpat"/> - <stat name="conflicts" value="0"/> - </component> - <component id="system.core0.BTB" name="BTB"> - <!-- all the buffer related are optional --> - <param name="BTB_config" value="8192,4,2,1, 1,3"/> - <!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> - </component> - </component> - <component id="system.L1Directory0" name="L1Directory0"> - <param name="Directory_type" value="0"/> - <!--0 cam based shadowed tag. 1 directory cache --> - <param name="Dir_config" value="2048,1,0,1, 4, 4,8"/> - <!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> - <param name="buffer_sizes" value="8, 8, 8, 8"/> - <!-- all the buffer related are optional --> - <param name="clockrate" value="1400"/> - <param name="ports" value="1,1,1"/> - <!-- number of r, w, and rw search ports --> - <param name="device_type" value="0"/> - <!-- altough there are multiple access types, - Performance simulator needs to cast them into reads or writes - e.g. the invalidates can be considered as writes --> - <stat name="read_accesses" value="800000"/> - <stat name="write_accesses" value="27276"/> - <stat name="read_misses" value="1632"/> - <stat name="write_misses" value="183"/> - <stat name="conflicts" value="20"/> - <stat name="duty_cycle" value="0.45"/> - </component> - <component id="system.L2Directory0" name="L2Directory0"> - <param name="Directory_type" value="1"/> - <!--0 cam based shadowed tag. 1 directory cache --> - <param name="Dir_config" value="1048576,16,16,1,2, 100"/> - <!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,--> - <param name="buffer_sizes" value="8, 8, 8, 8"/> - <!-- all the buffer related are optional --> - <param name="clockrate" value="1400"/> - <param name="ports" value="1,1,1"/> - <!-- number of r, w, and rw search ports --> - <param name="device_type" value="0"/> - <!-- altough there are multiple access types, - Performance simulator needs to cast them into reads or writes - e.g. the invalidates can be considered as writes --> - <stat name="read_accesses" value="0"/> - <stat name="write_accesses" value="0"/> - <stat name="read_misses" value="0"/> - <stat name="write_misses" value="0"/> - <stat name="conflicts" value="0"/> - <stat name="duty_cycle" value="0.45"/> - </component> - <component id="system.L20" name="L20"> - <!-- all the buffer related are optional --> - <param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/> - <!-- consider 4-way bank interleaving for Niagara 1 --> - <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> - <param name="buffer_sizes" value="16, 16, 16, 16"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <param name="clockrate" value="2962"/> - <param name="ports" value="1,1,1"/> - <!-- number of r, w, and rw ports --> - <param name="device_type" value="0"/> - <stat name="read_accesses" value="200000"/> - <stat name="write_accesses" value="0"/> - <stat name="read_misses" value="0"/> - <stat name="write_misses" value="0"/> - <stat name="conflicts" value="0"/> - <stat name="duty_cycle" value="0.5"/> - </component> - -<!--**********************************************************************--> -<component id="system.L30" name="L30"> - <param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/> - <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy --> - <param name="clockrate" value="3500"/> - <param name="ports" value="1,1,1"/> - <!-- number of r, w, and rw ports --> - <param name="device_type" value="0"/> - <param name="buffer_sizes" value="16, 16, 16, 16"/> - <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size--> - <stat name="read_accesses" value="58824"/> - <stat name="write_accesses" value="27276"/> - <stat name="read_misses" value="1632"/> - <stat name="write_misses" value="183"/> - <stat name="conflicts" value="0"/> - <stat name="duty_cycle" value="0.35"/> - </component> - - -<!--**********************************************************************--> - <component id="system.NoC0" name="noc0"> - <param name="clockrate" value="700"/> - <param name="type" value="1"/> - <!-- 1 NoC, O bus --> - <param name="horizontal_nodes" value="2"/> - <param name="vertical_nodes" value="1"/> - <param name="has_global_link" value="0"/> - <!-- 1 has global link, 0 does not have global link --> - <param name="link_throughput" value="1"/><!--w.r.t clock --> - <param name="link_latency" value="1"/><!--w.r.t clock --> - <!-- througput >= latency --> - <!-- Router architecture --> - <param name="input_ports" value="6"/> - <param name="output_ports" value="6"/> - <param name="virtual_channel_per_port" value="1"/> - <!-- input buffer; in classic routers only input ports need buffers --> - <param name="flit_bits" value="32"/> - <param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs--> - <param name="chip_coverage" value="1"/> - <!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 --> - <stat name="total_accesses" value="0"/> - <!-- This is the number of total accesses within the whole network not for each router --> - <stat name="duty_cycle" value="0.6"/> - </component> -<!--**********************************************************************--> -<!--**********************************************************************--> - - <component id="system.mem" name="mem"> - <!-- Main memory property --> - <param name="mem_tech_node" value="23"/> - <param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB --> - <param name="peak_transfer_rate" value="3200"/><!--MB/S--> - <param name="internal_prefetch_of_DRAM_chip" value="4"/> - <!-- 2 for DDR, 4 for DDR2, 8 for DDR3...--> - <!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property --> - <!-- above numbers can be easily found from Wikipedia --> - <param name="capacity_per_channel" value="4096"/> <!-- MB --> - <!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank - Current McPAT assumes single DIMMs are used.--> - <param name="number_ranks" value="2"/> - <param name="num_banks_of_DRAM_chip" value="6"/> - <param name="Block_width_of_DRAM_chip" value="64"/> <!-- B --> - <param name="output_width_of_DRAM_chip" value="8"/> - <!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip--> - <!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip--> - <param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 --> - <param name="burstlength_of_DRAM_chip" value="8"/> - <stat name="memory_accesses" value="1052"/> - <stat name="memory_reads" value="1052"/> - <stat name="memory_writes" value="1052"/> - </component> - <component id="system.mc" name="mc"> - <!-- Memeory controllers are for DDR(2,3...) DIMMs --> - <!-- current version of McPAT uses published values for base parameters of memory controller - improvments on MC will be added in later versions. --> - <param name="type" value="0"/> <!-- 1: low power; 0 high performance --> - <param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1--> - <param name="peak_transfer_rate" value="29568"/><!--MB/S Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs --> - <param name="block_size" value="64"/><!--B--> - <param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers --> - <!-- current McPAT only supports homogeneous memory controllers --> - <param name="memory_channels_per_mc" value="2"/> - <param name="number_ranks" value="1"/> - <param name="withPHY" value="0"/> - <!-- # of ranks of each channel--> - <param name="req_window_size_per_channel" value="16"/> - <param name="IO_buffer_size_per_channel" value="16"/> - <param name="databus_width" value="32"/> - <param name="addressbus_width" value="32"/> - <param name="PRT_entries" value="32"/> - <!-- # of empirical DRAM model parameter --> - <param name="dram_cmd_coeff" value="0"/> - <param name="dram_act_coeff" value="0"/> - <param name="dram_nop_coeff" value="0"/> - <param name="dram_activity_coeff" value="0"/> - <param name="dram_pre_coeff" value="3.8475e-8f"/> - <param name="dram_rd_coeff" value="7.74707143e-8f"/> - <param name="dram_wr_coeff" value="3.54664286e-8f"/> - <param name="dram_req_coeff" value="0"/> - <param name="dram_const_coeff" value="0"/> - - <!-- McPAT will add the control bus width to the addressbus width automatically --> - <stat name="memory_accesses" value="memory_accesses_match_mcpat"/> - <stat name="memory_reads" value="memory_reads_match_mcpat"/> - <stat name="memory_writes" value="memory_writes_match_mcpat"/> - <!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate - the average power per MC or per channel. This is sufficent for most application. - Further trackdown can be easily added in later versions. --> - </component> -<!--**********************************************************************--> - <component id="system.niu" name="niu"> - <!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller --> - <!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns. - the low bound of clock rate of a 10Gb MAC is 150Mhz --> - <param name="type" value="0"/> <!-- 1: low power; 0 high performance --> - <param name="clockrate" value="350"/> - <param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port --> - <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 --> - <stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth --> - <!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate - the average power per nic or per channel. This is sufficent for most application. --> - </component> -<!--**********************************************************************--> - <component id="system.pcie" name="pcie"> - <!-- On chip PCIe controller, including Phy--> - <!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns. - the low bound of clock rate of a PCIe per lane logic is 120Mhz --> - <param name="type" value="0"/> <!-- 1: low power; 0 high performance --> - <param name="withPHY" value="1"/> - <param name="clockrate" value="350"/> - <param name="number_units" value="0"/> - <param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 --> - <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 --> - <stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth --> - <!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate - the average power per pcie controller or per channel. This is sufficent for most application. --> - </component> -<!--**********************************************************************--> - <component id="system.flashc" name="flashc"> - <param name="number_flashcs" value="0"/> - <param name="type" value="1"/> <!-- 1: low power; 0 high performance --> - <param name="withPHY" value="1"/> - <param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S --> - <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 --> - <stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth --> - <!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate - the average power per fc or per channel. This is sufficent for most application --> - </component> -<!--**********************************************************************--> - - </component> -</component> diff --git a/cutlass-example/half.h b/cutlass-example/half.h deleted file mode 100644 index ee536e5..0000000 --- a/cutlass-example/half.h +++ /dev/null @@ -1,743 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! - \file - \brief Host-side implementation of half-precision float -*/ - -#pragma once - -#include <stdint.h> -#include <cmath> -#include <limits> -#include <utility> -#include <utility> - -#include <iomanip> -#include <istream> -#include <ostream> - -#include <cuda_fp16.h> - -namespace cutlass { - -/// IEEE binary16 floating-point value -class half_t { - public: - half_t(); - half_t(int); /// conversion from integer - half_t(float); /// conversion from fp32 - half_t(double); /// conversion from fp64 - - static half_t bitcast(unsigned short); /// bitcast performs no conversion - - static half_t convert(float const&); /// FP conversion - round toward nearest even - static float convert(unsigned short const&); /// floating point conversion to fp32 - - static half_t zero() { return bitcast(0); } /// +zero - static half_t one() { return bitcast(0x3c00); } /// one - static half_t nan() { return bitcast(0x7fff); } /// canonical not a number - static half_t inf() { return bitcast(0x7c00); } /// +infinity - static half_t ninf() { return bitcast(0xfc00); } /// -infinity - static half_t epsilon() { return bitcast(0x1000); } /// Machine epsilon - - bool signbit() const; /// sign bit - true: negative, false: positive - int exponent() const; /// unbiased exponent - unsigned short mantissa() const; /// mantissa bits - - bool isfinite() const; /// true if neither inf nor nan - bool isinf() const; /// true if value is + or - infinity - bool isnan() const; /// true if value is not a number - bool isnormal() const; /// true if nonzero value is normalized - bool iszero() const; /// true if value is + or - zero - - bool operator==(half_t const&) const; - bool operator!=(half_t const&) const; - bool operator==(float const&) const; - bool operator!=(float const&) const; - - bool operator<(half_t const&) const; - bool operator<=(half_t const&) const; - bool operator>(half_t const&) const; - bool operator>=(half_t const&) const; - - half_t operator+(half_t const&) const; - half_t operator-() const; - half_t operator-(half_t const&) const; - half_t operator*(half_t const&)const; - half_t operator/(half_t const&) const; - - half_t& operator+=(half_t const&); - half_t& operator-=(half_t const&); - half_t& operator*=(half_t const&); - half_t& operator/=(half_t const&); - - half_t& operator++(); - half_t& operator--(); - half_t operator++(int); - half_t operator--(int); - - operator bool() const; /// false if zero - operator int() const; /// conversion to int - operator float() const; /// conversion to fp32 - operator half() const; /// conversion to half - - uint16_t& raw() { return x; } - uint16_t raw() const { return x; } - - public: - /// data - unsigned short x; -}; - -/// Packed pair of half-precision elements -class half2_t { - public: - half2_t(); - half2_t(half_t lo, half_t hi); - half2_t(std::pair<float, float> const&); - explicit half2_t(unsigned data); - - half2_t operator+(half2_t const&) const; - half2_t operator-(half2_t const&) const; - half2_t operator*(half2_t const&)const; - half2_t operator/(half2_t const&) const; - - half2_t& operator+=(half2_t const&); - half2_t& operator-=(half2_t const&); - half2_t& operator*=(half2_t const&); - half2_t& operator/=(half2_t const&); - - float dot(half2_t const&) const; /// dot product with single-precision accumulation - float dot(half2_t const&, float) const; /// dot product with single-precision accumulation - - half_t doth(half2_t const&) const; /// dot product with half_t-precision accumulation - half_t doth(half2_t const&, half_t) const; /// dot product with half_t-precision accumulation - - unsigned packed() const; - - operator std::pair<float, float>() const; - operator unsigned() const; - - public: - half_t lo; - half_t hi; -}; - -template <typename Dest, typename Src> -Dest bitcast(Src const&); -template <> -float bitcast<float, unsigned>(unsigned const&); -template <> -float bitcast<float, int>(int const&); -template <> -unsigned bitcast<unsigned, float>(float const&); -template <> -half_t bitcast<half_t, unsigned short>(unsigned short const&); -template <> -unsigned short bitcast<unsigned short, half_t>(half_t const&); -template <> -half bitcast<half, unsigned short>(unsigned short const&); -} // namespace cutlass - -cutlass::half_t operator+(float, cutlass::half_t const&); -cutlass::half_t operator-(float, cutlass::half_t const&); -cutlass::half_t operator*(float, cutlass::half_t const&); -cutlass::half_t operator/(float, cutlass::half_t const&); - -std::ostream& operator<<(std::ostream&, cutlass::half_t const&); /// writes a half_t -std::istream& operator>>(std::istream&, cutlass::half_t&); /// reads a half_t - -#ifdef BOOST_LEXICAL_CAST_INCLUDED -namespace boost { - -/// lexical cast from string to half_t -template <> -cutlass::half_t lexical_cast<cutlass::half_t>(std::string const& arg); - -/// lexical cast from half_t to string -template <> -std::string lexical_cast<std::string>(cutlass::half_t const& arg); -} // namespace boost -#endif - -#define HLF_MANT_DIG 10 - -namespace std { - -cutlass::half_t abs(cutlass::half_t const&); /// absolute value - -bool isnan(cutlass::half_t const&); /// true if argument is NaN - -bool isfinite(cutlass::half_t const&); /// true if argument is neither NaN nor infinity - -cutlass::half_t nanh(const char* = 0); /// returns a not-a-number - -bool isinf(cutlass::half_t const&); /// returns true if argument is infinitey (+ or -) - -bool isnormal( - cutlass::half_t const&); /// returns true if argument is normal (neither zero nor infinity) - -int fpclassify(cutlass::half_t const&); /// returns a flag classifying floating-point value - -bool signbit(cutlass::half_t const&); /// returns true if negative, false if positive - -cutlass::half_t sqrt(cutlass::half_t const&); /// square root of half_t - -/// Numeric limits -template <> -struct numeric_limits<cutlass::half_t> { - static bool const is_specialized = true; - static bool const is_signed = true; - static bool const is_integer = false; - static bool const is_exact = false; - static bool const has_infinity = true; - static bool const has_quiet_NaN = true; - static bool const has_signaling_NaN = false; - static std::float_denorm_style const has_denorm = std::denorm_present; - static bool const has_denorm_loss = true; - static std::float_round_style const round_style = std::round_to_nearest; - static bool const is_iec559 = false; - static bool const is_bounded = true; - static bool const is_modulo = false; - static int const digits = HLF_MANT_DIG; - - static cutlass::half_t min() { return cutlass::half_t::bitcast(0x0001); } - - static cutlass::half_t lowest() { return cutlass::half_t::bitcast(0xfbff); } - - static cutlass::half_t max() { return cutlass::half_t::bitcast(0x7bff); } - - /// Returns smallest finite value - static cutlass::half_t epsilon() { return cutlass::half_t::epsilon(); } - - /// Returns smallest finite value - static cutlass::half_t round_error() { return cutlass::half_t(0.5f); } - - /// Returns smallest finite value - static cutlass::half_t infinity() { return cutlass::half_t::inf(); } - - /// Returns smallest finite value - static cutlass::half_t quiet_NaN() { return cutlass::half_t::nan(); } - - /// Returns smallest finite value - static cutlass::half_t signaling_NaN() { return cutlass::half_t::nan(); } - - /// Returns smallest finite value - static cutlass::half_t denorm_min() { return cutlass::half_t::bitcast(0x0001); } -}; -} // namespace std - -// -// -// - -inline cutlass::half_t cutlass::half_t::bitcast(unsigned short _x) { - half_t h; - h.x = _x; - return h; -} - -/// FP32 -> FP16 conversion - rounds to nearest even -inline cutlass::half_t cutlass::half_t::convert(float const& flt) { - // software implementation rounds toward nearest even - unsigned const& s = *reinterpret_cast<unsigned const*>(&flt); - uint16_t sign = uint16_t((s >> 16) & 0x8000); - int16_t exp = uint16_t(((s >> 23) & 0xff) - 127); - int mantissa = s & 0x7fffff; - uint16_t u = 0; - - if ((s & 0x7fffffff) == 0) { - // sign-preserving zero - return cutlass::half_t::bitcast(sign); - } - - if (exp > 15) { - if (exp == 128 && mantissa) { - // not a number - u = 0x7fff; - } else { - // overflow to infinity - u = sign | 0x7c00; - } - return cutlass::half_t::bitcast(u); - } - - int sticky_bit = 0; - - if (exp >= -14) { - // normal fp32 to normal fp16 - exp = uint16_t(exp + uint16_t(15)); - u = uint16_t(((exp & 0x1f) << 10)); - u = uint16_t(u | (mantissa >> 13)); - } else { - // normal single-precision to subnormal half_t-precision representation - int rshift = (-14 - exp); - if (rshift < 32) { - mantissa |= (1 << 23); - - sticky_bit = ((mantissa & ((1 << rshift) - 1)) != 0); - - mantissa = (mantissa >> rshift); - u = (uint16_t(mantissa >> 13) & 0x3ff); - } else { - mantissa = 0; - u = 0; - } - } - - // round to nearest even - int round_bit = ((mantissa >> 12) & 1); - sticky_bit |= ((mantissa & ((1 << 12) - 1)) != 0); - - if ((round_bit && sticky_bit) || (round_bit && (u & 1))) { - u = uint16_t(u + 1); - } - - u |= sign; - - return cutlass::half_t::bitcast(u); -} - -inline float cutlass::half_t::convert(unsigned short const& h) { - int sign = ((h >> 15) & 1); - int exp = ((h >> 10) & 0x1f); - int mantissa = (h & 0x3ff); - unsigned f = 0; - - if (exp > 0 && exp < 31) { - // normal - exp += 112; - f = (sign << 31) | (exp << 23) | (mantissa << 13); - } else if (exp == 0) { - if (mantissa) { - // subnormal - exp += 113; - while ((mantissa & (1 << 10)) == 0) { - mantissa <<= 1; - exp--; - } - mantissa &= 0x3ff; - f = (sign << 31) | (exp << 23) | (mantissa << 13); - } else { - // sign-preserving zero - f = (sign << 31); - } - } else if (exp == 31) { - if (mantissa) { - f = 0x7fffffff; // not a number - } else { - f = (0xff << 23) | (sign << 31); // inf - } - } - return *reinterpret_cast<float const*>(&f); -} - -inline cutlass::half_t::half_t() {} - -inline cutlass::half_t::half_t(int i) { x = convert(float(i)).x; } - -inline cutlass::half_t::half_t(float f) { x = convert(f).x; } - -inline cutlass::half_t::half_t(double d) { x = convert(float(d)).x; } - -inline bool cutlass::half_t::signbit() const { return (x >> 15) & 1; } - -inline int cutlass::half_t::exponent() const { return ((x >> 10) & 0x1f) - 15; } - -inline unsigned short cutlass::half_t::mantissa() const { return x & 0x3ff; } - -inline cutlass::half_t::operator bool() const { return (x & 0x7fff) != 0; } - -inline cutlass::half_t::operator int() const { return static_cast<int>(convert(x)); } - -inline cutlass::half_t::operator float() const { return convert(x); } - -inline cutlass::half_t::operator half() const { return cutlass::bitcast<half, unsigned short>(x); } - -inline bool cutlass::half_t::operator==(cutlass::half_t const& h) const { - if (iszero() && h.iszero()) { - return true; - } - return x == h.x; -} - -inline bool cutlass::half_t::operator!=(cutlass::half_t const& h) const { - if (iszero() && h.iszero()) { - return false; - } - return x != h.x; -} - -inline bool cutlass::half_t::operator==(float const& b) const { return x == half_t(b).x; } - -inline bool cutlass::half_t::operator!=(float const& b) const { return x != half_t(b).x; } - -inline bool cutlass::half_t::iszero() const { return (x & 0x7fff) == 0; } - -inline bool cutlass::half_t::isfinite() const { return (exponent() < 16); } - -inline bool cutlass::half_t::isnan() const { - int exp = ((x >> 10) & 0x1f); - if (exp == 0x1f) { - return (x & 0x3ff) != 0; - } - return false; -} - -inline bool cutlass::half_t::isinf() const { - int exp = ((x >> 10) & 0x1f); - if (exp == 0x1f) { - return (x & 0x3ff) == 0; - } - return false; -} - -inline bool cutlass::half_t::isnormal() const { - int exp = exponent(); - return exp > -15 && exp < 16; -} - -inline bool cutlass::half_t::operator<(half_t const& h) const { - int sign = ((x >> 15) & 1); - int h_sign = ((h.x >> 15) & 1); - if (sign == h_sign) { - return (x & 0x7fff) < (h.x & 0x7fff); - } else if (sign) { - return true; - } - return false; -} - -inline bool cutlass::half_t::operator<=(half_t const& h) const { - int sign = ((x >> 15) & 1); - int h_sign = ((h.x >> 15) & 1); - if (sign == h_sign) { - return (x & 0x7fff) <= (h.x & 0x7fff); - } else if (sign) { - return true; - } - return false; -} - -inline bool cutlass::half_t::operator>(half_t const& h) const { - int sign = ((x >> 15) & 1); - int h_sign = ((h.x >> 15) & 1); - if (sign == h_sign) { - return (x & 0x7fff) > (h.x & 0x7fff); - } else if (h_sign) { - return true; - } - return false; -} - -inline bool cutlass::half_t::operator>=(half_t const& h) const { - int sign = ((x >> 15) & 1); - int h_sign = ((h.x >> 15) & 1); - if (sign == h_sign) { - return (x & 0x7fff) >= (h.x & 0x7fff); - } else if (h_sign) { - return true; - } - return false; -} - -inline cutlass::half_t cutlass::half_t::operator+(cutlass::half_t const& b) const { - return cutlass::half_t(float(*this) + float(b)); -} - -inline cutlass::half_t cutlass::half_t::operator-() const { return bitcast(x ^ 0x8000); } - -inline cutlass::half_t cutlass::half_t::operator-(cutlass::half_t const& b) const { - return cutlass::half_t(float(*this) - float(b)); -} - -inline cutlass::half_t cutlass::half_t::operator*(cutlass::half_t const& b) const { - return cutlass::half_t(float(*this) * float(b)); -} - -inline cutlass::half_t cutlass::half_t::operator/(cutlass::half_t const& b) const { - return cutlass::half_t(float(*this) / float(b)); -} - -inline cutlass::half_t& cutlass::half_t::operator+=(cutlass::half_t const& b) { - *this = cutlass::half_t(float(*this) + float(b)); - return *this; -} - -inline cutlass::half_t& cutlass::half_t::operator-=(cutlass::half_t const& b) { - *this = cutlass::half_t(float(*this) - float(b)); - return *this; -} - -inline cutlass::half_t& cutlass::half_t::operator*=(cutlass::half_t const& b) { - *this = cutlass::half_t(float(*this) * float(b)); - return *this; -} - -inline cutlass::half_t& cutlass::half_t::operator/=(cutlass::half_t const& b) { - *this = cutlass::half_t(float(*this) / float(b)); - return *this; -} - -inline cutlass::half_t& cutlass::half_t::operator++() { - *this = cutlass::half_t(float(*this) + 1.0f); - return *this; -} - -inline cutlass::half_t& cutlass::half_t::operator--() { - *this = cutlass::half_t(float(*this) - 1.0f); - return *this; -} - -inline cutlass::half_t cutlass::half_t::operator++(int) { - half_t h = *this; - *this = cutlass::half_t(float(*this) + 1.0f); - return h; -} - -inline cutlass::half_t cutlass::half_t::operator--(int) { - half_t h = *this; - *this = cutlass::half_t(float(*this) - 1.0f); - return h; -} - -inline cutlass::half_t operator+(float a, cutlass::half_t const& b) { - return cutlass::half_t(a + float(b)); -} - -inline cutlass::half_t operator-(float a, cutlass::half_t const& b) { - return cutlass::half_t(a - float(b)); -} - -inline cutlass::half_t operator*(float a, cutlass::half_t const& b) { - return cutlass::half_t(a * float(b)); -} - -inline cutlass::half_t operator/(float a, cutlass::half_t const& b) { - return cutlass::half_t(a / float(b)); -} - -// -// -// - -inline cutlass::half2_t::half2_t() {} - -inline cutlass::half2_t::half2_t(half_t lo, half_t hi) : lo(lo), hi(hi) {} - -inline cutlass::half2_t::half2_t(std::pair<float, float> const& p) : lo(p.first), hi(p.second) {} - -inline cutlass::half2_t::half2_t(unsigned data) - : lo(half_t::bitcast(uint16_t(data & 0x0ffff))), - hi(half_t::bitcast(uint16_t((data >> 16) & 0x0ffff))) {} - -inline cutlass::half2_t cutlass::half2_t::operator+(half2_t const& b) const { - return half2_t(lo + b.lo, hi + b.hi); -} - -inline cutlass::half2_t cutlass::half2_t::operator-(half2_t const& b) const { - return half2_t(lo - b.lo, hi - b.hi); -} - -inline cutlass::half2_t cutlass::half2_t::operator*(half2_t const& b) const { - return half2_t(lo * b.lo, hi * b.hi); -} - -inline cutlass::half2_t cutlass::half2_t::operator/(half2_t const& b) const { - return half2_t(lo / b.lo, hi / b.hi); -} - -inline cutlass::half2_t& cutlass::half2_t::operator+=(half2_t const& b) { - lo += b.lo; - hi += b.hi; - return *this; -} - -inline cutlass::half2_t& cutlass::half2_t::operator-=(half2_t const& b) { - lo -= b.lo; - hi -= b.hi; - return *this; -} - -inline cutlass::half2_t& cutlass::half2_t::operator*=(half2_t const& b) { - lo *= b.lo; - hi *= b.hi; - return *this; -} - -inline cutlass::half2_t& cutlass::half2_t::operator/=(half2_t const& b) { - lo /= b.lo; - hi /= b.hi; - return *this; -} - -inline float cutlass::half2_t::dot(half2_t const& b) const { - return float(lo) * float(b.lo) + float(hi) * float(b.hi); -} - -inline float cutlass::half2_t::dot(half2_t const& b, float c) const { return c + dot(b); } - -inline cutlass::half_t cutlass::half2_t::doth(half2_t const& b) const { - return cutlass::half_t(dot(b)); -} - -inline cutlass::half_t cutlass::half2_t::doth(half2_t const& b, half_t c) const { - return cutlass::half_t(dot(b, float(c))); -} - -inline cutlass::half2_t::operator std::pair<float, float>() const { - return std::pair<float, float>(float(lo), float(hi)); -} - -inline unsigned cutlass::half2_t::packed() const { return (lo.x | (hi.x << 16)); } - -inline cutlass::half2_t::operator unsigned() const { return packed(); } - -// -// -// - -template <> -inline float cutlass::bitcast<float, unsigned>(unsigned const& u) { - return *reinterpret_cast<float const*>(&u); -} - -template <> -inline float cutlass::bitcast<float, int>(int const& i) { - return *reinterpret_cast<float const*>(&i); -} - -template <> -inline unsigned cutlass::bitcast<unsigned, float>(float const& f) { - return *reinterpret_cast<unsigned const*>(&f); -} - -template <> -inline cutlass::half_t cutlass::bitcast<cutlass::half_t, unsigned short>(unsigned short const& s) { - return *reinterpret_cast<cutlass::half_t const*>(&s); -} - -template <> -inline unsigned short cutlass::bitcast<unsigned short, cutlass::half_t>(cutlass::half_t const& h) { - return *reinterpret_cast<unsigned short const*>(&h); -} - -template <> -inline half cutlass::bitcast<half, unsigned short>(unsigned short const& s) { - return *reinterpret_cast<half const*>(&s); -} - -// -// Lexical casts -// - -#ifdef BOOST_LEXICAL_CAST_INCLUDED -namespace boost { -template <> -cutlass::half_t lexical_cast<cutlass::half_t>(std::string const& arg) { - return cutlass::half_t(boost::lexical_cast<float>(arg)); -} - -template <> -std::string lexical_cast<std::string>(cutlass::half_t const& arg) { - return boost::lexical_cast<std::string>(float(arg)); -} -} // namespace boost -#endif - -// -// Standard Library Operations -// - -// std -namespace std { - -inline cutlass::half_t abs(cutlass::half_t const& h) { - return cutlass::half_t::bitcast(h.x & 0x7fff); -} - -inline bool isnan(cutlass::half_t const& h) { return h.isnan(); } - -inline bool isfinite(cutlass::half_t const& h) { return h.isfinite(); } - -inline cutlass::half_t nanh(const char*) { return cutlass::half_t::nan(); } - -inline bool isinf(cutlass::half_t const& h) { return h.isinf(); } - -inline bool isnormal(cutlass::half_t const& h) { return h.isnormal(); } - -inline int fpclassify(cutlass::half_t const& h) { - int exp = h.exponent(); - unsigned short mantissa = h.mantissa(); - if (exp < -14) { - if (mantissa == 0) { - return FP_ZERO; - } else { - return FP_SUBNORMAL; - } - } else if (exp > 15) { - if (mantissa == 0) { - return FP_INFINITE; - } else { - return FP_NAN; - } - } - return FP_NORMAL; -} - -inline bool signbit(cutlass::half_t const& h) { return h.signbit(); } - -inline cutlass::half_t sqrt(cutlass::half_t const& h) { - return cutlass::half_t(std::sqrt(float(h))); -} -} // namespace std - -// -// Stream interactions -// - -/// put to stream - half_t-precision types bitcast as unsigned shorts if base is hexadecimal -inline std::ostream& operator<<(std::ostream& out, cutlass::half_t const& h) { - if (out.flags() & std::ios::hex) { - return out << h.x; - } else { - return out << float(h); - } -} - -/// read from stream - half_t-precision types parsed as unsigned shorts if base is hexadecimal -inline std::istream& operator>>(std::istream& in, cutlass::half_t& h) { - if (in.flags() & std::ios::hex) { - unsigned short u = 0; - in >> u; - h = cutlass::half_t::bitcast(u); - } else { - float f = 0; - in >> f; - h = cutlass::half_t(f); - } - return in; -} diff --git a/cutlass-example/host_tensor.h b/cutlass-example/host_tensor.h deleted file mode 100644 index 0936336..0000000 --- a/cutlass-example/host_tensor.h +++ /dev/null @@ -1,365 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -#pragma once - -/*! \file - \brief Template class to perform computations on tensors and manage memory. -*/ - -#include <cutlass/cutlass.h> -#include <cutlass/matrix_traits.h> -#include <device_memory.h> -#include <host_tensor_view.h> -#include <type_traits.h> -#include <vector> - -namespace cutlass { - -template <typename T, bool DeviceBacked_ = true> -class HostTensor : public HostTensorView<T> { - public: - /// Type used for device-side allocations - typedef typename TypeTraits<T>::device_type DeviceType; - - /// Base class - typedef HostTensorView<T> Base; - - /// If true, allocates device side memory - static bool const DeviceBacked = DeviceBacked_; - - /// Rank of tensor - static int const Rank = Base::Rank; - - /// Type used to compute the offset of an element to the base of a tensor - typedef typename Base::Offset_t Offset_t; - - /// Tensor reference to host memory - typedef typename Base::TensorRef_t TensorRef_t; - - /// Tensor reference to device memory - typedef TensorRef<DeviceType, TensorRef_t::Rank> DeviceTensorRef; - - /// Tensor reference to constant device memory - typedef TensorRef<DeviceType const, TensorRef_t::Rank> ConstDeviceTensorRef; - - /// Coordinate into tensor - typedef typename Base::Coord_t Coord_t; - - private: - /// Host-side memory allocation - std::vector<T> host_; - - /// Device-side memory - cutlass::device_memory::allocation<DeviceType> device_; - - public: - // - // Device and Host Methods - // - - /// Default constructor - HostTensor() {} - - /// Constructs a Tensor_view from stride and size - HostTensor(Coord_t const& _stride, Coord_t const& _size) { reset(_stride, _size); } - - /// Constructs a HostTensor from size - infers strides - HostTensor(Coord_t const& _size) { - Coord_t _stride = make_Coord( - _size.at(2) * _size.at(1) * _size.at(0), _size.at(1) * _size.at(0), _size.at(0), 1); - reset(_stride, _size); - } - - /// Returns the number of elements needed to back vector - size_t capacity() { return Base::capacity(); } - - /// Returns true if the Tensor_view is bound to some memory - bool good() const { return Base::good(); } - - /// Updates the reference and size of a Tensor_view object - void reset(Coord_t const& _stride, Coord_t const& _size) { - size_t _capacity = _size.at(0) * _stride.at(0); - - DeviceType* _device_memory = nullptr; - if (DeviceBacked) { - _device_memory = cutlass::device_memory::allocate<DeviceType>(_capacity); - } - - host_.clear(); - host_.resize(_capacity); - for (size_t i = 0; i < _capacity; ++i) { - host_[i] = T((int)0xdeadbeef); - } - device_.reset(_device_memory, _capacity); - - Base::reset(TensorRef_t(host_.data(), _stride), _size); - } - - /// Initializes the host tensor as a matrix - void resize_matrix(int rows, int columns, MatrixLayout::Kind layout) { - bool col_major = (layout == MatrixLayout::kColumnMajor); - int ldm = (col_major ? rows : columns); - - Coord_t stride = make_Coord(rows * columns, col_major ? 1 : ldm, col_major ? ldm : 1, 1); - - Coord_t size = make_Coord(1, rows, columns, 1); - - reset(stride, size); - } - - /// Simplifies resizing the host tensor - void resize(int elements) { resize_matrix(1, elements, MatrixLayout::kColumnMajor); } - - /// Gets pointer to host data - T const* host_data() const { return &host_[0]; } - - /// Gets pointer to host data - T* host_data() { return &host_[0]; } - - /// Gets pointer to device data - DeviceType* device_data() const { return device_.get(); } - - /// Copies data from device to host - void sync_host() { - if (DeviceBacked) { - device_memory::copy_to_host( - host_.data(), reinterpret_cast<T const*>(device_.get()), host_.size()); - } - } - - /// Copies data from host to device - void sync_device() { - if (DeviceBacked) { - device_memory::copy_to_device( - device_.get(), reinterpret_cast<DeviceType const*>(host_.data()), host_.size()); - } - } - - /// Copy data from a caller-supplied device pointer - void copy_to_host(DeviceType const *ptr_device) { - device_memory::copy_to_host( - host_.data(), reinterpret_cast<T const *>(ptr_device), host_.size()); - } - - /// Copies data to a caller-supplied device pointer - void copy_to_device(DeviceType *ptr_device) { - device_memory::copy_to_device( - ptr_device, reinterpret_cast<DeviceType const *>(host_.data()), host_.size()); - } - - /// Accesses the tensor reference pointing to data - TensorRef_t& host_ref() { return Base::ref(); } - - /// Accesses the tensor reference pointing to data - TensorRef_t const& host_ref() const { return Base::ref(); } - - /// Accesses the tensor reference pointing to data - DeviceTensorRef device_ref() const { return DeviceTensorRef(device_data(), stride()); } - - /// Returns a tensor ref to constant memory on the device - ConstDeviceTensorRef const_device_ref() const { - return ConstDeviceTensorRef(device_data(), stride()); - } - - /// Accesses the size - Coord_t const& size() const { return Base::size(); } - - /// Accesses the size - int size(int dim) const { return Base::size(dim); } - - /// Accesses the size - Coord_t const& stride() const { return Base::stride(); } - - /// Accesses the size - int stride(int dim) const { return Base::stride(dim); } - - /// Returns the index of an element - Offset_t offset(Coord_t const& coord) const { return Base::offset(coord); } - - /// Determines whether a location is within a tensor - bool contains(Coord_t const& coord) const { return Base::contains(coord); } - - /// Element-wise accessor - T& at(Coord_t const& coord) const { return Base::at(coord); } - - /// Element-wise accessor - T& operator[](Coord_t const& coord) { return at(coord); } - - /// Element-wise accessor with basic offset - T& at(int idx) const { return Base::at(idx); } - - /// Returns a Tensor_view given location and size quantities - TensorView<T> subview(Coord_t const& _location, Coord_t _size) const { - return Base::subview(_location, _size); - } - - /// Recurses through all dimensions and applies a unary operation - template <typename F> - void elementwise_in_place(F& op, int dim = 0, Offset_t dst_offset_base = 0) { - Base::elementwise_in_place(op, dim, dst_offset_base); - } - - /// Recurses through all dimensions and applies a unary operator, supplying the logical - /// coordinate within the tensor as an argument - template <typename F> - void elementwise_stream(F& op, int dim = 0, Offset_t dst_offset_base = 0) { - Base::elementwise_stream(op, dim, dst_offset_base); - } - - /// Recurses through all dimensions and applies a unary operator, supplying the logical - /// coordinate within the tensor as an argument - template <typename F> - void elementwise_generate(F& op, - int dim = 0, - Offset_t dst_offset_base = 0, - Coord_t coord = Coord_t(0)) { - Base::elementwise_generate(op, dim, dst_offset_base, coord); - } - - /// Recurses through all dimensions and applies a binary operation - template <typename Src, typename F> - bool elementwise_in_place(F& op, - int dim, - TensorView<Src> const& tensor, - Offset_t dst_offset_base = 0, - Offset_t src_offset_base = 0) { - return Base::elementwise_in_place(op, dim, tensor, dst_offset_base, src_offset_base); - } - - /// Accumulate in place - template <typename Src> - TensorView<T>& operator+=(TensorView<Src> const& tensor) { - Base::operator+=(tensor); - sync_device(); - return *this; - } - - /// Subtract in place - template <typename Src> - TensorView<T>& operator-=(TensorView<Src> const& tensor) { - Base::operator-=(tensor); - sync_device(); - return *this; - } - - /// Multiply in place - template <typename Src> - TensorView<T>& operator*=(TensorView<Src> const& tensor) { - Base::operator*=(tensor); - sync_device(); - return *this; - } - - /// Divide in place - template <typename Src> - TensorView<T>& operator/=(TensorView<Src> const& tensor) { - Base::operator/=(tensor); - sync_device(); - return *this; - } - - /// equality with epsilon tolerance - bool equals(TensorView<T> const& tensor, T epsilon) const { - return Base::equals(tensor, epsilon); - } - - /// equality with ulps tolerance - bool bit_equals(TensorView<T> const& tensor, long long ulps_threshold = 0) { - return Base::bit_equals(tensor, ulps_threshold); - } - - /// Computes general matrix product among select dimensions of a tensor - /// Assumes: - /// D: number of independent GEMMs to compute - /// H: height of matrix - /// W: width of matrix - template < - /// Data type of A matrix elements - typename A, - /// Data type of B matrix elements - typename B, - /// Data type of "compute" type (i.e. accumulator) - typename Ctype, - /// Data type of scale factors - typename Stype> - void gemm(TensorView<A> const& tensor_a, TensorView<B> const& tensor_b, Stype alpha, Stype beta) { - Base::template gemm<A, B, Ctype, Stype>(tensor_a, tensor_b, alpha, beta); - } - - /// Fills with random data - template <typename Gen> - void fill_random(Gen generator) { - Base::fill_random(generator); - sync_device(); - } - - /// Procedurally assigns elements - template <typename Gen> - void generate(Gen generator) { - Base::generate(generator); - sync_device(); - } - - /// Procedurally visits elements - template <typename Gen> - void visit(Gen& generator) const { - Base::visit(generator); - } - - /// initializes with identity - void fill_identity() { - Base::fill_identity(); - sync_device(); - } - - /// computes elements as a linear combination of their coordinates - void fill_linear(Coord_t v, T offset = T(0)) { - Base::fill_linear(v, offset); - sync_device(); - } - - /// computes elements as a linear combination of their coordinates - void fill_sequential(T v = T(1), T offset = T(0)) { - Base::fill_sequential(v, offset); - sync_device(); - } - - /// fills with a value - void fill(T val = T(0)) { - Base::fill(val); - sync_device(); - } - - /// Copies from external data source and performs type conversion - template <typename Src> - void fill(TensorView<Src> const& tensor) { - Base::fill(tensor); - sync_device(); - } - - /// Computes the norm of the matrix in double-precision - double norm() const { return Base::norm(); } -}; -} // namespace cutlass diff --git a/cutlass-example/host_tensor_view.h b/cutlass-example/host_tensor_view.h deleted file mode 100644 index 56f02d3..0000000 --- a/cutlass-example/host_tensor_view.h +++ /dev/null @@ -1,542 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Host-side implementation of useful operations -*/ - -#pragma once - -#include <cutlass/cutlass.h> -#include <cutlass/tensor_view.h> -#include <type_traits.h> - -namespace cutlass { - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename SrcType, typename DstType> -struct Cast { - static inline DstType apply(SrcType src) { return static_cast<DstType>(src); }; -}; - -template <> -struct Cast<float, int8_t> { - static inline int8_t apply(float src) { - return static_cast<int8_t>(fmaxf(-128.f, fminf(127.f, src))); - }; -}; - -template <> -struct Cast<float, uint8_t> { - static inline uint8_t apply(float src) { - return static_cast<uint8_t>(fmaxf(0.f, fminf(255.f, src))); - }; -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -template <typename T> -class HostTensorView : public TensorView<T> { - public: - /// Base class - typedef TensorView<T> TensorView_t; - - /// Convention: depth is the first dimension - static int const Dim_D = 0; - - /// Convention: height is the second dimension - static int const Dim_H = 1; - - /// Convention: width is the third dimension - static int const Dim_W = 2; - - /// Convention: channel is the second dimension - static int const Dim_C = 3; - - /// Rank of tensor - static int const Rank = TensorView_t::Rank; - - /// Type used to compute the offset of an element to the base of a tensor - typedef typename TensorView_t::Offset_t Offset_t; - - /// Reference and stride - typedef typename TensorView_t::TensorRef_t TensorRef_t; - - /// Coordinate into tensor - typedef typename TensorView_t::Coord_t Coord_t; - - public: - // - // Device and Host Methods - // - - /// Default constructor - HostTensorView() {} - - /// Constructs a Tensor_view from a TensorRef and size - HostTensorView(TensorRef_t const& _ref, Coord_t const& _size) : TensorView_t(_ref, _size) {} - - /// Accesses the size - Coord_t const& size() const { return TensorView_t::size(); } - - /// Accesses the size of a specified dimension - int size(int dim) const { return size().at(dim); } - - /// Accesses the stride - Coord_t const& stride() const { return TensorView_t::stride(); } - - /// Accesses the stride along a specified dimension - int stride(int dim) const { return stride().at(dim); } - - /// Returns the number of scalar elements needed to store tensor - size_t capacity() const { return size(3) * stride(3) * stride(2) * stride(1) * stride(0); } - - /// Returns true if the Tensor_view is bound to some memory - bool good() const { return TensorView_t::good(); } - - /// Updates the reference and size of a TensorView object - void reset(TensorRef_t const& _ref = TensorRef_t(0), Coord_t const& _size = Coord_t()) { - return TensorView_t::reset(_ref, _size); - } - - /// Accesses the tensor reference pointing to data - TensorRef_t& ref() { return TensorView_t::ref(); } - - /// Accesses the tensor reference pointing to data - TensorRef_t const& ref() const { return TensorView_t::ref(); } - - /// Assigns a tensor view - HostTensorView& operator=(TensorView_t const& _tensor) { - reset(_tensor.ref(), _tensor.size()); - return *this; - } - - /// Returns the index of an element - Offset_t offset(Coord_t const& coord) const { return TensorView_t::offset(coord); } - - /// Determines whether a location is within a tensor - bool contains(Coord_t const& coord) const { return TensorView_t::contains(coord); } - - /// Element-wise accessor - T& at(Coord_t const& coord) const { return TensorView_t::at(coord); } - - /// Element-wise accessor - T& operator[](Coord_t const& coord) const { return at(coord); } - - /// Accesses an element with a raw offset - T& at(int idx) const { return TensorView_t::at(idx); } - - /// Accesses an element with a raw offset - T& operator[](int idx) const { return at(idx); } - - /// Returns a Tensor_view given location and size quantities - TensorView_t subview(Coord_t const& location, Coord_t size) const { - return TensorView_t::subview(location, size); - } - - /// Recurses through all dimensions and applies a unary operation in place - template <typename F> - void elementwise_in_place(F& op, int dim = 0, Offset_t dst_offset_base = 0) { - Offset_t dst_offset = dst_offset_base; - - for (int idx = 0; idx < size(dim); ++idx, dst_offset += stride(dim)) { - if (dim < Rank - 1) { - elementwise_in_place(op, dim + 1, dst_offset); - } else { - op(ref().data()[dst_offset]); - } - } - } - - /// Recurses through all dimensions and applies a unary operator with no arguments - template <typename F> - void elementwise_stream(F& op, int dim = 0, Offset_t dst_offset_base = 0) { - Offset_t dst_offset = dst_offset_base; - - for (int idx = 0; idx < size(dim); ++idx, dst_offset += stride(dim)) { - if (dim < Rank - 1) { - elementwise_stream(op, dim + 1, dst_offset); - } else { - ref().data()[dst_offset] = op(); - } - } - } - - /// Recurses through all dimensions and applies a unary operator, supplying the logical - /// coordinate within the tensor as an argument - template <typename F> - void elementwise_generate(F& op, - int dim = 0, - Offset_t dst_offset_base = 0, - Coord_t coord = Coord_t(0)) { - Offset_t dst_offset = dst_offset_base; - - for (int idx = 0; idx < size(dim); ++idx, dst_offset += stride(dim)) { - coord.at(dim) = idx; - - if (dim < Rank - 1) { - elementwise_generate(op, dim + 1, dst_offset, coord); - } else { - ref().data()[dst_offset] = op(coord); - } - } - } - - /// Recurses through all dimensions and applies a unary operator, supplying the logical - /// coordinate within the tensor as an argument - template <typename F> - void elementwise_visit(F& op, - int dim = 0, - Offset_t dst_offset_base = 0, - Coord_t coord = Coord_t(0)) const { - Offset_t dst_offset = dst_offset_base; - - for (int idx = 0; idx < size(dim); ++idx, dst_offset += stride(dim)) { - coord.at(dim) = idx; - - if (dim < Rank - 1) { - elementwise_visit(op, dim + 1, dst_offset, coord); - } else { - op(ref().data()[dst_offset], coord); - } - } - } - - /// Recurses through all dimensions and applies a binary operation - template <typename Src, typename F> - bool elementwise_in_place(F& op, - TensorView<Src> const& tensor, - int dim = 0, - Offset_t dst_offset_base = 0, - Offset_t src_offset_base = 0) { - Offset_t dst_offset = dst_offset_base; - Offset_t src_offset = src_offset_base; - - if (size().at(dim) != tensor.size().at(dim)) { - return false; - } - - for (int idx = 0; idx < size(dim); - ++idx, dst_offset += stride(dim), src_offset += tensor.stride(dim)) { - if (dim < Rank - 1) { - elementwise_in_place(op, tensor, dim + 1, dst_offset, src_offset); - } else { - op(data()[dst_offset], tensor.data()[src_offset]); - } - } - - return true; - } - - template <typename Src> - struct LambdaBinaryAddition { - void operator()(T& a, Src b) const { a += T(b); } - }; - - template <typename Src> - struct LambdaBinarySubtraction { - void operator()(T& a, Src b) const { a -= T(b); } - }; - - template <typename Src> - struct LambdaBinaryMultiplication { - void operator()(T& a, Src b) const { a *= T(b); } - }; - - template <typename Src> - struct LambdaBinaryDivision { - void operator()(T& a, Src b) const { a /= T(b); } - }; - - /// Accumulate in place - template <typename Src> - TensorView<T>& operator+=(TensorView<Src> const& tensor) { - LambdaBinaryAddition<Src> op; - elementwise_in_place(op, tensor); - - return *this; - } - - /// Subtract in place - template <typename Src> - TensorView<T>& operator-=(TensorView<Src> const& tensor) { - LambdaBinarySubtraction<Src> op; - elementwise_in_place(op, tensor); - - return *this; - } - - /// Multiply in place - template <typename Src> - TensorView<T>& operator*=(TensorView<Src> const& tensor) { - LambdaBinaryMultiplication<Src> op; - elementwise_in_place(op, tensor); - - return *this; - } - - /// Divide in place - template <typename Src> - TensorView<T>& operator/=(TensorView<Src> const& tensor) { - LambdaBinaryDivision<Src> op; - elementwise_in_place(op, tensor); - - return *this; - } - - /// Comparison operator - struct EqualsOperator { - bool equal; - T eps; - - EqualsOperator(T _epsilon) : equal(true), eps(_epsilon) {} - - void operator()(T a, T b) { - if (std::abs(T(a - b)) > eps * std::max(std::abs(a), std::abs(b))) { - equal = false; - } - } - }; - - /// equality with epsilon tolerance - bool equals(TensorView<T> const& tensor, T epsilon) const { - EqualsOperator comparison_op(epsilon); - bool equal_size = elementwise_in_place(comparison_op, tensor); - - return equal_size && comparison_op.equal; - } - - /// Compares two values which are smaller or equal to a long long int - struct BitEqualsOperator { - bool equal; - long long eps; - uint64_t index; - - BitEqualsOperator(long long _ulps_threshold) : equal(true), eps(_ulps_threshold), index(0) {} - - void operator()(T a, T b) { - // convert bits to integers - long long bits_a = 0; - long long bits_b = 0; - - *reinterpret_cast<T*>(&bits_a) = TypeTraits<T>::remove_negative_zero(a); - *reinterpret_cast<T*>(&bits_b) = TypeTraits<T>::remove_negative_zero(b); - - // compute diff - long long ulps = bits_a - bits_b; - if (std::abs(ulps) > eps) { - equal = false; - } - index++; - } - }; - - /// equality with ulps tolerance - bool bit_equals(TensorView<T> const& tensor, long long ulps_threshold = 0) { - BitEqualsOperator comparison_op(ulps_threshold); - bool equal_size = elementwise_in_place(comparison_op, tensor); - - return equal_size && comparison_op.equal; - } - - /// Gets naked pointer to data - T* data() const { return TensorView_t::data(); } - - /// Computes general matrix product among select dimensions of a tensor - /// Assumes: - /// D: number of independent GEMMs to compute - /// H: height of matrix - /// W: width of matrix - /// C: "channels" of each element - template <typename A, typename B, typename Ctype, typename Stype> - void gemm(TensorView<A> const& tensor_a, TensorView<B> const& tensor_b, Stype alpha, Stype beta) { - int const Batch = size(Dim_D); - int const M = size(Dim_H); - int const N = size(Dim_W); - int const K = tensor_a.size(Dim_W); - int const C = tensor_a.size(Dim_C); - - // Sizes must match - if (tensor_a.size(Dim_H) != M || tensor_b.size(Dim_W) != N || tensor_b.size(Dim_C) != C || - tensor_b.size(Dim_H) != K) { - return; - } - - int const Mblock = 32; - int const Nblock = 32; - - for (int batch = 0; batch < Batch; ++batch) { - for (int row_block = 0; row_block < M; row_block += Mblock) { - for (int col_block = 0; col_block < N; col_block += Nblock) { - Ctype accum[Mblock][Nblock]; - - for (int j = 0; j < Nblock; j++) { - for (int i = 0; i < Mblock; i++) { - accum[i][j] = Ctype(0); - } - } - - for (int k_block = 0; k_block < K; ++k_block) { - for (int j = 0; j < Nblock; j++) { - for (int i = 0; i < Mblock; i++) { - int row = row_block + i; - int col = col_block + j; - - if (row < M && col < N) { - for (int channel = 0; channel < C; ++channel) { - Ctype a(tensor_a.at(make_Coord(batch, row, k_block, channel))); - Ctype b(tensor_b.at(make_Coord(batch, k_block, col, channel))); - - accum[i][j] += a * b; - } - } - } - } - } - - for (int j = 0; j < Nblock; j++) { - for (int i = 0; i < Mblock; i++) { - int row = row_block + i; - int col = col_block + j; - - Coord_t coord = make_Coord(batch, row, col, 0); - if (row < M && col < N) { - at(coord) = - Cast<Stype, T>::apply(alpha * Stype(accum[i][j]) + beta * Stype(at(coord))); - } - } - } - } - } - } - } - - /// Fills with random data - template <typename Gen> - void fill_random(Gen generator) { - elementwise_stream(generator); - } - - /// Procedurally assigns elements - template <typename Gen> - void generate(Gen generator) { - elementwise_generate(generator); - } - - /// Procedurally visits elements - template <typename Gen> - void visit(Gen& generator) const { - elementwise_visit(generator); - } - - /// Generator to fill a tensor with the identity matrix - struct LambdaFillIdentity { - T operator()(Coord_t const& coord) { return (coord.at(1) == coord.at(2) ? T(1) : T(0)); } - }; - - /// initializes with identity - void fill_identity() { - LambdaFillIdentity op; - elementwise_generate(op); - } - - /// Lambda for fill_linear() - struct LambdaFillLinear { - Coord_t v_; - T offset_; - - LambdaFillLinear(Coord_t const& _v, T _offset) : v_(_v), offset_(_offset) {} - - T operator()(Coord_t const& coord) { return T(v_.template dot<int>(coord)) + offset_; } - }; - - /// computes elements as a linear combination of their coordinates - void fill_linear(Coord_t v, T offset = T(0)) { - LambdaFillLinear lambda(v, offset); - elementwise_generate(lambda); - } - - /// computes elements as a linear combination of their coordinates - void fill_sequential(T v = T(1), T offset = T(0)) { - int const count = size().count(); - for (int i = 0; i < count; ++i) { - data()[i] = T(i); - } - } - - /// Returns a constant value - struct LambdaFillValue { - T value; - - LambdaFillValue(T _value) : value(_value) {} - - T operator()() { return value; } - }; - - /// fills with a value - void fill(T val = T(0)) { - LambdaFillValue op(val); - elementwise_stream(op); - } - - /// Conversion from Src to T - template <typename Src> - struct LambdaAssign { - void operator()(T& a, Src b) const { a = T(b); } - }; - - /// copies from external data source and performs type conversion - template <typename Src> - void fill(TensorView<Src> const& tensor) { - LambdaAssign<Src> op; - elementwise_in_place(op, tensor); - } - - /// Computes a norm - struct LambdaNorm { - double sum; - - LambdaNorm() : sum(0) {} - - void operator()(T const& element) { - double value(element); - double conj(element); // TODO - conjugates for complex - - sum += value * conj; - } - }; - - /// Computes the norm of the matrix in double-precision - double norm() const { - LambdaNorm op; - elementwise_in_place(op); - - return std::sqrt(op.sum); - } -}; - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -} // namespace cutlass diff --git a/cutlass-example/launch.sh b/cutlass-example/launch.sh deleted file mode 100755 index e48f53e..0000000 --- a/cutlass-example/launch.sh +++ /dev/null @@ -1,134 +0,0 @@ -#!/bin/bash -make clean -make CFLAGS=-DWMMA_GEMM_16x16x16_NT -./myprog > LOG_WMMA_GEMM_16x16x16_NT -make clean -make CFLAGS=-DWMMA_GEMM_16x16x32_NT -./myprog > LOG_WMMA_GEMM_16x16x32_NT -make clean -make CFLAGS=-DWMMA_GEMM_16x16x16_NN -./myprog > LOG_WMMA_GEMM_16x16x16_NN -make clean -make CFLAGS=-DWMMA_GEMM_16x16x32_NN -./myprog > LOG_WMMA_GEMM_16x16x32_NN -make clean -make CFLAGS=-DWMMA_GEMM_16x16x16_TT -./myprog > LOG_WMMA_GEMM_16x16x16_TT -make clean -make CFLAGS=-DWMMA_GEMM_16x16x32_TT -./myprog > LOG_WMMA_GEMM_16x16x32_TT -make clean -make CFLAGS=-DWMMA_GEMM_16x16x16_TN -./myprog > LOG_WMMA_GEMM_16x16x16_TN -make clean -make CFLAGS=-DWMMA_GEMM_16x16x32_TN -./myprog > LOG_WMMA_GEMM_16x16x32_TN -make clean -make CFLAGS=-DWMMA_16x16x16_GEMM_256x256x128_NT -./myprog > LOG_WMMA_16x16x16_GEMM_256x256x128_NT -make clean -make CFLAGS=-DWMMA_16x16x16_GEMM_256x256x128_NN -./myprog > LOG_WMMA_16x16x16_GEMM_256x256x128_NN -make clean -make CFLAGS=-DWMMA_16x16x16_GEMM_256x256x128_TT -./myprog > LOG_WMMA_16x16x16_GEMM_256x256x128_TT -make clean -make CFLAGS=-DWMMA_16x16x16_GEMM_256x256x128_TN -./myprog > LOG_WMMA_16x16x16_GEMM_256x256x128_TN -make clean -make CFLAGS=-DWMMA_GEMM_256x256x256_NT -./myprog > LOG_WMMA_GEMM_256x256x256_NT -make clean -make CFLAGS=-DWMMA_GEMM_256x256x256_NN -./myprog > LOG_WMMA_GEMM_256x256x256_NN -make clean -make CFLAGS=-DWMMA_GEMM_256x256x256_TT -./myprog > LOG_WMMA_GEMM_256x256x256_TT -make clean -make CFLAGS=-DWMMA_GEMM_256x256x256_TN -./myprog > LOG_WMMA_GEMM_256x256x256_TN -make clean -make CFLAGS=-DWMMA_GEMM_512x512x512_NT -./myprog > LOG_WMMA_GEMM_512x512x512_NT -make clean -make CFLAGS=-DWMMA_GEMM_512x512x512_NN -./myprog > LOG_WMMA_GEMM_512x512x512_NN -make clean -make CFLAGS=-DWMMA_GEMM_512x512x512_TT -./myprog > LOG_WMMA_GEMM_512x512x512_TT -make clean -make CFLAGS=-DWMMA_GEMM_512x512x512_TN -./myprog > LOG_WMMA_GEMM_512x512x512_TN -make clean -make CFLAGS=-DWMMA_GEMM_1024x1024x1024_NT -./myprog > LOG_WMMA_GEMM_1024x1024x1024_NT -make clean -make CFLAGS=-DWMMA_GEMM_1024x1024x1024_NN -./myprog > LOG_WMMA_GEMM_1024x1024x1024_NN -make clean -make CFLAGS=-DWMMA_GEMM_1024x1024x1024_TT -./myprog > LOG_WMMA_GEMM_1024x1024x1024_TT -make clean -make CFLAGS=-DWMMA_GEMM_1024x1024x1024_TN -./myprog > LOG_WMMA_GEMM_1024x1024x1024_TN -make clean -make CFLAGS=-DWMMA_GEMM_2048x2048x2048_NT -./myprog > LOG_WMMA_GEMM_2048x2048x2048_NT -make clean -make CFLAGS=-DWMMA_GEMM_2048x2048x2048_NN -./myprog > LOG_WMMA_GEMM_2048x2048x2048_NN -make clean -make CFLAGS=-DWMMA_GEMM_2048x2048x2048_TT -./myprog > LOG_WMMA_GEMM_2048x2048x2048_TT -make clean -make CFLAGS=-DWMMA_GEMM_2048x2048x2048_TN -./myprog > LOG_WMMA_GEMM_2048x2048x2048_TN -make clean -make CFLAGS=-DWMMA_GEMM_4096x4096x4096_NT -./myprog > LOG_WMMA_GEMM_4096x4096x4096_NT -make clean -make CFLAGS=-DWMMA_GEMM_4096x4096x4096_NN -./myprog > LOG_WMMA_GEMM_4096x4096x4096_NN -make clean -make CFLAGS=-DWMMA_GEMM_4096x4096x4096_TT -./myprog > LOG_WMMA_GEMM_4096x4096x4096_TT -make clean -make CFLAGS=-DWMMA_GEMM_4096x4096x4096_TN -./myprog > LOG_WMMA_GEMM_4096x4096x4096_TN -make clean -make CFLAGS=-DWMMA_GEMM_32x32x32_NT -./myprog > LOG_WMMA_GEMM_32x32x32_NT -make clean -make CFLAGS=-DWMMA_GEMM_32x32x32_NN -./myprog > LOG_WMMA_GEMM_32x32x32_NN -make clean -make CFLAGS=-DWMMA_GEMM_32x32x32_TT -./myprog > LOG_WMMA_GEMM_32x32x32_TT -make clean -make CFLAGS=-DWMMA_GEMM_32x32x32_TN -./myprog > LOG_WMMA_GEMM_32x32x32_TN -make clean -make CFLAGS=-DWMMA_GEMM_128x128x128_NT -./myprog > LOG_WMMA_GEMM_128x128x128_NT -make clean -make CFLAGS=-DWMMA_GEMM_128x128x128_NN -./myprog > LOG_WMMA_GEMM_128x128x128_NN -make clean -make CFLAGS=-DWMMA_GEMM_128x128x128_TT -./myprog > LOG_WMMA_GEMM_128x128x128_TT -make clean -make CFLAGS=-DWMMA_GEMM_128x128x128_TN -./myprog > LOG_WMMA_GEMM_128x128x128_TN -make clean -make CFLAGS=-DWMMA_GEMM_768x768x768_NT -./myprog > LOG_WMMA_GEMM_768x768x768_NT -make clean -make CFLAGS=-DWMMA_GEMM_768x768x768_NN -./myprog > LOG_WMMA_GEMM_768x768x768_NN -make clean -make CFLAGS=-DWMMA_GEMM_768x768x768_TT -./myprog > LOG_WMMA_GEMM_768x768x768_TT -make clean -make CFLAGS=-DWMMA_GEMM_768x768x768_TN -./myprog > LOG_WMMA_GEMM_768x768x768_TN -make clean diff --git a/cutlass-example/tensor_view_io.h b/cutlass-example/tensor_view_io.h deleted file mode 100644 index bc2e9b1..0000000 --- a/cutlass-example/tensor_view_io.h +++ /dev/null @@ -1,61 +0,0 @@ -/*************************************************************************************************** -* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. -* -* Redistribution and use in source and binary forms, with or without modification, are permitted -* provided that the following conditions are met: -* * Redistributions of source code must retain the above copyright notice, this list of -* conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright notice, this list of -* conditions and the following disclaimer in the documentation and/or other materials -* provided with the distribution. -* * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used -* to endorse or promote products derived from this software without specific prior written -* permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND -* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE -* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -* STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -**************************************************************************************************/ -#pragma once - -#include <cutlass/core_io.h> -#include <cutlass/tensor_view.h> - -template <typename T> -inline std::ostream& tensor_view_output(std::ostream& out, T t) { - out << t; - return out; -} - -template <> -inline std::ostream& tensor_view_output<int8_t>(std::ostream& out, int8_t t) { - out << int(t); - return out; -} - -template <typename T> -inline std::ostream& operator<<(std::ostream& out, cutlass::TensorView<T> const& tensor) { - for (int batch = 0; batch < tensor.size(0); ++batch) { - out << "[\n "; - for (int h = 0; h < tensor.size(1); ++h) { - for (int w = 0; w < tensor.size(2); ++w) { - for (int c = 0; c < tensor.size(3); ++c) { - out << ((c | w) ? " " : ""); - tensor_view_output(out, tensor.at(cutlass::make_Coord(batch, h, w, c))); - } - } - if (h + 1 < tensor.size(1)) { - out << " ;\n "; - } - } - out << " ]"; - } - - return out; -} diff --git a/cutlass-example/type_traits.h b/cutlass-example/type_traits.h deleted file mode 100644 index eabd67e..0000000 --- a/cutlass-example/type_traits.h +++ /dev/null @@ -1,160 +0,0 @@ -/*************************************************************************************************** - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, are permitted - * provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, this list of - * conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **************************************************************************************************/ -/*! \file - \brief Type traits for common CUDA types -*/ - -#pragma once - -#include <cuda_fp16.h> -#include <stdint.h> - -#include "half.h" - -namespace cutlass { -struct half_t; - -template <typename T> -struct TypeTraits; - -template <> -struct TypeTraits<int8_t> { -// static cudaDataType_t const cublas_type = CUDA_R_8I; - typedef int8_t host_type; - typedef int8_t device_type; - typedef int8_t integer_type; - typedef uint8_t unsigned_type; - static inline int8_t remove_negative_zero(int8_t x) { return x; } - static inline int to_print(int8_t x) { return (int)x; } -}; - -template <> -struct TypeTraits<uint8_t> { -// static cudaDataType_t const cublas_type = CUDA_R_8I; - typedef uint8_t host_type; - typedef uint8_t device_type; - typedef uint8_t integer_type; - typedef uint8_t unsigned_type; - static inline uint8_t remove_negative_zero(uint8_t x) { return x; } - static inline uint32_t to_print(uint8_t x) { return (uint32_t)x; } -}; - -template <> -struct TypeTraits<int> { -// static cudaDataType_t const cublas_type = CUDA_R_32I; - typedef int host_type; - typedef int device_type; - typedef int32_t integer_type; - typedef uint32_t unsigned_type; - static inline int32_t remove_negative_zero(int32_t x) { return x; } - static inline int to_print(int x) { return x; } -}; - -template <> -struct TypeTraits<unsigned> { -// static cudaDataType_t const cublas_type = CUDA_R_32I; - typedef unsigned host_type; - typedef unsigned device_type; - typedef uint32_t integer_type; - typedef uint32_t unsigned_type; - static inline uint32_t remove_negative_zero(uint32_t x) { return x; } - static inline uint32_t to_print(uint32_t x) { return x; } -}; - -template <> -struct TypeTraits<half> { -// static cudaDataType_t const cublas_type = CUDA_R_16F; - typedef half_t host_type; - typedef half device_type; - typedef int16_t integer_type; - typedef uint16_t unsigned_type; - static inline half remove_negative_zero(half x) { - integer_type h_int = reinterpret_cast<integer_type const&>(x); - if (h_int == 0x8000) { - h_int = 0; - } - x = reinterpret_cast<half const&>(h_int); - return x; - } - static inline half to_print(half x) { return x; } -}; - -template <> -struct TypeTraits<int64_t> { -// static cudaDataType_t const cublas_type = CUDA_R_8I; - typedef int64_t host_type; - typedef int64_t device_type; - typedef int64_t integer_type; - typedef uint64_t unsigned_type; - static inline int64_t remove_negative_zero(int64_t x) { return x; } - static inline int64_t to_print(int64_t x) { return x; } -}; - -template <> -struct TypeTraits<uint64_t> { -// static cudaDataType_t const cublas_type = CUDA_R_8I; - typedef uint64_t host_type; - typedef uint64_t device_type; - typedef uint64_t integer_type; - typedef uint64_t unsigned_type; - static inline uint64_t remove_negative_zero(uint64_t x) { return x; } - static inline uint64_t to_print(uint64_t x) { return x; } -}; - -template <> -struct TypeTraits<cutlass::half_t> { -// static cudaDataType_t const cublas_type = CUDA_R_16F; - typedef half_t host_type; - typedef half device_type; - typedef int16_t integer_type; - typedef uint16_t unsigned_type; - static inline half_t remove_negative_zero(half_t x) { - return (x.raw() == 0x8000 ? half_t::bitcast(0) : x); - } - static inline half_t to_print(half_t x) { return x; } -}; - -template <> -struct TypeTraits<float> { -// static cudaDataType_t const cublas_type = CUDA_R_32F; - typedef float host_type; - typedef float device_type; - typedef int32_t integer_type; - typedef uint32_t unsigned_type; - static inline float remove_negative_zero(float x) { return x == -0.f ? 0.f : x; } - static inline float to_print(float x) { return x; } -}; - -template <> -struct TypeTraits<double> { -// static cudaDataType_t const cublas_type = CUDA_R_64F; - typedef double host_type; - typedef double device_type; - typedef int64_t integer_type; - typedef uint64_t unsigned_type; - static inline double remove_negative_zero(double x) { return x == -0.0 ? 0.0 : x; } - static inline double to_print(double x) { return x; } -}; -} // namespace cutlass diff --git a/diff.diff b/diff.diff new file mode 100644 index 0000000..8ab27fe --- /dev/null +++ b/diff.diff @@ -0,0 +1,173 @@ +diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc +index 5964a4d..53436d3 100644 +--- a/libcuda/cuda_runtime_api.cc ++++ b/libcuda/cuda_runtime_api.cc +@@ -182,6 +182,8 @@ cudaError_t g_last_cudaError = cudaSuccess; + + extern stream_manager *g_stream_manager; + ++ ++ + void register_ptx_function( const char *name, function_info *impl ) + { + // no longer need this +@@ -1341,6 +1343,29 @@ std::string get_app_binary(){ + return self_exe_path; + } + ++static int get_app_cuda_version() { ++ int app_cuda_version = 0; ++ char fname[1024]; ++ snprintf(fname,1024,"_app_cuda_version_XXXXXX"); ++ int fd=mkstemp(fname); ++ close(fd); ++ std::string app_cuda_version_command = "ldd " + get_app_binary() + " | grep libcudart.so | sed 's/.*libcudart.so.\\(.*\\) =>.*/\\1/' > " + fname; ++ system(app_cuda_version_command.c_str()); ++ FILE * cmd = fopen(fname, "r"); ++ char buf[256]; ++ while (fgets(buf, sizeof(buf), cmd) != 0) { ++ std::cout << buf; ++ app_cuda_version = atoi(buf); ++ } ++ fclose(cmd); ++ if ( app_cuda_version == 0 ) { ++ printf( "Error - Cannot detect the app's CUDA version.\n" ); ++ exit(1); ++ } ++ return app_cuda_version; ++} ++ ++ + //! Call cuobjdump to extract everything (-elf -sass -ptx) + /*! + * This Function extract the whole PTX (for all the files) using cuobjdump +@@ -1366,23 +1391,10 @@ void extract_code_using_cuobjdump(){ + // Running cuobjdump using dynamic link to current process + // Needs the option '-all' to extract PTX from CDP-enabled binary + extern bool g_cdp_enabled; +- const int current_cuda = atoi(getenv("CUDA_VERSION_NUMBER")); +- if ( context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() && current_cuda > 4020 ) { +- const char* cuda_42_path = getenv("CUDA_42_INSTALL_PATH"); +- if ( NULL == cuda_42_path ) { +- printf("You are using a new version of CUDA and PTXPLUS. You are required to have CUDA SDK 4.2 and explicitly " +- "point to it via the environment variable $CUDA_42_INSTALL_PATH.\n\n"); +- exit(1); +- } else { +- command = "$CUDA_42_INSTALL_PATH/bin/cuobjdump"; +- } +- } else { +- command = "$CUDA_42_INSTALL_PATH/bin/cuobjdump"; +- } + if(!g_cdp_enabled) +- command += " -ptx -elf -sass " + app_binary + " > " + fname; ++ command = "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass " + app_binary + " > " + fname; + else +- command += " -ptx -elf -sass -all " + app_binary + " > " + fname; ++ command = "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all " + app_binary + " > " + fname; + bool parse_output = true; + int result = system(command.c_str()); + if(result) { +@@ -1765,6 +1777,7 @@ void cuobjdumpParseBinary(unsigned int handle){ + //TODO: Remove temporarily files as per configurations + } + ++ + void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) + { + #if (CUDART_VERSION < 2010) +@@ -1783,26 +1796,10 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) + // Making this a runtime variable based on the app, enables GPGPU-Sim compiled + // with a newer version of CUDA to run apps compiled with older versions of + // CUDA. This is especially useful for PTXPLUS execution. +- char fname[1024]; +- snprintf(fname,1024,"_app_cuda_version_XXXXXX"); +- int fd=mkstemp(fname); +- close(fd); +- int app_cuda_version = 0; +- std::string app_cuda_version_command = "ldd " + get_app_binary() + " | grep libcudart.so | sed 's/.*libcudart.so.\\(.*\\) =>.*/\\1/' > " + fname; +- system(app_cuda_version_command.c_str()); +- FILE * cmd = fopen(fname, "r"); +- char buf[256]; +- while (fgets(buf, sizeof(buf), cmd) != 0) { +- std::cout << buf; +- app_cuda_version = atoi(buf); +- } +- fclose(cmd); +- if ( app_cuda_version == 0 ) { +- printf( "Error - Cannot detect the app's CUDA version.\n" ); +- exit(1); +- } ++ int app_cuda_version = get_app_cuda_version(); ++ assert( app_cuda_version == CUDART_VERSION / 1000 && "The app must be compiled with same major version as the simulator." ); + const char* filename; +- if ( app_cuda_version < 6 ) { ++#if CUDART_VERSION < 6000 + // FatBin handle from the .fatbin.c file (one of the intermediate files generated by NVCC) + typedef struct {int m; int v; const unsigned long long* d; char* f;} __fatDeviceText __attribute__ ((aligned (8))); + __fatDeviceText * fatDeviceText = (__fatDeviceText *) fatCubin; +@@ -1814,9 +1811,9 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) + char * pfatbin = (char*) fatDeviceText->d; + int offset = *((int*)(pfatbin+48)); + filename = (pfatbin+16+offset); +- } else { ++#else + filename = "default"; +- } ++#endif + + // The extracted file name is associated with a fat_cubin_handle passed + // into cudaLaunch(). Inside cudaLaunch(), the associated file name is +diff --git a/setup_environment b/setup_environment +index 8bcb9aa..e5cd4fa 100644 +--- a/setup_environment ++++ b/setup_environment +@@ -134,18 +134,26 @@ else + echo "configured without a power model."; + fi + ++export PTXAS_CUDA_INSTALL_PATH=$CUDA_INSTALL_PATH ++echo ""; ++echo "----------------------------------------------------------------------------"; ++echo "WARNING - If you only care about PTX execution, ignore this warning. GPGPU-Sim supports PTX execution in modern CUDA." + if [ $CUDA_VERSION_NUMBER -gt 4200 ]; then +- echo ""; +- echo "----------------------------------------------------------------------------"; +- echo "WARNING - If you only care about PTX execution, ignore this warning. GPGPU-Sim supports PTX execution in modern CUDA." +- echo "If you want to run PTXPLUS, download SDK 4.2 (in addition to your modern CUDA) and set \$CUDA_42_INSTALL_PATH." +- echo "The following text describes why:"; +- echo "If you are using PTXPLUS, only sm_1x is supported and it requires that the app binaries are compiled in CUDA 4.2 or less."; +- echo "New versions of CUDA tools have dropped parsing support for sm_1x - therefore to use PTXPLUS with a modern card configuration, you must"; +- echo "have both CUDA 4.2 and a modern CUDA installed. When running PTXPLUS under a CUDA version >= 4.2, the simulator will fail unless \$CUDA_42_INSTALL_PATH"; +- echo "has been set properly. You must set this manually."; +- echo "----------------------------------------------------------------------------" ++ echo "If you want to run PTXPLUS (sm_1x SASS) with a modern card configuration, the apps and simulator must be compiled with CUDA 4.2." ++ echo "You can still run a PASCAL configuration when compiling with 4.2 by setting the \$PTXAS_CUDA_INSTALL_PATH directory environment variable." ++else ++ echo "If you want to run PTXPLUS (sm_1x SASS) with a modern card configuration - set the envronment variable" ++ echo "\$PTXAS_CUDA_INSTALL_PATH to point a CUDA version compabible with your card configurations (i.e. 8+ for PASCAL, 9+ for VOLTA etc..)" ++ echo "For example: \"export \$PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-9.1\"" + fi ++echo "The following text describes why:"; ++echo "If you are using PTXPLUS, only sm_1x is supported and it requires that the app and simulator binaries are compiled in CUDA 4.2 or less."; ++echo "The simulator requires it since CUDA headers desribe struct sizes in the exec which change from gen to gen."; ++echo "The apps require 4.2 because new versions of CUDA tools have dropped parsing support for generating sm_1x"; ++echo "When running using modern config (i.e. pascal) and PTXPLUS with CUDA 4.2, the \$PTXAS_CUDA_INSTALL_PATH env variable is required to get proper register usage" ++echo "(and hence occupancy) using a version of CUDA that knows the register usage on the real card." ++echo ""; ++echo "----------------------------------------------------------------------------"; + + echo "setup_environment succeeded"; + +diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc +index 22f03b9..d8e04d4 100644 +--- a/src/cuda-sim/ptx_loader.cc ++++ b/src/cuda-sim/ptx_loader.cc +@@ -339,7 +339,7 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num + snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",g_occupancy_sm_number); + #endif + +- snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", ++ snprintf(commandline,1024,"$PTXAS_CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", + extra_flags, fname2, tempfile_ptxinfo); + printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); + result = system(commandline); diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index aa43ffa..a79e740 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -182,6 +182,8 @@ cudaError_t g_last_cudaError = cudaSuccess; extern stream_manager *g_stream_manager; + + void register_ptx_function( const char *name, function_info *impl ) { // no longer need this @@ -324,7 +326,7 @@ private: gpgpu_ptx_sim_arg_list_t m_args; }; -class _cuda_device_id *GPGPUSim_Init() +struct _cuda_device_id *GPGPUSim_Init() { static _cuda_device_id *the_device = NULL; if( !the_device ) { @@ -952,9 +954,6 @@ __host__ cudaError_t CUDARTAPI cudaSetupArgument(const void *arg, size_t size, s gpgpusim_ptx_assert( !g_cuda_launch_stack.empty(), "empty launch stack" ); kernel_config &config = g_cuda_launch_stack.back(); config.set_arg(arg,size,offset); - #if 0 - printf("cudaSetupArgument:size%d,offset%d,sizeof(Arg[0])=%d)\n ",size,offset,sizeof(arg)); - #endif return g_last_cudaError = cudaSuccess; } @@ -988,14 +987,9 @@ __host__ cudaError_t CUDARTAPI cudaLaunchKernel ( const char* hostFun, dim3 grid g_cuda_launch_stack.push_back( kernel_config(gridDim,blockDim,sharedMem,s) ); - printf("cudaLaunchKernel:sizeof(Arg[0])=%d)\n ",sizeof(args[0])); - //gpgpusim_ptx_assert( !g_cuda_launch_stack.empty(), "empty launch stack" ); + //printf("cudaLaunchKernel:sizeof(Arg[0])=%d)\n ",sizeof(args[0])); kernel_config &config = g_cuda_launch_stack.back(); - config.set_arg(args[0],432,0); - printf("cudaLaunchParameter\n"); - for(int i=0;i<108;i++){ - printf("cudaLaunchParameter:%d:%08x\n",i,*(*((int **)args)+i)); - } + config.set_arg(args[0],432,0);//standard interface for cutlass library #TODO Implementing a generalized kernel CUctx_st* context = GPGPUSim_Context(); char *mode = getenv("PTX_SIM_MODE_FUNC"); @@ -1381,6 +1375,29 @@ std::string get_app_binary(){ return self_exe_path; } +static int get_app_cuda_version() { + int app_cuda_version = 0; + char fname[1024]; + snprintf(fname,1024,"_app_cuda_version_XXXXXX"); + int fd=mkstemp(fname); + close(fd); + std::string app_cuda_version_command = "ldd " + get_app_binary() + " | grep libcudart.so | sed 's/.*libcudart.so.\\(.*\\) =>.*/\\1/' > " + fname; + system(app_cuda_version_command.c_str()); + FILE * cmd = fopen(fname, "r"); + char buf[256]; + while (fgets(buf, sizeof(buf), cmd) != 0) { + std::cout << buf; + app_cuda_version = atoi(buf); + } + fclose(cmd); + if ( app_cuda_version == 0 ) { + printf( "Error - Cannot detect the app's CUDA version.\n" ); + exit(1); + } + return app_cuda_version; +} + + //! Call cuobjdump to extract everything (-elf -sass -ptx) /*! * This Function extract the whole PTX (for all the files) using cuobjdump @@ -1390,39 +1407,39 @@ std::string get_app_binary(){ * enabled * */ void extract_code_using_cuobjdump(){ - CUctx_st *context = GPGPUSim_Context(); - char command[1000]; + CUctx_st *context = GPGPUSim_Context(); + std::string command; - std::string app_binary = get_app_binary(); + std::string app_binary = get_app_binary(); char fname[1024]; snprintf(fname,1024,"_cuobjdump_complete_output_XXXXXX"); int fd=mkstemp(fname); close(fd); // Running cuobjdump using dynamic link to current process - snprintf(command,1000,"md5sum %s ", app_binary.c_str()); - printf("Running md5sum using \"%s\"\n", command); - system(command); + command = "md5sum " + app_binary; + printf("Running md5sum using \"%s\"\n", command.c_str()); + system(command.c_str()); // Running cuobjdump using dynamic link to current process // Needs the option '-all' to extract PTX from CDP-enabled binary extern bool g_cdp_enabled; if(!g_cdp_enabled) - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass %s > %s", app_binary.c_str(), fname); + command = "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass " + app_binary + " > " + fname; else - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); + command = "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all " + app_binary + " > " + fname; bool parse_output = true; - int result = system(command); + int result = system(command.c_str()); if(result) { if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support() && (result == 65280)) { // Some CUDA application may exclusively use kernels provided by CUDA // libraries (e.g. CUBLAS). Skipping cuobjdump extraction from the // executable for this case. // 65280 is the return code from cuobjdump denoting the specific error (tested on CUDA 4.0/4.1/4.2) - printf("WARNING: Failed to execute: %s\n", command); + printf("WARNING: Failed to execute: %s\n", command.c_str()); printf(" Executable binary does not contain any GPU kernel.\n"); parse_output = false; } else { - printf("ERROR: Failed to execute: %s\n", command); + printf("ERROR: Failed to execute: %s\n", command.c_str()); exit(1); } } @@ -1446,7 +1463,7 @@ void extract_code_using_cuobjdump(){ cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; int result = system(cmd.str().c_str()); if(result){ - std::cout << "Failed to execute: " << cmd << std::endl; + std::cout << "Failed to execute: " << cmd.str() << std::endl; exit(1); } std::ifstream libsf; @@ -1475,10 +1492,10 @@ void extract_code_using_cuobjdump(){ std::cout << "Running cuobjdump on " << line << std::endl; std::cout << "Using command: " << cmd.str() << std::endl; result = system(cmd.str().c_str()); - if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} + if(result) {printf("ERROR: Failed to execute: %s\n", command.c_str()); exit(1);} std::cout << "Done" << std::endl; - std::cout << "Trying to parse " << libcodfn << std::endl; + std::cout << "Trying to parse " << libcodfn.str() << std::endl; cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); cuobjdump_parse(); fclose(cuobjdump_in); @@ -1580,7 +1597,7 @@ std::list<cuobjdumpSection*> pruneSectionList(std::list<cuobjdumpSection*> cuobj //! Merge all PTX sections that have a specific identifier into one file std::list<cuobjdumpSection*> mergeMatchingSections(std::list<cuobjdumpSection*> cuobjdumpSectionList, std::string identifier){ - char *ptxcode = ""; + const char *ptxcode = ""; std::list<cuobjdumpSection*>::iterator old_iter; cuobjdumpPTXSection* old_ptxsection = NULL; cuobjdumpPTXSection* ptxsection; @@ -1729,68 +1746,70 @@ std::map<int, bool>fatbin_registered; std::map<std::string, symbol_table*> name_symtab; //! Keep track of the association between filename and cubin handle -void cuobjdumpRegisterFatBinary(unsigned int handle, char* filename){ +void cuobjdumpRegisterFatBinary(unsigned int handle, const char* filename){ fatbinmap[handle] = filename; } //! Either submit PTX for simulation or convert SASS to PTXPlus and submit it void cuobjdumpParseBinary(unsigned int handle){ - if(fatbin_registered[handle]) return; - fatbin_registered[handle] = true; - CUctx_st *context = GPGPUSim_Context(); - std::string fname = fatbinmap[handle]; + if(fatbin_registered[handle]) return; + fatbin_registered[handle] = true; + CUctx_st *context = GPGPUSim_Context(); + std::string fname = fatbinmap[handle]; - if (name_symtab.find(fname) != name_symtab.end()) { - symbol_table *symtab = name_symtab[fname]; - context->add_binary(symtab, handle); - return; - } + if (name_symtab.find(fname) != name_symtab.end()) { + symbol_table *symtab = name_symtab[fname]; + context->add_binary(symtab, handle); + return; + } - unsigned max_capability = 0; - for ( std::list<cuobjdumpSection*>::iterator iter = cuobjdumpSectionList.begin(); - iter != cuobjdumpSectionList.end(); - iter++){ - unsigned capability = (*iter)->getArch(); - if (capability > max_capability) max_capability = capability; - } - if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); + unsigned max_capability = 0; + for ( std::list<cuobjdumpSection*>::iterator iter = cuobjdumpSectionList.begin(); + iter != cuobjdumpSectionList.end(); + iter++ ){ + unsigned capability = (*iter)->getArch(); + if (capability > max_capability) max_capability = capability; + } + printf("Using PTX version = %u\n", max_capability); + if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); - cuobjdumpPTXSection* ptx = findPTXSection(fname); - symbol_table *symtab; - char *ptxcode; - const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); - if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL) { - ptxcode = readfile(ptx->getPTXfilename()); - } else { - printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); - ptxcode = readfile(override_ptx_name); - } - if(context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() ) { - cuobjdumpELFSection* elfsection = findELFSection(ptx->getIdentifier()); - assert (elfsection!= NULL); - char *ptxplus_str = gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus( - ptx->getPTXfilename(), - elfsection->getELFfilename(), - elfsection->getSASSfilename()); - symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxplus_str, handle); - printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); - context->add_binary(symtab, handle); - gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability ); - delete[] ptxplus_str; - } else { - symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxcode, handle); - printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); - context->add_binary(symtab, handle); - gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability ); - } - load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu()); - load_constants(symtab,STATIC_ALLOC_LIMIT,context->get_device()->get_gpgpu()); - name_symtab[fname] = symtab; + cuobjdumpPTXSection* ptx = findPTXSection(fname); + symbol_table *symtab; + char *ptxcode; + const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); + if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL) { + ptxcode = readfile(ptx->getPTXfilename()); + } else { + printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); + ptxcode = readfile(override_ptx_name); + } + if(context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() ) { + cuobjdumpELFSection* elfsection = findELFSection(ptx->getIdentifier()); + assert (elfsection!= NULL); + char *ptxplus_str = gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus( + ptx->getPTXfilename(), + elfsection->getELFfilename(), + elfsection->getSASSfilename()); + symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxplus_str, handle); + printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); + context->add_binary(symtab, handle); + gpgpu_ptxinfo_load_from_string( ptxcode, handle ); + delete[] ptxplus_str; + } else { + symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxcode, handle); + printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); + context->add_binary(symtab, handle); + gpgpu_ptxinfo_load_from_string( ptxcode, handle ); + } + load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu()); + load_constants(symtab,STATIC_ALLOC_LIMIT,context->get_device()->get_gpgpu()); + name_symtab[fname] = symtab; - //TODO: Remove temporarily files as per configurations + //TODO: Remove temporarily files as per configurations } + void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) { #if (CUDART_VERSION < 2010) @@ -1804,21 +1823,30 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) if (sizeof(void*) == 4) printf("GPGPU-Sim PTX: FatBin file name extraction has not been tested on 32-bit system.\n"); - // FatBin handle from the .fatbin.c file (one of the intermediate files generated by NVCC) - typedef struct {int m; int v; const unsigned long long* d; char* f;} __fatDeviceText __attribute__ ((aligned (8))); - __fatDeviceText * fatDeviceText = (__fatDeviceText *) fatCubin; + // This code will get the CUDA version the app was compiled with. + // We need this to determine how to handle the parsing of the binary. + // Making this a runtime variable based on the app, enables GPGPU-Sim compiled + // with a newer version of CUDA to run apps compiled with older versions of + // CUDA. This is especially useful for PTXPLUS execution. + int app_cuda_version = get_app_cuda_version(); + assert( app_cuda_version == CUDART_VERSION / 1000 && "The app must be compiled with same major version as the simulator." ); + const char* filename; +#if CUDART_VERSION < 6000 + // FatBin handle from the .fatbin.c file (one of the intermediate files generated by NVCC) + typedef struct {int m; int v; const unsigned long long* d; char* f;} __fatDeviceText __attribute__ ((aligned (8))); + __fatDeviceText * fatDeviceText = (__fatDeviceText *) fatCubin; + + // Extract the source code file name that generate the given FatBin. + // - Obtains the pointer to the actual fatbin structure from the FatBin handle (fatCubin). + // - An integer inside the fatbin structure contains the relative offset to the source code file name. + // - This offset differs among different CUDA and GCC versions. + char * pfatbin = (char*) fatDeviceText->d; + int offset = *((int*)(pfatbin+48)); + filename = (pfatbin+16+offset); +#else + filename = "default"; +#endif - // Extract the source code file name that generate the given FatBin. - // - Obtains the pointer to the actual fatbin structure from the FatBin handle (fatCubin). - // - An integer inside the fatbin structure contains the relative offset to the source code file name. - // - This offset differs among different CUDA and GCC versions. - #if (CUDART_VERSION <= 6000) - char * pfatbin = (char*) fatDeviceText->d; - int offset = *((int*)(pfatbin+48)); - char * filename = (pfatbin+16+offset); - #else - char * filename = "default"; - #endif // The extracted file name is associated with a fat_cubin_handle passed // into cudaLaunch(). Inside cudaLaunch(), the associated file name is // used to find the PTX/SASS section from cuobjdump, which contains the @@ -1838,7 +1866,7 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) return (void**)fat_cubin_handle; } - #if (CUDART_VERSION < 8000) +#if (CUDART_VERSION < 8000) else { static unsigned source_num=1; unsigned long long fat_cubin_handle = next_fat_bin_handle++; @@ -1886,7 +1914,7 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) } else { symtab=gpgpu_ptx_sim_load_ptx_from_string(ptx,source_num); context->add_binary(symtab,fat_cubin_handle); - gpgpu_ptxinfo_load_from_string( ptx, source_num, max_capability ); + gpgpu_ptxinfo_load_from_string( ptx, source_num ); } source_num++; load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu()); @@ -1896,7 +1924,12 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) } return (void**)fat_cubin_handle; } - #endif +#else + else { + printf("ERROR ** __cudaRegisterFatBinary() needs to be updated\n"); + abort(); + } +#endif } void __cudaUnregisterFatBinary(void **fatCubinHandle) diff --git a/libcuda/cuobjdump.l b/libcuda/cuobjdump.l index f63ee73..2b0dac8 100644 --- a/libcuda/cuobjdump.l +++ b/libcuda/cuobjdump.l @@ -143,7 +143,6 @@ newlines {newline}+ /* Looking for the identifier (filename) then the header is done */ - /* <endheader>[[:alnum:]_\./]+ yylval.string_value = strdup(yytext); yy_pop_state(); return FILENAME; */ <endheader>{notnewline}+ yylval.string_value = strdup(yytext); yy_pop_state(); return IDENTIFIER; @@ -159,8 +158,6 @@ newlines {newline}+ %% void cuobjdump_error(const char* message) { - printf(" "); printf(message); printf(" near \""); printf(yytext); printf("\""); - printf(" on line "); - char line[5]; sprintf(line, "%i", yylineno); printf(line); - printf("\n"); + printf(" %s near \"%s\"",message, yytext); + printf(" on line %i\n",yylineno); } diff --git a/libopencl/opencl_runtime_api.cc b/libopencl/opencl_runtime_api.cc index 63f7c81..97a54d8 100644 --- a/libopencl/opencl_runtime_api.cc +++ b/libopencl/opencl_runtime_api.cc @@ -577,7 +577,7 @@ void _cl_program::Build(const char *options) } info.m_asm = tmp; info.m_symtab = gpgpu_ptx_sim_load_ptx_from_string( tmp, source_num ); - gpgpu_ptxinfo_load_from_string( tmp, source_num); + gpgpu_ptxinfo_load_from_string( tmp, source_num ); free(tmp); } printf("GPGPU-Sim OpenCL API: finished compiling OpenCL kernels.\n"); diff --git a/linux-so-version.txt b/linux-so-version.txt new file mode 100644 index 0000000..40f775d --- /dev/null +++ b/linux-so-version.txt @@ -0,0 +1,2 @@ +libcudart.so.9.1{ +}; diff --git a/setup_environment b/setup_environment index 0b0a6ff..f1af978 100644 --- a/setup_environment +++ b/setup_environment @@ -6,7 +6,15 @@ export GPGPUSIM_SETUP_ENVIRONMENT_WAS_RUN= export GPGPUSIM_ROOT="$( cd "$( dirname "$BASH_SOURCE" )" && pwd )" GPGPUSIM_VERSION_STRING=`cat $GPGPUSIM_ROOT/version | awk '/Version/ {print $8}'` -GPGPUSIM_BUILD_STRING=`cat $GPGPUSIM_ROOT/version | awk '/Change/ {print $6}'` +#Detect Git branch and commit # +CURRENT_PWD=`pwd` +cd $GPGPUSIM_ROOT +GIT_COMMIT=`git log -n 1 | head -1 | sed -re 's/commit (.*)/\1/'` +GIT_FILES_CHANGED=`git diff --numstat | wc | sed -re 's/^\s+([0-9]+).*/\1./'` +GIT_FILES_CHANGED+=`git diff --numstat --cached | wc | sed -re 's/^\s+([0-9]+).*/\1/'` +GPGPUSIM_BUILD_STRING="gpgpu-sim_git-commit-$GIT_COMMIT-modified_$GIT_FILES_CHANGED" +cd $CURRENT_PWD + echo -n "GPGPU-Sim version $GPGPUSIM_VERSION_STRING (build $GPGPUSIM_BUILD_STRING) "; if [ ! -n "$CUDA_INSTALL_PATH" ]; then @@ -42,14 +50,14 @@ fi CC_VERSION=`gcc --version | head -1 | awk '{for(i=1;i<=NF;i++){ if(match($i,/^[0-9]\.[0-9]\.[0-9]$/)) {print $i; exit 0}}}'` CUDA_VERSION_STRING=`$CUDA_INSTALL_PATH/bin/nvcc --version | awk '/release/ {print $5;}' | sed 's/,//'`; -CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("%02u%02u", 10*int($1), 10*$2);}'` -if [ $CUDA_VERSION_NUMBER -gt 9000 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then +export CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("%02u%02u", 10*int($1), 10*$2);}'` +if [ $CUDA_VERSION_NUMBER -gt 9100 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then echo "ERROR ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; return -elif [ $CUDA_VERSION_NUMBER -gt 4020 ]; then - echo "WARNING ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not fully tested with CUDA version $CUDA_VERSION_STRING (please see README)"; fi + + if [ $# = '1' ] ; then export GPGPUSIM_CONFIG=gcc-$CC_VERSION/cuda-$CUDA_VERSION_NUMBER/$1 @@ -129,6 +137,29 @@ else echo "configured without a power model."; fi +if [ -z "$PTXAS_CUDA_INSTALL_PATH" ]; then + export PTXAS_CUDA_INSTALL_PATH=$CUDA_INSTALL_PATH; +fi +echo ""; +echo "----------------------------------------------------------------------------"; +echo "INFO - If you only care about PTX execution, ignore this message. GPGPU-Sim supports PTX execution in modern CUDA." +if [ $CUDA_VERSION_NUMBER -gt 4200 ]; then + echo "If you want to run PTXPLUS (sm_1x SASS) with a modern card configuration, the apps and simulator must be compiled with CUDA 4.2." + echo "You can still run a PASCAL configuration when compiling with 4.2 by setting the \$PTXAS_CUDA_INSTALL_PATH directory environment variable." +else + echo "If you want to run PTXPLUS (sm_1x SASS) with a modern card configuration - set the envronment variable" + echo "\$PTXAS_CUDA_INSTALL_PATH to point a CUDA version compabible with your card configurations (i.e. 8+ for PASCAL, 9+ for VOLTA etc..)" + echo "For example: \"export \$PTXAS_CUDA_INSTALL_PATH=/usr/local/cuda-9.1\"" +fi +echo "The following text describes why:"; +echo "If you are using PTXPLUS, only sm_1x is supported and it requires that the app and simulator binaries are compiled in CUDA 4.2 or less."; +echo "The simulator requires it since CUDA headers desribe struct sizes in the exec which change from gen to gen."; +echo "The apps require 4.2 because new versions of CUDA tools have dropped parsing support for generating sm_1x"; +echo "When running using modern config (i.e. pascal) and PTXPLUS with CUDA 4.2, the \$PTXAS_CUDA_INSTALL_PATH env variable is required to get proper register usage" +echo "(and hence occupancy) using a version of CUDA that knows the register usage on the real card." +echo ""; +echo "----------------------------------------------------------------------------"; + echo "setup_environment succeeded"; export GPGPUSIM_SETUP_ENVIRONMENT_WAS_RUN=1 diff --git a/src/Makefile b/src/Makefile index 09194f3..6001669 100644 --- a/src/Makefile +++ b/src/Makefile @@ -46,7 +46,7 @@ ifeq ($(TRACE),1) endif ifneq ($(DEBUG),1) - OPTFLAGS += -O0 + OPTFLAGS += -O3 else CXXFLAGS += endif diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index 72ece0b..f7f1016 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -184,7 +184,7 @@ void warp_inst_t::generate_mem_accesses() { if( empty() || op == MEMORY_BARRIER_OP || m_mem_accesses_created ) return; - if (!((op == LOAD_OP) || (op==TENSOR_CORE_LOAD_OP) || (op==VP_LOAD_OP) || (op == STORE_OP)||(op==TENSOR_CORE_STORE_OP)||(op==VP_STORE_OP))) + if (!((op == LOAD_OP) || (op==TENSOR_CORE_LOAD_OP) || (op == STORE_OP)||(op==TENSOR_CORE_STORE_OP))) return; if( m_warp_active_mask.count() == 0 ) return; // predicated off @@ -352,7 +352,6 @@ void warp_inst_t::generate_mem_accesses() ptx_file_line_stats_add_uncoalesced_gmem( pc, m_accessq.size() - starting_queue_size ); } m_mem_accesses_created=true; - print_m_accessq(); } void warp_inst_t::memory_coalescing_arch_13( bool is_write, mem_access_type access_type ) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index d628745..f561f34 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -78,13 +78,10 @@ enum uarch_op_t { ALU_OP=1, SFU_OP, TENSOR_CORE_OP, - VP_CORE_OP, ALU_SFU_OP, LOAD_OP, - VP_LOAD_OP, TENSOR_CORE_LOAD_OP, TENSOR_CORE_STORE_OP, - VP_STORE_OP, STORE_OP, BRANCH_OP, BARRIER_OP, @@ -140,7 +137,6 @@ enum operation_pipeline_t { SP__OP, SFU__OP, TENSOR_CORE__OP, - VP_CORE__OP, MEM__OP }; typedef enum operation_pipeline_t operation_pipeline; @@ -805,8 +801,8 @@ public: { fprintf(fp," [inst @ pc=0x%04x] ", pc ); } - bool is_load() const { return (op == LOAD_OP ||op==TENSOR_CORE_LOAD_OP||op==VP_LOAD_OP || memory_op == memory_load); } - bool is_store() const { return (op == STORE_OP ||op==TENSOR_CORE_STORE_OP||op==VP_STORE_OP || memory_op == memory_store); } + bool is_load() const { return (op == LOAD_OP ||op==TENSOR_CORE_LOAD_OP || memory_op == memory_load); } + bool is_store() const { return (op == STORE_OP ||op==TENSOR_CORE_STORE_OP || memory_op == memory_store); } unsigned get_num_operands() const {return num_operands;} unsigned get_num_regs() const {return num_regs;} void set_num_regs(unsigned num) {num_regs=num;} diff --git a/src/cuda-sim/.ptx.y.swp b/src/cuda-sim/.ptx.y.swp Binary files differdeleted file mode 100644 index c8a83b5..0000000 --- a/src/cuda-sim/.ptx.y.swp +++ /dev/null diff --git a/src/cuda-sim/Makefile b/src/cuda-sim/Makefile index d08a696..999dad7 100644 --- a/src/cuda-sim/Makefile +++ b/src/cuda-sim/Makefile @@ -42,7 +42,7 @@ include ../../version_detection.mk OUTPUT_DIR=$(SIM_OBJ_FILES_DIR)/cuda-sim -OPT := -O0 -g3 -Wall -Wno-unused-function -Wno-sign-compare +OPT := -O3 -g3 -Wall -Wno-unused-function -Wno-sign-compare ifeq ($(DEBUG),1) OPT := -g3 -Wall -Wno-unused-function -Wno-sign-compare endif @@ -62,7 +62,7 @@ ifeq ($(GNUC_CPP0X),1) endif endif -OBJS := $(OUTPUT_DIR)/ptx_parser.o $(OUTPUT_DIR)/ptx_loader.o $(OUTPUT_DIR)/cuda_device_printf.o $(OUTPUT_DIR)/instructions.o $(OUTPUT_DIR)/cuda-sim.o $(OUTPUT_DIR)/ptx_ir.o $(OUTPUT_DIR)/ptx_sim.o $(OUTPUT_DIR)/memory.o $(OUTPUT_DIR)/ptx-stats.o $(OUTPUT_DIR)/decuda_pred_table/decuda_pred_table.o $(OUTPUT_DIR)/ptx.tab.o $(OUTPUT_DIR)/lex.ptx_.o $(OUTPUT_DIR)/ptxinfo.tab.o $(OUTPUT_DIR)/lex.ptxinfo_.o $(OUTPUT_DIR)/cuda_device_runtime.o +OBJS := $(OUTPUT_DIR)/ptx_parser.o $(OUTPUT_DIR)/ptx_loader.o $(OUTPUT_DIR)/cuda_device_printf.o $(OUTPUT_DIR)/instructions.o $(OUTPUT_DIR)/cuda-sim.o $(OUTPUT_DIR)/ptx_ir.o $(OUTPUT_DIR)/ptx_sim.o $(OUTPUT_DIR)/memory.o $(OUTPUT_DIR)/ptx-stats.o $(OUTPUT_DIR)/decuda_pred_table/decuda_pred_table.o $(OUTPUT_DIR)/ptx.tab.o $(OUTPUT_DIR)/lex.ptx_.o $(OUTPUT_DIR)/ptxinfo.tab.o $(OUTPUT_DIR)/lex.ptxinfo_.o $(OUTPUT_DIR)/cuda_device_runtime.o OPT += -DCUDART_VERSION=$(CUDART_VERSION) diff --git a/src/cuda-sim/cuda-math.h b/src/cuda-sim/cuda-math.h index 314f813..a5db337 100644 --- a/src/cuda-sim/cuda-math.h +++ b/src/cuda-sim/cuda-math.h @@ -68,6 +68,8 @@ #ifndef CUDA_MATH #define CUDA_MATH +#include <cmath> + // cuda math implementations #undef max #undef min @@ -149,6 +151,7 @@ float __ll2float_rd(long long int a) { #include <device_types.h> #include <fenv.h> + // 32-bit integer to float float __int2float_rn(int a) { int orig_rnd_mode = fegetround(); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index dd7edd9..7587db7 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -542,7 +542,7 @@ void ptx_instruction::set_mul_div_or_other_archop(){ sp_op=INT_DIV_OP; break; default: - if((op==ALU_OP)||(op==VP_CORE_OP)) + if((op==ALU_OP)) sp_op=INT__OP; break; } @@ -649,11 +649,9 @@ void ptx_instruction::set_opcode_and_latency() break; case LD_OP: op = LOAD_OP; break; case MMA_LD_OP: op = TENSOR_CORE_LOAD_OP; break; - case VP_LD_OP: op = VP_LOAD_OP; break; case LDU_OP: op = LOAD_OP; break; case ST_OP: op = STORE_OP; break; case MMA_ST_OP: op = TENSOR_CORE_STORE_OP; break; - case VP_ST_OP: op = VP_STORE_OP; break; case BRA_OP: op = BRANCH_OP; break; case BREAKADDR_OP: op = BRANCH_OP; break; case TEX_OP: op = LOAD_OP; mem_op=TEX; break; @@ -801,26 +799,6 @@ void ptx_instruction::set_opcode_and_latency() initiation_interval = 64; op=TENSOR_CORE_OP; break; - case VP_MMA_OP: - if(get_wmma_type()==VP_MMA4) - { - latency = 64; - initiation_interval = 64; - } - if(get_wmma_type()==VP_MMA8) - { - latency =128; - initiation_interval = 128; - } - if(get_wmma_type()==VP_MMA16) - { - latency = 256; - initiation_interval = 256; - } - op=VP_CORE_OP; - op=VP_CORE_OP; - op=VP_CORE_OP; - break; case SHFL_OP: latency = 32; initiation_interval = 15; @@ -922,10 +900,10 @@ void ptx_instruction::pre_decode() case WT_OPTION: cache_op = CACHE_WRITE_THROUGH; break; default: //if( m_opcode == LD_OP || m_opcode == LDU_OP ) - if( m_opcode ==VP_LD_OP || m_opcode == MMA_LD_OP || m_opcode == LD_OP || m_opcode == LDU_OP ) + if( m_opcode == MMA_LD_OP || m_opcode == LD_OP || m_opcode == LDU_OP ) cache_op = CACHE_ALL; //else if( m_opcode == ST_OP ) - else if( m_opcode == VP_ST_OP ||m_opcode == MMA_ST_OP || m_opcode == ST_OP ) + else if( m_opcode == MMA_ST_OP || m_opcode == ST_OP ) cache_op = CACHE_WRITE_BACK; else if( m_opcode == ATOM_OP ) cache_op = CACHE_GLOBAL; @@ -1295,14 +1273,6 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) addr_t pc = next_instr(); assert( pc == inst.pc ); // make sure timing model and functional model are in sync const ptx_instruction *pI = m_func_info->get_instruction(pc); - //#if 0 - if(lane_id==0){ - //printf("EXECUTION_FLOW:LINE_NUM:%d\n",pI->source_line()); - printf("EXECUTION_FLOW:LINE_NUM:%d\n",pI->source_line()); - printf("EXECUTION_FLOW:INST:%s\n",pI->get_source()); - printf("EXECUTION_FLOW:PC%d\n",pc); - } - //#endif set_npc( pc + pI->inst_size() ); @@ -1349,12 +1319,12 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) pI = pJ; } - if(((inst_opcode==MMA_OP||inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_MMA_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP))){ + if(((inst_opcode==MMA_OP||inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP))){ if(inst.active_count()!=MAX_WARP_SIZE) while(1); } - if(((inst_opcode!=MMA_OP)&&(inst_opcode!=MMA_LD_OP)&&(inst_opcode!=MMA_ST_OP)&&(inst_opcode!=VP_LD_OP)&&(inst_opcode!=VP_ST_OP)&&(inst_opcode!=VP_MMA_OP))||((inst_opcode==MMA_OP||inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_MMA_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP)&&(lane_id==0))){ + if(((inst_opcode!=MMA_OP)&&(inst_opcode!=MMA_LD_OP)&&(inst_opcode!=MMA_ST_OP))||((inst_opcode==MMA_OP||inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP)&&(lane_id==0))){ switch ( inst_opcode ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; #define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; @@ -1405,8 +1375,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) _memory_op_t insn_memory_op = no_memory_op; unsigned insn_data_size = 0; if ( (pI->has_memory_read() || pI->has_memory_write()) ) { - if(!((inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP))) - //if(!((inst_opcode==MMA_LD_OP||inst_opcode==VP_LD_OP))) + if(!((inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP))) { insn_memaddr = last_eaddr(); insn_space = last_space(); @@ -1480,15 +1449,14 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) if ( (g_ptx_sim_num_insn % 100000) == 0 ) { dim3 ctaid = get_ctaid(); dim3 tid = get_tid(); - printf("GPGPU-Sim PTX: %u instructions simulated : ctaid=(%u,%u,%u) tid=(%u,%u,%u)\n", + DPRINTF(LIVENESS, "GPGPU-Sim PTX: %u instructions simulated : ctaid=(%u,%u,%u) tid=(%u,%u,%u)\n", g_ptx_sim_num_insn, ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z ); fflush(stdout); } // "Return values" if(!skip) { - if(!((inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP))) - //if(!((inst_opcode==MMA_LD_OP||inst_opcode==VP_LD_OP))) + if(!((inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP))) { inst.space = insn_space; inst.set_addr(lane_id, insn_memaddr); @@ -2150,7 +2118,7 @@ struct rec_pts { int s_num_recon; }; -struct std::map<function_info*,rec_pts> g_rpts; +class std::map<function_info*,rec_pts> g_rpts; struct rec_pts find_reconvergence_points( function_info *finfo ) { diff --git a/src/cuda-sim/half.hpp b/src/cuda-sim/half.h index 8f1a8eb..8f1a8eb 100644 --- a/src/cuda-sim/half.hpp +++ b/src/cuda-sim/half.h diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 52d89f2..2677c40 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -25,7 +25,7 @@ // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -#include "half.hpp" +#include "half.h" #include "instructions.h" #include "ptx_ir.h" #include "opcodes.h" @@ -48,7 +48,7 @@ using half_float::half; unsigned ptx_instruction::g_num_ptx_inst_uid=0; -bool g_debug_instruction = 1; +bool g_debug_instruction = 0; const char *g_opcode_string[NUM_OPCODES] = { @@ -129,15 +129,6 @@ unsigned thread_group_offset(int thread,unsigned wmma_type,unsigned wmma_layout } } break; - case VP_MMA: - case VP_MMA4: - case VP_MMA8: - case VP_MMA16: - if(wmma_layout==ROW) - offset=load_c_float_row[thread_group]+16*in_tg_index; - else - offset=load_c_float_col[thread_group]+in_tg_index; - break; default: abort(); @@ -1706,11 +1697,6 @@ void mapping(int thread,int wmma_type,int wmma_layout,int type,int index,int str } assg_offset=index; } - else if(wmma_type==VP_MMA || wmma_type==VP_MMA4 || wmma_type==VP_MMA8 || wmma_type==VP_MMA16){ - row=c_row_offset[thread/4]+thread%4; - col=c_col_offset[thread/4]+index; - assg_offset=index; - } if(wmma_type==LOAD_A||wmma_type==LOAD_B){ if(wmma_layout==ROW){ @@ -1724,152 +1710,6 @@ void mapping(int thread,int wmma_type,int wmma_layout,int type,int index,int str } } -void vp_mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) -{ - int i,j,k,thrd; - int row,col,offset; - ptx_reg_t matrix_a[16][16]; - ptx_reg_t matrix_b[16][16]; - ptx_reg_t matrix_c[16][16]; - ptx_reg_t matrix_d[16][16]; - ptx_reg_t src_data; - ptx_thread_info *thread; - int stride; - unsigned wmma_type = pI->get_wmma_type(); - unsigned a_layout = pI->get_wmma_layout(0); - unsigned b_layout = pI->get_wmma_layout(1); - unsigned type = pI->get_type(); - int tid = inst.warp_id_func() * core->get_warp_size(); - const operand_info &dst = pI->operand_lookup(0); - - unsigned thread_group_index; - - for (thrd=0; thrd < core->get_warp_size(); thrd++){ - thread = core->get_thread_info()[tid+thrd]; - if(g_debug_instruction) - printf("THREAD=%d\n:",thrd); - for(i=1;i<=3;i++){ - const operand_info &src_a= pI->operand_lookup(i); - unsigned nelem = src_a.get_vect_nelem(); - ptx_reg_t v[8]; - thread->get_vector_operand_values( src_a, v, nelem ); - if(g_debug_instruction){ - printf("Thread%d_Iteration=%d:",thrd,i); - for(k=0;k<nelem;k++){ - printf("%x ",v[k].u64); - } - printf("\n"); - } - int hex_val; - switch(i) { - case 1 ://operand 1 - for(k=0;k<8;k++){ - mapping(thrd,wmma_type,a_layout,S32_TYPE,k,16,row,col,offset); - if(g_debug_instruction) - printf("A:thread=%d,row=%d,col=%d,offset=%d\n",thrd,row,col,offset); - matrix_a[row][col]=v[offset]; - } - break; - case 2 ://operand 2 - for(k=0;k<8;k++){ - mapping(thrd,wmma_type,b_layout,S32_TYPE,k,16,row,col,offset); - if(g_debug_instruction) - printf("B:thread=%d,row=%d,col=%d,offset=%d\n",thrd,row,col,offset); - if(nelem==1){ - matrix_b[row][col].s32=((v[0].u32&(0xf<<4*k))>>4*k); - } - if(nelem==2){ - matrix_b[row][col].s32=((v[k/4].u32&(0xff<<8*(k%4)))>>8*(k%4)); - } - if(nelem==4){ - matrix_b[row][col].s32=((v[k/2].u32&(0xffff<<16*(k%2)))>>16*(k%2)); - } - } - break; - case 3 ://operand 3 - for(k=0;k<8;k++){ - mapping(thrd,wmma_type,ROW,S32_TYPE,k,16,row,col,offset); - if(g_debug_instruction) - printf("C:thread=%d,row=%d,col=%d,offset=%d\n",thrd,row,col,offset); - matrix_c[row][col]=v[offset]; - } - break; - default : - printf("Invalid Operand Index\n" ); - } - } - if(g_debug_instruction) - printf("\n"); - } - if(g_debug_instruction){ - printf("MATRIX_A\n"); - for (i=0;i<16;i++){ - for(j=0;j<16;j++){ - printf("%d ",matrix_a[i][j].s32); - } - printf("\n"); - } - } - printf("MATRIX_B\n"); - for (i=0;i<16;i++){ - for(j=0;j<16;j++){ - printf("%d ",matrix_b[i][j].s32); - } - printf("\n"); - } - printf("MATRIX_C\n"); - for (i=0;i<16;i++){ - for(j=0;j<16;j++){ - printf("%d ",matrix_c[i][j].s32); - } - printf("\n"); - } - for (i=0;i<16;i++){ - for(j=0;j<16;j++){ - matrix_d[i][j].f16=0; - } - } - - for (i=0;i<16;i++){ - for(j=0;j<16;j++){ - for(k=0;k<16;k++){ - matrix_d[i][j].s32=matrix_d[i][j].s32+matrix_a[i][k].s32*matrix_b[k][j].s32; - } - matrix_d[i][j].s32+=matrix_c[i][j].s32; - } - } - if(g_debug_instruction){ - printf("MATRIX_D\n"); - for (i=0;i<16;i++){ - for(j=0;j<16;j++){ - printf("%d ",matrix_d[i][j].s32); - } - printf("\n"); - } - } - for (thrd=0; thrd < core->get_warp_size(); thrd++){ - int row_t[8]; - int col_t[8]; - for(k=0;k<8;k++){ - mapping(thrd,wmma_type,ROW,type,k,16,row_t[k],col_t[k],offset); - if(g_debug_instruction) - printf("vp_mma:row:%d,col%d\n",row_t[k],col_t[k]); - } - thread = core->get_thread_info()[tid+thrd]; - - - thread->set_wmma_vector_operand_values(dst,matrix_d[row_t[0]][col_t[0]],matrix_d[row_t[1]][col_t[1]],matrix_d[row_t[2]][col_t[2]],matrix_d[row_t[3]][col_t[3]],matrix_d[row_t[4]][col_t[4]],matrix_d[row_t[5]][col_t[5]],matrix_d[row_t[6]][col_t[6]],matrix_d[row_t[7]][col_t[7]]); - - if(g_debug_instruction) - { - printf("thread%d:",thrd); - for(k=0;k<8;k++){ - printf("%d ",matrix_d[row_t[k]][col_t[k]].s32); - } - printf("\n"); - } - } -} void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { int i,j,k,thrd; @@ -2387,18 +2227,10 @@ ptx_reg_t f2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, } else { switch ( to_width ) { case 16: - mytemp=half(x.f32); - myfloat=mytemp; - y.f16 =mytemp; - #if 0 - printf("f2x: %f\n",myfloat); - #endif + y.f16 =half_float::half_cast<half,std::numeric_limits<float>::round_style>(x.f32);//mytemp; break; case 32: y.f32=float(x.f16); - #if 0 - printf("f2xnew:%x:my%f:%f\n",x.f16,y.f32,half_float::detail::half2float<float>(x.u16)); - #endif break; // handled by f2f case 64: y.f64 = x.f32; @@ -3119,78 +2951,6 @@ void ldu_impl( const ptx_instruction *pI, ptx_thread_info *thread ) ld_exec(pI,thread); } -void vp_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t & inst) -{ - size_t size; - unsigned smid; - int t; - int thrd,odd,inx,k; - ptx_thread_info *thread; - - const operand_info &src = pI->operand_lookup(1); - const operand_info &src1 = pI->operand_lookup(0); - const operand_info &src2 = pI->operand_lookup(2); - int tid = inst.warp_id_func()*core->get_warp_size(); - unsigned type = pI->get_type(); - unsigned wmma_type = pI->get_wmma_type(); - unsigned wmma_layout = pI->get_wmma_layout(0); - int stride; - _memory_op_t insn_memory_op = pI->has_memory_read() ? memory_load : memory_store; - for (thrd=0; thrd < core->get_warp_size(); thrd++) { - thread = core->get_thread_info()[tid+thrd]; - odd=thrd%2; - inx=thrd/2; - ptx_reg_t addr_reg = thread->get_operand_value(src1, src, type, thread, 1); - ptx_reg_t src2_data = thread->get_operand_value(src2, src, type, thread, 1); - const operand_info &src_a= pI->operand_lookup(1); - unsigned nelem = src_a.get_vect_nelem(); - ptx_reg_t* v= new ptx_reg_t[8]; - thread->get_vector_operand_values( src_a, v, nelem ); - stride=src2_data.u32; - - memory_space_t space = pI->get_space(); - new_addr_type mem_txn_addr[MAX_ACCESSES_PER_INSN_PER_THREAD]; - int num_mem_txn=0; - - memory_space *mem = NULL; - addr_t addr = addr_reg.u32; - - smid = thread->get_hw_sid(); - if( whichspace(addr) == shared_space ) { - addr= generic_to_shared(smid,addr); - space = shared_space; - } - decode_space(space,thread,src1,mem,addr); - - type_info_key::type_decode(type,size,t); - if(g_debug_instruction) - printf("vp_st: thrd=%d,addr=%x, fp(size=%d), stride=%d\n",thrd,addr_reg.u32,size,src2_data.u32); - addr_t new_addr = addr+thread_group_offset(thrd,VP_MMA,wmma_layout,type,stride)*size/8; - - if(g_debug_instruction){ - printf("vp_st:thread%d=%d,%d,%d,%d,%d,%d,%d,%d\n",thrd,v[0].s32,v[1].s32,v[2].s32,v[3].s32,v[4].s32,v[5].s32,v[6].s32,v[7].s32); - } - - for(k=0;k<8;k++){ - if(wmma_layout==ROW){ - mem->write(new_addr+4*k,size/8,&v[k].s64,thread,pI); - mem_txn_addr[num_mem_txn++]=new_addr+4*k; - } - else if(wmma_layout==COL){ - mem->write(new_addr+k*4*stride,size/8,&v[k].s64,thread,pI); - mem_txn_addr[num_mem_txn++]=new_addr+4*k*stride; - } - } - - delete [] v; - inst.space = space; - inst.set_addr(thrd, (new_addr_type *)mem_txn_addr , num_mem_txn); - inst.data_size = 4; // 4 byte transaction - assert( inst.memory_op == insn_memory_op ); -// thread->m_last_effective_address = addr; -// thread->m_last_memory_space = space; - } -} void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst ) { size_t size; @@ -3296,191 +3056,6 @@ void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst ) //thread->m_last_memory_space = space; } } -void vp_ld_impl(const ptx_instruction *pI, core_t *core, warp_inst_t &inst) -{ - size_t size; - int t,i; - unsigned smid; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - unsigned type = pI->get_type(); - unsigned wmma_type = pI->get_wmma_type(); - unsigned wmma_layout = pI->get_wmma_layout(0); - int tid = inst.warp_id_func()*core->get_warp_size(); - int thrd,stride; - ptx_thread_info *thread; - _memory_op_t insn_memory_op = pI->has_memory_read() ? memory_load : memory_store; - for (thrd=0; thrd < core->get_warp_size(); thrd++){ - thread = core->get_thread_info()[tid+thrd]; - ptx_reg_t src1_data = thread->get_operand_value(src1, dst, U32_TYPE, thread, 1); - ptx_reg_t src2_data = thread->get_operand_value(src2, dst, U32_TYPE, thread, 1); - stride=src2_data.u32; - memory_space_t space = pI->get_space(); - - new_addr_type mem_txn_addr[MAX_ACCESSES_PER_INSN_PER_THREAD]; - int num_mem_txn=0; - - memory_space *mem = NULL; - addr_t addr = src1_data.u32; - - smid = thread->get_hw_sid(); - if( whichspace(addr) == shared_space ) { - addr= generic_to_shared(smid,addr); - space = shared_space; - } - - decode_space(space,thread,src1,mem,addr); - type_info_key::type_decode(type,size,t); - - ptx_reg_t data[8]; - addr_t new_addr; - - //note we are using distribution of VP_MMA for every type of load! - if(wmma_type==LOAD_A||wmma_type==LOAD_C){ - new_addr = addr+thread_group_offset(thrd,VP_MMA,wmma_layout,type,stride)*size/8; - } - else if(wmma_type==LOAD_B4){ - new_addr = addr+thread_group_offset(thrd,VP_MMA,wmma_layout,type,stride)/2; - } - else if (wmma_type==LOAD_B8){ - new_addr = addr+thread_group_offset(thrd,VP_MMA,wmma_layout,type,stride); - } - else if (wmma_type==LOAD_B16){ - new_addr = addr+thread_group_offset(thrd,VP_MMA,wmma_layout,type,stride)*2; - } - - if(g_debug_instruction) - printf("vp_ld: thrx=%d,addr=%x, base_addr=%x, size=%d, stride=%d\n",thrd,new_addr,addr,size,src2_data.u32); - - if(wmma_type==LOAD_A||wmma_type==LOAD_C){ - printf("lda/c:"); - for(i=0;i<8;i++){ - if(wmma_layout==ROW){ - //mem->read(new_addr+4*i,size/8,&data[i].s64); - mem->read(new_addr+4*i,size/8,&data[i].s64); - printf("%x ", new_addr+4*i); - mem_txn_addr[num_mem_txn++]=new_addr+4*i; - } - else if(wmma_layout==COL){ - //mem->read(new_addr+4*stride*i,size/8,&data[i].s64); - printf("%x ", new_addr+4*stride*i); - mem->read(new_addr+4*stride*i,size/8,&data[i].s64); - mem_txn_addr[num_mem_txn++]=new_addr+4*stride*i; - } - } - - } - - else if(wmma_type==LOAD_B4){ - printf("ldb4:"); - if(wmma_layout==ROW){ - mem->read(new_addr,size/8,&data[0].s64); - printf("%x ",new_addr); - mem_txn_addr[num_mem_txn++]=new_addr; - } - else if(wmma_layout==COL){ - } - } - else if(wmma_type==LOAD_B8){ - printf("ldb8:"); - if(wmma_layout==ROW){ - mem->read(new_addr,size/8,&data[0].s64); - mem->read(new_addr+4,size/8,&data[1].s64); - printf("%x ",new_addr,new_addr+4); - - mem_txn_addr[num_mem_txn++]=new_addr; - mem_txn_addr[num_mem_txn++]=new_addr+4; - } - else if(wmma_layout==COL){ - - } - } - else if(wmma_type==LOAD_B16){ - printf("ldb16:"); - if(wmma_layout==ROW){ - mem->read(new_addr,size/8,&data[0].s64); - mem->read(new_addr+4,size/8,&data[1].s64); - mem->read(new_addr+8,size/8,&data[2].s64); - mem->read(new_addr+12,size/8,&data[3].s64); - printf("%x ",new_addr,new_addr+4,new_addr+8,new_addr+12); - mem_txn_addr[num_mem_txn++]=new_addr; - mem_txn_addr[num_mem_txn++]=new_addr+4; - mem_txn_addr[num_mem_txn++]=new_addr+8; - mem_txn_addr[num_mem_txn++]=new_addr+12; - } - else if(wmma_layout==COL){ - } - } - else{ - printf("wrong vp_load type\n");; - abort(); - } - printf("\n"); - - //generate timing memory request - inst.space = space; - inst.set_addr(thrd, (new_addr_type *)mem_txn_addr , num_mem_txn); - inst.data_size = 4; // 4 byte transaction - assert( inst.memory_op == insn_memory_op ); - printf("\nVPLOAD_THREAD%d:",thrd); - for(int lll=0;lll<num_mem_txn;lll++) - { - printf("%x ",mem_txn_addr[lll]); - } - printf("\n"); - - int num_reg; - if(g_debug_instruction){ - printf("\nvp_ld:thread%d= ",thrd); - if((wmma_type==LOAD_A)||(wmma_type==LOAD_C)){ - num_reg=8; - } - else if(wmma_type==LOAD_B4){ - num_reg=1; - } - else if(wmma_type==LOAD_B8){ - num_reg=2; - } - else if(wmma_type==LOAD_B16){ - num_reg=4; - } - for(i=0;i<num_reg;i++){ - printf("%x ",data[i].s32); - } - printf("\n"); - } - - if((wmma_type==LOAD_A)||(wmma_type==LOAD_C)){ - thread->set_wmma_vector_operand_values(dst,data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7]); - } - else if(wmma_type==LOAD_B4){ - thread->set_vector_operand_values(dst,data[0],data[0],data[0],data[0]); - } - else if(wmma_type==LOAD_B8){ - thread->set_vector_operand_values(dst,data[0],data[1],data[1],data[1]); - } - else if (wmma_type==LOAD_B16){ - thread->set_vector_operand_values(dst,data[0],data[1],data[2],data[3]); - } - else - abort(); - - - - if(g_debug_instruction){ - for(int i=0;i<num_reg;i++) - printf("vp_ld:data[%i].s64=%x\n",i,data[i].u64); - } - - - //thread->m_last_effective_address = addr; - //thread->m_last_memory_space = space; - } - - - -} void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst ) { diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 73f6161..e6f957a 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -55,9 +55,6 @@ OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9) OP_W_DEF(MMA_OP,mma_impl,"mma",1,1) OP_W_DEF(MMA_LD_OP,mma_ld_impl,"mma_load",1,5) OP_W_DEF(MMA_ST_OP,mma_st_impl,"mma_store",0,5) -OP_W_DEF(VP_MMA_OP,vp_mma_impl,"vp_mma",1,1) -OP_W_DEF(VP_LD_OP,vp_ld_impl,"vp_load",1,5) -OP_W_DEF(VP_ST_OP,vp_st_impl,"vp_store",0,5) OP_DEF(CALL_OP,call_impl,"call",1,3) OP_DEF(CALLP_OP,callp_impl,"callp",1,3) OP_DEF(CLZ_OP,clz_impl,"clz",1,1) diff --git a/src/cuda-sim/opcodes.h b/src/cuda-sim/opcodes.h index ad8d8f1..b91d92f 100644 --- a/src/cuda-sim/opcodes.h +++ b/src/cuda-sim/opcodes.h @@ -63,16 +63,9 @@ enum special_regs { enum wmma_type{ LOAD_A, LOAD_B, - LOAD_B4,//vp - LOAD_B8,//vp - LOAD_B16,//vp LOAD_C, STORE_D, MMA, - VP_MMA, - VP_MMA4, - VP_MMA8, - VP_MMA16, ROW, COL, M16N16K16 diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 9c78e9f..ab640d7 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -36,7 +36,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "ptx.tab.h" #include <string.h> -char linebuf[1024]; +char linebuf[4096]; unsigned col = 0; #define TC col+=strlen(ptx_text); #define CHECK_UNSIGNED \ @@ -72,9 +72,6 @@ brkpt TC; ptx_lval.int_value = BRKPT_OP; return OPCODE; wmma TC; ptx_lval.int_value = MMA_OP; return OPCODE; wmma\.load TC; ptx_lval.int_value = MMA_LD_OP; return OPCODE; wmma\.store TC; ptx_lval.int_value = MMA_ST_OP; return OPCODE; -vp\.load TC; ptx_lval.int_value=VP_LD_OP; return OPCODE; -vp\.store TC; ptx_lval.int_value=VP_ST_OP; return OPCODE; -vp TC; ptx_lval.int_value=VP_MMA_OP; return OPCODE; call TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode callp TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE; @@ -165,12 +162,6 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.c\.sync TC; ptx_lval.int_value = LOAD_C; return WMMA_DIRECTIVE; \.d\.sync TC; ptx_lval.int_value = STORE_D; return WMMA_DIRECTIVE; \.mma\.sync TC;ptx_lval.int_value=MMA; return WMMA_DIRECTIVE; -\.mma4\.sync TC;ptx_lval.int_value=VP_MMA4; return WMMA_DIRECTIVE; -\.mma8\.sync TC;ptx_lval.int_value=VP_MMA8; return WMMA_DIRECTIVE; -\.mma16\.sync TC;ptx_lval.int_value=VP_MMA16; return WMMA_DIRECTIVE; -\.b4\.sync TC; ptx_lval.int_value=LOAD_B4; return WMMA_DIRECTIVE; -\.b8\.sync TC; ptx_lval.int_value=LOAD_B8; return WMMA_DIRECTIVE; -\.b16\.sync TC; ptx_lval.int_value=LOAD_B16; return WMMA_DIRECTIVE; \.row TC; ptx_lval.int_value = ROW; return LAYOUT; \.col TC; ptx_lval.int_value = COL; return LAYOUT; @@ -415,7 +406,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; "//"[^\n]* TC; // eat single -\n.* col=0; strncpy(linebuf, yytext + 1, 1024); yyless( 1 ); +\n.* col=0; strncpy(linebuf, yytext + 1, sizeof(linebuf)); yyless( 1 ); " " TC; "\t" TC; diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 54ac2bc..8b901a3 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -279,6 +279,7 @@ ptr_spec: /*empty*/ ptr_space_spec: GLOBAL_DIRECTIVE { add_ptr_spec(global_space); } | LOCAL_DIRECTIVE { add_ptr_spec(local_space); } | SHARED_DIRECTIVE { add_ptr_spec(shared_space); } + | CONST_DIRECTIVE { add_ptr_spec(global_space); } ptr_align_spec: ALIGN_DIRECTIVE INT_OPERAND @@ -340,6 +341,7 @@ var_spec_list: var_spec var_spec: space_spec | type_spec | align_spec + | VISIBLE_DIRECTIVE | EXTERN_DIRECTIVE { add_extern_spec(); } | WEAK_DIRECTIVE ; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 9800e1e..d12c741 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1089,15 +1089,9 @@ ptx_instruction::ptx_instruction( int opcode, case SYNC_OPTION: case LOAD_A: case LOAD_B: - case LOAD_B4: - case LOAD_B8: - case LOAD_B16: case LOAD_C: case STORE_D: case MMA: - case VP_MMA4: - case VP_MMA8: - case VP_MMA16: m_wmma_type=last_ptx_inst_option; break; case ROW: diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index e025013..0767379 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -105,7 +105,7 @@ private: int m_is_function; bool m_is_non_arch_reg; - friend class type_info_key_compare; + friend struct type_info_key_compare; }; class symbol_table; @@ -1093,7 +1093,7 @@ public: int membar_level() const { return m_membar_level; } bool has_memory_read() const { - if( m_opcode == LD_OP || m_opcode == LDU_OP || m_opcode == TEX_OP|| m_opcode==MMA_LD_OP || m_opcode==VP_LD_OP) + if( m_opcode == LD_OP || m_opcode == LDU_OP || m_opcode == TEX_OP|| m_opcode==MMA_LD_OP ) return true; // Check PTXPlus operand type below // Source operands are memory operands @@ -1105,7 +1105,7 @@ public: return false; } bool has_memory_write() const { - if( m_opcode == ST_OP || m_opcode==MMA_ST_OP || m_opcode==VP_ST_OP ) return true; + if( m_opcode == ST_OP || m_opcode==MMA_ST_OP ) return true; // Check PTXPlus operand type below // Destination operand is a memory operand ptx_instruction::const_iterator op=op_iter_begin(); diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 6c1b595..11d9013 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -54,6 +54,7 @@ extern int ptxinfo_debug; extern FILE *ptxinfo_in; static bool g_save_embedded_ptx; +static int g_occupancy_sm_number; bool g_keep_intermediate_files; bool m_ptx_save_converted_ptxplus; @@ -71,6 +72,10 @@ void ptx_reg_options(option_parser_t opp) &m_ptx_save_converted_ptxplus, "Saved converted ptxplus to a file", "0"); + option_parser_register(opp, "-gpgpu_occupancy_sm_number", OPT_INT32, &g_occupancy_sm_number, + "The SM number to pass to ptxas when getting register usage for computing GPU occupancy. " + "This parameter is required in the config.", + "0"); } void print_ptx_file( const char *p, unsigned source_num, const char *filename ) @@ -120,7 +125,7 @@ char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptxfilenam fflush(stdout); printf("GPGPU-Sim PTX: calling cuobjdump_to_ptxplus\ncommandline: %s\n", commandline); result = system(commandline); - if(result){printf("GPGPU-Sim PTX: ERROR ** could not execute %s\n", commandline); exit(1);} + if(result){fprintf(stderr, "GPGPU-Sim PTX: ERROR ** could not execute %s\n", commandline); exit(1);} // Get ptxplus from file @@ -142,7 +147,7 @@ char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptxfilenam printf("GPGPU-Sim PTX: removing temporary files using \"%s\"\n", rm_commandline); int rm_result = system(rm_commandline); if( rm_result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while removing temporary files %d\n", rm_result); + fprintf(stderr, "GPGPU-Sim PTX: ERROR ** while removing temporary files %d\n", rm_result); exit(1); } } @@ -193,7 +198,7 @@ void fix_duplicate_errors(char fname2[1024]) { printf("Running: %s\n", commandline); int result = system(commandline); if (result != 0) { - printf("GPGPU-Sim PTX: ERROR ** while changing filename from %s to %s", fname2, tempfile); + fprintf(stderr, "GPGPU-Sim PTX: ERROR ** while changing filename from %s to %s", fname2, tempfile); exit(1); } @@ -282,12 +287,12 @@ void fix_duplicate_errors(char fname2[1024]) { printf("Running: %s\n", commandline); result = system(commandline); if (result != 0) { - printf("GPGPU-Sim PTX: ERROR ** while deleting %s", tempfile); + fprintf(stderr, "GPGPU-Sim PTX: ERROR ** while deleting %s", tempfile); exit(1); } } -void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version ) +void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num ) { char fname[1024]; snprintf(fname,1024,"_ptx_XXXXXX"); @@ -308,9 +313,9 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num printf("Running: %s\n", commandline2); int result = system(commandline2); if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); - printf(" Ensure you have write access to simulation directory\n"); - printf(" and have \'cat\' and \'sed\' in your path.\n"); + fprintf(stderr, "GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); + fprintf(stderr, " Ensure you have write access to simulation directory\n"); + fprintf(stderr, " and have \'cat\' and \'sed\' in your path.\n"); exit(1); } @@ -321,15 +326,20 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num extra_flags[0]=0; #if CUDART_VERSION >= 3000 - if (sm_version == 0) sm_version = 20; + if ( g_occupancy_sm_number == 0 ) { + fprintf( stderr, "gpgpusim.config must specify the sm version for the GPU that you use to compute occupancy \"-gpgpu_occupancy_sm_number XX\".\n" + "The register file size is specifically tied to the sm version used to querry ptxas for register usage.\n" + "A register size/SM mismatch may result in occupancy differences." ); + exit(1); + } extern bool g_cdp_enabled; if(!g_cdp_enabled) - snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); + snprintf(extra_flags,1024,"--gpu-name=sm_%u", g_occupancy_sm_number); else - snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version); + snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",g_occupancy_sm_number); #endif - snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", + snprintf(commandline,1024,"$PTXAS_CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", extra_flags, fname2, tempfile_ptxinfo); printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); result = system(commandline); @@ -347,8 +357,8 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num result = system(commandline); } if (result != 0) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); - printf(" Ensure ptxas is in your path.\n"); + fprintf(stderr, "GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); + fprintf(stderr, " Ensure ptxas is in your path.\n"); exit(1); } } @@ -362,7 +372,7 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num printf("GPGPU-Sim PTX: removing ptxinfo using \"%s\"\n", commandline); result = system(commandline); if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (c) %d\n", result); + fprintf(stderr, "GPGPU-Sim PTX: ERROR ** while loading PTX (c) %d\n", result); exit(1); } } diff --git a/src/cuda-sim/ptx_loader.h b/src/cuda-sim/ptx_loader.h index d3d0c92..cb02eda 100644 --- a/src/cuda-sim/ptx_loader.h +++ b/src/cuda-sim/ptx_loader.h @@ -32,7 +32,7 @@ extern bool g_override_embedded_ptx; class symbol_table *gpgpu_ptx_sim_load_ptx_from_string( const char *p, unsigned source_num ); -void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version=20 ); +void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num ); char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptx_str, const std::string sass_str, const std::string elf_str); bool keep_intermediate_files(); diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index eb81961..d5324d0 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -267,7 +267,7 @@ void parse_assert_impl( int test_value, const char *file, unsigned line, const c parse_error_impl(file,line, msg); } -extern char linebuf[1024]; +extern char linebuf[4096]; void set_return() @@ -436,7 +436,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_shared_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (shared memory space)\n", + printf("from 0x%llx to 0x%llx (shared memory space)\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); @@ -467,7 +467,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_global_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (global memory space) %u\n", + printf("from 0x%llx to 0x%llx (global memory space) %u\n", addr+addr_pad, addr+addr_pad + num_bits/8, g_const_alloc++); @@ -488,7 +488,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_global_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (global memory space)\n", + printf("from 0x%llx to 0x%llx (global memory space)\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); @@ -505,7 +505,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_local_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (local memory space)\n", + printf("from 0x%llx to 0x%llx (local memory space)\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); @@ -518,7 +518,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_local_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx\n", + printf("from 0x%llx to 0x%llx\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index ea87e59..0a6e8eb 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -28,7 +28,7 @@ #define ptx_sim_h_INCLUDED #include <stdlib.h> -#include "half.hpp" +#include "half.h" #include "../abstract_hardware_model.h" #include "../tr1_hash_map.h" diff --git a/src/debug.cc b/src/debug.cc index cfd7bb0..ae15760 100644 --- a/src/debug.cc +++ b/src/debug.cc @@ -222,7 +222,7 @@ void gpgpu_sim::gpgpu_debug() } } -bool thread_at_brkpt( ptx_thread_info *thread, const struct brk_pt &b ) +bool thread_at_brkpt( ptx_thread_info *thread, const class brk_pt &b ) { return b.is_equal(thread->get_location(),thread->get_uid()); } diff --git a/src/debug.h b/src/debug.h index 7c79f1e..1277494 100644 --- a/src/debug.h +++ b/src/debug.h @@ -87,7 +87,7 @@ extern int gpgpu_ptx_instruction_classification ; class ptx_thread_info; class ptx_instruction; -bool thread_at_brkpt( ptx_thread_info *thd_info, const struct brk_pt &b ); +bool thread_at_brkpt( ptx_thread_info *thd_info, const class brk_pt &b ); void hit_watchpoint( unsigned watchpoint_num, ptx_thread_info *thd, const ptx_instruction *pI ); #endif diff --git a/src/gpgpu-sim/Makefile b/src/gpgpu-sim/Makefile index 4f77699..f10a8a4 100644 --- a/src/gpgpu-sim/Makefile +++ b/src/gpgpu-sim/Makefile @@ -48,7 +48,7 @@ ifeq ($(GNUC_CPP0X), 1) endif ifneq ($(DEBUG),1) - OPTFLAGS += -O0 + OPTFLAGS += -O3 else CXXFLAGS += endif diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index a8bff14..15c63e7 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -87,7 +87,7 @@ struct bank_t unsigned int bkgrpindex; }; -struct mem_fetch; +class mem_fetch; class dram_t { @@ -178,7 +178,7 @@ private: unsigned int ave_mrqs_partial; unsigned int bwutil_partial; - struct memory_stats_t *m_stats; + class memory_stats_t *m_stats; class Stats* mrqq_Dist; //memory request queue inside DRAM friend class frfcfs_scheduler; diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 5ea4190..8886398 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -517,18 +517,28 @@ void cache_stats::print_stats(FILE *fout, const char *cache_name) const{ /// the provided name is used. /// The printed format is "<cache_name>[<request_type>][<request_status>] = <stat_value>" /// + std::vector< unsigned > total_access; + total_access.resize(NUM_MEM_ACCESS_TYPE, 0); std::string m_cache_name = cache_name; for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) { for (unsigned status = 0; status < NUM_CACHE_REQUEST_STATUS; ++status) { - if(m_stats[type][status] > 0){ - fprintf(fout, "\t%s[%s][%s] = %u\n", - m_cache_name.c_str(), - mem_access_type_str((enum mem_access_type)type), - cache_request_status_str((enum cache_request_status)status), - m_stats[type][status]); - } + fprintf(fout, "\t%s[%s][%s] = %u\n", + m_cache_name.c_str(), + mem_access_type_str((enum mem_access_type)type), + cache_request_status_str((enum cache_request_status)status), + m_stats[type][status]); + if(status != RESERVATION_FAIL) + total_access[type]+= m_stats[type][status]; } } + for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) { + if(total_access[type] > 0) + fprintf(fout, "\t%s[%s][%s] = %u\n", + m_cache_name.c_str(), + mem_access_type_str((enum mem_access_type)type), + "TOTAL_ACCESS", + total_access[type]); + } } void cache_sub_stats::print_port_stats(FILE *fout, const char *cache_name) const diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index eba6f54..d4b636b 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -32,10 +32,12 @@ #include <stdio.h> #include <stdlib.h> #include <math.h> +#include <signal.h> #include "zlib.h" #include "shader.h" +#include "shader_trace.h" #include "dram.h" #include "mem_fetch.h" @@ -87,6 +89,14 @@ unsigned long long gpu_tot_sim_cycle = 0; // performance counter for stalls due to congestion. unsigned int gpu_stall_dramfull = 0; unsigned int gpu_stall_icnt2sh = 0; +unsigned long long partiton_reqs_in_parallel = 0; +unsigned long long partiton_reqs_in_parallel_total = 0; +unsigned long long partiton_reqs_in_parallel_util = 0; +unsigned long long partiton_reqs_in_parallel_util_total = 0; +unsigned long long gpu_sim_cycle_parition_util = 0; +unsigned long long gpu_tot_sim_cycle_parition_util = 0; +unsigned long long partiton_replys_in_parallel = 0; +unsigned long long partiton_replys_in_parallel_total = 0; /* Clock Domains */ @@ -223,7 +233,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "per-shader L1 data cache config " " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}", "none" ); - option_parser_register(opp, "-gpgpu_cache:dl1PreShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, + option_parser_register(opp, "-gpgpu_cache:dl1PrefShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, "per-shader L1 data cache config " " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}", "none" ); @@ -309,9 +319,6 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_operand_collector_num_units_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_units_tensor_core, "number of collector units (default = 4)", "4"); - option_parser_register(opp, "-gpgpu_operand_collector_num_units_vp_core", OPT_INT32, &gpgpu_operand_collector_num_units_vp_core, - "number of collector units (default = 4)", - "4"); option_parser_register(opp, "-gpgpu_operand_collector_num_units_mem", OPT_INT32, &gpgpu_operand_collector_num_units_mem, "number of collector units (default = 2)", "2"); @@ -327,9 +334,6 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_in_ports_tensor_core, "number of collector unit in ports (default = 1)", "1"); - option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_vp_core", OPT_INT32, &gpgpu_operand_collector_num_in_ports_vp_core, - "number of collector unit in ports (default = 1)", - "1"); option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_mem", OPT_INT32, &gpgpu_operand_collector_num_in_ports_mem, "number of collector unit in ports (default = 1)", "1"); @@ -345,9 +349,6 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_out_ports_tensor_core, "number of collector unit in ports (default = 1)", "1"); - option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_vp_core", OPT_INT32, &gpgpu_operand_collector_num_out_ports_vp_core, - "number of collector unit in ports (default = 1)", - "1"); option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_mem", OPT_INT32, &gpgpu_operand_collector_num_out_ports_mem, "number of collector unit in ports (default = 1)", "1"); @@ -368,8 +369,8 @@ void shader_core_config::reg_options(class OptionParser * opp) "1"); option_parser_register(opp, "-gpgpu_pipeline_widths", OPT_CSTR, &pipeline_widths_string, "Pipeline widths " - "ID_OC_SP,ID_OC_SFU,ID_OC_TENSOR_CORE,ID_OC_VP_CORE,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_TENSOR_CORE,OC_EX_TENSOR_CORE,OC_EX_MEM,EX_WB", - "1,1,1,1,1,1,1,1,1,1,1" ); + "ID_OC_SP,ID_OC_SFU,ID_OC_TENSOR_CORE,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_TENSOR_CORE,OC_EX_TENSOR_CORE,OC_EX_MEM,EX_WB", + "1,1,1,1,1,1,1,1,1,1" ); option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32, &gpgpu_num_sp_units, "Number of SP units (default=1)", "1"); @@ -379,9 +380,6 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32, &gpgpu_num_tensor_core_units, "Number of tensor_core units (default=1)", "1"); - option_parser_register(opp, "-gpgpu_num_vp_core_units", OPT_INT32, &gpgpu_num_vp_core_units, - "Number of vp_core units (default=1)", - "1"); option_parser_register(opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units, "Number if ldst units (default=1) WARNING: not hooked up to anything", "1"); @@ -768,6 +766,10 @@ void gpgpu_sim::init() gpu_sim_insn = 0; last_gpu_sim_insn = 0; m_total_cta_launched=0; + partiton_reqs_in_parallel = 0; + partiton_replys_in_parallel = 0; + partiton_reqs_in_parallel_util = 0; + gpu_sim_cycle_parition_util = 0; reinit_clock_domains(); set_param_gpgpu_num_shaders(m_config.num_shader()); @@ -804,8 +806,16 @@ void gpgpu_sim::update_stats() { gpu_tot_sim_cycle += gpu_sim_cycle; gpu_tot_sim_insn += gpu_sim_insn; gpu_tot_issued_cta += m_total_cta_launched; + partiton_reqs_in_parallel_total += partiton_reqs_in_parallel; + partiton_replys_in_parallel_total += partiton_replys_in_parallel; + partiton_reqs_in_parallel_util_total += partiton_reqs_in_parallel_util; + gpu_tot_sim_cycle_parition_util += gpu_sim_cycle_parition_util ; gpu_sim_cycle = 0; + partiton_reqs_in_parallel = 0; + partiton_replys_in_parallel = 0; + partiton_reqs_in_parallel_util = 0; + gpu_sim_cycle_parition_util = 0; gpu_sim_insn = 0; m_total_cta_launched = 0; } @@ -989,6 +999,21 @@ void gpgpu_sim::gpu_print_stat() printf("gpu_stall_dramfull = %d\n", gpu_stall_dramfull); printf("gpu_stall_icnt2sh = %d\n", gpu_stall_icnt2sh ); + printf("partiton_reqs_in_parallel = %lld\n", partiton_reqs_in_parallel); + printf("partiton_reqs_in_parallel_total = %lld\n", partiton_reqs_in_parallel_total ); + printf("partiton_level_parallism = %12.4f\n", (float)partiton_reqs_in_parallel / gpu_sim_cycle); + printf("partiton_level_parallism_total = %12.4f\n", (float)(partiton_reqs_in_parallel+partiton_reqs_in_parallel_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); + printf("partiton_reqs_in_parallel_util = %lld\n", partiton_reqs_in_parallel_util); + printf("partiton_reqs_in_parallel_util_total = %lld\n", partiton_reqs_in_parallel_util_total ); + printf("gpu_sim_cycle_parition_util = %lld\n", gpu_sim_cycle_parition_util); + printf("gpu_tot_sim_cycle_parition_util = %lld\n", gpu_tot_sim_cycle_parition_util ); + printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle_parition_util); + printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_sim_cycle_parition_util+gpu_tot_sim_cycle_parition_util) ); + printf("partiton_replys_in_parallel = %lld\n", partiton_replys_in_parallel); + printf("partiton_replys_in_parallel_total = %lld\n", partiton_replys_in_parallel_total ); + printf("L2_BW = %12.4f GB/Sec\n", ((float)(partiton_replys_in_parallel * 32) / (gpu_sim_cycle * m_config.icnt_period)) / 1000000000); + printf("L2_BW_total = %12.4f GB/Sec\n", ((float)((partiton_replys_in_parallel+partiton_replys_in_parallel_total) * 32) / ((gpu_tot_sim_cycle+gpu_sim_cycle) * m_config.icnt_period)) / 1000000000 ); + time_t curr_time; time(&curr_time); unsigned long long elapsed_time = MAX( curr_time - g_simulation_starttime, 1 ); @@ -1202,8 +1227,8 @@ bool shader_core_ctx::occupy_shader_resource_1block(kernel_info_t & k, bool occu m_occupied_regs += (padded_cta_size * ((kernel_info->regs+3)&~3)); m_occupied_ctas++; - printf("GPGPU-Sim uArch: Shader %d occupied %d threads, %d shared mem, %d registers, %d ctas\n", - m_sid, m_occupied_n_threads, m_occupied_shmem, m_occupied_regs, m_occupied_ctas); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: Occupied %d threads, %d shared mem, %d registers, %d ctas\n", + m_occupied_n_threads, m_occupied_shmem, m_occupied_regs, m_occupied_ctas); } return true; @@ -1328,8 +1353,8 @@ void shader_core_ctx::issue_block2core( kernel_info_t &kernel ) m_n_active_cta++; shader_CTA_count_log(m_sid, 1); - printf("GPGPU-Sim uArch: core:%3d, cta:%2u, start_tid:%4u, end_tid:%4u, initialized @(%lld,%lld)\n", - m_sid, free_cta_hw_id, start_thread, end_thread, gpu_sim_cycle, gpu_tot_sim_cycle ); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: cta:%2u, start_tid:%4u, end_tid:%4u, initialized @(%lld,%lld)\n", + free_cta_hw_id, start_thread, end_thread, gpu_sim_cycle, gpu_tot_sim_cycle ); } @@ -1393,6 +1418,7 @@ void gpgpu_sim::cycle() for (unsigned i=0;i<m_shader_config->n_simt_clusters;i++) m_cluster[i]->icnt_cycle(); } + unsigned partiton_replys_in_parallel_per_cycle = 0; if (clock_mask & ICNT) { // pop from memory controller to interconnect for (unsigned i=0;i<m_memory_config->m_n_mem_sub_partition;i++) { @@ -1405,6 +1431,7 @@ void gpgpu_sim::cycle() mf->set_status(IN_ICNT_TO_SHADER,gpu_sim_cycle+gpu_tot_sim_cycle); ::icnt_push( m_shader_config->mem2device(i), mf->get_tpc(), mf, response_size ); m_memory_sub_partition[i]->pop(); + partiton_replys_in_parallel_per_cycle++; } else { gpu_stall_icnt2sh++; } @@ -1413,6 +1440,7 @@ void gpgpu_sim::cycle() } } } + partiton_replys_in_parallel += partiton_replys_in_parallel_per_cycle; if (clock_mask & DRAM) { for (unsigned i=0;i<m_memory_config->m_n_mem;i++){ @@ -1425,6 +1453,7 @@ void gpgpu_sim::cycle() } // L2 operations follow L2 clock domain + unsigned partiton_reqs_in_parallel_per_cycle = 0; if (clock_mask & L2) { m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].clear(); for (unsigned i=0;i<m_memory_config->m_n_mem_sub_partition;i++) { @@ -1435,11 +1464,17 @@ void gpgpu_sim::cycle() } else { mem_fetch* mf = (mem_fetch*) icnt_pop( m_shader_config->mem2device(i) ); m_memory_sub_partition[i]->push( mf, gpu_sim_cycle + gpu_tot_sim_cycle ); + partiton_reqs_in_parallel_per_cycle++; } m_memory_sub_partition[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle); m_memory_sub_partition[i]->accumulate_L2cache_stats(m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX]); } } + partiton_reqs_in_parallel += partiton_reqs_in_parallel_per_cycle; + if(partiton_reqs_in_parallel_per_cycle > 0){ + partiton_reqs_in_parallel_util += partiton_reqs_in_parallel_per_cycle; + gpu_sim_cycle_parition_util++; + } if (clock_mask & ICNT) { icnt_transfer(); @@ -1467,9 +1502,8 @@ void gpgpu_sim::cycle() if( g_single_step && ((gpu_sim_cycle+gpu_tot_sim_cycle) >= g_single_step) ) { - asm("int $03"); + raise(SIGTRAP); // Debug breakpoint } - printf("gpu_sim_cycle=%d\n",gpu_sim_cycle); gpu_sim_cycle++; if( g_interactive_debugger_enabled ) @@ -1528,7 +1562,8 @@ void gpgpu_sim::cycle() hrs = elapsed_time/3600 - 24*days; minutes = elapsed_time/60 - 60*(hrs + 24*days); sec = elapsed_time - 60*(minutes + 60*(hrs + 24*days)); - printf("GPGPU-Sim uArch: cycles simulated: %lld inst.: %lld (ipc=%4.1f) sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s", + + DPRINTF(LIVENESS, "GPGPU-Sim uArch: cycles simulated: %lld inst.: %lld (ipc=%4.1f) sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s", gpu_tot_sim_cycle + gpu_sim_cycle, gpu_tot_sim_insn + gpu_sim_insn, (double)gpu_sim_insn/(double)gpu_sim_cycle, (unsigned)((gpu_tot_sim_insn+gpu_sim_insn) / elapsed_time), diff --git a/src/gpgpu-sim/mem_fetch.cc b/src/gpgpu-sim/mem_fetch.cc index 580c051..729636d 100644 --- a/src/gpgpu-sim/mem_fetch.cc +++ b/src/gpgpu-sim/mem_fetch.cc @@ -39,7 +39,7 @@ mem_fetch::mem_fetch( const mem_access_t &access, unsigned wid, unsigned sid, unsigned tpc, - const class memory_config *config ) + const struct memory_config *config ) { m_request_uid = sm_next_mf_request_uid++; m_access = access; diff --git a/src/gpgpu-sim/mem_fetch.h b/src/gpgpu-sim/mem_fetch.h index c89edbb..de98748 100644 --- a/src/gpgpu-sim/mem_fetch.h +++ b/src/gpgpu-sim/mem_fetch.h @@ -55,7 +55,7 @@ public: unsigned wid, unsigned sid, unsigned tpc, - const class memory_config *config ); + const struct memory_config *config ); ~mem_fetch(); void set_status( enum mem_fetch_status status, unsigned long long cycle ); @@ -141,7 +141,7 @@ private: static unsigned sm_next_mf_request_uid; - const class memory_config *m_mem_config; + const struct memory_config *m_mem_config; unsigned icnt_flit_size; }; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index eeb59bb..23f255d 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -149,7 +149,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_TENSOR_CORE], - &m_pipeline_reg[ID_OC_VP_CORE], &m_pipeline_reg[ID_OC_MEM], i ) @@ -165,7 +164,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_TENSOR_CORE], - &m_pipeline_reg[ID_OC_VP_CORE], &m_pipeline_reg[ID_OC_MEM], i, config->gpgpu_scheduler_string @@ -182,7 +180,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_TENSOR_CORE], - &m_pipeline_reg[ID_OC_VP_CORE], &m_pipeline_reg[ID_OC_MEM], i ) @@ -198,7 +195,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_TENSOR_CORE], - &m_pipeline_reg[ID_OC_VP_CORE], &m_pipeline_reg[ID_OC_MEM], i, config->gpgpu_scheduler_string @@ -219,11 +215,10 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, } //op collector configuration - enum { SP_CUS, SFU_CUS, TENSOR_CORE_CUS, VP_CORE_CUS, MEM_CUS, GEN_CUS }; + enum { SP_CUS, SFU_CUS, TENSOR_CORE_CUS, MEM_CUS, GEN_CUS }; m_operand_collector.add_cu_set(SP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_sp); m_operand_collector.add_cu_set(SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu, m_config->gpgpu_operand_collector_num_out_ports_sfu); m_operand_collector.add_cu_set(TENSOR_CORE_CUS, config->gpgpu_operand_collector_num_units_tensor_core, config->gpgpu_operand_collector_num_out_ports_tensor_core); - m_operand_collector.add_cu_set(VP_CORE_CUS, config->gpgpu_operand_collector_num_units_vp_core, config->gpgpu_operand_collector_num_out_ports_vp_core); m_operand_collector.add_cu_set(MEM_CUS, m_config->gpgpu_operand_collector_num_units_mem, m_config->gpgpu_operand_collector_num_out_ports_mem); m_operand_collector.add_cu_set(GEN_CUS, m_config->gpgpu_operand_collector_num_units_gen, m_config->gpgpu_operand_collector_num_out_ports_gen); @@ -257,15 +252,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, in_ports.clear(),out_ports.clear(),cu_sets.clear(); } - for (unsigned i = 0; i < config->gpgpu_operand_collector_num_in_ports_vp_core; i++) { - in_ports.push_back(&m_pipeline_reg[ID_OC_VP_CORE]); - out_ports.push_back(&m_pipeline_reg[OC_EX_VP_CORE]); - cu_sets.push_back((unsigned)VP_CORE_CUS); - cu_sets.push_back((unsigned)GEN_CUS); - m_operand_collector.add_port(in_ports,out_ports,cu_sets); - in_ports.clear(),out_ports.clear(),cu_sets.clear(); - } - for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_mem; i++) { in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]); out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]); @@ -280,12 +266,10 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, in_ports.push_back(&m_pipeline_reg[ID_OC_SP]); in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]); in_ports.push_back(&m_pipeline_reg[ID_OC_TENSOR_CORE]); - in_ports.push_back(&m_pipeline_reg[ID_OC_VP_CORE]); in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]); out_ports.push_back(&m_pipeline_reg[OC_EX_SP]); out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]); out_ports.push_back(&m_pipeline_reg[OC_EX_TENSOR_CORE]); - out_ports.push_back(&m_pipeline_reg[OC_EX_VP_CORE]); out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]); cu_sets.push_back((unsigned)GEN_CUS); m_operand_collector.add_port(in_ports,out_ports,cu_sets); @@ -295,7 +279,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_operand_collector.init( m_config->gpgpu_num_reg_banks, this ); // execute - m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_sfu_units + config->gpgpu_num_tensor_core_units + config->gpgpu_num_vp_core_units + 1; // sp_unit, sfu, ldst_unit + m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_sfu_units + config->gpgpu_num_tensor_core_units + 1; // sp_unit, sfu, ldst_unit //m_dispatch_port = new enum pipeline_stage_name_t[ m_num_function_units ]; //m_issue_port = new enum pipeline_stage_name_t[ m_num_function_units ]; @@ -319,12 +303,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_issue_port.push_back(OC_EX_TENSOR_CORE); } - for (int k = 0; k < config->gpgpu_num_vp_core_units; k++) { - m_fu.push_back(new vp_core( &m_pipeline_reg[EX_WB], m_config, this )); - m_dispatch_port.push_back(ID_OC_VP_CORE); - m_issue_port.push_back(OC_EX_VP_CORE); - } - m_ldst_unit = new ldst_unit( m_icnt, m_mem_fetch_allocator, this, &m_operand_collector, m_scoreboard, config, mem_config, stats, shader_id, tpc_id ); m_fu.push_back(m_ldst_unit); m_dispatch_port.push_back(ID_OC_MEM); @@ -923,7 +901,7 @@ void scheduler_unit::cycle() ready_inst = true; const active_mask_t &active_mask = m_simt_stack[warp_id]->get_active_mask(); assert( warp(warp_id).inst_in_pipeline() ); - if ( (pI->op == LOAD_OP)||(pI->op ==TENSOR_CORE_LOAD_OP)||(pI->op ==VP_LOAD_OP)|| (pI->op == STORE_OP)|| (pI->op==TENSOR_CORE_STORE_OP) ||(pI->op==VP_STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) { + if ( (pI->op == LOAD_OP)||(pI->op ==TENSOR_CORE_LOAD_OP)|| (pI->op == STORE_OP)|| (pI->op==TENSOR_CORE_STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) { if( m_mem_out->has_free() ) { m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id); issued++; @@ -934,8 +912,7 @@ void scheduler_unit::cycle() bool sp_pipe_avail = m_sp_out->has_free(); bool sfu_pipe_avail = m_sfu_out->has_free(); bool tensor_core_pipe_avail = m_tensor_core_out->has_free(); - bool vp_core_pipe_avail = m_vp_core_out->has_free(); - if( sp_pipe_avail && (pI->op != SFU_OP) && (pI->op != TENSOR_CORE_OP) && (pI->op !=VP_CORE_OP)) { + if( sp_pipe_avail && (pI->op != SFU_OP) && (pI->op != TENSOR_CORE_OP) ) { //Jin: special for CDP api if(pI->m_is_cdp && !warp(warp_id).m_cdp_dummy) { @@ -976,14 +953,7 @@ void scheduler_unit::cycle() warp_inst_issued = true; } } - else if ( (pI->op == VP_CORE_OP) ) { - if( vp_core_pipe_avail ) { - m_shader->issue_warp(*m_vp_core_out,pI,active_mask,warp_id); - issued++; - issued_inst=true; - warp_inst_issued = true; - } - } } + } } else { SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) fails scoreboard\n", (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id() ); @@ -1149,11 +1119,10 @@ swl_scheduler::swl_scheduler ( shader_core_stats* stats, shader_core_ctx* shader register_set* sp_out, register_set* sfu_out, register_set* tensor_core_out, - register_set* vp_core_out, register_set* mem_out, int id, char* config_string ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, vp_core_out, mem_out, id ) + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ) { unsigned m_prioritization_readin; int ret = sscanf( config_string, @@ -1321,16 +1290,6 @@ void ldst_unit::get_L1T_sub_stats(struct cache_sub_stats &css) const{ void shader_core_ctx::warp_inst_complete(const warp_inst_t &inst) { - //#if 0 - //printf("[warp_inst_complete] uid=%u core=%u warp=%u pc=%#x @ time=%llu issued@%llu\n", - //const ptx_instruction *pI = m_func_info->get_instruction(inst.pc); - printf("[warp_inst_complete] uid=%u core=%u warp=%u pc=%d @ time=%llu \n", - inst.get_uid(), m_sid, inst.warp_id(), inst.pc, gpu_sim_cycle); - //printf("^instruction:%s",(pI->m_source).c_str()); - //inst.get_uid(), m_sid, inst.warp_id(), inst.pc, gpu_tot_sim_cycle + gpu_sim_cycle, inst.get_issue_cycle()); - //#endif - - if(inst.op_pipe==SP__OP) m_stats->m_num_sp_committed[m_sid]++; else if(inst.op_pipe==SFU__OP) @@ -1588,13 +1547,6 @@ tensor_core:: tensor_core( register_set* result_port, const shader_core_config m_name = "TENSOR_CORE"; } -vp_core:: vp_core( register_set* result_port, const shader_core_config *config,shader_core_ctx *core ) - : pipelined_simd_unit(result_port,config,config->max_vp_core_latency,core) -{ - m_name = "VP_CORE"; -} - - void sfu::issue( register_set& source_reg ) { warp_inst_t** ready_reg = source_reg.get_ready(); @@ -1615,16 +1567,6 @@ void tensor_core::issue( register_set& source_reg ) pipelined_simd_unit::issue(source_reg); } -void vp_core::issue( register_set& source_reg ) -{ - warp_inst_t** ready_reg = source_reg.get_ready(); - //m_core->incexecstat((*ready_reg)); - - (*ready_reg)->op_pipe= VP_CORE__OP; - m_core->incsfu_stat(m_core->get_config()->warp_size,(*ready_reg)->latency); - pipelined_simd_unit::issue(source_reg); -} - void ldst_unit::active_lanes_in_pipeline(){ unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline(); @@ -1655,13 +1597,6 @@ void tensor_core::active_lanes_in_pipeline(){ m_core->incfumemactivelanes_stat(active_count); } -void vp_core::active_lanes_in_pipeline(){ - unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline(); - assert(active_count<=m_core->get_config()->warp_size); - m_core->incsfuactivelanes_stat(active_count); - m_core->incfuactivelanes_stat(active_count); - m_core->incfumemactivelanes_stat(active_count); -} sp_unit::sp_unit( register_set* result_port, const shader_core_config *config,shader_core_ctx *core) : pipelined_simd_unit(result_port,config,config->max_sp_latency,core) @@ -2093,12 +2028,12 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num, kernel_info_t m_barriers.deallocate_barrier(cta_num); shader_CTA_count_unlog(m_sid, 1); - printf("GPGPU-Sim uArch: Shader %d finished CTA #%d (%lld,%lld), %u CTAs running\n", m_sid, cta_num, gpu_sim_cycle, gpu_tot_sim_cycle, - m_n_active_cta ); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: Finished CTA #%d (%lld,%lld), %u CTAs running\n", + cta_num, gpu_sim_cycle, gpu_tot_sim_cycle, m_n_active_cta); if( m_n_active_cta == 0 ) { - printf("GPGPU-Sim uArch: Shader %u empty (last released kernel %u \'%s\').\n", m_sid, kernel->get_uid(), - kernel->name().c_str() ); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: Empty (last released kernel %u \'%s\').\n", + kernel->get_uid(), kernel->name().c_str()); fflush(stdout); //Shader can only be empty when no more cta are dispatched @@ -2113,8 +2048,10 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num, kernel_info_t kernel->dec_running(); if( !m_gpu->kernel_more_cta_left(kernel) ) { if( !kernel->running() ) { - printf("GPGPU-Sim uArch: GPU detected kernel %u \'%s\' finished on shader %u.\n", kernel->get_uid(), - kernel->name().c_str(), m_sid ); + SHADER_DPRINTF(LIVENESS, + "GPGPU-Sim uArch: GPU detected kernel %u \'%s\' finished on shader %u.\n", kernel->get_uid(), + kernel->name().c_str(), m_sid); + if(m_kernel == kernel) m_kernel = NULL; m_gpu->set_kernel_done( kernel ); diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 99abb63..8ad6514 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -286,7 +286,7 @@ typedef std::bitset<WARP_PER_CTA_MAX> warp_set_t; int register_bank(int regnum, int wid, unsigned num_banks, unsigned bank_warp_shift); class shader_core_ctx; -class shader_core_config; +struct shader_core_config; class shader_core_stats; enum scheduler_prioritization_type @@ -319,12 +319,11 @@ public: register_set* sp_out, register_set* sfu_out, register_set* tensor_core_out, - register_set* vp_core_out, register_set* mem_out, int id) : m_supervised_warps(), m_stats(stats), m_shader(shader), m_scoreboard(scoreboard), m_simt_stack(simt), /*m_pipeline_reg(pipe_regs),*/ m_warp(warp), - m_sp_out(sp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_vp_core_out(vp_core_out),m_mem_out(mem_out), m_id(id){} + m_sp_out(sp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_mem_out(mem_out), m_id(id){} virtual ~scheduler_unit(){} virtual void add_supervised_warp_id(int i) { m_supervised_warps.push_back(&warp(i)); @@ -398,7 +397,6 @@ protected: register_set* m_sp_out; register_set* m_sfu_out; register_set* m_tensor_core_out; - register_set* m_vp_core_out; register_set* m_mem_out; int m_id; @@ -412,10 +410,9 @@ public: register_set* sp_out, register_set* sfu_out, register_set* tensor_core_out, - register_set* vp_core_out, register_set* mem_out, int id ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, vp_core_out, mem_out, id ){} + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ){} virtual ~lrr_scheduler () {} virtual void order_warps (); virtual void done_adding_supervised_warps() { @@ -431,10 +428,9 @@ public: register_set* sp_out, register_set* sfu_out, register_set* tensor_core_out, - register_set* vp_core_out, register_set* mem_out, int id ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out,vp_core_out, mem_out, id ){} + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ){} virtual ~gto_scheduler () {} virtual void order_warps (); virtual void done_adding_supervised_warps() { @@ -452,11 +448,10 @@ public: register_set* sp_out, register_set* sfu_out, register_set* tensor_core_out, - register_set* vp_core_out, register_set* mem_out, int id, char* config_str ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, vp_core_out, mem_out, id ), + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ), m_pending_warps() { unsigned inner_level_readin; @@ -504,7 +499,6 @@ public: register_set* sp_out, register_set* sfu_out, register_set* tensor_core_out, - register_set* vp_core_out, register_set* mem_out, int id, char* config_string ); @@ -979,7 +973,7 @@ struct ifetch_buffer_t { unsigned m_warp_id; }; -class shader_core_config; +struct shader_core_config; class simd_function_unit { public: @@ -1089,22 +1083,6 @@ public: virtual void active_lanes_in_pipeline(); virtual void issue( register_set& source_reg ); }; -class vp_core : public pipelined_simd_unit -{ -public: - vp_core( register_set* result_port, const shader_core_config *config, shader_core_ctx *core ); - virtual bool can_issue( const warp_inst_t &inst ) const - { - switch(inst.op) { - case VP_CORE_OP: break; - default: return false; - } - return pipelined_simd_unit::can_issue(inst); - } - virtual void active_lanes_in_pipeline(); - virtual void issue( register_set& source_reg ); -}; - class sp_unit : public pipelined_simd_unit @@ -1117,10 +1095,8 @@ public: case SFU_OP: return false; case LOAD_OP: return false; case TENSOR_CORE_LOAD_OP: return false; - case VP_LOAD_OP: return false; case STORE_OP: return false; case TENSOR_CORE_STORE_OP: return false; - case VP_STORE_OP: return false; case MEMORY_BARRIER_OP: return false; default: break; } @@ -1163,10 +1139,8 @@ public: switch(inst.op) { case LOAD_OP: break; case TENSOR_CORE_LOAD_OP: break; - case VP_LOAD_OP: break; case STORE_OP: break; case TENSOR_CORE_STORE_OP: break; - case VP_STORE_OP: break; case MEMORY_BARRIER_OP: break; default: return false; } @@ -1255,12 +1229,10 @@ enum pipeline_stage_name_t { ID_OC_SP=0, ID_OC_SFU, ID_OC_TENSOR_CORE, - ID_OC_VP_CORE, ID_OC_MEM, OC_EX_SP, OC_EX_SFU, OC_EX_TENSOR_CORE, - OC_EX_VP_CORE, OC_EX_MEM, EX_WB, N_PIPELINE_STAGES @@ -1270,12 +1242,10 @@ const char* const pipeline_stage_name_decode[] = { "ID_OC_SP", "ID_OC_SFU", "ID_OC_TENSOR_CORE", - "ID_OC_VP_CORE", "ID_OC_MEM", "OC_EX_SP", "OC_EX_SFU", "OC_EX_TENSOR_CORE", - "OC_EX_VP_CORE", "OC_EX_MEM", "EX_WB", "N_PIPELINE_STAGES" @@ -1328,12 +1298,6 @@ struct shader_core_config : public core_config gpgpu_operand_collector_num_in_ports_tensor_core=8; gpgpu_operand_collector_num_out_ports_tensor_core=8; - max_vp_core_latency = 512; - gpgpu_num_vp_core_units=8; - gpgpu_operand_collector_num_units_vp_core=24; - gpgpu_operand_collector_num_in_ports_vp_core=8; - gpgpu_operand_collector_num_out_ports_vp_core=8; - m_L1I_config.init(m_L1I_config.m_config_string,FuncCachePreferNone); m_L1T_config.init(m_L1T_config.m_config_string,FuncCachePreferNone); m_L1C_config.init(m_L1C_config.m_config_string,FuncCachePreferNone); @@ -1381,28 +1345,24 @@ struct shader_core_config : public core_config int gpgpu_operand_collector_num_units_sp; int gpgpu_operand_collector_num_units_sfu; int gpgpu_operand_collector_num_units_tensor_core; - int gpgpu_operand_collector_num_units_vp_core; int gpgpu_operand_collector_num_units_mem; int gpgpu_operand_collector_num_units_gen; unsigned int gpgpu_operand_collector_num_in_ports_sp; unsigned int gpgpu_operand_collector_num_in_ports_sfu; unsigned int gpgpu_operand_collector_num_in_ports_tensor_core; - unsigned int gpgpu_operand_collector_num_in_ports_vp_core; unsigned int gpgpu_operand_collector_num_in_ports_mem; unsigned int gpgpu_operand_collector_num_in_ports_gen; unsigned int gpgpu_operand_collector_num_out_ports_sp; unsigned int gpgpu_operand_collector_num_out_ports_sfu; unsigned int gpgpu_operand_collector_num_out_ports_tensor_core; - unsigned int gpgpu_operand_collector_num_out_ports_vp_core; unsigned int gpgpu_operand_collector_num_out_ports_mem; unsigned int gpgpu_operand_collector_num_out_ports_gen; int gpgpu_num_sp_units; int gpgpu_num_sfu_units; int gpgpu_num_tensor_core_units; - int gpgpu_num_vp_core_units; int gpgpu_num_mem_units; //Shader core resources @@ -1416,7 +1376,6 @@ struct shader_core_config : public core_config unsigned max_sp_latency; unsigned max_sfu_latency; unsigned max_tensor_core_latency; - unsigned max_vp_core_latency; unsigned n_simt_cores_per_cluster; unsigned n_simt_clusters; @@ -1433,7 +1392,7 @@ struct shader_core_config : public core_config struct shader_core_stats_pod { - void* shader_core_stats_pod_start[]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure + void* shader_core_stats_pod_start[0]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure unsigned long long *shader_cycles; unsigned *m_num_sim_insn; // number of scalar thread instructions committed by this shader core unsigned *m_num_sim_winsn; // number of warp instructions committed by this shader core @@ -1455,7 +1414,6 @@ struct shader_core_stats_pod { unsigned *m_num_sp_acesses; unsigned *m_num_sfu_acesses; unsigned *m_num_tensor_core_acesses; - unsigned *m_num_vp_core_acesses; unsigned *m_num_trans_acesses; unsigned *m_num_mem_acesses; unsigned *m_num_sp_committed; @@ -1463,7 +1421,6 @@ struct shader_core_stats_pod { unsigned *m_num_tlb_accesses; unsigned *m_num_sfu_committed; unsigned *m_num_tensor_core_committed; - unsigned *m_num_vp_core_committed; unsigned *m_num_mem_committed; unsigned *m_read_regfile_acesses; unsigned *m_write_regfile_acesses; @@ -1473,7 +1430,6 @@ struct shader_core_stats_pod { unsigned *m_active_sp_lanes; unsigned *m_active_sfu_lanes; unsigned *m_active_tensor_core_lanes; - unsigned *m_active_vp_core_lanes; unsigned *m_active_fu_lanes; unsigned *m_active_fu_mem_lanes; unsigned *m_n_diverge; // number of divergence occurring in this shader @@ -1546,7 +1502,6 @@ public: m_num_sp_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_sfu_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_tensor_core_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); - m_num_vp_core_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_trans_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_mem_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_sp_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); @@ -1555,12 +1510,10 @@ public: m_active_sp_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_active_sfu_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_active_tensor_core_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); - m_active_vp_core_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_active_fu_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_active_fu_mem_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_sfu_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_tensor_core_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); - m_num_vp_core_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_mem_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_read_regfile_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_write_regfile_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); diff --git a/src/gpgpu-sim/traffic_breakdown.cc b/src/gpgpu-sim/traffic_breakdown.cc index 587067f..32f0d30 100644 --- a/src/gpgpu-sim/traffic_breakdown.cc +++ b/src/gpgpu-sim/traffic_breakdown.cc @@ -46,7 +46,6 @@ std::string traffic_breakdown::classify_memfetch(class mem_fetch * mf) break; default: assert(0 && "Unknown traffic type"); } - printf("%s:Icnt:%s:Request: %x,Size%d,DataSize:%d,CntrlSize%d:\n",m_network_name.c_str(),traffic_name.c_str(),mf->get_addr(),mf->size(),mf->get_data_size(),mf->get_ctrl_size()); return traffic_name; } diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index a6d7eb4..ede9f20 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -91,9 +91,17 @@ void *gpgpu_sim_thread_sequential(void*) pthread_mutex_t g_sim_lock = PTHREAD_MUTEX_INITIALIZER; bool g_sim_active = false; bool g_sim_done = true; +bool break_limit = false; + +static void termination_callback() +{ + printf("GPGPU-Sim: *** exit detected ***\n"); + fflush(stdout); +} void *gpgpu_sim_thread_concurrent(void*) { + atexit(termination_callback); // concurrent kernel execution simulation thread do { if(g_debug_execution >= 3) { @@ -134,6 +142,7 @@ void *gpgpu_sim_thread_concurrent(void*) gpgpu_cuda_ptx_sim_main_func(*kernel); g_the_gpu->finish_functional_sim(kernel); } + //performance simulation if( g_the_gpu->active() ) { g_the_gpu->cycle(); @@ -143,17 +152,19 @@ void *gpgpu_sim_thread_concurrent(void*) if(g_the_gpu->cycle_insn_cta_max_hit()){ g_stream_manager->stop_all_running_kernels(); g_sim_done = true; + break_limit = true; } } active=g_the_gpu->active() || !g_stream_manager->empty_protected(); - } while( active ); + + } while( active && !g_sim_done); if(g_debug_execution >= 3) { printf("GPGPU-Sim: ** STOP simulation thread (no work) **\n"); fflush(stdout); } - g_the_gpu->print_stats(); if(sim_cycles) { + g_the_gpu->print_stats(); g_the_gpu->update_stats(); print_simulation_time(); } @@ -161,10 +172,14 @@ void *gpgpu_sim_thread_concurrent(void*) g_sim_active = false; pthread_mutex_unlock(&g_sim_lock); } while( !g_sim_done ); - if(g_debug_execution >= 3) { - printf("GPGPU-Sim: *** simulation thread exiting ***\n"); - fflush(stdout); + printf("GPGPU-Sim: *** simulation thread exiting ***\n"); + fflush(stdout); + + if(break_limit) { + printf("GPGPU-Sim: ** break due to reaching the maximum cycles (or instructions) **\n"); + exit(1); } + sem_post(&g_sim_signal_exit); return NULL; } @@ -178,7 +193,7 @@ void synchronize() bool done = false; do { pthread_mutex_lock(&g_sim_lock); - done = g_stream_manager->empty() && !g_sim_active; + done = ( g_stream_manager->empty() && !g_sim_active ) || g_sim_done; pthread_mutex_unlock(&g_sim_lock); } while (!done); printf("GPGPU-Sim: detected inactive GPU simulation thread\n"); diff --git a/src/stream_manager.h b/src/stream_manager.h index 222a1b2..d3a804f 100644 --- a/src/stream_manager.h +++ b/src/stream_manager.h @@ -93,7 +93,7 @@ public: m_stream=stream; m_done=false; } - stream_operation( class CUevent_st *e, struct CUstream_st *stream ) + stream_operation( struct CUevent_st *e, struct CUstream_st *stream ) { m_kernel=NULL; m_type=stream_event; @@ -172,10 +172,10 @@ private: bool m_sim_mode; kernel_info_t *m_kernel; - class CUevent_st *m_event; + struct CUevent_st *m_event; }; -class CUevent_st { +struct CUevent_st { public: CUevent_st( bool blocking ) { diff --git a/src/trace_streams.tup b/src/trace_streams.tup index c41690e..fd68a16 100644 --- a/src/trace_streams.tup +++ b/src/trace_streams.tup @@ -29,5 +29,6 @@ TS_TUP_BEGIN( trace_streams_type ) TS_TUP( WARP_SCHEDULER ), TS_TUP( SCOREBOARD ), TS_TUP( MEMORY_PARTITION_UNIT ), + TS_TUP( LIVENESS ), TS_TUP( NUM_TRACE_STREAMS ) TS_TUP_END( trace_streams_type ) |