diff options
| -rw-r--r-- | CHANGES | 16 | ||||
| -rw-r--r-- | README | 4 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 6 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 6 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.h | 2 |
5 files changed, 25 insertions, 9 deletions
@@ -3,11 +3,20 @@ Version 4.0.0 (development branch) versus 3.2.3 -Front-End: 1- Support .nc cache modifier and __ldg function to access the read-only L1D cache 2- Partially-support some SASS_60 in the PTXP_PLUS (not completed yet) --GPU Core: +3- Added parsing support for wmma.load,wmma.mma and wmma.store ptx instructions +4- Implmented cudaLaunchKernel for CUTLASS library +-GPU Core Functional Simulation +1- Implemented bfi and prmt instruction +2- Implemented wmma.load and wmma.store supporting all the layout configuration for TITANV GPU +3- Implemented wmma.mma instructions supporting all of its 32 configuration for TITANV GPU +4- debug support for wmma instruction using debug_tensorcore flag +-GPU Core Performance Simulation: 1- Fermi/Pascal coalescer: coalescing on 32-bytes sectors. 2- Adding separate dp unit pipeline. 3- diff dual issue: allow scheduler to issue diff insts at a time 4- Fair memory issue from multiple schedulers. +5- Added tensorcore unit pipeline. +6- Corrected the bug in vector load instruction -Cache System: 1- Sector L1/L2 cache 2- Fetch-on-write and lazy-fetch-on-read write allocation policy. @@ -23,12 +32,15 @@ Version 4.0.0 (development branch) versus 3.2.3 1- Adding more detailed cache statistics to define and analyze cache bottlenecks. 2- Adding more detailed memory statistics (BLP, RBL, etc) to define and analyze memory bottlenecks. 3- Addig new system stats: gpu occupancy, L2BW, etc +-Library: +1 Enabled CUTLASS Library on GPGPU-Sim +-Regression: +1- Added TensorCore Regression Kernel -Configs: Adding the Pascal and Volta config files that has been correlated against real hardware. See the correlation website here: https://engineering.purdue.edu/tgrogers/group/correlator.html - Version 3.2.3+edits (development branch) versus 3.2.3 - Support for running regression tests using Travis - Support added for CUDA dynamic parallelism (courtesy of Jin Wang from Georgia Tech) @@ -24,6 +24,10 @@ Mahmoud Khairy, Jain Akshay, Tor Aamodt, Timothy G Rogers, Exploring Modern GPU Memory System Design Challenges through Accurate Modeling, arXiv:1810.07269, https://arxiv.org/abs/1810.07269 +If you use the tensorcore in GPGPU-Sim or CUTLASS Library in your research +please cite: + add the arxiv link here + If you use the GPUWattch energy model in your research, please cite: Jingwen Leng, Tayler Hetherington, Ahmed ElTantawy, Syed Gilani, Nam Sung Kim, diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index c8351da..7532c01 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -12,6 +12,7 @@ -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 70 +-gpgpu_tensor_core_avail 1 # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 @@ -41,14 +42,13 @@ -gpgpu_simd_model 1 # Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE ## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12 +-gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12,1,1 -gpgpu_num_sp_units 4 -gpgpu_num_sfu_units 4 -gpgpu_num_dp_units 4 - # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" # All Div operations are executed on SFU unit diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 0c0707c..cd2ed26 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1179,7 +1179,7 @@ void two_level_active_scheduler::order_warps() for ( std::vector< shd_warp_t* >::iterator iter = m_next_cycle_prioritized_warps.begin(); iter != m_next_cycle_prioritized_warps.end(); ) { bool waiting = (*iter)->waiting(); - for (int i=0; i<4; i++){ + for (int i=0; i<MAX_INPUT_VALUES; i++){ const warp_inst_t* inst = (*iter)->ibuffer_next_inst(); //Is the instruction waiting on a long operation? if ( inst && inst->in[i] > 0 && this->m_scoreboard->islongop((*iter)->get_warp_id(), inst->in[i])){ @@ -1599,7 +1599,7 @@ void ldst_unit::L1_latency_queue_cycle() assert( !read_sent ); l1_latency_queue[0] = NULL; if ( mf_next->get_inst().is_load() ) { - for ( unsigned r=0; r < 4; r++) + for ( unsigned r=0; r < MAX_OUTPUT_VALUES; r++) if (mf_next->get_inst().out[r] > 0) { assert(m_pending_writes[mf_next->get_inst().warp_id()][mf_next->get_inst().out[r]]>0); @@ -2146,7 +2146,7 @@ void ldst_unit::issue( register_set ®_set ) if (inst->is_load() and inst->space.get_type() != shared_space) { unsigned warp_id = inst->warp_id(); unsigned n_accesses = inst->accessq_count(); - for (unsigned r = 0; r < 4; r++) { + for (unsigned r = 0; r < MAX_OUTPUT_VALUES; r++) { unsigned reg_id = inst->out[r]; if (reg_id > 0) { m_pending_writes[warp_id][reg_id] += n_accesses; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 437506c..3542120 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1360,7 +1360,7 @@ struct shader_core_config : public core_config max_sp_latency = 32; max_tensor_core_latency = 64; - gpgpu_num_tensor_core_units=8; + gpgpu_num_tensor_core_units=4;//It will be (#TENSORCORE INSIDE SM)/2 (One warp is allocated to 2 Tensor Core) gpgpu_operand_collector_num_units_tensor_core=24; gpgpu_operand_collector_num_in_ports_tensor_core=8; gpgpu_operand_collector_num_out_ports_tensor_core=8; |