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-rw-r--r--configs/tested-cfgs/SM2_GTX480/gpgpusim.config6
-rw-r--r--configs/tested-cfgs/SM6_TITANX/gpgpusim.config6
-rw-r--r--configs/tested-cfgs/SM7_TITANV/gpgpusim.config6
-rw-r--r--libopencl/opencl_runtime_api.cc54
-rw-r--r--src/cuda-sim/cuda-sim.cc29
-rw-r--r--src/cuda-sim/ptx.y18
-rw-r--r--src/gpgpu-sim/shader.cc9
7 files changed, 100 insertions, 28 deletions
diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
index cf3627b..7ff836a 100644
--- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
@@ -46,9 +46,9 @@
-gpgpu_num_dp_units 0
# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,2,2,1,8
+# "ADD,MAX,MUL,MAD,DIV,SHFL"
+-ptx_opcode_latency_int 4,13,4,5,145,32
+-ptx_opcode_initiation_int 1,2,2,1,8,4
-ptx_opcode_latency_fp 4,13,4,5,39
-ptx_opcode_initiation_fp 1,2,1,1,4
-ptx_opcode_latency_dp 8,19,8,8,330
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index a94b66a..ba37c0c 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -56,11 +56,11 @@
# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
+# "ADD,MAX,MUL,MAD,DIV,SHFL"
# All Div operations are executed on SFU unit
# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_int 4,13,4,5,145,32
+-ptx_opcode_initiation_int 1,1,1,1,4,4
-ptx_opcode_latency_fp 4,13,4,5,39
-ptx_opcode_initiation_fp 1,2,1,1,4
-ptx_opcode_latency_dp 8,19,8,8,330
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index ebd442f..f2301e8 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -66,10 +66,10 @@
# Instruction latencies and initiation intervals
# "ADD,MAX,MUL,MAD,DIV"
# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from
+# Throughput (initiation latency except shfl) are adopted from
# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_int 4,13,4,5,145,32
+-ptx_opcode_initiation_int 2,2,2,2,8,4
-ptx_opcode_latency_fp 4,13,4,5,39
-ptx_opcode_initiation_fp 2,2,2,2,4
-ptx_opcode_latency_dp 8,19,8,8,330
diff --git a/libopencl/opencl_runtime_api.cc b/libopencl/opencl_runtime_api.cc
index 97a54d8..752bfdf 100644
--- a/libopencl/opencl_runtime_api.cc
+++ b/libopencl/opencl_runtime_api.cc
@@ -263,15 +263,27 @@ void _cl_kernel::SetKernelArg(
cl_int _cl_kernel::bind_args( gpgpu_ptx_sim_arg_list_t &arg_list )
{
+ size_t offset = 0;
+
assert( arg_list.empty() );
unsigned k=0;
std::map<unsigned, arg_info>::iterator i;
for( i = m_args.begin(); i!=m_args.end(); i++ ) {
if( i->first != k )
return CL_INVALID_KERNEL_ARGS;
+
arg_info arg = i->second;
- gpgpu_ptx_sim_arg param( arg.m_arg_value, arg.m_arg_size, 0);
+ const symbol *sym = m_kernel_impl->get_arg(i->first);
+ const type_info_key &t = sym->type()->get_key();
+
+ int align = (t.get_alignment_spec() == -1) ? arg.m_arg_size : t.get_alignment_spec();
+ if( offset % align )
+ offset += (align - (offset % align));
+
+ gpgpu_ptx_sim_arg param( arg.m_arg_value, arg.m_arg_size, offset );
arg_list.push_front( param );
+
+ offset += arg.m_arg_size;
k++;
}
return CL_SUCCESS;
@@ -950,6 +962,17 @@ clEnqueueNDRangeKernel(cl_command_queue command_queue,
gpgpu_ptx_sim_memcpy_symbol( "%_global_block_offset", zeros, 3 * sizeof(int), 0, 1, gpu );
}
kernel_info_t *grid = gpgpu_opencl_ptx_sim_init_grid(kernel->get_implementation(),params,GridDim,BlockDim,gpu);
+
+ //do dynamic PDOM analysis for performance simulation scenario
+ std::string kname = grid->name();
+ function_info *kernel_func_info = grid->entry();
+ if (kernel_func_info->is_pdom_set()) {
+ printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", kname.c_str() );
+ } else {
+ printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", kname.c_str() );
+ kernel_func_info->do_pdom();
+ kernel_func_info->set_pdom();
+ }
if ( g_ptx_sim_mode )
gpgpu_opencl_ptx_sim_main_func( grid );
else
@@ -1256,6 +1279,35 @@ clGetProgramInfo(cl_program program,
}
extern CL_API_ENTRY cl_int CL_API_CALL
+clGetProgramBuildInfo (cl_program program,
+ cl_device_id device,
+ cl_program_build_info param_name,
+ size_t param_value_size,
+ void * param_value,
+ size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0
+{
+ char *buf = (char*)param_value;
+
+ switch( param_name ) {
+ case CL_PROGRAM_BUILD_STATUS:
+ CL_CASE( cl_build_status, CL_BUILD_SUCCESS );
+ break;
+ case CL_PROGRAM_BUILD_OPTIONS:
+ case CL_PROGRAM_BUILD_LOG:
+ CL_STRING_CASE( "" );
+ break;
+ case CL_PROGRAM_BINARY_TYPE:
+ CL_CASE( cl_program_binary_type, CL_PROGRAM_BINARY_TYPE_EXECUTABLE );
+ break;
+ default:
+ return CL_INVALID_VALUE;
+ break;
+ }
+
+ return CL_SUCCESS;
+}
+
+extern CL_API_ENTRY cl_int CL_API_CALL
clEnqueueCopyBuffer(cl_command_queue command_queue,
cl_mem src_buffer,
cl_mem dst_buffer,
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index f7bb9cc..7376cc6 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -71,9 +71,9 @@ unsigned cdp_latency[5];
void ptx_opcocde_latency_options (option_parser_t opp) {
option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int,
- "Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV>"
- "Default 1,1,19,25,145",
- "1,1,19,25,145");
+ "Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,SHFL>"
+ "Default 1,1,19,25,145,32",
+ "1,1,19,25,145,32");
option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp,
"Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>"
"Default 1,1,1,1,30",
@@ -91,9 +91,9 @@ void ptx_opcocde_latency_options (option_parser_t opp) {
"Default 64",
"64");
option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int,
- "Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV>"
- "Default 1,1,4,4,32",
- "1,1,4,4,32");
+ "Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,SHFL>"
+ "Default 1,1,4,4,32,4",
+ "1,1,4,4,32,4");
option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp,
"Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>"
"Default 1,1,1,1,5",
@@ -648,12 +648,12 @@ void ptx_instruction::set_bar_type()
void ptx_instruction::set_opcode_and_latency()
{
- unsigned int_latency[5];
+ unsigned int_latency[6];
unsigned fp_latency[5];
unsigned dp_latency[5];
unsigned sfu_latency;
unsigned tensor_latency;
- unsigned int_init[5];
+ unsigned int_init[6];
unsigned fp_init[5];
unsigned dp_init[5];
unsigned sfu_init;
@@ -664,10 +664,11 @@ void ptx_instruction::set_opcode_and_latency()
* [2] MUL
* [3] MAD
* [4] DIV
+ * [5] SHFL
*/
- sscanf(opcode_latency_int, "%u,%u,%u,%u,%u",
+ sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u",
&int_latency[0],&int_latency[1],&int_latency[2],
- &int_latency[3],&int_latency[4]);
+ &int_latency[3],&int_latency[4],&int_latency[5]);
sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u",
&fp_latency[0],&fp_latency[1],&fp_latency[2],
&fp_latency[3],&fp_latency[4]);
@@ -678,9 +679,9 @@ void ptx_instruction::set_opcode_and_latency()
&sfu_latency);
sscanf(opcode_latency_tensor, "%u",
&tensor_latency);
- sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u",
+ sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u",
&int_init[0],&int_init[1],&int_init[2],
- &int_init[3],&int_init[4]);
+ &int_init[3],&int_init[4],&int_init[5]);
sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u",
&fp_init[0],&fp_init[1],&fp_init[2],
&fp_init[3],&fp_init[4]);
@@ -873,8 +874,8 @@ void ptx_instruction::set_opcode_and_latency()
op=TENSOR_CORE_OP;
break;
case SHFL_OP:
- latency = 32;
- initiation_interval = 4;
+ latency = int_latency[5];
+ initiation_interval = int_init[5];
break;
default:
break;
diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y
index 45392fb..260564f 100644
--- a/src/cuda-sim/ptx.y
+++ b/src/cuda-sim/ptx.y
@@ -287,6 +287,7 @@ ptr_align_spec: ALIGN_DIRECTIVE INT_OPERAND
statement_block: LEFT_BRACE statement_list RIGHT_BRACE
statement_list: directive_statement { add_directive(); }
+ | statement_list prototype_block {printf("Prototype statement detected. WARNING: this is not supported yet on GPGPU-SIM\n"); }
| instruction_statement { add_instruction(); }
| statement_list directive_statement { add_directive(); }
| statement_list instruction_statement { add_instruction(); }
@@ -403,6 +404,23 @@ initializer_list: LEFT_BRACE literal_list RIGHT_BRACE { add_array_initializer();
literal_list: literal_operand
| literal_list COMMA literal_operand;
+// TODO: This is currently hardcoded to handle and ignore one specific case
+// that all prototype statements follow in the PTX from Pytorch. As a
+// workaround, this parses and ignores both the prototype declaration
+// and calling of the prototype (which conveniently comes right after the
+// declaration for all cases.) This should be changed to handle both
+// declaring the prototype, and actually calling it.
+prototype_block: prototype_decl prototype_call
+
+prototype_decl: IDENTIFIER COLON CALLPROTOTYPE_DIRECTIVE LEFT_PAREN prototype_param RIGHT_PAREN IDENTIFIER LEFT_PAREN prototype_param RIGHT_PAREN SEMI_COLON
+
+prototype_call: OPCODE LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA operand COMMA LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA IDENTIFIER SEMI_COLON
+ | OPCODE IDENTIFIER COMMA LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA IDENTIFIER SEMI_COLON
+
+prototype_param: /* empty */
+ | PARAM_DIRECTIVE B64_TYPE IDENTIFIER
+ | PARAM_DIRECTIVE B32_TYPE IDENTIFIER
+
instruction_statement: instruction SEMI_COLON
| IDENTIFIER COLON { add_label($1); }
| pred_spec instruction SEMI_COLON;
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 007ad42..96ba385 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -3002,7 +3002,7 @@ void shader_core_config::set_pipeline_latency() {
//calculate the max latency based on the input
- unsigned int_latency[5];
+ unsigned int_latency[6];
unsigned fp_latency[5];
unsigned dp_latency[5];
unsigned sfu_latency;
@@ -3014,10 +3014,11 @@ void shader_core_config::set_pipeline_latency() {
* [2] MUL
* [3] MAD
* [4] DIV
+ * [5] SHFL
*/
- sscanf(opcode_latency_int, "%u,%u,%u,%u,%u",
+ sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u",
&int_latency[0],&int_latency[1],&int_latency[2],
- &int_latency[3],&int_latency[4]);
+ &int_latency[3],&int_latency[4],&int_latency[5]);
sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u",
&fp_latency[0],&fp_latency[1],&fp_latency[2],
&fp_latency[3],&fp_latency[4]);
@@ -3034,7 +3035,7 @@ void shader_core_config::set_pipeline_latency() {
max_sfu_latency = std::max(dp_latency[4],sfu_latency);
//assume that the max operation has the max latency
max_sp_latency = fp_latency[1];
- max_int_latency = int_latency[1];
+ max_int_latency = std::max(int_latency[1],int_latency[5]);
max_dp_latency = dp_latency[1];
max_tensor_core_latency = tensor_latency;
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 00:00:26 +0000