diff options
| -rw-r--r-- | CHANGES | 1 | ||||
| -rw-r--r-- | Makefile | 1 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM2_GTX480/gpgpusim.config | 6 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 8 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 6 | ||||
| -rw-r--r-- | libcuda/cuda_api.h | 3 | ||||
| -rw-r--r-- | libcuda/cuda_runtime_api.cc | 54 | ||||
| -rw-r--r-- | libopencl/opencl_runtime_api.cc | 54 | ||||
| -rw-r--r-- | linux-so-version.txt | 2 | ||||
| -rw-r--r-- | setup_environment | 5 | ||||
| -rw-r--r-- | src/cuda-sim/cuda-sim.cc | 29 | ||||
| -rw-r--r-- | src/cuda-sim/ptx.y | 18 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 9 |
13 files changed, 162 insertions, 34 deletions
@@ -37,6 +37,7 @@ Version 4.0.0 (development branch) versus 3.2.3 3- Addig new system stats: gpu occupancy, L2BW, etc -Library: 1 Enabled CUTLASS Library on GPGPU-Sim +2 Enabled CUDA 10 -Regression: 1- Added TensorCore Regression Kernel -Configs: @@ -164,6 +164,7 @@ $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib if [ ! -f $(SIM_LIB_DIR)/libcudart.so.9.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.9.0; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.9.1 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.9.1; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.9.2 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.9.2; fi + if [ ! -f $(SIM_LIB_DIR)/libcudart.so.10.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.10.0; fi $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib g++ -dynamiclib -Wl,-headerpad_max_install_names,-undefined,dynamic_lookup,-compatibility_version,1.1,-current_version,1.1\ diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config index cf3627b..7ff836a 100644 --- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config +++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config @@ -46,9 +46,9 @@ -gpgpu_num_dp_units 0 # Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,2,2,1,8 +# "ADD,MAX,MUL,MAD,DIV,SHFL" +-ptx_opcode_latency_int 4,13,4,5,145,32 +-ptx_opcode_initiation_int 1,2,2,1,8,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index 2fe898a..ba37c0c 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -56,11 +56,11 @@ # Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" +# "ADD,MAX,MUL,MAD,DIV,SHFL" # All Div operations are executed on SFU unit # Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_int 4,13,4,5,145,32 +-ptx_opcode_initiation_int 1,1,1,1,4,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 @@ -135,7 +135,7 @@ # interconnection -network_mode 1 --inter_config_file config_fermi_islip.icnt +-inter_config_file config_pascal_islip.icnt # memory partition latency config -rop_latency 120 diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index ebd442f..f2301e8 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -66,10 +66,10 @@ # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" # All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from +# Throughput (initiation latency except shfl) are adopted from # http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_int 4,13,4,5,145,32 +-ptx_opcode_initiation_int 2,2,2,2,8,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 2,2,2,2,4 -ptx_opcode_latency_dp 8,19,8,8,330 diff --git a/libcuda/cuda_api.h b/libcuda/cuda_api.h index 3808e8a..0ded242 100644 --- a/libcuda/cuda_api.h +++ b/libcuda/cuda_api.h @@ -234,10 +234,11 @@ typedef struct CUgraphicsResource_st *CUgraphicsResource; /**< CUDA graphics int typedef unsigned long long CUtexObject; /**< An opaque value that represents a CUDA texture object */ typedef unsigned long long CUsurfObject; /**< An opaque value that represents a CUDA surface object */ +#if CUDART_VERSION < 10000 typedef struct CUuuid_st { /**< CUDA definition of UUID */ char bytes[16]; } CUuuid; - +#endif // #if CUDART_VERSION < 10000 #if __CUDA_API_VERSION >= 4010 diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 6a7826e..a6edf9a 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1448,6 +1448,50 @@ __host__ cudaError_t CUDARTAPI cudaConfigureCall(dim3 gridDim, dim3 blockDim, si return g_last_cudaError = cudaSuccess; } + +#if CUDART_VERSION >= 10000 +/* +* CUDA 10 requires a new CUDA kernel launch sequence +* A call to __cudaPushCallConfiguration() preceeds any call to cudaLaunchKernel() +* __cudaPushCallConfiguration is undocumented in the API but it simply sets up a buffer with the arguments which is accessed in cudaLaunchKernel() +* __cudaPopCallConfiguration is undocumented in the API but it simply pops the configuration set in cudaLaunchKernel() +* +* pushing more than 1 configuration without popping is currently not implemented in GPGPU-Sim and will result in an assert error +*/ +namespace g_cudaPushArgsBuffer +{ + bool g_is_initialized = false; + dim3 g_gridDim; + dim3 g_blockDim; + size_t g_sharedMem; + cudaStream_t g_stream; +} + +__host__ cudaError_t CUDARTAPI __cudaPushCallConfiguration(dim3 gridDim, dim3 blockDim, size_t sharedMem, cudaStream_t stream) +{ + assert(g_cudaPushArgsBuffer::g_is_initialized == false); + printf("Pushing cuda call configuration \n"); + g_cudaPushArgsBuffer::g_is_initialized = true; + g_cudaPushArgsBuffer::g_gridDim = gridDim; + g_cudaPushArgsBuffer::g_blockDim = blockDim; + g_cudaPushArgsBuffer::g_sharedMem = sharedMem; + g_cudaPushArgsBuffer::g_stream = stream; + + return cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI __cudaPopCallConfiguration() +{ + printf("Inside __cudaPopCallConfiguration\n"); + assert(g_cudaPushArgsBuffer::g_is_initialized == true); + printf("Poping cuda call configuration \n"); + g_cudaPushArgsBuffer::g_is_initialized = false; + return cudaSuccess; +} + +#endif // #if CUDART_VERSION >= 10000 + + __host__ cudaError_t CUDARTAPI cudaSetupArgument(const void *arg, size_t size, size_t offset) { if(g_debug_execution >= 3){ @@ -1551,8 +1595,14 @@ __host__ cudaError_t CUDARTAPI cudaLaunchKernel ( const char* hostFun, dim3 grid } CUctx_st *context = GPGPUSim_Context(); function_info *entry = context->get_kernel(hostFun); - - cudaConfigureCall(gridDim, blockDim, sharedMem, stream); + +#if CUDART_VERSION >= 10000 + assert(g_cudaPushArgsBuffer::g_is_initialized == false); + cudaConfigureCall(g_cudaPushArgsBuffer::g_gridDim, g_cudaPushArgsBuffer::g_blockDim, g_cudaPushArgsBuffer::g_sharedMem, g_cudaPushArgsBuffer::g_stream); +#else + cudaConfigureCall(gridDim, blockDim, sharedMem, stream); +#endif // #if CUDART_VERSION >= 10000 + for(unsigned i = 0; i < entry->num_args(); i++){ std::pair<size_t, unsigned> p = entry->get_param_config(i); cudaSetupArgument(args[i], p.first, p.second); diff --git a/libopencl/opencl_runtime_api.cc b/libopencl/opencl_runtime_api.cc index 97a54d8..752bfdf 100644 --- a/libopencl/opencl_runtime_api.cc +++ b/libopencl/opencl_runtime_api.cc @@ -263,15 +263,27 @@ void _cl_kernel::SetKernelArg( cl_int _cl_kernel::bind_args( gpgpu_ptx_sim_arg_list_t &arg_list ) { + size_t offset = 0; + assert( arg_list.empty() ); unsigned k=0; std::map<unsigned, arg_info>::iterator i; for( i = m_args.begin(); i!=m_args.end(); i++ ) { if( i->first != k ) return CL_INVALID_KERNEL_ARGS; + arg_info arg = i->second; - gpgpu_ptx_sim_arg param( arg.m_arg_value, arg.m_arg_size, 0); + const symbol *sym = m_kernel_impl->get_arg(i->first); + const type_info_key &t = sym->type()->get_key(); + + int align = (t.get_alignment_spec() == -1) ? arg.m_arg_size : t.get_alignment_spec(); + if( offset % align ) + offset += (align - (offset % align)); + + gpgpu_ptx_sim_arg param( arg.m_arg_value, arg.m_arg_size, offset ); arg_list.push_front( param ); + + offset += arg.m_arg_size; k++; } return CL_SUCCESS; @@ -950,6 +962,17 @@ clEnqueueNDRangeKernel(cl_command_queue command_queue, gpgpu_ptx_sim_memcpy_symbol( "%_global_block_offset", zeros, 3 * sizeof(int), 0, 1, gpu ); } kernel_info_t *grid = gpgpu_opencl_ptx_sim_init_grid(kernel->get_implementation(),params,GridDim,BlockDim,gpu); + + //do dynamic PDOM analysis for performance simulation scenario + std::string kname = grid->name(); + function_info *kernel_func_info = grid->entry(); + if (kernel_func_info->is_pdom_set()) { + printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", kname.c_str() ); + } else { + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", kname.c_str() ); + kernel_func_info->do_pdom(); + kernel_func_info->set_pdom(); + } if ( g_ptx_sim_mode ) gpgpu_opencl_ptx_sim_main_func( grid ); else @@ -1256,6 +1279,35 @@ clGetProgramInfo(cl_program program, } extern CL_API_ENTRY cl_int CL_API_CALL +clGetProgramBuildInfo (cl_program program, + cl_device_id device, + cl_program_build_info param_name, + size_t param_value_size, + void * param_value, + size_t * param_value_size_ret) CL_API_SUFFIX__VERSION_1_0 +{ + char *buf = (char*)param_value; + + switch( param_name ) { + case CL_PROGRAM_BUILD_STATUS: + CL_CASE( cl_build_status, CL_BUILD_SUCCESS ); + break; + case CL_PROGRAM_BUILD_OPTIONS: + case CL_PROGRAM_BUILD_LOG: + CL_STRING_CASE( "" ); + break; + case CL_PROGRAM_BINARY_TYPE: + CL_CASE( cl_program_binary_type, CL_PROGRAM_BINARY_TYPE_EXECUTABLE ); + break; + default: + return CL_INVALID_VALUE; + break; + } + + return CL_SUCCESS; +} + +extern CL_API_ENTRY cl_int CL_API_CALL clEnqueueCopyBuffer(cl_command_queue command_queue, cl_mem src_buffer, cl_mem dst_buffer, diff --git a/linux-so-version.txt b/linux-so-version.txt index a7c2d3c..357c6cd 100644 --- a/linux-so-version.txt +++ b/linux-so-version.txt @@ -6,3 +6,5 @@ libcudart.so.9.2{ }; libcuda.so.1{ }; +libcudart.so.10.0{ +};
\ No newline at end of file diff --git a/setup_environment b/setup_environment index b420584..154dea0 100644 --- a/setup_environment +++ b/setup_environment @@ -51,9 +51,10 @@ CC_VERSION=`gcc --version | head -1 | awk '{for(i=1;i<=NF;i++){ if(match($i,/^[0 CUDA_VERSION_STRING=`$CUDA_INSTALL_PATH/bin/nvcc --version | awk '/release/ {print $5;}' | sed 's/,//'`; export CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("%02u%02u", 10*int($1), 10*$2);}'` -if [ $CUDA_VERSION_NUMBER -gt 9100 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then +if [ $CUDA_VERSION_NUMBER -gt 10000 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then echo "ERROR ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; - return + echo $CUDA_VERSION_NUMBER + return fi if [ $CUDA_VERSION_NUMBER -ge 6000 ]; then diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index f7bb9cc..7376cc6 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -71,9 +71,9 @@ unsigned cdp_latency[5]; void ptx_opcocde_latency_options (option_parser_t opp) { option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, - "Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV>" - "Default 1,1,19,25,145", - "1,1,19,25,145"); + "Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,SHFL>" + "Default 1,1,19,25,145,32", + "1,1,19,25,145,32"); option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp, "Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>" "Default 1,1,1,1,30", @@ -91,9 +91,9 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Default 64", "64"); option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, - "Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV>" - "Default 1,1,4,4,32", - "1,1,4,4,32"); + "Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,SHFL>" + "Default 1,1,4,4,32,4", + "1,1,4,4,32,4"); option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp, "Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>" "Default 1,1,1,1,5", @@ -648,12 +648,12 @@ void ptx_instruction::set_bar_type() void ptx_instruction::set_opcode_and_latency() { - unsigned int_latency[5]; + unsigned int_latency[6]; unsigned fp_latency[5]; unsigned dp_latency[5]; unsigned sfu_latency; unsigned tensor_latency; - unsigned int_init[5]; + unsigned int_init[6]; unsigned fp_init[5]; unsigned dp_init[5]; unsigned sfu_init; @@ -664,10 +664,11 @@ void ptx_instruction::set_opcode_and_latency() * [2] MUL * [3] MAD * [4] DIV + * [5] SHFL */ - sscanf(opcode_latency_int, "%u,%u,%u,%u,%u", + sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u", &int_latency[0],&int_latency[1],&int_latency[2], - &int_latency[3],&int_latency[4]); + &int_latency[3],&int_latency[4],&int_latency[5]); sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u", &fp_latency[0],&fp_latency[1],&fp_latency[2], &fp_latency[3],&fp_latency[4]); @@ -678,9 +679,9 @@ void ptx_instruction::set_opcode_and_latency() &sfu_latency); sscanf(opcode_latency_tensor, "%u", &tensor_latency); - sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u", + sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u", &int_init[0],&int_init[1],&int_init[2], - &int_init[3],&int_init[4]); + &int_init[3],&int_init[4],&int_init[5]); sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u", &fp_init[0],&fp_init[1],&fp_init[2], &fp_init[3],&fp_init[4]); @@ -873,8 +874,8 @@ void ptx_instruction::set_opcode_and_latency() op=TENSOR_CORE_OP; break; case SHFL_OP: - latency = 32; - initiation_interval = 4; + latency = int_latency[5]; + initiation_interval = int_init[5]; break; default: break; diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 45392fb..260564f 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -287,6 +287,7 @@ ptr_align_spec: ALIGN_DIRECTIVE INT_OPERAND statement_block: LEFT_BRACE statement_list RIGHT_BRACE statement_list: directive_statement { add_directive(); } + | statement_list prototype_block {printf("Prototype statement detected. WARNING: this is not supported yet on GPGPU-SIM\n"); } | instruction_statement { add_instruction(); } | statement_list directive_statement { add_directive(); } | statement_list instruction_statement { add_instruction(); } @@ -403,6 +404,23 @@ initializer_list: LEFT_BRACE literal_list RIGHT_BRACE { add_array_initializer(); literal_list: literal_operand | literal_list COMMA literal_operand; +// TODO: This is currently hardcoded to handle and ignore one specific case +// that all prototype statements follow in the PTX from Pytorch. As a +// workaround, this parses and ignores both the prototype declaration +// and calling of the prototype (which conveniently comes right after the +// declaration for all cases.) This should be changed to handle both +// declaring the prototype, and actually calling it. +prototype_block: prototype_decl prototype_call + +prototype_decl: IDENTIFIER COLON CALLPROTOTYPE_DIRECTIVE LEFT_PAREN prototype_param RIGHT_PAREN IDENTIFIER LEFT_PAREN prototype_param RIGHT_PAREN SEMI_COLON + +prototype_call: OPCODE LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA operand COMMA LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA IDENTIFIER SEMI_COLON + | OPCODE IDENTIFIER COMMA LEFT_PAREN IDENTIFIER RIGHT_PAREN COMMA IDENTIFIER SEMI_COLON + +prototype_param: /* empty */ + | PARAM_DIRECTIVE B64_TYPE IDENTIFIER + | PARAM_DIRECTIVE B32_TYPE IDENTIFIER + instruction_statement: instruction SEMI_COLON | IDENTIFIER COLON { add_label($1); } | pred_spec instruction SEMI_COLON; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 007ad42..96ba385 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3002,7 +3002,7 @@ void shader_core_config::set_pipeline_latency() { //calculate the max latency based on the input - unsigned int_latency[5]; + unsigned int_latency[6]; unsigned fp_latency[5]; unsigned dp_latency[5]; unsigned sfu_latency; @@ -3014,10 +3014,11 @@ void shader_core_config::set_pipeline_latency() { * [2] MUL * [3] MAD * [4] DIV + * [5] SHFL */ - sscanf(opcode_latency_int, "%u,%u,%u,%u,%u", + sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u", &int_latency[0],&int_latency[1],&int_latency[2], - &int_latency[3],&int_latency[4]); + &int_latency[3],&int_latency[4],&int_latency[5]); sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u", &fp_latency[0],&fp_latency[1],&fp_latency[2], &fp_latency[3],&fp_latency[4]); @@ -3034,7 +3035,7 @@ void shader_core_config::set_pipeline_latency() { max_sfu_latency = std::max(dp_latency[4],sfu_latency); //assume that the max operation has the max latency max_sp_latency = fp_latency[1]; - max_int_latency = int_latency[1]; + max_int_latency = std::max(int_latency[1],int_latency[5]); max_dp_latency = dp_latency[1]; max_tensor_core_latency = tensor_latency; |