diff options
Diffstat (limited to 'bsmad_test/d.log')
| -rw-r--r-- | bsmad_test/d.log | 3049 |
1 files changed, 0 insertions, 3049 deletions
diff --git a/bsmad_test/d.log b/bsmad_test/d.log deleted file mode 100644 index 50ba43f..0000000 --- a/bsmad_test/d.log +++ /dev/null @@ -1,3049 +0,0 @@ - - - *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** - - -GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: - 1=functional simulation only, 0=detailed performance simulator) -GPGPU-Sim: Configuration options: - --network_mode 1 # Interconnection network mode --inter_config_file config_fermi_islip.icnt # Interconnection network config file --gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries --gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] --gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus --gpgpu_ptx_force_max_capability 60 # Force maximum compute capability --gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file --gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file --gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output --gpgpu_simd_model 1 # 1 = post-dominator --gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>} --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>} --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none} --gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) --gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) --n_regfile_gating_group 4 # group of lanes that should be read/written together) --gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations --gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations --gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) --gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) --gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) --gpgpu_n_clusters 28 # number of processing clusters --gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster --gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer --gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer --gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) --gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) --gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) --gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check --gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from --gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from --gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) --gpgpu_num_reg_banks 32 # Number of register banks (default = 8) --gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) --gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) --gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) --gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) --gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) --gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) --gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) --gpgpu_num_sched_per_core 2 # Number of warp schedulers per core --gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler --gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) --gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_num_sp_units 4 # Number of SP units (default=1) --gpgpu_num_sfu_units 1 # Number of SF units (default=1) --gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything --gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto --gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) --gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) --gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i --l2_ideal 0 # Use a ideal L2 cache that always hit --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>} --gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only --gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu --gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module --gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller --gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs --gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip --gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip --gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) --gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) --dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) --gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} --rop_latency 120 # ROP queue latency (default 85) --dram_latency 100 # DRAM latency (default 30) --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>} --gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address --gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits --gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file --power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) --power_per_cycle_dump 0 # Dump detailed power output each cycle --power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) --power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) --steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) --steady_state_definition 8:4 # allowed deviation:number of samples --gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) --gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) --gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>} --liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) --gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call --gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call --gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) --gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) --gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) --gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>} --gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU --gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger --visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) --visualizer_outputfile NULL # Specifies the output log file for visualizer --visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) --trace_enabled 0 # Turn on traces --trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none --trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 --trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) --enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) --ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. --gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 --gpgpu_cdp_enabled 0 # Turn on CDP --save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx --keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs --gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file --ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Presicion,BSMAD_lane_width>Default 1,1,19,25,145,1,4 --ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30 --ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335 --ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Precision,BSMAD_lane_width>Default 1,1,4,4,32,1,1 --ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5 --ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130 --cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600 -DRAM Timing Options: -nbk 16 # number of banks -CCD 2 # column to column delay -RRD 6 # minimal delay between activation of rows in different banks -RCD 12 # row to column delay -RAS 28 # time needed to activate row -RP 12 # time needed to precharge (deactivate) row -RC 40 # row cycle time -CDLR 5 # switching from write to read (changes tWTR) -WR 12 # last data-in to row precharge -CL 12 # CAS latency -WL 4 # Write latency -nbkgrp 1 # number of bank groups -CCDL 0 # column to column delay between accesses to different bank groups -RTPL 0 # read to precharge delay between accesses to different bank groups -Total number of memory sub partition = 22 -addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 -addr_dec_mask[BK] = 0000000000007080 high:15 low:7 -addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 -addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 -addr_dec_mask[BURST] = 000000000000001f high:5 low:0 -sub_partition_id_mask = 0000000000000080 -GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 -GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 -*** Initializing Memory Statistics *** -GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) -GPGPU-Sim uArch: Memory nodes ID start from index: 28 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 -GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) -GPGPU-Sim uArch: Memory nodes start from ID: 28 -GPGPU-Sim uArch: 0 1 2 3 4 5 6 -GPGPU-Sim uArch: 7 8 9 10 11 12 13 -GPGPU-Sim uArch: 14 15 16 17 18 19 20 -GPGPU-Sim uArch: 21 22 23 24 25 26 27 -GPGPU-Sim uArch: 28 29 30 31 32 33 34 -GPGPU-Sim uArch: 35 36 37 38 39 40 41 -GPGPU-Sim uArch: 42 43 44 45 46 47 48 -GPGPU-Sim uArch: 49 -e1ffbb239b1e632822e743b7e0c60b46 /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad -GPGPU-Sim uArch: performance model initialization complete. -GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default -self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad -Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " -Parsing file _cuobjdump_complete_output_8Ypfya -######### cuobjdump parser ######## -## Adding new section PTX -Adding ptx filename: _cuobjdump_1.ptx -Adding arch: sm_50 -Adding identifier: default -Done parsing!!! -GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 -WARNING: No guarantee that PTX will be parsed for SM version 50 -GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. -GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... -GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... -GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ -GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. -BEGINNING CUSTOM PTX. -ENDING CUSTOM PTX. -GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. -GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... -GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... -GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; -GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; -GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ -GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. -GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx -Adding _cuobjdump_1.ptx with cubin handle 1 -GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_CMkVsP" -Running: cat _ptx_CMkVsP | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_bVrCnu -GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_bVrCnu --output-file /dev/null 2> _ptx_CMkVsPinfo" -GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 -GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 -GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_CMkVsP _ptx2_bVrCnu _ptx_CMkVsPinfo" -GPGPU-Sim PTX: loading globals with explicit initializers... -GPGPU-Sim PTX: finished loading globals (0 bytes total). -GPGPU-Sim PTX: loading constants with explicit initializers... done. -GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 -GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 -Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes -GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes -GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes -GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes -GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes -GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping -GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ -GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes -GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -Number of Memory Banks Accessed per Memory Operation per Warp (from 0): -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Average # of Memory Banks Accessed per Memory Operation per Warp=-nan - -position of mrq chosen -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -average position of mrq chosen = -nan -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Network latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Flit latency average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Fragmentation average = -nan (1 samples) - minimum = nan (1 samples) - maximum = -nan (1 samples) -Injected packet rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Accepted packet rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Injected flit rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Accepted flit rate average = -nan (1 samples) - minimum = -nan (1 samples) - maximum = -nan (1 samples) -Injected packet size average = -nan (1 samples) -Accepted packet size average = -nan (1 samples) -Hops average = -nan (1 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -Number of Memory Banks Accessed per Memory Operation per Warp (from 0): -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Average # of Memory Banks Accessed per Memory Operation per Warp=-nan - -position of mrq chosen -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -average position of mrq chosen = -nan -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Network latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Flit latency average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Fragmentation average = -nan (2 samples) - minimum = nan (2 samples) - maximum = -nan (2 samples) -Injected packet rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Accepted packet rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Injected flit rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Accepted flit rate average = -nan (2 samples) - minimum = -nan (2 samples) - maximum = -nan (2 samples) -Injected packet size average = -nan (2 samples) -Accepted packet size average = -nan (2 samples) -Hops average = -nan (2 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -Number of Memory Banks Accessed per Memory Operation per Warp (from 0): -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Average # of Memory Banks Accessed per Memory Operation per Warp=-nan - -position of mrq chosen -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -average position of mrq chosen = -nan -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Network latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Flit latency average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Fragmentation average = -nan (3 samples) - minimum = nan (3 samples) - maximum = -nan (3 samples) -Injected packet rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Accepted packet rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Injected flit rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Accepted flit rate average = -nan (3 samples) - minimum = -nan (3 samples) - maximum = -nan (3 samples) -Injected packet size average = -nan (3 samples) -Accepted packet size average = -nan (3 samples) -Hops average = -nan (3 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 0 -gpu_tot_sim_insn = 0 -gpu_tot_ipc = -nan -gpu_tot_issued_cta = 0 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=0 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 0 - L1I_total_cache_misses = 0 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 0 - L1C_total_cache_misses = 0 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 0 -gpgpu_n_tot_w_icount = 0 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 0 -gpgpu_n_mem_write_global = 0 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 0 -gpgpu_n_load_insn = 0 -gpgpu_n_store_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 0 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 - -GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 -maxmrqlatency = 0 -maxdqlatency = 0 -maxmflatency = 0 -max_icnt2mem_latency = 0 -max_icnt2sh_latency = 0 -mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: -nan GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) - -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 0/0 = -nan -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: none none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none none none none none none none -dram[2]: none none none none none none none none none none none none none none none none -dram[3]: none none none none none none none none none none none none none none none none -dram[4]: none none none none none none none none none none none none none none none none -dram[5]: none none none none none none none none none none none none none none none none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -Number of Memory Banks Accessed per Memory Operation per Warp (from 0): -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Average # of Memory Banks Accessed per Memory Operation per Warp=-nan - -position of mrq chosen -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -average position of mrq chosen = -nan -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 3: -Cache L2_bank_006: -MSHR contents - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan -n_activity=0 dram_eff=-nan -bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=-nan - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 0 -L2_total_cache_misses = 0 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.000 - -icnt_total_pkts_mem_to_simt=0 -icnt_total_pkts_simt_to_mem=0 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = -nan - minimum = nan - maximum = -nan -Network latency average = -nan - minimum = nan - maximum = -nan -Slowest packet = -1 -Flit latency average = -nan - minimum = nan - maximum = -nan -Slowest flit = -1 -Fragmentation average = -nan - minimum = nan - maximum = -nan -Injected packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted packet rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected flit rate average = -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Accepted flit rate average= -nan - minimum = -nan (at node 0) - maximum = -nan (at node 0) -Injected packet length average = -nan -Accepted packet length average = -nan -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Network latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Flit latency average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Fragmentation average = -nan (4 samples) - minimum = nan (4 samples) - maximum = -nan (4 samples) -Injected packet rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Accepted packet rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Injected flit rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Accepted flit rate average = -nan (4 samples) - minimum = -nan (4 samples) - maximum = -nan (4 samples) -Injected packet size average = -nan (4 samples) -Accepted packet size average = -nan (4 samples) -Hops average = -nan (4 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- -GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' -GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit -GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) -GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 18:22:19 2017 -GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA -GPGPU-Sim uArch: Shader 1 finished CTA #0 (1079,0), 0 CTAs running -GPGPU-Sim uArch: Shader 1 empty (last released kernel 1 '_Z16digit_serial_madPjS_S_S_'). -GPGPU-Sim uArch: GPU detected kernel 1 '_Z16digit_serial_madPjS_S_S_' finished on shader 1. -Destroy streams for kernel 1: size 0 -kernel_name = _Z16digit_serial_madPjS_S_S_ -kernel_launch_uid = 1 -gpu_sim_cycle = 1080 -gpu_sim_insn = 675 -gpu_ipc = 0.6250 -gpu_tot_sim_cycle = 1080 -gpu_tot_sim_insn = 675 -gpu_tot_ipc = 0.6250 -gpu_tot_issued_cta = 1 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=675 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 13 - L1I_total_cache_misses = 2 - L1I_total_cache_miss_rate = 0.1538 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 4 - L1C_total_cache_misses = 4 - L1C_total_cache_miss_rate = 1.0000 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: - Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 - Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 - Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 800 -gpgpu_n_tot_w_icount = 25 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 3 -gpgpu_n_mem_write_global = 1 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 1 -gpgpu_n_load_insn = 34 -gpgpu_n_store_insn = 32 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 128 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:1900 W0_Scoreboard:292 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 -traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} -traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} -traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} -traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} -traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} -traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} -traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} -traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} -maxmrqlatency = 7 -maxdqlatency = 0 -maxmflatency = 252 -averagemflatency = 250 -max_icnt2mem_latency = 6 -max_icnt2sh_latency = 1079 -mrq_lat_table:7 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_table:0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2mem_lat_table:0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -icnt2sh_lat_table:0 0 4 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 -mf_lat_pw_table:0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum concurrent accesses to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -maximum service time to same row: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 750 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 759 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 1064 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 1038 0 0 0 0 228 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -average row accesses per activate: -dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan -dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan -dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 2.000000 -nan -nan -nan -nan -nan -dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan 1.000000 -dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -average row locality = 8/6 = 1.333333 -number of total memory accesses made: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total accesses: 0 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total read accesses: -dram[0]: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 7 -min_bank_accesses = 0! -min_chip_accesses = 0! -number of total write accesses: -dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -total reads: 1 -min_bank_accesses = 0! -min_chip_accesses = 0! -average mf latency per bank: -dram[0]: 252 none none none none none none none none none none none none none none none -dram[1]: none none none none none none none none none none 250 none none none none none -dram[2]: none none none none none none none none none none 250 none none none none none -dram[3]: none none none none none none none none none none 122 none none none none none -dram[4]: none none none none none none none none none none 252 none none none none 0 -dram[5]: none none none none none none none none none none none none none none 0 none -dram[6]: none none none none none none none none none none none none none none none none -dram[7]: none none none none none none none none none none none none none none none none -dram[8]: none none none none none none none none none none none none none none none none -dram[9]: none none none none none none none none none none none none none none none none -dram[10]: none none none none none none none none none none none none none none none none -maximum mf latency per bank: -dram[0]: 252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[1]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 -dram[2]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 -dram[3]: 0 0 0 0 0 0 0 0 0 0 244 0 0 0 0 0 -dram[4]: 0 0 0 0 0 0 0 0 0 0 252 0 0 0 0 0 -dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -Number of Memory Banks Accessed per Memory Operation per Warp (from 0): -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -Average # of Memory Banks Accessed per Memory Operation per Warp=-nan - -position of mrq chosen -0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - -average position of mrq chosen = -nan -Memory Partition 0: -Cache L2_bank_000: -MSHR contents - -Cache L2_bank_001: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 -n_activity=40 dram_eff=0.2 -bk0: 4a 1985i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 1: -Cache L2_bank_002: -MSHR contents - -Cache L2_bank_003: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 -n_activity=40 dram_eff=0.2 -bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 2: -Cache L2_bank_004: -MSHR contents - -Cache L2_bank_005: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 -n_activity=40 dram_eff=0.2 -bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 3: -Cache L2_bank_006: -MSHR contents -MSHR: tag=0x3e20200, atomic=0 1 entries : 0x7f6d3018f8f0 : mf: uid= 22, sid01:w00, part=3, addr=0x3e20200, load , size=128, unknown status = IN_PARTITION_DRAM (1079), - -Cache L2_bank_007: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=1996 n_act=1 n_pre=0 n_req=2 n_rd=3 n_write=4 bw_util=0.006986 -n_activity=29 dram_eff=0.4828 -bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 3a 1975i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=1 avg=0.00598802 -Memory Partition 4: -Cache L2_bank_008: -MSHR contents - -Cache L2_bank_009: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=1994 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007984 -n_activity=80 dram_eff=0.2 -bk0: 0a 2002i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 4a 1984i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 5: -Cache L2_bank_010: -MSHR contents - -Cache L2_bank_011: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 -n_activity=40 dram_eff=0.2 -bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2005i bk14: 4a 1985i bk15: 0a 2003i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 6: -Cache L2_bank_012: -MSHR contents - -Cache L2_bank_013: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 -n_activity=0 dram_eff=-nan -bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 7: -Cache L2_bank_014: -MSHR contents - -Cache L2_bank_015: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 -n_activity=0 dram_eff=-nan -bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 8: -Cache L2_bank_016: -MSHR contents - -Cache L2_bank_017: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 -n_activity=0 dram_eff=-nan -bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 9: -Cache L2_bank_018: -MSHR contents - -Cache L2_bank_019: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 -n_activity=0 dram_eff=-nan -bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 -Memory Partition 10: -Cache L2_bank_020: -MSHR contents - -Cache L2_bank_021: -MSHR contents - -In Dram Latency Queue (total = 0): -DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 -n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 -n_activity=0 dram_eff=-nan -bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i -dram_util_bins: 0 0 0 0 0 0 0 0 0 0 -dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 -mrqq: max=0 avg=0 - -========= L2 cache stats ========= -L2_cache_bank[0]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[2]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -L2_total_cache_accesses = 7 -L2_total_cache_misses = 7 -L2_total_cache_miss_rate = 1.0000 -L2_total_cache_pending_hits = 0 -L2_total_cache_reservation_fails = 0 -L2_total_cache_breakdown: - L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 3 - L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 - L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 1 - L2_cache_stats_breakdown[INST_ACC_R][MISS] = 2 -L2_cache_data_port_util = 0.000 -L2_cache_fill_port_util = 0.001 - -icnt_total_pkts_mem_to_simt=23 -icnt_total_pkts_simt_to_mem=11 -LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -----------------------------Interconnect-DETAILS-------------------------------- -Class 0: -Packet latency average = 7.42857 - minimum = 6 - maximum = 10 -Network latency average = 7.42857 - minimum = 6 - maximum = 10 -Slowest packet = 1 -Flit latency average = 6 - minimum = 6 - maximum = 6 -Slowest flit = 0 -Fragmentation average = 0 - minimum = 0 - maximum = 0 -Injected packet rate average = 0.00012975 - minimum = 0 (at node 0) - maximum = 0.00324374 (at node 1) -Accepted packet rate average = 0.00012975 - minimum = 0 (at node 0) - maximum = 0.00324374 (at node 1) -Injected flit rate average = 0.000315107 - minimum = 0 (at node 0) - maximum = 0.00509731 (at node 1) -Accepted flit rate average= 0.000315107 - minimum = 0 (at node 0) - maximum = 0.010658 (at node 1) -Injected packet length average = 2.42857 -Accepted packet length average = 2.42857 -Total in-flight flits = 0 (0 measured) -====== Overall Traffic Statistics ====== -====== Traffic class 0 ====== -Packet latency average = -nan (5 samples) - minimum = nan (5 samples) - maximum = -nan (5 samples) -Network latency average = -nan (5 samples) - minimum = nan (5 samples) - maximum = -nan (5 samples) -Flit latency average = -nan (5 samples) - minimum = nan (5 samples) - maximum = -nan (5 samples) -Fragmentation average = -nan (5 samples) - minimum = nan (5 samples) - maximum = -nan (5 samples) -Injected packet rate average = -nan (5 samples) - minimum = -nan (5 samples) - maximum = -nan (5 samples) -Accepted packet rate average = -nan (5 samples) - minimum = -nan (5 samples) - maximum = -nan (5 samples) -Injected flit rate average = -nan (5 samples) - minimum = -nan (5 samples) - maximum = -nan (5 samples) -Accepted flit rate average = -nan (5 samples) - minimum = -nan (5 samples) - maximum = -nan (5 samples) -Injected packet size average = -nan (5 samples) -Accepted packet size average = -nan (5 samples) -Hops average = -nan (5 samples) -----------------------------END-of-Interconnect-DETAILS------------------------- - - -gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 1 sec (1 sec) -gpgpu_simulation_rate = 675 (inst/sec) -gpgpu_simulation_rate = 1080 (cycle/sec) -kernel_name = -kernel_launch_uid = -gpu_sim_cycle = 0 -gpu_sim_insn = 0 -gpu_ipc = -nan -gpu_tot_sim_cycle = 1080 -gpu_tot_sim_insn = 675 -gpu_tot_ipc = 0.6250 -gpu_tot_issued_cta = 1 -max_total_param_size = 0 -gpu_stall_dramfull = 0 -gpu_stall_icnt2sh = 0 -gpu_total_sim_rate=675 - -========= Core cache stats ========= -L1I_cache: - L1I_total_cache_accesses = 13 - L1I_total_cache_misses = 2 - L1I_total_cache_miss_rate = 0.1538 - L1I_total_cache_pending_hits = 0 - L1I_total_cache_reservation_fails = 0 -L1D_cache: - L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 -Result: 0XA000006F - L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 - L1D_total_cache_accesses = 0 - L1D_total_cache_misses = 0 - L1D_total_cache_pending_hits = 0 - L1D_total_cache_reservation_fails = 0 - L1D_cache_data_port_util = 0.000 - L1D_cache_fill_port_util = 0.000 -L1C_cache: - L1C_total_cache_accesses = 4 - L1C_total_cache_misses = 4 - L1C_total_cache_miss_rate = 1.0000 - L1C_total_cache_pending_hits = 0 - L1C_total_cache_reservation_fails = 0 -L1T_cache: - L1T_total_cache_accesses = 0 - L1T_total_cache_misses = 0 - L1T_total_cache_pending_hits = 0 - L1T_total_cache_reservation_fails = 0 - -Total_core_cache_stats: - Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 - Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 - Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 -Shader 0 warp_id issue ditsribution: -warp_id: - -distro: - -gpgpu_n_tot_thrd_icount = 800 -gpgpu_n_tot_w_icount = 25 -gpgpu_n_stall_shd_mem = 0 -gpgpu_n_mem_read_local = 0 -gpgpu_n_mem_write_local = 0 -gpgpu_n_mem_read_global = 3 -gpgpu_n_mem_write_global = 1 -gpgpu_n_mem_texture = 0 -gpgpu_n_mem_const = 1 -gpgpu_n_load_insn = 34 -gpgpu_n_store_insn = 32 -gpgpu_n_shmem_insn = 0 -gpgpu_n_shmem_insn = 0 -gpgpu_n_tex_insn = 0 -gpgpu_n_const_mem_insn = 0 -gpgpu_n_param_mem_insn = 128 -gpgpu_n_shmem_bkconflict = 0 -gpgpu_n_cache_bkconflict = 0 -gpgpu_n_intrawarp_mshr_merge = 0 -gpgpu_n_cmem_portconflict = 0 -gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 -gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 -gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 -gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 -gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 -gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 -gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 -gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 -gpu_reg_bank_conflict_stalls = 0 -Warp Occupancy Distribution: -Stall:0 W0_Idle:1900 W0_Scoreboard:292 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 -traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} -traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} -traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} -traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} -traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} -traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} -traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} -traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} |