aboutsummaryrefslogtreecommitdiff
path: root/bsmad_test
diff options
context:
space:
mode:
Diffstat (limited to 'bsmad_test')
-rw-r--r--bsmad_test/.gdbinit97
-rw-r--r--bsmad_test/Makefile6
-rwxr-xr-xbsmad_test/bsmadbin2660316 -> 0 bytes
-rw-r--r--bsmad_test/bsmad_result.txt333
-rw-r--r--bsmad_test/bsmad_test.cu76
-rw-r--r--bsmad_test/bsmadoutput.txt3004
-rw-r--r--bsmad_test/config_fermi_islip.icnt70
-rw-r--r--bsmad_test/d.log3049
-rw-r--r--bsmad_test/gpgpu_inst_stats.txt26
-rw-r--r--bsmad_test/gpgpusim.config149
-rwxr-xr-xbsmad_test/gpuwattch_gtx1080Ti.xml538
-rw-r--r--bsmad_test/out.txt1837
-rw-r--r--bsmad_test/output2338
-rw-r--r--bsmad_test/output.txt2338
-rw-r--r--bsmad_test/result2338
15 files changed, 0 insertions, 16199 deletions
diff --git a/bsmad_test/.gdbinit b/bsmad_test/.gdbinit
deleted file mode 100644
index b456895..0000000
--- a/bsmad_test/.gdbinit
+++ /dev/null
@@ -1,97 +0,0 @@
-# Provides some useful debugging macros. To use this file, copy to your home
-# directory or to your simulation directory then run GPGPU-Sim in gdb.
-
-printf "\n ** loading GPGPU-Sim debugging macros... ** \n\n"
-
-set print pretty
-set print array-indexes
-set unwindonsignal on
-
-define dp
- call g_the_gpu->dump_pipeline((0x40|0x4|0x1),$arg0,0)
-end
-
-document dp
-Usage: dp <index>
-Display pipeline state.
-<index>: index of shader core you would like to see the pipeline state of
-
-This function displays the state of the pipeline on a single shader core
-(setting different values for the first argument of the call to
-dump_pipeline will cause different information to be displayed--
-see the source code for more details)
-end
-
-define dpc
- call g_the_gpu->dump_pipeline((0x40|0x4|0x1),$arg0,0)
- continue
-end
-
-document dpc
-Usage: dpc <index>
-Display pipeline state, then continue to next breakpoint.
-<index>: index of shader core you would like to see the pipeline state of
-
-This version is useful if you set a breakpoint where gpu_sim_cycle is
-incremented in gpu_sim_loop() in src/gpgpu-sim/gpu-sim.c
-repeatly hitting enter will advance to show the pipeline contents on
-the next cycle.
-end
-
-define dm
- call g_the_gpu->dump_pipeline(0x10000|0x10000000,0,$arg0)
-end
-
-define ptxdis
- set $addr=$arg0
- printf "disassemble instructions from 0x%x to 0x%x\n", $arg0, $arg1
- call fflush(stdout)
- while ( $addr <= $arg1 )
- printf "0x%04x (%4u) : ", $addr, $addr
- call ptx_print_insn( $addr, stdout )
- call fflush(stdout)
- set $addr = $addr + ptx_print_insn::size
- end
-end
-
-document ptxdis
-Usage: ptxdis <start> <end>
-Disassemble PTX instructions between <start> and <end> (PCs).
-end
-
-define ptxdis_func
- set $sid = $arg0
- set $cluster = g_the_gpu_config.m_shader_config.sid_to_cluster($sid)
- set $cid = g_the_gpu_config.m_shader_config.sid_to_cid($sid)
- set $ptx_tinfo = g_the_gpu->m_cluster[$cluster]->m_core[$cid]->m_thread[$arg1]
- set $finfo = $ptx_tinfo->m_func_info
- set $minpc = $finfo->m_start_PC
- set $maxpc = $minpc + $finfo->m_instr_mem_size
- printf "disassembly of function %s (min pc = %u, max pc = %u):\n", $finfo->m_name.c_str(), $minpc, $maxpc
- ptxdis $minpc $maxpc
-end
-
-document ptxdis_func
-Usage: ptxdis_func <shd_idx> <tid> (requires debug build)
-<shd_idx>: shader core number
-<tid>: thread ID
-end
-
-define ptx_tids2pcs
- set $i = 0
- while ( $i < $arg1 )
- set $tid = $arg0[$i]
- set $cluster = g_the_gpu_config.m_shader_config.sid_to_cluster($sid);
- set $cid = g_the_gpu_config.m_shader_config.sid_to_cid($sid);
- set $addr = g_the_gpu->m_cluster[$cluster]->m_core[$cid]->m_thread[$tid]->m_PC
- printf "%2u : tid = %3u => pc = %d\n", $i, $tid, $addr
- set $i = $i + 1
- end
-end
-
-document ptx_tids2pcs
-Usage: ptx_tids2pcs <tids> <tidslen> <shd_idx>
-<tids>: array of tids
-<tidslen>: length of <tids> array
-<shd_idx>: shader core number
-end
diff --git a/bsmad_test/Makefile b/bsmad_test/Makefile
deleted file mode 100644
index b841c6b..0000000
--- a/bsmad_test/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-all: bsmad_test.cu
- nvcc --gpu-architecture=compute_50 --gpu-code=compute_50 -lcudart -g -o bsmad bsmad_test.cu
-
-.PHONY:
-clean:
- rm bsmad
diff --git a/bsmad_test/bsmad b/bsmad_test/bsmad
deleted file mode 100755
index 56020ff..0000000
--- a/bsmad_test/bsmad
+++ /dev/null
Binary files differ
diff --git a/bsmad_test/bsmad_result.txt b/bsmad_test/bsmad_result.txt
deleted file mode 100644
index 968a990..0000000
--- a/bsmad_test/bsmad_result.txt
+++ /dev/null
@@ -1,333 +0,0 @@
-GNU gdb (GDB) SUSE (7.5.1-2.5.1)
-Copyright (C) 2012 Free Software Foundation, Inc.
-License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
-This is free software: you are free to change and redistribute it.
-There is NO WARRANTY, to the extent permitted by law. Type "show copying"
-and "show warranty" for details.
-This GDB was configured as "x86_64-suse-linux".
-For bug reporting instructions, please see:
-<http://www.gnu.org/software/gdb/bugs/>...
-Reading symbols from /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad...done.
-To enable execution of this file add
- add-auto-load-safe-path /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/.gdbinit
-line to your configuration file "/home/negargoli93/.gdbinit".
-To completely disable this security protection add
- set auto-load safe-path /
-line to your configuration file "/home/negargoli93/.gdbinit".
-For more information about this security protection see the
-"Auto-loading safe path" section in the GDB manual. E.g., run from the shell:
- info "(gdb)Auto-loading safe path"
-(gdb) r^C(gdb) r
-Starting program: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad
-[Thread debugging using libthread_db enabled]
-Using host libthread_db library "/lib64/libthread_db.so.1".
-
-
- *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-0751c1489add70d7494521c7f9d65f462e4391c6_modified_0] ***
-
-
-GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable:
- 1=functional simulation only, 0=detailed performance simulator)
-GPGPU-Sim: Configuration options:
-
--network_mode 1 # Interconnection network mode
--inter_config_file config_fermi_islip.icnt # Interconnection network config file
--gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries
--gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable]
--gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus
--gpgpu_ptx_force_max_capability 60 # Force maximum compute capability
--gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file
--gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file
--gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output
--gpgpu_simd_model 1 # 1 = post-dominator
--gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>}
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>}
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip)
--gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss)
--n_regfile_gating_group 4 # group of lanes that should be read/written together)
--gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations
--gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations
--gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)
--gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8)
--gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16)
--gpgpu_n_clusters 28 # number of processing clusters
--gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster
--gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer
--gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer
--gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16)
--gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on)
--gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check
--gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from
--gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from
--gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled)
--gpgpu_num_reg_banks 32 # Number of register banks (default = 8)
--gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off)
--gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4)
--gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4)
--gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2)
--gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0)
--gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0)
--gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0)
--gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now)
--gpgpu_num_sched_per_core 2 # Number of warp schedulers per core
--gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler
--gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)
--gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_num_sp_units 4 # Number of SP units (default=1)
--gpgpu_num_sfu_units 1 # Number of SF units (default=1)
--gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything
--gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto
--gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled)
--gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul)
--gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i
--l2_ideal 0 # Use a ideal L2 cache that always hit
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only
--gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu
--gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module
--gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller
--gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs
--gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip
--gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip
--gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR)
--gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle)
--dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR)
--gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
--rop_latency 120 # ROP queue latency (default 85)
--dram_latency 100 # DRAM latency (default 30)
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>}
--gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address
--gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits
--gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file
--power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off)
--power_per_cycle_dump 0 # Dump detailed power output each cycle
--power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off)
--power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest)
--steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off)
--steady_state_definition 8:4 # allowed deviation:number of samples
--gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>}
--liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print)
--gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call
--gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call
--gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off)
--gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now)
--gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1)
--gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>}
--gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU
--gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger
--visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off)
--visualizer_outputfile NULL # Specifies the output log file for visualizer
--visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest)
--trace_enabled 0 # Turn on traces
--trace_components none # comma seperated list of traces to enable. Complete list found in trace[New Thread 0x7ffff4512700 (LWP 5117)]
-[Thread 0x7ffff4512700 (LWP 5117) exited]
-[New Thread 0x7ffff4512700 (LWP 5120)]
-
-Program received signal SIGINT, Interrupt.
-0x00007ffff6f78fef in pthread_join () from /lib64/libpthread.so.0
-Missing separate debuginfos, use: zypper install Mesa-libGL1-debuginfo-8.0.4-20.27.1.x86_64 Mesa-libglapi0-debuginfo-8.0.4-20.27.1.x86_64 glibc-debuginfo-2.15-22.17.1.x86_64 libX11-6-debuginfo-1.5.0-2.7.1.x86_64 libX11-xcb1-debuginfo-1.5.0-2.7.1.x86_64 libXau6-debuginfo-1.0.7-2.1.2.x86_64 libXdamage1-debuginfo-1.1.3-2.1.2.x86_64 libXext6-debuginfo-1.3.1-2.4.1.x86_64 libXfixes3-debuginfo-5.0-2.4.1.x86_64 libXxf86vm1-debuginfo-1.1.2-2.7.1.x86_64 libdrm2-debuginfo-2.4.33-2.3.2.x86_64 libgcc47-debuginfo-4.7.1_20120723-1.1.1.x86_64 libstdc++47-debuginfo-4.7.1_20120723-1.1.1.x86_64 libxcb-glx0-debuginfo-1.8.1-2.8.1.x86_64 libxcb1-debuginfo-1.8.1-2.8.1.x86_64 zlib-debuginfo-1.2.7-2.1.2.x86_64
-(gdb)
-(gdb) quit
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) Please answer y or n.
-A debugging session is active.
-
- Inferior 1 [process 5113] will be killed.
-
-Quit anyway? (y or n) EOF [assumed Y]
diff --git a/bsmad_test/bsmad_test.cu b/bsmad_test/bsmad_test.cu
deleted file mode 100644
index 9be6e74..0000000
--- a/bsmad_test/bsmad_test.cu
+++ /dev/null
@@ -1,76 +0,0 @@
-#include <stdio.h>
-#define SIZE 1024
-#define THREADS_PER_BLOCK 32
-#define PART_THREADS 1
-#define NUM_BLOCKS 1
-#define I_PREC 4
-#define O_PREC 4
-
-__global__ void vector_add(int* A, int* B, int* res)
-{
- int tid = threadIdx.x + blockIdx.x * blockDim.x;
- res[tid] = A[tid] + B[tid];
-}
-
-__global__ void digit_serial_mad(unsigned* i_buffer, unsigned* i_synapse, unsigned* result, unsigned* accum)
-{
- unsigned tid = threadIdx.x + blockIdx.x * blockDim.x;
- unsigned buffer;
- unsigned synapse;
- if (tid < PART_THREADS)
- {
- buffer = i_buffer[tid];
- synapse = i_synapse[tid];
- }
-
- asm("/*");
- asm("CPTX_BEGIN");
- asm("bsmad.s32 %0, %1, %2, %3, %4, %5, %6, %7, %8;" : "=r"(result[tid]) :
- "r"(I_PREC), "r"(O_PREC), "r"(buffer), "r"(0), "r"(0), "r"(0), "r"(synapse), "r"(accum[tid]));
- asm("CPTX_END");
- asm("*/");
-}
-
-int main()
-{
- // host values
- unsigned *buffer = (unsigned*)malloc(sizeof(unsigned));
- unsigned *synapse = (unsigned*)malloc(sizeof(unsigned));
- unsigned *result = (unsigned*)calloc(THREADS_PER_BLOCK, sizeof(unsigned));
- unsigned *accum = (unsigned*)calloc(THREADS_PER_BLOCK, sizeof(unsigned));
- // assign host values
- *buffer = 0x5000003F;
- *synapse = 0x00000002;
- *accum = 0;
- // device pointers
- unsigned *d_buffer;
- unsigned *d_synapse;
- unsigned *d_result;
- unsigned *d_accum;
- // allocate device memory
- cudaMalloc(&d_buffer, sizeof(unsigned));
- cudaMalloc(&d_synapse, sizeof(unsigned));
- cudaMalloc(&d_result, sizeof(unsigned));
- cudaMalloc(&d_accum, sizeof(unsigned));
- // copy data to device
- cudaMemcpy(d_buffer, buffer, sizeof(unsigned), cudaMemcpyHostToDevice);
- cudaMemcpy(d_synapse, synapse, sizeof(unsigned), cudaMemcpyHostToDevice);
- cudaMemcpy(d_result, result, sizeof(unsigned) * THREADS_PER_BLOCK, cudaMemcpyHostToDevice);
- cudaMemcpy(d_accum, accum, sizeof(unsigned) * THREADS_PER_BLOCK, cudaMemcpyHostToDevice);
- // call kernel
- digit_serial_mad<<<NUM_BLOCKS, THREADS_PER_BLOCK>>>(d_buffer, d_synapse, d_result, d_accum);
- // copy data back to host
- cudaMemcpy(result, d_result, sizeof(unsigned) * THREADS_PER_BLOCK, cudaMemcpyDeviceToHost);
- // read out result
- printf("Result: %#X\n", result[0]);
- // clean up device memory
- cudaFree(d_buffer);
- cudaFree(d_synapse);
- cudaFree(d_result);
- cudaFree(d_accum);
- // clean up host memory
- free(buffer);
- free(synapse);
- free(result);
- free(accum);
-}
diff --git a/bsmad_test/bsmadoutput.txt b/bsmad_test/bsmadoutput.txt
deleted file mode 100644
index 7c5f9d5..0000000
--- a/bsmad_test/bsmadoutput.txt
+++ /dev/null
@@ -1,3004 +0,0 @@
-
-
- *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] ***
-
-
-GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable:
- 1=functional simulation only, 0=detailed performance simulator)
-GPGPU-Sim: Configuration options:
-
--network_mode 1 # Interconnection network mode
--inter_config_file config_fermi_islip.icnt # Interconnection network config file
--gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries
--gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable]
--gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus
--gpgpu_ptx_force_max_capability 60 # Force maximum compute capability
--gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file
--gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file
--gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output
--gpgpu_simd_model 1 # 1 = post-dominator
--gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>}
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>}
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip)
--gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss)
--n_regfile_gating_group 4 # group of lanes that should be read/written together)
--gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations
--gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations
--gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)
--gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8)
--gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16)
--gpgpu_n_clusters 28 # number of processing clusters
--gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster
--gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer
--gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer
--gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16)
--gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on)
--gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check
--gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from
--gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from
--gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled)
--gpgpu_num_reg_banks 32 # Number of register banks (default = 8)
--gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off)
--gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4)
--gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4)
--gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2)
--gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0)
--gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0)
--gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0)
--gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now)
--gpgpu_num_sched_per_core 2 # Number of warp schedulers per core
--gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler
--gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)
--gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_num_sp_units 4 # Number of SP units (default=1)
--gpgpu_num_sfu_units 1 # Number of SF units (default=1)
--gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything
--gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto
--gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled)
--gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul)
--gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i
--l2_ideal 0 # Use a ideal L2 cache that always hit
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only
--gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu
--gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module
--gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller
--gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs
--gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip
--gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip
--gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR)
--gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle)
--dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR)
--gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
--rop_latency 120 # ROP queue latency (default 85)
--dram_latency 100 # DRAM latency (default 30)
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>}
--gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address
--gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits
--gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file
--power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off)
--power_per_cycle_dump 0 # Dump detailed power output each cycle
--power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off)
--power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest)
--steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off)
--steady_state_definition 8:4 # allowed deviation:number of samples
--gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>}
--liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print)
--gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call
--gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call
--gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off)
--gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now)
--gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1)
--gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>}
--gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU
--gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger
--visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off)
--visualizer_outputfile NULL # Specifies the output log file for visualizer
--visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest)
--trace_enabled 0 # Turn on traces
--trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none
--trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0
--trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all)
--enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On)
--ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics.
--gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0
--gpgpu_cdp_enabled 0 # Turn on CDP
--save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx
--keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs
--gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file
--ptx_opcode_latency_int 4,13,4,5,145,4 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,19,25,145,1
--ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30
--ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335
--ptx_opcode_initiation_int 1,2,2,2,8,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,4,4,32,1
--ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5
--ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130
--cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600
-DRAM Timing Options:
-nbk 16 # number of banks
-CCD 2 # column to column delay
-RRD 6 # minimal delay between activation of rows in different banks
-RCD 12 # row to column delay
-RAS 28 # time needed to activate row
-RP 12 # time needed to precharge (deactivate) row
-RC 40 # row cycle time
-CDLR 5 # switching from write to read (changes tWTR)
-WR 12 # last data-in to row precharge
-CL 12 # CAS latency
-WL 4 # Write latency
-nbkgrp 1 # number of bank groups
-CCDL 0 # column to column delay between accesses to different bank groups
-RTPL 0 # read to precharge delay between accesses to different bank groups
-Total number of memory sub partition = 22
-addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0
-addr_dec_mask[BK] = 0000000000007080 high:15 low:7
-addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15
-addr_dec_mask[COL] = 0000000000000f7f high:12 low:0
-addr_dec_mask[BURST] = 000000000000001f high:5 low:0
-sub_partition_id_mask = 0000000000000080
-GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000
-GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364
-*** Initializing Memory Statistics ***
-GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID)
-GPGPU-Sim uArch: Memory nodes ID start from index: 28
-GPGPU-Sim uArch: 0 1 2 3 4 5 6
-GPGPU-Sim uArch: 7 8 9 10 11 12 13
-GPGPU-Sim uArch: 14 15 16 17 18 19 20
-GPGPU-Sim uArch: 21 22 23 24 25 26 27
-GPGPU-Sim uArch: 28 29 30 31 32 33 34
-GPGPU-Sim uArch: 35 36 37 38 39 40 41
-GPGPU-Sim uArch: 42 43 44 45 46 47 48
-GPGPU-Sim uArch: 49
-GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID)
-GPGPU-Sim uArch: Memory nodes start from ID: 28
-GPGPU-Sim uArch: 0 1 2 3 4 5 6
-GPGPU-Sim uArch: 7 8 9 10 11 12 13
-GPGPU-Sim uArch: 14 15 16 17 18 19 20
-GPGPU-Sim uArch: 21 22 23 24 25 26 27
-GPGPU-Sim uArch: 28 29 30 31 32 33 34
-GPGPU-Sim uArch: 35 36 37 38 39 40 41
-GPGPU-Sim uArch: 42 43 44 45 46 47 48
-GPGPU-Sim uArch: 49
-057a78a8e028f9794c162a7c4e45415d /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad
-GPGPU-Sim uArch: performance model initialization complete.
-GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default
-self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad
-Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad "
-Parsing file _cuobjdump_complete_output_A4Dkbu
-######### cuobjdump parser ########
-## Adding new section PTX
-Adding ptx filename: _cuobjdump_1.ptx
-Adding arch: sm_50
-Adding identifier: default
-Done parsing!!!
-GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1
-WARNING: No guarantee that PTX will be parsed for SM version 50
-GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done.
-GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_...
-GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_
-GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'.
-BEGINNING CUSTOM PTX.
-ENDING CUSTOM PTX.
-GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done.
-GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_...
-GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2;
-GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3;
-GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_
-GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'.
-GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx
-Adding _cuobjdump_1.ptx with cubin handle 1
-GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_3lcy4c"
-Running: cat _ptx_3lcy4c | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_6DnMXV
-GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_6DnMXV --output-file /dev/null 2> _ptx_3lcy4cinfo"
-GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352
-GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344
-GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_3lcy4c _ptx2_6DnMXV _ptx_3lcy4cinfo"
-GPGPU-Sim PTX: loading globals with explicit initializers...
-GPGPU-Sim PTX: finished loading globals (0 bytes total).
-GPGPU-Sim PTX: loading constants with explicit initializers... done.
-GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1
-GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes
-GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes
-GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes
-GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes
-GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Network latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Flit latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Fragmentation average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Injected packet rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Accepted packet rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Injected flit rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Accepted flit rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Injected packet size average = -nan (1 samples)
-Accepted packet size average = -nan (1 samples)
-Hops average = -nan (1 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Network latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Flit latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Fragmentation average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Injected packet rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Accepted packet rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Injected flit rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Accepted flit rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Injected packet size average = -nan (2 samples)
-Accepted packet size average = -nan (2 samples)
-Hops average = -nan (2 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Network latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Flit latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Fragmentation average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Injected packet rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Accepted packet rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Injected flit rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Accepted flit rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Injected packet size average = -nan (3 samples)
-Accepted packet size average = -nan (3 samples)
-Hops average = -nan (3 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0
-GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0
- 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1)
-bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Network latency average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Flit latency average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Fragmentation average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Injected packet rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Accepted packet rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Injected flit rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Accepted flit rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Injected packet size average = -nan (4 samples)
-Accepted packet size average = -nan (4 samples)
-Hops average = -nan (4 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_'
-GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit
-GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0)
-GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 17:28:53 2017
-GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA
-GPGPU-Sim uArch: Shader 1 finished CTA #0 (1081,0), 0 CTAs running
-GPGPU-Sim uArch: Shader 1 empty (last released kernel 1 '_Z16digit_serial_madPjS_S_S_').
-GPGPU-Sim uArch: GPU detected kernel 1 '_Z16digit_serial_madPjS_S_S_' finished on shader 1.
-Destroy streams for kernel 1: size 0
-kernel_name = _Z16digit_serial_madPjS_S_S_
-kernel_launch_uid = 1
-gpu_sim_cycle = 1082
-gpu_sim_insn = 675
-gpu_ipc = 0.6238
-gpu_tot_sim_cycle = 1082
-gpu_tot_sim_insn = 675
-gpu_tot_ipc = 0.6238
-gpu_tot_issued_cta = 1
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=675
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 13
- L1I_total_cache_misses = 2
- L1I_total_cache_miss_rate = 0.1538
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 4
- L1C_total_cache_misses = 4
- L1C_total_cache_miss_rate = 1.0000
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
- Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4
- Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11
- Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 800
-gpgpu_n_tot_w_icount = 25
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 3
-gpgpu_n_mem_write_global = 1
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 1
-gpgpu_n_load_insn = 34
-gpgpu_n_store_insn = 32
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 128
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:1902 W0_Scoreboard:294 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21
-traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,}
-traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,}
-traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,}
-traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,}
-traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,}
-traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,}
-traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,}
-traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,}
-maxmrqlatency = 7
-maxdqlatency = 0
-maxmflatency = 252
-averagemflatency = 250
-max_icnt2mem_latency = 6
-max_icnt2sh_latency = 1081
-mrq_lat_table:7 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 4 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 750 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 759 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 1066 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 1038 0 0 0 0 228
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 2.000000 -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan 1.000000
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 8/6 = 1.333333
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 7
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 1
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: 252 none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none 250 none none none none none
-dram[2]: none none none none none none none none none none 250 none none none none none
-dram[3]: none none none none none none none none none none 122 none none none none none
-dram[4]: none none none none none none none none none none 252 none none none none 0
-dram[5]: none none none none none none none none none none none none none none 0 none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 244 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 252 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984
-n_activity=40 dram_eff=0.2
-bk0: 4a 1989i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984
-n_activity=40 dram_eff=0.2
-bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 4a 1989i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 0a 2007i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984
-n_activity=40 dram_eff=0.2
-bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 4a 1989i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 0a 2007i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-MSHR: tag=0x3e20200, atomic=0 1 entries : 0x7f51d804c750 : mf: uid= 22, sid01:w00, part=3, addr=0x3e20200, load , size=128, unknown status = IN_PARTITION_DRAM (1081),
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2008 n_nop=2000 n_act=1 n_pre=0 n_req=2 n_rd=3 n_write=4 bw_util=0.006972
-n_activity=29 dram_eff=0.4828
-bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 3a 1979i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 0a 2007i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=1 avg=0.0059761
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2008 n_nop=1998 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007968
-n_activity=80 dram_eff=0.2
-bk0: 0a 2006i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 4a 1989i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 4a 1988i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984
-n_activity=40 dram_eff=0.2
-bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2009i bk14: 4a 1989i bk15: 0a 2007i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0
-n_activity=0 dram_eff=-nan
-bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0
-n_activity=0 dram_eff=-nan
-bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0
-n_activity=0 dram_eff=-nan
-bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0
-n_activity=0 dram_eff=-nan
-bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0
-n_activity=0 dram_eff=-nan
-bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 7
-L2_total_cache_misses = 7
-L2_total_cache_miss_rate = 1.0000
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
- L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 3
- L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1
- L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 1
- L2_cache_stats_breakdown[INST_ACC_R][MISS] = 2
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.001
-
-icnt_total_pkts_mem_to_simt=23
-icnt_total_pkts_simt_to_mem=11
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = 7.42857
- minimum = 6
- maximum = 10
-Network latency average = 7.42857
- minimum = 6
- maximum = 10
-Slowest packet = 1
-Flit latency average = 6
- minimum = 6
- maximum = 6
-Slowest flit = 0
-Fragmentation average = 0
- minimum = 0
- maximum = 0
-Injected packet rate average = 0.00012951
- minimum = 0 (at node 0)
- maximum = 0.00323774 (at node 1)
-Accepted packet rate average = 0.00012951
- minimum = 0 (at node 0)
- maximum = 0.00323774 (at node 1)
-Injected flit rate average = 0.000314524
- minimum = 0 (at node 0)
- maximum = 0.00508788 (at node 1)
-Accepted flit rate average= 0.000314524
- minimum = 0 (at node 0)
- maximum = 0.0106383 (at node 1)
-Injected packet length average = 2.42857
-Accepted packet length average = 2.42857
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (5 samples)
- minimum = nan (5 samples)
- maximum = -nan (5 samples)
-Network latency average = -nan (5 samples)
- minimum = nan (5 samples)
- maximum = -nan (5 samples)
-Flit latency average = -nan (5 samples)
- minimum = nan (5 samples)
- maximum = -nan (5 samples)
-Fragmentation average = -nan (5 samples)
- minimum = nan (5 samples)
- maximum = -nan (5 samples)
-Injected packet rate average = -nan (5 samples)
- minimum = -nan (5 samples)
- maximum = -nan (5 samples)
-Accepted packet rate average = -nan (5 samples)
- minimum = -nan (5 samples)
- maximum = -nan (5 samples)
-Injected flit rate average = -nan (5 samples)
- minimum = -nan (5 samples)
- maximum = -nan (5 samples)
-Accepted flit rate average = -nan (5 samples)
- minimum = -nan (5 samples)
- maximum = -nan (5 samples)
-Injected packet size average = -nan (5 samples)
-Accepted packet size average = -nan (5 samples)
-Hops average = -nan (5 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-
-
-gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 1 sec (1 sec)
-gpgpu_simulation_rate = 675 (inst/sec)
-gpgpu_simulation_rate = 1082 (cycle/sec)
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 1082
-gpu_tot_sim_insn = 675
-gpu_tot_ipc = 0.6238
-gpu_tot_issued_cta = 1
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=675
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 13
- L1I_total_cache_misses = 2
- L1I_total_cache_miss_rate = 0.1538
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 4
- L1C_total_cache_misses = 4
- L1C_total_cache_miss_rate = 1.0000
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
- Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4
- Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11
- Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 800
-gpgpu_n_tot_w_icount = 25
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 3
-gpgpu_n_mem_write_global = 1
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 1
-gpgpu_n_load_insn = 34
-gpgpu_n_store_insn = 32
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 128
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:1902 W0_Scoreboard:294 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21
-traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,}
-traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,}
-traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,}
-traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,}
-traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,}
-traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,}
-traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,}
-traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,}
-Result: 0XA000006F
diff --git a/bsmad_test/config_fermi_islip.icnt b/bsmad_test/config_fermi_islip.icnt
deleted file mode 100644
index 2a69ddd..0000000
--- a/bsmad_test/config_fermi_islip.icnt
+++ /dev/null
@@ -1,70 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 32;
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 50;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs = 1;
-vc_buf_size = 8;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters = 1;
-
-credit_delay = 0;
-routing_delay = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup = 2;
-output_speedup = 1;
-internal_speedup = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/bsmad_test/d.log b/bsmad_test/d.log
deleted file mode 100644
index 50ba43f..0000000
--- a/bsmad_test/d.log
+++ /dev/null
@@ -1,3049 +0,0 @@
-
-
- *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] ***
-
-
-GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable:
- 1=functional simulation only, 0=detailed performance simulator)
-GPGPU-Sim: Configuration options:
-
--network_mode 1 # Interconnection network mode
--inter_config_file config_fermi_islip.icnt # Interconnection network config file
--gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries
--gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable]
--gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus
--gpgpu_ptx_force_max_capability 60 # Force maximum compute capability
--gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file
--gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file
--gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output
--gpgpu_simd_model 1 # 1 = post-dominator
--gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>}
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>}
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip)
--gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss)
--n_regfile_gating_group 4 # group of lanes that should be read/written together)
--gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations
--gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations
--gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)
--gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8)
--gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16)
--gpgpu_n_clusters 28 # number of processing clusters
--gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster
--gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer
--gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer
--gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16)
--gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on)
--gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check
--gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from
--gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from
--gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled)
--gpgpu_num_reg_banks 32 # Number of register banks (default = 8)
--gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off)
--gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4)
--gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4)
--gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2)
--gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0)
--gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0)
--gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0)
--gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now)
--gpgpu_num_sched_per_core 2 # Number of warp schedulers per core
--gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler
--gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)
--gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_num_sp_units 4 # Number of SP units (default=1)
--gpgpu_num_sfu_units 1 # Number of SF units (default=1)
--gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything
--gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto
--gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled)
--gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul)
--gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i
--l2_ideal 0 # Use a ideal L2 cache that always hit
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only
--gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu
--gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module
--gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller
--gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs
--gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip
--gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip
--gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR)
--gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle)
--dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR)
--gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
--rop_latency 120 # ROP queue latency (default 85)
--dram_latency 100 # DRAM latency (default 30)
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>}
--gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address
--gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits
--gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file
--power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off)
--power_per_cycle_dump 0 # Dump detailed power output each cycle
--power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off)
--power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest)
--steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off)
--steady_state_definition 8:4 # allowed deviation:number of samples
--gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>}
--liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print)
--gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call
--gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call
--gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off)
--gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now)
--gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1)
--gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>}
--gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU
--gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger
--visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off)
--visualizer_outputfile NULL # Specifies the output log file for visualizer
--visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest)
--trace_enabled 0 # Turn on traces
--trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none
--trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0
--trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all)
--enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On)
--ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics.
--gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0
--gpgpu_cdp_enabled 0 # Turn on CDP
--save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx
--keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs
--gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file
--ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Presicion,BSMAD_lane_width>Default 1,1,19,25,145,1,4
--ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30
--ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335
--ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD_Precision,BSMAD_lane_width>Default 1,1,4,4,32,1,1
--ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5
--ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130
--cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600
-DRAM Timing Options:
-nbk 16 # number of banks
-CCD 2 # column to column delay
-RRD 6 # minimal delay between activation of rows in different banks
-RCD 12 # row to column delay
-RAS 28 # time needed to activate row
-RP 12 # time needed to precharge (deactivate) row
-RC 40 # row cycle time
-CDLR 5 # switching from write to read (changes tWTR)
-WR 12 # last data-in to row precharge
-CL 12 # CAS latency
-WL 4 # Write latency
-nbkgrp 1 # number of bank groups
-CCDL 0 # column to column delay between accesses to different bank groups
-RTPL 0 # read to precharge delay between accesses to different bank groups
-Total number of memory sub partition = 22
-addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0
-addr_dec_mask[BK] = 0000000000007080 high:15 low:7
-addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15
-addr_dec_mask[COL] = 0000000000000f7f high:12 low:0
-addr_dec_mask[BURST] = 000000000000001f high:5 low:0
-sub_partition_id_mask = 0000000000000080
-GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000
-GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364
-*** Initializing Memory Statistics ***
-GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID)
-GPGPU-Sim uArch: Memory nodes ID start from index: 28
-GPGPU-Sim uArch: 0 1 2 3 4 5 6
-GPGPU-Sim uArch: 7 8 9 10 11 12 13
-GPGPU-Sim uArch: 14 15 16 17 18 19 20
-GPGPU-Sim uArch: 21 22 23 24 25 26 27
-GPGPU-Sim uArch: 28 29 30 31 32 33 34
-GPGPU-Sim uArch: 35 36 37 38 39 40 41
-GPGPU-Sim uArch: 42 43 44 45 46 47 48
-GPGPU-Sim uArch: 49
-GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID)
-GPGPU-Sim uArch: Memory nodes start from ID: 28
-GPGPU-Sim uArch: 0 1 2 3 4 5 6
-GPGPU-Sim uArch: 7 8 9 10 11 12 13
-GPGPU-Sim uArch: 14 15 16 17 18 19 20
-GPGPU-Sim uArch: 21 22 23 24 25 26 27
-GPGPU-Sim uArch: 28 29 30 31 32 33 34
-GPGPU-Sim uArch: 35 36 37 38 39 40 41
-GPGPU-Sim uArch: 42 43 44 45 46 47 48
-GPGPU-Sim uArch: 49
-e1ffbb239b1e632822e743b7e0c60b46 /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad
-GPGPU-Sim uArch: performance model initialization complete.
-GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default
-self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad
-Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad "
-Parsing file _cuobjdump_complete_output_8Ypfya
-######### cuobjdump parser ########
-## Adding new section PTX
-Adding ptx filename: _cuobjdump_1.ptx
-Adding arch: sm_50
-Adding identifier: default
-Done parsing!!!
-GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1
-WARNING: No guarantee that PTX will be parsed for SM version 50
-GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done.
-GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_...
-GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_
-GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'.
-BEGINNING CUSTOM PTX.
-ENDING CUSTOM PTX.
-GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done.
-GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_...
-GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2;
-GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3;
-GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_
-GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'.
-GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx
-Adding _cuobjdump_1.ptx with cubin handle 1
-GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_CMkVsP"
-Running: cat _ptx_CMkVsP | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_bVrCnu
-GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_bVrCnu --output-file /dev/null 2> _ptx_CMkVsPinfo"
-GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352
-GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344
-GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_CMkVsP _ptx2_bVrCnu _ptx_CMkVsPinfo"
-GPGPU-Sim PTX: loading globals with explicit initializers...
-GPGPU-Sim PTX: finished loading globals (0 bytes total).
-GPGPU-Sim PTX: loading constants with explicit initializers... done.
-GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1
-GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes
-GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes
-GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes
-GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes
-GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-
-Number of Memory Banks Accessed per Memory Operation per Warp (from 0):
-0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Average # of Memory Banks Accessed per Memory Operation per Warp=-nan
-
-position of mrq chosen
-0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-
-average position of mrq chosen = -nan
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Network latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Flit latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Fragmentation average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Injected packet rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Accepted packet rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Injected flit rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Accepted flit rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Injected packet size average = -nan (1 samples)
-Accepted packet size average = -nan (1 samples)
-Hops average = -nan (1 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-
-Number of Memory Banks Accessed per Memory Operation per Warp (from 0):
-0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Average # of Memory Banks Accessed per Memory Operation per Warp=-nan
-
-position of mrq chosen
-0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-
-average position of mrq chosen = -nan
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Network latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Flit latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Fragmentation average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Injected packet rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Accepted packet rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Injected flit rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Accepted flit rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Injected packet size average = -nan (2 samples)
-Accepted packet size average = -nan (2 samples)
-Hops average = -nan (2 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-
-Number of Memory Banks Accessed per Memory Operation per Warp (from 0):
-0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Average # of Memory Banks Accessed per Memory Operation per Warp=-nan
-
-position of mrq chosen
-0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-
-average position of mrq chosen = -nan
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Network latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Flit latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Fragmentation average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Injected packet rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Accepted packet rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Injected flit rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Accepted flit rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Injected packet size average = -nan (3 samples)
-Accepted packet size average = -nan (3 samples)
-Hops average = -nan (3 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-
-GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1)
- -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-
-Number of Memory Banks Accessed per Memory Operation per Warp (from 0):
-0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Average # of Memory Banks Accessed per Memory Operation per Warp=-nan
-
-position of mrq chosen
-0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-
-average position of mrq chosen = -nan
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Network latency average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Flit latency average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Fragmentation average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Injected packet rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Accepted packet rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Injected flit rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Accepted flit rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Injected packet size average = -nan (4 samples)
-Accepted packet size average = -nan (4 samples)
-Hops average = -nan (4 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_'
-GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit
-GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0)
-GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 18:22:19 2017
-GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA
-GPGPU-Sim uArch: Shader 1 finished CTA #0 (1079,0), 0 CTAs running
-GPGPU-Sim uArch: Shader 1 empty (last released kernel 1 '_Z16digit_serial_madPjS_S_S_').
-GPGPU-Sim uArch: GPU detected kernel 1 '_Z16digit_serial_madPjS_S_S_' finished on shader 1.
-Destroy streams for kernel 1: size 0
-kernel_name = _Z16digit_serial_madPjS_S_S_
-kernel_launch_uid = 1
-gpu_sim_cycle = 1080
-gpu_sim_insn = 675
-gpu_ipc = 0.6250
-gpu_tot_sim_cycle = 1080
-gpu_tot_sim_insn = 675
-gpu_tot_ipc = 0.6250
-gpu_tot_issued_cta = 1
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=675
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 13
- L1I_total_cache_misses = 2
- L1I_total_cache_miss_rate = 0.1538
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 4
- L1C_total_cache_misses = 4
- L1C_total_cache_miss_rate = 1.0000
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
- Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4
- Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11
- Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 800
-gpgpu_n_tot_w_icount = 25
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 3
-gpgpu_n_mem_write_global = 1
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 1
-gpgpu_n_load_insn = 34
-gpgpu_n_store_insn = 32
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 128
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:1900 W0_Scoreboard:292 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21
-traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,}
-traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,}
-traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,}
-traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,}
-traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,}
-traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,}
-traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,}
-traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,}
-maxmrqlatency = 7
-maxdqlatency = 0
-maxmflatency = 252
-averagemflatency = 250
-max_icnt2mem_latency = 6
-max_icnt2sh_latency = 1079
-mrq_lat_table:7 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 4 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 750 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 759 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 1064 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 1038 0 0 0 0 228
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 2.000000 -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan 1.000000
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 8/6 = 1.333333
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 7
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 1
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: 252 none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none 250 none none none none none
-dram[2]: none none none none none none none none none none 250 none none none none none
-dram[3]: none none none none none none none none none none 122 none none none none none
-dram[4]: none none none none none none none none none none 252 none none none none 0
-dram[5]: none none none none none none none none none none none none none none 0 none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 244 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 252 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-
-Number of Memory Banks Accessed per Memory Operation per Warp (from 0):
-0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Average # of Memory Banks Accessed per Memory Operation per Warp=-nan
-
-position of mrq chosen
-0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-
-average position of mrq chosen = -nan
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992
-n_activity=40 dram_eff=0.2
-bk0: 4a 1985i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992
-n_activity=40 dram_eff=0.2
-bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992
-n_activity=40 dram_eff=0.2
-bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-MSHR: tag=0x3e20200, atomic=0 1 entries : 0x7f6d3018f8f0 : mf: uid= 22, sid01:w00, part=3, addr=0x3e20200, load , size=128, unknown status = IN_PARTITION_DRAM (1079),
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2004 n_nop=1996 n_act=1 n_pre=0 n_req=2 n_rd=3 n_write=4 bw_util=0.006986
-n_activity=29 dram_eff=0.4828
-bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 3a 1975i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=1 avg=0.00598802
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2004 n_nop=1994 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007984
-n_activity=80 dram_eff=0.2
-bk0: 0a 2002i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 4a 1984i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992
-n_activity=40 dram_eff=0.2
-bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2005i bk14: 4a 1985i bk15: 0a 2003i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0
-n_activity=0 dram_eff=-nan
-bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0
-n_activity=0 dram_eff=-nan
-bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0
-n_activity=0 dram_eff=-nan
-bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0
-n_activity=0 dram_eff=-nan
-bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0
-n_activity=0 dram_eff=-nan
-bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=0
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 7
-L2_total_cache_misses = 7
-L2_total_cache_miss_rate = 1.0000
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
- L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 3
- L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1
- L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 1
- L2_cache_stats_breakdown[INST_ACC_R][MISS] = 2
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.001
-
-icnt_total_pkts_mem_to_simt=23
-icnt_total_pkts_simt_to_mem=11
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = 7.42857
- minimum = 6
- maximum = 10
-Network latency average = 7.42857
- minimum = 6
- maximum = 10
-Slowest packet = 1
-Flit latency average = 6
- minimum = 6
- maximum = 6
-Slowest flit = 0
-Fragmentation average = 0
- minimum = 0
- maximum = 0
-Injected packet rate average = 0.00012975
- minimum = 0 (at node 0)
- maximum = 0.00324374 (at node 1)
-Accepted packet rate average = 0.00012975
- minimum = 0 (at node 0)
- maximum = 0.00324374 (at node 1)
-Injected flit rate average = 0.000315107
- minimum = 0 (at node 0)
- maximum = 0.00509731 (at node 1)
-Accepted flit rate average= 0.000315107
- minimum = 0 (at node 0)
- maximum = 0.010658 (at node 1)
-Injected packet length average = 2.42857
-Accepted packet length average = 2.42857
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (5 samples)
- minimum = nan (5 samples)
- maximum = -nan (5 samples)
-Network latency average = -nan (5 samples)
- minimum = nan (5 samples)
- maximum = -nan (5 samples)
-Flit latency average = -nan (5 samples)
- minimum = nan (5 samples)
- maximum = -nan (5 samples)
-Fragmentation average = -nan (5 samples)
- minimum = nan (5 samples)
- maximum = -nan (5 samples)
-Injected packet rate average = -nan (5 samples)
- minimum = -nan (5 samples)
- maximum = -nan (5 samples)
-Accepted packet rate average = -nan (5 samples)
- minimum = -nan (5 samples)
- maximum = -nan (5 samples)
-Injected flit rate average = -nan (5 samples)
- minimum = -nan (5 samples)
- maximum = -nan (5 samples)
-Accepted flit rate average = -nan (5 samples)
- minimum = -nan (5 samples)
- maximum = -nan (5 samples)
-Injected packet size average = -nan (5 samples)
-Accepted packet size average = -nan (5 samples)
-Hops average = -nan (5 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-
-
-gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 1 sec (1 sec)
-gpgpu_simulation_rate = 675 (inst/sec)
-gpgpu_simulation_rate = 1080 (cycle/sec)
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 1080
-gpu_tot_sim_insn = 675
-gpu_tot_ipc = 0.6250
-gpu_tot_issued_cta = 1
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=675
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 13
- L1I_total_cache_misses = 2
- L1I_total_cache_miss_rate = 0.1538
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-Result: 0XA000006F
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 4
- L1C_total_cache_misses = 4
- L1C_total_cache_miss_rate = 1.0000
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
- Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4
- Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11
- Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 800
-gpgpu_n_tot_w_icount = 25
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 3
-gpgpu_n_mem_write_global = 1
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 1
-gpgpu_n_load_insn = 34
-gpgpu_n_store_insn = 32
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 128
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:1900 W0_Scoreboard:292 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21
-traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,}
-traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,}
-traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,}
-traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,}
-traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,}
-traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,}
-traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,}
-traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,}
diff --git a/bsmad_test/gpgpu_inst_stats.txt b/bsmad_test/gpgpu_inst_stats.txt
deleted file mode 100644
index 96fa69d..0000000
--- a/bsmad_test/gpgpu_inst_stats.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-kernel line : count latency dram_traffic smem_bk_conflicts smem_warp gmem_access_generated gmem_warp exposed_latency warp_divergence
-_1.ptx 92 : 32 160 128 0 0 1 1 0 0
-_1.ptx 90 : 32 448 0 0 0 0 0 0 0
-_1.ptx 67 : 32 186 0 0 0 0 0 0 1
-_1.ptx 66 : 32 224 0 0 0 0 0 0 0
-_1.ptx 65 : 32 416 0 0 0 0 0 0 0
-_1.ptx 88 : 32 192 0 0 0 0 0 0 0
-_1.ptx 64 : 32 192 0 0 0 0 0 0 0
-_1.ptx 87 : 32 192 0 0 0 0 0 0 0
-_1.ptx 63 : 32 192 0 0 0 0 0 0 0
-_1.ptx 86 : 32 8256 128 0 0 1 1 0 0
-_1.ptx 99 : 32 192 0 0 0 0 0 0 0
-_1.ptx 62 : 32 192 0 0 0 0 0 0 0
-_1.ptx 85 : 32 352 0 0 0 0 0 0 0
-_1.ptx 61 : 32 8192 0 0 0 0 0 0 0
-_1.ptx 84 : 32 352 0 0 0 0 0 0 0
-_1.ptx 60 : 32 8192 0 0 0 0 0 0 0
-_1.ptx 83 : 32 320 0 0 0 0 0 0 0
-_1.ptx 59 : 32 8224 0 0 0 0 0 0 0
-_1.ptx 58 : 32 8224 128 0 0 0 0 0 0
-_1.ptx 69 : 1 7 0 0 0 0 0 0 0
-_1.ptx 70 : 1 256 128 0 0 1 1 0 0
-_1.ptx 71 : 1 7 0 0 0 0 0 0 0
-_1.ptx 72 : 1 256 128 0 0 1 1 0 0
-_1.ptx 75 : 32 224 0 0 0 0 0 0 0
-_1.ptx 76 : 32 224 0 0 0 0 0 0 0
diff --git a/bsmad_test/gpgpusim.config b/bsmad_test/gpgpusim.config
deleted file mode 100644
index 6b512ba..0000000
--- a/bsmad_test/gpgpusim.config
+++ /dev/null
@@ -1,149 +0,0 @@
-# This config models the Pascal GP102 (GeForceGTX 1080Ti)
-
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 60
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 11
--gpgpu_n_sub_partition_per_mchannel 2
-
-# Pascal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA TITAN X clock domains are adopted from
-# https://en.wikipedia.org/wiki/GeForce_10_series
--gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32
--gpgpu_shader_cta 32
--gpgpu_simd_model 1
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,1,4,1,1,6
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 1
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# SFU is 32-width in pascal, then dp units initiation is 1 cycle
--ptx_opcode_latency_int 4,13,4,5,145,4,4
--ptx_opcode_initiation_int 1,2,2,2,8,4,4
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 1,2,1,1,130
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
-# Pascal GP102 has 96KB Shared memory
-# Pascal GP102 has 64KB L1 cache
-# The default is to disable the L1 cache, unless cache modifieres is used
--gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8
--gpgpu_shmem_size 98304
--gmem_skip_L1D 1
-
-# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4
--gpgpu_cache:dl2_texture_only 0
-
-# 4 KB Inst.
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
-# 48 KB Tex
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
-
-# enable operand collector
-## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
--gpgpu_operand_collector_num_units_sp 20
--gpgpu_operand_collector_num_units_sfu 4
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
-# gpgpu_num_reg_banks should be increased to 32, but it gives an error!
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle
--gpgpu_max_insn_issue_per_warp 2
-
-# interconnection
--network_mode 1
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles). I.e.
-# Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 116
-
-# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits)
-# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition
-# the atom size of GDDR5X (the smallest read request) is 32 bytes
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 4
--gpgpu_dram_burst_length 8
--dram_data_command_freq_ratio 4 # GDDR5X is QDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
-
-# Use the same GDDR5 timing from hynix H5GQ1H24AFR
-# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
--gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
- CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
-
-# Pascal has four schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs
--power_simulation_enabled 1
--gpuwattch_xml_file gpuwattch_gtx1080Ti.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/bsmad_test/gpuwattch_gtx1080Ti.xml b/bsmad_test/gpuwattch_gtx1080Ti.xml
deleted file mode 100755
index 02619ff..0000000
--- a/bsmad_test/gpuwattch_gtx1080Ti.xml
+++ /dev/null
@@ -1,538 +0,0 @@
-<?xml version="1.0" ?>
-<component id="root" name="root">
- <component id="system" name="system">
- <!--McPAT will skip the components if number is set to 0 -->
- <param name="GPU_Architecture" value="1"/><!-- 0-G80; 1-Fermi; others not supported -->
- <param name="number_of_cores" value="28"/>
- <param name="architecture" value="1"/> <!-- fermi:1 quadro:2 other: undefined-->
- <param name="number_of_L1Directories" value="0"/>
- <param name="number_of_L2Directories" value="0"/>
- <param name="number_of_L2s" value="1"/> <!-- This number means how many L2 clusters in each cluster there can be multiple banks/ports -->
- <param name="number_of_L3s" value="0"/> <!-- This number means how many L3 clusters -->
- <param name="number_of_NoCs" value="1"/>
- <param name="homogeneous_cores" value="1"/><!--1 means homo -->
- <param name="homogeneous_L2s" value="1"/>
- <param name="homogeneous_L1Directorys" value="1"/>
- <param name="homogeneous_L2Directorys" value="1"/>
- <param name="homogeneous_L3s" value="1"/>
- <param name="homogeneous_ccs" value="1"/><!--cache coherece hardware -->
- <param name="homogeneous_NoCs" value="1"/>
- <param name="core_tech_node" value="23"/><!-- nm -->
- <param name="target_core_clockrate" value="1481"/><!--MHz -->
- <param name="temperature" value="380"/> <!-- Kelvin -->
- <param name="number_cache_levels" value="2"/>
- <param name="interconnect_projection_type" value="0"/><!--0: agressive wire technology; 1: conservative wire technology -->
- <param name="device_type" value="0"/><!--0: HP(High Performance Type); 1: LSTP(Low standby power) 2: LOP (Low Operating Power) -->
- <param name="longer_channel_device" value="1"/><!-- 0 no use; 1 use when possible -->
- <param name="machine_bits" value="32"/>
- <param name="virtual_address_width" value="32"/>
- <param name="physical_address_width" value="32"/>
- <param name="virtual_memory_page_size" value="4096"/>
- <param name="idle_core_power" value="1.59"/><!-- idle core power for GTX479 -->
- <!--param name="scaling_coefficients" value="10,0.0884816,10,10,8,10,4.12782,10,2.48832,10,10,10,4.29982,0.387764,0.0714269,0.14302,0.01,0.546811,0.485351,0.806633,0.818073,1.9207,100,100,100,87.9303,100,10,4.3548,10"/-->
- <param name="TOT_INST" value="10" />
- <param name="FP_INT" value="10" />
- <param name="IC_H" value="0.001" />
- <param name="IC_M" value="10" />
- <param name="DC_RH" value="1" />
- <param name="DC_RM" value="1" />
- <param name="DC_WH" value="1" />
- <param name="DC_WM" value="1" />
- <param name="TC_H" value="0.001" />
- <param name="TC_M" value="10" />
- <param name="CC_H" value="4.5071" />
- <param name="CC_M" value="10" />
- <param name="SHRD_ACC" value="10" />
- <param name="REG_RD" value="1.6294" />
- <param name="REG_WR" value="0.5031" />
- <param name="NON_REG_OPs" value="0.01" />
- <param name="SP_ACC" value="10" />
- <param name="SFU_ACC" value="0.0082" />
- <param name="FPU_ACC" value="0.4126" />
- <param name="MEM_RD" value="0.1234" />
- <param name="MEM_WR" value="0.001" />
- <param name="MEM_PRE" value="0.001" />
- <param name="L2_RH" value="100" />
- <param name="L2_RM" value="100" />
- <param name="L2_WH" value="100" />
- <param name="L2_WM" value="42.6966" />
- <param name="NOC_A" value="100" />
- <param name="PIPE_A" value="44.8085" />
- <param name="IDLE_CORE_N" value="2.0382"/>
- <param name="CONST_DYNAMICN" value="5.0005" />
- <stat name="num_idle_cores" value="0"/><!-- Average Number of idle cores during this period -->
- <stat name="total_cycles" value="total_cycles_match_mcpat"/>
- <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
- <stat name="busy_cycles" value="busy_cycles_match_mcpat"/>
- <!--This page size(B) is complete different from the page size in Main memo secction. this page size is the size of
- virtual memory from OS/Archi perspective; the page size in Main memo secction is the actuall physical line in a DRAM bank -->
- <!-- *********************** cores ******************* -->
- <component id="system.core0" name="core0">
- <!-- Core property -->
- <param name="clock_rate" value="1481"/>
- <param name="instruction_length" value="32"/>
- <param name="opcode_width" value="9"/>
- <!-- address width determins the tag_width in Cache, LSQ and buffers in cache controller
- default value is machine_bits, if not set -->
- <param name="machine_type" value="1"/><!-- 1 inorder; 0 OOO-->
- <!-- inorder/OoO -->
- <param name="number_hardware_threads" value="32"/>
- <!-- number_instruction_fetch_ports(icache ports) is always 1 in single-thread processor,
- it only may be more than one in SMT processors. BTB ports always equals to fetch ports since
- branch information in consective branch instructions in the same fetch group can be read out from BTB once.-->
- <param name="fetch_width" value="1"/>
- <!-- fetch_width determins the size of cachelines of L1 cache block -->
- <param name="number_instruction_fetch_ports" value="1"/>
- <param name="decode_width" value="1"/>
- <!-- decode_width determins the number of ports of the
- renaming table (both RAM and CAM) scheme -->
- <param name="issue_width" value="2"/>
- <!-- issue_width determins the number of ports of Issue window and other logic
- as in the complexity effective proccessors paper; issue_width==dispatch_width -->
- <param name="commit_width" value="2"/>
- <!-- commit_width determins the number of ports of register files -->
- <param name="fp_issue_width" value="1"/>
- <param name="prediction_width" value="0"/>
- <!-- number of branch instructions can be predicted simultannouesl-->
- <!-- Current version of McPAT does not distinguish int and floating point pipelines
- Theses parameters are reserved for future use.-->
- <param name="pipelines_per_core" value="1,1"/>
- <!--integer_pipeline and floating_pipelines, if the floating_pipelines is 0, then the pipeline is shared-->
- <param name="pipeline_depth" value="8,8"/>
- <!-- pipeline depth of int and fp, if pipeline is shared, the second number is the average cycles of fp ops -->
- <!-- issue and exe unit-->
- <param name="ALU_per_core" value="32"/>
- <!-- contains an adder, a shifter, and a logical unit -->
- <param name="MUL_per_core" value="4"/>
- <!-- For MUL and Div -->
- <param name="FPU_per_core" value="32"/>
- <!-- buffer between IF and ID stage -->
- <param name="instruction_buffer_size" value="1"/>
- <!-- buffer between ID and sche/exe stage -->
- <param name="decoded_stream_buffer_size" value="1"/>
- <param name="instruction_window_scheme" value="0"/><!-- 0 PHYREG based, 1 RSBASED-->
- <!-- McPAT support 2 types of OoO cores, RS based and physical reg based-->
- <param name="instruction_window_size" value="1"/>
- <param name="fp_instruction_window_size" value="1"/>
- <!-- the instruction issue Q as in Alpha 21264; The RS as in Intel P6 -->
- <param name="ROB_size" value="0"/>
- <!-- each in-flight instruction has an entry in ROB -->
- <!-- registers -->
- <!-- SM parameters Added by Syed Gilani -->
- <param name="rf_banks" value="32"/>
- <param name="simd_width" value="32"/>
- <param name="collector_units" value="32"/>
- <param name="core_clock_ratio" value="2"/>
- <param name="warp_size" value="32"/>
-
- <param name="archi_Regs_IRF_size" value="65536"/>
- <param name="archi_Regs_FRF_size" value="32"/>
- <!-- if OoO processor, phy_reg number is needed for renaming logic,
- renaming logic is for both integer and floating point insts. -->
- <param name="phy_Regs_IRF_size" value="32"/>
- <param name="phy_Regs_FRF_size" value="32"/>
- <!-- rename logic -->
- <param name="rename_scheme" value="0"/>
- <!-- can be RAM based(0) or CAM based(1) rename scheme
- RAM-based scheme will have free list, status table;
- CAM-based scheme have the valid bit in the data field of the CAM
- both RAM and CAM need RAM-based checkpoint table, checkpoint_depth=# of in_flight instructions;
- Detailed RAT Implementation see TR -->
- <param name="register_windows_size" value="0"/>
- <!-- how many windows in the windowed register file, sun processors;
- no register windowing is used when this number is 0 -->
- <!-- In OoO cores, loads and stores can be issued whether inorder(Pentium Pro) or (OoO)out-of-order(Alpha),
- They will always try to exeute out-of-order though. -->
- <param name="LSU_order" value="inorder"/>
- <param name="store_buffer_size" value="32"/>
- <!-- By default, in-order cores do not have load buffers -->
- <param name="load_buffer_size" value="32"/>
- <!-- number of ports refer to sustainable concurrent memory accesses -->
- <param name="memory_ports" value="2"/>
- <!-- max_allowed_in_flight_memo_instructions determins the # of ports of load and store buffer
- as well as the ports of Dcache which is connected to LSU -->
- <!-- dual-pumped Dcache can be used to save the extra read/write ports -->
- <param name="RAS_size" value="1"/>
- <!-- general stats, defines simulation periods;require total, idle, and busy cycles for senity check -->
- <!-- please note: if target architecture is X86, then all the instrucions refer to (fused) micro-ops -->
- <stat name="total_instructions" value="total_instructions_match_mcpat"/>
- <stat name="int_instructions" value="int_instruction_match_mcpat"/>
- <stat name="fp_instructions" value="flt_instruction_match_mcpat"/>
- <stat name="branch_instructions" value="branch_instruction_match_mcpat"/>
- <stat name="branch_mispredictions" value="0"/>
- <stat name="load_instructions" value="load_instruction_match_mcpat"/>
- <stat name="store_instructions" value="store_instruction_match_mcpat"/>
- <stat name="committed_instructions" value="total_instructions_match_mcpat"/>
- <stat name="committed_int_instructions" value="int_instruction_match_mcpat"/>
- <stat name="committed_fp_instructions" value="flt_instruction_match_mcpat"/>
- <stat name="pipeline_duty_cycle" value="0.6"/><!--<=1, runtime_ipc/peak_ipc; averaged for all cores if homogenous -->
- <!-- the following cycle stats are used for heterogeneouse cores only,
- please ignore them if homogeneouse cores -->
- <stat name="total_cycles" value="total_cycles_match_mcpat"/>
- <stat name="idle_cycles" value="idle_cycles_match_mcpat"/>
- <stat name="busy_cycles" value="busy_cycles_match_mcpat"/>
- <!-- instruction buffer stats -->
- <!-- ROB stats, both RS and Phy based OoOs have ROB
- performance simulator should capture the difference on accesses,
- otherwise, McPAT has to guess based on number of commited instructions. -->
- <stat name="ROB_reads" value="263886"/>
- <stat name="ROB_writes" value="263886"/>
- <!-- RAT accesses -->
- <stat name="rename_accesses" value="263886"/>
- <stat name="fp_rename_accesses" value="263886"/>
- <!-- decode and rename stage use this, should be total ic - nop -->
- <!-- Inst window stats -->
- <stat name="inst_window_reads" value="263886"/>
- <stat name="inst_window_writes" value="263886"/>
- <stat name="inst_window_wakeup_accesses" value="263886"/>
- <stat name="fp_inst_window_reads" value="263886"/>
- <stat name="fp_inst_window_writes" value="263886"/>
- <stat name="fp_inst_window_wakeup_accesses" value="263886"/>
- <!-- RF accesses -->
- <stat name="int_regfile_reads" value="int_register_read_access_match_mcpat"/>
- <stat name="float_regfile_reads" value="int_register_write_access_match_mcpat"/>
- <stat name="int_regfile_writes" value="float_register_read_access_match_mcpat"/>
- <stat name="float_regfile_writes" value="float_register_write_access_match_mcpat"/>
-
- <!-- The following stat is for operand collector power - Added by Syed -->
- <stat name="non_rf_operands" value="0"/>
-
- <!-- accesses to the working reg -->
- <stat name="function_calls" value="0"/>
- <stat name="context_switches" value="0"/> <!--not used in the McPAT -->
- <!-- Number of Windowes switches (number of function calls and returns)-->
- <!-- Alu stats by default, the processor has one FPU that includes the divider and
- multiplier. The fpu accesses should include accesses to multiplier and divider -->
- <stat name="ialu_accesses" value="ialu_accesses_match_mcpat"/>
- <stat name="fpu_accesses" value="fpu_accesses_match_mcpat"/>
- <stat name="mul_accesses" value="mul_accesses_match_mcpat"/>
- <stat name="cdb_alu_accesses" value="0"/>
- <stat name="cdb_mul_accesses" value="0"/>
- <stat name="cdb_fpu_accesses" value="0"/>
- <!-- multiple cycle accesses should be counted multiple times,
- otherwise, McPAT can use internal counter for different floating point instructions
- to get final accesses. But that needs detailed info for floating point inst mix -->
- <!-- currently the performance simulator should
- make sure all the numbers are final numbers,
- including the explicit read/write accesses,
- and the implicite accesses such as replacements and etc.
- Future versions of McPAT may be able to reason the implicite access
- based on param and stats of last level cache
- The same rule applies to all cache access stats too! -->
- <!-- following is AF for max power computation.
- Do not change them, unless you understand them-->
- <stat name="IFU_duty_cycle" value="0.25"/>
- <stat name="LSU_duty_cycle" value="0.25"/>
- <stat name="MemManU_I_duty_cycle" value="1"/>
- <stat name="MemManU_D_duty_cycle" value="0.25"/>
- <stat name="ALU_duty_cycle" value="0.9"/>
- <stat name="MUL_duty_cycle" value="0.5"/>
- <stat name="FPU_duty_cycle" value="1"/><!-- FPU numbers are already average -->
- <stat name="ALU_cdb_duty_cycle" value="0.9"/>
- <stat name="MUL_cdb_duty_cycle" value="0.5"/>
- <stat name="FPU_cdb_duty_cycle" value="15"/>
- <component id="system.core0.predictor" name="PBT">
- <!-- branch predictor; tournament predictor see Alpha implementation -->
- <param name="local_predictor_size" value="10,3"/>
- <param name="local_predictor_entries" value="1024"/>
- <param name="global_predictor_entries" value="4096"/>
- <param name="global_predictor_bits" value="2"/>
- <param name="chooser_predictor_entries" value="4096"/>
- <param name="chooser_predictor_bits" value="2"/>
- <!-- These parameters can be combined like below in next version
- <param name="load_predictor" value="10,3,1024"/>
- <param name="global_predictor" value="4096,2"/>
- <param name="predictor_chooser" value="4096,2"/>
- -->
- </component>
- <component id="system.core0.itlb" name="itlb">
- <param name="number_entries" value="1"/>
- <stat name="total_accesses" value="0"/>
- <stat name="total_misses" value="0"/>
- <stat name="conflicts" value="0"/>
- <!-- there is no write requests to itlb although writes happen to itlb after miss,
- which is actually a replacement -->
- </component>
- <component id="system.core0.icache" name="icache">
- <!-- there is no write requests to itlb although writes happen to it after miss,
- which is actually a replacement -->
- <param name="icache_config" value="16384,128,4,1,1,3,8,0"/>
- <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
- <!-- cache_policy;//0 no write or write-though with non-write allocate;1 write-back with write-allocate -->
- <param name="buffer_sizes" value="16, 16, 16,0"/>
- <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
- <stat name="read_accesses" value="total_instructions_match_mcpat"/>
- <stat name="read_misses" value="0"/>
- <stat name="conflicts" value="0"/>
- </component>
- <component id="system.core0.dtlb" name="dtlb">
- <param name="number_entries" value="1"/>
- <stat name="total_accesses" value="0"/>
- <stat name="total_misses" value="0"/>
- <stat name="conflicts" value="0"/>
- </component>
- <component id="system.core0.ccache" name="ccache">
- <!-- all the buffer related are optional -->
- <param name="ccache_config" value="16384,64,2,1,1,3,8,0"/>
- <param name="buffer_sizes" value="16, 16, 16, 0"/>
- <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
- <stat name="read_accesses" value="ccache_read_accesses_match_mcpat"/>
- <stat name="write_accesses" value="0"/>
- <stat name="read_misses" value="ccache_read_misses_match_mcpat"/>
- <stat name="write_misses" value="0"/>
- <stat name="conflicts" value="0"/>
- </component>
- <component id="system.core0.tcache" name="tcache">
- <!-- all the buffer related are optional -->
- <param name="tcache_config" value="49152,128,8,1,1,3,8,0"/>
- <param name="buffer_sizes" value="16, 16, 16, 0"/>
- <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
- <stat name="read_accesses" value="tcache_read_accesses_match_mcpat"/>
- <stat name="write_accesses" value="0"/>
- <stat name="read_misses" value="tcache_read_misses_match_mcpat"/>
- <stat name="write_misses" value="0"/>
- <stat name="conflicts" value="0"/>
- </component>
- <!--model the shared memory by mimicing dcache-->
- <component id="system.core0.sharedmemory" name="sharedmemory">
- <!-- all the buffer related are optional -->
- <param name="sharedmemory_config" value="98304,16,1,16,1,3,16,0"/>
- <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
- <param name="buffer_sizes" value="16, 16, 16, 16"/>
- <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
- <stat name="read_accesses" value="sharedmemory_read_access_match_mcpat"/>
- <stat name="write_accesses" value="sharedmemory_write_access_match_mcpat"/>
- <stat name="read_misses" value="0"/>
- <stat name="write_misses" value="0"/>
- <stat name="conflicts" value="0"/>
- </component>
- <component id="system.core0.dcache" name="dcache">
- <!-- all the buffer related are optional -->
- <param name="dcache_config" value="16384,32,4,1,1,3,8,0"/>
- <param name="buffer_sizes" value="16, 16, 16, 0"/>
- <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
- <stat name="read_accesses" value="dcache_read_access_match_mcpat"/>
- <stat name="write_accesses" value="dcache_write_access_match_mcpat"/>
- <stat name="read_misses" value="dcache_read_miss_match_mcpat"/>
- <stat name="write_misses" value="dcache_write_miss_match_mcpat"/>
- <stat name="conflicts" value="0"/>
- </component>
- <component id="system.core0.BTB" name="BTB">
- <!-- all the buffer related are optional -->
- <param name="BTB_config" value="8192,4,2,1, 1,3"/>
- <!-- the parameters are capacity,block_width,associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
- </component>
- </component>
- <component id="system.L1Directory0" name="L1Directory0">
- <param name="Directory_type" value="0"/>
- <!--0 cam based shadowed tag. 1 directory cache -->
- <param name="Dir_config" value="2048,1,0,1, 4, 4,8"/>
- <!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
- <param name="buffer_sizes" value="8, 8, 8, 8"/>
- <!-- all the buffer related are optional -->
- <param name="clockrate" value="1400"/>
- <param name="ports" value="1,1,1"/>
- <!-- number of r, w, and rw search ports -->
- <param name="device_type" value="0"/>
- <!-- altough there are multiple access types,
- Performance simulator needs to cast them into reads or writes
- e.g. the invalidates can be considered as writes -->
- <stat name="read_accesses" value="800000"/>
- <stat name="write_accesses" value="27276"/>
- <stat name="read_misses" value="1632"/>
- <stat name="write_misses" value="183"/>
- <stat name="conflicts" value="20"/>
- <stat name="duty_cycle" value="0.45"/>
- </component>
- <component id="system.L2Directory0" name="L2Directory0">
- <param name="Directory_type" value="1"/>
- <!--0 cam based shadowed tag. 1 directory cache -->
- <param name="Dir_config" value="1048576,16,16,1,2, 100"/>
- <!-- the parameters are capacity,block_width, associativity,bank, throughput w.r.t. core clock, latency w.r.t. core clock,-->
- <param name="buffer_sizes" value="8, 8, 8, 8"/>
- <!-- all the buffer related are optional -->
- <param name="clockrate" value="1400"/>
- <param name="ports" value="1,1,1"/>
- <!-- number of r, w, and rw search ports -->
- <param name="device_type" value="0"/>
- <!-- altough there are multiple access types,
- Performance simulator needs to cast them into reads or writes
- e.g. the invalidates can be considered as writes -->
- <stat name="read_accesses" value="0"/>
- <stat name="write_accesses" value="0"/>
- <stat name="read_misses" value="0"/>
- <stat name="write_misses" value="0"/>
- <stat name="conflicts" value="0"/>
- <stat name="duty_cycle" value="0.45"/>
- </component>
- <component id="system.L20" name="L20">
- <!-- all the buffer related are optional -->
- <param name="L2_config" value="131072,128,16,1, 4,23, 64, 1"/>
- <!-- consider 4-way bank interleaving for Niagara 1 -->
- <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
- <param name="buffer_sizes" value="16, 16, 16, 16"/>
- <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
- <param name="clockrate" value="2962"/>
- <param name="ports" value="1,1,1"/>
- <!-- number of r, w, and rw ports -->
- <param name="device_type" value="0"/>
- <stat name="read_accesses" value="200000"/>
- <stat name="write_accesses" value="0"/>
- <stat name="read_misses" value="0"/>
- <stat name="write_misses" value="0"/>
- <stat name="conflicts" value="0"/>
- <stat name="duty_cycle" value="0.5"/>
- </component>
-
-<!--**********************************************************************-->
-<component id="system.L30" name="L30">
- <param name="L3_config" value="1048576,64,16,1, 2,100, 64,1"/>
- <!-- the parameters are capacity,block_width, associativity, bank, throughput w.r.t. core clock, latency w.r.t. core clock,output_width, cache policy -->
- <param name="clockrate" value="3500"/>
- <param name="ports" value="1,1,1"/>
- <!-- number of r, w, and rw ports -->
- <param name="device_type" value="0"/>
- <param name="buffer_sizes" value="16, 16, 16, 16"/>
- <!-- cache controller buffer sizes: miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
- <stat name="read_accesses" value="58824"/>
- <stat name="write_accesses" value="27276"/>
- <stat name="read_misses" value="1632"/>
- <stat name="write_misses" value="183"/>
- <stat name="conflicts" value="0"/>
- <stat name="duty_cycle" value="0.35"/>
- </component>
-
-
-<!--**********************************************************************-->
- <component id="system.NoC0" name="noc0">
- <param name="clockrate" value="700"/>
- <param name="type" value="1"/>
- <!-- 1 NoC, O bus -->
- <param name="horizontal_nodes" value="2"/>
- <param name="vertical_nodes" value="1"/>
- <param name="has_global_link" value="0"/>
- <!-- 1 has global link, 0 does not have global link -->
- <param name="link_throughput" value="1"/><!--w.r.t clock -->
- <param name="link_latency" value="1"/><!--w.r.t clock -->
- <!-- througput >= latency -->
- <!-- Router architecture -->
- <param name="input_ports" value="6"/>
- <param name="output_ports" value="6"/>
- <param name="virtual_channel_per_port" value="1"/>
- <!-- input buffer; in classic routers only input ports need buffers -->
- <param name="flit_bits" value="32"/>
- <param name="input_buffer_entries_per_vc" value="1"/><!--VCs within the same ports share input buffers whose size is propotional to the number of VCs-->
- <param name="chip_coverage" value="1"/>
- <!-- When multiple NOC present, one NOC will cover part of the whole chip. chip_coverage <=1 -->
- <stat name="total_accesses" value="0"/>
- <!-- This is the number of total accesses within the whole network not for each router -->
- <stat name="duty_cycle" value="0.6"/>
- </component>
-<!--**********************************************************************-->
-<!--**********************************************************************-->
-
- <component id="system.mem" name="mem">
- <!-- Main memory property -->
- <param name="mem_tech_node" value="23"/>
- <param name="device_clock" value="200"/><!--MHz, this is clock rate of the actual memory device, not the FSB -->
- <param name="peak_transfer_rate" value="3200"/><!--MB/S-->
- <param name="internal_prefetch_of_DRAM_chip" value="4"/>
- <!-- 2 for DDR, 4 for DDR2, 8 for DDR3...-->
- <!-- the device clock, peak_transfer_rate, and the internal prefetch decide the DIMM property -->
- <!-- above numbers can be easily found from Wikipedia -->
- <param name="capacity_per_channel" value="4096"/> <!-- MB -->
- <!-- capacity_per_Dram_chip=capacity_per_channel/number_of_dimms/number_ranks/Dram_chips_per_rank
- Current McPAT assumes single DIMMs are used.-->
- <param name="number_ranks" value="2"/>
- <param name="num_banks_of_DRAM_chip" value="6"/>
- <param name="Block_width_of_DRAM_chip" value="64"/> <!-- B -->
- <param name="output_width_of_DRAM_chip" value="8"/>
- <!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
- <!--number of Dram_chips_per_rank=" 72/output_width_of_DRAM_chip-->
- <param name="page_size_of_DRAM_chip" value="8"/> <!-- 8 or 16 -->
- <param name="burstlength_of_DRAM_chip" value="8"/>
- <stat name="memory_accesses" value="1052"/>
- <stat name="memory_reads" value="1052"/>
- <stat name="memory_writes" value="1052"/>
- </component>
- <component id="system.mc" name="mc">
- <!-- Memeory controllers are for DDR(2,3...) DIMMs -->
- <!-- current version of McPAT uses published values for base parameters of memory controller
- improvments on MC will be added in later versions. -->
- <param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
- <param name="mc_clock" value="1848"/><!--DIMM IO bus clock rate MHz DDR2-400 for Niagara 1-->
- <param name="peak_transfer_rate" value="29568"/><!--MB/S Syed: GTX 470 has 177.4GB/s mem transfer rate with 6 MCs -->
- <param name="block_size" value="64"/><!--B-->
- <param name="number_mcs" value="6"/><!-- 6 GDDR5 memory controllers -->
- <!-- current McPAT only supports homogeneous memory controllers -->
- <param name="memory_channels_per_mc" value="2"/>
- <param name="number_ranks" value="1"/>
- <param name="withPHY" value="0"/>
- <!-- # of ranks of each channel-->
- <param name="req_window_size_per_channel" value="16"/>
- <param name="IO_buffer_size_per_channel" value="16"/>
- <param name="databus_width" value="32"/>
- <param name="addressbus_width" value="32"/>
- <param name="PRT_entries" value="32"/>
- <!-- # of empirical DRAM model parameter -->
- <param name="dram_cmd_coeff" value="0"/>
- <param name="dram_act_coeff" value="0"/>
- <param name="dram_nop_coeff" value="0"/>
- <param name="dram_activity_coeff" value="0"/>
- <param name="dram_pre_coeff" value="3.8475e-8f"/>
- <param name="dram_rd_coeff" value="7.74707143e-8f"/>
- <param name="dram_wr_coeff" value="3.54664286e-8f"/>
- <param name="dram_req_coeff" value="0"/>
- <param name="dram_const_coeff" value="0"/>
-
- <!-- McPAT will add the control bus width to the addressbus width automatically -->
- <stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
- <stat name="memory_reads" value="memory_reads_match_mcpat"/>
- <stat name="memory_writes" value="memory_writes_match_mcpat"/>
- <!-- McPAT does not track individual mc, instead, it takes the total accesses and calculate
- the average power per MC or per channel. This is sufficent for most application.
- Further trackdown can be easily added in later versions. -->
- </component>
-<!--**********************************************************************-->
- <component id="system.niu" name="niu">
- <!-- On chip 10Gb Ethernet NIC, including XAUI Phy and MAC controller -->
- <!-- For a minimum IP packet size of 84B at 10Gb/s, a new packet arrives every 67.2ns.
- the low bound of clock rate of a 10Gb MAC is 150Mhz -->
- <param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
- <param name="clockrate" value="350"/>
- <param name="number_units" value="0"/> <!-- unlike PCIe and memory controllers, each Ethernet controller only have one port -->
- <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
- <stat name="total_load_perc" value="0.7"/> <!-- ratio of total achived load to total achivable bandwidth -->
- <!-- McPAT does not track individual nic, instead, it takes the total accesses and calculate
- the average power per nic or per channel. This is sufficent for most application. -->
- </component>
-<!--**********************************************************************-->
- <component id="system.pcie" name="pcie">
- <!-- On chip PCIe controller, including Phy-->
- <!-- For a minimum PCIe packet size of 84B at 8Gb/s per lane (PCIe 3.0), a new packet arrives every 84ns.
- the low bound of clock rate of a PCIe per lane logic is 120Mhz -->
- <param name="type" value="0"/> <!-- 1: low power; 0 high performance -->
- <param name="withPHY" value="1"/>
- <param name="clockrate" value="350"/>
- <param name="number_units" value="0"/>
- <param name="num_channels" value="8"/> <!-- 2 ,4 ,8 ,16 ,32 -->
- <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
- <stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth -->
- <!-- McPAT does not track individual pcie controllers, instead, it takes the total accesses and calculate
- the average power per pcie controller or per channel. This is sufficent for most application. -->
- </component>
-<!--**********************************************************************-->
- <component id="system.flashc" name="flashc">
- <param name="number_flashcs" value="0"/>
- <param name="type" value="1"/> <!-- 1: low power; 0 high performance -->
- <param name="withPHY" value="1"/>
- <param name="peak_transfer_rate" value="200"/><!--Per controller sustainable reak rate MB/S -->
- <stat name="duty_cycle" value="1.0"/> <!-- achievable max load <= 1.0 -->
- <stat name="total_load_perc" value="0.7"/> <!-- Percentage of total achived load to total achivable bandwidth -->
- <!-- McPAT does not track individual flash controller, instead, it takes the total accesses and calculate
- the average power per fc or per channel. This is sufficent for most application -->
- </component>
-<!--**********************************************************************-->
-
- </component>
-</component>
diff --git a/bsmad_test/out.txt b/bsmad_test/out.txt
deleted file mode 100644
index 4e95cb1..0000000
--- a/bsmad_test/out.txt
+++ /dev/null
@@ -1,1837 +0,0 @@
-
-
- *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] ***
-
-
-GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable:
- 1=functional simulation only, 0=detailed performance simulator)
-GPGPU-Sim: Configuration options:
-
--network_mode 1 # Interconnection network mode
--inter_config_file config_fermi_islip.icnt # Interconnection network config file
--gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries
--gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable]
--gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus
--gpgpu_ptx_force_max_capability 60 # Force maximum compute capability
--gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file
--gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file
--gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output
--gpgpu_simd_model 1 # 1 = post-dominator
--gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>}
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>}
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip)
--gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss)
--n_regfile_gating_group 4 # group of lanes that should be read/written together)
--gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations
--gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations
--gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)
--gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8)
--gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16)
--gpgpu_n_clusters 28 # number of processing clusters
--gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster
--gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer
--gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer
--gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16)
--gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on)
--gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check
--gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from
--gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from
--gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled)
--gpgpu_num_reg_banks 32 # Number of register banks (default = 8)
--gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off)
--gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4)
--gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4)
--gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2)
--gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0)
--gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0)
--gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0)
--gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now)
--gpgpu_num_sched_per_core 2 # Number of warp schedulers per core
--gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler
--gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)
--gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_num_sp_units 4 # Number of SP units (default=1)
--gpgpu_num_sfu_units 1 # Number of SF units (default=1)
--gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything
--gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto
--gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled)
--gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul)
--gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i
--l2_ideal 0 # Use a ideal L2 cache that always hit
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only
--gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu
--gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module
--gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller
--gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs
--gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip
--gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip
--gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR)
--gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle)
--dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR)
--gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
--rop_latency 120 # ROP queue latency (default 85)
--dram_latency 100 # DRAM latency (default 30)
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>}
--gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address
--gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits
--gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file
--power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off)
--power_per_cycle_dump 0 # Dump detailed power output each cycle
--power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off)
--power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest)
--steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off)
--steady_state_definition 8:4 # allowed deviation:number of samples
--gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>}
--liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print)
--gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call
--gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call
--gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off)
--gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now)
--gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1)
--gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>}
--gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU
--gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger
--visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off)
--visualizer_outputfile NULL # Specifies the output log file for visualizer
--visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest)
--trace_enabled 0 # Turn on traces
--trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none
--trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0
--trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all)
--enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On)
--ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics.
--gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0
--gpgpu_cdp_enabled 0 # Turn on CDP
--save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx
--keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs
--gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file
--ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,19,25,145,1
--ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30
--ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335
--ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,4,4,32,1
--ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5
--ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130
--cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600
-DRAM Timing Options:
-nbk 16 # number of banks
-CCD 2 # column to column delay
-RRD 6 # minimal delay between activation of rows in different banks
-RCD 12 # row to column delay
-RAS 28 # time needed to activate row
-RP 12 # time needed to precharge (deactivate) row
-RC 40 # row cycle time
-CDLR 5 # switching from write to read (changes tWTR)
-WR 12 # last data-in to row precharge
-CL 12 # CAS latency
-WL 4 # Write latency
-nbkgrp 1 # number of bank groups
-CCDL 0 # column to column delay between accesses to different bank groups
-RTPL 0 # read to precharge delay between accesses to different bank groups
-Total number of memory sub partition = 22
-addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0
-addr_dec_mask[BK] = 0000000000007080 high:15 low:7
-addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15
-addr_dec_mask[COL] = 0000000000000f7f high:12 low:0
-addr_dec_mask[BURST] = 000000000000001f high:5 low:0
-sub_partition_id_mask = 0000000000000080
-GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000
-GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364
-*** Initializing Memory Statistics ***
-GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID)
-GPGPU-Sim uArch: Memory nodes ID start from index: 28
-GPGPU-Sim uArch: 0 1 2 3 4 5 6
-GPGPU-Sim uArch: 7 8 9 10 11 12 13
-GPGPU-Sim uArch: 14 15 16 17 18 19 20
-GPGPU-Sim uArch: 21 22 23 24 25 26 27
-GPGPU-Sim uArch: 28 29 30 31 32 33 34
-GPGPU-Sim uArch: 35 36 37 38 39 40 41
-GPGPU-Sim uArch: 42 43 44 45 46 47 48
-GPGPU-Sim uArch: 49
-GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID)
-GPGPU-Sim uArch: Memory nodes start from ID: 28
-GPGPU-Sim uArch: 0 1 2 3 4 5 6
-GPGPU-Sim uArch: 7 8 9 10 11 12 13
-GPGPU-Sim uArch: 14 15 16 17 18 19 20
-GPGPU-Sim uArch: 21 22 23 24 25 26 27
-GPGPU-Sim uArch: 28 29 30 31 32 33 34
-GPGPU-Sim uArch: 35 36 37 38 39 40 41
-GPGPU-Sim uArch: 42 43 44 45 46 47 48
-GPGPU-Sim uArch: 49
-1739ba94823ccfb8e12f742738e8e16e /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad
-GPGPU-Sim uArch: performance model initialization complete.
-GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default
-self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad
-Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad "
-Parsing file _cuobjdump_complete_output_leydyg
-######### cuobjdump parser ########
-## Adding new section PTX
-Adding ptx filename: _cuobjdump_1.ptx
-Adding arch: sm_50
-Adding identifier: default
-Done parsing!!!
-GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1
-WARNING: No guarantee that PTX will be parsed for SM version 50
-GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done.
-GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_...
-GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_
-GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'.
-BEGINNING CUSTOM PTX.
-ENDING CUSTOM PTX.
-GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done.
-GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_...
-GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2;
-GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3;
-GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_
-GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'.
-GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx
-Adding _cuobjdump_1.ptx with cubin handle 1
-GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_8pgp00"
-Running: cat _ptx_8pgp00 | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_ZhKBsL
-GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_ZhKBsL --output-file /dev/null 2> _ptx_8pgp00info"
-GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352
-GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344
-GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_8pgp00 _ptx2_ZhKBsL _ptx_8pgp00info"
-GPGPU-Sim PTX: loading globals with explicit initializers...
-GPGPU-Sim PTX: finished loading globals (0 bytes total).
-GPGPU-Sim PTX: loading constants with explicit initializers... done.
-GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1
-GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes
-GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes
-GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes
-GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes
-GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Network latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Flit latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Fragmentation average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Injected packet rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Accepted packet rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Injected flit rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Accepted flit rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Injected packet size average = -nan (1 samples)
-Accepted packet size average = -nan (1 samples)
-Hops average = -nan (1 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Network latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Flit latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Fragmentation average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Injected packet rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Accepted packet rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Injected flit rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Accepted flit rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Injected packet size average = -nan (2 samples)
-Accepted packet size average = -nan (2 samples)
-Hops average = -nan (2 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i
-GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0
-bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Network latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Flit latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Fragmentation average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Injected packet rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Accepted packet rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Injected flit rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Accepted flit rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Injected packet size average = -nan (3 samples)
-Accepted packet size average = -nan (3 samples)
-Hops average = -nan (3 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1)
-GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_'
-GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit
-GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0)
-GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 16:03:17 2017
-GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA
diff --git a/bsmad_test/output b/bsmad_test/output
deleted file mode 100644
index db0d524..0000000
--- a/bsmad_test/output
+++ /dev/null
@@ -1,2338 +0,0 @@
-
-
- *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] ***
-
-
-GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable:
- 1=functional simulation only, 0=detailed performance simulator)
-GPGPU-Sim: Configuration options:
-
--network_mode 1 # Interconnection network mode
--inter_config_file config_fermi_islip.icnt # Interconnection network config file
--gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries
--gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable]
--gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus
--gpgpu_ptx_force_max_capability 60 # Force maximum compute capability
--gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file
--gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file
--gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output
--gpgpu_simd_model 1 # 1 = post-dominator
--gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>}
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>}
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip)
--gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss)
--n_regfile_gating_group 4 # group of lanes that should be read/written together)
--gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations
--gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations
--gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)
--gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8)
--gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16)
--gpgpu_n_clusters 28 # number of processing clusters
--gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster
--gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer
--gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer
--gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16)
--gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on)
--gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check
--gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from
--gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from
--gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled)
--gpgpu_num_reg_banks 32 # Number of register banks (default = 8)
--gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off)
--gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4)
--gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4)
--gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2)
--gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0)
--gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0)
--gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0)
--gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now)
--gpgpu_num_sched_per_core 2 # Number of warp schedulers per core
--gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler
--gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)
--gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_num_sp_units 4 # Number of SP units (default=1)
--gpgpu_num_sfu_units 1 # Number of SF units (default=1)
--gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything
--gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto
--gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled)
--gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul)
--gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i
--l2_ideal 0 # Use a ideal L2 cache that always hit
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only
--gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu
--gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module
--gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller
--gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs
--gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip
--gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip
--gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR)
--gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle)
--dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR)
--gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
--rop_latency 120 # ROP queue latency (default 85)
--dram_latency 100 # DRAM latency (default 30)
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>}
--gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address
--gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits
--gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file
--power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off)
--power_per_cycle_dump 0 # Dump detailed power output each cycle
--power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off)
--power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest)
--steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off)
--steady_state_definition 8:4 # allowed deviation:number of samples
--gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>}
--liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print)
--gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call
--gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call
--gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off)
--gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now)
--gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1)
--gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>}
--gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU
--gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger
--visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off)
--visualizer_outputfile NULL # Specifies the output log file for visualizer
--visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest)
--trace_enabled 0 # Turn on traces
--trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none
--trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0
--trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all)
--enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On)
--ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics.
--gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0
--gpgpu_cdp_enabled 0 # Turn on CDP
--save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx
--keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs
--gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file
--ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,19,25,145,1
--ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30
--ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335
--ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,4,4,32,1
--ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5
--ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130
--cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600
-DRAM Timing Options:
-nbk 16 # number of banks
-CCD 2 # column to column delay
-RRD 6 # minimal delay between activation of rows in different banks
-RCD 12 # row to column delay
-RAS 28 # time needed to activate row
-RP 12 # time needed to precharge (deactivate) row
-RC 40 # row cycle time
-CDLR 5 # switching from write to read (changes tWTR)
-WR 12 # last data-in to row precharge
-CL 12 # CAS latency
-WL 4 # Write latency
-nbkgrp 1 # number of bank groups
-CCDL 0 # column to column delay between accesses to different bank groups
-RTPL 0 # read to precharge delay between accesses to different bank groups
-Total number of memory sub partition = 22
-addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0
-addr_dec_mask[BK] = 0000000000007080 high:15 low:7
-addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15
-addr_dec_mask[COL] = 0000000000000f7f high:12 low:0
-addr_dec_mask[BURST] = 000000000000001f high:5 low:0
-sub_partition_id_mask = 0000000000000080
-GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000
-GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364
-*** Initializing Memory Statistics ***
-GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID)
-GPGPU-Sim uArch: Memory nodes ID start from index: 28
-GPGPU-Sim uArch: 0 1 2 3 4 5 6
-GPGPU-Sim uArch: 7 8 9 10 11 12 13
-GPGPU-Sim uArch: 14 15 16 17 18 19 20
-GPGPU-Sim uArch: 21 22 23 24 25 26 27
-GPGPU-Sim uArch: 28 29 30 31 32 33 34
-GPGPU-Sim uArch: 35 36 37 38 39 40 41
-GPGPU-Sim uArch: 42 43 44 45 46 47 48
-GPGPU-Sim uArch: 49
-GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID)
-GPGPU-Sim uArch: Memory nodes start from ID: 28
-GPGPU-Sim uArch: 0 1 2 3 4 5 6
-GPGPU-Sim uArch: 7 8 9 10 11 12 13
-GPGPU-Sim uArch: 14 15 16 17 18 19 20
-GPGPU-Sim uArch: 21 22 23 24 25 26 27
-GPGPU-Sim uArch: 28 29 30 31 32 33 34
-GPGPU-Sim uArch: 35 36 37 38 39 40 41
-GPGPU-Sim uArch: 42 43 44 45 46 47 48
-GPGPU-Sim uArch: 49
-733602e7cd2fc7896e7fece60068330a /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad
-GPGPU-Sim uArch: performance model initialization complete.
-GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default
-self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad
-Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad "
-Parsing file _cuobjdump_complete_output_Fvj0UD
-######### cuobjdump parser ########
-## Adding new section PTX
-Adding ptx filename: _cuobjdump_1.ptx
-Adding arch: sm_50
-Adding identifier: default
-Done parsing!!!
-GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1
-WARNING: No guarantee that PTX will be parsed for SM version 50
-GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done.
-GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_...
-GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_
-GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'.
-BEGINNING CUSTOM PTX.
-ENDING CUSTOM PTX.
-GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done.
-GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_...
-GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2;
-GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3;
-GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_
-GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'.
-GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx
-Adding _cuobjdump_1.ptx with cubin handle 1
-GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_qiCCrA"
-Running: cat _ptx_qiCCrA | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_zIGfYw
-GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_zIGfYw --output-file /dev/null 2> _ptx_qiCCrAinfo"
-GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352
-GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344
-GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_qiCCrA _ptx2_zIGfYw _ptx_qiCCrAinfo"
-GPGPU-Sim PTX: loading globals with explicit initializers...
-GPGPU-Sim PTX: finished loading globals (0 bytes total).
-GPGPU-Sim PTX: loading constants with explicit initializers... done.
-GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1
-GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes
-GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes
-GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes
-GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes
-GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Network latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Flit latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Fragmentation average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Injected packet rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Accepted packet rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Injected flit rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Accepted flit rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Injected packet size average = -nan (1 samples)
-Accepted packet size average = -nan (1 samples)
-Hops average = -nan (1 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Network latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Flit latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Fragmentation average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Injected packet rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Accepted packet rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Injected flit rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Accepted flit rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Injected packet size average = -nan (2 samples)
-Accepted packet size average = -nan (2 samples)
-Hops average = -nan (2 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Network latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Flit latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Fragmentation average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Injected packet rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Accepted packet rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Injected flit rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Accepted flit rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Injected packet size average = -nan (3 samples)
-Accepted packet size average = -nan (3 samples)
-Hops average = -nan (3 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-
-GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1)
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Network latency average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Flit latency average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Fragmentation average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Injected packet rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Accepted packet rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Injected flit rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Accepted flit rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Injected packet size average = -nan (4 samples)
-Accepted packet size average = -nan (4 samples)
-Hops average = -nan (4 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_'
-GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit
-GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0)
-GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 13:33:51 2017
-GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA
diff --git a/bsmad_test/output.txt b/bsmad_test/output.txt
deleted file mode 100644
index 7414f61..0000000
--- a/bsmad_test/output.txt
+++ /dev/null
@@ -1,2338 +0,0 @@
-
-
- *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] ***
-
-
-GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable:
- 1=functional simulation only, 0=detailed performance simulator)
-GPGPU-Sim: Configuration options:
-
--network_mode 1 # Interconnection network mode
--inter_config_file config_fermi_islip.icnt # Interconnection network config file
--gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries
--gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable]
--gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus
--gpgpu_ptx_force_max_capability 60 # Force maximum compute capability
--gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file
--gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file
--gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output
--gpgpu_simd_model 1 # 1 = post-dominator
--gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>}
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>}
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip)
--gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss)
--n_regfile_gating_group 4 # group of lanes that should be read/written together)
--gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations
--gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations
--gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)
--gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8)
--gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16)
--gpgpu_n_clusters 28 # number of processing clusters
--gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster
--gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer
--gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer
--gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16)
--gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on)
--gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check
--gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from
--gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from
--gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled)
--gpgpu_num_reg_banks 32 # Number of register banks (default = 8)
--gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off)
--gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4)
--gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4)
--gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2)
--gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0)
--gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0)
--gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0)
--gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now)
--gpgpu_num_sched_per_core 2 # Number of warp schedulers per core
--gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler
--gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)
--gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_num_sp_units 4 # Number of SP units (default=1)
--gpgpu_num_sfu_units 1 # Number of SF units (default=1)
--gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything
--gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto
--gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled)
--gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul)
--gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i
--l2_ideal 0 # Use a ideal L2 cache that always hit
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only
--gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu
--gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module
--gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller
--gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs
--gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip
--gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip
--gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR)
--gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle)
--dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR)
--gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
--rop_latency 120 # ROP queue latency (default 85)
--dram_latency 100 # DRAM latency (default 30)
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>}
--gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address
--gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits
--gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file
--power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off)
--power_per_cycle_dump 0 # Dump detailed power output each cycle
--power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off)
--power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest)
--steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off)
--steady_state_definition 8:4 # allowed deviation:number of samples
--gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>}
--liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print)
--gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call
--gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call
--gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off)
--gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now)
--gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1)
--gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>}
--gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU
--gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger
--visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off)
--visualizer_outputfile NULL # Specifies the output log file for visualizer
--visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest)
--trace_enabled 0 # Turn on traces
--trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none
--trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0
--trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all)
--enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On)
--ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics.
--gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0
--gpgpu_cdp_enabled 0 # Turn on CDP
--save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx
--keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs
--gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file
--ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,19,25,145,1
--ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30
--ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335
--ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,4,4,32,1
--ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5
--ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130
--cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600
-DRAM Timing Options:
-nbk 16 # number of banks
-CCD 2 # column to column delay
-RRD 6 # minimal delay between activation of rows in different banks
-RCD 12 # row to column delay
-RAS 28 # time needed to activate row
-RP 12 # time needed to precharge (deactivate) row
-RC 40 # row cycle time
-CDLR 5 # switching from write to read (changes tWTR)
-WR 12 # last data-in to row precharge
-CL 12 # CAS latency
-WL 4 # Write latency
-nbkgrp 1 # number of bank groups
-CCDL 0 # column to column delay between accesses to different bank groups
-RTPL 0 # read to precharge delay between accesses to different bank groups
-Total number of memory sub partition = 22
-addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0
-addr_dec_mask[BK] = 0000000000007080 high:15 low:7
-addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15
-addr_dec_mask[COL] = 0000000000000f7f high:12 low:0
-addr_dec_mask[BURST] = 000000000000001f high:5 low:0
-sub_partition_id_mask = 0000000000000080
-GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000
-GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364
-*** Initializing Memory Statistics ***
-GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID)
-GPGPU-Sim uArch: Memory nodes ID start from index: 28
-GPGPU-Sim uArch: 0 1 2 3 4 5 6
-GPGPU-Sim uArch: 7 8 9 10 11 12 13
-GPGPU-Sim uArch: 14 15 16 17 18 19 20
-GPGPU-Sim uArch: 21 22 23 24 25 26 27
-GPGPU-Sim uArch: 28 29 30 31 32 33 34
-GPGPU-Sim uArch: 35 36 37 38 39 40 41
-GPGPU-Sim uArch: 42 43 44 45 46 47 48
-GPGPU-Sim uArch: 49
-GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID)
-GPGPU-Sim uArch: Memory nodes start from ID: 28
-GPGPU-Sim uArch: 0 1 2 3 4 5 6
-GPGPU-Sim uArch: 7 8 9 10 11 12 13
-GPGPU-Sim uArch: 14 15 16 17 18 19 20
-GPGPU-Sim uArch: 21 22 23 24 25 26 27
-GPGPU-Sim uArch: 28 29 30 31 32 33 34
-GPGPU-Sim uArch: 35 36 37 38 39 40 41
-GPGPU-Sim uArch: 42 43 44 45 46 47 48
-GPGPU-Sim uArch: 49
-1739ba94823ccfb8e12f742738e8e16e /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad
-GPGPU-Sim uArch: performance model initialization complete.
-GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default
-self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad
-Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad "
-Parsing file _cuobjdump_complete_output_r35nHZ
-######### cuobjdump parser ########
-## Adding new section PTX
-Adding ptx filename: _cuobjdump_1.ptx
-Adding arch: sm_50
-Adding identifier: default
-Done parsing!!!
-GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1
-WARNING: No guarantee that PTX will be parsed for SM version 50
-GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done.
-GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_...
-GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_
-GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'.
-BEGINNING CUSTOM PTX.
-ENDING CUSTOM PTX.
-GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done.
-GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_...
-GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2;
-GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3;
-GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_
-GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'.
-GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx
-Adding _cuobjdump_1.ptx with cubin handle 1
-GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_hSOoDH"
-Running: cat _ptx_hSOoDH | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_FSgqzp
-GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_FSgqzp --output-file /dev/null 2> _ptx_hSOoDHinfo"
-GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352
-GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344
-GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_hSOoDH _ptx2_FSgqzp _ptx_hSOoDHinfo"
-GPGPU-Sim PTX: loading globals with explicit initializers...
-GPGPU-Sim PTX: finished loading globals (0 bytes total).
-GPGPU-Sim PTX: loading constants with explicit initializers... done.
-GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1
-GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes
-GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes
-GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes
-GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes
-GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Network latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Flit latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Fragmentation average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Injected packet rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Accepted packet rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Injected flit rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Accepted flit rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Injected packet size average = -nan (1 samples)
-Accepted packet size average = -nan (1 samples)
-Hops average = -nan (1 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Network latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Flit latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Fragmentation average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Injected packet rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Accepted packet rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Injected flit rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Accepted flit rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Injected packet size average = -nan (2 samples)
-Accepted packet size average = -nan (2 samples)
-Hops average = -nan (2 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Network latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Flit latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Fragmentation average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Injected packet rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Accepted packet rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Injected flit rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Accepted flit rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Injected packet size average = -nan (3 samples)
-Accepted packet size average = -nan (3 samples)
-Hops average = -nan (3 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-
-GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1)
- 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Network latency average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Flit latency average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Fragmentation average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Injected packet rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Accepted packet rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Injected flit rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Accepted flit rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Injected packet size average = -nan (4 samples)
-Accepted packet size average = -nan (4 samples)
-Hops average = -nan (4 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_'
-GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit
-GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0)
-GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 16:02:01 2017
-GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA
diff --git a/bsmad_test/result b/bsmad_test/result
deleted file mode 100644
index 210fed9..0000000
--- a/bsmad_test/result
+++ /dev/null
@@ -1,2338 +0,0 @@
-
-
- *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] ***
-
-
-GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable:
- 1=functional simulation only, 0=detailed performance simulator)
-GPGPU-Sim: Configuration options:
-
--network_mode 1 # Interconnection network mode
--inter_config_file config_fermi_islip.icnt # Interconnection network config file
--gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries
--gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable]
--gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus
--gpgpu_ptx_force_max_capability 60 # Force maximum compute capability
--gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file
--gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file
--gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output
--gpgpu_simd_model 1 # 1 = post-dominator
--gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {<nthread>:<warpsize>}
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:<rf>}
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}
--gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip)
--gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss)
--n_regfile_gating_group 4 # group of lanes that should be read/written together)
--gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations
--gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations
--gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)
--gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8)
--gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16)
--gpgpu_n_clusters 28 # number of processing clusters
--gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster
--gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer
--gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer
--gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB)
--gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16)
--gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on)
--gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check
--gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from
--gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from
--gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled)
--gpgpu_num_reg_banks 32 # Number of register banks (default = 8)
--gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off)
--gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4)
--gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4)
--gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2)
--gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0)
--gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0)
--gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1)
--gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0)
--gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now)
--gpgpu_num_sched_per_core 2 # Number of warp schedulers per core
--gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler
--gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)
--gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
--gpgpu_num_sp_units 4 # Number of SP units (default=1)
--gpgpu_num_sfu_units 1 # Number of SF units (default=1)
--gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything
--gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:<num_active_warps>:<inner_prioritization>:<outer_prioritization>For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto
--gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled)
--gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul)
--gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i
--l2_ideal 0 # Use a ideal L2 cache that always hit
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>}
--gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only
--gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu
--gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module
--gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller
--gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs
--gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip
--gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip
--gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR)
--gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle)
--dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR)
--gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}
--rop_latency 120 # ROP queue latency (default 85)
--dram_latency 100 # DRAM latency (default 30)
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@<start bit>;<memory address map>}
--gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address
--gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits
--gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file
--power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off)
--power_per_cycle_dump 0 # Dump detailed power output each cycle
--power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off)
--power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest)
--steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off)
--steady_state_definition 8:4 # allowed deviation:number of samples
--gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit)
--gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {<freq>:<flag>}
--liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print)
--gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call
--gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call
--gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off)
--gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now)
--gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1)
--gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {<Core Clock>:<ICNT Clock>:<L2 Clock>:<DRAM Clock>}
--gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU
--gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger
--visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off)
--visualizer_outputfile NULL # Specifies the output log file for visualizer
--visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest)
--trace_enabled 0 # Turn on traces
--trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none
--trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0
--trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all)
--enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On)
--ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics.
--gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0
--gpgpu_cdp_enabled 0 # Turn on CDP
--save_embedded_ptx 0 # saves ptx files embedded in binary as <n>.ptx
--keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs
--gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file
--ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,19,25,145,1
--ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,30
--ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,335
--ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers <ADD,MAX,MUL,MAD,DIV,BSMAD>Default 1,1,4,4,32,1
--ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points <ADD,MAX,MUL,MAD,DIV>Default 1,1,1,1,5
--ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points <ADD,MAX,MUL,MAD,DIV>Default 8,8,8,8,130
--cdp_latency 7200,8000,100,12000,1600 # CDP API latency <cudaStreamCreateWithFlags, cudaGetParameterBufferV2_init_perWarp, cudaGetParameterBufferV2_perKernel, cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>Default 7200,8000,100,12000,1600
-DRAM Timing Options:
-nbk 16 # number of banks
-CCD 2 # column to column delay
-RRD 6 # minimal delay between activation of rows in different banks
-RCD 12 # row to column delay
-RAS 28 # time needed to activate row
-RP 12 # time needed to precharge (deactivate) row
-RC 40 # row cycle time
-CDLR 5 # switching from write to read (changes tWTR)
-WR 12 # last data-in to row precharge
-CL 12 # CAS latency
-WL 4 # Write latency
-nbkgrp 1 # number of bank groups
-CCDL 0 # column to column delay between accesses to different bank groups
-RTPL 0 # read to precharge delay between accesses to different bank groups
-Total number of memory sub partition = 22
-addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0
-addr_dec_mask[BK] = 0000000000007080 high:15 low:7
-addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15
-addr_dec_mask[COL] = 0000000000000f7f high:12 low:0
-addr_dec_mask[BURST] = 000000000000001f high:5 low:0
-sub_partition_id_mask = 0000000000000080
-GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000
-GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364
-*** Initializing Memory Statistics ***
-GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID)
-GPGPU-Sim uArch: Memory nodes ID start from index: 28
-GPGPU-Sim uArch: 0 1 2 3 4 5 6
-GPGPU-Sim uArch: 7 8 9 10 11 12 13
-GPGPU-Sim uArch: 14 15 16 17 18 19 20
-GPGPU-Sim uArch: 21 22 23 24 25 26 27
-GPGPU-Sim uArch: 28 29 30 31 32 33 34
-GPGPU-Sim uArch: 35 36 37 38 39 40 41
-GPGPU-Sim uArch: 42 43 44 45 46 47 48
-GPGPU-Sim uArch: 49
-GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID)
-GPGPU-Sim uArch: Memory nodes start from ID: 28
-GPGPU-Sim uArch: 0 1 2 3 4 5 6
-GPGPU-Sim uArch: 7 8 9 10 11 12 13
-GPGPU-Sim uArch: 14 15 16 17 18 19 20
-GPGPU-Sim uArch: 21 22 23 24 25 26 27
-GPGPU-Sim uArch: 28 29 30 31 32 33 34
-GPGPU-Sim uArch: 35 36 37 38 39 40 41
-GPGPU-Sim uArch: 42 43 44 45 46 47 48
-GPGPU-Sim uArch: 49
-1739ba94823ccfb8e12f742738e8e16e /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad
-GPGPU-Sim uArch: performance model initialization complete.
-GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default
-self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad
-Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad "
-Parsing file _cuobjdump_complete_output_ppZXax
-######### cuobjdump parser ########
-## Adding new section PTX
-Adding ptx filename: _cuobjdump_1.ptx
-Adding arch: sm_50
-Adding identifier: default
-Done parsing!!!
-GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1
-WARNING: No guarantee that PTX will be parsed for SM version 50
-GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done.
-GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'...
-GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_...
-GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_
-GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'.
-BEGINNING CUSTOM PTX.
-ENDING CUSTOM PTX.
-GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done.
-GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'...
-GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_...
-GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2;
-GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3;
-GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_
-GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'.
-GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx
-Adding _cuobjdump_1.ptx with cubin handle 1
-GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_D0f3bm"
-Running: cat _ptx_D0f3bm | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_ctl9cb
-GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_ctl9cb --output-file /dev/null 2> _ptx_D0f3bminfo"
-GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352
-GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344
-GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_D0f3bm _ptx2_ctl9cb _ptx_D0f3bminfo"
-GPGPU-Sim PTX: loading globals with explicit initializers...
-GPGPU-Sim PTX: finished loading globals (0 bytes total).
-GPGPU-Sim PTX: loading constants with explicit initializers... done.
-GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1
-GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2
-Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes
-GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes
-GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes
-GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes
-GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes
-GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping
-GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__
-GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes
-GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Network latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Flit latency average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Fragmentation average = -nan (1 samples)
- minimum = nan (1 samples)
- maximum = -nan (1 samples)
-Injected packet rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Accepted packet rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Injected flit rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Accepted flit rate average = -nan (1 samples)
- minimum = -nan (1 samples)
- maximum = -nan (1 samples)
-Injected packet size average = -nan (1 samples)
-Accepted packet size average = -nan (1 samples)
-Hops average = -nan (1 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Network latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Flit latency average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Fragmentation average = -nan (2 samples)
- minimum = nan (2 samples)
- maximum = -nan (2 samples)
-Injected packet rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Accepted packet rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Injected flit rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Accepted flit rate average = -nan (2 samples)
- minimum = -nan (2 samples)
- maximum = -nan (2 samples)
-Injected packet size average = -nan (2 samples)
-Accepted packet size average = -nan (2 samples)
-Hops average = -nan (2 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Network latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Flit latency average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Fragmentation average = -nan (3 samples)
- minimum = nan (3 samples)
- maximum = -nan (3 samples)
-Injected packet rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Accepted packet rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Injected flit rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Accepted flit rate average = -nan (3 samples)
- minimum = -nan (3 samples)
- maximum = -nan (3 samples)
-Injected packet size average = -nan (3 samples)
-Accepted packet size average = -nan (3 samples)
-Hops average = -nan (3 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-kernel_name =
-kernel_launch_uid =
-gpu_sim_cycle = 0
-gpu_sim_insn = 0
-gpu_ipc = -nan
-gpu_tot_sim_cycle = 0
-gpu_tot_sim_insn = 0
-gpu_tot_ipc = -nan
-gpu_tot_issued_cta = 0
-max_total_param_size = 0
-gpu_stall_dramfull = 0
-gpu_stall_icnt2sh = 0
-gpu_total_sim_rate=0
-
-========= Core cache stats =========
-L1I_cache:
-
-GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0
- L1I_total_cache_accesses = 0
- L1I_total_cache_misses = 0
- L1I_total_cache_pending_hits = 0
- L1I_total_cache_reservation_fails = 0
-L1D_cache:
- L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
- L1D_total_cache_accesses = 0
- L1D_total_cache_misses = 0
- L1D_total_cache_pending_hits = 0
- L1D_total_cache_reservation_fails = 0
- L1D_cache_data_port_util = 0.000
- L1D_cache_fill_port_util = 0.000
-L1C_cache:
- L1C_total_cache_accesses = 0
- L1C_total_cache_misses = 0
- L1C_total_cache_pending_hits = 0
- L1C_total_cache_reservation_fails = 0
-L1T_cache:
- L1T_total_cache_accesses = 0
- L1T_total_cache_misses = 0
- L1T_total_cache_pending_hits = 0
- L1T_total_cache_reservation_fails = 0
-
-Total_core_cache_stats:
-Shader 0 warp_id issue ditsribution:
-warp_id:
-
-distro:
-
-gpgpu_n_tot_thrd_icount = 0
-gpgpu_n_tot_w_icount = 0
-gpgpu_n_stall_shd_mem = 0
-gpgpu_n_mem_read_local = 0
-gpgpu_n_mem_write_local = 0
-gpgpu_n_mem_read_global = 0
-gpgpu_n_mem_write_global = 0
-gpgpu_n_mem_texture = 0
-gpgpu_n_mem_const = 0
-gpgpu_n_load_insn = 0
-gpgpu_n_store_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_shmem_insn = 0
-gpgpu_n_tex_insn = 0
-gpgpu_n_const_mem_insn = 0
-gpgpu_n_param_mem_insn = 0
-gpgpu_n_shmem_bkconflict = 0
-gpgpu_n_cache_bkconflict = 0
-gpgpu_n_intrawarp_mshr_merge = 0
-gpgpu_n_cmem_portconflict = 0
-gpgpu_stall_shd_mem[c_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0
-gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0
-gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[s_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0
-gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0
-gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0
-gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0
-gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0
-gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0
-gpu_reg_bank_conflict_stalls = 0
-Warp Occupancy Distribution:
-Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0
-GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1)
-maxmrqlatency = 0
-maxdqlatency = 0
-maxmflatency = 0
-max_icnt2mem_latency = 0
-max_icnt2sh_latency = 0
-mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum concurrent accesses to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-maximum service time to same row:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-average row accesses per activate:
-dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan
-average row locality = 0/0 = -nan
-number of total memory accesses made:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total accesses: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total read accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-number of total write accesses:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-total reads: 0
-min_bank_accesses = 0!
-min_chip_accesses = 0!
-average mf latency per bank:
-dram[0]: none none none none none none none none none none none none none none none none
-dram[1]: none none none none none none none none none none none none none none none none
-dram[2]: none none none none none none none none none none none none none none none none
-dram[3]: none none none none none none none none none none none none none none none none
-dram[4]: none none none none none none none none none none none none none none none none
-dram[5]: none none none none none none none none none none none none none none none none
-dram[6]: none none none none none none none none none none none none none none none none
-dram[7]: none none none none none none none none none none none none none none none none
-dram[8]: none none none none none none none none none none none none none none none none
-dram[9]: none none none none none none none none none none none none none none none none
-dram[10]: none none none none none none none none none none none none none none none none
-maximum mf latency per bank:
-dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-Memory Partition 0:
-Cache L2_bank_000:
-MSHR contents
-
-Cache L2_bank_001:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 1:
-Cache L2_bank_002:
-MSHR contents
-
-Cache L2_bank_003:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 2:
-Cache L2_bank_004:
-MSHR contents
-
-Cache L2_bank_005:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 3:
-Cache L2_bank_006:
-MSHR contents
-
-Cache L2_bank_007:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 4:
-Cache L2_bank_008:
-MSHR contents
-
-Cache L2_bank_009:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 5:
-Cache L2_bank_010:
-MSHR contents
-
-Cache L2_bank_011:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 6:
-Cache L2_bank_012:
-MSHR contents
-
-Cache L2_bank_013:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 7:
-Cache L2_bank_014:
-MSHR contents
-
-Cache L2_bank_015:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 8:
-Cache L2_bank_016:
-MSHR contents
-
-Cache L2_bank_017:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 9:
-Cache L2_bank_018:
-MSHR contents
-
-Cache L2_bank_019:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-Memory Partition 10:
-Cache L2_bank_020:
-MSHR contents
-
-Cache L2_bank_021:
-MSHR contents
-
-In Dram Latency Queue (total = 0):
-DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40
-n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan
-n_activity=0 dram_eff=-nan
-bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i
-dram_util_bins: 0 0 0 0 0 0 0 0 0 0
-dram_eff_bins: 0 0 0 0 0 0 0 0 0 0
-mrqq: max=0 avg=-nan
-
-========= L2 cache stats =========
-L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0
-L2_total_cache_accesses = 0
-L2_total_cache_misses = 0
-L2_total_cache_pending_hits = 0
-L2_total_cache_reservation_fails = 0
-L2_total_cache_breakdown:
-L2_cache_data_port_util = 0.000
-L2_cache_fill_port_util = 0.000
-
-icnt_total_pkts_mem_to_simt=0
-icnt_total_pkts_simt_to_mem=0
-LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-----------------------------Interconnect-DETAILS--------------------------------
-Class 0:
-Packet latency average = -nan
- minimum = nan
- maximum = -nan
-Network latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest packet = -1
-Flit latency average = -nan
- minimum = nan
- maximum = -nan
-Slowest flit = -1
-Fragmentation average = -nan
- minimum = nan
- maximum = -nan
-Injected packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted packet rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected flit rate average = -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Accepted flit rate average= -nan
- minimum = -nan (at node 0)
- maximum = -nan (at node 0)
-Injected packet length average = -nan
-Accepted packet length average = -nan
-Total in-flight flits = 0 (0 measured)
-====== Overall Traffic Statistics ======
-====== Traffic class 0 ======
-Packet latency average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Network latency average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Flit latency average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Fragmentation average = -nan (4 samples)
- minimum = nan (4 samples)
- maximum = -nan (4 samples)
-Injected packet rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Accepted packet rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Injected flit rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Accepted flit rate average = -nan (4 samples)
- minimum = -nan (4 samples)
- maximum = -nan (4 samples)
-Injected packet size average = -nan (4 samples)
-Accepted packet size average = -nan (4 samples)
-Hops average = -nan (4 samples)
-----------------------------END-of-Interconnect-DETAILS-------------------------
-GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_'
-GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit
-GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0)
-GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 16:27:07 2017
-GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA
generated by cgit v1.3 (git 2.53.0) at 2026-07-22 23:30:27 +0000