diff options
Diffstat (limited to 'configs/tested-cfgs/SM7_QV100/gpgpusim.config')
| -rw-r--r-- | configs/tested-cfgs/SM7_QV100/gpgpusim.config | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index c0d22ee..9903711 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -13,12 +13,13 @@ -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 70 - # Device Limits -gpgpu_stack_size_limit 1024 -gpgpu_heap_size_limit 8388608 -gpgpu_runtime_sync_depth_limit 2 -gpgpu_runtime_pending_launch_count_limit 2048 +-gpgpu_kernel_launch_latency 5000 +-gpgpu_TB_launch_latency 2 # Compute Capability -gpgpu_compute_capability_major 7 @@ -107,7 +108,7 @@ -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 -perf_sim_memcpy 1 --memory_partition_indexing 4 +-memory_partition_indexing 2 # 128 KB Inst. -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 @@ -116,17 +117,18 @@ -gpgpu_tex_cache:l1 N:4:128:256,L:R:m:N:L,T:512:8,128:2 # 64 KB Const -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 +-perfect_inst_const_cache 1 # Volta has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated -sub_core_model 1 # disable specialized operand collectors and use generic operand collectors instead -enable_specialized_operand_collector 0 --gpgpu_operand_collector_num_units_gen 8 +-gpgpu_operand_collector_num_units_gen 32 -gpgpu_operand_collector_num_in_ports_gen 8 -gpgpu_operand_collector_num_out_ports_gen 8 # volta has 8 banks, 4 schedulers, two banks per scheduler --gpgpu_num_reg_banks 8 +-gpgpu_num_reg_banks 32 # shared memory bankconflict detection -gpgpu_shmem_num_banks 32 @@ -139,10 +141,14 @@ -gpgpu_dual_issue_diff_exec_units 1 # interconnection --network_mode 1 --inter_config_file config_volta_islip.icnt +#-network_mode 1 +#-inter_config_file config_volta_islip.icnt # for local xbar, use: -# "-network_mode 2 -inct_in_buffer_limit 512 -inct_out_buffer_limit 512 -inct_subnets 2" +-network_mode 2 +-inct_in_buffer_limit 512 +-inct_out_buffer_limit 512 +-inct_subnets 2 +-arbiter_algo 1 # memory partition latency config -rop_latency 160 @@ -159,7 +165,7 @@ -gpgpu_dram_burst_length 2 -dram_data_command_freq_ratio 2 # HBM is DDR -gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS +-gpgpu_mem_addr_mapping dramid@6;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.CBCSSSSS # HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) # Timing for 1 GHZ |