diff options
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/tested-cfgs/SM75_RTX2060/trace.config | 20 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM7_QV100/trace.config | 13 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/trace.config | 13 |
3 files changed, 46 insertions, 0 deletions
diff --git a/configs/tested-cfgs/SM75_RTX2060/trace.config b/configs/tested-cfgs/SM75_RTX2060/trace.config index 41987cf..17b6cc7 100644 --- a/configs/tested-cfgs/SM75_RTX2060/trace.config +++ b/configs/tested-cfgs/SM75_RTX2060/trace.config @@ -3,3 +3,23 @@ -trace_opcode_latency_initiation_dp 8,4 -trace_opcode_latency_initiation_sfu 20,8 -trace_opcode_latency_initiation_tensor 8,4 + +#execute branch insts on spec unit 1 +#in Turing, there is a dedicated branch unit +#<enabled>,<num_units>,<max_latency>,<ID_OC_SPEC>,<OC_EX_SPEC>,<NAME> +-specialized_unit_1 1,4,4,4,4,BRA +#<latency>,<initiation> +-trace_opcode_latency_initiation_spec_op_1 4,4 + +#TEX unit, make fixed latency for all tex insts +-specialized_unit_2 1,1,200,4,4,TEX +-trace_opcode_latency_initiation_spec_op_2 200,4 + +#tensor unit +-specialized_unit_3 1,4,8,4,4,TENSOR +-trace_opcode_latency_initiation_spec_op_3 8,4 + +#UDP unit +#for more info about UDP, see https://www.hotchips.org/hc31/HC31_2.12_NVIDIA_final.pdf +-specialized_unit_4 1,4,4,4,4,UDP +-trace_opcode_latency_initiation_spec_op_4 4,2 diff --git a/configs/tested-cfgs/SM7_QV100/trace.config b/configs/tested-cfgs/SM7_QV100/trace.config index 04ac009..88f5706 100644 --- a/configs/tested-cfgs/SM7_QV100/trace.config +++ b/configs/tested-cfgs/SM7_QV100/trace.config @@ -4,3 +4,16 @@ -trace_opcode_latency_initiation_sfu 20,8 -trace_opcode_latency_initiation_tensor 8,4 +#execute branch insts on spec unit 1 +#in Volta, there is a dedicated branch unit +#<enabled>,<num_units>,<max_latency>,<ID_OC_SPEC>,<OC_EX_SPEC>,<NAME> +-specialized_unit_1 1,4,4,4,4,BRA +-trace_opcode_latency_initiation_spec_op_1 4,4 + +#TEX unit, make fixed latency for all tex insts +-specialized_unit_2 1,4,200,4,4,TEX +-trace_opcode_latency_initiation_spec_op_2 200,4 + +#tensor unit +-specialized_unit_3 1,4,8,4,4,TENSOR +-trace_opcode_latency_initiation_spec_op_3 8,4 diff --git a/configs/tested-cfgs/SM7_TITANV/trace.config b/configs/tested-cfgs/SM7_TITANV/trace.config index 04ac009..88f5706 100644 --- a/configs/tested-cfgs/SM7_TITANV/trace.config +++ b/configs/tested-cfgs/SM7_TITANV/trace.config @@ -4,3 +4,16 @@ -trace_opcode_latency_initiation_sfu 20,8 -trace_opcode_latency_initiation_tensor 8,4 +#execute branch insts on spec unit 1 +#in Volta, there is a dedicated branch unit +#<enabled>,<num_units>,<max_latency>,<ID_OC_SPEC>,<OC_EX_SPEC>,<NAME> +-specialized_unit_1 1,4,4,4,4,BRA +-trace_opcode_latency_initiation_spec_op_1 4,4 + +#TEX unit, make fixed latency for all tex insts +-specialized_unit_2 1,4,200,4,4,TEX +-trace_opcode_latency_initiation_spec_op_2 200,4 + +#tensor unit +-specialized_unit_3 1,4,8,4,4,TENSOR +-trace_opcode_latency_initiation_spec_op_3 8,4 |