diff options
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 11 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt | 2 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 38 |
3 files changed, 21 insertions, 30 deletions
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index 3842508..ed35531 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -86,6 +86,7 @@ -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 -perf_sim_memcpy 1 +-memory_partition_indexing 0 # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 @@ -131,13 +132,8 @@ # dram model config -gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 -gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 240 +-gpgpu_dram_return_queue_size 64 # for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) # 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition @@ -149,7 +145,7 @@ -gpgpu_mem_address_mask 1 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS -# Use the same GDDR5 timing +# Use the same GDDR5 timing, scaled to 2500MHZ -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" @@ -176,7 +172,6 @@ # power model configs, disable it untill we create a real energy model for Pascal 102 -power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx480.xml # tracing functionality #-trace_enabled 1 diff --git a/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt index 2f25889..615d0a9 100644 --- a/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt +++ b/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt @@ -7,7 +7,7 @@ network_count = 2; // Topology topology = fly; -k = 64; +k = 88; n = 1; // Routing diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index c8351da..03ef5b9 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -1,5 +1,5 @@ # This config models the Volta Titan X -# For more info about this card: +# For more info about volta architecture: # http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf # https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# # http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf @@ -21,15 +21,15 @@ -gpgpu_n_clusters 40 -gpgpu_n_cores_per_cluster 2 -gpgpu_n_mem 24 --gpgpu_n_sub_partition_per_mchannel 1 +-gpgpu_n_sub_partition_per_mchannel 2 # volta clock domains #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> -# Volta NVIDIA GV100 clock domains are adopted from +# Volta NVIDIA V100 clock domains are adopted from # https://en.wikipedia.org/wiki/Volta_(microarchitecture) --gpgpu_clock_domains 1200.0:2000.0:1200.0:850.0 +-gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0 # boost mode -# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0 +# -gpgpu_clock_domains 1455.0:1455.0:1455.0:850.0 # shader core pipeline config -gpgpu_shader_registers 65536 @@ -44,7 +44,7 @@ # ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB ## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12 +-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,12 -gpgpu_num_sp_units 4 -gpgpu_num_sfu_units 4 -gpgpu_num_dp_units 4 @@ -81,11 +81,12 @@ -smem_latency 19 -gpgpu_flush_l1_cache 1 -# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache --gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32 --gpgpu_cache:dl2_texture_only 0 +# 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache +-gpgpu_cache:dl2 S:32:128:24,L:B:m:L:L,A:192:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 -perf_sim_memcpy 1 +-memory_partition_indexing 0 # 128 KB Inst. -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 @@ -108,7 +109,8 @@ -gpgpu_operand_collector_num_out_ports_mem 1 -gpgpu_operand_collector_num_in_ports_dp 1 -gpgpu_operand_collector_num_out_ports_dp 1 --gpgpu_num_reg_banks 32 +# two banks per scheduler +-gpgpu_num_reg_banks 8 # shared memory bankconflict detection -gpgpu_shmem_num_banks 32 @@ -130,21 +132,16 @@ # dram model config -gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 -gpgpu_frfcfs_dram_sched_queue_size 64 -gpgpu_dram_return_queue_size 192 -# for HBM, 32 channles, each (128 bits) 16 bytes width +# for HBM, three stacks, 24 channles, each (128 bits) 16 bytes width -gpgpu_n_mem_per_ctrlr 1 -gpgpu_dram_buswidth 16 -gpgpu_dram_burst_length 2 -dram_data_command_freq_ratio 2 # HBM is DDR -gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCB.CCCSSSSS # HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) # Timing for 1 GHZ @@ -152,9 +149,9 @@ #-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: # CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" -# Timing for 715 MHZ, Tesla Volta V100 HBM runs at 715 MHZ --gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: - CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" +# Timing for 850 MHZ, Tesla TITANV V100 HBM runs at 850 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3" # HBM has dual bus interface, in which it can issue two col and row commands at a time -dual_bus_interface 1 @@ -182,7 +179,6 @@ # power model configs, disable it untill we create a real energy model for Pascal 100 -power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx480.xml # tracing functionality #-trace_enabled 1 |