32 files changed, 200 insertions, 25 deletions
diff --git a/configs/3.x-cfgs/GTX480/config_fermi_islip.icnt b/configs/deprecated-cfgs/GTX480/config_fermi_islip.icnt
index 7820e4e..7820e4e 100644
--- a/configs/3.x-cfgs/GTX480/config_fermi_islip.icnt
+++ b/configs/deprecated-cfgs/GTX480/config_fermi_islip.icnt
diff --git a/configs/3.x-cfgs/GTX480/gpgpusim.config b/configs/deprecated-cfgs/GTX480/gpgpusim.config
index ee90c12..620e938 100644
--- a/configs/3.x-cfgs/GTX480/gpgpusim.config
+++ b/configs/deprecated-cfgs/GTX480/gpgpusim.config
@@ -1,3 +1,6 @@
+#Save the cuobjdump dump
+#-save_embedded_ptx 1
+
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
diff --git a/configs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml b/configs/deprecated-cfgs/GTX480/gpuwattch_gtx480.xml
index 304e0fd..304e0fd 100755
--- a/configs/3.x-cfgs/GTX480/gpuwattch_gtx480.xml
+++ b/configs/deprecated-cfgs/GTX480/gpuwattch_gtx480.xml
diff --git a/configs/3.x-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt b/configs/deprecated-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
index 069ca02..069ca02 100644
--- a/configs/3.x-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
+++ b/configs/deprecated-cfgs/GeForceGTX750Ti/config_fermi_islip.icnt
diff --git a/configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config b/configs/deprecated-cfgs/GeForceGTX750Ti/gpgpusim.config
index c675aab..4f717c3 100644
--- a/configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config
+++ b/configs/deprecated-cfgs/GeForceGTX750Ti/gpgpusim.config
@@ -1,3 +1,6 @@
+#Save the cuobjdump dump
+#-save_embedded_ptx 1
+
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
diff --git a/configs/3.x-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml b/configs/deprecated-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
index e2b2324..e2b2324 100755
--- a/configs/3.x-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
+++ b/configs/deprecated-cfgs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml
diff --git a/configs/3.x-cfgs/QuadroFX5600/gpgpusim.config b/configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config
index 6f836ee..7f4e088 100644
--- a/configs/3.x-cfgs/QuadroFX5600/gpgpusim.config
+++ b/configs/deprecated-cfgs/QuadroFX5600/gpgpusim.config
@@ -1,3 +1,6 @@
+#Save the cuobjdump dump
+#-save_embedded_ptx 1
+
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
diff --git a/configs/3.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml b/configs/deprecated-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
index 2c5a6fc..2c5a6fc 100644
--- a/configs/3.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
+++ b/configs/deprecated-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml
diff --git a/configs/3.x-cfgs/QuadroFX5600/icnt_config_islip.icnt b/configs/deprecated-cfgs/QuadroFX5600/icnt_config_islip.icnt
index de3bcc8..de3bcc8 100644
--- a/configs/3.x-cfgs/QuadroFX5600/icnt_config_islip.icnt
+++ b/configs/deprecated-cfgs/QuadroFX5600/icnt_config_islip.icnt
diff --git a/configs/3.x-cfgs/QuadroFX5800/config_quadro_islip.icnt b/configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt
index cfe9cac..cfe9cac 100644
--- a/configs/3.x-cfgs/QuadroFX5800/config_quadro_islip.icnt
+++ b/configs/deprecated-cfgs/QuadroFX5800/config_quadro_islip.icnt
diff --git a/configs/3.x-cfgs/QuadroFX5800/gpgpusim.config b/configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config
index fef1110..9266480 100644
--- a/configs/3.x-cfgs/QuadroFX5800/gpgpusim.config
+++ b/configs/deprecated-cfgs/QuadroFX5800/gpgpusim.config
@@ -1,3 +1,6 @@
+#Save the cuobjdump dump
+#-save_embedded_ptx 1
+
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
diff --git a/configs/3.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM6_GTX1080/config_fermi_islip.icnt
index 2a69ddd..2a69ddd 100644
--- a/configs/3.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt
+++ b/configs/deprecated-cfgs/SM6_GTX1080/config_fermi_islip.icnt
diff --git a/configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config
index fb044c6..fb044c6 100644
--- a/configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config
+++ b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config
diff --git a/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config.orig b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config.orig
new file mode 100644
index 0000000..66b99d7
--- /dev/null
+++ b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config.orig
@@ -0,0 +1,157 @@
+# This config models the Pascal GP102 (GeForceGTX 1080Ti)
+
+#Save the cuobjdump dump
+#-save_embedded_ptx 1
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+<<<<<<< HEAD:configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config
+-gpgpu_ptx_force_max_capability 60
+=======
+-gpgpu_ptx_force_max_capability 61
+>>>>>>> 0e8d4f190940681601bdf7f95a5686baa0b6463b:configs/GeForceGTX1080Ti/gpgpusim.config
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 11
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Pascal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA TITAN X clock domains are adopted from 
+# https://en.wikipedia.org/wiki/GeForce_10_series
+-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 60
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,1,1,4,1,1,6
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# SFU is 32-width in pascal, then dp units initiation is 1 cycle
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 1,2,1,1,130
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP102 has 96KB Shared memory
+# Pascal GP102 has 64KB L1 cache
+# The default is to disable the L1 cache, unless cache modifieres is used
+-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,8
+-gpgpu_shmem_size 98304
+-gmem_skip_L1D 1
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4
+-gpgpu_cache:dl2_texture_only 0 
+
+# 4 KB Inst.
+-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
+
+# enable operand collector 
+## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
+-gpgpu_operand_collector_num_units_sp 20
+-gpgpu_operand_collector_num_units_sfu 4
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+# gpgpu_num_reg_banks should be increased to 32, but it gives an error!
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits)
+# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes 
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing from hynix H5GQ1H24AFR
+# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
+
+# Pascal has four schedulers per core
+-gpgpu_num_sched_per_core 2
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/3.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml b/configs/deprecated-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
index 02619ff..02619ff 100755
--- a/configs/3.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
+++ b/configs/deprecated-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml
diff --git a/configs/3.x-cfgs/SM6_P100/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM6_P100/config_fermi_islip.icnt
index d26c8d9..d26c8d9 100644
--- a/configs/3.x-cfgs/SM6_P100/config_fermi_islip.icnt
+++ b/configs/deprecated-cfgs/SM6_P100/config_fermi_islip.icnt
diff --git a/configs/3.x-cfgs/SM6_P100/gpgpusim.config b/configs/deprecated-cfgs/SM6_P100/gpgpusim.config
index a5e6736..a5e6736 100644
--- a/configs/3.x-cfgs/SM6_P100/gpgpusim.config
+++ b/configs/deprecated-cfgs/SM6_P100/gpgpusim.config
diff --git a/configs/3.x-cfgs/SM6_P100/gpuwattch_gtx480.xml b/configs/deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml
index 304e0fd..304e0fd 100755
--- a/configs/3.x-cfgs/SM6_P100/gpuwattch_gtx480.xml
+++ b/configs/deprecated-cfgs/SM6_P100/gpuwattch_gtx480.xml
diff --git a/configs/3.x-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM6_TITANX/config_fermi_islip.icnt
index 602daee..602daee 100644
--- a/configs/3.x-cfgs/SM6_TITANX/config_fermi_islip.icnt
+++ b/configs/deprecated-cfgs/SM6_TITANX/config_fermi_islip.icnt
diff --git a/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config
index 28912a3..28912a3 100644
--- a/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/deprecated-cfgs/SM6_TITANX/gpgpusim.config
diff --git a/configs/3.x-cfgs/SM6_TITANX/gpuwattch_gtx480.xml b/configs/deprecated-cfgs/SM6_TITANX/gpuwattch_gtx480.xml
index 304e0fd..304e0fd 100755
--- a/configs/3.x-cfgs/SM6_TITANX/gpuwattch_gtx480.xml
+++ b/configs/deprecated-cfgs/SM6_TITANX/gpuwattch_gtx480.xml
diff --git a/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/deprecated-cfgs/SM7_TITANV/config_fermi_islip.icnt
index fac792a..fac792a 100644
--- a/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
+++ b/configs/deprecated-cfgs/SM7_TITANV/config_fermi_islip.icnt
diff --git a/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config
index aefb04a..aefb04a 100644
--- a/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/deprecated-cfgs/SM7_TITANV/gpgpusim.config
diff --git a/configs/3.x-cfgs/TeslaC2050/config_fermi_islip.icnt b/configs/deprecated-cfgs/TeslaC2050/config_fermi_islip.icnt
index a11bd8e..a11bd8e 100644
--- a/configs/3.x-cfgs/TeslaC2050/config_fermi_islip.icnt
+++ b/configs/deprecated-cfgs/TeslaC2050/config_fermi_islip.icnt
diff --git a/configs/3.x-cfgs/TeslaC2050/gpgpusim.config b/configs/deprecated-cfgs/TeslaC2050/gpgpusim.config
index 6ac2c12..ca80972 100644
--- a/configs/3.x-cfgs/TeslaC2050/gpgpusim.config
+++ b/configs/deprecated-cfgs/TeslaC2050/gpgpusim.config
@@ -1,3 +1,6 @@
+#Save the cuobjdump dump
+#-save_embedded_ptx 1
+
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
diff --git a/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt b/configs/tested-cfgs/SM2_GTX480/config_fermi_islip.icnt
index c399db9..c399db9 100644
--- a/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt
+++ b/configs/tested-cfgs/SM2_GTX480/config_fermi_islip.icnt
diff --git a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
index 4096b09..d71b2fd 100644
--- a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
@@ -30,9 +30,10 @@
 -gpgpu_simd_model 1 
 
 # Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-#For Fermi, DP unit =0, DP inst is executed on SFU
--gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
+# For Fermi, DP unit =0, DP inst is executed on SFU
+# For Fermi, INT unit =0, INT inst is executed on SP
+-gpgpu_pipeline_widths 2,0,0,1,1,2,0,0,1,1,2
 -gpgpu_num_sp_units 2
 -gpgpu_num_sfu_units 1
 -gpgpu_num_dp_units 0
diff --git a/configs/4.x-cfgs/SM2_GTX480/gpuwattch_gtx480.xml b/configs/tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml
index 304e0fd..304e0fd 100755
--- a/configs/4.x-cfgs/SM2_GTX480/gpuwattch_gtx480.xml
+++ b/configs/tested-cfgs/SM2_GTX480/gpuwattch_gtx480.xml
diff --git a/configs/4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt
index dec4789..dec4789 100644
--- a/configs/4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt
+++ b/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt
diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index ed35531..cb23ab3 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -35,10 +35,11 @@
 -gpgpu_simd_model 1 
 
 # Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP102 has 4 SP SIMD units and 4 SFU units
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs
+# There is no int unit in Pascal
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5
+-gpgpu_pipeline_widths 2,1,0,2,1,2,1,0,2,1,5
 -gpgpu_num_sp_units 2
 -gpgpu_num_sfu_units 2
 -gpgpu_num_dp_units 1
diff --git a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt
index 615d0a9..615d0a9 100644
--- a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
+++ b/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 03ef5b9..8ed4cd0 100644
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -41,13 +41,16 @@
 -gpgpu_simd_model 1 
 
 # Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
+# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
+## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,12
+-gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
 -gpgpu_num_sp_units 4
 -gpgpu_num_sfu_units 4
 -gpgpu_num_dp_units 4
+-gpgpu_num_int_units 4
+-gpgpu_tensor_core_avail 1
+-gpgpu_num_tensor_core_units 4
 
 # Instruction latencies and initiation intervals
 # "ADD,MAX,MUL,MAD,DIV"
@@ -62,7 +65,8 @@
 -ptx_opcode_initiation_dp 4,4,4,4,130
 -ptx_opcode_latency_sfu 100
 -ptx_opcode_initiation_sfu 8
-
+-ptx_opcode_latency_tesnor 64
+-ptx_opcode_initiation_tensor 64
 
 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
@@ -72,6 +76,8 @@
 # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
 # disable this mode in case of multi kernels/apps execution
 -adpative_volta_cache_config 1
+# Volta unified cache has four ports
+-mem_unit_ports 4
 -gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_shmem_size 98304
 -gmem_skip_L1D 0
@@ -96,20 +102,15 @@
 # 64 KB Const
 -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
 
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
-# two banks per scheduler
+# Volta has sub core model, in which each scheduler has its own reisiter file and EUs
+# i.e. schedulers are isolated
+-sub_core_model 0
+# disable specialized operand collectors and use generic operand collectors instead
+-enable_specialized_operand_collector 0
+-gpgpu_operand_collector_num_units_gen 8
+-gpgpu_operand_collector_num_in_ports_gen 8
+-gpgpu_operand_collector_num_out_ports_gen 8
+# volta has 8 banks, 4 schedulers, two banks per scheduler
 -gpgpu_num_reg_banks 8
 
 # shared memory bankconflict detection 
@@ -118,7 +119,7 @@
 -gpgpu_shmem_warp_parts 1
 -gpgpu_coalesce_arch 60
 
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
+## In Volta, a warp scheduler can issue 1 inst per cycle
 -gpgpu_max_insn_issue_per_warp 1
 -gpgpu_dual_issue_diff_exec_units 1