1 files changed, 52 insertions, 0 deletions

diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index f8746e6..72639d4 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -1636,6 +1636,18 @@ void simt_splits_table::update_pc_for_split(unsigned split_id,
                                              address_type new_pc) {
   assert(m_splits_table.find(split_id) != m_splits_table.end());
   assert(m_splits_table[split_id].m_valid);
+  static const bool dbg_pc_enabled = (getenv("MEMCO_DBG_PC") != NULL);
+  if (dbg_pc_enabled && m_warp_id == 0) {
+    fprintf(stderr,
+            "[SPLIT_PC_UPDATE] cycle=%llu warp=%u split_id=%u "
+            "old_pc=0x%lx new_pc=0x%lx\n",
+            (unsigned long long)(GPGPU_Context()->the_gpgpusim->g_the_gpu->gpu_sim_cycle +
+                                 GPGPU_Context()->the_gpgpusim->g_the_gpu->gpu_tot_sim_cycle),
+            m_warp_id, split_id,
+            (unsigned long)m_splits_table[split_id].m_pc,
+            (unsigned long)new_pc);
+    fflush(stderr);
+  }
   m_splits_table[split_id].m_pc = new_pc;
 }
 
@@ -1886,6 +1898,15 @@ unsigned simt_splits_table::insert_new_entry(simt_splits_table_entry entry,
   assert(entry_num != (unsigned)-1);
   m_fifo_queue.push_back(
       fifo_entry(entry_num, gpgpusim_total_cycles, m_fifo_queue.size()));
+  static const bool dbg_pc_enabled = (getenv("MEMCO_DBG_PC") != NULL);
+  if (dbg_pc_enabled && m_warp_id == 0) {
+    fprintf(stderr,
+            "[SPLIT_INSERT-A] cycle=%llu warp=%u split_id=%u pc=0x%lx mask=%s\n",
+            gpgpusim_total_cycles, m_warp_id, entry_num,
+            (unsigned long)entry.m_pc,
+            entry.m_active_mask.to_string().c_str());
+    fflush(stderr);
+  }
   return entry_num;
 }
 
@@ -1934,6 +1955,14 @@ unsigned simt_splits_table::insert_new_entry(
   assert(entry != (unsigned)-1);
   m_fifo_queue.push_back(
       fifo_entry(entry, gpgpusim_total_cycles, m_fifo_queue.size()));
+  static const bool dbg_pc_enabled = (getenv("MEMCO_DBG_PC") != NULL);
+  if (dbg_pc_enabled && m_warp_id == 0) {
+    fprintf(stderr,
+            "[SPLIT_INSERT] cycle=%llu warp=%u split_id=%u pc=0x%lx mask=%s\n",
+            gpgpusim_total_cycles, m_warp_id, entry,
+            (unsigned long)pc, tmp_active_mask.to_string().c_str());
+    fflush(stderr);
+  }
   return entry;
 }
 
@@ -1983,6 +2012,14 @@ unsigned simt_splits_table::insert_new_entry(
   // call_ret=true: push to front for LIFO ordering
   m_fifo_queue.push_front(
       fifo_entry(entry, gpgpusim_total_cycles, m_fifo_queue.size()));
+  static const bool dbg_pc_enabled = (getenv("MEMCO_DBG_PC") != NULL);
+  if (dbg_pc_enabled && m_warp_id == 0) {
+    fprintf(stderr,
+            "[SPLIT_INSERT-C] cycle=%llu warp=%u split_id=%u pc=0x%lx mask=%s\n",
+            gpgpusim_total_cycles, m_warp_id, entry,
+            (unsigned long)pc, tmp_active_mask.to_string().c_str());
+    fflush(stderr);
+  }
   return entry;
 }
 
@@ -2691,6 +2728,21 @@ void simt_tables::update(simt_mask_t &thread_done, addr_vector_t &next_pc,
   address_type top_recvg_pc = m_simt_splits_table->get_rpc();
   unsigned top_recvg_entry = m_simt_splits_table->get_rpc_entry();
   address_type top_pc = m_simt_splits_table->get_pc();
+  if (top_pc != next_inst_pc) {
+    static const bool dbg_pc_enabled = (getenv("MEMCO_DBG_PC") != NULL);
+    if (dbg_pc_enabled) {
+      fprintf(stderr,
+              "[SIMT_UPDATE_MISMATCH] cycle=%llu warp=%u top_pc=0x%lx "
+              "next_inst_pc=0x%lx top_mask=%s active_split=%u\n",
+              (unsigned long long)(GPGPU_Context()->the_gpgpusim->g_the_gpu->gpu_sim_cycle +
+                                   GPGPU_Context()->the_gpgpusim->g_the_gpu->gpu_tot_sim_cycle),
+              m_warp_id, (unsigned long)top_pc,
+              (unsigned long)next_inst_pc,
+              top_active_mask.to_string().c_str(),
+              m_simt_splits_table->get_active_split_id());
+      fflush(stderr);
+    }
+  }
   assert(top_pc == next_inst_pc);
   assert(top_active_mask.any());