aboutsummaryrefslogtreecommitdiff
path: root/src/abstract_hardware_model.cc
diff options
context:
space:
mode:
Diffstat (limited to 'src/abstract_hardware_model.cc')
-rw-r--r--src/abstract_hardware_model.cc42
1 files changed, 34 insertions, 8 deletions
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index 7922bc5..e0e1d23 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -205,8 +205,8 @@ gpgpu_t::gpgpu_t(const gpgpu_functional_sim_config &config, gpgpu_context *ctx)
gpu_tot_sim_cycle = 0;
}
-address_type line_size_based_tag_func(new_addr_type address,
- new_addr_type line_size) {
+new_addr_type line_size_based_tag_func(new_addr_type address,
+ new_addr_type line_size) {
// gives the tag for an address based on a given line size
return address & ~(line_size - 1);
}
@@ -257,6 +257,7 @@ void warp_inst_t::do_atomic(bool forceDo) {
void warp_inst_t::do_atomic(const active_mask_t &access_mask, bool forceDo) {
assert(m_isatomic && (!m_empty || forceDo));
+ if (!should_do_atomic) return;
for (unsigned i = 0; i < m_config->warp_size; i++) {
if (access_mask.test(i)) {
dram_callback_t &cb = m_per_scalar_thread[i].callback;
@@ -447,7 +448,7 @@ void warp_inst_t::generate_mem_accesses() {
for (unsigned thread = 0; thread < m_config->warp_size; thread++) {
if (!active(thread)) continue;
new_addr_type addr = m_per_scalar_thread[thread].memreqaddr[0];
- unsigned block_address = line_size_based_tag_func(addr, cache_block_size);
+ new_addr_type block_address = line_size_based_tag_func(addr, cache_block_size);
accesses[block_address].set(thread);
unsigned idx = addr - block_address;
for (unsigned i = 0; i < data_size; i++) byte_mask.set(idx + i);
@@ -529,20 +530,37 @@ void warp_inst_t::memory_coalescing_arch(bool is_write,
(m_per_scalar_thread[thread].memreqaddr[access] != 0);
access++) {
new_addr_type addr = m_per_scalar_thread[thread].memreqaddr[access];
- unsigned block_address = line_size_based_tag_func(addr, segment_size);
+ new_addr_type block_address = line_size_based_tag_func(addr, segment_size);
unsigned chunk =
(addr & 127) / 32; // which 32-byte chunk within in a 128-byte
// chunk does this thread access?
transaction_info &info = subwarp_transactions[block_address];
// can only write to one segment
- assert(block_address == line_size_based_tag_func(
- addr + data_size_coales - 1, segment_size));
+ // it seems like in trace driven, a thread can write to more than one
+ // segment assert(block_address ==
+ // line_size_based_tag_func(addr+data_size_coales-1,segment_size));
info.chunks.set(chunk);
info.active.set(thread);
unsigned idx = (addr & 127);
- for (unsigned i = 0; i < data_size_coales; i++) info.bytes.set(idx + i);
+ for (unsigned i = 0; i < data_size_coales; i++)
+ if ((idx + i) < MAX_MEMORY_ACCESS_SIZE) info.bytes.set(idx + i);
+
+ // it seems like in trace driven, a thread can write to more than one
+ // segment handle this special case
+ if (block_address != line_size_based_tag_func(
+ addr + data_size_coales - 1, segment_size)) {
+ addr = addr + data_size_coales - 1;
+ new_addr_type block_address = line_size_based_tag_func(addr, segment_size);
+ unsigned chunk = (addr & 127) / 32;
+ transaction_info &info = subwarp_transactions[block_address];
+ info.chunks.set(chunk);
+ info.active.set(thread);
+ unsigned idx = (addr & 127);
+ for (unsigned i = 0; i < data_size_coales; i++)
+ if ((idx + i) < MAX_MEMORY_ACCESS_SIZE) info.bytes.set(idx + i);
+ }
}
}
@@ -607,7 +625,7 @@ void warp_inst_t::memory_coalescing_arch_atomic(bool is_write,
if (!active(thread)) continue;
new_addr_type addr = m_per_scalar_thread[thread].memreqaddr[0];
- unsigned block_address = line_size_based_tag_func(addr, segment_size);
+ new_addr_type block_address = line_size_based_tag_func(addr, segment_size);
unsigned chunk =
(addr & 127) / 32; // which 32-byte chunk within in a 128-byte chunk
// does this thread access?
@@ -746,6 +764,10 @@ kernel_info_t::kernel_info_t(dim3 gridDim, dim3 blockDim,
// Jin: launch latency management
m_launch_latency = entry->gpgpu_ctx->device_runtime->g_kernel_launch_latency;
+ m_kernel_TB_latency =
+ entry->gpgpu_ctx->device_runtime->g_kernel_launch_latency +
+ num_blocks() * entry->gpgpu_ctx->device_runtime->g_TB_launch_latency;
+
cache_config_set = false;
}
@@ -773,6 +795,10 @@ kernel_info_t::kernel_info_t(
// Jin: launch latency management
m_launch_latency = entry->gpgpu_ctx->device_runtime->g_kernel_launch_latency;
+ m_kernel_TB_latency =
+ entry->gpgpu_ctx->device_runtime->g_kernel_launch_latency +
+ num_blocks() * entry->gpgpu_ctx->device_runtime->g_TB_launch_latency;
+
cache_config_set = false;
m_NameToCudaArray = nameToCudaArray;
m_NameToTextureInfo = nameToTextureInfo;