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Diffstat (limited to 'src/cuda-sim/cuda-sim.cc')
-rw-r--r--src/cuda-sim/cuda-sim.cc50
1 files changed, 9 insertions, 41 deletions
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index dd7edd9..7587db7 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -542,7 +542,7 @@ void ptx_instruction::set_mul_div_or_other_archop(){
sp_op=INT_DIV_OP;
break;
default:
- if((op==ALU_OP)||(op==VP_CORE_OP))
+ if((op==ALU_OP))
sp_op=INT__OP;
break;
}
@@ -649,11 +649,9 @@ void ptx_instruction::set_opcode_and_latency()
break;
case LD_OP: op = LOAD_OP; break;
case MMA_LD_OP: op = TENSOR_CORE_LOAD_OP; break;
- case VP_LD_OP: op = VP_LOAD_OP; break;
case LDU_OP: op = LOAD_OP; break;
case ST_OP: op = STORE_OP; break;
case MMA_ST_OP: op = TENSOR_CORE_STORE_OP; break;
- case VP_ST_OP: op = VP_STORE_OP; break;
case BRA_OP: op = BRANCH_OP; break;
case BREAKADDR_OP: op = BRANCH_OP; break;
case TEX_OP: op = LOAD_OP; mem_op=TEX; break;
@@ -801,26 +799,6 @@ void ptx_instruction::set_opcode_and_latency()
initiation_interval = 64;
op=TENSOR_CORE_OP;
break;
- case VP_MMA_OP:
- if(get_wmma_type()==VP_MMA4)
- {
- latency = 64;
- initiation_interval = 64;
- }
- if(get_wmma_type()==VP_MMA8)
- {
- latency =128;
- initiation_interval = 128;
- }
- if(get_wmma_type()==VP_MMA16)
- {
- latency = 256;
- initiation_interval = 256;
- }
- op=VP_CORE_OP;
- op=VP_CORE_OP;
- op=VP_CORE_OP;
- break;
case SHFL_OP:
latency = 32;
initiation_interval = 15;
@@ -922,10 +900,10 @@ void ptx_instruction::pre_decode()
case WT_OPTION: cache_op = CACHE_WRITE_THROUGH; break;
default:
//if( m_opcode == LD_OP || m_opcode == LDU_OP )
- if( m_opcode ==VP_LD_OP || m_opcode == MMA_LD_OP || m_opcode == LD_OP || m_opcode == LDU_OP )
+ if( m_opcode == MMA_LD_OP || m_opcode == LD_OP || m_opcode == LDU_OP )
cache_op = CACHE_ALL;
//else if( m_opcode == ST_OP )
- else if( m_opcode == VP_ST_OP ||m_opcode == MMA_ST_OP || m_opcode == ST_OP )
+ else if( m_opcode == MMA_ST_OP || m_opcode == ST_OP )
cache_op = CACHE_WRITE_BACK;
else if( m_opcode == ATOM_OP )
cache_op = CACHE_GLOBAL;
@@ -1295,14 +1273,6 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
addr_t pc = next_instr();
assert( pc == inst.pc ); // make sure timing model and functional model are in sync
const ptx_instruction *pI = m_func_info->get_instruction(pc);
- //#if 0
- if(lane_id==0){
- //printf("EXECUTION_FLOW:LINE_NUM:%d\n",pI->source_line());
- printf("EXECUTION_FLOW:LINE_NUM:%d\n",pI->source_line());
- printf("EXECUTION_FLOW:INST:%s\n",pI->get_source());
- printf("EXECUTION_FLOW:PC%d\n",pc);
- }
- //#endif
set_npc( pc + pI->inst_size() );
@@ -1349,12 +1319,12 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
pI = pJ;
}
- if(((inst_opcode==MMA_OP||inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_MMA_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP))){
+ if(((inst_opcode==MMA_OP||inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP))){
if(inst.active_count()!=MAX_WARP_SIZE)
while(1);
}
- if(((inst_opcode!=MMA_OP)&&(inst_opcode!=MMA_LD_OP)&&(inst_opcode!=MMA_ST_OP)&&(inst_opcode!=VP_LD_OP)&&(inst_opcode!=VP_ST_OP)&&(inst_opcode!=VP_MMA_OP))||((inst_opcode==MMA_OP||inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_MMA_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP)&&(lane_id==0))){
+ if(((inst_opcode!=MMA_OP)&&(inst_opcode!=MMA_LD_OP)&&(inst_opcode!=MMA_ST_OP))||((inst_opcode==MMA_OP||inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP)&&(lane_id==0))){
switch ( inst_opcode ) {
#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break;
#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break;
@@ -1405,8 +1375,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
_memory_op_t insn_memory_op = no_memory_op;
unsigned insn_data_size = 0;
if ( (pI->has_memory_read() || pI->has_memory_write()) ) {
- if(!((inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP)))
- //if(!((inst_opcode==MMA_LD_OP||inst_opcode==VP_LD_OP)))
+ if(!((inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP)))
{
insn_memaddr = last_eaddr();
insn_space = last_space();
@@ -1480,15 +1449,14 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
if ( (g_ptx_sim_num_insn % 100000) == 0 ) {
dim3 ctaid = get_ctaid();
dim3 tid = get_tid();
- printf("GPGPU-Sim PTX: %u instructions simulated : ctaid=(%u,%u,%u) tid=(%u,%u,%u)\n",
+ DPRINTF(LIVENESS, "GPGPU-Sim PTX: %u instructions simulated : ctaid=(%u,%u,%u) tid=(%u,%u,%u)\n",
g_ptx_sim_num_insn, ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z );
fflush(stdout);
}
// "Return values"
if(!skip) {
- if(!((inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP)))
- //if(!((inst_opcode==MMA_LD_OP||inst_opcode==VP_LD_OP)))
+ if(!((inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP)))
{
inst.space = insn_space;
inst.set_addr(lane_id, insn_memaddr);
@@ -2150,7 +2118,7 @@ struct rec_pts {
int s_num_recon;
};
-struct std::map<function_info*,rec_pts> g_rpts;
+class std::map<function_info*,rec_pts> g_rpts;
struct rec_pts find_reconvergence_points( function_info *finfo )
{
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