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Diffstat (limited to 'src/gpgpu-sim/shader.h')
| -rw-r--r-- | src/gpgpu-sim/shader.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index cd03aec..1fff5e5 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1666,6 +1666,12 @@ class ldst_unit : public pipelined_simd_unit { mem_src_t resolve_source(const warp_inst_t &inst, unsigned access_src_wid, unsigned access_src_split_id) const; + // MEMCO v3: inter-set coalescing pass on a composite's accessq. + // Stage B: normalize each access's source_list to a single-entry list + // derived from its single (source_wid, source_split_id) stamp. No merging + // performed at this stage. Stage C will add the segment-equal merge step. + // Behavior gated off: env var MEMCOV3_DISABLE_INTERSET_COALESCE=1 skips. + void coalesce_accessq_across_sets(warp_inst_t &inst); gpgpu_sim *m_gpu; const memory_config *m_memory_config; @@ -1693,6 +1699,15 @@ class ldst_unit : public pipelined_simd_unit { // Set at each "m_next_wb = ..." assignment; defaults to composite primary. unsigned m_next_wb_src_wid; unsigned m_next_wb_src_split_id; + // MEMCO v3: list of all (wid, split_id) sources that contributed to the + // access feeding m_next_wb. Populated from mf->get_access().get_source_list() + // at arb time. Falls back to single-element [(m_next_wb_src_wid, + // m_next_wb_src_split_id)] when the access has no explicit source_list. + std::vector<std::pair<unsigned, unsigned> > m_next_wb_src_list; + // MEMCO v3: diagnostic counters. n_merges = inter-set merge events; + // n_merged_sources = total sources absorbed by merges (0 => no merging). + unsigned long long m_n_interset_merges; + unsigned long long m_n_interset_merged_sources; // MEM co-issue intra-warp pending writes: primary and intra-warp-coissued // may write the same register number (R5) for disjoint thread subsets. // The existing m_pending_writes[wid][reg] is single-counter per (wid,reg) |