diff options
Diffstat (limited to 'src/gpgpu-sim/shader.h')
| -rw-r--r-- | src/gpgpu-sim/shader.h | 40 |
1 files changed, 38 insertions, 2 deletions
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index c25f185..c01abf1 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -693,7 +693,7 @@ class opndcoll_rfu_t { // operand collector based register file unit class op_t { public: - op_t() { m_valid = false; } + op_t() { m_valid = false; m_set_warp_id = (unsigned)-1; } op_t(collector_unit_t *cu, unsigned op, unsigned reg, unsigned num_banks, bool sub_core_model, unsigned banks_per_sched, unsigned sched_id) { m_valid = true; @@ -702,9 +702,24 @@ class opndcoll_rfu_t { // operand collector based register file unit m_operand = op; m_register = reg; m_shced_id = sched_id; + m_set_warp_id = (unsigned)-1; m_bank = register_bank(reg, cu->get_warp_id(), num_banks, sub_core_model, banks_per_sched, sched_id); } + // Per-set variant: uses explicit warp_id for bank computation + op_t(collector_unit_t *cu, unsigned op, unsigned reg, unsigned num_banks, + bool sub_core_model, unsigned banks_per_sched, unsigned sched_id, + unsigned set_warp_id) { + m_valid = true; + m_warp = NULL; + m_cu = cu; + m_operand = op; + m_register = reg; + m_shced_id = sched_id; + m_set_warp_id = set_warp_id; + m_bank = register_bank(reg, set_warp_id, num_banks, sub_core_model, + banks_per_sched, sched_id); + } op_t(const warp_inst_t *warp, unsigned reg, unsigned num_banks, bool sub_core_model, unsigned banks_per_sched, unsigned sched_id) { m_valid = true; @@ -713,9 +728,23 @@ class opndcoll_rfu_t { // operand collector based register file unit m_cu = NULL; m_operand = -1; m_shced_id = sched_id; + m_set_warp_id = (unsigned)-1; m_bank = register_bank(reg, warp->warp_id(), num_banks, sub_core_model, banks_per_sched, sched_id); } + // Explicit warp_id variant for writeback of co-issued sets + op_t(unsigned explicit_warp_id, unsigned reg, unsigned num_banks, + bool sub_core_model, unsigned banks_per_sched, unsigned sched_id) { + m_valid = true; + m_warp = NULL; + m_cu = NULL; + m_operand = (unsigned)-1; + m_register = reg; + m_shced_id = sched_id; + m_set_warp_id = explicit_warp_id; + m_bank = register_bank(reg, explicit_warp_id, num_banks, sub_core_model, + banks_per_sched, sched_id); + } // accessors bool valid() const { return m_valid; } @@ -724,7 +753,9 @@ class opndcoll_rfu_t { // operand collector based register file unit return m_register; } unsigned get_wid() const { - if (m_warp) + if (m_set_warp_id != (unsigned)-1) + return m_set_warp_id; + else if (m_warp) return m_warp->warp_id(); else if (m_cu) return m_cu->get_warp_id(); @@ -784,6 +815,7 @@ class opndcoll_rfu_t { // operand collector based register file unit unsigned m_register; unsigned m_bank; unsigned m_shced_id; // scheduler id that has issued this inst + unsigned m_set_warp_id; // per-set warp_id override for SIMD partitioning }; enum alloc_t { @@ -946,6 +978,7 @@ class opndcoll_rfu_t { // operand collector based register file unit m_not_ready.reset(); m_warp_id = -1; m_num_banks = 0; + m_has_simd_sets = false; } // accessors bool ready() const; @@ -988,6 +1021,9 @@ class opndcoll_rfu_t { // operand collector based register file unit unsigned m_num_banks_per_sched; bool m_sub_core_model; unsigned m_reg_id; // if sub_core_model enabled, limit regs this cu can r/w + + // SIMD lane partitioning: tracks whether this CU holds a composite + bool m_has_simd_sets; }; class dispatch_unit_t { |