aboutsummaryrefslogtreecommitdiff
path: root/src/gpgpu-sim/shader.h
diff options
context:
space:
mode:
Diffstat (limited to 'src/gpgpu-sim/shader.h')
-rw-r--r--src/gpgpu-sim/shader.h61
1 files changed, 7 insertions, 54 deletions
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 99abb63..8ad6514 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -286,7 +286,7 @@ typedef std::bitset<WARP_PER_CTA_MAX> warp_set_t;
int register_bank(int regnum, int wid, unsigned num_banks, unsigned bank_warp_shift);
class shader_core_ctx;
-class shader_core_config;
+struct shader_core_config;
class shader_core_stats;
enum scheduler_prioritization_type
@@ -319,12 +319,11 @@ public:
register_set* sp_out,
register_set* sfu_out,
register_set* tensor_core_out,
- register_set* vp_core_out,
register_set* mem_out,
int id)
: m_supervised_warps(), m_stats(stats), m_shader(shader),
m_scoreboard(scoreboard), m_simt_stack(simt), /*m_pipeline_reg(pipe_regs),*/ m_warp(warp),
- m_sp_out(sp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_vp_core_out(vp_core_out),m_mem_out(mem_out), m_id(id){}
+ m_sp_out(sp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_mem_out(mem_out), m_id(id){}
virtual ~scheduler_unit(){}
virtual void add_supervised_warp_id(int i) {
m_supervised_warps.push_back(&warp(i));
@@ -398,7 +397,6 @@ protected:
register_set* m_sp_out;
register_set* m_sfu_out;
register_set* m_tensor_core_out;
- register_set* m_vp_core_out;
register_set* m_mem_out;
int m_id;
@@ -412,10 +410,9 @@ public:
register_set* sp_out,
register_set* sfu_out,
register_set* tensor_core_out,
- register_set* vp_core_out,
register_set* mem_out,
int id )
- : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, vp_core_out, mem_out, id ){}
+ : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ){}
virtual ~lrr_scheduler () {}
virtual void order_warps ();
virtual void done_adding_supervised_warps() {
@@ -431,10 +428,9 @@ public:
register_set* sp_out,
register_set* sfu_out,
register_set* tensor_core_out,
- register_set* vp_core_out,
register_set* mem_out,
int id )
- : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out,vp_core_out, mem_out, id ){}
+ : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ){}
virtual ~gto_scheduler () {}
virtual void order_warps ();
virtual void done_adding_supervised_warps() {
@@ -452,11 +448,10 @@ public:
register_set* sp_out,
register_set* sfu_out,
register_set* tensor_core_out,
- register_set* vp_core_out,
register_set* mem_out,
int id,
char* config_str )
- : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, vp_core_out, mem_out, id ),
+ : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ),
m_pending_warps()
{
unsigned inner_level_readin;
@@ -504,7 +499,6 @@ public:
register_set* sp_out,
register_set* sfu_out,
register_set* tensor_core_out,
- register_set* vp_core_out,
register_set* mem_out,
int id,
char* config_string );
@@ -979,7 +973,7 @@ struct ifetch_buffer_t {
unsigned m_warp_id;
};
-class shader_core_config;
+struct shader_core_config;
class simd_function_unit {
public:
@@ -1089,22 +1083,6 @@ public:
virtual void active_lanes_in_pipeline();
virtual void issue( register_set& source_reg );
};
-class vp_core : public pipelined_simd_unit
-{
-public:
- vp_core( register_set* result_port, const shader_core_config *config, shader_core_ctx *core );
- virtual bool can_issue( const warp_inst_t &inst ) const
- {
- switch(inst.op) {
- case VP_CORE_OP: break;
- default: return false;
- }
- return pipelined_simd_unit::can_issue(inst);
- }
- virtual void active_lanes_in_pipeline();
- virtual void issue( register_set& source_reg );
-};
-
class sp_unit : public pipelined_simd_unit
@@ -1117,10 +1095,8 @@ public:
case SFU_OP: return false;
case LOAD_OP: return false;
case TENSOR_CORE_LOAD_OP: return false;
- case VP_LOAD_OP: return false;
case STORE_OP: return false;
case TENSOR_CORE_STORE_OP: return false;
- case VP_STORE_OP: return false;
case MEMORY_BARRIER_OP: return false;
default: break;
}
@@ -1163,10 +1139,8 @@ public:
switch(inst.op) {
case LOAD_OP: break;
case TENSOR_CORE_LOAD_OP: break;
- case VP_LOAD_OP: break;
case STORE_OP: break;
case TENSOR_CORE_STORE_OP: break;
- case VP_STORE_OP: break;
case MEMORY_BARRIER_OP: break;
default: return false;
}
@@ -1255,12 +1229,10 @@ enum pipeline_stage_name_t {
ID_OC_SP=0,
ID_OC_SFU,
ID_OC_TENSOR_CORE,
- ID_OC_VP_CORE,
ID_OC_MEM,
OC_EX_SP,
OC_EX_SFU,
OC_EX_TENSOR_CORE,
- OC_EX_VP_CORE,
OC_EX_MEM,
EX_WB,
N_PIPELINE_STAGES
@@ -1270,12 +1242,10 @@ const char* const pipeline_stage_name_decode[] = {
"ID_OC_SP",
"ID_OC_SFU",
"ID_OC_TENSOR_CORE",
- "ID_OC_VP_CORE",
"ID_OC_MEM",
"OC_EX_SP",
"OC_EX_SFU",
"OC_EX_TENSOR_CORE",
- "OC_EX_VP_CORE",
"OC_EX_MEM",
"EX_WB",
"N_PIPELINE_STAGES"
@@ -1328,12 +1298,6 @@ struct shader_core_config : public core_config
gpgpu_operand_collector_num_in_ports_tensor_core=8;
gpgpu_operand_collector_num_out_ports_tensor_core=8;
- max_vp_core_latency = 512;
- gpgpu_num_vp_core_units=8;
- gpgpu_operand_collector_num_units_vp_core=24;
- gpgpu_operand_collector_num_in_ports_vp_core=8;
- gpgpu_operand_collector_num_out_ports_vp_core=8;
-
m_L1I_config.init(m_L1I_config.m_config_string,FuncCachePreferNone);
m_L1T_config.init(m_L1T_config.m_config_string,FuncCachePreferNone);
m_L1C_config.init(m_L1C_config.m_config_string,FuncCachePreferNone);
@@ -1381,28 +1345,24 @@ struct shader_core_config : public core_config
int gpgpu_operand_collector_num_units_sp;
int gpgpu_operand_collector_num_units_sfu;
int gpgpu_operand_collector_num_units_tensor_core;
- int gpgpu_operand_collector_num_units_vp_core;
int gpgpu_operand_collector_num_units_mem;
int gpgpu_operand_collector_num_units_gen;
unsigned int gpgpu_operand_collector_num_in_ports_sp;
unsigned int gpgpu_operand_collector_num_in_ports_sfu;
unsigned int gpgpu_operand_collector_num_in_ports_tensor_core;
- unsigned int gpgpu_operand_collector_num_in_ports_vp_core;
unsigned int gpgpu_operand_collector_num_in_ports_mem;
unsigned int gpgpu_operand_collector_num_in_ports_gen;
unsigned int gpgpu_operand_collector_num_out_ports_sp;
unsigned int gpgpu_operand_collector_num_out_ports_sfu;
unsigned int gpgpu_operand_collector_num_out_ports_tensor_core;
- unsigned int gpgpu_operand_collector_num_out_ports_vp_core;
unsigned int gpgpu_operand_collector_num_out_ports_mem;
unsigned int gpgpu_operand_collector_num_out_ports_gen;
int gpgpu_num_sp_units;
int gpgpu_num_sfu_units;
int gpgpu_num_tensor_core_units;
- int gpgpu_num_vp_core_units;
int gpgpu_num_mem_units;
//Shader core resources
@@ -1416,7 +1376,6 @@ struct shader_core_config : public core_config
unsigned max_sp_latency;
unsigned max_sfu_latency;
unsigned max_tensor_core_latency;
- unsigned max_vp_core_latency;
unsigned n_simt_cores_per_cluster;
unsigned n_simt_clusters;
@@ -1433,7 +1392,7 @@ struct shader_core_config : public core_config
struct shader_core_stats_pod {
- void* shader_core_stats_pod_start[]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure
+ void* shader_core_stats_pod_start[0]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure
unsigned long long *shader_cycles;
unsigned *m_num_sim_insn; // number of scalar thread instructions committed by this shader core
unsigned *m_num_sim_winsn; // number of warp instructions committed by this shader core
@@ -1455,7 +1414,6 @@ struct shader_core_stats_pod {
unsigned *m_num_sp_acesses;
unsigned *m_num_sfu_acesses;
unsigned *m_num_tensor_core_acesses;
- unsigned *m_num_vp_core_acesses;
unsigned *m_num_trans_acesses;
unsigned *m_num_mem_acesses;
unsigned *m_num_sp_committed;
@@ -1463,7 +1421,6 @@ struct shader_core_stats_pod {
unsigned *m_num_tlb_accesses;
unsigned *m_num_sfu_committed;
unsigned *m_num_tensor_core_committed;
- unsigned *m_num_vp_core_committed;
unsigned *m_num_mem_committed;
unsigned *m_read_regfile_acesses;
unsigned *m_write_regfile_acesses;
@@ -1473,7 +1430,6 @@ struct shader_core_stats_pod {
unsigned *m_active_sp_lanes;
unsigned *m_active_sfu_lanes;
unsigned *m_active_tensor_core_lanes;
- unsigned *m_active_vp_core_lanes;
unsigned *m_active_fu_lanes;
unsigned *m_active_fu_mem_lanes;
unsigned *m_n_diverge; // number of divergence occurring in this shader
@@ -1546,7 +1502,6 @@ public:
m_num_sp_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_sfu_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_tensor_core_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
- m_num_vp_core_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_trans_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_mem_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_sp_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
@@ -1555,12 +1510,10 @@ public:
m_active_sp_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_active_sfu_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_active_tensor_core_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
- m_active_vp_core_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_active_fu_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_active_fu_mem_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_sfu_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_tensor_core_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
- m_num_vp_core_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_mem_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_read_regfile_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_write_regfile_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
generated by cgit v1.3 (git 2.53.0) at 2026-07-22 14:03:26 +0000