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-rw-r--r--src/gpgpu-sim/Makefile2
-rw-r--r--src/gpgpu-sim/dram.h4
-rw-r--r--src/gpgpu-sim/gpu-cache.cc24
-rw-r--r--src/gpgpu-sim/gpu-sim.cc79
-rw-r--r--src/gpgpu-sim/mem_fetch.cc2
-rw-r--r--src/gpgpu-sim/mem_fetch.h4
-rw-r--r--src/gpgpu-sim/shader.cc91
-rw-r--r--src/gpgpu-sim/shader.h61
-rw-r--r--src/gpgpu-sim/traffic_breakdown.cc1
9 files changed, 101 insertions, 167 deletions
diff --git a/src/gpgpu-sim/Makefile b/src/gpgpu-sim/Makefile
index 4f77699..f10a8a4 100644
--- a/src/gpgpu-sim/Makefile
+++ b/src/gpgpu-sim/Makefile
@@ -48,7 +48,7 @@ ifeq ($(GNUC_CPP0X), 1)
endif
ifneq ($(DEBUG),1)
- OPTFLAGS += -O0
+ OPTFLAGS += -O3
else
CXXFLAGS +=
endif
diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h
index a8bff14..15c63e7 100644
--- a/src/gpgpu-sim/dram.h
+++ b/src/gpgpu-sim/dram.h
@@ -87,7 +87,7 @@ struct bank_t
unsigned int bkgrpindex;
};
-struct mem_fetch;
+class mem_fetch;
class dram_t
{
@@ -178,7 +178,7 @@ private:
unsigned int ave_mrqs_partial;
unsigned int bwutil_partial;
- struct memory_stats_t *m_stats;
+ class memory_stats_t *m_stats;
class Stats* mrqq_Dist; //memory request queue inside DRAM
friend class frfcfs_scheduler;
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index 5ea4190..8886398 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -517,18 +517,28 @@ void cache_stats::print_stats(FILE *fout, const char *cache_name) const{
/// the provided name is used.
/// The printed format is "<cache_name>[<request_type>][<request_status>] = <stat_value>"
///
+ std::vector< unsigned > total_access;
+ total_access.resize(NUM_MEM_ACCESS_TYPE, 0);
std::string m_cache_name = cache_name;
for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) {
for (unsigned status = 0; status < NUM_CACHE_REQUEST_STATUS; ++status) {
- if(m_stats[type][status] > 0){
- fprintf(fout, "\t%s[%s][%s] = %u\n",
- m_cache_name.c_str(),
- mem_access_type_str((enum mem_access_type)type),
- cache_request_status_str((enum cache_request_status)status),
- m_stats[type][status]);
- }
+ fprintf(fout, "\t%s[%s][%s] = %u\n",
+ m_cache_name.c_str(),
+ mem_access_type_str((enum mem_access_type)type),
+ cache_request_status_str((enum cache_request_status)status),
+ m_stats[type][status]);
+ if(status != RESERVATION_FAIL)
+ total_access[type]+= m_stats[type][status];
}
}
+ for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) {
+ if(total_access[type] > 0)
+ fprintf(fout, "\t%s[%s][%s] = %u\n",
+ m_cache_name.c_str(),
+ mem_access_type_str((enum mem_access_type)type),
+ "TOTAL_ACCESS",
+ total_access[type]);
+ }
}
void cache_sub_stats::print_port_stats(FILE *fout, const char *cache_name) const
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index eba6f54..d4b636b 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -32,10 +32,12 @@
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
+#include <signal.h>
#include "zlib.h"
#include "shader.h"
+#include "shader_trace.h"
#include "dram.h"
#include "mem_fetch.h"
@@ -87,6 +89,14 @@ unsigned long long gpu_tot_sim_cycle = 0;
// performance counter for stalls due to congestion.
unsigned int gpu_stall_dramfull = 0;
unsigned int gpu_stall_icnt2sh = 0;
+unsigned long long partiton_reqs_in_parallel = 0;
+unsigned long long partiton_reqs_in_parallel_total = 0;
+unsigned long long partiton_reqs_in_parallel_util = 0;
+unsigned long long partiton_reqs_in_parallel_util_total = 0;
+unsigned long long gpu_sim_cycle_parition_util = 0;
+unsigned long long gpu_tot_sim_cycle_parition_util = 0;
+unsigned long long partiton_replys_in_parallel = 0;
+unsigned long long partiton_replys_in_parallel_total = 0;
/* Clock Domains */
@@ -223,7 +233,7 @@ void shader_core_config::reg_options(class OptionParser * opp)
"per-shader L1 data cache config "
" {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}",
"none" );
- option_parser_register(opp, "-gpgpu_cache:dl1PreShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared,
+ option_parser_register(opp, "-gpgpu_cache:dl1PrefShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared,
"per-shader L1 data cache config "
" {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}",
"none" );
@@ -309,9 +319,6 @@ void shader_core_config::reg_options(class OptionParser * opp)
option_parser_register(opp, "-gpgpu_operand_collector_num_units_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_units_tensor_core,
"number of collector units (default = 4)",
"4");
- option_parser_register(opp, "-gpgpu_operand_collector_num_units_vp_core", OPT_INT32, &gpgpu_operand_collector_num_units_vp_core,
- "number of collector units (default = 4)",
- "4");
option_parser_register(opp, "-gpgpu_operand_collector_num_units_mem", OPT_INT32, &gpgpu_operand_collector_num_units_mem,
"number of collector units (default = 2)",
"2");
@@ -327,9 +334,6 @@ void shader_core_config::reg_options(class OptionParser * opp)
option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_in_ports_tensor_core,
"number of collector unit in ports (default = 1)",
"1");
- option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_vp_core", OPT_INT32, &gpgpu_operand_collector_num_in_ports_vp_core,
- "number of collector unit in ports (default = 1)",
- "1");
option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_mem", OPT_INT32, &gpgpu_operand_collector_num_in_ports_mem,
"number of collector unit in ports (default = 1)",
"1");
@@ -345,9 +349,6 @@ void shader_core_config::reg_options(class OptionParser * opp)
option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_out_ports_tensor_core,
"number of collector unit in ports (default = 1)",
"1");
- option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_vp_core", OPT_INT32, &gpgpu_operand_collector_num_out_ports_vp_core,
- "number of collector unit in ports (default = 1)",
- "1");
option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_mem", OPT_INT32, &gpgpu_operand_collector_num_out_ports_mem,
"number of collector unit in ports (default = 1)",
"1");
@@ -368,8 +369,8 @@ void shader_core_config::reg_options(class OptionParser * opp)
"1");
option_parser_register(opp, "-gpgpu_pipeline_widths", OPT_CSTR, &pipeline_widths_string,
"Pipeline widths "
- "ID_OC_SP,ID_OC_SFU,ID_OC_TENSOR_CORE,ID_OC_VP_CORE,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_TENSOR_CORE,OC_EX_TENSOR_CORE,OC_EX_MEM,EX_WB",
- "1,1,1,1,1,1,1,1,1,1,1" );
+ "ID_OC_SP,ID_OC_SFU,ID_OC_TENSOR_CORE,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_TENSOR_CORE,OC_EX_TENSOR_CORE,OC_EX_MEM,EX_WB",
+ "1,1,1,1,1,1,1,1,1,1" );
option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32, &gpgpu_num_sp_units,
"Number of SP units (default=1)",
"1");
@@ -379,9 +380,6 @@ void shader_core_config::reg_options(class OptionParser * opp)
option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32, &gpgpu_num_tensor_core_units,
"Number of tensor_core units (default=1)",
"1");
- option_parser_register(opp, "-gpgpu_num_vp_core_units", OPT_INT32, &gpgpu_num_vp_core_units,
- "Number of vp_core units (default=1)",
- "1");
option_parser_register(opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units,
"Number if ldst units (default=1) WARNING: not hooked up to anything",
"1");
@@ -768,6 +766,10 @@ void gpgpu_sim::init()
gpu_sim_insn = 0;
last_gpu_sim_insn = 0;
m_total_cta_launched=0;
+ partiton_reqs_in_parallel = 0;
+ partiton_replys_in_parallel = 0;
+ partiton_reqs_in_parallel_util = 0;
+ gpu_sim_cycle_parition_util = 0;
reinit_clock_domains();
set_param_gpgpu_num_shaders(m_config.num_shader());
@@ -804,8 +806,16 @@ void gpgpu_sim::update_stats() {
gpu_tot_sim_cycle += gpu_sim_cycle;
gpu_tot_sim_insn += gpu_sim_insn;
gpu_tot_issued_cta += m_total_cta_launched;
+ partiton_reqs_in_parallel_total += partiton_reqs_in_parallel;
+ partiton_replys_in_parallel_total += partiton_replys_in_parallel;
+ partiton_reqs_in_parallel_util_total += partiton_reqs_in_parallel_util;
+ gpu_tot_sim_cycle_parition_util += gpu_sim_cycle_parition_util ;
gpu_sim_cycle = 0;
+ partiton_reqs_in_parallel = 0;
+ partiton_replys_in_parallel = 0;
+ partiton_reqs_in_parallel_util = 0;
+ gpu_sim_cycle_parition_util = 0;
gpu_sim_insn = 0;
m_total_cta_launched = 0;
}
@@ -989,6 +999,21 @@ void gpgpu_sim::gpu_print_stat()
printf("gpu_stall_dramfull = %d\n", gpu_stall_dramfull);
printf("gpu_stall_icnt2sh = %d\n", gpu_stall_icnt2sh );
+ printf("partiton_reqs_in_parallel = %lld\n", partiton_reqs_in_parallel);
+ printf("partiton_reqs_in_parallel_total = %lld\n", partiton_reqs_in_parallel_total );
+ printf("partiton_level_parallism = %12.4f\n", (float)partiton_reqs_in_parallel / gpu_sim_cycle);
+ printf("partiton_level_parallism_total = %12.4f\n", (float)(partiton_reqs_in_parallel+partiton_reqs_in_parallel_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) );
+ printf("partiton_reqs_in_parallel_util = %lld\n", partiton_reqs_in_parallel_util);
+ printf("partiton_reqs_in_parallel_util_total = %lld\n", partiton_reqs_in_parallel_util_total );
+ printf("gpu_sim_cycle_parition_util = %lld\n", gpu_sim_cycle_parition_util);
+ printf("gpu_tot_sim_cycle_parition_util = %lld\n", gpu_tot_sim_cycle_parition_util );
+ printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle_parition_util);
+ printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_sim_cycle_parition_util+gpu_tot_sim_cycle_parition_util) );
+ printf("partiton_replys_in_parallel = %lld\n", partiton_replys_in_parallel);
+ printf("partiton_replys_in_parallel_total = %lld\n", partiton_replys_in_parallel_total );
+ printf("L2_BW = %12.4f GB/Sec\n", ((float)(partiton_replys_in_parallel * 32) / (gpu_sim_cycle * m_config.icnt_period)) / 1000000000);
+ printf("L2_BW_total = %12.4f GB/Sec\n", ((float)((partiton_replys_in_parallel+partiton_replys_in_parallel_total) * 32) / ((gpu_tot_sim_cycle+gpu_sim_cycle) * m_config.icnt_period)) / 1000000000 );
+
time_t curr_time;
time(&curr_time);
unsigned long long elapsed_time = MAX( curr_time - g_simulation_starttime, 1 );
@@ -1202,8 +1227,8 @@ bool shader_core_ctx::occupy_shader_resource_1block(kernel_info_t & k, bool occu
m_occupied_regs += (padded_cta_size * ((kernel_info->regs+3)&~3));
m_occupied_ctas++;
- printf("GPGPU-Sim uArch: Shader %d occupied %d threads, %d shared mem, %d registers, %d ctas\n",
- m_sid, m_occupied_n_threads, m_occupied_shmem, m_occupied_regs, m_occupied_ctas);
+ SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: Occupied %d threads, %d shared mem, %d registers, %d ctas\n",
+ m_occupied_n_threads, m_occupied_shmem, m_occupied_regs, m_occupied_ctas);
}
return true;
@@ -1328,8 +1353,8 @@ void shader_core_ctx::issue_block2core( kernel_info_t &kernel )
m_n_active_cta++;
shader_CTA_count_log(m_sid, 1);
- printf("GPGPU-Sim uArch: core:%3d, cta:%2u, start_tid:%4u, end_tid:%4u, initialized @(%lld,%lld)\n",
- m_sid, free_cta_hw_id, start_thread, end_thread, gpu_sim_cycle, gpu_tot_sim_cycle );
+ SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: cta:%2u, start_tid:%4u, end_tid:%4u, initialized @(%lld,%lld)\n",
+ free_cta_hw_id, start_thread, end_thread, gpu_sim_cycle, gpu_tot_sim_cycle );
}
@@ -1393,6 +1418,7 @@ void gpgpu_sim::cycle()
for (unsigned i=0;i<m_shader_config->n_simt_clusters;i++)
m_cluster[i]->icnt_cycle();
}
+ unsigned partiton_replys_in_parallel_per_cycle = 0;
if (clock_mask & ICNT) {
// pop from memory controller to interconnect
for (unsigned i=0;i<m_memory_config->m_n_mem_sub_partition;i++) {
@@ -1405,6 +1431,7 @@ void gpgpu_sim::cycle()
mf->set_status(IN_ICNT_TO_SHADER,gpu_sim_cycle+gpu_tot_sim_cycle);
::icnt_push( m_shader_config->mem2device(i), mf->get_tpc(), mf, response_size );
m_memory_sub_partition[i]->pop();
+ partiton_replys_in_parallel_per_cycle++;
} else {
gpu_stall_icnt2sh++;
}
@@ -1413,6 +1440,7 @@ void gpgpu_sim::cycle()
}
}
}
+ partiton_replys_in_parallel += partiton_replys_in_parallel_per_cycle;
if (clock_mask & DRAM) {
for (unsigned i=0;i<m_memory_config->m_n_mem;i++){
@@ -1425,6 +1453,7 @@ void gpgpu_sim::cycle()
}
// L2 operations follow L2 clock domain
+ unsigned partiton_reqs_in_parallel_per_cycle = 0;
if (clock_mask & L2) {
m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].clear();
for (unsigned i=0;i<m_memory_config->m_n_mem_sub_partition;i++) {
@@ -1435,11 +1464,17 @@ void gpgpu_sim::cycle()
} else {
mem_fetch* mf = (mem_fetch*) icnt_pop( m_shader_config->mem2device(i) );
m_memory_sub_partition[i]->push( mf, gpu_sim_cycle + gpu_tot_sim_cycle );
+ partiton_reqs_in_parallel_per_cycle++;
}
m_memory_sub_partition[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle);
m_memory_sub_partition[i]->accumulate_L2cache_stats(m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX]);
}
}
+ partiton_reqs_in_parallel += partiton_reqs_in_parallel_per_cycle;
+ if(partiton_reqs_in_parallel_per_cycle > 0){
+ partiton_reqs_in_parallel_util += partiton_reqs_in_parallel_per_cycle;
+ gpu_sim_cycle_parition_util++;
+ }
if (clock_mask & ICNT) {
icnt_transfer();
@@ -1467,9 +1502,8 @@ void gpgpu_sim::cycle()
if( g_single_step && ((gpu_sim_cycle+gpu_tot_sim_cycle) >= g_single_step) ) {
- asm("int $03");
+ raise(SIGTRAP); // Debug breakpoint
}
- printf("gpu_sim_cycle=%d\n",gpu_sim_cycle);
gpu_sim_cycle++;
if( g_interactive_debugger_enabled )
@@ -1528,7 +1562,8 @@ void gpgpu_sim::cycle()
hrs = elapsed_time/3600 - 24*days;
minutes = elapsed_time/60 - 60*(hrs + 24*days);
sec = elapsed_time - 60*(minutes + 60*(hrs + 24*days));
- printf("GPGPU-Sim uArch: cycles simulated: %lld inst.: %lld (ipc=%4.1f) sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s",
+
+ DPRINTF(LIVENESS, "GPGPU-Sim uArch: cycles simulated: %lld inst.: %lld (ipc=%4.1f) sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s",
gpu_tot_sim_cycle + gpu_sim_cycle, gpu_tot_sim_insn + gpu_sim_insn,
(double)gpu_sim_insn/(double)gpu_sim_cycle,
(unsigned)((gpu_tot_sim_insn+gpu_sim_insn) / elapsed_time),
diff --git a/src/gpgpu-sim/mem_fetch.cc b/src/gpgpu-sim/mem_fetch.cc
index 580c051..729636d 100644
--- a/src/gpgpu-sim/mem_fetch.cc
+++ b/src/gpgpu-sim/mem_fetch.cc
@@ -39,7 +39,7 @@ mem_fetch::mem_fetch( const mem_access_t &access,
unsigned wid,
unsigned sid,
unsigned tpc,
- const class memory_config *config )
+ const struct memory_config *config )
{
m_request_uid = sm_next_mf_request_uid++;
m_access = access;
diff --git a/src/gpgpu-sim/mem_fetch.h b/src/gpgpu-sim/mem_fetch.h
index c89edbb..de98748 100644
--- a/src/gpgpu-sim/mem_fetch.h
+++ b/src/gpgpu-sim/mem_fetch.h
@@ -55,7 +55,7 @@ public:
unsigned wid,
unsigned sid,
unsigned tpc,
- const class memory_config *config );
+ const struct memory_config *config );
~mem_fetch();
void set_status( enum mem_fetch_status status, unsigned long long cycle );
@@ -141,7 +141,7 @@ private:
static unsigned sm_next_mf_request_uid;
- const class memory_config *m_mem_config;
+ const struct memory_config *m_mem_config;
unsigned icnt_flit_size;
};
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index eeb59bb..23f255d 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -149,7 +149,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
&m_pipeline_reg[ID_OC_SP],
&m_pipeline_reg[ID_OC_SFU],
&m_pipeline_reg[ID_OC_TENSOR_CORE],
- &m_pipeline_reg[ID_OC_VP_CORE],
&m_pipeline_reg[ID_OC_MEM],
i
)
@@ -165,7 +164,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
&m_pipeline_reg[ID_OC_SP],
&m_pipeline_reg[ID_OC_SFU],
&m_pipeline_reg[ID_OC_TENSOR_CORE],
- &m_pipeline_reg[ID_OC_VP_CORE],
&m_pipeline_reg[ID_OC_MEM],
i,
config->gpgpu_scheduler_string
@@ -182,7 +180,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
&m_pipeline_reg[ID_OC_SP],
&m_pipeline_reg[ID_OC_SFU],
&m_pipeline_reg[ID_OC_TENSOR_CORE],
- &m_pipeline_reg[ID_OC_VP_CORE],
&m_pipeline_reg[ID_OC_MEM],
i
)
@@ -198,7 +195,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
&m_pipeline_reg[ID_OC_SP],
&m_pipeline_reg[ID_OC_SFU],
&m_pipeline_reg[ID_OC_TENSOR_CORE],
- &m_pipeline_reg[ID_OC_VP_CORE],
&m_pipeline_reg[ID_OC_MEM],
i,
config->gpgpu_scheduler_string
@@ -219,11 +215,10 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
}
//op collector configuration
- enum { SP_CUS, SFU_CUS, TENSOR_CORE_CUS, VP_CORE_CUS, MEM_CUS, GEN_CUS };
+ enum { SP_CUS, SFU_CUS, TENSOR_CORE_CUS, MEM_CUS, GEN_CUS };
m_operand_collector.add_cu_set(SP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_sp);
m_operand_collector.add_cu_set(SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu, m_config->gpgpu_operand_collector_num_out_ports_sfu);
m_operand_collector.add_cu_set(TENSOR_CORE_CUS, config->gpgpu_operand_collector_num_units_tensor_core, config->gpgpu_operand_collector_num_out_ports_tensor_core);
- m_operand_collector.add_cu_set(VP_CORE_CUS, config->gpgpu_operand_collector_num_units_vp_core, config->gpgpu_operand_collector_num_out_ports_vp_core);
m_operand_collector.add_cu_set(MEM_CUS, m_config->gpgpu_operand_collector_num_units_mem, m_config->gpgpu_operand_collector_num_out_ports_mem);
m_operand_collector.add_cu_set(GEN_CUS, m_config->gpgpu_operand_collector_num_units_gen, m_config->gpgpu_operand_collector_num_out_ports_gen);
@@ -257,15 +252,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
in_ports.clear(),out_ports.clear(),cu_sets.clear();
}
- for (unsigned i = 0; i < config->gpgpu_operand_collector_num_in_ports_vp_core; i++) {
- in_ports.push_back(&m_pipeline_reg[ID_OC_VP_CORE]);
- out_ports.push_back(&m_pipeline_reg[OC_EX_VP_CORE]);
- cu_sets.push_back((unsigned)VP_CORE_CUS);
- cu_sets.push_back((unsigned)GEN_CUS);
- m_operand_collector.add_port(in_ports,out_ports,cu_sets);
- in_ports.clear(),out_ports.clear(),cu_sets.clear();
- }
-
for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_mem; i++) {
in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]);
out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]);
@@ -280,12 +266,10 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
in_ports.push_back(&m_pipeline_reg[ID_OC_SP]);
in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]);
in_ports.push_back(&m_pipeline_reg[ID_OC_TENSOR_CORE]);
- in_ports.push_back(&m_pipeline_reg[ID_OC_VP_CORE]);
in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]);
out_ports.push_back(&m_pipeline_reg[OC_EX_SP]);
out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]);
out_ports.push_back(&m_pipeline_reg[OC_EX_TENSOR_CORE]);
- out_ports.push_back(&m_pipeline_reg[OC_EX_VP_CORE]);
out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]);
cu_sets.push_back((unsigned)GEN_CUS);
m_operand_collector.add_port(in_ports,out_ports,cu_sets);
@@ -295,7 +279,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
m_operand_collector.init( m_config->gpgpu_num_reg_banks, this );
// execute
- m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_sfu_units + config->gpgpu_num_tensor_core_units + config->gpgpu_num_vp_core_units + 1; // sp_unit, sfu, ldst_unit
+ m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_sfu_units + config->gpgpu_num_tensor_core_units + 1; // sp_unit, sfu, ldst_unit
//m_dispatch_port = new enum pipeline_stage_name_t[ m_num_function_units ];
//m_issue_port = new enum pipeline_stage_name_t[ m_num_function_units ];
@@ -319,12 +303,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
m_issue_port.push_back(OC_EX_TENSOR_CORE);
}
- for (int k = 0; k < config->gpgpu_num_vp_core_units; k++) {
- m_fu.push_back(new vp_core( &m_pipeline_reg[EX_WB], m_config, this ));
- m_dispatch_port.push_back(ID_OC_VP_CORE);
- m_issue_port.push_back(OC_EX_VP_CORE);
- }
-
m_ldst_unit = new ldst_unit( m_icnt, m_mem_fetch_allocator, this, &m_operand_collector, m_scoreboard, config, mem_config, stats, shader_id, tpc_id );
m_fu.push_back(m_ldst_unit);
m_dispatch_port.push_back(ID_OC_MEM);
@@ -923,7 +901,7 @@ void scheduler_unit::cycle()
ready_inst = true;
const active_mask_t &active_mask = m_simt_stack[warp_id]->get_active_mask();
assert( warp(warp_id).inst_in_pipeline() );
- if ( (pI->op == LOAD_OP)||(pI->op ==TENSOR_CORE_LOAD_OP)||(pI->op ==VP_LOAD_OP)|| (pI->op == STORE_OP)|| (pI->op==TENSOR_CORE_STORE_OP) ||(pI->op==VP_STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) {
+ if ( (pI->op == LOAD_OP)||(pI->op ==TENSOR_CORE_LOAD_OP)|| (pI->op == STORE_OP)|| (pI->op==TENSOR_CORE_STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) {
if( m_mem_out->has_free() ) {
m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id);
issued++;
@@ -934,8 +912,7 @@ void scheduler_unit::cycle()
bool sp_pipe_avail = m_sp_out->has_free();
bool sfu_pipe_avail = m_sfu_out->has_free();
bool tensor_core_pipe_avail = m_tensor_core_out->has_free();
- bool vp_core_pipe_avail = m_vp_core_out->has_free();
- if( sp_pipe_avail && (pI->op != SFU_OP) && (pI->op != TENSOR_CORE_OP) && (pI->op !=VP_CORE_OP)) {
+ if( sp_pipe_avail && (pI->op != SFU_OP) && (pI->op != TENSOR_CORE_OP) ) {
//Jin: special for CDP api
if(pI->m_is_cdp && !warp(warp_id).m_cdp_dummy) {
@@ -976,14 +953,7 @@ void scheduler_unit::cycle()
warp_inst_issued = true;
}
}
- else if ( (pI->op == VP_CORE_OP) ) {
- if( vp_core_pipe_avail ) {
- m_shader->issue_warp(*m_vp_core_out,pI,active_mask,warp_id);
- issued++;
- issued_inst=true;
- warp_inst_issued = true;
- }
- } }
+ }
} else {
SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) fails scoreboard\n",
(*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id() );
@@ -1149,11 +1119,10 @@ swl_scheduler::swl_scheduler ( shader_core_stats* stats, shader_core_ctx* shader
register_set* sp_out,
register_set* sfu_out,
register_set* tensor_core_out,
- register_set* vp_core_out,
register_set* mem_out,
int id,
char* config_string )
- : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, vp_core_out, mem_out, id )
+ : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id )
{
unsigned m_prioritization_readin;
int ret = sscanf( config_string,
@@ -1321,16 +1290,6 @@ void ldst_unit::get_L1T_sub_stats(struct cache_sub_stats &css) const{
void shader_core_ctx::warp_inst_complete(const warp_inst_t &inst)
{
- //#if 0
- //printf("[warp_inst_complete] uid=%u core=%u warp=%u pc=%#x @ time=%llu issued@%llu\n",
- //const ptx_instruction *pI = m_func_info->get_instruction(inst.pc);
- printf("[warp_inst_complete] uid=%u core=%u warp=%u pc=%d @ time=%llu \n",
- inst.get_uid(), m_sid, inst.warp_id(), inst.pc, gpu_sim_cycle);
- //printf("^instruction:%s",(pI->m_source).c_str());
- //inst.get_uid(), m_sid, inst.warp_id(), inst.pc, gpu_tot_sim_cycle + gpu_sim_cycle, inst.get_issue_cycle());
- //#endif
-
-
if(inst.op_pipe==SP__OP)
m_stats->m_num_sp_committed[m_sid]++;
else if(inst.op_pipe==SFU__OP)
@@ -1588,13 +1547,6 @@ tensor_core:: tensor_core( register_set* result_port, const shader_core_config
m_name = "TENSOR_CORE";
}
-vp_core:: vp_core( register_set* result_port, const shader_core_config *config,shader_core_ctx *core )
- : pipelined_simd_unit(result_port,config,config->max_vp_core_latency,core)
-{
- m_name = "VP_CORE";
-}
-
-
void sfu::issue( register_set& source_reg )
{
warp_inst_t** ready_reg = source_reg.get_ready();
@@ -1615,16 +1567,6 @@ void tensor_core::issue( register_set& source_reg )
pipelined_simd_unit::issue(source_reg);
}
-void vp_core::issue( register_set& source_reg )
-{
- warp_inst_t** ready_reg = source_reg.get_ready();
- //m_core->incexecstat((*ready_reg));
-
- (*ready_reg)->op_pipe= VP_CORE__OP;
- m_core->incsfu_stat(m_core->get_config()->warp_size,(*ready_reg)->latency);
- pipelined_simd_unit::issue(source_reg);
-}
-
void ldst_unit::active_lanes_in_pipeline(){
unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline();
@@ -1655,13 +1597,6 @@ void tensor_core::active_lanes_in_pipeline(){
m_core->incfumemactivelanes_stat(active_count);
}
-void vp_core::active_lanes_in_pipeline(){
- unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline();
- assert(active_count<=m_core->get_config()->warp_size);
- m_core->incsfuactivelanes_stat(active_count);
- m_core->incfuactivelanes_stat(active_count);
- m_core->incfumemactivelanes_stat(active_count);
-}
sp_unit::sp_unit( register_set* result_port, const shader_core_config *config,shader_core_ctx *core)
: pipelined_simd_unit(result_port,config,config->max_sp_latency,core)
@@ -2093,12 +2028,12 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num, kernel_info_t
m_barriers.deallocate_barrier(cta_num);
shader_CTA_count_unlog(m_sid, 1);
- printf("GPGPU-Sim uArch: Shader %d finished CTA #%d (%lld,%lld), %u CTAs running\n", m_sid, cta_num, gpu_sim_cycle, gpu_tot_sim_cycle,
- m_n_active_cta );
+ SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: Finished CTA #%d (%lld,%lld), %u CTAs running\n",
+ cta_num, gpu_sim_cycle, gpu_tot_sim_cycle, m_n_active_cta);
if( m_n_active_cta == 0 ) {
- printf("GPGPU-Sim uArch: Shader %u empty (last released kernel %u \'%s\').\n", m_sid, kernel->get_uid(),
- kernel->name().c_str() );
+ SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: Empty (last released kernel %u \'%s\').\n",
+ kernel->get_uid(), kernel->name().c_str());
fflush(stdout);
//Shader can only be empty when no more cta are dispatched
@@ -2113,8 +2048,10 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num, kernel_info_t
kernel->dec_running();
if( !m_gpu->kernel_more_cta_left(kernel) ) {
if( !kernel->running() ) {
- printf("GPGPU-Sim uArch: GPU detected kernel %u \'%s\' finished on shader %u.\n", kernel->get_uid(),
- kernel->name().c_str(), m_sid );
+ SHADER_DPRINTF(LIVENESS,
+ "GPGPU-Sim uArch: GPU detected kernel %u \'%s\' finished on shader %u.\n", kernel->get_uid(),
+ kernel->name().c_str(), m_sid);
+
if(m_kernel == kernel)
m_kernel = NULL;
m_gpu->set_kernel_done( kernel );
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 99abb63..8ad6514 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -286,7 +286,7 @@ typedef std::bitset<WARP_PER_CTA_MAX> warp_set_t;
int register_bank(int regnum, int wid, unsigned num_banks, unsigned bank_warp_shift);
class shader_core_ctx;
-class shader_core_config;
+struct shader_core_config;
class shader_core_stats;
enum scheduler_prioritization_type
@@ -319,12 +319,11 @@ public:
register_set* sp_out,
register_set* sfu_out,
register_set* tensor_core_out,
- register_set* vp_core_out,
register_set* mem_out,
int id)
: m_supervised_warps(), m_stats(stats), m_shader(shader),
m_scoreboard(scoreboard), m_simt_stack(simt), /*m_pipeline_reg(pipe_regs),*/ m_warp(warp),
- m_sp_out(sp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_vp_core_out(vp_core_out),m_mem_out(mem_out), m_id(id){}
+ m_sp_out(sp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_mem_out(mem_out), m_id(id){}
virtual ~scheduler_unit(){}
virtual void add_supervised_warp_id(int i) {
m_supervised_warps.push_back(&warp(i));
@@ -398,7 +397,6 @@ protected:
register_set* m_sp_out;
register_set* m_sfu_out;
register_set* m_tensor_core_out;
- register_set* m_vp_core_out;
register_set* m_mem_out;
int m_id;
@@ -412,10 +410,9 @@ public:
register_set* sp_out,
register_set* sfu_out,
register_set* tensor_core_out,
- register_set* vp_core_out,
register_set* mem_out,
int id )
- : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, vp_core_out, mem_out, id ){}
+ : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ){}
virtual ~lrr_scheduler () {}
virtual void order_warps ();
virtual void done_adding_supervised_warps() {
@@ -431,10 +428,9 @@ public:
register_set* sp_out,
register_set* sfu_out,
register_set* tensor_core_out,
- register_set* vp_core_out,
register_set* mem_out,
int id )
- : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out,vp_core_out, mem_out, id ){}
+ : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ){}
virtual ~gto_scheduler () {}
virtual void order_warps ();
virtual void done_adding_supervised_warps() {
@@ -452,11 +448,10 @@ public:
register_set* sp_out,
register_set* sfu_out,
register_set* tensor_core_out,
- register_set* vp_core_out,
register_set* mem_out,
int id,
char* config_str )
- : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, vp_core_out, mem_out, id ),
+ : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ),
m_pending_warps()
{
unsigned inner_level_readin;
@@ -504,7 +499,6 @@ public:
register_set* sp_out,
register_set* sfu_out,
register_set* tensor_core_out,
- register_set* vp_core_out,
register_set* mem_out,
int id,
char* config_string );
@@ -979,7 +973,7 @@ struct ifetch_buffer_t {
unsigned m_warp_id;
};
-class shader_core_config;
+struct shader_core_config;
class simd_function_unit {
public:
@@ -1089,22 +1083,6 @@ public:
virtual void active_lanes_in_pipeline();
virtual void issue( register_set& source_reg );
};
-class vp_core : public pipelined_simd_unit
-{
-public:
- vp_core( register_set* result_port, const shader_core_config *config, shader_core_ctx *core );
- virtual bool can_issue( const warp_inst_t &inst ) const
- {
- switch(inst.op) {
- case VP_CORE_OP: break;
- default: return false;
- }
- return pipelined_simd_unit::can_issue(inst);
- }
- virtual void active_lanes_in_pipeline();
- virtual void issue( register_set& source_reg );
-};
-
class sp_unit : public pipelined_simd_unit
@@ -1117,10 +1095,8 @@ public:
case SFU_OP: return false;
case LOAD_OP: return false;
case TENSOR_CORE_LOAD_OP: return false;
- case VP_LOAD_OP: return false;
case STORE_OP: return false;
case TENSOR_CORE_STORE_OP: return false;
- case VP_STORE_OP: return false;
case MEMORY_BARRIER_OP: return false;
default: break;
}
@@ -1163,10 +1139,8 @@ public:
switch(inst.op) {
case LOAD_OP: break;
case TENSOR_CORE_LOAD_OP: break;
- case VP_LOAD_OP: break;
case STORE_OP: break;
case TENSOR_CORE_STORE_OP: break;
- case VP_STORE_OP: break;
case MEMORY_BARRIER_OP: break;
default: return false;
}
@@ -1255,12 +1229,10 @@ enum pipeline_stage_name_t {
ID_OC_SP=0,
ID_OC_SFU,
ID_OC_TENSOR_CORE,
- ID_OC_VP_CORE,
ID_OC_MEM,
OC_EX_SP,
OC_EX_SFU,
OC_EX_TENSOR_CORE,
- OC_EX_VP_CORE,
OC_EX_MEM,
EX_WB,
N_PIPELINE_STAGES
@@ -1270,12 +1242,10 @@ const char* const pipeline_stage_name_decode[] = {
"ID_OC_SP",
"ID_OC_SFU",
"ID_OC_TENSOR_CORE",
- "ID_OC_VP_CORE",
"ID_OC_MEM",
"OC_EX_SP",
"OC_EX_SFU",
"OC_EX_TENSOR_CORE",
- "OC_EX_VP_CORE",
"OC_EX_MEM",
"EX_WB",
"N_PIPELINE_STAGES"
@@ -1328,12 +1298,6 @@ struct shader_core_config : public core_config
gpgpu_operand_collector_num_in_ports_tensor_core=8;
gpgpu_operand_collector_num_out_ports_tensor_core=8;
- max_vp_core_latency = 512;
- gpgpu_num_vp_core_units=8;
- gpgpu_operand_collector_num_units_vp_core=24;
- gpgpu_operand_collector_num_in_ports_vp_core=8;
- gpgpu_operand_collector_num_out_ports_vp_core=8;
-
m_L1I_config.init(m_L1I_config.m_config_string,FuncCachePreferNone);
m_L1T_config.init(m_L1T_config.m_config_string,FuncCachePreferNone);
m_L1C_config.init(m_L1C_config.m_config_string,FuncCachePreferNone);
@@ -1381,28 +1345,24 @@ struct shader_core_config : public core_config
int gpgpu_operand_collector_num_units_sp;
int gpgpu_operand_collector_num_units_sfu;
int gpgpu_operand_collector_num_units_tensor_core;
- int gpgpu_operand_collector_num_units_vp_core;
int gpgpu_operand_collector_num_units_mem;
int gpgpu_operand_collector_num_units_gen;
unsigned int gpgpu_operand_collector_num_in_ports_sp;
unsigned int gpgpu_operand_collector_num_in_ports_sfu;
unsigned int gpgpu_operand_collector_num_in_ports_tensor_core;
- unsigned int gpgpu_operand_collector_num_in_ports_vp_core;
unsigned int gpgpu_operand_collector_num_in_ports_mem;
unsigned int gpgpu_operand_collector_num_in_ports_gen;
unsigned int gpgpu_operand_collector_num_out_ports_sp;
unsigned int gpgpu_operand_collector_num_out_ports_sfu;
unsigned int gpgpu_operand_collector_num_out_ports_tensor_core;
- unsigned int gpgpu_operand_collector_num_out_ports_vp_core;
unsigned int gpgpu_operand_collector_num_out_ports_mem;
unsigned int gpgpu_operand_collector_num_out_ports_gen;
int gpgpu_num_sp_units;
int gpgpu_num_sfu_units;
int gpgpu_num_tensor_core_units;
- int gpgpu_num_vp_core_units;
int gpgpu_num_mem_units;
//Shader core resources
@@ -1416,7 +1376,6 @@ struct shader_core_config : public core_config
unsigned max_sp_latency;
unsigned max_sfu_latency;
unsigned max_tensor_core_latency;
- unsigned max_vp_core_latency;
unsigned n_simt_cores_per_cluster;
unsigned n_simt_clusters;
@@ -1433,7 +1392,7 @@ struct shader_core_config : public core_config
struct shader_core_stats_pod {
- void* shader_core_stats_pod_start[]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure
+ void* shader_core_stats_pod_start[0]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure
unsigned long long *shader_cycles;
unsigned *m_num_sim_insn; // number of scalar thread instructions committed by this shader core
unsigned *m_num_sim_winsn; // number of warp instructions committed by this shader core
@@ -1455,7 +1414,6 @@ struct shader_core_stats_pod {
unsigned *m_num_sp_acesses;
unsigned *m_num_sfu_acesses;
unsigned *m_num_tensor_core_acesses;
- unsigned *m_num_vp_core_acesses;
unsigned *m_num_trans_acesses;
unsigned *m_num_mem_acesses;
unsigned *m_num_sp_committed;
@@ -1463,7 +1421,6 @@ struct shader_core_stats_pod {
unsigned *m_num_tlb_accesses;
unsigned *m_num_sfu_committed;
unsigned *m_num_tensor_core_committed;
- unsigned *m_num_vp_core_committed;
unsigned *m_num_mem_committed;
unsigned *m_read_regfile_acesses;
unsigned *m_write_regfile_acesses;
@@ -1473,7 +1430,6 @@ struct shader_core_stats_pod {
unsigned *m_active_sp_lanes;
unsigned *m_active_sfu_lanes;
unsigned *m_active_tensor_core_lanes;
- unsigned *m_active_vp_core_lanes;
unsigned *m_active_fu_lanes;
unsigned *m_active_fu_mem_lanes;
unsigned *m_n_diverge; // number of divergence occurring in this shader
@@ -1546,7 +1502,6 @@ public:
m_num_sp_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_sfu_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_tensor_core_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
- m_num_vp_core_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_trans_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_mem_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_sp_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
@@ -1555,12 +1510,10 @@ public:
m_active_sp_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_active_sfu_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_active_tensor_core_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
- m_active_vp_core_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_active_fu_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_active_fu_mem_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_sfu_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_tensor_core_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
- m_num_vp_core_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_num_mem_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_read_regfile_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
m_write_regfile_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned));
diff --git a/src/gpgpu-sim/traffic_breakdown.cc b/src/gpgpu-sim/traffic_breakdown.cc
index 587067f..32f0d30 100644
--- a/src/gpgpu-sim/traffic_breakdown.cc
+++ b/src/gpgpu-sim/traffic_breakdown.cc
@@ -46,7 +46,6 @@ std::string traffic_breakdown::classify_memfetch(class mem_fetch * mf)
break;
default: assert(0 && "Unknown traffic type");
}
- printf("%s:Icnt:%s:Request: %x,Size%d,DataSize:%d,CntrlSize%d:\n",m_network_name.c_str(),traffic_name.c_str(),mf->get_addr(),mf->size(),mf->get_data_size(),mf->get_ctrl_size());
return traffic_name;
}
generated by cgit v1.3 (git 2.53.0) at 2026-07-21 06:12:15 +0000