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-rw-r--r--src/gpgpu-sim/dram.cc5
-rw-r--r--src/gpgpu-sim/dram.h5
-rw-r--r--src/gpgpu-sim/gpu-cache.cc6
-rw-r--r--src/gpgpu-sim/gpu-cache.h5
-rw-r--r--src/gpgpu-sim/gpu-sim.cc18
-rw-r--r--src/gpgpu-sim/gpu-sim.h3
-rw-r--r--src/gpgpu-sim/l2cache.cc5
-rw-r--r--src/gpgpu-sim/l2cache.h5
-rw-r--r--src/gpgpu-sim/power_interface.cc5
-rw-r--r--src/gpgpu-sim/power_interface.h5
-rw-r--r--src/gpgpu-sim/power_stat.cc5
-rw-r--r--src/gpgpu-sim/power_stat.h5
-rw-r--r--src/gpgpu-sim/shader.cc21
-rw-r--r--src/gpgpu-sim/shader.h50
14 files changed, 73 insertions, 70 deletions
diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc
index 545c45d..662c2ed 100644
--- a/src/gpgpu-sim/dram.cc
+++ b/src/gpgpu-sim/dram.cc
@@ -1,6 +1,7 @@
// Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda,
-// Ivan Sham, George L. Yuan, Vijay Kandiah, Nikos Hardavellas
-// The University of British Columbia, Northwestern University
+// Ivan Sham, George L. Yuan, Vijay Kandiah, Nikos Hardavellas,
+// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers
+// The University of British Columbia, Northwestern University, Purdue University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h
index 88e46ed..90ea3e4 100644
--- a/src/gpgpu-sim/dram.h
+++ b/src/gpgpu-sim/dram.h
@@ -1,6 +1,7 @@
// Copyright (c) 2009-2021, Tor M. Aamodt, Ivan Sham, Ali Bakhoda,
-// George L. Yuan, Wilson W.L. Fung, Vijay Kandiah, Nikos Hardavellas
-// The University of British Columbia, Northwestern University
+// George L. Yuan, Wilson W.L. Fung, Vijay Kandiah, Nikos Hardavellas,
+// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers
+// The University of British Columbia, Northwestern University, Purdue University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index a2aeec5..3a5a67d 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -1,5 +1,7 @@
-// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas
-// The University of British Columbia, Northwestern University
+// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington,
+// Vijay Kandiah, Nikos Hardavellas, Mahmoud Khairy, Junrui Pan,
+// Timothy G. Rogers
+// The University of British Columbia, Northwestern University, Purdue University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index 498dfeb..4bbf7e2 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -1,5 +1,6 @@
-// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas
-// The University of British Columbia, Northwestern University
+// Copyright (c) 2009-2021, Tor M. Aamodt, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas,
+// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers
+// The University of British Columbia, Northwestern University, Purdue University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index e44551e..5af244b 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -1,6 +1,7 @@
// Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, George L. Yuan,
-// Ali Bakhoda, Andrew Turner, Ivan Sham, Vijay Kandiah, Nikos Hardavellas
-// The University of British Columbia, Northwestern University
+// Ali Bakhoda, Andrew Turner, Ivan Sham, Vijay Kandiah, Nikos Hardavellas,
+// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers
+// The University of British Columbia, Northwestern University, Purdue University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -394,7 +395,7 @@ void shader_core_config::reg_options(class OptionParser *opp) {
"gpgpu_ignore_resources_limitation (default 0)", "0");
option_parser_register(
opp, "-gpgpu_shader_cta", OPT_UINT32, &max_cta_per_core,
- "Maximum number of concurrent CTAs in shader (default 8)", "8");
+ "Maximum number of concurrent CTAs in shader (default 32)", "32");
option_parser_register(
opp, "-gpgpu_num_cta_barriers", OPT_UINT32, &max_barriers_per_cta,
"Maximum number of named barriers per CTA (default 16)", "16");
@@ -700,7 +701,8 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) {
"500.0:2000.0:2000.0:2000.0");
option_parser_register(
opp, "-gpgpu_max_concurrent_kernel", OPT_INT32, &max_concurrent_kernel,
- "maximum kernels that can run concurrently on GPU", "8");
+ "maximum kernels that can run concurrently on GPU, set this value "
+ "according to max resident grids for your compute capability", "32");
option_parser_register(
opp, "-gpgpu_cflog_interval", OPT_INT32, &gpgpu_cflog_interval,
"Interval between each snapshot in control flow logger", "0");
@@ -1638,9 +1640,9 @@ bool shader_core_ctx::occupy_shader_resource_1block(kernel_info_t &k,
SHADER_DPRINTF(LIVENESS,
"GPGPU-Sim uArch: Occupied %u threads, %u shared mem, %u "
- "registers, %u ctas\n",
+ "registers, %u ctas, on shader %d\n",
m_occupied_n_threads, m_occupied_shmem, m_occupied_regs,
- m_occupied_ctas);
+ m_occupied_ctas, m_sid);
}
return true;
@@ -1806,9 +1808,9 @@ void shader_core_ctx::issue_block2core(kernel_info_t &kernel) {
shader_CTA_count_log(m_sid, 1);
SHADER_DPRINTF(LIVENESS,
"GPGPU-Sim uArch: cta:%2u, start_tid:%4u, end_tid:%4u, "
- "initialized @(%lld,%lld)\n",
+ "initialized @(%lld,%lld), kernel_uid:%u, kernel_name:%s\n",
free_cta_hw_id, start_thread, end_thread, m_gpu->gpu_sim_cycle,
- m_gpu->gpu_tot_sim_cycle);
+ m_gpu->gpu_tot_sim_cycle, kernel.get_uid(), kernel.get_name().c_str());
}
///////////////////////////////////////////////////////////////////////////////////////////
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index 68b3dfa..de69ef8 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -1,5 +1,6 @@
// Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Vijay Kandiah, Nikos Hardavellas
-// The University of British Columbia, Northwestern University
+// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers
+// The University of British Columbia, Northwestern University, Purdue University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc
index 511c15e..44d793c 100644
--- a/src/gpgpu-sim/l2cache.cc
+++ b/src/gpgpu-sim/l2cache.cc
@@ -1,5 +1,6 @@
-// Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas
-// The University of British Columbia, Northwestern University
+// Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas,
+// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers
+// The University of British Columbia, Northwestern University, Purdue University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h
index 902a4b7..7fa1f29 100644
--- a/src/gpgpu-sim/l2cache.h
+++ b/src/gpgpu-sim/l2cache.h
@@ -1,5 +1,6 @@
-// Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas
-// The University of British Columbia, Northwestern University
+// Copyright (c) 2009-2021, Tor M. Aamodt, Vijay Kandiah, Nikos Hardavellas,
+// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers
+// The University of British Columbia, Northwestern University, Purdue University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/gpgpu-sim/power_interface.cc b/src/gpgpu-sim/power_interface.cc
index 63b9852..470f2f9 100644
--- a/src/gpgpu-sim/power_interface.cc
+++ b/src/gpgpu-sim/power_interface.cc
@@ -1,5 +1,6 @@
-// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas
-// The University of British Columbia, Northwestern University
+// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas,
+// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers
+// The University of British Columbia, Northwestern University, Purdue University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/gpgpu-sim/power_interface.h b/src/gpgpu-sim/power_interface.h
index 1a48894..1c6c510 100644
--- a/src/gpgpu-sim/power_interface.h
+++ b/src/gpgpu-sim/power_interface.h
@@ -1,5 +1,6 @@
-// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas
-// The University of British Columbia, Northwestern University
+// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas,
+// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers
+// The University of British Columbia, Northwestern University, Purdue University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/gpgpu-sim/power_stat.cc b/src/gpgpu-sim/power_stat.cc
index fd7a775..d0e673c 100644
--- a/src/gpgpu-sim/power_stat.cc
+++ b/src/gpgpu-sim/power_stat.cc
@@ -1,5 +1,6 @@
-// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas
-// The University of British Columbia, Northwestern University
+// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas,
+// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers
+// The University of British Columbia, Northwestern University, Purdue University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/gpgpu-sim/power_stat.h b/src/gpgpu-sim/power_stat.h
index e2c3ed5..d40f1d9 100644
--- a/src/gpgpu-sim/power_stat.h
+++ b/src/gpgpu-sim/power_stat.h
@@ -1,5 +1,6 @@
-// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas
-// The University of British Columbia, Northwestern University
+// Copyright (c) 2009-2021, Tor M. Aamodt, Ahmed El-Shafiey, Tayler Hetherington, Vijay Kandiah, Nikos Hardavellas,
+// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers
+// The University of British Columbia, Northwestern University, Purdue University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index c0161dd..6f68283 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1,6 +1,7 @@
// Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda,
-// George L. Yuan, Andrew Turner, Inderpreet Singh, Vijay Kandiah, Nikos Hardavellas
-// The University of British Columbia, Northwestern University
+// George L. Yuan, Andrew Turner, Inderpreet Singh, Vijay Kandiah, Nikos Hardavellas,
+// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers
+// The University of British Columbia, Northwestern University, Purdue University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -950,7 +951,7 @@ void shader_core_ctx::fetch() {
m_threadState[tid].m_active = false;
unsigned cta_id = m_warp[warp_id]->get_cta_id();
if (m_thread[tid] == NULL) {
- register_cta_thread_exit(cta_id, m_kernel);
+ register_cta_thread_exit(cta_id, m_warp[warp_id]->get_kernel_info());
} else {
register_cta_thread_exit(cta_id,
&(m_thread[tid]->get_kernel()));
@@ -2091,10 +2092,11 @@ bool ldst_unit::constant_cycle(warp_inst_t &inst, mem_stage_stall_type &rc_fail,
mem_stage_stall_type fail;
if (m_config->perfect_inst_const_cache) {
fail = NO_RC_FAIL;
+ unsigned access_count = inst.accessq_count();
while (inst.accessq_count() > 0) inst.accessq_pop_back();
if (inst.is_load()) {
for (unsigned r = 0; r < MAX_OUTPUT_VALUES; r++)
- if (inst.out[r] > 0) m_pending_writes[inst.warp_id()][inst.out[r]]--;
+ if (inst.out[r] > 0) m_pending_writes[inst.warp_id()][inst.out[r]] -= access_count;
}
} else {
fail = process_memory_access_queue(m_L1C, inst);
@@ -3897,6 +3899,8 @@ void shader_core_ctx::get_icnt_power_stats(long &n_simt_to_mem,
n_mem_to_simt += m_stats->n_mem_to_simt[m_sid];
}
+kernel_info_t* shd_warp_t::get_kernel_info() const { return m_shader->get_kernel_info(); }
+
bool shd_warp_t::functional_done() const {
return get_n_completed() == m_warp_size;
}
@@ -4238,12 +4242,19 @@ bool opndcoll_rfu_t::collector_unit_t::allocate(register_set *pipeline_reg_set,
warp_inst_t **pipeline_reg = pipeline_reg_set->get_ready();
if ((pipeline_reg) and !((*pipeline_reg)->empty())) {
m_warp_id = (*pipeline_reg)->warp_id();
+ std::vector<int> prev_regs; // remove duplicate regs within same instr
for (unsigned op = 0; op < MAX_REG_OPERANDS; op++) {
int reg_num =
(*pipeline_reg)
->arch_reg.src[op]; // this math needs to match that used in
// function_info::ptx_decode_inst
- if (reg_num >= 0) { // valid register
+ bool new_reg = true;
+ for (auto r : prev_regs) {
+ if (r == reg_num)
+ new_reg = false;
+ }
+ if (reg_num >= 0 && new_reg) { // valid register
+ prev_regs.push_back(reg_num);
m_src_op[op] = op_t(this, op, reg_num, m_num_banks, m_bank_warp_shift,
m_sub_core_model, m_num_banks_per_sched,
(*pipeline_reg)->get_schd_id());
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 65d5625..deea1c9 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1,6 +1,7 @@
// Copyright (c) 2009-2021, Tor M. Aamodt, Wilson W.L. Fung, Andrew Turner,
-// Ali Bakhoda, Vijay Kandiah, Nikos Hardavellas
-// The University of British Columbia, Northwestern University
+// Ali Bakhoda, Vijay Kandiah, Nikos Hardavellas,
+// Mahmoud Khairy, Junrui Pan, Timothy G. Rogers
+// The University of British Columbia, Northwestern University, Purdue University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -170,6 +171,7 @@ class shd_warp_t {
void clear_membar() { m_membar = false; }
bool get_membar() const { return m_membar; }
virtual address_type get_pc() const { return m_next_pc; }
+ virtual kernel_info_t* get_kernel_info() const;
void set_next_pc(address_type pc) { m_next_pc = pc; }
void store_info_of_last_inst_at_barrier(const warp_inst_t *pI) {
@@ -954,41 +956,19 @@ class opndcoll_rfu_t { // operand collector based register file unit
void init(bool sub_core_model, unsigned num_warp_scheds) {
m_sub_core_model = sub_core_model;
m_num_warp_scheds = num_warp_scheds;
- if (m_sub_core_model) {
- m_last_cu_set = new unsigned(m_num_warp_scheds);
- for (unsigned i = 0; i < m_num_warp_scheds; i++)
- {
- m_last_cu_set[i] = i * m_num_collectors / m_num_warp_scheds;
- }
- }
-
}
collector_unit_t *find_ready() {
- if (m_sub_core_model) {
- assert(m_num_collectors % m_num_warp_scheds == 0 &&
- m_num_collectors >= m_num_warp_scheds);
- unsigned cusPerSched = m_num_collectors / m_num_warp_scheds;
- for (unsigned i = 0; i < m_num_warp_scheds; i++) {
- unsigned cuLowerBound = i * cusPerSched;
- unsigned cuUpperBound = cuLowerBound + cusPerSched;
- assert(0 <= cuLowerBound && cuUpperBound <= m_num_collectors);
- assert(cuLowerBound <= m_last_cu_set[i] && m_last_cu_set[i] <= cuUpperBound);
- for (unsigned j = cuLowerBound; j < cuUpperBound; j++) {
- unsigned c = cuLowerBound + (m_last_cu_set[i] + j + 1) % cusPerSched;
- if ((*m_collector_units)[c].ready()) {
- m_last_cu_set[i] = c;
- return &((*m_collector_units)[c]);
- }
- }
- }
- } else {
- for (unsigned n = 0; n < m_num_collectors; n++) {
- unsigned c = (m_last_cu + n + 1) % m_num_collectors;
- if ((*m_collector_units)[c].ready()) {
- m_last_cu = c;
- return &((*m_collector_units)[c]);
- }
+ // With sub-core enabled round robin starts with the next cu assigned to a
+ // different sub-core than the one that dispatched last
+ unsigned cusPerSched = m_num_collectors / m_num_warp_scheds;
+ unsigned rr_increment = m_sub_core_model ?
+ cusPerSched - (m_last_cu % cusPerSched) : 1;
+ for (unsigned n = 0; n < m_num_collectors; n++) {
+ unsigned c = (m_last_cu + n + rr_increment) % m_num_collectors;
+ if ((*m_collector_units)[c].ready()) {
+ m_last_cu = c;
+ return &((*m_collector_units)[c]);
}
}
return NULL;
@@ -998,9 +978,7 @@ class opndcoll_rfu_t { // operand collector based register file unit
unsigned m_num_collectors;
std::vector<collector_unit_t> *m_collector_units;
unsigned m_last_cu; // dispatch ready cu's rr
- unsigned *m_last_cu_set;
unsigned m_next_cu; // for initialization
-
bool m_sub_core_model;
unsigned m_num_warp_scheds;
};
generated by cgit v1.3 (git 2.53.0) at 2026-07-22 02:12:20 +0000