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-rw-r--r--src/abstract_hardware_model.cc4
-rw-r--r--src/abstract_hardware_model.h10
-rw-r--r--src/gpgpu-sim/addrdec.cc15
-rw-r--r--src/gpgpu-sim/gpu-cache.cc3
-rw-r--r--src/gpgpu-sim/gpu-cache.h5
-rw-r--r--src/gpgpu-sim/gpu-sim.cc2
-rw-r--r--src/gpgpu-sim/shader.cc68
7 files changed, 64 insertions, 43 deletions
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index 4bfe3c9..7922bc5 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -746,7 +746,7 @@ kernel_info_t::kernel_info_t(dim3 gridDim, dim3 blockDim,
// Jin: launch latency management
m_launch_latency = entry->gpgpu_ctx->device_runtime->g_kernel_launch_latency;
- volta_cache_config_set = false;
+ cache_config_set = false;
}
/*A snapshot of the texture mappings needs to be stored in the kernel's info as
@@ -773,7 +773,7 @@ kernel_info_t::kernel_info_t(
// Jin: launch latency management
m_launch_latency = entry->gpgpu_ctx->device_runtime->g_kernel_launch_latency;
- volta_cache_config_set = false;
+ cache_config_set = false;
m_NameToCudaArray = nameToCudaArray;
m_NameToTextureInfo = nameToTextureInfo;
}
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index dda4ead..4a6e02a 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -65,6 +65,12 @@ enum FuncCache {
FuncCachePreferL1 = 2
};
+enum AdaptiveCache
+{
+ FIXED = 0,
+ VOLTA = 1
+};
+
#ifdef __cplusplus
#include <stdio.h>
@@ -323,7 +329,7 @@ class kernel_info_t {
unsigned long long end_cycle;
unsigned m_launch_latency;
- mutable bool volta_cache_config_set;
+ mutable bool cache_config_set;
};
class core_config {
@@ -369,7 +375,7 @@ class core_config {
unsigned gpgpu_max_insn_issue_per_warp;
bool gmem_skip_L1D; // on = global memory access always skip the L1 cache
- bool adaptive_volta_cache_config;
+ bool adaptive_cache_config;
};
// bounded stack that implements simt reconvergence using pdom mechanism from
diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc
index 655d790..6ae57a1 100644
--- a/src/gpgpu-sim/addrdec.cc
+++ b/src/gpgpu-sim/addrdec.cc
@@ -144,16 +144,11 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr,
if (m_n_channel == 32) {
std::bitset<64> a(tlx->row);
std::bitset<5> chip(tlx->chip);
- chip[0] = a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[6] ^ a[5] ^ a[3] ^
- a[0] ^ chip[0];
- chip[1] = a[14] ^ a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[7] ^ a[6] ^ a[4] ^
- a[1] ^ chip[1];
- chip[2] = a[14] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[6] ^ a[3] ^ a[2] ^
- a[0] ^ chip[2];
- chip[3] =
- a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[4] ^ a[3] ^ a[1] ^ chip[3];
- chip[4] =
- a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[5] ^ a[4] ^ a[2] ^ chip[4];
+ chip[0] = a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[6] ^ a[5] ^ a[3] ^ a[0] ^ chip[0];
+ chip[1] = a[14] ^ a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[7] ^ a[6] ^ a[4] ^ a[1] ^ chip[1];
+ chip[2] = a[14] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[6] ^ a[3] ^ a[2] ^ a[0] ^ chip[2];
+ chip[3] = a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[7] ^ a[4] ^ a[3] ^ a[1] ^ chip[3];
+ chip[4] = a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[5] ^ a[4] ^ a[2] ^ chip[4];
tlx->chip = chip.to_ulong();
} else { /* Else incorrect number of channels for the hashing function */
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index 76f9aef..5cdeeb1 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -59,6 +59,9 @@ const char *cache_fail_status_str(enum cache_reservation_fail_reason status) {
}
unsigned l1d_cache_config::set_bank(new_addr_type addr) const {
+ //For sector cache, we select one sector per bank (sector interleaving)
+ //This is what was found in Volta (one sector per bank, sector interleaving)
+ //otherwise, line interleaving
if (m_cache_type == SECTOR)
return (addr >> m_sector_sz_log2) & (l1_banks - 1);
else
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index d4bc9b4..7554b3f 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -677,6 +677,11 @@ class cache_config {
assert(m_valid);
return MAX_DEFAULT_CACHE_SIZE_MULTIBLIER * m_nset * original_m_assoc;
}
+ unsigned get_max_assoc() const
+ {
+ assert( m_valid );
+ return MAX_DEFAULT_CACHE_SIZE_MULTIBLIER * original_m_assoc;
+ }
void print(FILE *fp) const {
fprintf(fp, "Size = %d B (%d Set x %d-way x %d byte line)\n",
m_line_sz * m_nset * m_assoc, m_nset, m_assoc, m_line_sz);
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 485d42e..5ded780 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -319,7 +319,7 @@ void shader_core_config::reg_options(class OptionParser *opp) {
opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size,
"Size of shared memory per shader core (default 16kB)", "16384");
option_parser_register(opp, "-adaptive_cache_config", OPT_BOOL,
- &adaptive_volta_cache_config, "adaptive_cache_config",
+ &adaptive_cache_config, "adaptive_cache_config",
"0");
option_parser_register(
opp, "-gpgpu_shmem_sizeDefault", OPT_UINT32, &gpgpu_shmem_sizeDefault,
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index c7738c0..16bc770 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -3082,36 +3082,48 @@ unsigned int shader_core_config::max_cta(const kernel_info_t &k) const {
abort();
}
- if (adaptive_volta_cache_config && !k.volta_cache_config_set) {
- // For Volta, we assign the remaining shared memory to L1 cache
- // For more info, see
- // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
- unsigned total_shmed = kernel_info->smem * result;
- assert(total_shmed >= 0 && total_shmed <= gpgpu_shmem_size);
- assert(gpgpu_shmem_size == 98304); // Volta has 96 KB shared
- assert(m_L1D_config.get_nset() == 4); // Volta L1 has four sets
- if (total_shmed < gpgpu_shmem_size) {
- if (total_shmed == 0)
- m_L1D_config.set_assoc(256); // L1 is 128KB ans shd=0
- else if (total_shmed > 0 && total_shmed <= 8192)
- m_L1D_config.set_assoc(240); // L1 is 120KB ans shd=8KB
- else if (total_shmed > 8192 && total_shmed <= 16384)
- m_L1D_config.set_assoc(224); // L1 is 112KB ans shd=16KB
- else if (total_shmed > 16384 && total_shmed <= 32768)
- m_L1D_config.set_assoc(192); // L1 is 96KB ans shd=32KB
- else if (total_shmed > 32768 && total_shmed <= 65536)
- m_L1D_config.set_assoc(128); // L1 is 64KB ans shd=64KB
- else if (total_shmed > 65536 && total_shmed <= gpgpu_shmem_size)
- m_L1D_config.set_assoc(64); // L1 is 32KB and shd=96KB
- else
- assert(0);
+ if(adaptive_cache_config && !k.cache_config_set) {
+ //For more info about adaptive cache, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
+ unsigned total_shmed = kernel_info->smem * result;
+ assert(total_shmed >=0 && total_shmed <= gpgpu_shmem_size);
+ //assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared
+ //assert(m_L1D_config.get_nset() == 4); //Volta L1 has four sets
+ if(total_shmed < gpgpu_shmem_size){
+ switch (adaptive_cache_config) {
+ case FIXED:
+ break;
+ case VOLTA: {
+ //For Volta, we assign the remaining shared memory to L1 cache
+ //For more info about adaptive cache, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
+ assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared
- printf("GPGPU-Sim: Reconfigure L1 cache in Volta Archi to %uKB\n",
- m_L1D_config.get_total_size_inKB());
- }
+ //To Do: make it flexible and not tuned to 9KB share memory
+ unsigned max_assoc = m_L1D_config.get_max_assoc();
+ if(total_shmed == 0)
+ m_L1D_config.set_assoc(max_assoc); //L1 is 128KB and shd=0
+ else if(total_shmed > 0 && total_shmed <= 8192)
+ m_L1D_config.set_assoc(0.9375 * max_assoc); //L1 is 120KB and shd=8KB
+ else if(total_shmed > 8192 && total_shmed <= 16384)
+ m_L1D_config.set_assoc(0.875 * max_assoc); //L1 is 112KB and shd=16KB
+ else if(total_shmed > 16384 && total_shmed <= 32768)
+ m_L1D_config.set_assoc(0.75 * max_assoc); //L1 is 96KB and shd=32KB
+ else if(total_shmed > 32768 && total_shmed <= 65536)
+ m_L1D_config.set_assoc(0.5 * max_assoc); //L1 is 64KB and shd=64KB
+ else if(total_shmed > 65536 && total_shmed <= gpgpu_shmem_size)
+ m_L1D_config.set_assoc(0.25 * max_assoc); //L1 is 32KB and shd=96KB
+ else
+ assert(0);
+ break;
+ }
+ default:
+ assert(0);
+ }
- k.volta_cache_config_set = true;
- }
+ printf ("GPGPU-Sim: Reconfigure L1 cache to %uKB\n", m_L1D_config.get_total_size_inKB());
+ }
+
+ k.cache_config_set = true;
+ }
return result;
}
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