diff options
Diffstat (limited to 'src')
33 files changed, 189 insertions, 711 deletions
diff --git a/src/Makefile b/src/Makefile index 09194f3..6001669 100644 --- a/src/Makefile +++ b/src/Makefile @@ -46,7 +46,7 @@ ifeq ($(TRACE),1) endif ifneq ($(DEBUG),1) - OPTFLAGS += -O0 + OPTFLAGS += -O3 else CXXFLAGS += endif diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index 72ece0b..f7f1016 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -184,7 +184,7 @@ void warp_inst_t::generate_mem_accesses() { if( empty() || op == MEMORY_BARRIER_OP || m_mem_accesses_created ) return; - if (!((op == LOAD_OP) || (op==TENSOR_CORE_LOAD_OP) || (op==VP_LOAD_OP) || (op == STORE_OP)||(op==TENSOR_CORE_STORE_OP)||(op==VP_STORE_OP))) + if (!((op == LOAD_OP) || (op==TENSOR_CORE_LOAD_OP) || (op == STORE_OP)||(op==TENSOR_CORE_STORE_OP))) return; if( m_warp_active_mask.count() == 0 ) return; // predicated off @@ -352,7 +352,6 @@ void warp_inst_t::generate_mem_accesses() ptx_file_line_stats_add_uncoalesced_gmem( pc, m_accessq.size() - starting_queue_size ); } m_mem_accesses_created=true; - print_m_accessq(); } void warp_inst_t::memory_coalescing_arch_13( bool is_write, mem_access_type access_type ) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index d628745..f561f34 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -78,13 +78,10 @@ enum uarch_op_t { ALU_OP=1, SFU_OP, TENSOR_CORE_OP, - VP_CORE_OP, ALU_SFU_OP, LOAD_OP, - VP_LOAD_OP, TENSOR_CORE_LOAD_OP, TENSOR_CORE_STORE_OP, - VP_STORE_OP, STORE_OP, BRANCH_OP, BARRIER_OP, @@ -140,7 +137,6 @@ enum operation_pipeline_t { SP__OP, SFU__OP, TENSOR_CORE__OP, - VP_CORE__OP, MEM__OP }; typedef enum operation_pipeline_t operation_pipeline; @@ -805,8 +801,8 @@ public: { fprintf(fp," [inst @ pc=0x%04x] ", pc ); } - bool is_load() const { return (op == LOAD_OP ||op==TENSOR_CORE_LOAD_OP||op==VP_LOAD_OP || memory_op == memory_load); } - bool is_store() const { return (op == STORE_OP ||op==TENSOR_CORE_STORE_OP||op==VP_STORE_OP || memory_op == memory_store); } + bool is_load() const { return (op == LOAD_OP ||op==TENSOR_CORE_LOAD_OP || memory_op == memory_load); } + bool is_store() const { return (op == STORE_OP ||op==TENSOR_CORE_STORE_OP || memory_op == memory_store); } unsigned get_num_operands() const {return num_operands;} unsigned get_num_regs() const {return num_regs;} void set_num_regs(unsigned num) {num_regs=num;} diff --git a/src/cuda-sim/.ptx.y.swp b/src/cuda-sim/.ptx.y.swp Binary files differdeleted file mode 100644 index c8a83b5..0000000 --- a/src/cuda-sim/.ptx.y.swp +++ /dev/null diff --git a/src/cuda-sim/Makefile b/src/cuda-sim/Makefile index d08a696..999dad7 100644 --- a/src/cuda-sim/Makefile +++ b/src/cuda-sim/Makefile @@ -42,7 +42,7 @@ include ../../version_detection.mk OUTPUT_DIR=$(SIM_OBJ_FILES_DIR)/cuda-sim -OPT := -O0 -g3 -Wall -Wno-unused-function -Wno-sign-compare +OPT := -O3 -g3 -Wall -Wno-unused-function -Wno-sign-compare ifeq ($(DEBUG),1) OPT := -g3 -Wall -Wno-unused-function -Wno-sign-compare endif @@ -62,7 +62,7 @@ ifeq ($(GNUC_CPP0X),1) endif endif -OBJS := $(OUTPUT_DIR)/ptx_parser.o $(OUTPUT_DIR)/ptx_loader.o $(OUTPUT_DIR)/cuda_device_printf.o $(OUTPUT_DIR)/instructions.o $(OUTPUT_DIR)/cuda-sim.o $(OUTPUT_DIR)/ptx_ir.o $(OUTPUT_DIR)/ptx_sim.o $(OUTPUT_DIR)/memory.o $(OUTPUT_DIR)/ptx-stats.o $(OUTPUT_DIR)/decuda_pred_table/decuda_pred_table.o $(OUTPUT_DIR)/ptx.tab.o $(OUTPUT_DIR)/lex.ptx_.o $(OUTPUT_DIR)/ptxinfo.tab.o $(OUTPUT_DIR)/lex.ptxinfo_.o $(OUTPUT_DIR)/cuda_device_runtime.o +OBJS := $(OUTPUT_DIR)/ptx_parser.o $(OUTPUT_DIR)/ptx_loader.o $(OUTPUT_DIR)/cuda_device_printf.o $(OUTPUT_DIR)/instructions.o $(OUTPUT_DIR)/cuda-sim.o $(OUTPUT_DIR)/ptx_ir.o $(OUTPUT_DIR)/ptx_sim.o $(OUTPUT_DIR)/memory.o $(OUTPUT_DIR)/ptx-stats.o $(OUTPUT_DIR)/decuda_pred_table/decuda_pred_table.o $(OUTPUT_DIR)/ptx.tab.o $(OUTPUT_DIR)/lex.ptx_.o $(OUTPUT_DIR)/ptxinfo.tab.o $(OUTPUT_DIR)/lex.ptxinfo_.o $(OUTPUT_DIR)/cuda_device_runtime.o OPT += -DCUDART_VERSION=$(CUDART_VERSION) diff --git a/src/cuda-sim/cuda-math.h b/src/cuda-sim/cuda-math.h index 314f813..a5db337 100644 --- a/src/cuda-sim/cuda-math.h +++ b/src/cuda-sim/cuda-math.h @@ -68,6 +68,8 @@ #ifndef CUDA_MATH #define CUDA_MATH +#include <cmath> + // cuda math implementations #undef max #undef min @@ -149,6 +151,7 @@ float __ll2float_rd(long long int a) { #include <device_types.h> #include <fenv.h> + // 32-bit integer to float float __int2float_rn(int a) { int orig_rnd_mode = fegetround(); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index dd7edd9..7587db7 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -542,7 +542,7 @@ void ptx_instruction::set_mul_div_or_other_archop(){ sp_op=INT_DIV_OP; break; default: - if((op==ALU_OP)||(op==VP_CORE_OP)) + if((op==ALU_OP)) sp_op=INT__OP; break; } @@ -649,11 +649,9 @@ void ptx_instruction::set_opcode_and_latency() break; case LD_OP: op = LOAD_OP; break; case MMA_LD_OP: op = TENSOR_CORE_LOAD_OP; break; - case VP_LD_OP: op = VP_LOAD_OP; break; case LDU_OP: op = LOAD_OP; break; case ST_OP: op = STORE_OP; break; case MMA_ST_OP: op = TENSOR_CORE_STORE_OP; break; - case VP_ST_OP: op = VP_STORE_OP; break; case BRA_OP: op = BRANCH_OP; break; case BREAKADDR_OP: op = BRANCH_OP; break; case TEX_OP: op = LOAD_OP; mem_op=TEX; break; @@ -801,26 +799,6 @@ void ptx_instruction::set_opcode_and_latency() initiation_interval = 64; op=TENSOR_CORE_OP; break; - case VP_MMA_OP: - if(get_wmma_type()==VP_MMA4) - { - latency = 64; - initiation_interval = 64; - } - if(get_wmma_type()==VP_MMA8) - { - latency =128; - initiation_interval = 128; - } - if(get_wmma_type()==VP_MMA16) - { - latency = 256; - initiation_interval = 256; - } - op=VP_CORE_OP; - op=VP_CORE_OP; - op=VP_CORE_OP; - break; case SHFL_OP: latency = 32; initiation_interval = 15; @@ -922,10 +900,10 @@ void ptx_instruction::pre_decode() case WT_OPTION: cache_op = CACHE_WRITE_THROUGH; break; default: //if( m_opcode == LD_OP || m_opcode == LDU_OP ) - if( m_opcode ==VP_LD_OP || m_opcode == MMA_LD_OP || m_opcode == LD_OP || m_opcode == LDU_OP ) + if( m_opcode == MMA_LD_OP || m_opcode == LD_OP || m_opcode == LDU_OP ) cache_op = CACHE_ALL; //else if( m_opcode == ST_OP ) - else if( m_opcode == VP_ST_OP ||m_opcode == MMA_ST_OP || m_opcode == ST_OP ) + else if( m_opcode == MMA_ST_OP || m_opcode == ST_OP ) cache_op = CACHE_WRITE_BACK; else if( m_opcode == ATOM_OP ) cache_op = CACHE_GLOBAL; @@ -1295,14 +1273,6 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) addr_t pc = next_instr(); assert( pc == inst.pc ); // make sure timing model and functional model are in sync const ptx_instruction *pI = m_func_info->get_instruction(pc); - //#if 0 - if(lane_id==0){ - //printf("EXECUTION_FLOW:LINE_NUM:%d\n",pI->source_line()); - printf("EXECUTION_FLOW:LINE_NUM:%d\n",pI->source_line()); - printf("EXECUTION_FLOW:INST:%s\n",pI->get_source()); - printf("EXECUTION_FLOW:PC%d\n",pc); - } - //#endif set_npc( pc + pI->inst_size() ); @@ -1349,12 +1319,12 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) pI = pJ; } - if(((inst_opcode==MMA_OP||inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_MMA_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP))){ + if(((inst_opcode==MMA_OP||inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP))){ if(inst.active_count()!=MAX_WARP_SIZE) while(1); } - if(((inst_opcode!=MMA_OP)&&(inst_opcode!=MMA_LD_OP)&&(inst_opcode!=MMA_ST_OP)&&(inst_opcode!=VP_LD_OP)&&(inst_opcode!=VP_ST_OP)&&(inst_opcode!=VP_MMA_OP))||((inst_opcode==MMA_OP||inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_MMA_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP)&&(lane_id==0))){ + if(((inst_opcode!=MMA_OP)&&(inst_opcode!=MMA_LD_OP)&&(inst_opcode!=MMA_ST_OP))||((inst_opcode==MMA_OP||inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP)&&(lane_id==0))){ switch ( inst_opcode ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; #define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; @@ -1405,8 +1375,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) _memory_op_t insn_memory_op = no_memory_op; unsigned insn_data_size = 0; if ( (pI->has_memory_read() || pI->has_memory_write()) ) { - if(!((inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP))) - //if(!((inst_opcode==MMA_LD_OP||inst_opcode==VP_LD_OP))) + if(!((inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP))) { insn_memaddr = last_eaddr(); insn_space = last_space(); @@ -1480,15 +1449,14 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) if ( (g_ptx_sim_num_insn % 100000) == 0 ) { dim3 ctaid = get_ctaid(); dim3 tid = get_tid(); - printf("GPGPU-Sim PTX: %u instructions simulated : ctaid=(%u,%u,%u) tid=(%u,%u,%u)\n", + DPRINTF(LIVENESS, "GPGPU-Sim PTX: %u instructions simulated : ctaid=(%u,%u,%u) tid=(%u,%u,%u)\n", g_ptx_sim_num_insn, ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z ); fflush(stdout); } // "Return values" if(!skip) { - if(!((inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP||inst_opcode==VP_LD_OP||inst_opcode==VP_ST_OP))) - //if(!((inst_opcode==MMA_LD_OP||inst_opcode==VP_LD_OP))) + if(!((inst_opcode==MMA_LD_OP||inst_opcode==MMA_ST_OP))) { inst.space = insn_space; inst.set_addr(lane_id, insn_memaddr); @@ -2150,7 +2118,7 @@ struct rec_pts { int s_num_recon; }; -struct std::map<function_info*,rec_pts> g_rpts; +class std::map<function_info*,rec_pts> g_rpts; struct rec_pts find_reconvergence_points( function_info *finfo ) { diff --git a/src/cuda-sim/half.hpp b/src/cuda-sim/half.h index 8f1a8eb..8f1a8eb 100644 --- a/src/cuda-sim/half.hpp +++ b/src/cuda-sim/half.h diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 52d89f2..2677c40 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -25,7 +25,7 @@ // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -#include "half.hpp" +#include "half.h" #include "instructions.h" #include "ptx_ir.h" #include "opcodes.h" @@ -48,7 +48,7 @@ using half_float::half; unsigned ptx_instruction::g_num_ptx_inst_uid=0; -bool g_debug_instruction = 1; +bool g_debug_instruction = 0; const char *g_opcode_string[NUM_OPCODES] = { @@ -129,15 +129,6 @@ unsigned thread_group_offset(int thread,unsigned wmma_type,unsigned wmma_layout } } break; - case VP_MMA: - case VP_MMA4: - case VP_MMA8: - case VP_MMA16: - if(wmma_layout==ROW) - offset=load_c_float_row[thread_group]+16*in_tg_index; - else - offset=load_c_float_col[thread_group]+in_tg_index; - break; default: abort(); @@ -1706,11 +1697,6 @@ void mapping(int thread,int wmma_type,int wmma_layout,int type,int index,int str } assg_offset=index; } - else if(wmma_type==VP_MMA || wmma_type==VP_MMA4 || wmma_type==VP_MMA8 || wmma_type==VP_MMA16){ - row=c_row_offset[thread/4]+thread%4; - col=c_col_offset[thread/4]+index; - assg_offset=index; - } if(wmma_type==LOAD_A||wmma_type==LOAD_B){ if(wmma_layout==ROW){ @@ -1724,152 +1710,6 @@ void mapping(int thread,int wmma_type,int wmma_layout,int type,int index,int str } } -void vp_mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) -{ - int i,j,k,thrd; - int row,col,offset; - ptx_reg_t matrix_a[16][16]; - ptx_reg_t matrix_b[16][16]; - ptx_reg_t matrix_c[16][16]; - ptx_reg_t matrix_d[16][16]; - ptx_reg_t src_data; - ptx_thread_info *thread; - int stride; - unsigned wmma_type = pI->get_wmma_type(); - unsigned a_layout = pI->get_wmma_layout(0); - unsigned b_layout = pI->get_wmma_layout(1); - unsigned type = pI->get_type(); - int tid = inst.warp_id_func() * core->get_warp_size(); - const operand_info &dst = pI->operand_lookup(0); - - unsigned thread_group_index; - - for (thrd=0; thrd < core->get_warp_size(); thrd++){ - thread = core->get_thread_info()[tid+thrd]; - if(g_debug_instruction) - printf("THREAD=%d\n:",thrd); - for(i=1;i<=3;i++){ - const operand_info &src_a= pI->operand_lookup(i); - unsigned nelem = src_a.get_vect_nelem(); - ptx_reg_t v[8]; - thread->get_vector_operand_values( src_a, v, nelem ); - if(g_debug_instruction){ - printf("Thread%d_Iteration=%d:",thrd,i); - for(k=0;k<nelem;k++){ - printf("%x ",v[k].u64); - } - printf("\n"); - } - int hex_val; - switch(i) { - case 1 ://operand 1 - for(k=0;k<8;k++){ - mapping(thrd,wmma_type,a_layout,S32_TYPE,k,16,row,col,offset); - if(g_debug_instruction) - printf("A:thread=%d,row=%d,col=%d,offset=%d\n",thrd,row,col,offset); - matrix_a[row][col]=v[offset]; - } - break; - case 2 ://operand 2 - for(k=0;k<8;k++){ - mapping(thrd,wmma_type,b_layout,S32_TYPE,k,16,row,col,offset); - if(g_debug_instruction) - printf("B:thread=%d,row=%d,col=%d,offset=%d\n",thrd,row,col,offset); - if(nelem==1){ - matrix_b[row][col].s32=((v[0].u32&(0xf<<4*k))>>4*k); - } - if(nelem==2){ - matrix_b[row][col].s32=((v[k/4].u32&(0xff<<8*(k%4)))>>8*(k%4)); - } - if(nelem==4){ - matrix_b[row][col].s32=((v[k/2].u32&(0xffff<<16*(k%2)))>>16*(k%2)); - } - } - break; - case 3 ://operand 3 - for(k=0;k<8;k++){ - mapping(thrd,wmma_type,ROW,S32_TYPE,k,16,row,col,offset); - if(g_debug_instruction) - printf("C:thread=%d,row=%d,col=%d,offset=%d\n",thrd,row,col,offset); - matrix_c[row][col]=v[offset]; - } - break; - default : - printf("Invalid Operand Index\n" ); - } - } - if(g_debug_instruction) - printf("\n"); - } - if(g_debug_instruction){ - printf("MATRIX_A\n"); - for (i=0;i<16;i++){ - for(j=0;j<16;j++){ - printf("%d ",matrix_a[i][j].s32); - } - printf("\n"); - } - } - printf("MATRIX_B\n"); - for (i=0;i<16;i++){ - for(j=0;j<16;j++){ - printf("%d ",matrix_b[i][j].s32); - } - printf("\n"); - } - printf("MATRIX_C\n"); - for (i=0;i<16;i++){ - for(j=0;j<16;j++){ - printf("%d ",matrix_c[i][j].s32); - } - printf("\n"); - } - for (i=0;i<16;i++){ - for(j=0;j<16;j++){ - matrix_d[i][j].f16=0; - } - } - - for (i=0;i<16;i++){ - for(j=0;j<16;j++){ - for(k=0;k<16;k++){ - matrix_d[i][j].s32=matrix_d[i][j].s32+matrix_a[i][k].s32*matrix_b[k][j].s32; - } - matrix_d[i][j].s32+=matrix_c[i][j].s32; - } - } - if(g_debug_instruction){ - printf("MATRIX_D\n"); - for (i=0;i<16;i++){ - for(j=0;j<16;j++){ - printf("%d ",matrix_d[i][j].s32); - } - printf("\n"); - } - } - for (thrd=0; thrd < core->get_warp_size(); thrd++){ - int row_t[8]; - int col_t[8]; - for(k=0;k<8;k++){ - mapping(thrd,wmma_type,ROW,type,k,16,row_t[k],col_t[k],offset); - if(g_debug_instruction) - printf("vp_mma:row:%d,col%d\n",row_t[k],col_t[k]); - } - thread = core->get_thread_info()[tid+thrd]; - - - thread->set_wmma_vector_operand_values(dst,matrix_d[row_t[0]][col_t[0]],matrix_d[row_t[1]][col_t[1]],matrix_d[row_t[2]][col_t[2]],matrix_d[row_t[3]][col_t[3]],matrix_d[row_t[4]][col_t[4]],matrix_d[row_t[5]][col_t[5]],matrix_d[row_t[6]][col_t[6]],matrix_d[row_t[7]][col_t[7]]); - - if(g_debug_instruction) - { - printf("thread%d:",thrd); - for(k=0;k<8;k++){ - printf("%d ",matrix_d[row_t[k]][col_t[k]].s32); - } - printf("\n"); - } - } -} void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { int i,j,k,thrd; @@ -2387,18 +2227,10 @@ ptx_reg_t f2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, } else { switch ( to_width ) { case 16: - mytemp=half(x.f32); - myfloat=mytemp; - y.f16 =mytemp; - #if 0 - printf("f2x: %f\n",myfloat); - #endif + y.f16 =half_float::half_cast<half,std::numeric_limits<float>::round_style>(x.f32);//mytemp; break; case 32: y.f32=float(x.f16); - #if 0 - printf("f2xnew:%x:my%f:%f\n",x.f16,y.f32,half_float::detail::half2float<float>(x.u16)); - #endif break; // handled by f2f case 64: y.f64 = x.f32; @@ -3119,78 +2951,6 @@ void ldu_impl( const ptx_instruction *pI, ptx_thread_info *thread ) ld_exec(pI,thread); } -void vp_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t & inst) -{ - size_t size; - unsigned smid; - int t; - int thrd,odd,inx,k; - ptx_thread_info *thread; - - const operand_info &src = pI->operand_lookup(1); - const operand_info &src1 = pI->operand_lookup(0); - const operand_info &src2 = pI->operand_lookup(2); - int tid = inst.warp_id_func()*core->get_warp_size(); - unsigned type = pI->get_type(); - unsigned wmma_type = pI->get_wmma_type(); - unsigned wmma_layout = pI->get_wmma_layout(0); - int stride; - _memory_op_t insn_memory_op = pI->has_memory_read() ? memory_load : memory_store; - for (thrd=0; thrd < core->get_warp_size(); thrd++) { - thread = core->get_thread_info()[tid+thrd]; - odd=thrd%2; - inx=thrd/2; - ptx_reg_t addr_reg = thread->get_operand_value(src1, src, type, thread, 1); - ptx_reg_t src2_data = thread->get_operand_value(src2, src, type, thread, 1); - const operand_info &src_a= pI->operand_lookup(1); - unsigned nelem = src_a.get_vect_nelem(); - ptx_reg_t* v= new ptx_reg_t[8]; - thread->get_vector_operand_values( src_a, v, nelem ); - stride=src2_data.u32; - - memory_space_t space = pI->get_space(); - new_addr_type mem_txn_addr[MAX_ACCESSES_PER_INSN_PER_THREAD]; - int num_mem_txn=0; - - memory_space *mem = NULL; - addr_t addr = addr_reg.u32; - - smid = thread->get_hw_sid(); - if( whichspace(addr) == shared_space ) { - addr= generic_to_shared(smid,addr); - space = shared_space; - } - decode_space(space,thread,src1,mem,addr); - - type_info_key::type_decode(type,size,t); - if(g_debug_instruction) - printf("vp_st: thrd=%d,addr=%x, fp(size=%d), stride=%d\n",thrd,addr_reg.u32,size,src2_data.u32); - addr_t new_addr = addr+thread_group_offset(thrd,VP_MMA,wmma_layout,type,stride)*size/8; - - if(g_debug_instruction){ - printf("vp_st:thread%d=%d,%d,%d,%d,%d,%d,%d,%d\n",thrd,v[0].s32,v[1].s32,v[2].s32,v[3].s32,v[4].s32,v[5].s32,v[6].s32,v[7].s32); - } - - for(k=0;k<8;k++){ - if(wmma_layout==ROW){ - mem->write(new_addr+4*k,size/8,&v[k].s64,thread,pI); - mem_txn_addr[num_mem_txn++]=new_addr+4*k; - } - else if(wmma_layout==COL){ - mem->write(new_addr+k*4*stride,size/8,&v[k].s64,thread,pI); - mem_txn_addr[num_mem_txn++]=new_addr+4*k*stride; - } - } - - delete [] v; - inst.space = space; - inst.set_addr(thrd, (new_addr_type *)mem_txn_addr , num_mem_txn); - inst.data_size = 4; // 4 byte transaction - assert( inst.memory_op == insn_memory_op ); -// thread->m_last_effective_address = addr; -// thread->m_last_memory_space = space; - } -} void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst ) { size_t size; @@ -3296,191 +3056,6 @@ void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst ) //thread->m_last_memory_space = space; } } -void vp_ld_impl(const ptx_instruction *pI, core_t *core, warp_inst_t &inst) -{ - size_t size; - int t,i; - unsigned smid; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - unsigned type = pI->get_type(); - unsigned wmma_type = pI->get_wmma_type(); - unsigned wmma_layout = pI->get_wmma_layout(0); - int tid = inst.warp_id_func()*core->get_warp_size(); - int thrd,stride; - ptx_thread_info *thread; - _memory_op_t insn_memory_op = pI->has_memory_read() ? memory_load : memory_store; - for (thrd=0; thrd < core->get_warp_size(); thrd++){ - thread = core->get_thread_info()[tid+thrd]; - ptx_reg_t src1_data = thread->get_operand_value(src1, dst, U32_TYPE, thread, 1); - ptx_reg_t src2_data = thread->get_operand_value(src2, dst, U32_TYPE, thread, 1); - stride=src2_data.u32; - memory_space_t space = pI->get_space(); - - new_addr_type mem_txn_addr[MAX_ACCESSES_PER_INSN_PER_THREAD]; - int num_mem_txn=0; - - memory_space *mem = NULL; - addr_t addr = src1_data.u32; - - smid = thread->get_hw_sid(); - if( whichspace(addr) == shared_space ) { - addr= generic_to_shared(smid,addr); - space = shared_space; - } - - decode_space(space,thread,src1,mem,addr); - type_info_key::type_decode(type,size,t); - - ptx_reg_t data[8]; - addr_t new_addr; - - //note we are using distribution of VP_MMA for every type of load! - if(wmma_type==LOAD_A||wmma_type==LOAD_C){ - new_addr = addr+thread_group_offset(thrd,VP_MMA,wmma_layout,type,stride)*size/8; - } - else if(wmma_type==LOAD_B4){ - new_addr = addr+thread_group_offset(thrd,VP_MMA,wmma_layout,type,stride)/2; - } - else if (wmma_type==LOAD_B8){ - new_addr = addr+thread_group_offset(thrd,VP_MMA,wmma_layout,type,stride); - } - else if (wmma_type==LOAD_B16){ - new_addr = addr+thread_group_offset(thrd,VP_MMA,wmma_layout,type,stride)*2; - } - - if(g_debug_instruction) - printf("vp_ld: thrx=%d,addr=%x, base_addr=%x, size=%d, stride=%d\n",thrd,new_addr,addr,size,src2_data.u32); - - if(wmma_type==LOAD_A||wmma_type==LOAD_C){ - printf("lda/c:"); - for(i=0;i<8;i++){ - if(wmma_layout==ROW){ - //mem->read(new_addr+4*i,size/8,&data[i].s64); - mem->read(new_addr+4*i,size/8,&data[i].s64); - printf("%x ", new_addr+4*i); - mem_txn_addr[num_mem_txn++]=new_addr+4*i; - } - else if(wmma_layout==COL){ - //mem->read(new_addr+4*stride*i,size/8,&data[i].s64); - printf("%x ", new_addr+4*stride*i); - mem->read(new_addr+4*stride*i,size/8,&data[i].s64); - mem_txn_addr[num_mem_txn++]=new_addr+4*stride*i; - } - } - - } - - else if(wmma_type==LOAD_B4){ - printf("ldb4:"); - if(wmma_layout==ROW){ - mem->read(new_addr,size/8,&data[0].s64); - printf("%x ",new_addr); - mem_txn_addr[num_mem_txn++]=new_addr; - } - else if(wmma_layout==COL){ - } - } - else if(wmma_type==LOAD_B8){ - printf("ldb8:"); - if(wmma_layout==ROW){ - mem->read(new_addr,size/8,&data[0].s64); - mem->read(new_addr+4,size/8,&data[1].s64); - printf("%x ",new_addr,new_addr+4); - - mem_txn_addr[num_mem_txn++]=new_addr; - mem_txn_addr[num_mem_txn++]=new_addr+4; - } - else if(wmma_layout==COL){ - - } - } - else if(wmma_type==LOAD_B16){ - printf("ldb16:"); - if(wmma_layout==ROW){ - mem->read(new_addr,size/8,&data[0].s64); - mem->read(new_addr+4,size/8,&data[1].s64); - mem->read(new_addr+8,size/8,&data[2].s64); - mem->read(new_addr+12,size/8,&data[3].s64); - printf("%x ",new_addr,new_addr+4,new_addr+8,new_addr+12); - mem_txn_addr[num_mem_txn++]=new_addr; - mem_txn_addr[num_mem_txn++]=new_addr+4; - mem_txn_addr[num_mem_txn++]=new_addr+8; - mem_txn_addr[num_mem_txn++]=new_addr+12; - } - else if(wmma_layout==COL){ - } - } - else{ - printf("wrong vp_load type\n");; - abort(); - } - printf("\n"); - - //generate timing memory request - inst.space = space; - inst.set_addr(thrd, (new_addr_type *)mem_txn_addr , num_mem_txn); - inst.data_size = 4; // 4 byte transaction - assert( inst.memory_op == insn_memory_op ); - printf("\nVPLOAD_THREAD%d:",thrd); - for(int lll=0;lll<num_mem_txn;lll++) - { - printf("%x ",mem_txn_addr[lll]); - } - printf("\n"); - - int num_reg; - if(g_debug_instruction){ - printf("\nvp_ld:thread%d= ",thrd); - if((wmma_type==LOAD_A)||(wmma_type==LOAD_C)){ - num_reg=8; - } - else if(wmma_type==LOAD_B4){ - num_reg=1; - } - else if(wmma_type==LOAD_B8){ - num_reg=2; - } - else if(wmma_type==LOAD_B16){ - num_reg=4; - } - for(i=0;i<num_reg;i++){ - printf("%x ",data[i].s32); - } - printf("\n"); - } - - if((wmma_type==LOAD_A)||(wmma_type==LOAD_C)){ - thread->set_wmma_vector_operand_values(dst,data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7]); - } - else if(wmma_type==LOAD_B4){ - thread->set_vector_operand_values(dst,data[0],data[0],data[0],data[0]); - } - else if(wmma_type==LOAD_B8){ - thread->set_vector_operand_values(dst,data[0],data[1],data[1],data[1]); - } - else if (wmma_type==LOAD_B16){ - thread->set_vector_operand_values(dst,data[0],data[1],data[2],data[3]); - } - else - abort(); - - - - if(g_debug_instruction){ - for(int i=0;i<num_reg;i++) - printf("vp_ld:data[%i].s64=%x\n",i,data[i].u64); - } - - - //thread->m_last_effective_address = addr; - //thread->m_last_memory_space = space; - } - - - -} void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t &inst ) { diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 73f6161..e6f957a 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -55,9 +55,6 @@ OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9) OP_W_DEF(MMA_OP,mma_impl,"mma",1,1) OP_W_DEF(MMA_LD_OP,mma_ld_impl,"mma_load",1,5) OP_W_DEF(MMA_ST_OP,mma_st_impl,"mma_store",0,5) -OP_W_DEF(VP_MMA_OP,vp_mma_impl,"vp_mma",1,1) -OP_W_DEF(VP_LD_OP,vp_ld_impl,"vp_load",1,5) -OP_W_DEF(VP_ST_OP,vp_st_impl,"vp_store",0,5) OP_DEF(CALL_OP,call_impl,"call",1,3) OP_DEF(CALLP_OP,callp_impl,"callp",1,3) OP_DEF(CLZ_OP,clz_impl,"clz",1,1) diff --git a/src/cuda-sim/opcodes.h b/src/cuda-sim/opcodes.h index ad8d8f1..b91d92f 100644 --- a/src/cuda-sim/opcodes.h +++ b/src/cuda-sim/opcodes.h @@ -63,16 +63,9 @@ enum special_regs { enum wmma_type{ LOAD_A, LOAD_B, - LOAD_B4,//vp - LOAD_B8,//vp - LOAD_B16,//vp LOAD_C, STORE_D, MMA, - VP_MMA, - VP_MMA4, - VP_MMA8, - VP_MMA16, ROW, COL, M16N16K16 diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 9c78e9f..ab640d7 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -36,7 +36,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "ptx.tab.h" #include <string.h> -char linebuf[1024]; +char linebuf[4096]; unsigned col = 0; #define TC col+=strlen(ptx_text); #define CHECK_UNSIGNED \ @@ -72,9 +72,6 @@ brkpt TC; ptx_lval.int_value = BRKPT_OP; return OPCODE; wmma TC; ptx_lval.int_value = MMA_OP; return OPCODE; wmma\.load TC; ptx_lval.int_value = MMA_LD_OP; return OPCODE; wmma\.store TC; ptx_lval.int_value = MMA_ST_OP; return OPCODE; -vp\.load TC; ptx_lval.int_value=VP_LD_OP; return OPCODE; -vp\.store TC; ptx_lval.int_value=VP_ST_OP; return OPCODE; -vp TC; ptx_lval.int_value=VP_MMA_OP; return OPCODE; call TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode callp TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE; @@ -165,12 +162,6 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.c\.sync TC; ptx_lval.int_value = LOAD_C; return WMMA_DIRECTIVE; \.d\.sync TC; ptx_lval.int_value = STORE_D; return WMMA_DIRECTIVE; \.mma\.sync TC;ptx_lval.int_value=MMA; return WMMA_DIRECTIVE; -\.mma4\.sync TC;ptx_lval.int_value=VP_MMA4; return WMMA_DIRECTIVE; -\.mma8\.sync TC;ptx_lval.int_value=VP_MMA8; return WMMA_DIRECTIVE; -\.mma16\.sync TC;ptx_lval.int_value=VP_MMA16; return WMMA_DIRECTIVE; -\.b4\.sync TC; ptx_lval.int_value=LOAD_B4; return WMMA_DIRECTIVE; -\.b8\.sync TC; ptx_lval.int_value=LOAD_B8; return WMMA_DIRECTIVE; -\.b16\.sync TC; ptx_lval.int_value=LOAD_B16; return WMMA_DIRECTIVE; \.row TC; ptx_lval.int_value = ROW; return LAYOUT; \.col TC; ptx_lval.int_value = COL; return LAYOUT; @@ -415,7 +406,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; "//"[^\n]* TC; // eat single -\n.* col=0; strncpy(linebuf, yytext + 1, 1024); yyless( 1 ); +\n.* col=0; strncpy(linebuf, yytext + 1, sizeof(linebuf)); yyless( 1 ); " " TC; "\t" TC; diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 54ac2bc..8b901a3 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -279,6 +279,7 @@ ptr_spec: /*empty*/ ptr_space_spec: GLOBAL_DIRECTIVE { add_ptr_spec(global_space); } | LOCAL_DIRECTIVE { add_ptr_spec(local_space); } | SHARED_DIRECTIVE { add_ptr_spec(shared_space); } + | CONST_DIRECTIVE { add_ptr_spec(global_space); } ptr_align_spec: ALIGN_DIRECTIVE INT_OPERAND @@ -340,6 +341,7 @@ var_spec_list: var_spec var_spec: space_spec | type_spec | align_spec + | VISIBLE_DIRECTIVE | EXTERN_DIRECTIVE { add_extern_spec(); } | WEAK_DIRECTIVE ; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 9800e1e..d12c741 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1089,15 +1089,9 @@ ptx_instruction::ptx_instruction( int opcode, case SYNC_OPTION: case LOAD_A: case LOAD_B: - case LOAD_B4: - case LOAD_B8: - case LOAD_B16: case LOAD_C: case STORE_D: case MMA: - case VP_MMA4: - case VP_MMA8: - case VP_MMA16: m_wmma_type=last_ptx_inst_option; break; case ROW: diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index e025013..0767379 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -105,7 +105,7 @@ private: int m_is_function; bool m_is_non_arch_reg; - friend class type_info_key_compare; + friend struct type_info_key_compare; }; class symbol_table; @@ -1093,7 +1093,7 @@ public: int membar_level() const { return m_membar_level; } bool has_memory_read() const { - if( m_opcode == LD_OP || m_opcode == LDU_OP || m_opcode == TEX_OP|| m_opcode==MMA_LD_OP || m_opcode==VP_LD_OP) + if( m_opcode == LD_OP || m_opcode == LDU_OP || m_opcode == TEX_OP|| m_opcode==MMA_LD_OP ) return true; // Check PTXPlus operand type below // Source operands are memory operands @@ -1105,7 +1105,7 @@ public: return false; } bool has_memory_write() const { - if( m_opcode == ST_OP || m_opcode==MMA_ST_OP || m_opcode==VP_ST_OP ) return true; + if( m_opcode == ST_OP || m_opcode==MMA_ST_OP ) return true; // Check PTXPlus operand type below // Destination operand is a memory operand ptx_instruction::const_iterator op=op_iter_begin(); diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 6c1b595..11d9013 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -54,6 +54,7 @@ extern int ptxinfo_debug; extern FILE *ptxinfo_in; static bool g_save_embedded_ptx; +static int g_occupancy_sm_number; bool g_keep_intermediate_files; bool m_ptx_save_converted_ptxplus; @@ -71,6 +72,10 @@ void ptx_reg_options(option_parser_t opp) &m_ptx_save_converted_ptxplus, "Saved converted ptxplus to a file", "0"); + option_parser_register(opp, "-gpgpu_occupancy_sm_number", OPT_INT32, &g_occupancy_sm_number, + "The SM number to pass to ptxas when getting register usage for computing GPU occupancy. " + "This parameter is required in the config.", + "0"); } void print_ptx_file( const char *p, unsigned source_num, const char *filename ) @@ -120,7 +125,7 @@ char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptxfilenam fflush(stdout); printf("GPGPU-Sim PTX: calling cuobjdump_to_ptxplus\ncommandline: %s\n", commandline); result = system(commandline); - if(result){printf("GPGPU-Sim PTX: ERROR ** could not execute %s\n", commandline); exit(1);} + if(result){fprintf(stderr, "GPGPU-Sim PTX: ERROR ** could not execute %s\n", commandline); exit(1);} // Get ptxplus from file @@ -142,7 +147,7 @@ char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptxfilenam printf("GPGPU-Sim PTX: removing temporary files using \"%s\"\n", rm_commandline); int rm_result = system(rm_commandline); if( rm_result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while removing temporary files %d\n", rm_result); + fprintf(stderr, "GPGPU-Sim PTX: ERROR ** while removing temporary files %d\n", rm_result); exit(1); } } @@ -193,7 +198,7 @@ void fix_duplicate_errors(char fname2[1024]) { printf("Running: %s\n", commandline); int result = system(commandline); if (result != 0) { - printf("GPGPU-Sim PTX: ERROR ** while changing filename from %s to %s", fname2, tempfile); + fprintf(stderr, "GPGPU-Sim PTX: ERROR ** while changing filename from %s to %s", fname2, tempfile); exit(1); } @@ -282,12 +287,12 @@ void fix_duplicate_errors(char fname2[1024]) { printf("Running: %s\n", commandline); result = system(commandline); if (result != 0) { - printf("GPGPU-Sim PTX: ERROR ** while deleting %s", tempfile); + fprintf(stderr, "GPGPU-Sim PTX: ERROR ** while deleting %s", tempfile); exit(1); } } -void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version ) +void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num ) { char fname[1024]; snprintf(fname,1024,"_ptx_XXXXXX"); @@ -308,9 +313,9 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num printf("Running: %s\n", commandline2); int result = system(commandline2); if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); - printf(" Ensure you have write access to simulation directory\n"); - printf(" and have \'cat\' and \'sed\' in your path.\n"); + fprintf(stderr, "GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); + fprintf(stderr, " Ensure you have write access to simulation directory\n"); + fprintf(stderr, " and have \'cat\' and \'sed\' in your path.\n"); exit(1); } @@ -321,15 +326,20 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num extra_flags[0]=0; #if CUDART_VERSION >= 3000 - if (sm_version == 0) sm_version = 20; + if ( g_occupancy_sm_number == 0 ) { + fprintf( stderr, "gpgpusim.config must specify the sm version for the GPU that you use to compute occupancy \"-gpgpu_occupancy_sm_number XX\".\n" + "The register file size is specifically tied to the sm version used to querry ptxas for register usage.\n" + "A register size/SM mismatch may result in occupancy differences." ); + exit(1); + } extern bool g_cdp_enabled; if(!g_cdp_enabled) - snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); + snprintf(extra_flags,1024,"--gpu-name=sm_%u", g_occupancy_sm_number); else - snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version); + snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",g_occupancy_sm_number); #endif - snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", + snprintf(commandline,1024,"$PTXAS_CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", extra_flags, fname2, tempfile_ptxinfo); printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); result = system(commandline); @@ -347,8 +357,8 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num result = system(commandline); } if (result != 0) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); - printf(" Ensure ptxas is in your path.\n"); + fprintf(stderr, "GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); + fprintf(stderr, " Ensure ptxas is in your path.\n"); exit(1); } } @@ -362,7 +372,7 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num printf("GPGPU-Sim PTX: removing ptxinfo using \"%s\"\n", commandline); result = system(commandline); if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (c) %d\n", result); + fprintf(stderr, "GPGPU-Sim PTX: ERROR ** while loading PTX (c) %d\n", result); exit(1); } } diff --git a/src/cuda-sim/ptx_loader.h b/src/cuda-sim/ptx_loader.h index d3d0c92..cb02eda 100644 --- a/src/cuda-sim/ptx_loader.h +++ b/src/cuda-sim/ptx_loader.h @@ -32,7 +32,7 @@ extern bool g_override_embedded_ptx; class symbol_table *gpgpu_ptx_sim_load_ptx_from_string( const char *p, unsigned source_num ); -void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version=20 ); +void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num ); char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptx_str, const std::string sass_str, const std::string elf_str); bool keep_intermediate_files(); diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index eb81961..d5324d0 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -267,7 +267,7 @@ void parse_assert_impl( int test_value, const char *file, unsigned line, const c parse_error_impl(file,line, msg); } -extern char linebuf[1024]; +extern char linebuf[4096]; void set_return() @@ -436,7 +436,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_shared_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (shared memory space)\n", + printf("from 0x%llx to 0x%llx (shared memory space)\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); @@ -467,7 +467,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_global_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (global memory space) %u\n", + printf("from 0x%llx to 0x%llx (global memory space) %u\n", addr+addr_pad, addr+addr_pad + num_bits/8, g_const_alloc++); @@ -488,7 +488,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_global_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (global memory space)\n", + printf("from 0x%llx to 0x%llx (global memory space)\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); @@ -505,7 +505,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_local_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (local memory space)\n", + printf("from 0x%llx to 0x%llx (local memory space)\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); @@ -518,7 +518,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_local_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx\n", + printf("from 0x%llx to 0x%llx\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index ea87e59..0a6e8eb 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -28,7 +28,7 @@ #define ptx_sim_h_INCLUDED #include <stdlib.h> -#include "half.hpp" +#include "half.h" #include "../abstract_hardware_model.h" #include "../tr1_hash_map.h" diff --git a/src/debug.cc b/src/debug.cc index cfd7bb0..ae15760 100644 --- a/src/debug.cc +++ b/src/debug.cc @@ -222,7 +222,7 @@ void gpgpu_sim::gpgpu_debug() } } -bool thread_at_brkpt( ptx_thread_info *thread, const struct brk_pt &b ) +bool thread_at_brkpt( ptx_thread_info *thread, const class brk_pt &b ) { return b.is_equal(thread->get_location(),thread->get_uid()); } diff --git a/src/debug.h b/src/debug.h index 7c79f1e..1277494 100644 --- a/src/debug.h +++ b/src/debug.h @@ -87,7 +87,7 @@ extern int gpgpu_ptx_instruction_classification ; class ptx_thread_info; class ptx_instruction; -bool thread_at_brkpt( ptx_thread_info *thd_info, const struct brk_pt &b ); +bool thread_at_brkpt( ptx_thread_info *thd_info, const class brk_pt &b ); void hit_watchpoint( unsigned watchpoint_num, ptx_thread_info *thd, const ptx_instruction *pI ); #endif diff --git a/src/gpgpu-sim/Makefile b/src/gpgpu-sim/Makefile index 4f77699..f10a8a4 100644 --- a/src/gpgpu-sim/Makefile +++ b/src/gpgpu-sim/Makefile @@ -48,7 +48,7 @@ ifeq ($(GNUC_CPP0X), 1) endif ifneq ($(DEBUG),1) - OPTFLAGS += -O0 + OPTFLAGS += -O3 else CXXFLAGS += endif diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index a8bff14..15c63e7 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -87,7 +87,7 @@ struct bank_t unsigned int bkgrpindex; }; -struct mem_fetch; +class mem_fetch; class dram_t { @@ -178,7 +178,7 @@ private: unsigned int ave_mrqs_partial; unsigned int bwutil_partial; - struct memory_stats_t *m_stats; + class memory_stats_t *m_stats; class Stats* mrqq_Dist; //memory request queue inside DRAM friend class frfcfs_scheduler; diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 5ea4190..8886398 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -517,18 +517,28 @@ void cache_stats::print_stats(FILE *fout, const char *cache_name) const{ /// the provided name is used. /// The printed format is "<cache_name>[<request_type>][<request_status>] = <stat_value>" /// + std::vector< unsigned > total_access; + total_access.resize(NUM_MEM_ACCESS_TYPE, 0); std::string m_cache_name = cache_name; for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) { for (unsigned status = 0; status < NUM_CACHE_REQUEST_STATUS; ++status) { - if(m_stats[type][status] > 0){ - fprintf(fout, "\t%s[%s][%s] = %u\n", - m_cache_name.c_str(), - mem_access_type_str((enum mem_access_type)type), - cache_request_status_str((enum cache_request_status)status), - m_stats[type][status]); - } + fprintf(fout, "\t%s[%s][%s] = %u\n", + m_cache_name.c_str(), + mem_access_type_str((enum mem_access_type)type), + cache_request_status_str((enum cache_request_status)status), + m_stats[type][status]); + if(status != RESERVATION_FAIL) + total_access[type]+= m_stats[type][status]; } } + for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) { + if(total_access[type] > 0) + fprintf(fout, "\t%s[%s][%s] = %u\n", + m_cache_name.c_str(), + mem_access_type_str((enum mem_access_type)type), + "TOTAL_ACCESS", + total_access[type]); + } } void cache_sub_stats::print_port_stats(FILE *fout, const char *cache_name) const diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index eba6f54..d4b636b 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -32,10 +32,12 @@ #include <stdio.h> #include <stdlib.h> #include <math.h> +#include <signal.h> #include "zlib.h" #include "shader.h" +#include "shader_trace.h" #include "dram.h" #include "mem_fetch.h" @@ -87,6 +89,14 @@ unsigned long long gpu_tot_sim_cycle = 0; // performance counter for stalls due to congestion. unsigned int gpu_stall_dramfull = 0; unsigned int gpu_stall_icnt2sh = 0; +unsigned long long partiton_reqs_in_parallel = 0; +unsigned long long partiton_reqs_in_parallel_total = 0; +unsigned long long partiton_reqs_in_parallel_util = 0; +unsigned long long partiton_reqs_in_parallel_util_total = 0; +unsigned long long gpu_sim_cycle_parition_util = 0; +unsigned long long gpu_tot_sim_cycle_parition_util = 0; +unsigned long long partiton_replys_in_parallel = 0; +unsigned long long partiton_replys_in_parallel_total = 0; /* Clock Domains */ @@ -223,7 +233,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "per-shader L1 data cache config " " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}", "none" ); - option_parser_register(opp, "-gpgpu_cache:dl1PreShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, + option_parser_register(opp, "-gpgpu_cache:dl1PrefShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, "per-shader L1 data cache config " " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}", "none" ); @@ -309,9 +319,6 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_operand_collector_num_units_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_units_tensor_core, "number of collector units (default = 4)", "4"); - option_parser_register(opp, "-gpgpu_operand_collector_num_units_vp_core", OPT_INT32, &gpgpu_operand_collector_num_units_vp_core, - "number of collector units (default = 4)", - "4"); option_parser_register(opp, "-gpgpu_operand_collector_num_units_mem", OPT_INT32, &gpgpu_operand_collector_num_units_mem, "number of collector units (default = 2)", "2"); @@ -327,9 +334,6 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_in_ports_tensor_core, "number of collector unit in ports (default = 1)", "1"); - option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_vp_core", OPT_INT32, &gpgpu_operand_collector_num_in_ports_vp_core, - "number of collector unit in ports (default = 1)", - "1"); option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_mem", OPT_INT32, &gpgpu_operand_collector_num_in_ports_mem, "number of collector unit in ports (default = 1)", "1"); @@ -345,9 +349,6 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_tensor_core", OPT_INT32, &gpgpu_operand_collector_num_out_ports_tensor_core, "number of collector unit in ports (default = 1)", "1"); - option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_vp_core", OPT_INT32, &gpgpu_operand_collector_num_out_ports_vp_core, - "number of collector unit in ports (default = 1)", - "1"); option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_mem", OPT_INT32, &gpgpu_operand_collector_num_out_ports_mem, "number of collector unit in ports (default = 1)", "1"); @@ -368,8 +369,8 @@ void shader_core_config::reg_options(class OptionParser * opp) "1"); option_parser_register(opp, "-gpgpu_pipeline_widths", OPT_CSTR, &pipeline_widths_string, "Pipeline widths " - "ID_OC_SP,ID_OC_SFU,ID_OC_TENSOR_CORE,ID_OC_VP_CORE,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_TENSOR_CORE,OC_EX_TENSOR_CORE,OC_EX_MEM,EX_WB", - "1,1,1,1,1,1,1,1,1,1,1" ); + "ID_OC_SP,ID_OC_SFU,ID_OC_TENSOR_CORE,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_TENSOR_CORE,OC_EX_TENSOR_CORE,OC_EX_MEM,EX_WB", + "1,1,1,1,1,1,1,1,1,1" ); option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32, &gpgpu_num_sp_units, "Number of SP units (default=1)", "1"); @@ -379,9 +380,6 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32, &gpgpu_num_tensor_core_units, "Number of tensor_core units (default=1)", "1"); - option_parser_register(opp, "-gpgpu_num_vp_core_units", OPT_INT32, &gpgpu_num_vp_core_units, - "Number of vp_core units (default=1)", - "1"); option_parser_register(opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units, "Number if ldst units (default=1) WARNING: not hooked up to anything", "1"); @@ -768,6 +766,10 @@ void gpgpu_sim::init() gpu_sim_insn = 0; last_gpu_sim_insn = 0; m_total_cta_launched=0; + partiton_reqs_in_parallel = 0; + partiton_replys_in_parallel = 0; + partiton_reqs_in_parallel_util = 0; + gpu_sim_cycle_parition_util = 0; reinit_clock_domains(); set_param_gpgpu_num_shaders(m_config.num_shader()); @@ -804,8 +806,16 @@ void gpgpu_sim::update_stats() { gpu_tot_sim_cycle += gpu_sim_cycle; gpu_tot_sim_insn += gpu_sim_insn; gpu_tot_issued_cta += m_total_cta_launched; + partiton_reqs_in_parallel_total += partiton_reqs_in_parallel; + partiton_replys_in_parallel_total += partiton_replys_in_parallel; + partiton_reqs_in_parallel_util_total += partiton_reqs_in_parallel_util; + gpu_tot_sim_cycle_parition_util += gpu_sim_cycle_parition_util ; gpu_sim_cycle = 0; + partiton_reqs_in_parallel = 0; + partiton_replys_in_parallel = 0; + partiton_reqs_in_parallel_util = 0; + gpu_sim_cycle_parition_util = 0; gpu_sim_insn = 0; m_total_cta_launched = 0; } @@ -989,6 +999,21 @@ void gpgpu_sim::gpu_print_stat() printf("gpu_stall_dramfull = %d\n", gpu_stall_dramfull); printf("gpu_stall_icnt2sh = %d\n", gpu_stall_icnt2sh ); + printf("partiton_reqs_in_parallel = %lld\n", partiton_reqs_in_parallel); + printf("partiton_reqs_in_parallel_total = %lld\n", partiton_reqs_in_parallel_total ); + printf("partiton_level_parallism = %12.4f\n", (float)partiton_reqs_in_parallel / gpu_sim_cycle); + printf("partiton_level_parallism_total = %12.4f\n", (float)(partiton_reqs_in_parallel+partiton_reqs_in_parallel_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); + printf("partiton_reqs_in_parallel_util = %lld\n", partiton_reqs_in_parallel_util); + printf("partiton_reqs_in_parallel_util_total = %lld\n", partiton_reqs_in_parallel_util_total ); + printf("gpu_sim_cycle_parition_util = %lld\n", gpu_sim_cycle_parition_util); + printf("gpu_tot_sim_cycle_parition_util = %lld\n", gpu_tot_sim_cycle_parition_util ); + printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle_parition_util); + printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_sim_cycle_parition_util+gpu_tot_sim_cycle_parition_util) ); + printf("partiton_replys_in_parallel = %lld\n", partiton_replys_in_parallel); + printf("partiton_replys_in_parallel_total = %lld\n", partiton_replys_in_parallel_total ); + printf("L2_BW = %12.4f GB/Sec\n", ((float)(partiton_replys_in_parallel * 32) / (gpu_sim_cycle * m_config.icnt_period)) / 1000000000); + printf("L2_BW_total = %12.4f GB/Sec\n", ((float)((partiton_replys_in_parallel+partiton_replys_in_parallel_total) * 32) / ((gpu_tot_sim_cycle+gpu_sim_cycle) * m_config.icnt_period)) / 1000000000 ); + time_t curr_time; time(&curr_time); unsigned long long elapsed_time = MAX( curr_time - g_simulation_starttime, 1 ); @@ -1202,8 +1227,8 @@ bool shader_core_ctx::occupy_shader_resource_1block(kernel_info_t & k, bool occu m_occupied_regs += (padded_cta_size * ((kernel_info->regs+3)&~3)); m_occupied_ctas++; - printf("GPGPU-Sim uArch: Shader %d occupied %d threads, %d shared mem, %d registers, %d ctas\n", - m_sid, m_occupied_n_threads, m_occupied_shmem, m_occupied_regs, m_occupied_ctas); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: Occupied %d threads, %d shared mem, %d registers, %d ctas\n", + m_occupied_n_threads, m_occupied_shmem, m_occupied_regs, m_occupied_ctas); } return true; @@ -1328,8 +1353,8 @@ void shader_core_ctx::issue_block2core( kernel_info_t &kernel ) m_n_active_cta++; shader_CTA_count_log(m_sid, 1); - printf("GPGPU-Sim uArch: core:%3d, cta:%2u, start_tid:%4u, end_tid:%4u, initialized @(%lld,%lld)\n", - m_sid, free_cta_hw_id, start_thread, end_thread, gpu_sim_cycle, gpu_tot_sim_cycle ); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: cta:%2u, start_tid:%4u, end_tid:%4u, initialized @(%lld,%lld)\n", + free_cta_hw_id, start_thread, end_thread, gpu_sim_cycle, gpu_tot_sim_cycle ); } @@ -1393,6 +1418,7 @@ void gpgpu_sim::cycle() for (unsigned i=0;i<m_shader_config->n_simt_clusters;i++) m_cluster[i]->icnt_cycle(); } + unsigned partiton_replys_in_parallel_per_cycle = 0; if (clock_mask & ICNT) { // pop from memory controller to interconnect for (unsigned i=0;i<m_memory_config->m_n_mem_sub_partition;i++) { @@ -1405,6 +1431,7 @@ void gpgpu_sim::cycle() mf->set_status(IN_ICNT_TO_SHADER,gpu_sim_cycle+gpu_tot_sim_cycle); ::icnt_push( m_shader_config->mem2device(i), mf->get_tpc(), mf, response_size ); m_memory_sub_partition[i]->pop(); + partiton_replys_in_parallel_per_cycle++; } else { gpu_stall_icnt2sh++; } @@ -1413,6 +1440,7 @@ void gpgpu_sim::cycle() } } } + partiton_replys_in_parallel += partiton_replys_in_parallel_per_cycle; if (clock_mask & DRAM) { for (unsigned i=0;i<m_memory_config->m_n_mem;i++){ @@ -1425,6 +1453,7 @@ void gpgpu_sim::cycle() } // L2 operations follow L2 clock domain + unsigned partiton_reqs_in_parallel_per_cycle = 0; if (clock_mask & L2) { m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].clear(); for (unsigned i=0;i<m_memory_config->m_n_mem_sub_partition;i++) { @@ -1435,11 +1464,17 @@ void gpgpu_sim::cycle() } else { mem_fetch* mf = (mem_fetch*) icnt_pop( m_shader_config->mem2device(i) ); m_memory_sub_partition[i]->push( mf, gpu_sim_cycle + gpu_tot_sim_cycle ); + partiton_reqs_in_parallel_per_cycle++; } m_memory_sub_partition[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle); m_memory_sub_partition[i]->accumulate_L2cache_stats(m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX]); } } + partiton_reqs_in_parallel += partiton_reqs_in_parallel_per_cycle; + if(partiton_reqs_in_parallel_per_cycle > 0){ + partiton_reqs_in_parallel_util += partiton_reqs_in_parallel_per_cycle; + gpu_sim_cycle_parition_util++; + } if (clock_mask & ICNT) { icnt_transfer(); @@ -1467,9 +1502,8 @@ void gpgpu_sim::cycle() if( g_single_step && ((gpu_sim_cycle+gpu_tot_sim_cycle) >= g_single_step) ) { - asm("int $03"); + raise(SIGTRAP); // Debug breakpoint } - printf("gpu_sim_cycle=%d\n",gpu_sim_cycle); gpu_sim_cycle++; if( g_interactive_debugger_enabled ) @@ -1528,7 +1562,8 @@ void gpgpu_sim::cycle() hrs = elapsed_time/3600 - 24*days; minutes = elapsed_time/60 - 60*(hrs + 24*days); sec = elapsed_time - 60*(minutes + 60*(hrs + 24*days)); - printf("GPGPU-Sim uArch: cycles simulated: %lld inst.: %lld (ipc=%4.1f) sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s", + + DPRINTF(LIVENESS, "GPGPU-Sim uArch: cycles simulated: %lld inst.: %lld (ipc=%4.1f) sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s", gpu_tot_sim_cycle + gpu_sim_cycle, gpu_tot_sim_insn + gpu_sim_insn, (double)gpu_sim_insn/(double)gpu_sim_cycle, (unsigned)((gpu_tot_sim_insn+gpu_sim_insn) / elapsed_time), diff --git a/src/gpgpu-sim/mem_fetch.cc b/src/gpgpu-sim/mem_fetch.cc index 580c051..729636d 100644 --- a/src/gpgpu-sim/mem_fetch.cc +++ b/src/gpgpu-sim/mem_fetch.cc @@ -39,7 +39,7 @@ mem_fetch::mem_fetch( const mem_access_t &access, unsigned wid, unsigned sid, unsigned tpc, - const class memory_config *config ) + const struct memory_config *config ) { m_request_uid = sm_next_mf_request_uid++; m_access = access; diff --git a/src/gpgpu-sim/mem_fetch.h b/src/gpgpu-sim/mem_fetch.h index c89edbb..de98748 100644 --- a/src/gpgpu-sim/mem_fetch.h +++ b/src/gpgpu-sim/mem_fetch.h @@ -55,7 +55,7 @@ public: unsigned wid, unsigned sid, unsigned tpc, - const class memory_config *config ); + const struct memory_config *config ); ~mem_fetch(); void set_status( enum mem_fetch_status status, unsigned long long cycle ); @@ -141,7 +141,7 @@ private: static unsigned sm_next_mf_request_uid; - const class memory_config *m_mem_config; + const struct memory_config *m_mem_config; unsigned icnt_flit_size; }; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index eeb59bb..23f255d 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -149,7 +149,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_TENSOR_CORE], - &m_pipeline_reg[ID_OC_VP_CORE], &m_pipeline_reg[ID_OC_MEM], i ) @@ -165,7 +164,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_TENSOR_CORE], - &m_pipeline_reg[ID_OC_VP_CORE], &m_pipeline_reg[ID_OC_MEM], i, config->gpgpu_scheduler_string @@ -182,7 +180,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_TENSOR_CORE], - &m_pipeline_reg[ID_OC_VP_CORE], &m_pipeline_reg[ID_OC_MEM], i ) @@ -198,7 +195,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, &m_pipeline_reg[ID_OC_SP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_TENSOR_CORE], - &m_pipeline_reg[ID_OC_VP_CORE], &m_pipeline_reg[ID_OC_MEM], i, config->gpgpu_scheduler_string @@ -219,11 +215,10 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, } //op collector configuration - enum { SP_CUS, SFU_CUS, TENSOR_CORE_CUS, VP_CORE_CUS, MEM_CUS, GEN_CUS }; + enum { SP_CUS, SFU_CUS, TENSOR_CORE_CUS, MEM_CUS, GEN_CUS }; m_operand_collector.add_cu_set(SP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_sp); m_operand_collector.add_cu_set(SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu, m_config->gpgpu_operand_collector_num_out_ports_sfu); m_operand_collector.add_cu_set(TENSOR_CORE_CUS, config->gpgpu_operand_collector_num_units_tensor_core, config->gpgpu_operand_collector_num_out_ports_tensor_core); - m_operand_collector.add_cu_set(VP_CORE_CUS, config->gpgpu_operand_collector_num_units_vp_core, config->gpgpu_operand_collector_num_out_ports_vp_core); m_operand_collector.add_cu_set(MEM_CUS, m_config->gpgpu_operand_collector_num_units_mem, m_config->gpgpu_operand_collector_num_out_ports_mem); m_operand_collector.add_cu_set(GEN_CUS, m_config->gpgpu_operand_collector_num_units_gen, m_config->gpgpu_operand_collector_num_out_ports_gen); @@ -257,15 +252,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, in_ports.clear(),out_ports.clear(),cu_sets.clear(); } - for (unsigned i = 0; i < config->gpgpu_operand_collector_num_in_ports_vp_core; i++) { - in_ports.push_back(&m_pipeline_reg[ID_OC_VP_CORE]); - out_ports.push_back(&m_pipeline_reg[OC_EX_VP_CORE]); - cu_sets.push_back((unsigned)VP_CORE_CUS); - cu_sets.push_back((unsigned)GEN_CUS); - m_operand_collector.add_port(in_ports,out_ports,cu_sets); - in_ports.clear(),out_ports.clear(),cu_sets.clear(); - } - for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_mem; i++) { in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]); out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]); @@ -280,12 +266,10 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, in_ports.push_back(&m_pipeline_reg[ID_OC_SP]); in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]); in_ports.push_back(&m_pipeline_reg[ID_OC_TENSOR_CORE]); - in_ports.push_back(&m_pipeline_reg[ID_OC_VP_CORE]); in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]); out_ports.push_back(&m_pipeline_reg[OC_EX_SP]); out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]); out_ports.push_back(&m_pipeline_reg[OC_EX_TENSOR_CORE]); - out_ports.push_back(&m_pipeline_reg[OC_EX_VP_CORE]); out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]); cu_sets.push_back((unsigned)GEN_CUS); m_operand_collector.add_port(in_ports,out_ports,cu_sets); @@ -295,7 +279,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_operand_collector.init( m_config->gpgpu_num_reg_banks, this ); // execute - m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_sfu_units + config->gpgpu_num_tensor_core_units + config->gpgpu_num_vp_core_units + 1; // sp_unit, sfu, ldst_unit + m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_sfu_units + config->gpgpu_num_tensor_core_units + 1; // sp_unit, sfu, ldst_unit //m_dispatch_port = new enum pipeline_stage_name_t[ m_num_function_units ]; //m_issue_port = new enum pipeline_stage_name_t[ m_num_function_units ]; @@ -319,12 +303,6 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_issue_port.push_back(OC_EX_TENSOR_CORE); } - for (int k = 0; k < config->gpgpu_num_vp_core_units; k++) { - m_fu.push_back(new vp_core( &m_pipeline_reg[EX_WB], m_config, this )); - m_dispatch_port.push_back(ID_OC_VP_CORE); - m_issue_port.push_back(OC_EX_VP_CORE); - } - m_ldst_unit = new ldst_unit( m_icnt, m_mem_fetch_allocator, this, &m_operand_collector, m_scoreboard, config, mem_config, stats, shader_id, tpc_id ); m_fu.push_back(m_ldst_unit); m_dispatch_port.push_back(ID_OC_MEM); @@ -923,7 +901,7 @@ void scheduler_unit::cycle() ready_inst = true; const active_mask_t &active_mask = m_simt_stack[warp_id]->get_active_mask(); assert( warp(warp_id).inst_in_pipeline() ); - if ( (pI->op == LOAD_OP)||(pI->op ==TENSOR_CORE_LOAD_OP)||(pI->op ==VP_LOAD_OP)|| (pI->op == STORE_OP)|| (pI->op==TENSOR_CORE_STORE_OP) ||(pI->op==VP_STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) { + if ( (pI->op == LOAD_OP)||(pI->op ==TENSOR_CORE_LOAD_OP)|| (pI->op == STORE_OP)|| (pI->op==TENSOR_CORE_STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) { if( m_mem_out->has_free() ) { m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id); issued++; @@ -934,8 +912,7 @@ void scheduler_unit::cycle() bool sp_pipe_avail = m_sp_out->has_free(); bool sfu_pipe_avail = m_sfu_out->has_free(); bool tensor_core_pipe_avail = m_tensor_core_out->has_free(); - bool vp_core_pipe_avail = m_vp_core_out->has_free(); - if( sp_pipe_avail && (pI->op != SFU_OP) && (pI->op != TENSOR_CORE_OP) && (pI->op !=VP_CORE_OP)) { + if( sp_pipe_avail && (pI->op != SFU_OP) && (pI->op != TENSOR_CORE_OP) ) { //Jin: special for CDP api if(pI->m_is_cdp && !warp(warp_id).m_cdp_dummy) { @@ -976,14 +953,7 @@ void scheduler_unit::cycle() warp_inst_issued = true; } } - else if ( (pI->op == VP_CORE_OP) ) { - if( vp_core_pipe_avail ) { - m_shader->issue_warp(*m_vp_core_out,pI,active_mask,warp_id); - issued++; - issued_inst=true; - warp_inst_issued = true; - } - } } + } } else { SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) fails scoreboard\n", (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id() ); @@ -1149,11 +1119,10 @@ swl_scheduler::swl_scheduler ( shader_core_stats* stats, shader_core_ctx* shader register_set* sp_out, register_set* sfu_out, register_set* tensor_core_out, - register_set* vp_core_out, register_set* mem_out, int id, char* config_string ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, vp_core_out, mem_out, id ) + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ) { unsigned m_prioritization_readin; int ret = sscanf( config_string, @@ -1321,16 +1290,6 @@ void ldst_unit::get_L1T_sub_stats(struct cache_sub_stats &css) const{ void shader_core_ctx::warp_inst_complete(const warp_inst_t &inst) { - //#if 0 - //printf("[warp_inst_complete] uid=%u core=%u warp=%u pc=%#x @ time=%llu issued@%llu\n", - //const ptx_instruction *pI = m_func_info->get_instruction(inst.pc); - printf("[warp_inst_complete] uid=%u core=%u warp=%u pc=%d @ time=%llu \n", - inst.get_uid(), m_sid, inst.warp_id(), inst.pc, gpu_sim_cycle); - //printf("^instruction:%s",(pI->m_source).c_str()); - //inst.get_uid(), m_sid, inst.warp_id(), inst.pc, gpu_tot_sim_cycle + gpu_sim_cycle, inst.get_issue_cycle()); - //#endif - - if(inst.op_pipe==SP__OP) m_stats->m_num_sp_committed[m_sid]++; else if(inst.op_pipe==SFU__OP) @@ -1588,13 +1547,6 @@ tensor_core:: tensor_core( register_set* result_port, const shader_core_config m_name = "TENSOR_CORE"; } -vp_core:: vp_core( register_set* result_port, const shader_core_config *config,shader_core_ctx *core ) - : pipelined_simd_unit(result_port,config,config->max_vp_core_latency,core) -{ - m_name = "VP_CORE"; -} - - void sfu::issue( register_set& source_reg ) { warp_inst_t** ready_reg = source_reg.get_ready(); @@ -1615,16 +1567,6 @@ void tensor_core::issue( register_set& source_reg ) pipelined_simd_unit::issue(source_reg); } -void vp_core::issue( register_set& source_reg ) -{ - warp_inst_t** ready_reg = source_reg.get_ready(); - //m_core->incexecstat((*ready_reg)); - - (*ready_reg)->op_pipe= VP_CORE__OP; - m_core->incsfu_stat(m_core->get_config()->warp_size,(*ready_reg)->latency); - pipelined_simd_unit::issue(source_reg); -} - void ldst_unit::active_lanes_in_pipeline(){ unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline(); @@ -1655,13 +1597,6 @@ void tensor_core::active_lanes_in_pipeline(){ m_core->incfumemactivelanes_stat(active_count); } -void vp_core::active_lanes_in_pipeline(){ - unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline(); - assert(active_count<=m_core->get_config()->warp_size); - m_core->incsfuactivelanes_stat(active_count); - m_core->incfuactivelanes_stat(active_count); - m_core->incfumemactivelanes_stat(active_count); -} sp_unit::sp_unit( register_set* result_port, const shader_core_config *config,shader_core_ctx *core) : pipelined_simd_unit(result_port,config,config->max_sp_latency,core) @@ -2093,12 +2028,12 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num, kernel_info_t m_barriers.deallocate_barrier(cta_num); shader_CTA_count_unlog(m_sid, 1); - printf("GPGPU-Sim uArch: Shader %d finished CTA #%d (%lld,%lld), %u CTAs running\n", m_sid, cta_num, gpu_sim_cycle, gpu_tot_sim_cycle, - m_n_active_cta ); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: Finished CTA #%d (%lld,%lld), %u CTAs running\n", + cta_num, gpu_sim_cycle, gpu_tot_sim_cycle, m_n_active_cta); if( m_n_active_cta == 0 ) { - printf("GPGPU-Sim uArch: Shader %u empty (last released kernel %u \'%s\').\n", m_sid, kernel->get_uid(), - kernel->name().c_str() ); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: Empty (last released kernel %u \'%s\').\n", + kernel->get_uid(), kernel->name().c_str()); fflush(stdout); //Shader can only be empty when no more cta are dispatched @@ -2113,8 +2048,10 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num, kernel_info_t kernel->dec_running(); if( !m_gpu->kernel_more_cta_left(kernel) ) { if( !kernel->running() ) { - printf("GPGPU-Sim uArch: GPU detected kernel %u \'%s\' finished on shader %u.\n", kernel->get_uid(), - kernel->name().c_str(), m_sid ); + SHADER_DPRINTF(LIVENESS, + "GPGPU-Sim uArch: GPU detected kernel %u \'%s\' finished on shader %u.\n", kernel->get_uid(), + kernel->name().c_str(), m_sid); + if(m_kernel == kernel) m_kernel = NULL; m_gpu->set_kernel_done( kernel ); diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 99abb63..8ad6514 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -286,7 +286,7 @@ typedef std::bitset<WARP_PER_CTA_MAX> warp_set_t; int register_bank(int regnum, int wid, unsigned num_banks, unsigned bank_warp_shift); class shader_core_ctx; -class shader_core_config; +struct shader_core_config; class shader_core_stats; enum scheduler_prioritization_type @@ -319,12 +319,11 @@ public: register_set* sp_out, register_set* sfu_out, register_set* tensor_core_out, - register_set* vp_core_out, register_set* mem_out, int id) : m_supervised_warps(), m_stats(stats), m_shader(shader), m_scoreboard(scoreboard), m_simt_stack(simt), /*m_pipeline_reg(pipe_regs),*/ m_warp(warp), - m_sp_out(sp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_vp_core_out(vp_core_out),m_mem_out(mem_out), m_id(id){} + m_sp_out(sp_out),m_sfu_out(sfu_out),m_tensor_core_out(tensor_core_out),m_mem_out(mem_out), m_id(id){} virtual ~scheduler_unit(){} virtual void add_supervised_warp_id(int i) { m_supervised_warps.push_back(&warp(i)); @@ -398,7 +397,6 @@ protected: register_set* m_sp_out; register_set* m_sfu_out; register_set* m_tensor_core_out; - register_set* m_vp_core_out; register_set* m_mem_out; int m_id; @@ -412,10 +410,9 @@ public: register_set* sp_out, register_set* sfu_out, register_set* tensor_core_out, - register_set* vp_core_out, register_set* mem_out, int id ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, vp_core_out, mem_out, id ){} + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ){} virtual ~lrr_scheduler () {} virtual void order_warps (); virtual void done_adding_supervised_warps() { @@ -431,10 +428,9 @@ public: register_set* sp_out, register_set* sfu_out, register_set* tensor_core_out, - register_set* vp_core_out, register_set* mem_out, int id ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out,vp_core_out, mem_out, id ){} + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ){} virtual ~gto_scheduler () {} virtual void order_warps (); virtual void done_adding_supervised_warps() { @@ -452,11 +448,10 @@ public: register_set* sp_out, register_set* sfu_out, register_set* tensor_core_out, - register_set* vp_core_out, register_set* mem_out, int id, char* config_str ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, vp_core_out, mem_out, id ), + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, tensor_core_out, mem_out, id ), m_pending_warps() { unsigned inner_level_readin; @@ -504,7 +499,6 @@ public: register_set* sp_out, register_set* sfu_out, register_set* tensor_core_out, - register_set* vp_core_out, register_set* mem_out, int id, char* config_string ); @@ -979,7 +973,7 @@ struct ifetch_buffer_t { unsigned m_warp_id; }; -class shader_core_config; +struct shader_core_config; class simd_function_unit { public: @@ -1089,22 +1083,6 @@ public: virtual void active_lanes_in_pipeline(); virtual void issue( register_set& source_reg ); }; -class vp_core : public pipelined_simd_unit -{ -public: - vp_core( register_set* result_port, const shader_core_config *config, shader_core_ctx *core ); - virtual bool can_issue( const warp_inst_t &inst ) const - { - switch(inst.op) { - case VP_CORE_OP: break; - default: return false; - } - return pipelined_simd_unit::can_issue(inst); - } - virtual void active_lanes_in_pipeline(); - virtual void issue( register_set& source_reg ); -}; - class sp_unit : public pipelined_simd_unit @@ -1117,10 +1095,8 @@ public: case SFU_OP: return false; case LOAD_OP: return false; case TENSOR_CORE_LOAD_OP: return false; - case VP_LOAD_OP: return false; case STORE_OP: return false; case TENSOR_CORE_STORE_OP: return false; - case VP_STORE_OP: return false; case MEMORY_BARRIER_OP: return false; default: break; } @@ -1163,10 +1139,8 @@ public: switch(inst.op) { case LOAD_OP: break; case TENSOR_CORE_LOAD_OP: break; - case VP_LOAD_OP: break; case STORE_OP: break; case TENSOR_CORE_STORE_OP: break; - case VP_STORE_OP: break; case MEMORY_BARRIER_OP: break; default: return false; } @@ -1255,12 +1229,10 @@ enum pipeline_stage_name_t { ID_OC_SP=0, ID_OC_SFU, ID_OC_TENSOR_CORE, - ID_OC_VP_CORE, ID_OC_MEM, OC_EX_SP, OC_EX_SFU, OC_EX_TENSOR_CORE, - OC_EX_VP_CORE, OC_EX_MEM, EX_WB, N_PIPELINE_STAGES @@ -1270,12 +1242,10 @@ const char* const pipeline_stage_name_decode[] = { "ID_OC_SP", "ID_OC_SFU", "ID_OC_TENSOR_CORE", - "ID_OC_VP_CORE", "ID_OC_MEM", "OC_EX_SP", "OC_EX_SFU", "OC_EX_TENSOR_CORE", - "OC_EX_VP_CORE", "OC_EX_MEM", "EX_WB", "N_PIPELINE_STAGES" @@ -1328,12 +1298,6 @@ struct shader_core_config : public core_config gpgpu_operand_collector_num_in_ports_tensor_core=8; gpgpu_operand_collector_num_out_ports_tensor_core=8; - max_vp_core_latency = 512; - gpgpu_num_vp_core_units=8; - gpgpu_operand_collector_num_units_vp_core=24; - gpgpu_operand_collector_num_in_ports_vp_core=8; - gpgpu_operand_collector_num_out_ports_vp_core=8; - m_L1I_config.init(m_L1I_config.m_config_string,FuncCachePreferNone); m_L1T_config.init(m_L1T_config.m_config_string,FuncCachePreferNone); m_L1C_config.init(m_L1C_config.m_config_string,FuncCachePreferNone); @@ -1381,28 +1345,24 @@ struct shader_core_config : public core_config int gpgpu_operand_collector_num_units_sp; int gpgpu_operand_collector_num_units_sfu; int gpgpu_operand_collector_num_units_tensor_core; - int gpgpu_operand_collector_num_units_vp_core; int gpgpu_operand_collector_num_units_mem; int gpgpu_operand_collector_num_units_gen; unsigned int gpgpu_operand_collector_num_in_ports_sp; unsigned int gpgpu_operand_collector_num_in_ports_sfu; unsigned int gpgpu_operand_collector_num_in_ports_tensor_core; - unsigned int gpgpu_operand_collector_num_in_ports_vp_core; unsigned int gpgpu_operand_collector_num_in_ports_mem; unsigned int gpgpu_operand_collector_num_in_ports_gen; unsigned int gpgpu_operand_collector_num_out_ports_sp; unsigned int gpgpu_operand_collector_num_out_ports_sfu; unsigned int gpgpu_operand_collector_num_out_ports_tensor_core; - unsigned int gpgpu_operand_collector_num_out_ports_vp_core; unsigned int gpgpu_operand_collector_num_out_ports_mem; unsigned int gpgpu_operand_collector_num_out_ports_gen; int gpgpu_num_sp_units; int gpgpu_num_sfu_units; int gpgpu_num_tensor_core_units; - int gpgpu_num_vp_core_units; int gpgpu_num_mem_units; //Shader core resources @@ -1416,7 +1376,6 @@ struct shader_core_config : public core_config unsigned max_sp_latency; unsigned max_sfu_latency; unsigned max_tensor_core_latency; - unsigned max_vp_core_latency; unsigned n_simt_cores_per_cluster; unsigned n_simt_clusters; @@ -1433,7 +1392,7 @@ struct shader_core_config : public core_config struct shader_core_stats_pod { - void* shader_core_stats_pod_start[]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure + void* shader_core_stats_pod_start[0]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure unsigned long long *shader_cycles; unsigned *m_num_sim_insn; // number of scalar thread instructions committed by this shader core unsigned *m_num_sim_winsn; // number of warp instructions committed by this shader core @@ -1455,7 +1414,6 @@ struct shader_core_stats_pod { unsigned *m_num_sp_acesses; unsigned *m_num_sfu_acesses; unsigned *m_num_tensor_core_acesses; - unsigned *m_num_vp_core_acesses; unsigned *m_num_trans_acesses; unsigned *m_num_mem_acesses; unsigned *m_num_sp_committed; @@ -1463,7 +1421,6 @@ struct shader_core_stats_pod { unsigned *m_num_tlb_accesses; unsigned *m_num_sfu_committed; unsigned *m_num_tensor_core_committed; - unsigned *m_num_vp_core_committed; unsigned *m_num_mem_committed; unsigned *m_read_regfile_acesses; unsigned *m_write_regfile_acesses; @@ -1473,7 +1430,6 @@ struct shader_core_stats_pod { unsigned *m_active_sp_lanes; unsigned *m_active_sfu_lanes; unsigned *m_active_tensor_core_lanes; - unsigned *m_active_vp_core_lanes; unsigned *m_active_fu_lanes; unsigned *m_active_fu_mem_lanes; unsigned *m_n_diverge; // number of divergence occurring in this shader @@ -1546,7 +1502,6 @@ public: m_num_sp_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_sfu_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_tensor_core_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); - m_num_vp_core_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_trans_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_mem_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_sp_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); @@ -1555,12 +1510,10 @@ public: m_active_sp_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_active_sfu_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_active_tensor_core_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); - m_active_vp_core_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_active_fu_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_active_fu_mem_lanes= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_sfu_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_tensor_core_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); - m_num_vp_core_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_num_mem_committed= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_read_regfile_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); m_write_regfile_acesses= (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); diff --git a/src/gpgpu-sim/traffic_breakdown.cc b/src/gpgpu-sim/traffic_breakdown.cc index 587067f..32f0d30 100644 --- a/src/gpgpu-sim/traffic_breakdown.cc +++ b/src/gpgpu-sim/traffic_breakdown.cc @@ -46,7 +46,6 @@ std::string traffic_breakdown::classify_memfetch(class mem_fetch * mf) break; default: assert(0 && "Unknown traffic type"); } - printf("%s:Icnt:%s:Request: %x,Size%d,DataSize:%d,CntrlSize%d:\n",m_network_name.c_str(),traffic_name.c_str(),mf->get_addr(),mf->size(),mf->get_data_size(),mf->get_ctrl_size()); return traffic_name; } diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index a6d7eb4..ede9f20 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -91,9 +91,17 @@ void *gpgpu_sim_thread_sequential(void*) pthread_mutex_t g_sim_lock = PTHREAD_MUTEX_INITIALIZER; bool g_sim_active = false; bool g_sim_done = true; +bool break_limit = false; + +static void termination_callback() +{ + printf("GPGPU-Sim: *** exit detected ***\n"); + fflush(stdout); +} void *gpgpu_sim_thread_concurrent(void*) { + atexit(termination_callback); // concurrent kernel execution simulation thread do { if(g_debug_execution >= 3) { @@ -134,6 +142,7 @@ void *gpgpu_sim_thread_concurrent(void*) gpgpu_cuda_ptx_sim_main_func(*kernel); g_the_gpu->finish_functional_sim(kernel); } + //performance simulation if( g_the_gpu->active() ) { g_the_gpu->cycle(); @@ -143,17 +152,19 @@ void *gpgpu_sim_thread_concurrent(void*) if(g_the_gpu->cycle_insn_cta_max_hit()){ g_stream_manager->stop_all_running_kernels(); g_sim_done = true; + break_limit = true; } } active=g_the_gpu->active() || !g_stream_manager->empty_protected(); - } while( active ); + + } while( active && !g_sim_done); if(g_debug_execution >= 3) { printf("GPGPU-Sim: ** STOP simulation thread (no work) **\n"); fflush(stdout); } - g_the_gpu->print_stats(); if(sim_cycles) { + g_the_gpu->print_stats(); g_the_gpu->update_stats(); print_simulation_time(); } @@ -161,10 +172,14 @@ void *gpgpu_sim_thread_concurrent(void*) g_sim_active = false; pthread_mutex_unlock(&g_sim_lock); } while( !g_sim_done ); - if(g_debug_execution >= 3) { - printf("GPGPU-Sim: *** simulation thread exiting ***\n"); - fflush(stdout); + printf("GPGPU-Sim: *** simulation thread exiting ***\n"); + fflush(stdout); + + if(break_limit) { + printf("GPGPU-Sim: ** break due to reaching the maximum cycles (or instructions) **\n"); + exit(1); } + sem_post(&g_sim_signal_exit); return NULL; } @@ -178,7 +193,7 @@ void synchronize() bool done = false; do { pthread_mutex_lock(&g_sim_lock); - done = g_stream_manager->empty() && !g_sim_active; + done = ( g_stream_manager->empty() && !g_sim_active ) || g_sim_done; pthread_mutex_unlock(&g_sim_lock); } while (!done); printf("GPGPU-Sim: detected inactive GPU simulation thread\n"); diff --git a/src/stream_manager.h b/src/stream_manager.h index 222a1b2..d3a804f 100644 --- a/src/stream_manager.h +++ b/src/stream_manager.h @@ -93,7 +93,7 @@ public: m_stream=stream; m_done=false; } - stream_operation( class CUevent_st *e, struct CUstream_st *stream ) + stream_operation( struct CUevent_st *e, struct CUstream_st *stream ) { m_kernel=NULL; m_type=stream_event; @@ -172,10 +172,10 @@ private: bool m_sim_mode; kernel_info_t *m_kernel; - class CUevent_st *m_event; + struct CUevent_st *m_event; }; -class CUevent_st { +struct CUevent_st { public: CUevent_st( bool blocking ) { diff --git a/src/trace_streams.tup b/src/trace_streams.tup index c41690e..fd68a16 100644 --- a/src/trace_streams.tup +++ b/src/trace_streams.tup @@ -29,5 +29,6 @@ TS_TUP_BEGIN( trace_streams_type ) TS_TUP( WARP_SCHEDULER ), TS_TUP( SCOREBOARD ), TS_TUP( MEMORY_PARTITION_UNIT ), + TS_TUP( LIVENESS ), TS_TUP( NUM_TRACE_STREAMS ) TS_TUP_END( trace_streams_type ) |