diff options
Diffstat (limited to 'src')
32 files changed, 2259 insertions, 269 deletions
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index 7922bc5..29df769 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -536,13 +536,30 @@ void warp_inst_t::memory_coalescing_arch(bool is_write, transaction_info &info = subwarp_transactions[block_address]; // can only write to one segment - assert(block_address == line_size_based_tag_func( - addr + data_size_coales - 1, segment_size)); + //it seems like in trace driven, a thread can write to more than one segment + //assert(block_address == line_size_based_tag_func(addr+data_size_coales-1,segment_size)); info.chunks.set(chunk); info.active.set(thread); unsigned idx = (addr & 127); - for (unsigned i = 0; i < data_size_coales; i++) info.bytes.set(idx + i); + for( unsigned i=0; i < data_size_coales; i++ ) + if((idx+i) < MAX_MEMORY_ACCESS_SIZE) + info.bytes.set(idx+i); + + //it seems like in trace driven, a thread can write to more than one segment + //handle this special case + if(block_address != line_size_based_tag_func(addr+data_size_coales-1,segment_size)) { + addr = addr+data_size_coales-1; + unsigned block_address = line_size_based_tag_func(addr,segment_size); + unsigned chunk = (addr&127)/32; + transaction_info &info = subwarp_transactions[block_address]; + info.chunks.set(chunk); + info.active.set(thread); + unsigned idx = (addr&127); + for( unsigned i=0; i < data_size_coales; i++ ) + if((idx+i) < MAX_MEMORY_ACCESS_SIZE) + info.bytes.set(idx+i); + } } } @@ -746,6 +763,8 @@ kernel_info_t::kernel_info_t(dim3 gridDim, dim3 blockDim, // Jin: launch latency management m_launch_latency = entry->gpgpu_ctx->device_runtime->g_kernel_launch_latency; + m_kernel_TB_latency = entry->gpgpu_ctx->device_runtime->g_kernel_launch_latency + num_blocks() * entry->gpgpu_ctx->device_runtime->g_TB_launch_latency; + cache_config_set = false; } @@ -773,6 +792,8 @@ kernel_info_t::kernel_info_t( // Jin: launch latency management m_launch_latency = entry->gpgpu_ctx->device_runtime->g_kernel_launch_latency; + m_kernel_TB_latency = entry->gpgpu_ctx->device_runtime->g_kernel_launch_latency + num_blocks() * entry->gpgpu_ctx->device_runtime->g_TB_launch_latency; + cache_config_set = false; m_NameToCudaArray = nameToCudaArray; m_NameToTextureInfo = nameToTextureInfo; diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 46534ab..a640ba3 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -65,7 +65,11 @@ enum FuncCache { FuncCachePreferL1 = 2 }; -enum AdaptiveCache { FIXED = 0, VOLTA = 1 }; +enum AdaptiveCache +{ + FIXED = 0, + ADAPTIVE_VOLTA = 1 +}; #ifdef __cplusplus @@ -97,7 +101,8 @@ enum uarch_op_t { BARRIER_OP, MEMORY_BARRIER_OP, CALL_OPS, - RET_OPS + RET_OPS, + EXIT_OPS }; typedef enum uarch_op_t op_type; @@ -323,9 +328,11 @@ class kernel_info_t { unsigned long long launch_cycle; unsigned long long start_cycle; unsigned long long end_cycle; - unsigned m_launch_latency; + unsigned m_launch_latency; mutable bool cache_config_set; + + unsigned m_kernel_TB_latency; //this used for any CPU-GPU kernel latency and counted in the gpu_cycle }; class core_config { diff --git a/src/cuda-sim/cuda_device_runtime.h b/src/cuda-sim/cuda_device_runtime.h index 1d661b2..4ede31a 100644 --- a/src/cuda-sim/cuda_device_runtime.h +++ b/src/cuda-sim/cuda_device_runtime.h @@ -43,6 +43,7 @@ class cuda_device_runtime { std::map<void*, device_launch_config_t> g_cuda_device_launch_param_map; std::list<device_launch_operation_t> g_cuda_device_launch_op; unsigned g_kernel_launch_latency; + unsigned g_TB_launch_latency; unsigned long long g_max_total_param_size; bool g_cdp_enabled; diff --git a/src/cuda-sim/ptx-stats.cc b/src/cuda-sim/ptx-stats.cc index 9f7e760..8661a29 100644 --- a/src/cuda-sim/ptx-stats.cc +++ b/src/cuda-sim/ptx-stats.cc @@ -168,6 +168,7 @@ void ptx_file_line_stats_add_exec_count(const ptx_instruction *pInsn) { void ptx_stats::ptx_file_line_stats_add_latency(unsigned pc, unsigned latency) { const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc); + if(pInsn != NULL) ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), pInsn->source_line())] .latency += latency; @@ -179,6 +180,7 @@ void ptx_stats::ptx_file_line_stats_add_dram_traffic(unsigned pc, unsigned dram_traffic) { const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc); + if(pInsn != NULL) ptx_file_line_stats_tracker[ptx_file_line(pInsn->source_file(), pInsn->source_line())] .dram_traffic += dram_traffic; @@ -191,10 +193,12 @@ void ptx_stats::ptx_file_line_stats_add_smem_bank_conflict( unsigned pc, unsigned n_way_bkconflict) { const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc); + if(pInsn != NULL) { ptx_file_line_stats &line_stats = ptx_file_line_stats_tracker[ptx_file_line( pInsn->source_file(), pInsn->source_line())]; - line_stats.smem_n_way_bank_conflict_total += n_way_bkconflict; - line_stats.smem_warp_count += 1; + line_stats.smem_n_way_bank_conflict_total += n_way_bkconflict; + line_stats.smem_warp_count += 1; + } } // attribute a non-coalesced mem access to a ptx instruction @@ -204,10 +208,12 @@ void ptx_stats::ptx_file_line_stats_add_uncoalesced_gmem(unsigned pc, unsigned n_access) { const ptx_instruction *pInsn = gpgpu_ctx->pc_to_instruction(pc); + if(pInsn != NULL) { ptx_file_line_stats &line_stats = ptx_file_line_stats_tracker[ptx_file_line( pInsn->source_file(), pInsn->source_line())]; - line_stats.gmem_n_access_total += n_access; - line_stats.gmem_warp_count += 1; + line_stats.gmem_n_access_total += n_access; + line_stats.gmem_warp_count += 1; + } } // a class that tracks the inflight memory instructions of a shader core diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 6627847..67cf157 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1336,12 +1336,13 @@ class function_info { memory_space *param_mem, gpgpu_t *gpu, dim3 gridDim, dim3 blockDim); - const struct gpgpu_ptx_sim_info *get_kernel_info() const { + virtual const struct gpgpu_ptx_sim_info* get_kernel_info () const + { assert(m_kernel_info.maxthreads == maxnt_id); return &m_kernel_info; } - const void set_kernel_info(const struct gpgpu_ptx_sim_info &info) { + virtual const void set_kernel_info (const struct gpgpu_ptx_sim_info &info) { m_kernel_info = info; m_kernel_info.ptx_version = 10 * get_ptx_version().ver(); m_kernel_info.sm_target = get_ptx_version().target(); @@ -1377,6 +1378,10 @@ class function_info { // backward pointer class gpgpu_context *gpgpu_ctx; +protected: + //Registers/shmem/etc. used (from ptxas -v), loaded from ___.ptxinfo along with ___.ptx + struct gpgpu_ptx_sim_info m_kernel_info; + private: unsigned maxnt_id; unsigned m_uid; @@ -1400,9 +1405,8 @@ class function_info { std::map<std::string, unsigned> labels; unsigned num_reconvergence_pairs; - // Registers/shmem/etc. used (from ptxas -v), loaded from ___.ptxinfo along + //Registers/shmem/etc. used (from ptxas -v), loaded from ___.ptxinfo along with ___.ptx // with ___.ptx - struct gpgpu_ptx_sim_info m_kernel_info; symbol_table *m_symtab; diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 372bda4..0b217a6 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -38,7 +38,7 @@ /// extern prototypes -extern int ptx_error(yyscan_t yyscanner, const char *s); +extern int ptx_error( yyscan_t yyscanner, ptx_recognizer* recognizer, const char *s ); extern int ptx_lex_init(yyscan_t *scanner); extern void ptx_set_in(FILE *_in_str, yyscan_t yyscanner); extern int ptx_parse(yyscan_t scanner, ptx_recognizer *recognizer); diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index 3ae8de3..a401ed6 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -36,7 +36,7 @@ typedef void *yyscan_t; extern int ptx_get_lineno(yyscan_t yyscanner); extern YYSTYPE *ptx_get_lval(yyscan_t yyscanner); -extern int ptx_error(yyscan_t yyscanner, const char *s); +extern int ptx_error( yyscan_t yyscanner, ptx_recognizer* recognizer, const char *s ); extern int ptx_lex_init(yyscan_t *scanner); extern void ptx_set_in(FILE *_in_str, yyscan_t yyscanner); extern FILE *ptx_get_in(yyscan_t yyscanner); @@ -225,7 +225,7 @@ void ptx_recognizer::parse_error_impl(const char *file, unsigned line, g_error_detected = 1; printf("%s:%u: Parse error: %s (%s:%u)\n\n", gpgpu_ctx->g_filename, ptx_get_lineno(scanner), buf, file, line); - ptx_error(scanner, NULL); + ptx_error(scanner, this, NULL); abort(); exit(1); } diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc index 655d790..3018d3a 100644 --- a/src/gpgpu-sim/addrdec.cc +++ b/src/gpgpu-sim/addrdec.cc @@ -28,6 +28,7 @@ #include "addrdec.h" #include <string.h> +#include <math.h> #include "../option_parser.h" #include "gpu-sim.h" @@ -64,8 +65,7 @@ void linear_to_raw_address_translation::addrdec_setoption(option_parser_t opp) { "0 = old addressing mask, 1 = new addressing mask, 2 " "= new add. mask + flipped bank sel and chip sel bits", "0"); - option_parser_register( - opp, "-memory_partition_indexing", OPT_UINT32, &memory_partition_indexing, + option_parser_register(opp, "-gpgpu_memory_partition_indexing", OPT_UINT32, &memory_partition_indexing, "0 = no indexing, 1 = bitwise xoring, 2 = IPoly, 3 = custom indexing", "0"); } @@ -89,7 +89,7 @@ new_addr_type linear_to_raw_address_translation::partition_address( void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_t *tlx) const { - unsigned long long int addr_for_chip, rest_of_addr; + unsigned long long int addr_for_chip, rest_of_addr, rest_of_addr_high_bits; if (!gap) { tlx->chip = addrdec_packbits(addrdec_mask[CHIP], addr, addrdec_mkhigh[CHIP], addrdec_mklow[CHIP]); @@ -101,6 +101,8 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_mklow[COL]); tlx->burst = addrdec_packbits(addrdec_mask[BURST], addr, addrdec_mkhigh[BURST], addrdec_mklow[BURST]); + rest_of_addr_high_bits = (addr>>(ADDR_CHIP_S+(log2channel+log2sub_partition))); + } else { // Split the given address at ADDR_CHIP_S into (MSBs,LSBs) // - extract chip address using modulus of MSBs @@ -108,6 +110,7 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, // the LSBs addr_for_chip = (addr >> ADDR_CHIP_S) % m_n_channel; rest_of_addr = ((addr >> ADDR_CHIP_S) / m_n_channel) << ADDR_CHIP_S; + rest_of_addr_high_bits = ((addr>>ADDR_CHIP_S) / m_n_channel); rest_of_addr |= addr & ((1 << ADDR_CHIP_S) - 1); tlx->chip = addr_for_chip; @@ -127,7 +130,7 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, break; case BITWISE_PERMUTATION: { assert(!gap); - tlx->chip = (tlx->chip) ^ (tlx->row & (m_n_channel - 1)); + tlx->chip = (tlx->chip) ^ (rest_of_addr_high_bits & (m_n_channel-1)); assert(tlx->chip < m_n_channel); break; } @@ -136,13 +139,29 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, * Set Indexing function from "Pseudo-randomly interleaved memory." * Rau, B. R et al. * ISCA 1991 + * http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=348DEA37A3E440473B3C075EAABC63B6?doi=10.1.1.12.7149&rep=rep1&type=pdf * - * equations are adopted from: + * equations are corresponding to IPOLY(37) and are adopted from: * "Sacat: streaming-aware conflict-avoiding thrashing-resistant gpgpu * cache management scheme." Khairy et al. IEEE TPDS 2017. + * + * equations for 32 banks are corresponding to IPOLY(37) + * equations for 64 banks are corresponding to IPOLY(67) + * To see all the IPOLY equations for all the degrees, see + * http://wireless-systems.ece.gatech.edu/6604/handouts/Peterson's%20Table.pdf + * + * We generate these equations using GF(2) arithmetic: + * http://www.ee.unb.ca/cgi-bin/tervo/calc.pl?num=&den=&f=d&e=1&m=1 + * + * We go through all the strides 128 (10000000), 256 (100000000),... and do modular arithmetic in GF(2) + * Then, we create the H-matrix and group each bit together, for more info read the ISCA 1991 paper + * + * IPOLY hashing guarantees conflict-free for all 2^n strides which widely exit in GPGPU applications + * and also show good performance for other strides. */ - if (m_n_channel == 32) { - std::bitset<64> a(tlx->row); + assert(!gap); + if(m_n_channel == 32 && m_n_sub_partition_in_channel == 1) { + std::bitset<64> a( rest_of_addr_high_bits); std::bitset<5> chip(tlx->chip); chip[0] = a[13] ^ a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[6] ^ a[5] ^ a[3] ^ a[0] ^ chip[0]; @@ -155,13 +174,41 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, chip[4] = a[12] ^ a[11] ^ a[10] ^ a[9] ^ a[8] ^ a[5] ^ a[4] ^ a[2] ^ chip[4]; tlx->chip = chip.to_ulong(); - + break; + } else if (m_n_channel == 16 && m_n_sub_partition_in_channel==2) { + std::bitset<64> a( rest_of_addr_high_bits); + std::bitset<4> chip(tlx->chip); + std::bitset<32> bk(tlx->bk); + chip[0] = a[13]^a[12]^a[11]^a[10]^a[9]^a[6]^a[5]^a[3]^a[0]^chip[0]; + chip[1] = a[14]^a[13]^a[12]^a[11]^a[10]^a[7]^a[6]^a[4]^a[1]^chip[1]; + chip[2] = a[14]^a[10]^a[9]^a[8]^a[7]^a[6]^a[3]^a[2]^a[0]^chip[2]; + chip[3] = a[11]^a[10]^a[9]^a[8]^a[7]^a[4]^a[3]^a[1]^chip[3]; + tlx->chip = chip.to_ulong(); + unsigned par_id = a[12]^a[11]^a[10]^a[9]^a[8]^a[5]^a[4]^a[2]^bk[0]; + tlx->sub_partition = tlx->chip * m_n_sub_partition_in_channel + par_id; + assert(tlx->chip < m_n_channel); + assert(tlx->sub_partition < m_n_channel * m_n_sub_partition_in_channel); + return; + break; + } else if (m_n_channel == 32 && m_n_sub_partition_in_channel==2) { + std::bitset<64> a( rest_of_addr_high_bits); + std::bitset<5> chip(tlx->chip); + std::bitset<32> bk(tlx->bk); + chip[0] = a[18]^a[17]^a[16]^a[15]^a[12]^a[10]^a[6]^a[5]^a[0]^chip[0]; + chip[1] = a[15]^a[13]^a[12]^a[11]^a[10]^a[7]^a[5]^a[1]^a[0]^chip[1]; + chip[2] = a[16]^a[14]^a[13]^a[12]^a[11]^a[8]^a[6]^a[2]^a[1]^chip[2]; + chip[3] = a[17]^a[15]^a[14]^a[13]^a[12]^a[9]^a[7]^a[3]^a[2]^chip[3]; + chip[4] = a[18]^a[16]^a[15]^a[14]^a[13]^a[10]^a[8]^a[4]^a[3]^chip[4]; + tlx->chip = chip.to_ulong(); + unsigned par_id = a[17]^a[16]^a[15]^a[14]^a[11]^a[9]^a[5]^a[4]^bk[0]; + tlx->sub_partition = tlx->chip * m_n_sub_partition_in_channel + par_id; + assert(tlx->chip < m_n_channel); + assert(tlx->sub_partition < m_n_channel * m_n_sub_partition_in_channel); + return; + break; } else { /* Else incorrect number of channels for the hashing function */ - assert( - "\nGPGPU-Sim memory_partition_indexing error: The number of " - "channels should be " - "32 for the hashing IPOLY index function.\n" && - 0); + assert("\nGPGPU-Sim memory_partition_indexing error: The number of channels should be " + "32 or 64 for the hashing IPOLY index function.\n" && 0); } assert(tlx->chip < m_n_channel); break; @@ -171,7 +218,7 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, // random selected bits from the page and bank bits // similar to // Liu, Yuxi, et al. "Get Out of the Valley: Power-Efficient Address - // Mapping for GPUs." ISCA 2018 + assert(!gap); std::bitset<64> a(tlx->row); std::bitset<5> chip(tlx->chip); std::bitset<4> b(tlx->bk); @@ -187,8 +234,7 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, case RANDOM: { // This is an unrealistic hashing using software hashtable // we generate a random set for each memory address and save the value in - // a big hashtable for future reuse - new_addr_type chip_address = (addr >> ADDR_CHIP_S); + new_addr_type chip_address = (addr>>(ADDR_CHIP_S-log2sub_partition)); tr1_hash_map<new_addr_type, unsigned>::const_iterator got = address_random_interleaving.find(chip_address); if (got == address_random_interleaving.end()) { @@ -308,6 +354,8 @@ void linear_to_raw_address_translation::init( unsigned i; unsigned long long int mask; unsigned int nchipbits = ::LOGB2_32(n_channel); + log2channel = nchipbits; + log2sub_partition = ::LOGB2_32(n_sub_partition_in_channel); m_n_channel = n_channel; m_n_sub_partition_in_channel = n_sub_partition_in_channel; diff --git a/src/gpgpu-sim/addrdec.h b/src/gpgpu-sim/addrdec.h index 03b84a4..6eddb15 100644 --- a/src/gpgpu-sim/addrdec.h +++ b/src/gpgpu-sim/addrdec.h @@ -87,6 +87,8 @@ class linear_to_raw_address_translation { unsigned int gap; unsigned m_n_channel; int m_n_sub_partition_in_channel; + unsigned log2channel; + unsigned log2sub_partition; }; #endif diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index 02356b2..6f3155f 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -207,8 +207,31 @@ dram_req_t::dram_req_t(class mem_fetch *mf, unsigned banks, } case BITWISE_XORING_BK_INDEX: { // xoring bank bits with lower bits of the page - int lbank = log2(banks); + int lbank = LOGB2(banks); bk = tlx.bk ^ (tlx.row & ((1 << lbank) - 1)); + break; + } + case IPOLY_BK_INDEX: + { + /*IPOLY for bank indexing function from "Pseudo-randomly interleaved memory." + * Rau, B. R et al. + * ISCA 1991 + * http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=348DEA37A3E440473B3C075EAABC63B6?doi=10.1.1.12.7149&rep=rep1&type=pdf + */ + if (banks == 16) { + std::bitset<64> a(tlx.row); + std::bitset<4> b(tlx.bk); + b[0] = a[11]^a[10]^a[9]^a[8]^a[6]^a[4]^a[3]^a[0]^b[0]; + b[1] = a[12]^a[8]^a[7]^a[6]^a[5]^a[3]^a[1]^a[0]^b[1]; + b[2] = a[9]^a[8]^a[7]^a[6]^a[4]^a[2]^a[1]^b[2]; + b[3] = a[10]^a[9]^a[8]^a[7]^a[5]^a[3]^a[2]^b[3]; + bk = b.to_ulong(); + assert(bk < banks); + } + else{ /* Else incorrect number of channels for the hashing function */ + assert("\nGPGPU-Sim memory_banking indexing error: The number of banks should be " + "16 for the hashing IPOLY index function.\n" && 0); + } break; } case CUSTOM_BK_INDEX: diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index 2e39a43..fbdf1e1 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -97,6 +97,7 @@ struct bank_t { enum bank_index_function { LINEAR_BK_INDEX = 0, BITWISE_XORING_BK_INDEX, + IPOLY_BK_INDEX, CUSTOM_BK_INDEX }; diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index af22c4c..cafa8d9 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -1315,6 +1315,9 @@ enum cache_request_status data_cache::wr_miss_wa_naive( mem_fetch *wb = m_memfetch_creator->alloc( evicted.m_block_addr, m_wrbk_type, evicted.m_modified_size, true, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); + //the evicted block may have wrong chip id when advanced L2 hashing is used, so set the right chip address from the original mf + wb->set_chip(mf->get_tlx_addr().chip); + wb->set_parition(mf->get_tlx_addr().sub_partition); send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); } @@ -1358,6 +1361,9 @@ enum cache_request_status data_cache::wr_miss_wa_fetch_on_write( mem_fetch *wb = m_memfetch_creator->alloc( evicted.m_block_addr, m_wrbk_type, evicted.m_modified_size, true, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); + //the evicted block may have wrong chip id when advanced L2 hashing is used, so set the right chip address from the original mf + wb->set_chip(mf->get_tlx_addr().chip); + wb->set_parition(mf->get_tlx_addr().sub_partition); send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); } @@ -1424,6 +1430,9 @@ enum cache_request_status data_cache::wr_miss_wa_fetch_on_write( mem_fetch *wb = m_memfetch_creator->alloc( evicted.m_block_addr, m_wrbk_type, evicted.m_modified_size, true, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); + //the evicted block may have wrong chip id when advanced L2 hashing is used, so set the right chip address from the original mf + wb->set_chip(mf->get_tlx_addr().chip); + wb->set_parition(mf->get_tlx_addr().sub_partition); send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); } @@ -1473,6 +1482,9 @@ enum cache_request_status data_cache::wr_miss_wa_lazy_fetch_on_read( mem_fetch *wb = m_memfetch_creator->alloc( evicted.m_block_addr, m_wrbk_type, evicted.m_modified_size, true, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); + //the evicted block may have wrong chip id when advanced L2 hashing is used, so set the right chip address from the original mf + wb->set_chip(mf->get_tlx_addr().chip); + wb->set_parition(mf->get_tlx_addr().sub_partition); send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); } @@ -1545,6 +1557,9 @@ enum cache_request_status data_cache::rd_miss_base( mem_fetch *wb = m_memfetch_creator->alloc( evicted.m_block_addr, m_wrbk_type, evicted.m_modified_size, true, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); + //the evicted block may have wrong chip id when advanced L2 hashing is used, so set the right chip address from the original mf + wb->set_chip(mf->get_tlx_addr().chip); + wb->set_parition(mf->get_tlx_addr().sub_partition); send_write_request(wb, WRITE_BACK_REQUEST_SENT, time, events); } return MISS; diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index a6a39ab..34bc7d9 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -65,6 +65,7 @@ #include "power_stat.h" #include "stats.h" #include "visualizer.h" +#include "../trace-driven/trace_driven.h" #ifdef GPGPUSIM_POWER_MODEL #include "power_interface.h" @@ -129,10 +130,9 @@ void power_config::reg_options(class OptionParser *opp) { } void memory_config::reg_options(class OptionParser *opp) { - option_parser_register(opp, "-perf_sim_memcpy", OPT_BOOL, &m_perf_sim_memcpy, + option_parser_register(opp, "-gpgpu_perf_sim_memcpy", OPT_BOOL, &m_perf_sim_memcpy, "Fill the L2 cache on memcpy", "1"); - option_parser_register(opp, "-simple_dram_model", OPT_BOOL, - &simple_dram_model, + option_parser_register(opp, "-gpgpu_simple_dram_model", OPT_BOOL, &simple_dram_model, "simple_dram_model with fixed latency and BW", "0"); option_parser_register(opp, "-gpgpu_dram_scheduler", OPT_INT32, &scheduler_type, "0 = fifo, 1 = FR-FCFS (defaul)", @@ -187,12 +187,11 @@ void memory_config::reg_options(class OptionParser *opp) { "DRAM timing parameters = " "{nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}", "4:2:8:12:21:13:34:9:4:5:13:1:0:0"); - option_parser_register(opp, "-rop_latency", OPT_UINT32, &rop_latency, + option_parser_register(opp, "-gpgpu_l2_rop_latency", OPT_UINT32, &rop_latency, "ROP queue latency (default 85)", "85"); option_parser_register(opp, "-dram_latency", OPT_UINT32, &dram_latency, "DRAM latency (default 30)", "30"); - option_parser_register(opp, "-dual_bus_interface", OPT_UINT32, - &dual_bus_interface, + option_parser_register(opp, "-dram_dual_bus_interface", OPT_UINT32, &dual_bus_interface, "dual_bus_interface (default = 0) ", "0"); option_parser_register(opp, "-dram_bnk_indexing_policy", OPT_UINT32, &dram_bnk_indexing_policy, @@ -204,13 +203,11 @@ void memory_config::reg_options(class OptionParser *opp) { "dram_bnkgrp_indexing_policy (0 = take higher bits, 1 " "= take lower bits) (Default = 0)", "0"); - option_parser_register(opp, "-Seperate_Write_Queue_Enable", OPT_BOOL, - &seperate_write_queue_enabled, + option_parser_register(opp, "-dram_seperate_write_queue_enable", OPT_BOOL, &seperate_write_queue_enabled, "Seperate_Write_Queue_Enable", "0"); - option_parser_register(opp, "-Write_Queue_Size", OPT_CSTR, - &write_queue_size_opt, "Write_Queue_Size", "32:28:16"); - option_parser_register( - opp, "-Elimnate_rw_turnaround", OPT_BOOL, &elimnate_rw_turnaround, + option_parser_register(opp, "-dram_write_queue_size", OPT_CSTR, &write_queue_size_opt, + "Write_Queue_Size", "32:28:16"); + option_parser_register(opp, "-dram_elimnate_rw_turnaround", OPT_BOOL, &elimnate_rw_turnaround, "elimnate_rw_turnaround i.e set tWTR and tRTW = 0", "0"); option_parser_register(opp, "-icnt_flit_size", OPT_UINT32, &icnt_flit_size, "icnt_flit_size", "32"); @@ -248,11 +245,11 @@ void shader_core_config::reg_options(class OptionParser *opp) { " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_" "alloc>,<mshr>:<N>:<merge>,<mq> | none}", "none"); - option_parser_register(opp, "-l1_banks", OPT_UINT32, &m_L1D_config.l1_banks, + option_parser_register(opp, "-gpgpu_l1_banks", OPT_UINT32, &m_L1D_config.l1_banks, "The number of L1 cache banks", "1"); - option_parser_register(opp, "-l1_latency", OPT_UINT32, - &m_L1D_config.l1_latency, "L1 Hit Latency", "1"); - option_parser_register(opp, "-smem_latency", OPT_UINT32, &smem_latency, + option_parser_register(opp, "-gpgpu_l1_latency", OPT_UINT32, &m_L1D_config.l1_latency, + "L1 Hit Latency", "1"); + option_parser_register(opp, "-gpgpu_smem_latency", OPT_UINT32, &smem_latency, "smem Latency", "3"); option_parser_register(opp, "-gpgpu_cache:dl1PrefL1", OPT_CSTR, &m_L1D_config.m_config_stringPrefL1, @@ -266,7 +263,7 @@ void shader_core_config::reg_options(class OptionParser *opp) { " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_" "alloc>,<mshr>:<N>:<merge>,<mq> | none}", "none"); - option_parser_register(opp, "-gmem_skip_L1D", OPT_BOOL, &gmem_skip_L1D, + option_parser_register(opp, "-gpgpu_gmem_skip_L1D", OPT_BOOL, &gmem_skip_L1D, "global memory access skip L1D cache (implements " "-Xptxas -dlcm=cg, default=no skip)", "0"); @@ -318,8 +315,8 @@ void shader_core_config::reg_options(class OptionParser *opp) { option_parser_register( opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size, "Size of shared memory per shader core (default 16kB)", "16384"); - option_parser_register(opp, "-adaptive_cache_config", OPT_BOOL, - &adaptive_cache_config, "adaptive_cache_config", "0"); + option_parser_register(opp, "-gpgpu_adaptive_cache_config", OPT_UINT32, &adaptive_cache_config, + "adaptive_cache_config", "0"); option_parser_register( opp, "-gpgpu_shmem_sizeDefault", OPT_UINT32, &gpgpu_shmem_sizeDefault, "Size of shared memory per shader core (default 16kB)", "16384"); @@ -342,8 +339,7 @@ void shader_core_config::reg_options(class OptionParser *opp) { "Number of portions a warp is divided into for shared " "memory bank conflict check ", "2"); - option_parser_register( - opp, "-mem_unit_ports", OPT_INT32, &mem_unit_ports, + option_parser_register(opp, "-gpgpu_mem_unit_ports", OPT_INT32, &mem_unit_ports, "The number of memory transactions allowed per core cycle", "1"); option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &mem_warp_parts, @@ -369,9 +365,9 @@ void shader_core_config::reg_options(class OptionParser *opp) { option_parser_register( opp, "-gpgpu_reg_bank_use_warp_id", OPT_BOOL, &gpgpu_reg_bank_use_warp_id, "Use warp ID in mapping registers to banks (default = off)", "0"); - option_parser_register(opp, "-sub_core_model", OPT_BOOL, &sub_core_model, + option_parser_register(opp, "-gpgpu_sub_core_model", OPT_BOOL, &sub_core_model, "Sub Core Volta/Pascal model (default = off)", "0"); - option_parser_register(opp, "-enable_specialized_operand_collector", OPT_BOOL, + option_parser_register(opp, "-gpgpu_enable_specialized_operand_collector", OPT_BOOL, &enable_specialized_operand_collector, "enable_specialized_operand_collector", "1"); option_parser_register(opp, "-gpgpu_operand_collector_num_units_sp", @@ -496,9 +492,9 @@ void shader_core_config::reg_options(class OptionParser *opp) { "1"); option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32, &gpgpu_num_tensor_core_units, - "Number of tensor_core units (default=1)", "1"); - option_parser_register( - opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units, + "Number of tensor_core units (default=1)", + "0"); + option_parser_register(opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units, "Number if ldst units (default=1) WARNING: not hooked up to anything", "1"); option_parser_register( @@ -515,6 +511,31 @@ void shader_core_config::reg_options(class OptionParser *opp) { option_parser_register( opp, "-gpgpu_concurrent_kernel_sm", OPT_BOOL, &gpgpu_concurrent_kernel_sm, "Support concurrent kernels on a SM (default = disabled)", "0"); + option_parser_register(opp, "-gpgpu_perfect_inst_const_cache", OPT_BOOL, &perfect_inst_const_cache, + "perfect inst and const cache mode, so all inst and const hits in the cache(default = disabled)", + "0"); + option_parser_register(opp, "-gpgpu_inst_fetch_throughput", OPT_INT32, &inst_fetch_throughput, + "the number of fetched intruction per warp each cycle", + "1"); + option_parser_register(opp, "-gpgpu_reg_file_port_throughput", OPT_INT32, ®_file_port_throughput, + "the number ports of the register file", + "1"); + //used for trace-driven mode + option_parser_register(opp, "-trace_opcode_latency_initiation_int", OPT_CSTR, &trace_opcode_latency_initiation_int, + "Opcode latencies and initiation for integers in trace driven mode <latency,initiation>", + "4,1"); + option_parser_register(opp, "-trace_opcode_latency_initiation_sp", OPT_CSTR, &trace_opcode_latency_initiation_sp, + "Opcode latencies and initiation for sp in trace driven mode <latency,initiation>", + "4,1"); + option_parser_register(opp, "-trace_opcode_latency_initiation_dp", OPT_CSTR, &trace_opcode_latency_initiation_dp, + "Opcode latencies and initiation for dp in trace driven mode <latency,initiation>", + "4,1"); + option_parser_register(opp, "-trace_opcode_latency_initiation_sfu", OPT_CSTR, &trace_opcode_latency_initiation_sfu, + "Opcode latencies and initiation for sfu in trace driven mode <latency,initiation>", + "4,1"); + option_parser_register(opp, "-trace_opcode_latency_initiation_tensor", OPT_CSTR, &trace_opcode_latency_initiation_tensor, + "Opcode latencies and initiation for tensor in trace driven mode <latency,initiation>", + "4,1"); } void gpgpu_sim_config::reg_options(option_parser_t opp) { @@ -620,6 +641,22 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) { option_parser_register(opp, "-gpgpu_cdp_enabled", OPT_BOOL, &(gpgpu_ctx->device_runtime->g_cdp_enabled), "Turn on CDP", "0"); + + option_parser_register(opp, "-gpgpu_TB_launch_latency", OPT_INT32, + &(gpgpu_ctx->device_runtime->g_TB_launch_latency), "thread block launch latency in cycles. Default: 0", + "0"); + + //Trace driven mode parameters + option_parser_register(opp, "-trace_driven_mode", OPT_BOOL, + &trace_driven_mode, "Turn on trace_driven_mode", + "0"); + option_parser_register(opp, "-trace_skip_first_kernel", OPT_BOOL, + &trace_skip_first_kernel, "skip first intiliztion kernel in trace mode", + "0"); + option_parser_register(opp, "-trace", OPT_CSTR, + &g_traces_filename, "traces kernel file" + "traces kernel file directory", + "./traces/kernelslist.g"); } ///////////////////////////////////////////////////////////////////////////// @@ -696,9 +733,18 @@ bool gpgpu_sim::get_more_cta_left() const { return false; } +void gpgpu_sim::decrement_kernel_latency() +{ + for(unsigned n=0; n < m_running_kernels.size(); n++ ) { + if( m_running_kernels[n] && m_running_kernels[n]->m_kernel_TB_latency ) + m_running_kernels[n]->m_kernel_TB_latency--; + } +} + kernel_info_t *gpgpu_sim::select_kernel() { if (m_running_kernels[m_last_issued_kernel] && - !m_running_kernels[m_last_issued_kernel]->no_more_ctas_to_run()) { + !m_running_kernels[m_last_issued_kernel]->no_more_ctas_to_run() && + !m_running_kernels[m_last_issued_kernel]->m_kernel_TB_latency) { unsigned launch_uid = m_running_kernels[m_last_issued_kernel]->get_uid(); if (std::find(m_executed_kernel_uids.begin(), m_executed_kernel_uids.end(), launch_uid) == m_executed_kernel_uids.end()) { @@ -714,7 +760,8 @@ kernel_info_t *gpgpu_sim::select_kernel() { for (unsigned n = 0; n < m_running_kernels.size(); n++) { unsigned idx = (n + m_last_issued_kernel + 1) % m_config.max_concurrent_kernel; - if (kernel_more_cta_left(m_running_kernels[idx])) { + if( kernel_more_cta_left(m_running_kernels[idx]) && + !m_running_kernels[idx]->m_kernel_TB_latency){ m_last_issued_kernel = idx; m_running_kernels[idx]->start_cycle = gpu_sim_cycle + gpu_tot_sim_cycle; // record this kernel for stat print if it is the first time this kernel @@ -1583,6 +1630,11 @@ void shader_core_ctx::issue_block2core(kernel_info_t &kernel) { for (unsigned i = start_thread; i < end_thread; i++) { m_threadState[i].m_cta_id = free_cta_hw_id; unsigned warp_id = i / m_config->warp_size; + if(m_gpu->get_config().is_trace_driven_mode()) { + trace_shader_core_ctx* trace_core = static_cast<trace_shader_core_ctx*> (this); + nthreads_in_block += trace_core->trace_sim_inc_thread(kernel); + } + else nthreads_in_block += ptx_sim_init_thread( kernel, &m_thread[i], m_sid, i, cta_size - (i - start_thread), m_config->n_thread_per_shader, this, free_cta_hw_id, warp_id, @@ -1621,8 +1673,7 @@ void shader_core_ctx::issue_block2core(kernel_info_t &kernel) { m_barriers.allocate_barrier(free_cta_hw_id, warps); // initialize the SIMT stacks and fetch hardware - init_warps(free_cta_hw_id, start_thread, end_thread, ctaid, cta_size, - kernel.get_uid()); + init_warps( free_cta_hw_id, start_thread, end_thread, ctaid, cta_size, kernel); m_n_active_cta++; shader_CTA_count_log(m_sid, 1); @@ -1814,6 +1865,7 @@ void gpgpu_sim::cycle() { #endif issue_block2core(); + decrement_kernel_latency(); // Depending on configuration, invalidate the caches once all of threads are // completed. @@ -1926,7 +1978,8 @@ void shader_core_ctx::dump_warp_state(FILE *fout) const { void gpgpu_sim::perf_memcpy_to_gpu(size_t dst_start_addr, size_t count) { if (m_memory_config->m_perf_sim_memcpy) { - assert(dst_start_addr % 32 == 0); + //if(!m_config.trace_driven_mode) //in trace-driven mode, CUDA runtime can start nre data structure at any position + // assert (dst_start_addr % 32 == 0); for (unsigned counter = 0; counter < count; counter += 32) { const unsigned wr_addr = dst_start_addr + counter; diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 19fbf5d..0c4474c 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -370,6 +370,12 @@ class gpgpu_sim_config : public power_config, return runtime_pending_launch_count_limit; } + bool is_trace_driven_mode() const { return trace_driven_mode; } + bool is_skip_first_kernel() const { return trace_skip_first_kernel; } + char* get_traces_filename() const { return g_traces_filename; } + bool flush_l1() const { return gpgpu_flush_l1_cache; } + + private: void init_clock_domains(void); @@ -422,6 +428,11 @@ class gpgpu_sim_config : public power_config, unsigned int gpgpu_compute_capability_minor; unsigned long long liveness_message_freq; + //trace driven mode options + bool trace_driven_mode; + bool trace_skip_first_kernel; + char *g_traces_filename; + friend class gpgpu_sim; }; @@ -525,6 +536,7 @@ class gpgpu_sim : public gpgpu_t { bool kernel_more_cta_left(kernel_info_t *kernel) const; bool hit_max_cta_count() const; kernel_info_t *select_kernel(); + void decrement_kernel_latency(); const gpgpu_sim_config &get_config() const { return m_config; } void gpu_print_stat(); diff --git a/src/gpgpu-sim/icnt_wrapper.cc b/src/gpgpu-sim/icnt_wrapper.cc index 890638a..4ae7aa8 100644 --- a/src/gpgpu-sim/icnt_wrapper.cc +++ b/src/gpgpu-sim/icnt_wrapper.cc @@ -144,16 +144,14 @@ void icnt_reg_options(class OptionParser* opp) { "Interconnection network config file", "mesh"); // parameters for local xbar - option_parser_register(opp, "-inct_in_buffer_limit", OPT_UINT32, - &g_inct_config.in_buffer_limit, "in_buffer_limit", - "64"); - option_parser_register(opp, "-inct_out_buffer_limit", OPT_UINT32, - &g_inct_config.out_buffer_limit, "out_buffer_limit", - "64"); - option_parser_register(opp, "-inct_subnets", OPT_UINT32, - &g_inct_config.subnets, "subnets", "2"); - option_parser_register(opp, "-arbiter_algo", OPT_UINT32, - &g_inct_config.arbiter_algo, "arbiter_algo", "1"); + option_parser_register(opp, "-icnt_in_buffer_limit", OPT_UINT32, &g_inct_config.in_buffer_limit, "in_buffer_limit", "64"); + option_parser_register(opp, "-icnt_out_buffer_limit", OPT_UINT32, &g_inct_config.out_buffer_limit, "out_buffer_limit", "64"); + option_parser_register(opp, "-icnt_subnets", OPT_UINT32, &g_inct_config.subnets, "subnets", "2"); + option_parser_register(opp, "-icnt_arbiter_algo", OPT_UINT32, &g_inct_config.arbiter_algo, "arbiter_algo", "1"); + option_parser_register(opp, "-icnt_verbose", OPT_UINT32, &g_inct_config.verbose, "inct_verbose", "0"); + option_parser_register(opp, "-icnt_grant_cycles", OPT_UINT32, &g_inct_config.grant_cycles, "grant_cycles", "1"); + + } void icnt_wrapper_init() { diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index ab6e5c2..6651b21 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -793,7 +793,9 @@ void memory_sub_partition::push(mem_fetch *m_req, unsigned long long cycle) { mem_fetch *memory_sub_partition::pop() { mem_fetch *mf = m_L2_icnt_queue->pop(); m_request_tracker.erase(mf); - if (mf && mf->isatomic()) mf->do_atomic(); + if ( mf && mf->isatomic() && !m_gpu->get_config().is_trace_driven_mode() ){ + mf->do_atomic(); + } if (mf && (mf->get_access_type() == L2_WRBK_ACC || mf->get_access_type() == L1_WRBK_ACC)) { delete mf; diff --git a/src/gpgpu-sim/local_interconnect.cc b/src/gpgpu-sim/local_interconnect.cc index cd32386..f74960e 100644 --- a/src/gpgpu-sim/local_interconnect.cc +++ b/src/gpgpu-sim/local_interconnect.cc @@ -37,22 +37,22 @@ #include "local_interconnect.h" #include "mem_fetch.h" -xbar_router::xbar_router(unsigned router_id, enum Interconnect_type m_type, - unsigned n_shader, unsigned n_mem, - unsigned m_in_buffer_limit, - unsigned m_out_buffer_limit, - enum Arbiteration_type m_arbit_type) { +xbar_router::xbar_router(unsigned router_id, enum Interconnect_type m_type, unsigned n_shader, unsigned n_mem, const struct inct_config& m_localinct_config) +{ m_id = router_id; router_type = m_type; _n_mem = n_mem; _n_shader = n_shader; total_nodes = n_shader + n_mem; + verbose=m_localinct_config.verbose; + grant_cycles = m_localinct_config.grant_cycles; + grant_cycles_count = m_localinct_config.grant_cycles; in_buffers.resize(total_nodes); out_buffers.resize(total_nodes); next_node.resize(total_nodes, 0); - in_buffer_limit = m_in_buffer_limit; - out_buffer_limit = m_out_buffer_limit; - arbit_type = m_arbit_type; + in_buffer_limit = m_localinct_config.in_buffer_limit; + out_buffer_limit = m_localinct_config.out_buffer_limit; + arbit_type = m_localinct_config.arbiter_algo; next_node_id = 0; if (m_type == REQ_NET) { active_in_buffers = n_shader; @@ -69,6 +69,9 @@ xbar_router::xbar_router(unsigned router_id, enum Interconnect_type m_type, out_buffer_util = 0; in_buffer_util = 0; packets_num = 0; + conflicts_util=0; + cycles_util=0; + reqs_util=0; } xbar_router::~xbar_router() {} @@ -117,14 +120,18 @@ void xbar_router::Advance() { } void xbar_router::RR_Advance() { - cycles++; + bool active = false; vector<bool> issued(total_nodes, false); + unsigned conflict_sub =0 ; + unsigned reqs =0 ; + for (unsigned i = 0; i < total_nodes; ++i) { unsigned node_id = (i + next_node_id) % total_nodes; if (!in_buffers[node_id].empty()) { + active=true; Packet _packet = in_buffers[node_id].front(); // ensure that the outbuffer has space and not issued before in this cycle if (Has_Buffer_Out(_packet.output_deviceID, 1)) { @@ -132,23 +139,40 @@ void xbar_router::RR_Advance() { out_buffers[_packet.output_deviceID].push(_packet); in_buffers[node_id].pop(); issued[_packet.output_deviceID] = true; + reqs++; } else - conflicts++; + conflict_sub++; } else { out_buffer_full++; - if (issued[_packet.output_deviceID]) conflicts++; + if(issued[_packet.output_deviceID]) + conflict_sub++; } } } next_node_id = (++next_node_id % total_nodes); + conflicts += conflict_sub; + if(active){ + conflicts_util += conflict_sub; + cycles_util++; + reqs_util+=reqs; + } + + if(verbose) { + printf("%d : cycle %d : conflicts = %d\n", m_id, cycles, conflict_sub); + printf("%d : cycle %d : passing reqs = %d\n", m_id, cycles, reqs); + } + // collect some stats about buffer util for (unsigned i = 0; i < total_nodes; ++i) { in_buffer_util += in_buffers[i].size(); out_buffer_util += out_buffers[i].size(); } + + cycles++; + } // iSLIP algorithm @@ -156,26 +180,36 @@ void xbar_router::RR_Advance() { // IEEE/ACM transactions on networking 2 (1999): 188-201. // https://www.cs.rutgers.edu/~sn624/552-F18/papers/islip.pdf void xbar_router::iSLIP_Advance() { - cycles++; vector<unsigned> node_tmp; + bool active = false; - // calcaulte how many conflicts are there for stats + unsigned conflict_sub =0 ; + unsigned reqs =0 ; + + //calcaulte how many conflicts are there for stats for (unsigned i = 0; i < total_nodes; ++i) { + if (!in_buffers[i].empty()) { Packet _packet_tmp = in_buffers[i].front(); if (!node_tmp.empty()) { if (std::find(node_tmp.begin(), node_tmp.end(), _packet_tmp.output_deviceID) != node_tmp.end()) { - conflicts++; + conflict_sub++; } else node_tmp.push_back(_packet_tmp.output_deviceID); } else { node_tmp.push_back(_packet_tmp.output_deviceID); } + active=true; } } + conflicts += conflict_sub; + if(active){ + conflicts_util += conflict_sub; + cycles_util++; + } // do iSLIP for (unsigned i = 0; i < total_nodes; ++i) { if (Has_Buffer_Out(i, 1)) { @@ -187,7 +221,23 @@ void xbar_router::iSLIP_Advance() { if (_packet.output_deviceID == i) { out_buffers[_packet.output_deviceID].push(_packet); in_buffers[node_id].pop(); - next_node[i] = (++node_id % total_nodes); + if(verbose) + printf("%d : cycle %d : send req from %d to %d\n", m_id, cycles, node_id, i-_n_shader); + if(grant_cycles_count == 1) + next_node[i] = (++node_id % total_nodes); + if(verbose){ + for(unsigned k=j+1; k<total_nodes; ++k){ + unsigned node_id2 = (k+next_node[i])%total_nodes; + if(!in_buffers[node_id2].empty()) { + Packet _packet2 = in_buffers[node_id2].front(); + + if(_packet2.output_deviceID==i) + printf("%d : cycle %d : cannot send req from %d to %d\n", m_id, cycles, node_id2, i-_n_shader); + } + } + } + + reqs++; break; } } @@ -196,11 +246,33 @@ void xbar_router::iSLIP_Advance() { out_buffer_full++; } + if(active){ + reqs_util+=reqs; + } + + if(verbose) + printf("%d : cycle %d : grant_cycles = %d\n", m_id, cycles, grant_cycles); + + if(active && grant_cycles_count == 1) + grant_cycles_count = grant_cycles; + else if (active) + grant_cycles_count--; + + + if(verbose) { + printf("%d : cycle %d : conflicts = %d\n", m_id, cycles, conflict_sub); + printf("%d : cycle %d : passing reqs = %d\n", m_id, cycles, reqs); + } + + // collect some stats about buffer util for (unsigned i = 0; i < total_nodes; ++i) { in_buffer_util += in_buffers[i].size(); out_buffer_util += out_buffers[i].size(); } + + cycles++; + } bool xbar_router::Busy() const { @@ -246,10 +318,7 @@ void LocalInterconnect::CreateInterconnect(unsigned m_n_shader, net.resize(n_subnets); for (unsigned i = 0; i < n_subnets; ++i) { - net[i] = new xbar_router(i, static_cast<Interconnect_type>(i), m_n_shader, - m_n_mem, m_inct_config.in_buffer_limit, - m_inct_config.out_buffer_limit, - m_inct_config.arbiter_algo); + net[i] = new xbar_router( i, static_cast<Interconnect_type>(i), m_n_shader, m_n_mem, m_inct_config); } } @@ -312,51 +381,29 @@ bool LocalInterconnect::HasBuffer(unsigned deviceID, unsigned int size) const { } void LocalInterconnect::DisplayStats() const { - cout << "Req_Network_injected_packets_num = " << net[REQ_NET]->packets_num - << endl; - cout << "Req_Network_cycles = " << net[REQ_NET]->cycles << endl; - cout << "Req_Network_injected_packets_per_cycle = " - << (float)(net[REQ_NET]->packets_num) / (net[REQ_NET]->cycles) << endl; - cout << "Req_Network_conflicts_per_cycle = " - << (float)(net[REQ_NET]->conflicts) / (net[REQ_NET]->cycles) << endl; - cout << "Req_Network_in_buffer_full_per_cycle = " - << (float)(net[REQ_NET]->in_buffer_full) / (net[REQ_NET]->cycles) - << endl; - cout << "Req_Network_in_buffer_avg_util = " - << ((float)(net[REQ_NET]->in_buffer_util) / (net[REQ_NET]->cycles) / - net[REQ_NET]->active_in_buffers) - << endl; - cout << "Req_Network_out_buffer_full_per_cycle = " - << (float)(net[REQ_NET]->out_buffer_full) / (net[REQ_NET]->cycles) - << endl; - cout << "Req_Network_out_buffer_avg_util = " - << ((float)(net[REQ_NET]->out_buffer_util) / (net[REQ_NET]->cycles) / - net[REQ_NET]->active_out_buffers) - << endl; + printf("Req_Network_injected_packets_num = %lld\n", net[REQ_NET]->packets_num); + printf("Req_Network_cycles = %lld\n", net[REQ_NET]->cycles); + printf("Req_Network_injected_packets_per_cycle = %12.4f \n", (float)(net[REQ_NET]->packets_num) / (net[REQ_NET]->cycles)); + printf("Req_Network_conflicts_per_cycle = %12.4f\n", (float)(net[REQ_NET]->conflicts) / (net[REQ_NET]->cycles)); + printf("Req_Network_conflicts_per_cycle_util = %12.4f\n", (float)(net[REQ_NET]->conflicts_util) / (net[REQ_NET]->cycles_util)); + printf("Req_Bank_Level_Parallism = %12.4f\n", (float)(net[REQ_NET]->reqs_util) / (net[REQ_NET]->cycles_util)); + printf("Req_Network_in_buffer_full_per_cycle = %12.4f\n", (float)(net[REQ_NET]->in_buffer_full) / (net[REQ_NET]->cycles)); + printf("Req_Network_in_buffer_avg_util = %12.4f\n", ((float)(net[REQ_NET]->in_buffer_util) / (net[REQ_NET]->cycles) / net[REQ_NET]->active_in_buffers)); + printf("Req_Network_out_buffer_full_per_cycle = %12.4f\n", (float)(net[REQ_NET]->out_buffer_full) / (net[REQ_NET]->cycles)); + printf("Req_Network_out_buffer_avg_util = %12.4f\n", ((float)(net[REQ_NET]->out_buffer_util) / (net[REQ_NET]->cycles) / net[REQ_NET]->active_out_buffers)); + + printf("\n"); + printf("Reply_Network_injected_packets_num = %lld\n", net[REPLY_NET]->packets_num); + printf("Reply_Network_cycles = %lld\n", net[REPLY_NET]->cycles); + printf("Reply_Network_injected_packets_per_cycle = %12.4f\n", (float)(net[REPLY_NET]->packets_num) / (net[REPLY_NET]->cycles)); + printf("Reply_Network_conflicts_per_cycle = %12.4f\n", (float)(net[REPLY_NET]->conflicts) / (net[REPLY_NET]->cycles)); + printf("Reply_Network_conflicts_per_cycle_util = %12.4f\n", (float)(net[REPLY_NET]->conflicts_util) / (net[REPLY_NET]->cycles_util)); + printf("Reply_Bank_Level_Parallism = %12.4f\n", (float)(net[REPLY_NET]->reqs_util) / (net[REPLY_NET]->cycles_util)); + printf("Reply_Network_in_buffer_full_per_cycle = %12.4f\n", (float)(net[REPLY_NET]->in_buffer_full) / (net[REPLY_NET]->cycles)); + printf("Reply_Network_in_buffer_avg_util = %12.4f\n", ((float)(net[REPLY_NET]->in_buffer_util) / (net[REPLY_NET]->cycles) / net[REPLY_NET]->active_in_buffers)); + printf("Reply_Network_out_buffer_full_per_cycle = %12.4f\n", (float)(net[REPLY_NET]->out_buffer_full) / (net[REPLY_NET]->cycles)); + printf("Reply_Network_out_buffer_avg_util = %12.4f\n", ((float)(net[REPLY_NET]->out_buffer_util) / (net[REPLY_NET]->cycles) / net[REPLY_NET]->active_out_buffers)); - cout << endl; - cout << "Reply_Network_injected_packets_num = " << net[REPLY_NET]->packets_num - << endl; - cout << "Reply_Network_cycles = " << net[REPLY_NET]->cycles << endl; - cout << "Reply_Network_injected_packets_per_cycle = " - << (float)(net[REPLY_NET]->packets_num) / (net[REPLY_NET]->cycles) - << endl; - cout << "Reply_Network_conflicts_per_cycle = " - << (float)(net[REPLY_NET]->conflicts) / (net[REPLY_NET]->cycles) << endl; - cout << "Reply_Network_in_buffer_full_per_cycle = " - << (float)(net[REPLY_NET]->in_buffer_full) / (net[REPLY_NET]->cycles) - << endl; - cout << "Reply_Network_in_buffer_avg_util = " - << ((float)(net[REPLY_NET]->in_buffer_util) / (net[REPLY_NET]->cycles) / - net[REPLY_NET]->active_in_buffers) - << endl; - cout << "Reply_Network_out_buffer_full_per_cycle = " - << (float)(net[REPLY_NET]->out_buffer_full) / (net[REPLY_NET]->cycles) - << endl; - cout << "Reply_Network_out_buffer_avg_util= " - << ((float)(net[REPLY_NET]->out_buffer_util) / (net[REPLY_NET]->cycles) / - net[REPLY_NET]->active_out_buffers) - << endl; } void LocalInterconnect::DisplayOverallStats() const {} diff --git a/src/gpgpu-sim/local_interconnect.h b/src/gpgpu-sim/local_interconnect.h index 29cd903..ff55bad 100644 --- a/src/gpgpu-sim/local_interconnect.h +++ b/src/gpgpu-sim/local_interconnect.h @@ -45,16 +45,15 @@ struct inct_config { unsigned out_buffer_limit; unsigned subnets; Arbiteration_type arbiter_algo; + unsigned verbose; + unsigned grant_cycles; }; class xbar_router { public: - xbar_router(unsigned router_id, enum Interconnect_type m_type, - unsigned n_shader, unsigned n_mem, unsigned m_in_buffer_limit, - unsigned m_out_buffer_limit, enum Arbiteration_type m_arbit_type); - ~xbar_router(); - void Push(unsigned input_deviceID, unsigned output_deviceID, void* data, - unsigned int size); + xbar_router(unsigned router_id, enum Interconnect_type m_type, unsigned n_shader, unsigned n_mem, const struct inct_config& m_localinct_config); + ~xbar_router(); + void Push(unsigned input_deviceID, unsigned output_deviceID, void* data, unsigned int size); void* Pop(unsigned ouput_deviceID); void Advance(); @@ -66,6 +65,9 @@ class xbar_router { // some stats unsigned long long cycles; unsigned long long conflicts; + unsigned long long conflicts_util; + unsigned long long cycles_util; + unsigned long long reqs_util; unsigned long long out_buffer_full; unsigned long long out_buffer_util; unsigned long long in_buffer_full; @@ -94,6 +96,10 @@ class xbar_router { enum Interconnect_type router_type; unsigned active_in_buffers, active_out_buffers; Arbiteration_type arbit_type; + unsigned verbose; + + unsigned grant_cycles; + unsigned grant_cycles_count; friend class LocalInterconnect; }; diff --git a/src/gpgpu-sim/mem_fetch.cc b/src/gpgpu-sim/mem_fetch.cc index 7cb02cf..952c9e9 100644 --- a/src/gpgpu-sim/mem_fetch.cc +++ b/src/gpgpu-sim/mem_fetch.cc @@ -65,6 +65,10 @@ mem_fetch::mem_fetch(const mem_access_t &access, const warp_inst_t *inst, icnt_flit_size = config->icnt_flit_size; original_mf = m_original_mf; original_wr_mf = m_original_wr_mf; + if(m_original_mf){ + m_raw_addr.chip=m_original_mf->get_tlx_addr().chip; + m_raw_addr.sub_partition=m_original_mf->get_tlx_addr().sub_partition; + } } mem_fetch::~mem_fetch() { m_status = MEM_FETCH_DELETED; } diff --git a/src/gpgpu-sim/mem_fetch.h b/src/gpgpu-sim/mem_fetch.h index 71d8acd..1e5e04e 100644 --- a/src/gpgpu-sim/mem_fetch.h +++ b/src/gpgpu-sim/mem_fetch.h @@ -76,6 +76,8 @@ class mem_fetch { void print(FILE *fp, bool print_inst = true) const; const addrdec_t &get_tlx_addr() const { return m_raw_addr; } + void set_chip(unsigned chip_id) { m_raw_addr.chip = chip_id; } + void set_parition(unsigned sub_partition_id) { m_raw_addr.sub_partition = sub_partition_id; } unsigned get_data_size() const { return m_data_size; } void set_data_size(unsigned size) { m_data_size = size; } unsigned get_ctrl_size() const { return m_ctrl_size; } diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc index e50ad9e..7055769 100644 --- a/src/gpgpu-sim/mem_latency_stat.cc +++ b/src/gpgpu-sim/mem_latency_stat.cc @@ -42,6 +42,8 @@ #include <stdio.h> #include <stdlib.h> #include <string.h> +#include <math.h> + #include "../../libcuda/gpgpu_context.h" memory_stats_t::memory_stats_t(unsigned n_shader, @@ -226,15 +228,16 @@ void memory_stats_t::memlatstat_dram_access(mem_fetch *mf) { bankwrites[mf->get_sid()][dram_id][bank]++; shader_mem_acc_log(mf->get_sid(), dram_id, bank, 'w'); } - totalbankwrites[dram_id][bank]++; + totalbankwrites[dram_id][bank] += ceil(mf->get_data_size() / m_memory_config->dram_atom_size); } else { bankreads[mf->get_sid()][dram_id][bank]++; shader_mem_acc_log(mf->get_sid(), dram_id, bank, 'r'); - totalbankreads[dram_id][bank]++; + totalbankreads[dram_id][bank] += ceil(mf->get_data_size() / m_memory_config->dram_atom_size); } - mem_access_type_stats[mf->get_access_type()][dram_id][bank]++; + mem_access_type_stats[mf->get_access_type()][dram_id][bank] += ceil(mf->get_data_size() / m_memory_config->dram_atom_size); } - if (mf->get_pc() != (unsigned)-1) + + if (mf->get_pc() != (unsigned)-1) m_gpu->gpgpu_ctx->stats->ptx_file_line_stats_add_dram_traffic( mf->get_pc(), mf->get_data_size()); } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index b596c0d..268d4d4 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -47,6 +47,7 @@ #include "stat-tool.h" #include "traffic_breakdown.h" #include "visualizer.h" +#include "../trace-driven/trace_driven.h" #define PRIORITIZE_MSHR_OVER_WB 1 #define MAX(a, b) (((a) > (b)) ? (a) : (b)) @@ -367,12 +368,12 @@ shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu, m_fu.push_back(new dp_unit(&m_pipeline_reg[EX_WB], m_config, this)); m_dispatch_port.push_back(ID_OC_DP); m_issue_port.push_back(OC_EX_DP); - } + } for (int k = 0; k < m_config->gpgpu_num_int_units; k++) { m_fu.push_back(new int_unit(&m_pipeline_reg[EX_WB], m_config, this)); m_dispatch_port.push_back(ID_OC_INT); m_issue_port.push_back(OC_EX_INT); - } + } for (int k = 0; k < m_config->gpgpu_num_sfu_units; k++) { m_fu.push_back(new sfu(&m_pipeline_reg[EX_WB], m_config, this)); @@ -441,10 +442,11 @@ void shader_core_ctx::reinit(unsigned start_thread, unsigned end_thread, } } -void shader_core_ctx::init_warps(unsigned cta_id, unsigned start_thread, - unsigned end_thread, unsigned ctaid, - int cta_size, unsigned kernel_id) { - address_type start_pc = next_pc(start_thread); +void shader_core_ctx::init_warps( unsigned cta_id, unsigned start_thread, unsigned end_thread, unsigned ctaid, int cta_size, kernel_info_t &kernel ) +{ + // + address_type start_pc = next_pc(start_thread); + unsigned kernel_id = kernel.get_uid(); if (m_config->model == POST_DOMINATOR) { unsigned start_warp = start_thread / m_config->warp_size; unsigned warp_per_cta = cta_size / m_config->warp_size; @@ -473,8 +475,10 @@ void shader_core_ctx::init_warps(unsigned cta_id, unsigned start_thread, m_simt_stack[i]->resume(fname); m_simt_stack[i]->get_pdom_stack_top_info(&pc, &rpc); for (unsigned t = 0; t < m_config->warp_size; t++) { - m_thread[i * m_config->warp_size + t]->set_npc(pc); - m_thread[i * m_config->warp_size + t]->update_pc(); + if(m_thread != NULL) { + m_thread[i * m_config->warp_size + t]->set_npc(pc); + m_thread[i * m_config->warp_size + t]->update_pc(); + } } start_pc = pc; } @@ -483,7 +487,12 @@ void shader_core_ctx::init_warps(unsigned cta_id, unsigned start_thread, ++m_dynamic_warp_id; m_not_completed += n_active; ++m_active_warps; - } + } + + if(m_gpu->get_config().is_trace_driven_mode()){ + trace_shader_core_ctx* trace_core = static_cast<trace_shader_core_ctx*> (this); + trace_core->init_traces( start_warp, end_warp, kernel ); + } } } @@ -773,34 +782,45 @@ void shader_core_stats::visualizer_print(gzFile visualizer_file) { check ptx_ir.h to verify this does not overlap \ other memory spaces */ void shader_core_ctx::decode() { - if (m_inst_fetch_buffer.m_valid) { - // decode 1 or 2 instructions and place them into ibuffer - address_type pc = m_inst_fetch_buffer.m_pc; - const warp_inst_t *pI1 = m_gpu->gpgpu_ctx->ptx_fetch_inst(pc); - m_warp[m_inst_fetch_buffer.m_warp_id].ibuffer_fill(0, pI1); - m_warp[m_inst_fetch_buffer.m_warp_id].inc_inst_in_pipeline(); - if (pI1) { - m_stats->m_num_decoded_insn[m_sid]++; - if (pI1->oprnd_type == INT_OP) { - m_stats->m_num_INTdecoded_insn[m_sid]++; - } else if (pI1->oprnd_type == FP_OP) { - m_stats->m_num_FPdecoded_insn[m_sid]++; - } - const warp_inst_t *pI2 = - m_gpu->gpgpu_ctx->ptx_fetch_inst(pc + pI1->isize); - if (pI2) { - m_warp[m_inst_fetch_buffer.m_warp_id].ibuffer_fill(1, pI2); + if( m_inst_fetch_buffer.m_valid ) { + // decode 1 or 2 instructions and place them into ibuffer + address_type pc = m_inst_fetch_buffer.m_pc; + const warp_inst_t* pI1; + if(m_gpu->get_config().is_trace_driven_mode()){ + trace_shader_core_ctx* trace_core = static_cast<trace_shader_core_ctx*> (this); + pI1 = trace_core->m_trace_warp[m_inst_fetch_buffer.m_warp_id].get_next_inst(); + } + else + pI1 = m_gpu->gpgpu_ctx->ptx_fetch_inst(pc); + m_warp[m_inst_fetch_buffer.m_warp_id].ibuffer_fill(0,pI1); m_warp[m_inst_fetch_buffer.m_warp_id].inc_inst_in_pipeline(); - m_stats->m_num_decoded_insn[m_sid]++; - if (pI2->oprnd_type == INT_OP) { - m_stats->m_num_INTdecoded_insn[m_sid]++; - } else if (pI2->oprnd_type == FP_OP) { - m_stats->m_num_FPdecoded_insn[m_sid]++; + if( pI1 ) { + m_stats->m_num_decoded_insn[m_sid]++; + if(pI1->oprnd_type==INT_OP){ + m_stats->m_num_INTdecoded_insn[m_sid]++; + }else if(pI1->oprnd_type==FP_OP) { + m_stats->m_num_FPdecoded_insn[m_sid]++; + } + const warp_inst_t* pI2; + if(m_gpu->get_config().is_trace_driven_mode()){ + trace_shader_core_ctx* trace_core = static_cast<trace_shader_core_ctx*> (this); + pI2 = trace_core->m_trace_warp[m_inst_fetch_buffer.m_warp_id].get_next_inst(); + } + else + pI2 = m_gpu->gpgpu_ctx->ptx_fetch_inst(pc+pI1->isize); + if( pI2 ) { + m_warp[m_inst_fetch_buffer.m_warp_id].ibuffer_fill(1,pI2); + m_warp[m_inst_fetch_buffer.m_warp_id].inc_inst_in_pipeline(); + m_stats->m_num_decoded_insn[m_sid]++; + if(pI2->oprnd_type==INT_OP){ + m_stats->m_num_INTdecoded_insn[m_sid]++; + }else if(pI2->oprnd_type==FP_OP) { + m_stats->m_num_FPdecoded_insn[m_sid]++; + } + } } - } + m_inst_fetch_buffer.m_valid = false; } - m_inst_fetch_buffer.m_valid = false; - } } void shader_core_ctx::fetch() { @@ -810,6 +830,11 @@ void shader_core_ctx::fetch() { m_warp[mf->get_wid()].clear_imiss_pending(); m_inst_fetch_buffer = ifetch_buffer_t( m_warp[mf->get_wid()].get_pc(), mf->get_access_size(), mf->get_wid()); + if(m_gpu->get_config().is_trace_driven_mode()){ + trace_shader_core_ctx* trace_core = static_cast<trace_shader_core_ctx*> (this); + assert( trace_core->m_trace_warp[mf->get_wid()].get_pc() == (address_type)(mf->get_addr()-PROGRAM_MEM_START)); + } + else assert(m_warp[mf->get_wid()].get_pc() == (mf->get_addr() - PROGRAM_MEM_START)); // Verify that we got the instruction we @@ -836,10 +861,14 @@ void shader_core_ctx::fetch() { if (m_threadState[tid].m_active == true) { m_threadState[tid].m_active = false; unsigned cta_id = m_warp[warp_id].get_cta_id(); - register_cta_thread_exit(cta_id, &(m_thread[tid]->get_kernel())); + if(m_gpu->get_config().is_trace_driven_mode()) { + register_cta_thread_exit(cta_id, m_kernel); + } + else + register_cta_thread_exit(cta_id, &(m_thread[tid]->get_kernel())); m_not_completed -= 1; m_active_threads.reset(tid); - assert(m_thread[tid] != NULL); + if(!m_gpu->get_config().is_trace_driven_mode()) assert( m_thread[tid]!= NULL ); did_exit = true; } } @@ -849,29 +878,39 @@ void shader_core_ctx::fetch() { } // this code fetches instructions from the i-cache or generates memory - // requests - if (!m_warp[warp_id].functional_done() && - !m_warp[warp_id].imiss_pending() && - m_warp[warp_id].ibuffer_empty()) { - address_type pc = m_warp[warp_id].get_pc(); - address_type ppc = pc + PROGRAM_MEM_START; - unsigned nbytes = 16; - unsigned offset_in_block = - pc & (m_config->m_L1I_config.get_line_sz() - 1); + if( !m_warp[warp_id].functional_done() && !m_warp[warp_id].imiss_pending() && m_warp[warp_id].ibuffer_empty() ) { + address_type pc; + if(m_gpu->get_config().is_trace_driven_mode()){ + trace_shader_core_ctx* trace_core = static_cast<trace_shader_core_ctx*> (this); + pc = trace_core->m_trace_warp[warp_id].get_pc(); + } + else + pc = m_warp[warp_id].get_pc(); + address_type ppc = pc + PROGRAM_MEM_START; + unsigned nbytes= m_gpu->get_config().is_trace_driven_mode()? 32 : 16; + unsigned offset_in_block = pc & (m_config->m_L1I_config.get_line_sz()-1); if ((offset_in_block + nbytes) > m_config->m_L1I_config.get_line_sz()) nbytes = (m_config->m_L1I_config.get_line_sz() - offset_in_block); // TODO: replace with use of allocator // mem_fetch *mf = m_mem_fetch_allocator->alloc() mem_access_t acc(INST_ACC_R, ppc, nbytes, false, m_gpu->gpgpu_ctx); - mem_fetch *mf = new mem_fetch( - acc, NULL /*we don't have an instruction yet*/, READ_PACKET_SIZE, - warp_id, m_sid, m_tpc, m_memory_config, - m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); - std::list<cache_event> events; - enum cache_request_status status = m_L1I->access( - (new_addr_type)ppc, mf, - m_gpu->gpu_sim_cycle + m_gpu->gpu_tot_sim_cycle, events); + mem_fetch *mf = new mem_fetch(acc, + NULL/*we don't have an instruction yet*/, + READ_PACKET_SIZE, + warp_id, + m_sid, + m_tpc, + m_memory_config, + m_gpu->gpu_tot_sim_cycle+m_gpu->gpu_sim_cycle + ); + std::list<cache_event> events; + enum cache_request_status status; + if(m_config->perfect_inst_const_cache) + status = HIT; + else + status = m_L1I->access( (new_addr_type)ppc, mf, m_gpu->gpu_sim_cycle+m_gpu->gpu_tot_sim_cycle,events); + if (status == MISS) { m_last_warp_fetched = warp_id; m_warp[warp_id].set_imiss_pending(); @@ -909,29 +948,33 @@ void shader_core_ctx::issue_warp(register_set &pipe_reg_set, unsigned warp_id, unsigned sch_id) { warp_inst_t **pipe_reg = pipe_reg_set.get_free(m_config->sub_core_model, sch_id); - assert(pipe_reg); + assert(pipe_reg); - m_warp[warp_id].ibuffer_free(); - assert(next_inst->valid()); - **pipe_reg = *next_inst; // static instruction information + m_warp[warp_id].ibuffer_free(); + assert(next_inst->valid()); + **pipe_reg = *next_inst; // static instruction information (*pipe_reg)->issue(active_mask, warp_id, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle, m_warp[warp_id].get_dynamic_warp_id(), sch_id); // dynamic instruction information - m_stats->shader_cycle_distro[2 + (*pipe_reg)->active_count()]++; - func_exec_inst(**pipe_reg); - if (next_inst->op == BARRIER_OP) { - m_warp[warp_id].store_info_of_last_inst_at_barrier(*pipe_reg); + m_stats->shader_cycle_distro[2+(*pipe_reg)->active_count()]++; + func_exec_inst( **pipe_reg ); + + if( next_inst->op == BARRIER_OP ){ + m_warp[warp_id].store_info_of_last_inst_at_barrier(*pipe_reg); m_barriers.warp_reaches_barrier(m_warp[warp_id].get_cta_id(), warp_id, const_cast<warp_inst_t *>(next_inst)); - } else if (next_inst->op == MEMORY_BARRIER_OP) { - m_warp[warp_id].set_membar(); - } + }else if( next_inst->op == MEMORY_BARRIER_OP ){ + m_warp[warp_id].set_membar(); + } + + if(!m_gpu->get_config().is_trace_driven_mode()) //No SIMT-stack in trace-driven mode + updateSIMTStack(warp_id,*pipe_reg); + + m_scoreboard->reserveRegisters(*pipe_reg); + m_warp[warp_id].set_next_pc(next_inst->pc + next_inst->isize); - updateSIMTStack(warp_id, *pipe_reg); - m_scoreboard->reserveRegisters(*pipe_reg); - m_warp[warp_id].set_next_pc(next_inst->pc + next_inst->isize); } void shader_core_ctx::issue() { @@ -1067,7 +1110,15 @@ void scheduler_unit::cycle() { // dual issue to diff execution // units (as in Maxwell and // Pascal) - + + if(warp(warp_id).ibuffer_empty()) + SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) fails as ibuffer_empty\n", + (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id() ); + + if(warp(warp_id).waiting()) + SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) fails as waiting for barrier\n", + (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id() ); + while (!warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue)) { @@ -1082,7 +1133,10 @@ void scheduler_unit::cycle() { bool valid = warp(warp_id).ibuffer_next_valid(); bool warp_inst_issued = false; unsigned pc, rpc; - m_simt_stack[warp_id]->get_pdom_stack_top_info(&pc, &rpc); + if(m_shader->m_gpu->get_config().is_trace_driven_mode()) + pc = pI->pc; //assume no control hazard in trace mode. TO DO: to be fixed + else + m_simt_stack[warp_id]->get_pdom_stack_top_info(&pc,&rpc); SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) has valid instruction (%s)\n", (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id(), @@ -1105,8 +1159,11 @@ void scheduler_unit::cycle() { "Warp (warp_id %u, dynamic_warp_id %u) passes scoreboard\n", (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id()); ready_inst = true; - const active_mask_t &active_mask = - m_simt_stack[warp_id]->get_active_mask(); + + //For Trace-driven, the active mask already set in from traces, so just read it from the inst + const active_mask_t &active_mask = m_shader->m_gpu->get_config().is_trace_driven_mode()? + pI->get_active_mask() : m_simt_stack[warp_id]->get_active_mask(); + assert(warp(warp_id).inst_in_pipeline()); if ((pI->op == LOAD_OP) || (pI->op == STORE_OP) || @@ -1125,18 +1182,14 @@ void scheduler_unit::cycle() { previous_issued_inst_exec_type = exec_unit_type_t::MEM; } } else { - bool sp_pipe_avail = - m_sp_out->has_free(m_shader->m_config->sub_core_model, m_id); - bool sfu_pipe_avail = - m_sfu_out->has_free(m_shader->m_config->sub_core_model, m_id); - bool tensor_core_pipe_avail = m_tensor_core_out->has_free( - m_shader->m_config->sub_core_model, m_id); - bool dp_pipe_avail = - m_dp_out->has_free(m_shader->m_config->sub_core_model, m_id); - bool int_pipe_avail = - m_int_out->has_free(m_shader->m_config->sub_core_model, m_id); - // This code need to be refactored + bool sp_pipe_avail = (m_shader->m_config->gpgpu_num_sp_units > 0) && m_sp_out->has_free(m_shader->m_config->sub_core_model, m_id); + bool sfu_pipe_avail = (m_shader->m_config->gpgpu_num_sfu_units > 0) && m_sfu_out->has_free(m_shader->m_config->sub_core_model, m_id); + bool tensor_core_pipe_avail = (m_shader->m_config->gpgpu_num_tensor_core_units > 0) && m_tensor_core_out->has_free(m_shader->m_config->sub_core_model, m_id); + bool dp_pipe_avail = (m_shader->m_config->gpgpu_num_dp_units > 0) && m_dp_out->has_free(m_shader->m_config->sub_core_model, m_id); + bool int_pipe_avail = (m_shader->m_config->gpgpu_num_int_units > 0) && m_int_out->has_free(m_shader->m_config->sub_core_model, m_id); + + //This code need to be refactored if (pI->op != TENSOR_CORE_OP && pI->op != SFU_OP && pI->op != DP_OP) { bool execute_on_SP = false; @@ -1225,12 +1278,10 @@ void scheduler_unit::cycle() { warp_inst_issued = true; previous_issued_inst_exec_type = exec_unit_type_t::SFU; } - } else if ((pI->op == TENSOR_CORE_OP) && - !(diff_exec_units && previous_issued_inst_exec_type == - exec_unit_type_t::SP)) { - if (tensor_core_pipe_avail) { - m_shader->issue_warp(*m_tensor_core_out, pI, active_mask, - warp_id, m_id); + } + else if ( (pI->op == TENSOR_CORE_OP) && !(diff_exec_units && previous_issued_inst_exec_type == exec_unit_type_t::TENSOR) ) { + if( tensor_core_pipe_avail ) { + m_shader->issue_warp(*m_tensor_core_out,pI,active_mask,warp_id,m_id); issued++; issued_inst = true; warp_inst_issued = true; @@ -1579,8 +1630,8 @@ void ldst_unit::get_L1T_sub_stats(struct cache_sub_stats &css) const { void shader_core_ctx::warp_inst_complete(const warp_inst_t &inst) { #if 0 - printf("[warp_inst_complete] uid=%u core=%u warp=%u pc=%#x @ time=%llu issued@%llu\n", - inst.get_uid(), m_sid, inst.warp_id(), inst.pc, gpu_tot_sim_cycle + gpu_sim_cycle, inst.get_issue_cycle()); + printf("[warp_inst_complete] uid=%u core=%u warp=%u pc=%#x @ time=%llu \n", + inst.get_uid(), m_sid, inst.warp_id(), inst.pc, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle); #endif if (inst.op_pipe == SP__OP) @@ -1647,9 +1698,13 @@ void shader_core_ctx::writeback() { } } -bool ldst_unit::shared_cycle(warp_inst_t &inst, mem_stage_stall_type &rc_fail, - mem_stage_access_type &fail_type) { - if (inst.space.get_type() != shared_space) return true; +bool ldst_unit::shared_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail, mem_stage_access_type &fail_type) +{ + if( inst.space.get_type() != shared_space ) + return true; + + if( inst.active_count() == 0 ) + return true; if (inst.has_dispatch_delay()) { m_stats->gpgpu_n_shmem_bank_access[m_sid]++; @@ -1852,7 +1907,20 @@ bool ldst_unit::constant_cycle(warp_inst_t &inst, mem_stage_stall_type &rc_fail, (inst.space.get_type() != param_space_kernel))) return true; if (inst.active_count() == 0) return true; - mem_stage_stall_type fail = process_memory_access_queue(m_L1C, inst); + + mem_stage_stall_type fail; + if(m_config->perfect_inst_const_cache) { + fail = NO_RC_FAIL; + while(inst.accessq_count() > 0) inst.accessq_pop_back(); + if ( inst.is_load() ) { + for ( unsigned r=0; r < MAX_OUTPUT_VALUES; r++) + if (inst.out[r] > 0) + m_pending_writes[inst.warp_id()][inst.out[r]]--; + } + } else { + fail = process_memory_access_queue(m_L1C,inst); + } + if (fail != NO_RC_FAIL) { rc_fail = fail; // keep other fails if this didn't fail. fail_type = C_MEM; @@ -1884,8 +1952,11 @@ bool ldst_unit::memory_cycle(warp_inst_t &inst, (inst.space.get_type() != local_space) && (inst.space.get_type() != param_space_local))) return true; - if (inst.active_count() == 0) return true; - assert(!inst.accessq_empty()); + if( inst.active_count() == 0 ) + return true; + if( inst.accessq_empty() ) + return true; + mem_stage_stall_type stall_cond = NO_RC_FAIL; const mem_access_t &access = inst.accessq_back(); @@ -2288,9 +2359,9 @@ void ldst_unit::writeback() { if (!m_pipeline_reg[0]->empty()) { m_next_wb = *m_pipeline_reg[0]; if (m_next_wb.isatomic()) { - m_next_wb.do_atomic(); - m_core->decrement_atomic_count(m_next_wb.warp_id(), - m_next_wb.active_count()); + if(!m_core->get_gpu()->get_config().is_trace_driven_mode()) + m_next_wb.do_atomic(); + m_core->decrement_atomic_count(m_next_wb.warp_id(), m_next_wb.active_count()); } m_core->dec_inst_in_pipeline(m_pipeline_reg[0]->warp_id()); m_pipeline_reg[0]->clear(); @@ -2316,10 +2387,11 @@ void ldst_unit::writeback() { case 3: // global/local if (m_next_global) { m_next_wb = m_next_global->get_inst(); - if (m_next_global->isatomic()) + if( m_next_global->isatomic() ) { m_core->decrement_atomic_count( m_next_global->get_wid(), m_next_global->get_access_warp_mask().count()); + } delete m_next_global; m_next_global = NULL; serviced_client = next_client; @@ -2374,9 +2446,11 @@ inst->space.get_type() != shared_space) { unsigned warp_id = inst->warp_id(); pipelined_simd_unit::issue(reg_set); } */ -void ldst_unit::cycle() { - writeback(); - m_operand_collector->step(); +void ldst_unit::cycle() +{ + writeback(); + for(int i=0; i< m_config->reg_file_port_throughput; ++i) + m_operand_collector->step(); for (unsigned stage = 0; (stage + 1) < m_pipeline_depth; stage++) if (m_pipeline_reg[stage]->empty() && !m_pipeline_reg[stage + 1]->empty()) move_warp(m_pipeline_reg[stage], m_pipeline_reg[stage + 1]); @@ -3095,11 +3169,11 @@ unsigned int shader_core_config::max_cta(const kernel_info_t &k) const { switch (adaptive_cache_config) { case FIXED: break; - case VOLTA: { + case ADAPTIVE_VOLTA: { // For Volta, we assign the remaining shared memory to L1 cache // For more info about adaptive cache, see // https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x - assert(gpgpu_shmem_size == 98304); // Volta has 96 KB shared + //assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared // To Do: make it flexible and not tuned to 9KB share memory unsigned max_assoc = m_L1D_config.get_max_assoc(); @@ -3184,8 +3258,10 @@ void shader_core_ctx::cycle() { execute(); read_operands(); issue(); - decode(); - fetch(); + for(int i=0; i< m_config->inst_fetch_throughput; ++i) { + decode(); + fetch(); + } } // Flushes all content of the cache to memory @@ -3234,28 +3310,31 @@ std::list<opndcoll_rfu_t::op_t> opndcoll_rfu_t::arbiter_t::allocate_reads() { ///// wavefront allocator from booksim... ---> // Loop through diagonals of request matrix + // printf("####\n"); for (int p = 0; p < _square; ++p) { - output = (_pri + p) % _square; + output = ( _pri + p ) % _outputs; // Step through the current diagonal for (input = 0; input < _inputs; ++input) { assert(input < _inputs); assert(output < _outputs); - if ((output < _outputs) && (_inmatch[input] == -1) && - (_outmatch[output] == -1) && + if ( ( output < _outputs ) && + ( _inmatch[input] == -1 ) && + //( _outmatch[output] == -1 ) && //allow OC to read multiple reg banks at the same cycle (_request[input][output] /*.label != -1*/)) { // Grant! _inmatch[input] = output; _outmatch[output] = input; + // printf("Register File: granting bank %d to OC %d, schedid %d, warpid %d, Regid %d\n", input, output, (m_queue[input].front()).get_sid(), (m_queue[input].front()).get_wid(), (m_queue[input].front()).get_reg()); } - output = (output + 1) % _square; + output = ( output + 1 ) % _outputs; } } // Round-robin the priority diagonal - _pri = (_pri + 1) % _square; + _pri = ( _pri + 1 ) % _outputs; /// <--- end code from booksim @@ -3481,6 +3560,15 @@ bool shader_core_ctx::warp_waiting_at_mem_barrier(unsigned warp_id) { if (!m_warp[warp_id].get_membar()) return false; if (!m_scoreboard->pendingWrites(warp_id)) { m_warp[warp_id].clear_membar(); + if (m_gpu->get_config().flush_l1()) { + //Mahmoud fixed this on Nov 2019 + //Invalidate L1 cache + //Based on Nvidia Doc, at MEM barrier, we have to + //(1) wait for all pending writes till they are acked + //(2) invalidate L1 cache to ensure coherence and avoid reading stall data + cache_invalidate(); + //TO DO: you need to stall the SM for 5k cycles. + } return false; } return true; @@ -3925,8 +4013,10 @@ simt_core_cluster::simt_core_cluster(class gpgpu_sim *gpu, unsigned cluster_id, m_core = new shader_core_ctx *[config->n_simt_cores_per_cluster]; for (unsigned i = 0; i < config->n_simt_cores_per_cluster; i++) { unsigned sid = m_config->cid_to_sid(i, m_cluster_id); - m_core[i] = new shader_core_ctx(gpu, this, sid, m_cluster_id, config, - mem_config, stats); + if(gpu->get_config().is_trace_driven_mode()) + m_core[i] = new trace_shader_core_ctx(gpu,this,sid,m_cluster_id,config,mem_config,stats); + else + m_core[i] = new shader_core_ctx(gpu,this,sid,m_cluster_id,config,mem_config,stats); m_core_sim_order.push_back(i); } } @@ -4267,3 +4357,5 @@ void shader_core_ctx::checkExecutionStatusAndUpdate(warp_inst_t &inst, } } } + + diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 1af35cf..7d8b77a 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1531,7 +1531,16 @@ class shader_core_config : public core_config { // Jin: concurrent kernel on sm bool gpgpu_concurrent_kernel_sm; - bool adpative_volta_cache_config; + bool perfect_inst_const_cache; + unsigned inst_fetch_throughput; + unsigned reg_file_port_throughput; + + char* trace_opcode_latency_initiation_int; + char* trace_opcode_latency_initiation_sp; + char* trace_opcode_latency_initiation_dp; + char* trace_opcode_latency_initiation_sfu; + char* trace_opcode_latency_initiation_tensor; + }; struct shader_core_stats_pod { @@ -2053,10 +2062,8 @@ class shader_core_ctx : public core_t { } int test_res_bus(int latency); - void init_warps(unsigned cta_id, unsigned start_thread, unsigned end_thread, - unsigned ctaid, int cta_size, unsigned kernel_id); - virtual void checkExecutionStatusAndUpdate(warp_inst_t &inst, unsigned t, - unsigned tid); + void init_warps(unsigned cta_id, unsigned start_thread, unsigned end_thread,unsigned ctaid, int cta_size, kernel_info_t &kernel); + virtual void checkExecutionStatusAndUpdate(warp_inst_t &inst, unsigned t, unsigned tid); address_type next_pc(int tid) const; void fetch(); void register_cta_thread_exit(unsigned cta_num, kernel_info_t *kernel); @@ -2070,7 +2077,7 @@ class shader_core_ctx : public core_t { void issue_warp(register_set &warp, const warp_inst_t *pI, const active_mask_t &active_mask, unsigned warp_id, unsigned sch_id); - void func_exec_inst(warp_inst_t &inst); + virtual void func_exec_inst( warp_inst_t &inst ); // Returns numbers of addresses in translated_addrs unsigned translate_local_memaddr(address_type localaddr, unsigned tid, @@ -2168,6 +2175,8 @@ class shader_core_ctx : public core_t { unsigned int m_occupied_ctas; std::bitset<MAX_THREAD_PER_SM> m_occupied_hwtid; std::map<unsigned int, unsigned int> m_occupied_cta_to_hwtid; + + friend class trace_shader_core_ctx; }; class simt_core_cluster { diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index b7b7f34..d6d0b23 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -232,6 +232,37 @@ gpgpu_sim *gpgpu_context::gpgpu_ptx_sim_init_perf() { return the_gpgpusim->g_the_gpu; } +gpgpu_sim *gpgpu_context::gpgpu_trace_sim_init_perf(int argc, const char *argv[]) +{ + srand(1); + print_splash(); + func_sim->read_sim_environment_variables(); + ptx_parser->read_parser_environment_variables(); + option_parser_t opp = option_parser_create(); + + ptx_reg_options(opp); + func_sim->ptx_opcocde_latency_options(opp); + + icnt_reg_options(opp); + the_gpgpusim->g_the_gpu_config = new gpgpu_sim_config(this); + the_gpgpusim->g_the_gpu_config->reg_options(opp); // register GPU microrachitecture options + + option_parser_cmdline(opp, argc, argv); // parse configuration options + fprintf(stdout, "GPGPU-Sim: Configuration options:\n\n"); + option_parser_print(opp, stdout); + // Set the Numeric locale to a standard locale where a decimal point is a "dot" not a "comma" + // so it does the parsing correctly independent of the system environment variables + assert(setlocale(LC_NUMERIC,"C")); + the_gpgpusim->g_the_gpu_config->init(); + + the_gpgpusim->g_the_gpu = new gpgpu_sim(*(the_gpgpusim->g_the_gpu_config), this); + the_gpgpusim->g_stream_manager = new stream_manager((the_gpgpusim->g_the_gpu), func_sim->g_cuda_launch_blocking); + + the_gpgpusim->g_simulation_starttime = time((time_t *)NULL); + + return the_gpgpusim->g_the_gpu; +} + void gpgpu_context::start_sim_thread(int api) { if (the_gpgpusim->g_sim_done) { the_gpgpusim->g_sim_done = false; diff --git a/src/trace-driven/ISA_Def/kepler_opcode.h b/src/trace-driven/ISA_Def/kepler_opcode.h new file mode 100644 index 0000000..675ea6c --- /dev/null +++ b/src/trace-driven/ISA_Def/kepler_opcode.h @@ -0,0 +1,149 @@ +//developed by Mahmoud Khairy, Purdue Univ + +#ifndef KEPLER_OPCODE_H +#define KEPLER_OPCODE_H + +#include "trace_opcode.h" +#include <unordered_map> +#include <string> + +#define KEPLER_BINART_VERSION 35 +#define KEPLER_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000 + +//TO DO: moving this to a yml or def files + +///Kepler ISA +//see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html +static const std::unordered_map<std::string,OpcodeChar> Kepler_OpcodeMap = { + //Floating Point 32 Instructions + {"FFMA", OpcodeChar(OP_FFMA, SP_OP)}, + {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)}, + {"FADD", OpcodeChar(OP_FADD, SP_OP)}, + {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)}, + {"FCMP", OpcodeChar(OP_FCMP, SP_OP)}, + {"FMUL", OpcodeChar(OP_FMUL, SP_OP)}, + {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)}, + {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)}, + {"FSWZ", OpcodeChar(OP_FSWZ, SP_OP)}, + {"FSET", OpcodeChar(OP_FSET, SP_OP)}, + {"FSETP", OpcodeChar(OP_FSETP, SP_OP)}, + {"FCHK", OpcodeChar(OP_FCHK, SP_OP)}, + {"RRO", OpcodeChar(OP_RRO, SP_OP)}, + //SFU + {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)}, + + + //Double Point Instructions + {"DFMA", OpcodeChar(OP_DFMA, DP_OP)}, + {"DADD", OpcodeChar(OP_DADD, DP_OP)}, + {"DMUL", OpcodeChar(OP_DMUL, DP_OP)}, + {"DMNMX", OpcodeChar(OP_DMNMX, DP_OP)}, + {"DSET", OpcodeChar(OP_DSET, DP_OP)}, + {"DSETP", OpcodeChar(OP_DSETP, DP_OP)}, + + //Integer Instructions + {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)}, + {"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)}, + {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)}, + {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)}, + {"IADD", OpcodeChar(OP_IADD, INTP_OP)}, + {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)}, + {"ISUB", OpcodeChar(OP_ISUB, INTP_OP)}, + {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)}, + {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)}, + {"ISAD", OpcodeChar(OP_ISAD, INTP_OP)}, + {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)}, + {"BFE", OpcodeChar(OP_BFE, INTP_OP)}, + {"BFI", OpcodeChar(OP_BFI, INTP_OP)}, + {"SHR", OpcodeChar(OP_SHR, INTP_OP)}, + {"SHL", OpcodeChar(OP_SHL, INTP_OP)}, + {"SHF", OpcodeChar(OP_SHF, INTP_OP)}, + {"LOP", OpcodeChar(OP_LOP, INTP_OP)}, + {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)}, + {"FLO", OpcodeChar(OP_FLO, INTP_OP)}, + {"ISET", OpcodeChar(OP_ISET, INTP_OP)}, + {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)}, + {"ICMP", OpcodeChar(OP_ICMP, INTP_OP)}, + {"POPC", OpcodeChar(OP_POPC, INTP_OP)}, + + //Conversion Instructions + {"F2F", OpcodeChar(OP_F2F, ALU_OP)}, + {"F2I", OpcodeChar(OP_F2I, ALU_OP)}, + {"I2F", OpcodeChar(OP_I2F, ALU_OP)}, + {"I2I", OpcodeChar(OP_I2I, ALU_OP)}, + + //Movement Instructions + {"MOV", OpcodeChar(OP_MOV, ALU_OP)}, + {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)}, + {"SEL", OpcodeChar(OP_SEL, ALU_OP)}, + {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)}, + {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)}, + + //Predicate Instructions + {"P2R", OpcodeChar(OP_P2R, ALU_OP)}, + {"R2P", OpcodeChar(OP_R2P, ALU_OP)}, + {"CSET", OpcodeChar(OP_CSET, ALU_OP)}, + {"CSETP", OpcodeChar(OP_CSETP, ALU_OP)}, + {"PSET", OpcodeChar(OP_PSET, ALU_OP)}, + {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)}, + + //Texture Instructions + //For now, we ignore texture loads, consider it as ALU_OP + {"TEX", OpcodeChar(OP_TEX, ALU_OP)}, + {"TLD", OpcodeChar(OP_TLD, ALU_OP)}, + {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)}, + {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)}, + + //Load/Store Instructions + //For now, we ignore constant loads, consider it as ALU_OP, TO DO + {"LDC", OpcodeChar(OP_LDC, ALU_OP)}, + //in Kepler, LD is load global so set it to LDG + {"LD", OpcodeChar(OP_LDG, LOAD_OP)}, + {"LDG", OpcodeChar(OP_LDG, LOAD_OP)}, + {"LDL", OpcodeChar(OP_LDL, LOAD_OP)}, + {"LDS", OpcodeChar(OP_LDS, LOAD_OP)}, + {"LDSLK", OpcodeChar(OP_LDSLK, LOAD_OP)}, + {"ST", OpcodeChar(OP_STG, STORE_OP)}, + {"STL", OpcodeChar(OP_STL, STORE_OP)}, + {"STS", OpcodeChar(OP_STS, STORE_OP)}, + {"STSCUL", OpcodeChar(OP_STSCUL, STORE_OP)}, + {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)}, + {"RED", OpcodeChar(OP_RED, STORE_OP)}, + {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)}, + {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)}, + {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)}, + + //surface memory instructions + {"SUCLAMP", OpcodeChar(OP_SUCLAMP, LOAD_OP)}, + {"SUBFM", OpcodeChar(OP_SUBFM, LOAD_OP)}, + {"SUEAU", OpcodeChar(OP_SUEAU, LOAD_OP)}, + {"SULDGA", OpcodeChar(OP_SULDGA, LOAD_OP)}, + {"SUSTGA", OpcodeChar(OP_SUSTGA, STORE_OP)}, + + //Control Instructions + {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)}, + {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)}, + {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)}, + {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)}, + {"CAL", OpcodeChar(OP_CAL, CALL_OPS)}, + {"JCAL", OpcodeChar(OP_JCAL, CALL_OPS)}, + {"RET", OpcodeChar(OP_RET, RET_OPS)}, + {"BRK", OpcodeChar(OP_BRK, RET_OPS)}, + {"CONT", OpcodeChar(OP_CONT, RET_OPS)}, + {"SSY", OpcodeChar(OP_SSY, RET_OPS)}, + {"PBK", OpcodeChar(OP_PBK, RET_OPS)}, + {"PCNT", OpcodeChar(OP_PCNT, RET_OPS)}, + {"PRET", OpcodeChar(OP_PRET, RET_OPS)}, + {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)}, + {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)}, + + //Miscellaneous Instructions + {"NOP", OpcodeChar(OP_NOP, ALU_OP)}, + {"S2R", OpcodeChar(OP_S2R, ALU_OP)}, + {"B2R", OpcodeChar(OP_B2R, ALU_OP)}, + {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)}, + {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)}, +}; + +#endif diff --git a/src/trace-driven/ISA_Def/pascal_opcode.h b/src/trace-driven/ISA_Def/pascal_opcode.h new file mode 100644 index 0000000..66a0841 --- /dev/null +++ b/src/trace-driven/ISA_Def/pascal_opcode.h @@ -0,0 +1,201 @@ +//developed by Mahmoud Khairy, Purdue Univ + +#ifndef PASCAL_OPCODE_H +#define PASCAL_OPCODE_H + +#include "trace_opcode.h" +#include <unordered_map> +#include <string> + +#define PASCAL_TITANX_BINART_VERSION 61 +#define PASCAL_P100_BINART_VERSION 60 + +#define PASCAL_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000 + +//TO DO: moving this to a yml or def files + +///Pascal SM_61 ISA +//see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html +static const std::unordered_map<std::string,OpcodeChar> Pascal_OpcodeMap = { + //Floating Point 32 Instructions + {"FADD", OpcodeChar(OP_FADD, SP_OP)}, + {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)}, + {"FCHK", OpcodeChar(OP_FCHK, SP_OP)}, + {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)}, + {"FFMA", OpcodeChar(OP_FFMA, SP_OP)}, + {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)}, + {"FMUL", OpcodeChar(OP_FMUL, SP_OP)}, + {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)}, + {"FSEL", OpcodeChar(OP_FSEL, SP_OP)}, + {"FSET", OpcodeChar(OP_FSET, SP_OP)}, + {"FSETP", OpcodeChar(OP_FSETP, SP_OP)}, + {"FSWZADD", OpcodeChar(OP_FSWZADD, SP_OP)}, + {"RRO", OpcodeChar(OP_RRO, SP_OP)}, + + //SFU + {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)}, + + //Floating Point 16 Instructions + {"HADD2", OpcodeChar(OP_HADD2, SP_OP)}, + {"HFMA2", OpcodeChar(OP_HFMA2, SP_OP)}, + {"HMUL2", OpcodeChar(OP_HMUL2, SP_OP)}, + {"HSET2", OpcodeChar(OP_HSET2, SP_OP)}, + {"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)}, + + //Double Point Instructions + {"DADD", OpcodeChar(OP_DADD, DP_OP)}, + {"DFMA", OpcodeChar(OP_DFMA, DP_OP)}, + {"DMUL", OpcodeChar(OP_DMUL, DP_OP)}, + {"DSETP", OpcodeChar(OP_DSETP, DP_OP)}, + {"DMNMX", OpcodeChar(OP_DMNMX, DP_OP)}, + {"DSET", OpcodeChar(OP_DSET, DP_OP)}, + + //Integer Instructions + {"BMSK", OpcodeChar(OP_BMSK, INTP_OP)}, + {"BREV", OpcodeChar(OP_BREV, INTP_OP)}, + {"FLO", OpcodeChar(OP_FLO, INTP_OP)}, + {"IABS", OpcodeChar(OP_IABS, INTP_OP)}, + {"IADD", OpcodeChar(OP_IADD, INTP_OP)}, + {"IADD3", OpcodeChar(OP_IADD3, INTP_OP)}, + {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)}, + {"IDP", OpcodeChar(OP_IDP, INTP_OP)}, + {"IDP4A", OpcodeChar(OP_IDP4A, INTP_OP)}, + {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)}, + {"IMMA", OpcodeChar(OP_IMMA, INTP_OP)}, + {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)}, + {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)}, + {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)}, + {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)}, + {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)}, + {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)}, + {"ISET", OpcodeChar(OP_ISET, INTP_OP)}, + {"LEA", OpcodeChar(OP_LEA, INTP_OP)}, + {"LOP", OpcodeChar(OP_LOP, INTP_OP)}, + {"LOP3", OpcodeChar(OP_LOP3, INTP_OP)}, + {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)}, + {"POPC", OpcodeChar(OP_POPC, INTP_OP)}, + {"SHF", OpcodeChar(OP_SHF, INTP_OP)}, + {"SHR", OpcodeChar(OP_SHR, INTP_OP)}, + {"VABSDIFF", OpcodeChar(OP_VABSDIFF, INTP_OP)}, + {"VABSDIFF4", OpcodeChar(OP_VABSDIFF4, INTP_OP)}, + {"BFE", OpcodeChar(OP_BFE, INTP_OP)}, + {"BFI", OpcodeChar(OP_BFI, INTP_OP)}, + {"ICMP", OpcodeChar(OP_ICMP, INTP_OP)}, + {"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)}, + {"SHL", OpcodeChar(OP_SHL, INTP_OP)}, + {"XMAD", OpcodeChar(OP_XMAD, INTP_OP)}, + {"VMNMX", OpcodeChar(OP_VMNMX, INTP_OP)}, + + + //Conversion Instructions + {"F2F", OpcodeChar(OP_F2F, ALU_OP)}, + {"F2I", OpcodeChar(OP_F2I, ALU_OP)}, + {"I2F", OpcodeChar(OP_I2F, ALU_OP)}, + {"I2I", OpcodeChar(OP_I2I, ALU_OP)}, + {"I2IP", OpcodeChar(OP_I2IP, ALU_OP)}, + {"FRND", OpcodeChar(OP_FRND, ALU_OP)}, + + //Movement Instructions + {"MOV", OpcodeChar(OP_MOV, ALU_OP)}, + {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)}, + {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)}, + {"SEL", OpcodeChar(OP_SEL, ALU_OP)}, + {"SGXT", OpcodeChar(OP_SGXT, ALU_OP)}, + {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)}, + + //Predicate Instructions + {"PLOP3", OpcodeChar(OP_PLOP3, ALU_OP)}, + {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)}, + {"P2R", OpcodeChar(OP_P2R, ALU_OP)}, + {"R2P", OpcodeChar(OP_R2P, ALU_OP)}, + {"CSET", OpcodeChar(OP_CSET, ALU_OP)}, + {"CSETP", OpcodeChar(OP_CSETP, ALU_OP)}, + {"PSET", OpcodeChar(OP_PSET, ALU_OP)}, + + + //Load/Store Instructions + {"LD", OpcodeChar(OP_LD, LOAD_OP)}, + //For now, we ignore constant loads, consider it as ALU_OP, TO DO + {"LDC", OpcodeChar(OP_LDC, ALU_OP)}, + {"LDG", OpcodeChar(OP_LDG, LOAD_OP)}, + {"LDL", OpcodeChar(OP_LDL, LOAD_OP)}, + {"LDS", OpcodeChar(OP_LDS, LOAD_OP)}, + {"ST", OpcodeChar(OP_ST, STORE_OP)}, + {"STG", OpcodeChar(OP_STG, STORE_OP)}, + {"STL", OpcodeChar(OP_STL, STORE_OP)}, + {"STS", OpcodeChar(OP_STS, STORE_OP)}, + {"MATCH", OpcodeChar(OP_MATCH, ALU_OP)}, + {"QSPC", OpcodeChar(OP_QSPC, ALU_OP)}, + {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)}, + {"ATOMS", OpcodeChar(OP_ATOMS, STORE_OP)}, + {"ATOMG", OpcodeChar(OP_ATOMG, STORE_OP)}, + {"RED", OpcodeChar(OP_RED, STORE_OP)}, + {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)}, + {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)}, + {"ERRBAR", OpcodeChar(OP_ERRBAR, ALU_OP)}, + {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)}, + {"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)}, + + //Texture Instructions + //For now, we ignore texture loads, consider it as ALU_OP + {"TEX", OpcodeChar(OP_TEX, ALU_OP)}, + {"TLD", OpcodeChar(OP_TLD, ALU_OP)}, + {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)}, + {"TMML", OpcodeChar(OP_TMML, ALU_OP)}, + {"TXD", OpcodeChar(OP_TXD, ALU_OP)}, + {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)}, + {"TEXS", OpcodeChar(OP_TEXS, ALU_OP)}, + {"TLD4S", OpcodeChar(OP_TLD4S, ALU_OP)}, + {"TLDS", OpcodeChar(OP_TLDS, ALU_OP)}, + + //Control Instructions + {"BMOV", OpcodeChar(OP_BMOV, BRANCH_OP)}, + {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)}, + {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)}, + {"BREAK", OpcodeChar(OP_BREAK, BRANCH_OP)}, + {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)}, + {"BSSY", OpcodeChar(OP_BSSY, BRANCH_OP)}, + {"BSYNC", OpcodeChar(OP_BSYNC, BRANCH_OP)}, + {"CALL", OpcodeChar(OP_CALL, CALL_OPS)}, + {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)}, + {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)}, + {"SSY", OpcodeChar(OP_SSY, BRANCH_OP)}, + {"SYNC", OpcodeChar(OP_SYNC, BRANCH_OP)}, + {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)}, + {"KILL", OpcodeChar(OP_KILL, BRANCH_OP)}, + {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, BRANCH_OP)}, + {"RET", OpcodeChar(OP_RET, RET_OPS)}, + {"RPCMOV", OpcodeChar(OP_RPCMOV, BRANCH_OP)}, + {"RTT", OpcodeChar(OP_RTT, RET_OPS)}, + {"WARPSYNC", OpcodeChar(OP_WARPSYNC, BRANCH_OP)}, + {"YIELD", OpcodeChar(OP_YIELD, BRANCH_OP)}, + {"CAL", OpcodeChar(OP_CAL, CALL_OPS)}, + {"JCAL", OpcodeChar(OP_JCAL, CALL_OPS)}, + {"PRET", OpcodeChar(OP_PRET, CALL_OPS)}, + {"BRK", OpcodeChar(OP_BRK, CALL_OPS)}, + {"PBK", OpcodeChar(OP_PBK, CALL_OPS)}, + {"CONT", OpcodeChar(OP_CONT, CALL_OPS)}, + {"PCNT", OpcodeChar(OP_PCNT, CALL_OPS)}, + {"PEXIT", OpcodeChar(OP_PEXIT, CALL_OPS)}, + + //Miscellaneous Instructions + {"B2R", OpcodeChar(OP_B2R, ALU_OP)}, + {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)}, + {"CS2R", OpcodeChar(OP_CS2R, ALU_OP)}, + {"CSMTEST", OpcodeChar(OP_CSMTEST, ALU_OP)}, + {"DEPBAR", OpcodeChar(OP_DEPBAR, ALU_OP)}, + {"GETLMEMBASE", OpcodeChar(OP_GETLMEMBASE, ALU_OP)}, + {"LEPC", OpcodeChar(OP_LEPC ,ALU_OP)}, + {"NOP", OpcodeChar(OP_NOP ,ALU_OP)}, + {"PMTRIG", OpcodeChar(OP_PMTRIG, ALU_OP)}, + {"R2B", OpcodeChar(OP_R2B, ALU_OP)}, + {"S2R", OpcodeChar(OP_S2R, ALU_OP)}, + {"SETCTAID", OpcodeChar(OP_SETCTAID, ALU_OP)}, + {"SETLMEMBASE", OpcodeChar(OP_SETLMEMBASE, ALU_OP)}, + {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)}, + {"VOTE_VTG", OpcodeChar(OP_VOTE_VTG, ALU_OP)}, + +}; + +#endif diff --git a/src/trace-driven/ISA_Def/trace_opcode.h b/src/trace-driven/ISA_Def/trace_opcode.h new file mode 100644 index 0000000..ed147fc --- /dev/null +++ b/src/trace-driven/ISA_Def/trace_opcode.h @@ -0,0 +1,71 @@ +//developed by Mahmoud Khairy, Purdue Univ + +#ifndef TRACE_OPCODE_H +#define TRACE_OPCODE_H + +#include "../../abstract_hardware_model.h" +#include <unordered_map> +#include <string> + + +enum TraceInstrOpcode { + //volta (common insts for others cards as well) + OP_FADD = 1, OP_FADD32I, OP_FCHK, OP_FFMA32I, OP_FFMA, OP_FMNMX, OP_FMUL, OP_FMUL32I, OP_FSEL, OP_FSET, OP_FSETP, + OP_FSWZADD, OP_MUFU, OP_HADD2, OP_HADD2_32I, OP_HFMA2, OP_HFMA2_32I, OP_HMUL2, OP_HMUL2_32I, OP_HSET2, OP_HSETP2, + OP_HMMA, OP_DADD, OP_DFMA, OP_DMUL, OP_DSETP, + OP_BMSK, OP_BREV, OP_FLO, OP_IABS, OP_IADD, OP_IADD3, OP_IADD32I, OP_IDP, OP_IDP4A, OP_IMAD, OP_IMMA, OP_IMNMX, + OP_IMUL, OP_IMUL32I, OP_ISCADD, OP_ISCADD32I, OP_ISETP, OP_LEA, OP_LOP, OP_LOP3, OP_LOP32I, OP_POPC, OP_SHF, OP_SHR, + OP_VABSDIFF, OP_VABSDIFF4, + OP_F2F, OP_F2I, OP_I2F, OP_I2I, OP_I2IP, OP_FRND, OP_MOV, OP_MOV32I, OP_PRMT, OP_SEL, OP_SGXT, OP_SHFL, OP_PLOP3, + OP_PSETP, OP_P2R, OP_R2P, OP_LD, OP_LDC, OP_LDG, OP_LDL, OP_LDS, OP_ST, OP_STG, OP_STL, OP_STS, OP_MATCH, OP_QSPC, + OP_ATOM, OP_ATOMS, OP_ATOMG, OP_RED, OP_CCTL, OP_CCTLL, OP_ERRBAR, OP_MEMBAR, OP_CCTLT, + OP_TEX, OP_TLD, OP_TLD4, + OP_TMML, OP_TXD, OP_TXQ, OP_BMOV, OP_BPT, OP_BRA, OP_BREAK, OP_BRX, OP_BSSY, OP_BSYNC, OP_CALL, OP_EXIT, OP_JMP, OP_JMX, + OP_KILL, OP_NANOSLEEP, OP_RET, OP_RPCMOV, OP_RTT, OP_WARPSYNC, OP_YIELD, OP_B2R, OP_BAR, OP_CS2R, OP_CSMTEST, OP_DEPBAR, + OP_GETLMEMBASE, OP_LEPC, OP_NOP, OP_PMTRIG, OP_R2B, OP_S2R, OP_SETCTAID, OP_SETLMEMBASE, OP_VOTE, OP_VOTE_VTG, + //unique insts for pascal + OP_RRO, OP_DMNMX, OP_DSET, OP_BFE, OP_BFI, OP_ICMP, OP_IMADSP, OP_SHL, OP_XMAD, OP_CSET, OP_CSETP, + OP_TEXS, OP_TLD4S, OP_TLDS, OP_CAL, OP_JCAL, OP_PRET, OP_BRK, OP_PBK, OP_CONT, OP_PCNT, OP_PEXIT, OP_SSY, OP_SYNC, OP_PSET + , OP_VMNMX, OP_ISET, + //unique insts for kepler + OP_FCMP, OP_FSWZ, OP_ISAD, OP_LDSLK, OP_STSCUL, OP_SUCLAMP, OP_SUBFM, OP_SUEAU, OP_SULDGA, OP_SUSTGA, OP_ISUB, + SASS_NUM_OPCODES /* The total number of opcodes. */ +}; +typedef enum TraceInstrOpcode sass_op_type; + +/* +enum uarch_op_t { + NO_OP=-1, + ALU_OP=1, + SFU_OP, + TENSOR_CORE_OP, + DP_OP, + SP_OP, + INTP_OP, + ALU_SFU_OP, + LOAD_OP, + TENSOR_CORE_LOAD_OP, + TENSOR_CORE_STORE_OP, + STORE_OP, + BRANCH_OP, + BARRIER_OP, + MEMORY_BARRIER_OP, + CALL_OPS, + RET_OPS +}; +typedef enum uarch_op_t op_type; + */ + +struct OpcodeChar +{ + OpcodeChar(unsigned m_opcode, unsigned m_opcode_category) { + opcode = m_opcode; + opcode_category = m_opcode_category; + } + unsigned opcode; + unsigned opcode_category; +}; + + +#endif diff --git a/src/trace-driven/ISA_Def/turing_opcode.h b/src/trace-driven/ISA_Def/turing_opcode.h new file mode 100644 index 0000000..4df44d9 --- /dev/null +++ b/src/trace-driven/ISA_Def/turing_opcode.h @@ -0,0 +1,24 @@ +//developed by Mahmoud Khairy, Purdue Univ + +#ifndef TURING_OPCODE_H +#define TURING_OPCODE_H + +#include "trace_opcode.h" +#include <unordered_map> +#include <string> + +//TO DO: moving this to a yml or def files + + +#define TURING_BINART_VERSION 72 + +///Tuing SM_72 ISA +//see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html +static const std::unordered_map<std::string,OpcodeChar> Turing_OpcodeMap = { + +//TO fill + +}; + +#endif diff --git a/src/trace-driven/ISA_Def/volta_opcode.h b/src/trace-driven/ISA_Def/volta_opcode.h new file mode 100644 index 0000000..03d50b7 --- /dev/null +++ b/src/trace-driven/ISA_Def/volta_opcode.h @@ -0,0 +1,175 @@ +//developed by Mahmoud Khairy, Purdue Univ + +#ifndef VOLTA_OPCODE_H +#define VOLTA_OPCODE_H + +#include "trace_opcode.h" +#include <unordered_map> +#include <string> + +#define VOLTA_BINART_VERSION 70 +#define VOLTA_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000 + +//TO DO: moving this to a yml or def files + +///Volta SM_70 ISA +//see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html +static const std::unordered_map<std::string,OpcodeChar> Volta_OpcodeMap = { + //Floating Point 32 Instructions + {"FADD", OpcodeChar(OP_FADD, SP_OP)}, + {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)}, + {"FCHK", OpcodeChar(OP_FCHK, SP_OP)}, + {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)}, + {"FFMA", OpcodeChar(OP_FFMA, SP_OP)}, + {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)}, + {"FMUL", OpcodeChar(OP_FMUL, SP_OP)}, + {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)}, + {"FSEL", OpcodeChar(OP_FSEL, SP_OP)}, + {"FSET", OpcodeChar(OP_FSET, SP_OP)}, + {"FSETP", OpcodeChar(OP_FSETP, SP_OP)}, + {"FSWZADD", OpcodeChar(OP_FSWZADD, SP_OP)}, + //SFU + {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)}, + + //Floating Point 16 Instructions + {"HADD2", OpcodeChar(OP_HADD2, SP_OP)}, + {"HADD2_32I", OpcodeChar(OP_HADD2_32I, SP_OP)}, + {"HFMA2", OpcodeChar(OP_HFMA2, SP_OP)}, + {"HFMA2_32I", OpcodeChar(OP_HFMA2_32I, SP_OP)}, + {"HMUL2", OpcodeChar(OP_HMUL2, SP_OP)}, + {"HMUL2_32I", OpcodeChar(OP_HMUL2_32I, SP_OP)}, + {"HSET2", OpcodeChar(OP_HSET2, SP_OP)}, + {"HSETP2", OpcodeChar(OP_HSETP2, SP_OP)}, + + //Tensor Core Instructions + {"HMMA", OpcodeChar(OP_HMMA, TENSOR_CORE_OP)}, + + //Double Point Instructions + {"DADD", OpcodeChar(OP_DADD, DP_OP)}, + {"DFMA", OpcodeChar(OP_DFMA, DP_OP)}, + {"DMUL", OpcodeChar(OP_DMUL, DP_OP)}, + {"DSETP", OpcodeChar(OP_DSETP, DP_OP)}, + + //Integer Instructions + {"BMSK", OpcodeChar(OP_BMSK, INTP_OP)}, + {"BREV", OpcodeChar(OP_BREV, INTP_OP)}, + {"FLO", OpcodeChar(OP_FLO, INTP_OP)}, + {"IABS", OpcodeChar(OP_IABS, INTP_OP)}, + {"IADD", OpcodeChar(OP_IADD, INTP_OP)}, + {"IADD3", OpcodeChar(OP_IADD3, INTP_OP)}, + {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)}, + {"IDP", OpcodeChar(OP_IDP, INTP_OP)}, + {"IDP4A", OpcodeChar(OP_IDP4A, INTP_OP)}, + {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)}, + {"IMMA", OpcodeChar(OP_IMMA, INTP_OP)}, + {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)}, + {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)}, + {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)}, + {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)}, + {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)}, + {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)}, + {"LEA", OpcodeChar(OP_LEA, INTP_OP)}, + {"LOP", OpcodeChar(OP_LOP, INTP_OP)}, + {"LOP3", OpcodeChar(OP_LOP3, INTP_OP)}, + {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)}, + {"POPC", OpcodeChar(OP_POPC, INTP_OP)}, + {"SHF", OpcodeChar(OP_SHF, INTP_OP)}, + {"SHR", OpcodeChar(OP_SHR, INTP_OP)}, + {"VABSDIFF", OpcodeChar(OP_VABSDIFF, INTP_OP)}, + {"VABSDIFF4", OpcodeChar(OP_VABSDIFF4, INTP_OP)}, + + //Conversion Instructions + {"F2F", OpcodeChar(OP_F2F, ALU_OP)}, + {"F2I", OpcodeChar(OP_F2I, ALU_OP)}, + {"I2F", OpcodeChar(OP_I2F, ALU_OP)}, + {"I2I", OpcodeChar(OP_I2I, ALU_OP)}, + {"I2IP", OpcodeChar(OP_I2IP, ALU_OP)}, + {"FRND", OpcodeChar(OP_FRND, ALU_OP)}, + + //Movement Instructions + {"MOV", OpcodeChar(OP_MOV, ALU_OP)}, + {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)}, + {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)}, + {"SEL", OpcodeChar(OP_SEL, ALU_OP)}, + {"SGXT", OpcodeChar(OP_SGXT, ALU_OP)}, + {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)}, + + //Predicate Instructions + {"PLOP3", OpcodeChar(OP_PLOP3, ALU_OP)}, + {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)}, + {"P2R", OpcodeChar(OP_P2R, ALU_OP)}, + {"R2P", OpcodeChar(OP_R2P, ALU_OP)}, + + //Load/Store Instructions + {"LD", OpcodeChar(OP_LD, LOAD_OP)}, + //For now, we ignore constant loads, consider it as ALU_OP, TO DO + {"LDC", OpcodeChar(OP_LDC, ALU_OP)}, + {"LDG", OpcodeChar(OP_LDG, LOAD_OP)}, + {"LDL", OpcodeChar(OP_LDL, LOAD_OP)}, + {"LDS", OpcodeChar(OP_LDS, LOAD_OP)}, + {"ST", OpcodeChar(OP_ST, STORE_OP)}, + {"STG", OpcodeChar(OP_STG, STORE_OP)}, + {"STL", OpcodeChar(OP_STL, STORE_OP)}, + {"STS", OpcodeChar(OP_STS, STORE_OP)}, + {"MATCH", OpcodeChar(OP_MATCH, ALU_OP)}, + {"QSPC", OpcodeChar(OP_QSPC, ALU_OP)}, + {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)}, + {"ATOMS", OpcodeChar(OP_ATOMS, STORE_OP)}, + {"ATOMG", OpcodeChar(OP_ATOMG, STORE_OP)}, + {"RED", OpcodeChar(OP_RED, STORE_OP)}, + {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)}, + {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)}, + {"ERRBAR", OpcodeChar(OP_ERRBAR, ALU_OP)}, + {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)}, + {"CCTLT", OpcodeChar(OP_CCTLT, ALU_OP)}, + + //Texture Instructions + //For now, we ignore texture loads, consider it as ALU_OP + {"TEX", OpcodeChar(OP_TEX, ALU_OP)}, + {"TLD", OpcodeChar(OP_TLD, ALU_OP)}, + {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)}, + {"TMML", OpcodeChar(OP_TMML, ALU_OP)}, + {"TXD", OpcodeChar(OP_TXD, ALU_OP)}, + {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)}, + + //Control Instructions + {"BMOV", OpcodeChar(OP_BMOV, BRANCH_OP)}, + {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)}, + {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)}, + {"BREAK", OpcodeChar(OP_BREAK, BRANCH_OP)}, + {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)}, + {"BSSY", OpcodeChar(OP_BSSY, BRANCH_OP)}, + {"BSYNC", OpcodeChar(OP_BSYNC, BRANCH_OP)}, + {"CALL", OpcodeChar(OP_CALL, CALL_OPS)}, + {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)}, + {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)}, + {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)}, + {"KILL", OpcodeChar(OP_KILL, BRANCH_OP)}, + {"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, BRANCH_OP)}, + {"RET", OpcodeChar(OP_RET, RET_OPS)}, + {"RPCMOV", OpcodeChar(OP_RPCMOV, BRANCH_OP)}, + {"RTT", OpcodeChar(OP_RTT, RET_OPS)}, + {"WARPSYNC", OpcodeChar(OP_WARPSYNC, BRANCH_OP)}, + {"YIELD", OpcodeChar(OP_YIELD, BRANCH_OP)}, + + //Miscellaneous Instructions + {"B2R", OpcodeChar(OP_B2R, ALU_OP)}, + {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)}, + {"CS2R", OpcodeChar(OP_CS2R, ALU_OP)}, + {"CSMTEST", OpcodeChar(OP_CSMTEST, ALU_OP)}, + {"DEPBAR", OpcodeChar(OP_DEPBAR, ALU_OP)}, + {"GETLMEMBASE", OpcodeChar(OP_GETLMEMBASE, ALU_OP)}, + {"LEPC", OpcodeChar(OP_LEPC ,ALU_OP)}, + {"NOP", OpcodeChar(OP_NOP ,ALU_OP)}, + {"PMTRIG", OpcodeChar(OP_PMTRIG, ALU_OP)}, + {"R2B", OpcodeChar(OP_R2B, ALU_OP)}, + {"S2R", OpcodeChar(OP_S2R, ALU_OP)}, + {"SETCTAID", OpcodeChar(OP_SETCTAID, ALU_OP)}, + {"SETLMEMBASE", OpcodeChar(OP_SETLMEMBASE, ALU_OP)}, + {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)}, + {"VOTE_VTG", OpcodeChar(OP_VOTE_VTG, ALU_OP)}, + +}; + +#endif diff --git a/src/trace-driven/gpgpusim_trace_driven_main.cc b/src/trace-driven/gpgpusim_trace_driven_main.cc new file mode 100644 index 0000000..90dc769 --- /dev/null +++ b/src/trace-driven/gpgpusim_trace_driven_main.cc @@ -0,0 +1,123 @@ +//developed by Mahmoud Khairy, Purdue Univ + +#include <time.h> +#include <stdio.h> +#include <vector> +#include <iostream> +#include <fstream> +#include <string> +#include <sstream> +#include <math.h> + +#include "../abstract_hardware_model.h" +#include "../option_parser.h" +#include "../cuda-sim/cuda-sim.h" +#include "../gpgpu-sim/gpu-sim.h" +#include "../../libcuda/gpgpu_context.h" +#include "trace_driven.h" +#include "ISA_Def/trace_opcode.h" +#include "../gpgpusim_entrypoint.h" + +/* TO DO: + * NOTE: the current version of trace-driven is functionally working fine, + * but we still need to improve traces compression and simulation speed. + * This includes: + * 1- Prefetch concurrent thread that prefetches traces from disk (to not be limited by disk speed) + * 2- traces compression format + * a. cfg format and remove thread/block Id from the head + * b. using zlib library to save in binary format + * + * 3- Efficient memory improvement (save string not objects - parse only 10 in the buffer) + * 4- Seeking capability - thread scheduler (save tb index and warp index info in the traces header) + * 5- Get rid off traces intermediate files - change the tracer + */ + +int main ( int argc, const char **argv ) +{ + + gpgpu_context* m_gpgpu_context = new gpgpu_context(); + gpgpu_sim * m_gpgpu_sim = m_gpgpu_context->gpgpu_trace_sim_init_perf(argc,argv); + m_gpgpu_sim->init(); + + //for each kernel + //load file + //parse and create kernel info + //launch + //while loop till the end of the end kernel execution + //prints stats + + trace_parser tracer(m_gpgpu_sim->get_config().get_traces_filename(), m_gpgpu_sim, m_gpgpu_context); + trace_config config(m_gpgpu_sim); + + std::vector<std::string> commandlist = tracer.parse_kernellist_file(); + bool first_kernel=true; + + for(unsigned i=0; i<commandlist.size(); ++i) { + + trace_kernel_info_t* kernel_info = NULL; + if(commandlist[i].substr(0,6) == "Memcpy") { + + size_t addre, Bcount; + tracer.parse_memcpy_info(commandlist[i], addre, Bcount); + std::cout<<commandlist[i]<<std::endl; + m_gpgpu_sim->perf_memcpy_to_gpu(addre, Bcount); + continue; + } + else { + //skip the first unimportant initialization kernel + if(m_gpgpu_sim->get_config().is_skip_first_kernel() && first_kernel) { + first_kernel = false; + continue; + } + kernel_info = tracer.parse_kernel_info(commandlist[i], &config); + m_gpgpu_sim->launch(kernel_info); + } + + bool active = false; + bool sim_cycles = false; + bool break_limit = false; + + do { + if(!m_gpgpu_sim->active()) + break; + + //performance simulation + if( m_gpgpu_sim->active() ) { + m_gpgpu_sim->cycle(); + sim_cycles = true; + m_gpgpu_sim->deadlock_check(); + }else { + if(m_gpgpu_sim->cycle_insn_cta_max_hit()){ + m_gpgpu_context->the_gpgpusim->g_stream_manager->stop_all_running_kernels(); + break_limit = true; + } + } + + active=m_gpgpu_sim->active() ; + + } while( active ); + + if(kernel_info) { + tracer.kernel_finalizer(kernel_info); + m_gpgpu_sim->print_stats(); + } + + if(sim_cycles) { + m_gpgpu_sim->update_stats(); + m_gpgpu_context->print_simulation_time(); + } + + if(break_limit) { + printf("GPGPU-Sim: ** break due to reaching the maximum cycles (or instructions) **\n"); + fflush(stdout); + exit(1); + } + } + + //we print this message to inform the gpgpu-simulation stats_collect script that we are done + printf("GPGPU-Sim: *** simulation thread exiting ***\n"); + printf("GPGPU-Sim: *** exit detected ***\n"); + + return 1; +} diff --git a/src/trace-driven/trace_driven.cc b/src/trace-driven/trace_driven.cc new file mode 100644 index 0000000..76eb7ca --- /dev/null +++ b/src/trace-driven/trace_driven.cc @@ -0,0 +1,707 @@ +//developed by Mahmoud Khairy, Purdue Univ + +#include <time.h> +#include <stdio.h> +#include <vector> +#include <iostream> +#include <fstream> +#include <string> +#include <sstream> +#include <math.h> +#include <bits/stdc++.h> + +#include "../abstract_hardware_model.h" +#include "../option_parser.h" +#include "../cuda-sim/cuda-sim.h" +#include "../cuda-sim/ptx_ir.h" +#include "../cuda-sim/ptx_parser.h" +#include "../gpgpu-sim/gpu-sim.h" +#include "../../libcuda/gpgpu_context.h" +#include "trace_driven.h" +#include "ISA_Def/trace_opcode.h" +#include "ISA_Def/volta_opcode.h" +#include "ISA_Def/turing_opcode.h" +#include "ISA_Def/pascal_opcode.h" +#include "ISA_Def/kepler_opcode.h" +#include "../gpgpusim_entrypoint.h" + + +bool is_number(const std::string& s) +{ + std::string::const_iterator it = s.begin(); + while (it != s.end() && std::isdigit(*it)) ++it; + return !s.empty() && it == s.end(); +} + +void split(const std::string& str, std::vector<std::string>& cont, char delimi = ' ') +{ + std::stringstream ss(str); + std::string token; + while (std::getline(ss, token, delimi)) { + cont.push_back(token); + } +} + +trace_parser::trace_parser(const char* kernellist_filepath, gpgpu_sim * m_gpgpu_sim, gpgpu_context* m_gpgpu_context) +{ + + this->m_gpgpu_sim = m_gpgpu_sim; + this->m_gpgpu_context = m_gpgpu_context; + kernellist_filename = kernellist_filepath; +} + +std::vector<std::string> trace_parser::parse_kernellist_file() { + + ifs.open(kernellist_filename); + + if (!ifs.is_open()) { + std::cout << "Unable to open file: " <<kernellist_filename<<std::endl; + exit(1); + } + + std::string directory(kernellist_filename); + const size_t last_slash_idx = directory.rfind('/'); + if (std::string::npos != last_slash_idx) + { + directory = directory.substr(0, last_slash_idx); + } + + std::string line, filepath; + std::vector<std::string> kernellist; + while(!ifs.eof()) { + getline(ifs, line); + if(line.empty()) + continue; + else if(line.substr(0,6) == "Memcpy") { + kernellist.push_back(line); + } + else if(line.substr(0,6) == "kernel") { + filepath = directory+"/"+line; + kernellist.push_back(filepath); + } + } + + ifs.close(); + return kernellist; +} + +void trace_parser::parse_memcpy_info(const std::string& memcpy_command, size_t& address, size_t& count) { + std::vector<std::string> params; + split(memcpy_command, params, ','); + assert(params.size() == 3); + std::stringstream ss; + ss.str(params[1]); + ss>>std::hex>>address; + ss.clear(); + ss.str(params[2]); + ss>>std::dec>>count; +} + +trace_kernel_info_t* trace_parser::parse_kernel_info(const std::string& kerneltraces_filepath, trace_config* config) { + + ifs.open(kerneltraces_filepath.c_str()); + + if (!ifs.is_open()) { + std::cout << "Unable to open file: " <<kerneltraces_filepath<<std::endl; + exit(1); + } + + std::cout << "Processing kernel " <<kerneltraces_filepath<<std::endl; + + unsigned grid_dim_x=0, grid_dim_y=0, grid_dim_z=0, tb_dim_x=0, tb_dim_y=0, tb_dim_z=0; + unsigned shmem=0, nregs=0, cuda_stream_id=0, kernel_id=0, binary_verion=0; + std::string line; + std::stringstream ss; + std::string string1, string2; + std::string kernel_name; + + while(!ifs.eof()) { + getline(ifs, line); + + if (line.length() == 0) { + continue; + } + else if(line[0] == '#'){ + //the trace format, ignore this and assume fixed format for now + break; //the begin of the instruction stream + } + else if(line[0] == '-') { + ss.str(line); + ss.ignore(); + ss>>string1>>string2; + if(string1 == "kernel" && string2 == "name") { + const size_t equal_idx = line.find('='); + kernel_name = line.substr(equal_idx+1); + } + else if(string1 == "kernel" && string2 == "id") { + sscanf(line.c_str(), "-kernel id = %d", &kernel_id); + } + else if(string1 == "grid" && string2 == "dim") { + sscanf(line.c_str(), "-grid dim = (%d,%d,%d)", &grid_dim_x, &grid_dim_y, &grid_dim_z); + } + else if (string1 == "block" && string2 == "dim") { + sscanf(line.c_str(), "-block dim = (%d,%d,%d)", &tb_dim_x, &tb_dim_y, &tb_dim_z); + } + else if (string1 == "shmem") { + sscanf(line.c_str(), "-shmem = %d", &shmem); + } + else if (string1 == "nregs") { + sscanf(line.c_str(), "-nregs = %d", &nregs); + } + else if (string1 == "cuda" && string2 == "stream") { + sscanf(line.c_str(), "-cuda stream id = %d", &cuda_stream_id); + } + else if (string1 == "binary" && string2 == "version") { + sscanf(line.c_str(), "-binary version = %d", &binary_verion); + } + std::cout << line << std::endl; + continue; + } + } + + gpgpu_ptx_sim_info info; + info.smem = shmem; + info.regs = nregs; + dim3 gridDim(grid_dim_x, grid_dim_y, grid_dim_z); + dim3 blockDim(tb_dim_x, tb_dim_y, tb_dim_z); + trace_function_info* function_info = new trace_function_info(info, m_gpgpu_context); + function_info->set_name(kernel_name.c_str()); + trace_kernel_info_t* kernel_info = new trace_kernel_info_t(gridDim, blockDim, binary_verion, function_info, &ifs, m_gpgpu_sim, m_gpgpu_context, config); + + return kernel_info; +} + + +void trace_parser::kernel_finalizer(trace_kernel_info_t* kernel_info){ + if (ifs.is_open()) + ifs.close(); + + delete kernel_info->entry(); + delete kernel_info; +} + +const trace_warp_inst_t* trace_shd_warp_t::get_next_inst(){ + if(trace_pc < warp_traces.size()) + { + return &warp_traces[trace_pc++]; + } + else + return NULL; +} + +void trace_shd_warp_t::clear() { + trace_pc=0; + warp_traces.clear(); +} + +//functional_done +bool trace_shd_warp_t::trace_done() { + return trace_pc==(warp_traces.size()); +} + +address_type trace_shd_warp_t::get_start_pc(){ + assert(warp_traces.size() > 0); + return warp_traces[0].pc; +} + +address_type trace_shd_warp_t::get_pc(){ + assert(warp_traces.size() > 0 ); + assert(trace_pc < warp_traces.size()); + return warp_traces[trace_pc].pc; +} + +trace_kernel_info_t::trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m_binary_verion, trace_function_info* m_function_info, std::ifstream* inputstream, gpgpu_sim * gpgpu_sim, gpgpu_context* gpgpu_context, class trace_config* config):kernel_info_t(gridDim, blockDim, m_function_info) { + ifs = inputstream; + m_gpgpu_sim = gpgpu_sim; + m_gpgpu_context = gpgpu_context; + binary_verion = m_binary_verion; + m_tconfig = config; + + //resolve the binary version + if(m_binary_verion == VOLTA_BINART_VERSION) + OpcodeMap = &Volta_OpcodeMap; + else if(m_binary_verion == PASCAL_TITANX_BINART_VERSION || m_binary_verion == PASCAL_P100_BINART_VERSION) + OpcodeMap = &Pascal_OpcodeMap; + else if(m_binary_verion == KEPLER_BINART_VERSION) + OpcodeMap = &Kepler_OpcodeMap; + else if(m_binary_verion == TURING_BINART_VERSION) + OpcodeMap = &Turing_OpcodeMap; + else + assert(0 && "unsupported binary version"); +} + +bool trace_kernel_info_t::get_next_threadblock_traces(std::vector<std::vector<trace_warp_inst_t>*> threadblock_traces) { + + for(unsigned i=0; i<threadblock_traces.size(); ++i) { + threadblock_traces[i]->clear(); + } + + unsigned block_id_x=0, block_id_y=0, block_id_z=0; + unsigned warp_id=0; + unsigned insts_num=0; + + + bool start_of_tb_stream_found = false; + + while(!ifs->eof()) { + std::string line; + std::stringstream ss; + std::string string1, string2; + + getline(*ifs, line); + + if (line.length() == 0) { + continue; + } + else { + ss.str(line); + ss>>string1>>string2; + if (string1 == "#BEGIN_TB") { + if(!start_of_tb_stream_found) + { + start_of_tb_stream_found=true; + } + else + assert(0 && "Parsing error: thread block start before the previous one finish"); + } + else if (string1 == "#END_TB") { + assert(start_of_tb_stream_found); + break; //end of TB stream + } + else if(string1 == "thread" && string2 == "block") { + assert(start_of_tb_stream_found); + sscanf(line.c_str(), "thread block = %d,%d,%d", &block_id_x, &block_id_y, &block_id_z); + std::cout << line << std::endl; + } + else if (string1 == "warp") { + //the start of new warp stream + assert(start_of_tb_stream_found); + sscanf(line.c_str(), "warp = %d", &warp_id); + } + else if (string1 == "insts") { + assert(start_of_tb_stream_found); + sscanf(line.c_str(), "insts = %d", &insts_num); + threadblock_traces[warp_id]->reserve(insts_num); + } + else { + assert(start_of_tb_stream_found); + trace_warp_inst_t inst(m_gpgpu_sim->getShaderCoreConfig(), m_gpgpu_context, m_tconfig); + inst.parse_from_string(line, OpcodeMap); + threadblock_traces[warp_id]->push_back(inst); + } + } + } + + return true; +} + +bool trace_warp_inst_t::check_opcode_contain(const std::vector<std::string>& opcode, std::string param) +{ + for(unsigned i=0; i<opcode.size(); ++i) + if(opcode[i] == param) + return true; + + return false; +} + + + +unsigned trace_warp_inst_t::get_datawidth_from_opcode(const std::vector<std::string>& opcode) +{ + for(unsigned i=0; i<opcode.size(); ++i) { + if(is_number(opcode[i])){ + return (std::stoi(opcode[i],NULL)/8); + } + else if(opcode[i][0] == 'U' && is_number(opcode[i].substr(1))){ + //handle the U* case + unsigned bits; + sscanf(opcode[i].c_str(), "U%u",&bits); + return bits/8; + } + } + + return 4; //default is 4 bytes +} + +bool trace_warp_inst_t::parse_from_string(std::string trace, const std::unordered_map<std::string,OpcodeChar>* OpcodeMap){ + + std::stringstream ss; + ss.str(trace); + + std::string temp; + unsigned threadblock_x=0, threadblock_y=0, threadblock_z=0, warpid_tb=0, sm_id=0, warpid_sm=0; + unsigned long long m_pc=0; + unsigned mask=0; + unsigned reg_dest[4]; + std::string opcode; + unsigned reg_dsts_num=0; + unsigned reg_srcs_num=0; + unsigned reg_srcs[4]; + unsigned mem_width=0; + unsigned long long mem_addresses[warp_size()]; + unsigned address_mode=0; + unsigned long long base_address=0; + int stride=0; + + //Start Parsing + ss>>std::dec>>threadblock_x>>threadblock_y>>threadblock_z>>warpid_tb; + + //ignore core id + //ss>>std::dec>>sm_id>>warpid_sm; + + ss>>std::hex>>m_pc; + ss>>std::hex>>mask; + + std::bitset<MAX_WARP_SIZE> mask_bits(mask); + + ss>>std::dec>>reg_dsts_num; + for(unsigned i=0; i<reg_dsts_num; ++i) { + ss>>std::dec>>temp; + sscanf(temp.c_str(), "R%d", ®_dest[i]); + } + + ss>>opcode; + + ss>>reg_srcs_num; + for(unsigned i=0; i<reg_srcs_num; ++i) { + ss>>temp; + sscanf(temp.c_str(), "R%d", ®_srcs[i]); + + } + + ss>>mem_width; + + if(mem_width > 0) //then it is a memory inst + { + ss>>std::dec>>address_mode; + if(address_mode==0){ + //read addresses one by one from the file + for (int s = 0; s < warp_size(); s++) { + if(mask_bits.test(s)) + ss>>std::hex>>mem_addresses[s]; + else + mem_addresses[s]=0; + } + } + else if(address_mode==1){ + //read addresses as base address and stride + ss>>std::hex>>base_address; + ss>>std::dec>>stride; + bool first_bit1_found=false; + bool last_bit1_found=false; + unsigned long long addra=base_address; + for (int s = 0; s < warp_size(); s++) { + if(mask_bits.test(s) && !first_bit1_found){ + first_bit1_found=true; + mem_addresses[s]=base_address; + } else if(first_bit1_found && !last_bit1_found) { + if(mask_bits.test(s)) { + addra += stride; + mem_addresses[s] = addra; + } else + last_bit1_found=true; + } + else + mem_addresses[s]=0; + } + } + } + //Finish Parsing + //After parsing, fill the inst_t and warp_inst_t params + + //fill active mask + active_mask_t active_mask = mask_bits; + set_active( active_mask ); + + //get the opcode + std::istringstream iss(opcode); + std::vector<std::string> opcode_tokens; + std::string token; + while (std::getline(iss, token, '.')) { + if (!token.empty()) + opcode_tokens.push_back(token); + } + + std::string opcode1 = opcode_tokens[0]; + + //fill and initialize common params + m_decoded = true; + pc = (address_type)m_pc; //we will lose the high 32 bits from casting long to unsigned, it should be okay! + + isize = 16; //starting from MAXWELL isize=16 bytes (including the control bytes) + for(unsigned i=0; i<MAX_OUTPUT_VALUES; i++) { + out[i] = 0; + } + for(unsigned i=0; i<MAX_INPUT_VALUES; i++) { + in[i] = 0; + } + + is_vectorin = 0; + is_vectorout = 0; + ar1 = 0; + ar2 = 0; + memory_op = no_memory_op; + data_size = 0; + op = ALU_OP; + mem_op= NOT_TEX; + + std::unordered_map<std::string,OpcodeChar>::const_iterator it= OpcodeMap->find(opcode1); + if (it != OpcodeMap->end()) { + m_opcode = it->second.opcode; + op = (op_type)(it->second.opcode_category); + } + else { + std::cout<<"ERROR: undefined instruction : "<<opcode<<" Opcode: "<<opcode1<<std::endl; + assert(0 && "undefined instruction"); + } + + //fill regs information + num_regs = reg_srcs_num+reg_dsts_num; + num_operands = num_regs; + outcount=reg_dsts_num; + for(unsigned m=0; m<reg_dsts_num; ++m){ + out[m]=reg_dest[m]+1; //Increment by one because GPGPU-sim starts from R1, while SASS starts from R0 + arch_reg.dst[m]=reg_dest[m]+1; + } + + incount=reg_srcs_num; + for(unsigned m=0; m<reg_srcs_num; ++m){ + in[m]=reg_srcs[m]+1; //Increment by one because GPGPU-sim starts from R1, while SASS starts from R0 + arch_reg.src[m]=reg_srcs[m]+1; + } + //TO DO: handle: vector, store insts have no output, double inst and hmma, and 64 bit address + //remove redundant registers + + //fill latency and initl + m_tconfig->set_latency(op, latency, initiation_interval); + + //fill addresses + if(mem_width > 0) { + for(unsigned i=0; i<warp_size(); ++i) + set_addr(i, mem_addresses[i]); + } + + + //handle special cases and fill memory space + switch(m_opcode){ + case OP_LDG: + case OP_LDL: + assert(mem_width>0); + //Nvbit reports incorrect data width, and we have to parse the opcode to get the correct data width + data_size = get_datawidth_from_opcode(opcode_tokens); + memory_op = memory_load; + cache_op = CACHE_ALL; + if(m_opcode == OP_LDL) + space.set_type(local_space); + else + space.set_type(global_space); + //check the cache scope, if its strong GPU, then bypass L1 + if(check_opcode_contain( opcode_tokens , "STRONG") && check_opcode_contain( opcode_tokens , "GPU")) { + cache_op = CACHE_GLOBAL; + } + break; + case OP_STG: + case OP_STL: + case OP_ATOMG: + case OP_RED: + case OP_ATOM: + assert(mem_width>0); + data_size = get_datawidth_from_opcode(opcode_tokens); + memory_op = memory_store; + cache_op = CACHE_ALL; + if(m_opcode == OP_STL) + space.set_type(local_space); + else + space.set_type(global_space); + + if(m_opcode == OP_ATOMG || m_opcode == OP_ATOM || m_opcode == OP_RED){ + m_isatomic = true; + memory_op = memory_load; + op=LOAD_OP; + cache_op = CACHE_GLOBAL; + + //ATOMIC writes to the first operand, we missed that in the trace so we fixed it here. TO be fixed in tracer + outcount=reg_dsts_num+1; + out[0]=in[0]; //Increment by one because GPGPU-sim starts from R1, while SASS starts from R0 + arch_reg.dst[0]=reg_srcs[0]; + num_regs = reg_srcs_num+reg_dsts_num+1; + num_operands = num_regs; + + } + + break; + case OP_LDS: + case OP_STS: + case OP_ATOMS: + assert(mem_width>0); + data_size = mem_width; + space.set_type(shared_space); + if(m_opcode == OP_ATOMS || m_opcode == OP_LDS) { + //m_isatomic = true; + op=LOAD_OP; + memory_op = memory_load; + } + break; + case OP_ST: + case OP_LD: + //TO DO: set generic load based on the address + //right now, we consider all loads are shared. + assert(mem_width>0); + data_size = get_datawidth_from_opcode(opcode_tokens); + space.set_type(shared_space); + if(m_opcode == OP_LD) + memory_op = memory_load; + else + memory_op = memory_store; + break; + case OP_BAR: + //TO DO: fill this correctly + bar_id = 0; + bar_count = (unsigned)-1; + bar_type = SYNC; + //TO DO + //if bar_type = RED; + //set bar_type + // barrier_type bar_type; + // reduction_type red_type; + break; + case OP_HADD2: + case OP_HADD2_32I: + case OP_HFMA2: + case OP_HFMA2_32I: + case OP_HMUL2_32I: + case OP_HSET2: + case OP_HSETP2: + initiation_interval = initiation_interval/2; //FP16 has 2X throughput than FP32 + break; + default: + break; + } + + return true; +} + +trace_config::trace_config(gpgpu_sim* m_gpgpu_sim){ + + this->m_gpgpu_sim=m_gpgpu_sim; + parse_config(); +} + +void trace_config::parse_config() +{ + + sscanf(m_gpgpu_sim->getShaderCoreConfig()->trace_opcode_latency_initiation_int, "%u,%u", + &int_latency,&int_init); + sscanf(m_gpgpu_sim->getShaderCoreConfig()->trace_opcode_latency_initiation_sp, "%u,%u", + &fp_latency,&fp_init); + sscanf(m_gpgpu_sim->getShaderCoreConfig()->trace_opcode_latency_initiation_dp, "%u,%u", + &dp_latency,&dp_init); + sscanf(m_gpgpu_sim->getShaderCoreConfig()->trace_opcode_latency_initiation_sfu, "%u,%u", + &sfu_latency,&sfu_init); + sscanf(m_gpgpu_sim->getShaderCoreConfig()->trace_opcode_latency_initiation_tensor, "%u,%u", + &tensor_latency,&tensor_init); + +} +void trace_config::set_latency(unsigned category, unsigned& latency, unsigned& initiation_interval) +{ + initiation_interval = latency = 1; + + switch(category){ + case ALU_OP: + case INTP_OP: + case BRANCH_OP: + case CALL_OPS: + case RET_OPS: + latency = int_latency; + initiation_interval = int_init; + break; + case SP_OP: + latency = fp_latency; + initiation_interval = fp_init; + break; + case DP_OP: + latency = dp_latency; + initiation_interval = dp_init; + break; + case SFU_OP: + latency = sfu_latency; + initiation_interval = sfu_init; + break; + case TENSOR_CORE_OP: + latency = tensor_latency; + initiation_interval = tensor_init; + break; + default: + break; + } + +} + +unsigned trace_shader_core_ctx::trace_sim_inc_thread( kernel_info_t &kernel) +{ + + if ( kernel.no_more_ctas_to_run() ) { + return 0; //finished! + } + + if( kernel.more_threads_in_cta() ) { + kernel.increment_thread_id(); + } + + if( !kernel.more_threads_in_cta() ) + kernel.increment_cta_id(); + + return 1; +} + +void trace_shader_core_ctx::init_traces( unsigned start_warp, unsigned end_warp, kernel_info_t &kernel ) { + + std::vector<std::vector<trace_warp_inst_t>*> threadblock_traces; + for (unsigned i = start_warp; i < end_warp; ++i) { + m_trace_warp[i].clear(); + threadblock_traces.push_back(&(m_trace_warp[i].warp_traces)); + } + trace_kernel_info_t& trace_kernel = static_cast<trace_kernel_info_t&> (kernel); + trace_kernel.get_next_threadblock_traces(threadblock_traces); + + //set pc + for (unsigned i = start_warp; i < end_warp; ++i) { + m_warp[i].set_next_pc(m_trace_warp[i].get_start_pc()); + } +} + + +void trace_shader_core_ctx::checkExecutionStatusAndUpdate(warp_inst_t &inst, unsigned t, unsigned tid) +{ + if(inst.isatomic()) + m_warp[inst.warp_id()].inc_n_atomic(); + + if ( inst.op == EXIT_OPS ) { + m_warp[inst.warp_id()].set_completed(t); + } + +} + +void trace_shader_core_ctx::func_exec_inst( warp_inst_t &inst ) +{ + //here, we generate memory acessess and set the status if thread (done?) + if( inst.is_load() || inst.is_store() ) + { + inst.generate_mem_accesses(); + } + for ( unsigned t=0; t < m_warp_size; t++ ) { + if( inst.active(t) ) { + unsigned warpId = inst.warp_id(); + unsigned tid=m_warp_size*warpId+t; + + //virtual function + checkExecutionStatusAndUpdate(inst,t,tid); + } + } + if(m_trace_warp[inst.warp_id()].trace_done() && m_warp[inst.warp_id()].functional_done()) { + m_warp[inst.warp_id()].ibuffer_flush(); + m_barriers.warp_exit( inst.warp_id() ); + } +} + diff --git a/src/trace-driven/trace_driven.h b/src/trace-driven/trace_driven.h new file mode 100644 index 0000000..e9fecd9 --- /dev/null +++ b/src/trace-driven/trace_driven.h @@ -0,0 +1,153 @@ +//developed by Mahmoud Khairy, Purdue Univ + +#include <stdio.h> +#include <stdlib.h> +#include <assert.h> + +#ifndef TRACE_DRIVEN_H +#define TRACE_DRIVEN_H + +#include "../abstract_hardware_model.h" +#include "../gpgpu-sim/shader.h" +#include "ISA_Def/trace_opcode.h" + +class trace_function_info: public function_info { +public: + trace_function_info(const struct gpgpu_ptx_sim_info &info, gpgpu_context* m_gpgpu_context):function_info(0, m_gpgpu_context ) { + m_kernel_info = info; + } + + virtual const struct gpgpu_ptx_sim_info* get_kernel_info () const { + return &m_kernel_info; + } + + virtual const void set_kernel_info (const struct gpgpu_ptx_sim_info &info) { + m_kernel_info = info; + } + + virtual ~trace_function_info() { + + } + +}; + +class trace_warp_inst_t: public warp_inst_t { +public: + + trace_warp_inst_t() { + m_gpgpu_context=NULL; + m_opcode=0; + m_tconfig=NULL; + } + + trace_warp_inst_t(const class core_config *config, gpgpu_context* gpgpu_context, class trace_config* tconfig ):warp_inst_t(config) { + m_gpgpu_context = gpgpu_context; + m_opcode=0; + m_tconfig=tconfig; + } + + bool parse_from_string(std::string trace, const std::unordered_map<std::string,OpcodeChar>* OpcodeMap); + +private: + gpgpu_context* m_gpgpu_context; + class trace_config* m_tconfig; + unsigned m_opcode; + bool check_opcode_contain(const std::vector<std::string>& opcode, std::string param); + unsigned get_datawidth_from_opcode(const std::vector<std::string>& opcode); +}; + +class trace_kernel_info_t: public kernel_info_t { +public: + trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m_binary_verion, trace_function_info* m_function_info, std::ifstream* inputstream, gpgpu_sim * gpgpu_sim, gpgpu_context* gpgpu_context, class trace_config* config); + + bool get_next_threadblock_traces(std::vector<std::vector<trace_warp_inst_t>*> threadblock_traces); + +private: + std::ifstream* ifs; + gpgpu_sim * m_gpgpu_sim; + gpgpu_context* m_gpgpu_context; + trace_config* m_tconfig; + unsigned binary_verion; + const std::unordered_map<std::string,OpcodeChar>* OpcodeMap; + +}; + + +class trace_config { +public: + trace_config(gpgpu_sim * m_gpgpu_sim); + + void set_latency(unsigned category, unsigned& latency, unsigned& initiation_interval); + void parse_config(); + + +private: + + unsigned int_latency, fp_latency, dp_latency, sfu_latency, tensor_latency; + unsigned int_init, fp_init, dp_init, sfu_init, tensor_init; + gpgpu_sim* m_gpgpu_sim; + +}; + +class trace_parser { +public: + trace_parser(const char* kernellist_filepath, gpgpu_sim * m_gpgpu_sim, gpgpu_context* m_gpgpu_context); + + std::vector<std::string> parse_kernellist_file(); + trace_kernel_info_t* parse_kernel_info(const std::string& kerneltraces_filepath, trace_config* config); + void parse_memcpy_info(const std::string& memcpy_command, size_t& add, size_t& count); + + void kernel_finalizer(trace_kernel_info_t* kernel_info); + +private: + + std::string kernellist_filename; + std::ifstream ifs; + gpgpu_sim * m_gpgpu_sim; + gpgpu_context* m_gpgpu_context; + +}; + +class trace_shd_warp_t { +public: + trace_shd_warp_t() { + trace_pc=0; + } + + std::vector<trace_warp_inst_t> warp_traces; + const trace_warp_inst_t* get_next_inst(); + void clear(); + bool trace_done(); + address_type get_start_pc(); + address_type get_pc(); + +private: + unsigned trace_pc; + +}; + +class trace_shader_core_ctx: public shader_core_ctx { +public: + trace_shader_core_ctx(class gpgpu_sim *gpu, + class simt_core_cluster *cluster, + unsigned shader_id, + unsigned tpc_id, + const shader_core_config *config, + const memory_config *mem_config, + shader_core_stats *stats):shader_core_ctx(gpu, cluster, shader_id, tpc_id, config, mem_config, stats) { + + m_trace_warp.resize(get_config()->max_warps_per_shader); + } + + virtual void checkExecutionStatusAndUpdate(warp_inst_t &inst, unsigned t, unsigned tid); + void init_traces( unsigned start_warp, unsigned end_warp, kernel_info_t &kernel ); + unsigned trace_sim_inc_thread( kernel_info_t &kernel); + virtual void func_exec_inst( warp_inst_t &inst ); + friend class shader_core_ctx; + +private: + std::vector<trace_shd_warp_t> m_trace_warp; + +}; + +#endif |