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2021-05-18dirty counter added. NO increamenting yetJRPAN
2021-05-18Merge pull request #12 from barnes88/sub_core_develmkhairy
sub_core_model operand collector unit partitioning
2021-05-17specialized unit get_ready() was missing subcoreAaron Barnes
2021-05-13Merge pull request #13 from JRPan/fix-config-parserTim Rogers
fix adaptive cache cfg option parsing data type
2021-05-13fix adaptive cache cfg option parsing data typeJRPAN
2021-05-13rm old dirs in format-code.shAaron Barnes
2021-05-13run changes through clang-formatAaron Barnes
2021-05-13specialized unit should be partitioned tooAaron Barnes
2021-05-12rm unnecessary instr getAaron Barnes
2021-05-12remove printsAaron Barnes
2021-05-12fix prints / segfaultAaron M Barnes
2021-05-11fix print, move simd::issue() impl to .cc fileAaron M Barnes
2021-05-11issue function needed to be constrainedAaron Barnes
2021-05-11add prints for ex issue validationAaron M Barnes
2021-05-11minor fixes, pure virtual callsAaron M Barnes
2021-05-11Merge branch 'sub_core_devel' of github.com:barnes88/gpgpu-sim_distribution ↵Aaron Barnes
into sub_core_devel
2021-05-11partition issue() in the shader execute stageAaron Barnes
2021-05-10cleanup find_readyAaron M Barnes
2021-05-10more cleanupAaron M Barnes
2021-05-10clean up redundant method argsAaron Barnes
2021-05-10fix assertAaron Barnes
2021-05-10move reg_id calc to cu object initAaron Barnes
2021-05-10need at least 1 cu per sched for sub_core model, fix find_ready() reg_idAaron Barnes
2021-05-10remove printsAaron Barnes
2021-05-10dont need du idAaron M Barnes
2021-05-10fix find_ready reg_idAaron Barnes
2021-05-10minor fix accessing duAaron M Barnes
2021-05-10sub core model dispatches only to assigned exec pipelinesAaron Barnes
2021-05-09validated collector unit partitioning based on schedulerAaron M Barnes
2021-05-09useful print statementAaron M Barnes
2021-05-09minor fixesAaron M Barnes
2021-05-09parition CU allocation, add printsAaron Barnes
2021-03-25change the L1 cache policy based on recent ubenchMahmoud Khairy A. Abdallah
2021-03-25change the L1 cache policy to be on-miss based on recent ubenchMahmoud Khairy A. Abdallah
2021-02-25Merge branch 'dev' of https://github.com/accel-sim/gpgpu-sim_distribution ↵Mahmoud Khairy A. Abdallah
into HEAD
2021-02-25adding new RTX 3070 configMahmoud Khairy A. Abdallah
2021-02-19Merge pull request #9 from JRPan/fix-cache-hashmkhairy
Fix cache hash function and renaming
2021-02-17fix hash funcitonJRPAN
2021-02-16Merge pull request #7 from JRPan/fix-was_writeback_sentmkhairy
bug fix was_writeback_sent()
2021-02-15bug fix was_writeback_sentJRPAN
2021-01-28Merge branch 'dev' of https://github.com/accel-sim/gpgpu-sim_distribution ↵Mahmoud Khairy A. Abdallah
into HEAD
2021-01-27Merge pull request #5 from allencho1222/patch-2Tim Rogers
do not truncate 32 MSB bits of the memory address
2021-01-27Merge pull request #4 from allencho1222/patch-1Tim Rogers
change address type into ull
2020-11-22Merge pull request #6 from JRPan/add_mshrmkhairy
added MSHR_HIT
2020-11-15added MSHR_HITJRPAN
2020-11-09do not truncate 32 MSB bits of the memory addressallen
2020-11-09change address type into ullallen
2020-10-26Merge pull request #3 from gvoskuilen/devmkhairy
Fix for bugs in lazy write handling
2020-10-26Fix for bugs in lazy write handlingGwen
2020-10-18Merge pull request #202 from accel-sim/devTor Aamodt
slight change to support trace-driven split
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