| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-08-05 | Added ptx_warp_info to know how many threads within a warp have executed | sspenst | |
| 2016-08-05 | bsmad gives the correct output in the small cases I have tried, still need ↵ | sspenst | |
| to complete the TODOs noted in bsmad_impl | |||
| 2016-08-04 | A thread executing BSMAD is now able to access information from all threads ↵ | sspenst | |
| in its warp | |||
| 2016-07-11 | Changed sst return value to be the address instead of index offset | sspenst | |
| 2016-07-11 | Reverted the previous commit to add a cleaner way of getting NUM_THREADS. ↵ | sspenst | |
| Now, sst_impl doesn't functionally execute on the last indexed element of an array, but instead on the actual last thread that executes | |||
| 2016-07-08 | Made gridDim and blockDim global variables so that they can be accessed from ↵ | sspenst | |
| sst_impl | |||
| 2016-07-08 | SST should now properly simulate the barrier operation | sspenst | |
| 2016-07-07 | sst_impl cleanup | sspenst | |
| 2016-07-07 | Indices are now stored corresponding to values. SST now returns the number ↵ | sspenst | |
| of elements instead of the device memory address | |||
| 2016-07-07 | SST instruction now returns the end address of the new sparse array | sspenst | |
| 2016-07-07 | SST instruction now updates the original array instead of storing the result ↵ | sspenst | |
| in sstarr memory | |||
| 2016-07-07 | Rough implementation of the SST instruction. It squeezes out the zeros that ↵ | sspenst | |
| are in the sstarr memory and writes the data back into sstarr memory. | |||
| 2016-07-06 | Added the ability to load from sstarr memory after data has been stored in it | sspenst | |
| 2016-07-06 | Added sstarr memory, which works the same as shared memory | sspenst | |
| 2016-07-05 | Slight addition to the parser for CPTX aesthetics. You now begin and end ↵ | sspenst | |
| your custom inserted PTX with CPTX_BEGIN and CPTX_END, respectively. | |||
| 2016-07-04 | Initial SST recognition from PTX parser | sspenst | |
| 2016-07-04 | Restored madp instruction. | speverel | |
| 2016-07-04 | Reverted part of the previous commit so that our new changes related to DNNs ↵ | sspenst | |
| can be done in a different branch | |||
| 2016-06-16 | Added the ability to inject arbitrary PTX instructions. ↵ | speverel | |
| This will be used to add custom instructions in the future; the imaginary instructions 'spr' and 'ama' have been added as samples. | |||
| 2016-06-13 | If ptxas notices any duplicate errors, they now automatically get resolved ↵ | sspenst | |
| and the program continues with the duplicate function/variable declarations removed. | |||
| 2016-06-10 | Vastly improved runtime by relating symbol tables to file names | sspenst | |
| 2016-06-09 | Merge branch 'dev' of https://github.com/sspenst/gpgpu-sim_distribution into dev | speverel | |
| 2016-06-09 | Modified runtime API to support synchronization with the null stream. | speverel | |
| 2016-06-09 | Forgot to add a return value | sspenst | |
| 2016-06-09 | Added a basic implementation of cudaStreamCreateWithFlags | sspenst | |
| 2016-06-07 | Updated the PTX section merging to be able to deal with multiple identifiers | sspenst | |
| 2016-06-07 | The ptx parser now recognizes the NC option for ld.global, however this ↵ | sspenst | |
| option is not actually implemented | |||
| 2016-06-07 | Added support for cudaMemcpyDefault flag in cudaMemcpy. Also increased the ↵ | speverel | |
| maximum allowable memory to 2GB and the compute version to 5.2. | |||
| 2016-06-06 | Added support for BFE (Bit field extract) instruction. | speverel | |
| 2016-06-03 | Merge branch 'dev' of https://github.com/sspenst/gpgpu-sim_distribution into dev | speverel | |
| 2016-06-03 | Added support for %laneid SFR. Also added a notice clarifying that power ↵ | speverel | |
| modeling for GTX750Ti is currently completely untested and should not be considered supported. | |||
| 2016-06-03 | Added mergeSectionList to combine any PTX files that remain after pruning ↵ | sspenst | |
| into a single file. | |||
| 2016-06-02 | Updated parser and config file to support compute versions up to 5.2. Full ↵ | speverel | |
| support is NOT claimed; however, it has been tested to work on a number of CUDA version 7.5 benchmarks such as matrix multiply and simpleMultiGPU. | |||
| 2016-06-02 | Merge pull request #1 from speverel/dev | speverel | |
| Dev | |||
| 2016-06-02 | Merge branch 'dev' of github.com:speverel/gpgpu-sim_distribution into dev | sspenst | |
| 2016-06-02 | Added handling of .cc option for arithmetic instructions. NOTE: Only made ↵ | speverel | |
| changes to parse instructions. Carry functionality NOT fully implemented; .cc instructions function like their unmodified ueqivelents. Also modified GTX750Ti config to model L1 data cache as simply not being used for global loads (instead of not existing at all). Changed ptxinfo parsing to avoid crashing when info includes texture information. | |||
| 2016-06-02 | Merge pull request #20 from sspenst/dev | gpgpu-sim | |
| merged Scott's commits from p4 regarding the GeForceGTX750Ti configuration files | |||
| 2016-06-02 | Added handling of .cc option for arithmetic instructions. NOTE: Only made ↵ | speverel | |
| changes to parse instructions. Carry functionality NOT fully implemented; .cc instructions function like their unmodified ueqivelents. Also modified GTX750Ti config to model L1 data cache as simply not being used for global loads (instead of not existing at all). Changed ptxinfo parsing to avoid crashing when info includes texture information. | |||
| 2016-06-02 | Made additional improvements to Maxwell correlation in config file such as ↵ | Scott Peverelle | |
| merger of L1/Texture cache. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21837] | |||
| 2016-06-02 | Tweaked Maxwell config to improve correspondence in a number of areas; clock ↵ | Scott Peverelle | |
| speed, DRAM bus width, L2 cache size etc. Adjusted parse_and_compare to match new clock frequency as per config file. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21818] | |||
| 2016-06-02 | Modified config files to better represent Maxwell architecture; ↵ | Scott Peverelle | |
| specifically, changed the number of clusters, controllers, and interconnect nodes. Also modified parse_and_compare to fix an occasional division by zero bug. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21812] | |||
| 2016-06-02 | GeForceGTX750Ti correlation setup. Modified config file to reflect GTX750Ti ↵ | Scott Peverelle | |
| architecture. Modified shader.h to allow for larger CTA per warp, to accomodate Maxwell specs. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21798] | |||
| 2016-06-02 | Branch of GTX480 configs for Maxwell board | Scott Peverelle | |
| [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21797] | |||
| 2016-06-01 | Added new GTX750Ti config files. | speverel | |
| 2016-06-01 | Added GTX750Ti config files. Also modified shader.h to support larger number ↵ | speverel | |
| of warps per CTA (64), which is necessary for Maxwell boards like the GTX750Ti. | |||
| 2016-05-16 | Merge pull request #17 from ElTantawy/dev | gpgpu-sim | |
| Initial support for 7.5 - tested on simple sdk benchmaks (e.g., template, vectorAdd, ...) | |||
| 2016-05-15 | fixing the credits | Ahmed ElTantawy | |
| 2016-05-15 | Crediting lonestartGPU in the CHANGES for their help in CUDA 5.5 support | Ahmed ElTantawy | |
| 2016-05-15 | updating CHANGES | Ahmed ElTantawy | |
| 2016-05-13 | changed gpgpu_ptxinfo_load_from_string definition for Ahmed | sspenst | |
 |
index : weft | |
| CPEN 511 Project - Weft: Improving SIMD Utilization through MIMD-like Co-issue and Thread Compaction | Davit Grigoryan |
| summaryrefslogtreecommitdiff |