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Signed-off-by: Mengchi Zhang <[email protected]>
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Signed-off-by: Mengchi Zhang <[email protected]>
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https://github.rcac.purdue.edu/abdallm/gpgpu-sim_distribution into dev-purdue-integration
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1- round robin inst issue for warp multiple schedulers
2- add sector mask in the memory request (to bused later for L2 sector cache)
3- Adding Fermi coalescer
4- Ensure different exen units are used in dual_issue mode
5- Report how many dual_issue happened
6- Adding oldest_first scheduler
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shfl instruction implemented
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Initial support of CUDA Dynamic Parallelism on GPGPUSim
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call.uni in reconvergence
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maximum allowable memory to 2GB and the compute version to 5.2.
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18452]
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http://www.gpgpu-sim.org/bugs/show_bug.cgi?id=81
Review ID: 173001
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18179]
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for specific caches.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16683]
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still caching data from local memory space.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16601]
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Also changed some initialization code when cores are created in both the funcational and perfromance simulator
review:3001 lgtm:5
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16506]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16495]
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Review ID:32001
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16205]
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even if flushing L1 cache between kernels option is not set
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15834]
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L1 Cache and Shared Memory configurations across kernels. The support
enable the user to specify two more configurations (Preferred L1) or
(Preferred Shared Memory) besides the default config. If the
cudaFuncSetCacheConfig API is used to set the cache configuration
of a specific kernel to either of these configuration (cudaFuncCachePreferShared,
cudaFuncCachePreferL1), the simulator will change the cache configuration
at kernel launch accordingly, if there is no alternative configurations
provided to the simulator it will use the default configurations with a
warning message display
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15816]
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that categorize access by their access type (global memory read/write, local memory read/write, instruction read, ... etc.).
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15784]
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//depot/gpgpu_sim_research/fermi_locality/...
to //depot/gpgpu_sim_research/fermi/...
Adding in some protected constructors to the core cache classes.
This allows us to customize caches (for example having them use a custom tag array) more easily.
Also I made the in-class tag_array object in the baseline_cache into a pointer. This allows derived classes to easily create custom tag arrays.
I think in general, class extendibility is increased when pointers are used instead of in-object storage.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15223]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14789]
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//depot/gpgpu_sim_research/fermi_power/distribution/...
to //depot/gpgpu_sim_research/fermi/distribution/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14554]
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Now the two configs will feature 32-bank shared memory with a more flexible broadcast mechanism.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14509]
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replication, implemented write allocate / write back policies in L2 cache, added configurable parameters in gpgpusim.config ("W" = Write Allocate, "N" = No write allocate -> "P" = Private, "S" = shared), modified the cache configuration lines to always be separated by ":" instead of ":" and ",", and modified L1 and L2 data cache to be "Write Back" caches instead of "Read Only".
Still need to implement Ahmed's sectored cache implementation.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14081]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14067]
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Adding support for the floating point input coordinate, and handling of out-of-bound coordinates.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13959]
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bug 18 (external) for detail. The blocked SDK benchmarks are still not working due to mismatch of texture element layout in memory between real GPU and GPGPU-Sim.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13933]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13918]
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Experimental library support (diff abstract_hardware_model.cc) (currently broken because of undocumented cudaGetExportTable function in the cuda rt api)
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13793]
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- Now there is only one macro for all use of unordered_map in the code.
- Moving all instances of gcc/cuda version detection into a single file.
- Adding a warning when the fallback is triggered.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13542]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13535]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13519]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13435]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13410]
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callp_imp using a core_t function, thus moving the querying function into the abstract model of the core instead of shader_core_ctx which represents the performance mode. This code simplify the querying and also avoid the unnecessary calling hierarchy that was used.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13375]
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A bit of cleanup
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12627]
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Right now this doesn't cause any trouble becaue increment_thread_id guarantees that this particular part of the condition is never false (in correct operation)
Normal kernel configuration have the z dimention smaller than the x dimention which causes it to be always true, but with a weird configuration, this is a potential place for failure.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12357]
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. the option -gpgpu_ptx_save_converted_ptxplus allows keeping the ptxplus file
. the option -gpgpu_keep allows keeping intermediate files used to communicate with other programs (e.g. cuobjdump)
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12304]
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1. A configurable number of functional units within each SM
2. A configurable pipeline widths (i.e. Issue width, writeback width ...).
Merging
//depot/gpgpu_sim_research/fermi_replay/distribution/src/...
to //depot/gpgpu_sim_research/fermi/distribution/src/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12091]
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1. Adds support for using cuobjdump for both ptx and ptxplus execution. This has been tested with CUDA 4.0
. Ptxplus is no longer supported through decuda/decuda_to_ptxplus
2. Adds support for converting the SASS output by cuobjdump to ptxplus. This has been tested with CUDA 4.0
. The old path that extracts ptx from cubin files is still preserved
3. Adds a bank group model. (WARNING: memory config has changed, please adapt yours). To disable the bank groups model, set nbkgrp to 1 and tCCDL and tRTPL to 0
Diff the configuration files to learn about how to use those new options.
Merging
//depot/gpgpu_sim_research/fermi-test/distribution/...
to //depot/gpgpu_sim_research/fermi/distribution/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12023]
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