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stalling to send four requests per warp into L1T tag lookup.
If L1T is really 32B blocks (as per Henry's paper), this suggests
banking of L1T needs to be modeled.
Other changes:
1. bug fix in memory access generation for texture/const cache access
2. adding back memory latency measurement for visualizer
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configuration
components of this class.
2. clock memory pipeline no. subwarp times for each shader clock and increase
rob-size for texture cache (trying to improve correlation, currently at 0.9218)
3. start to modify shader stats to add back features for visualizer (warp
divergence distribution kind of working again)
passing cuda 3.1 regression and ptxplus correlation tests
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passing CUDA 3.1 and ptxplus correlation, but correlation still bad (0.62)...
after debugging 1 to get it working with ptxplus, problem is very clear:
shared and constant cache accesses not occuring for operations that combine these with ALU operations.
TODO:
have a "read-operands" stage, which somehow combines operand collector
register reading with shared and const memory accesses...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7895]
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- read only cache model with integrated mshrs (no L1D, yet); new
cache interface should be easily extendable to support texture
cache with latency fifo and separate tag/data arrays, though
this is not yet added (currently tags and data arrays are not
decoupled for texture)
- new partition model using the above
removes all old MSHRs, L1D etc...
passing CUDA 3.1 regression
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7875]
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(and parse it before creating the simulator objects).
2. creating core_config to hold only features of a shader_core that are high
level enough either (a) the functional simulator needs to know about them,
or (b) they affect memory *access* generation.
3. in config files only (so far) separate out notion of write-{through,back},
from notion of when a line is allocated... will use this to distinguish
different types of caches.
passing CUDA 3.1 regression
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7870]
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this gives us a place to stick caches shared among shader cores but
on the shader side of the interconnect... maybe move the clock
boundary code here? after integrating booksim 2 code?
2. added a pending write table to ldst_unit rather than scoreboard
... rationale is that ld/st unit needs to process register writes
once it is done it can notify scoreboard once.
3. re-enabled shared memory delay (use pipeline within ldst_unit)
4. re-enabling operand collector writeback for all instruction types
5. disable MSHRs in this change list
passing CUDA 3.1 regression
next? texture cache, then redo mshrs?
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845]
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2. refactor memory stage into a ld/st function unit
3. refactor memory access generation (moved into warp_inst_t class)
the above should make supporting fermi uarch much easier
passing CUDA 3.1 regression
still need to...
(a) update scoreboard to keep count of outstanding memory requests
and use operand collector for writebacks into register file
(b) add back shared memory pipeline delay
(c) remove use of MSHR's for non-cached global/local accesses
(d) replace texture cache with a split tag/data array pipe
(e) re-implement memory_partition stuff so it makes more sense
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7835]
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1. Moving mem_access_t to abstract_hardware_model and making set (queue) of
accesses part of warp_inst_t. I.e., treat set of accesses as an ISA concept
rather than a hardware organization concept. This is only partly "done"...
logic for computing accesses is still part of shader_core_ctx in this CL.
Given number of warp_inst_t accessors for accessq, now seems like we might even
want to move some memory stage code into warp_inst_t class. How those
accesses make it to memory system is the hardware concept.
2. Making warp_inst_t an explicit arguement of subroutines used in memory stage...
The eventual goal here is (likely) to refactor memory into a hardware block...
i.e., have function units be a class that contains some set of pipeline stages
internally and some set of input/output "ports".
3. Moving accessor functions is_load, is_store; is_const, is_local into class
declaration (where they belong).
4. Removing code for selecting pipeline uarch (might add it back later, but first
want a clean GT200 organization). In particular, removing option to have an
operand collector -- now you MUST have the operand collector.
5. Removing more deadcode from prior changes (fixed delay queue related)
Scripts/configs:
6. Correlation script not printing out exit condition when hardware launch fails
7. Update config files to have proper compute model selected
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7834]
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entirely)
2. some bug fixes for warp_inst_t
3. creating a new class, gpgpu_t, which contains the functional "memory" state visible
to all threads running on a GPU (doing this as part of my continuing effort to hunt
down and eradicate every global variable that is not the top level "the gpu")
4. other misc. changes
Almost passing CUDA 3.1 regression? oclHistogram keeps failing under torque, but
does not fail when run on the command line from the same directory.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7827]
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up to 50%
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7816]
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refactoring: create warp_inst_t that provides notion of a group of scalar instructions
traveling down the pipeline.
delete DWF
delete MIMD
delete warp_tracker
delete old writeback stage, replace it with a stub that just writes back everything
delete old pipeline model
current status: MSHR's need to change to deal with the new structure
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7814]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7811]
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(i'll use "fermi" for more disruptive changes to the pipeline model such
as updating the MSHRs and getting rid of the warp tracker, ripping out DWF, etc...)
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7805]
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(add scoreboard logic from ptxplus branch and modified operand collector
with parallel ALU/SFU pipelines)
passing regressions
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local storage for local param memory)
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parameter spaces (kernel parameters are conceptually different from
function parameters, but PTX only has one .param keyword)
- removing more dead code
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6870]
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a fixed address mapping between shared,local to generic that depends
upon hardware thread context used... might be interesting to explore
tradeoffs at some point)
- remove util.h... we don't need TRUE, FALSE anymore now that
everything is C++
- remove some dead code from shader_decode
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6867]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6829]
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