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AgeCommit message (Collapse)Author
2018-06-13debug printaamir
2018-06-13generic matrix multiply kernel passedaamir
2018-06-11tested all the configuration of mmaaamir
2018-06-11added all the configurationaamir
2018-06-08regression passedAamir Raihan
2018-06-06added profilling xls and changes for regressionaamir
2018-06-05added support for wmma:load_c:f16_typeaamir
2018-06-02mma working for type32_32aamir
2018-06-01added mma & mma_staamir
2018-06-01wmma load workingaamir
2018-05-30adding code for wmma_ld_impl, error at decode spaceaamir
2018-05-30changes for vector operandsaamir
2018-05-27added wmma parsing but execution getting abortedaamir
2018-05-12mma addednegargoli93
2018-05-12commit for eece527projectnegargoli93
2017-09-24Changed how warp level instructions are handled to avoid an assert that is ↵speverel
guaranteed to fail in functional simulation only mode. Hopefully this shouldn't introduce any new issues.
2017-08-17Merged all work on the dev branch since the divergence point into the dnn ↵speverel
branch, incorporating Dynamic Parallelism and many bug fixes.
2016-09-06Merge pull request #30 from sspenst/devgpgpu-sim
shfl instruction implemented
2016-09-05Merge pull request #28 from jwang323/cdp_cleangpgpu-sim
Initial support of CUDA Dynamic Parallelism on GPGPUSim
2016-09-02MOD: Add macros to turn off cuda_device_runtime for CUDA < 5.0Jin Wang
2016-08-25OCDsspenst
2016-08-25Fixed minor shfl bugssspenst
2016-08-24Cleanupsspenst
2016-08-24Added shfl instructionsspenst
2016-08-09Changed bsmad_impl to match Ahmed's output. Added latency and ↵sspenst
initiation_interval numbers for bsmad
2016-08-08Forgot to multiply by the synapsesspenst
2016-08-05Added ptx_warp_info to know how many threads within a warp have executedsspenst
2016-08-05bsmad gives the correct output in the small cases I have tried, still need ↵sspenst
to complete the TODOs noted in bsmad_impl
2016-08-04A thread executing BSMAD is now able to access information from all threads ↵sspenst
in its warp
2016-07-11Changed sst return value to be the address instead of index offsetsspenst
2016-07-11Reverted the previous commit to add a cleaner way of getting NUM_THREADS. ↵sspenst
Now, sst_impl doesn't functionally execute on the last indexed element of an array, but instead on the actual last thread that executes
2016-07-08Made gridDim and blockDim global variables so that they can be accessed from ↵sspenst
sst_impl
2016-07-08SST should now properly simulate the barrier operationsspenst
2016-07-07sst_impl cleanupsspenst
2016-07-07Indices are now stored corresponding to values. SST now returns the number ↵sspenst
of elements instead of the device memory address
2016-07-07SST instruction now returns the end address of the new sparse arraysspenst
2016-07-07SST instruction now updates the original array instead of storing the result ↵sspenst
in sstarr memory
2016-07-07Rough implementation of the SST instruction. It squeezes out the zeros that ↵sspenst
are in the sstarr memory and writes the data back into sstarr memory.
2016-07-06Added sstarr memory, which works the same as shared memorysspenst
2016-07-05ADD: add support for cudaStreamCreateWithFlagsJin Wang
2016-07-05ADD: add cudaGetParameterBufferV2 and add cudaLaunchDeviceV2 implementation. ↵Jin Wang
Kernel launch to stream not yet implemented
2016-07-05ADD: handle child kernel name in mov instruction. ADD: detect call ↵Jin Wang
cudaGetParameterBufferV2 and call cudaLaunchDeviceV2
2016-07-04Initial SST recognition from PTX parsersspenst
2016-07-04Restored madp instruction.speverel
2016-07-04Reverted part of the previous commit so that our new changes related to DNNs ↵sspenst
can be done in a different branch
2016-06-16Added the ability to inject arbitrary PTX instructions. ↵speverel
This will be used to add custom instructions in the future; the imaginary instructions 'spr' and 'ama' have been added as samples.
2016-06-06Added support for BFE (Bit field extract) instruction.speverel
2016-06-02Added handling of .cc option for arithmetic instructions. NOTE: Only made ↵speverel
changes to parse instructions. Carry functionality NOT fully implemented; .cc instructions function like their unmodified ueqivelents. Also modified GTX750Ti config to model L1 data cache as simply not being used for global loads (instead of not existing at all). Changed ptxinfo parsing to avoid crashing when info includes texture information.
2014-08-14This should fix 2.3 regression and may fix others as well.Ahmed El-Shafiey
Remove redudant definition for some tokens which confuses the parser [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18462]
2014-08-14Support for named bariers + bar.red + bar.arrive instructionsAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18452]
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