| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-07-15 | Move s_g_pc_to_insn | Mengchi Zhang | |
| Signed-off-by: Mengchi Zhang <[email protected]> | |||
| 2019-07-15 | Move function_info::sm_next_id | Mengchi Zhang | |
| Signed-off-by: Mengchi Zhang <[email protected]> | |||
| 2019-07-15 | Move g_ptx_cta_info_uid and symbol::sm_next_uid | Mengchi Zhang | |
| Signed-off-by: Mengchi Zhang <[email protected]> | |||
| 2019-07-15 | Move g_num_ptx_inst_uid | Mengchi Zhang | |
| Signed-off-by: Mengchi Zhang <[email protected]> | |||
| 2019-07-15 | Move operand_info::sm_next_uid | Mengchi Zhang | |
| Signed-off-by: Mengchi Zhang <[email protected]> | |||
| 2019-07-10 | Move g_pc_to_finfo | Mengchi Zhang | |
| Signed-off-by: Mengchi Zhang <[email protected]> | |||
| 2019-07-08 | Move opcode_latency_int thus pass gpgpu_context into many classes | Mengchi Zhang | |
| Signed-off-by: Mengchi Zhang <[email protected]> | |||
| 2019-07-07 | g_keep_intermediate_files | Mengchi Zhang | |
| Signed-off-by: Mengchi Zhang <[email protected]> | |||
| 2018-11-09 | resolving merge conflict | Deval Shah | |
| 2018-11-03 | merged with memory subsytem. Regression is passing but tensorcore kernel is ↵ | aamir | |
| stuck in deadlock | |||
| 2018-10-24 | merged tensor-cores code | aamir | |
| 2018-08-16 | Timing model for VCORE | negargoli93 | |
| 2018-08-16 | fix alignment bug in parser, modified ptxjitconfig, minor fixes | Jonathan | |
| 2018-08-07 | implemented prmt and started working on variable precision mul inst | aamir | |
| 2018-08-07 | working fix for deadlock due to operand collector, parser changes to support ↵ | J | |
| culaunchkernel | |||
| 2018-07-22 | added regression and debugged the failing testcase | aamir | |
| 2018-07-18 | added c++filt that works better, param offset dumping, protection for ↵ | Jonathan | |
| failing system calls | |||
| 2018-07-04 | dumps ptx kernels and scripts to launch all kernels | Jonathan | |
| 2018-07-04 | dump and load block and grid size and launch | Jonathan | |
| 2018-06-28 | dumps pointers by accessing global memory | Jonathan | |
| 2018-06-28 | Tests to find conditions that a value is a pointer and new mallocPtr_Size | Jonathan | |
| 2018-06-27 | WIP dump params | Jonathan | |
| 2018-06-21 | WIP adding support for PTX JIT and dumping params to cudaLaunches | Jonathan | |
| 2018-06-14 | bfe bug fix | Jonathan | |
| 2018-06-11 | added all the configuration | aamir | |
| 2018-06-05 | added support for wmma:load_c:f16_type | aamir | |
| 2018-05-31 | mma_ld_impl | aamir | |
| 2018-05-30 | adding code for wmma_ld_impl, error at decode space | aamir | |
| 2018-05-30 | changes for vector operands | aamir | |
| 2018-05-27 | added wmma parsing but execution getting aborted | aamir | |
| 2018-05-12 | commit for eece527project | negargoli93 | |
| 2018-04-22 | Some classes were referred to as a class and a struct (reported as clang ↵ | Nathan Conrad | |
| warnings). This makes these consistent. | |||
| 2018-04-19 | Crash when array pointers are passed | Amruth | |
| 2018-04-14 | solving alignment issue | Amruth | |
| 2018-04-01 | fix regressions -- move call to pre_decode into do_pdom | Tor Aamodt | |
| 2018-03-23 | dynamic pdom analysis at runtime | Amruth | |
| 2017-08-17 | Merged all work on the dev branch since the divergence point into the dnn ↵ | speverel | |
| branch, incorporating Dynamic Parallelism and many bug fixes. | |||
| 2016-09-06 | Merge pull request #30 from sspenst/dev | gpgpu-sim | |
| shfl instruction implemented | |||
| 2016-08-24 | Added shfl instruction | sspenst | |
| 2016-07-06 | Added sstarr memory, which works the same as shared memory | sspenst | |
| 2016-07-06 | BUG: wrong declaration for m_args_aligned_size | Jin Wang | |
| 2016-07-05 | MOD: compute child parameter size | Jin Wang | |
| 2016-07-05 | ADD: add cudaGetParameterBufferV2 and add cudaLaunchDeviceV2 implementation. ↵ | Jin Wang | |
| Kernel launch to stream not yet implemented | |||
| 2016-07-05 | ADD: initial support for instruction group used by CDP | Jin Wang | |
| 2015-03-04 | initial support for CUDA 5.0, 5.5, 6.0 to get template from SDK running | Ahmed ElTantawy | |
| 2014-08-14 | This should fix 2.3 regression and may fix others as well. | Ahmed El-Shafiey | |
| Remove redudant definition for some tokens which confuses the parser [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18462] | |||
| 2014-08-14 | Support for named bariers + bar.red + bar.arrive instructions | Ahmed El-Shafiey | |
| [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18452] | |||
| 2014-08-14 | This should fix the NNC undefined memory locations bug. It turned out that ↵ | Ahmed El-Shafiey | |
| the main problem is in the benchmark code itself. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15537] | |||
| 2014-08-14 | fixing some assignment in the "get_operand_value" function where unsigned ↵ | Ahmed El-Shafiey | |
| were assigned to unions! Also, do proper initialization in the constructors of operand_info, therse among places where valgrind complaining from NNC, but still it is not fixed. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15503] | |||
| 2014-08-14 | Fixing a bug exposed by the fix for bug 42. | Tim Rogers | |
| The "_" "null" register potentially generated by ptx and intentionally generated by ptxplus was being initialized without a type. This caused the parser to think it was not a register. Fix is to allow the parser to think of it as register, but ensure the arch-sim does not by adding a flag indicating that it is special. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15305] | |||
