| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-10-18 | Re-designed cache model: | Tor Aamodt | |
| - read only cache model with integrated mshrs (no L1D, yet); new cache interface should be easily extendable to support texture cache with latency fifo and separate tag/data arrays, though this is not yet added (currently tags and data arrays are not decoupled for texture) - new partition model using the above removes all old MSHRs, L1D etc... passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7875] | |||
| 2010-10-16 | 1. moving address decoding into a class (and out of cache entirely) | Tor Aamodt | |
| 2. moving DRAM timing parameters into memory_config class 3. removing some likely useless statistics 4. other cleaning up of code passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7868] | |||
| 2010-07-15 | creating branch for adding support for CUDA 3.x and Fermi | Tor Aamodt | |
| [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6829] | |||
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index : weft | |
| CPEN 511 Project - Weft: Improving SIMD Utilization through MIMD-like Co-issue and Thread Compaction | Davit Grigoryan |
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