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2018-08-16Timing model for VCOREnegargoli93
2018-07-16fix pipline for tensor_core and change confignegargoli93
2018-06-22No need to change the config file for adding tensor-corenegargoli
2018-06-20Tensor core timing modelnegargoli93
2018-06-08regression passedAamir Raihan
2018-05-30adding code for wmma_ld_impl, error at decode spaceaamir
2018-05-12commit for eece527projectnegargoli93
2017-08-17Merged all work on the dev branch since the divergence point into the dnn ↵speverel
branch, incorporating Dynamic Parallelism and many bug fixes.
2017-07-20Fixing BankGroup Indexing BugMahmoud
2016-09-05MOD: modify Makefile to make CUDART_VERSION available to gpu-sim.ccJin Wang
2016-09-02BUG: concurrent kernel on the same SMX does not work with non-legacy local ↵Jin Wang
memory mapping, turn off by default
2016-09-02MOD: Add macros to turn off cuda_device_runtime for CUDA < 5.0Jin Wang
2016-07-06Added the ability to load from sstarr memory after data has been stored in itsspenst
2016-07-06ADD: add knob to enable CDP in gpgpusim configJin Wang
2016-07-06MOD: modify to new structure name gpgpu_ptx_sim_infoJin Wang
2016-07-06ADD: add kernel launching latency from stream to distributorJin Wang
2016-07-06ADD: print kernel parameter size footprint. BUG: concurrent kernels on same ↵Jin Wang
shader, should use hw_cta_id to store shared mem info
2016-07-06ADD: add stats for kernel launching and complete cycleJin Wang
2016-07-06BUG: concurrent kernels on same SM may occupy warps from running CTAsJin Wang
2016-07-06ADD: add separate cdp latencyJin Wang
2016-07-06ADD: add cdp latencyJin Wang
2016-07-06BUG: for concurrent kernels on same shader, should select kernel from the ↵Jin Wang
distributor directly
2016-07-06ADD: support concurrent kernels on one shaderJin Wang
2016-07-05MOD: schedule one child kernel each cycleJin Wang
2016-07-05BUG: kernels should return to stream if not pushed to concurrent kernel poolJin Wang
2016-07-05MOD: add child kernel stream and scheduling supportJin Wang
2016-06-02GeForceGTX750Ti correlation setup. Modified config file to reflect GTX750Ti ↵Scott Peverelle
architecture. Modified shader.h to allow for larger CTA per warp, to accomodate Maxwell specs. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21798]
2015-06-05Fixing bug with local stats not being reset on call to update_stats. Added ↵Tayler Hetherington
code to remove the trailing newline character from the C++ name de-mangling fix. Also, fixed small bug with previous commit
2015-06-05Fixing bug with max cycle/instruction/cta + bug with C++ name de-mangling ↵Tayler Hetherington
with spaces (e.g., using templates)
2015-03-05Merge pull request #9 from ElTantawy/masterandrewboktor
initial support for CUDA 5.0, 5.5, 6.0 to get template from SDK running
2015-03-04initial support for CUDA 5.0, 5.5, 6.0 to get template from SDK runningAhmed ElTantawy
2015-02-19Adding an assert to make sure we got the right instruction backAndrew Boktor
2015-02-18Making sure that we only service returning cache misses when we have a place ↵Andrew Boktor
to fetch into.
2015-02-18Fixing icache bug where for each miss we also count a hit.Andrew Boktor
2014-10-06Fixed mac build failsMyrice
1. ptx_sim.h::473, stack cannot use incomplete type "operand_info" which is a forward declaration. The reason is underlying implementation of stack is deque which need a complete type. It is better to remove forward declaration by break circular dependence for future fixes. It is also benefit unit test 2. shader.h::1334, this hack cannot pass clang. Clang does not allow a array with not a explicit size. Please fix this hack by correct implementation as soon as possible 3. The default parameter causes clang to fail because it frustrate the compiler. This is still under discussion whether such implementation is correct. http://stackoverflow.com/questions/18313509/default-argument-gcc-vs-clang. I changed it to two constructors to avoid confusion.
2014-08-14-Forcing make clean to remove all automatically generated files by parsers ↵Ahmed El-Shafiey
(should fix regressions). -remove some printfs that were there for debugging [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18480]
2014-08-14Support for named bariers + bar.red + bar.arrive instructionsAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18452]
2014-08-14- Code review 1173001Tayler Hetherington
- Added a parameter to the cache configuration to configure the set index function. - Added a hash set index function to the Fermi L1 data cache for the two default cache sizes, 16KB/48KB with 32/64 sets. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18202]
2014-08-14warning fixes 2nd patch, including comments removal and strict aliasing fixes.leonyu
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17183]
2014-08-14Bug FIX: icnt::full() check using wrong mf sizeDongdong Li
Review ID: 89001 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17086]
2014-08-14Fixing assertion that occurs when L1 cache is configured with ↵Wilson Fung
write-allocation policy. Also added description for the write-allocation fix implemented by Tayler. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16914]
2014-08-14Fixing the intra-partition address calculation so that every set in L2 cache ↵Wilson Fung
is used. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16904]
2014-08-14Refactoring:Dongdong Li
1. Decouple the constructor of interconnect interface 2. Some type changed to unsigned from int Fixed Bug: wrong variable in InterconnectInterface::Busy() Review: 83001 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16877]
2014-08-14Adding the ability to trace all the shader coresTim Rogers
Review ID: 75001 lgtm: 2 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16758]
2014-08-14Intesim2 IntegrationDongdong Li
Details: See Review 80001 https://gpgpu-sim-code-review.appspot.com/80001/ [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16747]
2014-08-14Review 77001: Fixing Writeback/Write allocate hard coded memory_access_types ↵Tayler Hetherington
for specific caches. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16683]
2014-08-14Adding bandwidth modeling to the cache model.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16671]
2014-08-14Lengthened the DRAM return queue size to have enough credits in order to ↵Wilson Fung
keep the DRAM utilized. Also extended the state printing function to print out mem_fetch entries inside the DRAM delay queue. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16639]
2014-08-14Fix for bug 63. bk[i]->n_idle should be bk[j]->n_idle instead.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16635]
2014-08-14Redesigned the memory partition unit to support multiple L2 cache banks per ↵Wilson Fung
partition. Each L2 cache banks has its own connection to the interconnection network to allow L2 bandwidth to scale without increase the number of memory parttiion units. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16613]
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