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2014-08-14Printing out the simulation rateTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11066]
2014-08-14Back out changelist 10951Hadi Jooybar
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10963]
2014-08-14Should be tested.Hadi Jooybar
Does not support sm_20 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10951]
2014-08-14Making the default L2 something saneTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10899]
2014-08-14 - Fixing L1 Texture cache option (I updated the description to look like ↵Ali Bakhoda
the other L1 cache options) and change the default values to the one in Quadro config. The old default value could not even be parsed. - Removed the SIMD width option from the shader_core_pipeline_opt description and default value and Quadro config file. Also changed the default thread count from 256 to 1024. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10897]
2014-08-14Actually fixing the atomic bugTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10756]
2014-08-14Fixing the atomics I broke with the insn count fixTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10754]
2014-08-14Fixing the varying instruction count when the cache configuration changes.Tim Rogers
The problem was 2-fold: 1) If all the lanes hit, we were not incrementing the instruction count since the instruction did not progress to the WB stage, the scoreboard relasing is done in the ldst_unit::cycle function for cache hits. Added code there to increment the instrcution count. 2) Loads were some lanes hit in cache and some lanes do not were not being comepletely counted. Only the lanes sent off to the memory system were being counted because we were setting the warp's active lanes to the access's acrtive lanes.... I am not sure why this code was there... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10737]
2014-08-14Adding a print guard if there is no cacheTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10728]
2014-08-14Integration change. - CL 9058 , adding the l1 cache stat print to the end of ↵Tim Rogers
execution [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10727]
2014-08-14Integration change. CL 8980 - l1 cache stat printTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10726]
2014-08-14Ejection from the interface buffer between interconnet and L2 happens in L2 ↵Ali Bakhoda
clock domain instead of ICNT clock domain. Note: if NOT having an L2 cache is supported in later versions of this branch then this ejection needs to happen in DRAM clock domain when L2 is disabled. cuda regression tests pass [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10501]
2014-08-14Integrated in CL10323 from tm-test branchInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10324]
2014-08-14Fix for Bug 111, integrated in CL10260Inderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10300]
2014-08-14Fix for Bug 110 - integrates in CL 10258 from tm-test branchInderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 10299]
2014-08-14Added read to precharge constraint - negligible effect to DRAM efficiency.Inderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9929]
2014-08-14Fixed the DRAM timing model to add the write-read turn and write-precharge ↵Wilson Fung
delay. Still need to update/validate the Quadro config for this. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9921]
2014-08-14Integration change from CL8943 to fix barrier behaviour.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9884]
2014-08-14fixup some dangling referencesTor Aamodt
update README and CHANGES to hopefully anticipate most basic questions we'll see [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9880]
2014-08-14change copyright notice to include authorsTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
2014-08-14Fixing comment clobber from yesterdayTim Rogers
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9771]
2011-07-07Integration change. Bringing in some changes from mem_divergence that allow ↵Tim Rogers
for multiple configs of the built simulator to exist at one time. Now you no longer have to clean build when changing from debug to release configs it also eliminates the possibility of having a fraken-file where some objects are in debug and some are in release. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9743]
2011-06-29changing copyright to BSDTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
2011-05-28fix for bug 103Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9395]
2011-05-26Another local memory address translation bug fix - it now adds an offset to ↵Inderpreet Singh
prevent writing over symbol global memory and kernel param memory at address 0x0 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9354]
2011-05-25Bug fix for local memory address translation that was made in tm-test branch ↵Inderpreet Singh
but missed in the last changelist for this (fermi) branch. (CL9267) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9307]
2011-05-25Fix bug #100: local memory address translation returns multiple addressesInderpreet Singh
Fix bug #101: Coalescing allows multiple accesses per thread for local memory access This will break atomics which assume at most one thread per mem_fetch. It did not break scoreboard as that logic tracks mem_fetches at warp level, not thread level. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9303]
2011-03-03refactor pipeline stage namesTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8544]
2011-02-01Added configurable schedulers!aturner
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8472]
2011-01-24Adds highly configurable opperand collectoraturner
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8407]
2011-01-20Integration change. Bug fixes from AMD-CMU trace gen branch. Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8389]
2011-01-02integrateTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8312]
2011-01-02integrate bug fix (passes fast regression)Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8310]
2010-12-28- parameter memory and active threads now part of kernel_info_t:Tor Aamodt
Parameters are finalized at kernel launch, which means the contents of parameter memory are initialized. Kernel arguement names have a fixed order, hence same address should be assigned on subsequent kernel launches of same kernel in other streams provided the data size param_t::size of arguments for each kernel launch is identical (an assertion has been added to check this is true). - passing regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8303]
2010-12-28- Checkpointing new support for concurrent kernel execution (CUDA only, not ↵Tor Aamodt
OpenCL) This changelist adds full support for streams supported by a new class, stream_manager and enables concurrent execution of kernels from different streams. - fast_regression.sh fails for simpleMultiCopy, simpleStreams (other tests passing) ** Known issues ** - Kernel parameter passing is not done correctly for concurrent kernel execution (somehow concurrentKernels is not affected by this): the parameters are stored inside function_info, which is shared among parallel kernel launches so that the values passed into the launch are likely to get overwritten if multiple grids are launched in parallel streams. - Statistics are printed out whenever the simulation thread runs out of cuda commands (doesn't make sense to print out when a kernel ends during concurrent kernel execution). This will probably require further tweaking so as to be more compatible with data collection scripts. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8302]
2010-11-30integrate changes (makes code more modular, i would argue)Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8179]
2010-11-29make an explicit read operands stageTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8174]
2010-11-29integrate mask changesTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8170]
2010-11-28bug fix for ptxplus w/ data cache disabledTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8156]
2010-11-28enabling L2 data cache... it is write through, write evict like L1.Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8154]
2010-11-28adding 1st level data cacheTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8153]
2010-10-240.9756 correlation. Set L1T line size to 128 bytes... problem wasTor Aamodt
stalling to send four requests per warp into L1T tag lookup. If L1T is really 32B blocks (as per Henry's paper), this suggests banking of L1T needs to be modeled. Other changes: 1. bug fix in memory access generation for texture/const cache access 2. adding back memory latency measurement for visualizer [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7913]
2010-10-241. updates to .gdbinit fileTor Aamodt
2. update texture to bypass ROP-delay queue... correlation now 0.9592 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7912]
2010-10-241. fix load imbalance issue (CTA's were filling up first core in a cluster ↵Tor Aamodt
before moving to next) this improves correlation to 0.9471 2. update config to use sm_12 if available (goal: seems like BlackScholes has different ipc on hardware from before, this didn't help though) 3. update comparison scripts since no ld_const stuff was removed [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7911]
2010-10-24add back per shader icount tracking for visualizerTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7910]
2010-10-241. adding top level configuration class and making shader and memory ↵Tor Aamodt
configuration components of this class. 2. clock memory pipeline no. subwarp times for each shader clock and increase rob-size for texture cache (trying to improve correlation, currently at 0.9218) 3. start to modify shader stats to add back features for visualizer (warp divergence distribution kind of working again) passing cuda 3.1 regression and ptxplus correlation tests [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909]
2010-10-22enables global loads/stores for ptxplusTor Aamodt
passing CUDA 3.1 and ptxplus correlation correlation back to around 0.89 on ptxplus vs quadro fx5800 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7898]
2010-10-211. rewriting memory access generation code (from scratch), why not...Tor Aamodt
passing CUDA 3.1 and ptxplus correlation, but correlation still bad (0.62)... after debugging 1 to get it working with ptxplus, problem is very clear: shared and constant cache accesses not occuring for operations that combine these with ALU operations. TODO: have a "read-operands" stage, which somehow combines operand collector register reading with shared and const memory accesses... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7895]
2010-10-19adding texture cache model with fragment fifo for latency hidingTor Aamodt
passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7886]
2010-10-18update lru state on hitTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7883]
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