| Age | Commit message (Collapse) | Author |
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1- round robin inst issue for warp multiple schedulers
2- add sector mask in the memory request (to bused later for L2 sector cache)
3- Adding Fermi coalescer
4- Ensure different exen units are used in dual_issue mode
5- Report how many dual_issue happened
6- Adding oldest_first scheduler
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memory mapping, turn off by default
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shader, should use hw_cta_id to store shared mem info
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distributor directly
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architecture. Modified shader.h to allow for larger CTA per warp, to accomodate Maxwell specs.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21798]
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code to remove the trailing newline character from the C++ name de-mangling fix. Also, fixed small bug with previous commit
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with spaces (e.g., using templates)
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initial support for CUDA 5.0, 5.5, 6.0 to get template from SDK running
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to fetch into.
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1. ptx_sim.h::473, stack cannot use incomplete type "operand_info" which is a forward declaration. The reason is underlying implementation of stack is deque which need a complete type. It is better to remove forward declaration by break circular dependence for future fixes. It is also benefit unit test
2. shader.h::1334, this hack cannot pass clang. Clang does not allow a array with not a explicit size. Please fix this hack by correct implementation as soon as possible
3. The default parameter causes clang to fail because it frustrate the compiler. This is still under discussion whether such implementation is correct. http://stackoverflow.com/questions/18313509/default-argument-gcc-vs-clang. I changed it to two constructors to avoid confusion.
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(should fix regressions).
-remove some printfs that were there for debugging
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18480]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18452]
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- Added a parameter to the cache configuration to configure the set index function.
- Added a hash set index function to the Fermi L1 data cache for the two default cache sizes, 16KB/48KB with 32/64 sets.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18202]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17183]
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Review ID: 89001
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17086]
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write-allocation policy. Also added description for the write-allocation fix implemented by Tayler.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16914]
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is used.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16904]
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1. Decouple the constructor of interconnect interface
2. Some type changed to unsigned from int
Fixed Bug: wrong variable in InterconnectInterface::Busy()
Review: 83001
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16877]
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Review ID: 75001 lgtm: 2
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16758]
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Details: See Review 80001 https://gpgpu-sim-code-review.appspot.com/80001/
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16747]
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for specific caches.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16683]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16671]
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keep the DRAM utilized. Also extended the state printing function to print out mem_fetch entries inside the DRAM delay queue.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16639]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16635]
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partition. Each L2 cache banks has its own connection to the interconnection network to allow L2 bandwidth to scale without increase the number of memory parttiion units.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16613]
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still caching data from local memory space.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16601]
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Main contribution is a static warp limiting scheduler.
There is also some minor cleanup to the heirarchy of the cache code and removal some excessively long lines
Review ID: 36001 lgtm: 1
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16580]
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"WarpIssueDynamicIdBreakdown" are being printed in the visualization files without any data.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16572]
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Also changed some initialization code when cores are created in both the funcational and perfromance simulator
review:3001 lgtm:5
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16506]
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generated go in a directory independent of the source directory
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16503]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16495]
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simulation liveness printout (default to 1 per second in wall clock time).
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16482]
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