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Adding -gpuwattch_xml_file gpuwattch_gtx480.xml to configs/GTX480/gpgpusim.config.
Default changed from mcpat.xml -> gpuwattch.xml.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14808]
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//depot/gpgpu_sim_research/fermi_power/...
to //depot/gpgpu_sim_research/fermi/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14777]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14737]
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available only for GTX480) and enable it from GTX480 config
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14727]
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//depot/gpgpu_sim_research/fermi_power/distribution/...
to //depot/gpgpu_sim_research/fermi/distribution/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
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Now the two configs will feature 32-bank shared memory with a more flexible broadcast mechanism.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14509]
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instance of option parser). Changed DRAM timing options to use this new format.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14457]
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policies>, <MSHR>, <Miss queue/FIFO sizing>
- Fixing default configurations to match the new format and additonal parameters
- Fixing Fermi's 48kB cache configuration
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14370]
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as per Wilson's request
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14367]
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Integrated in CL14335 and CL14336
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14366]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14280]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14199]
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access functions. Removes the multiple long flaky branches in the access functions (caused by multiple config options) and replaces them with a single function that is set in the constructor to reflect the current configuration.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14198]
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Separated the L1 and L2 cache access() implementations. Removed PRIVATE/SHARED cache scope configurations.
Added WRITE_EVICT cache write policy.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14109]
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(Doxygen notation).
Removing some error checking /debugging code
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14091]
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gpu-cache.h to gpu-cache.cc for mshr_table, baseline/read_only/data/texture_caches
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14090]
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replication, implemented write allocate / write back policies in L2 cache, added configurable parameters in gpgpusim.config ("W" = Write Allocate, "N" = No write allocate -> "P" = Private, "S" = shared), modified the cache configuration lines to always be separated by ":" instead of ":" and ",", and modified L1 and L2 data cache to be "Write Back" caches instead of "Read Only".
Still need to implement Ahmed's sectored cache implementation.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14081]
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gpgpu_sim::issue_block2core() (Bug 19 External).
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13942]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13918]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13819]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13703]
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There is a problem with the linkage on my machine. Before this changelist the code didn't build on my machine. After it it builds but fails to run due to missing dynamic linkage. And obviously it breaks the jenkins build.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13684]
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Fixing failed compilation due to double definition of parsing functions
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13683]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13595]
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- Now there is only one macro for all use of unordered_map in the code.
- Moving all instances of gcc/cuda version detection into a single file.
- Adding a warning when the fallback is triggered.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13542]
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Is really harmless since you can call delete on primatives allocated with new[] without consequence (all delete [] does is ensure that the destructors will be called)
Still, it is always good practice to de-allocate anything allocated with new[] with delete[] - just in case the type allocated changes and the person that changes it forgets to update the de-allocation.
Really, this little array should be on the stack...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13414]
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callp_imp using a core_t function, thus moving the querying function into the abstract model of the core instead of shader_core_ctx which represents the performance mode. This code simplify the querying and also avoid the unnecessary calling hierarchy that was used.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13375]
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makedepend generates the dependencies in Makefile.makedepend that is generated dynamically and cleaned with "make clean"
Next step is to use gcc's "-M" option and get rid of makedepend altogether.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13292]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13261]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13139]
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- Increased burst length to 8 and changed address mapping to reflect 16 banks as suggested by Jungrae.
- Decreased the DRAM clock to 924MHz from 1848MHz.
- Corrected CAS Latency and Write Latency in the timing constraints.
- Added a new option 'dram_data_command_freq_ratio' to configure the frequency ratio between the DRAM data bus and command bus.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13138]
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be reporting the actual overall, instead of the average of just the final sampling window for AerialVision.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13045]
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replay eddy.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12666]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12564]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12383]
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just print the stats whenever a kernel is done.
This requires decoupling updating the stats from printing them and modifying the printing code to accomodate this change.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12366]
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- FUs depended on the result bus to know if they are going to be used on a certain cycle, this is not the case anymore, occupied bitvectors are added
- A configurable number of result buses is added (the number of buses is equal to the EX_WB pipe width)
- Modified the Fermi config file to add two ports to the operand collector
IPC with a theoretical limit of number_of_SMs*64 is achievable using this configuration
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12349]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12343]
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The observed latencies are reduced by 5 to account for other stages in the SM pipeline
Eventually this should be calibrated against the microbenchmarks
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12310]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12305]
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(see Bug #133)
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12257]
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(shared,tex,const,global/local,L1D) in ldst unit to round-robin.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12248]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12203]
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1. A configurable number of functional units within each SM
2. A configurable pipeline widths (i.e. Issue width, writeback width ...).
Merging
//depot/gpgpu_sim_research/fermi_replay/distribution/src/...
to //depot/gpgpu_sim_research/fermi/distribution/src/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12091]
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default if its configurations are not present
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12033]
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1. Adds support for using cuobjdump for both ptx and ptxplus execution. This has been tested with CUDA 4.0
. Ptxplus is no longer supported through decuda/decuda_to_ptxplus
2. Adds support for converting the SASS output by cuobjdump to ptxplus. This has been tested with CUDA 4.0
. The old path that extracts ptx from cubin files is still preserved
3. Adds a bank group model. (WARNING: memory config has changed, please adapt yours). To disable the bank groups model, set nbkgrp to 1 and tCCDL and tRTPL to 0
Diff the configuration files to learn about how to use those new options.
Merging
//depot/gpgpu_sim_research/fermi-test/distribution/...
to //depot/gpgpu_sim_research/fermi/distribution/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12023]
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instructions to be over counted when the LD instruction is stalled for a long time after sending part of its memory requests. Those memory requests manage to return before the LD is done sending all of its requests.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11888]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11877]
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of memory partition as well (before it just leaves the memory address unchanged!).
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11755]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11728]
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