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branch, incorporating Dynamic Parallelism and many bug fixes.
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Interconnection assertion failing demystifying
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1- round robin inst issue for warp multiple schedulers
2- add sector mask in the memory request (to bused later for L2 sector cache)
3- Adding Fermi coalescer
4- Ensure different exen units are used in dual_issue mode
5- Report how many dual_issue happened
6- Adding oldest_first scheduler
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updatet the built number output when we run gpgpu-sim we need to recompile cuda-sim everytime the detailed_version has changed
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# and branch will be embedded in the built executable and print out when gpgpu-sim runs
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The block containing predicate ret instruction should add the
consecutive block to its successor_ids set. next_addr should be assigned
with current instruction address add instruction size instead of 1.
Signed-off-by: Mengchi Zhang <[email protected]>
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shfl instruction implemented
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Initial support of CUDA Dynamic Parallelism on GPGPUSim
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memory mapping, turn off by default
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initiation_interval numbers for bsmad
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to complete the TODOs noted in bsmad_impl
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in its warp
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Now, sst_impl doesn't functionally execute on the last indexed element of an array, but instead on the actual last thread that executes
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sst_impl
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of elements instead of the device memory address
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in sstarr memory
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are in the sstarr memory and writes the data back into sstarr memory.
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