From 360d856f7189b2a69e5b48c04f9a0cdcbb6466b1 Mon Sep 17 00:00:00 2001 From: WilliamMTK Date: Tue, 18 Feb 2025 17:14:19 -0500 Subject: Fix cache string description in config files (#96) * fix_cache_string: update cache desc in config files and remove typos * fix_cache_string: update gitignore --- .gitignore | 8 ++++++++ configs/tested-cfgs/SM2_GTX480/gpgpusim.config | 4 ++-- configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config | 4 ++-- configs/tested-cfgs/SM6_TITANX/gpgpusim.config | 4 ++-- configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 4 ++-- configs/tested-cfgs/SM75_RTX2060_S/gpgpusim.config | 4 ++-- configs/tested-cfgs/SM7_GV100/gpgpusim.config | 4 ++-- configs/tested-cfgs/SM7_QV100/gpgpusim.config | 4 ++-- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 4 ++-- configs/tested-cfgs/SM86_RTX3070/gpgpusim.config | 4 ++-- src/gpgpu-sim/gpu-sim.cc | 4 ++-- 11 files changed, 28 insertions(+), 20 deletions(-) diff --git a/.gitignore b/.gitignore index 340277a..c27f921 100644 --- a/.gitignore +++ b/.gitignore @@ -56,9 +56,17 @@ debug_tools/WatchYourStep/ptxjitplus/gpgpu* debug_tools/WatchYourStep/ptxjitplus/*.old debug_tools/WatchYourStep/ptxjitplus/ptxjitplus debug_tools/WatchYourStep/ptxjitplus/*.ptx +*.tmp # Accel-sim packages used for regressions accel-sim-framework/ gpu-app-collection/ setup + +# OS/IDE specific files +.idea/ +.vscode/ +.DS_Store +.DS_store +__pycache__/ diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config index bc01821..4763728 100644 --- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config +++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config @@ -56,8 +56,8 @@ # In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb -# :::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo +# :::,::::,::,:**, +# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used # Note: Hashing set index function (H) only applies to a set size of 32 or 64. -gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,S:64:8,8 -gpgpu_shmem_size 49152 diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config index ef47ddf..9cb328f 100644 --- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config @@ -99,8 +99,8 @@ # Greedy then oldest scheduler -gpgpu_scheduler gto -# :::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo +# :::,::::,::,:**, +# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used # Note: Hashing set index function (H) only applies to a set size of 32 or 64. # The defulat is to disable the L1 cache, unless cache modifieres are used -gpgpu_cache:dl1 S:4:128:32,L:L:s:N:L,A:256:8,16:0,32 diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config index 7d3e2d4..882630e 100644 --- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config @@ -123,8 +123,8 @@ -gpgpu_dual_issue_diff_exec_units 1 ## L1/shared memory configuration -# :::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo +# :::,::::,::,:**, +# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used # Note: Hashing set index function (H) only applies to a set size of 32 or 64. # The defulat is to disable the L1 cache, unless cache modifieres are used -gpgpu_l1_banks 2 diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index 6ff4b6c..8cc3ed6 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -83,8 +83,8 @@ -gpgpu_dual_issue_diff_exec_units 1 ## L1/shared memory configuration -# :::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo +# :::,::::,::,:**, +# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used # In adaptive cache, we adaptively assign the remaining shared memory to L1 cache # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x -gpgpu_adaptive_cache_config 1 diff --git a/configs/tested-cfgs/SM75_RTX2060_S/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060_S/gpgpusim.config index 08ac752..290c08d 100644 --- a/configs/tested-cfgs/SM75_RTX2060_S/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060_S/gpgpusim.config @@ -128,8 +128,8 @@ -gpgpu_num_reg_banks 16 -gpgpu_reg_file_port_throughput 2 -# :::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo +# :::,::::,::,:**, +# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used -gpgpu_adaptive_cache_config 0 -gpgpu_l1_banks 4 -gpgpu_cache:dl1 S:1:128:512,L:L:s:N:L,A:256:8,16:0,32 diff --git a/configs/tested-cfgs/SM7_GV100/gpgpusim.config b/configs/tested-cfgs/SM7_GV100/gpgpusim.config index 26ce0eb..4887be8 100644 --- a/configs/tested-cfgs/SM7_GV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_GV100/gpgpusim.config @@ -137,8 +137,8 @@ -gpgpu_dual_issue_diff_exec_units 1 ## L1/shared memory configuration -# :::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo +# :::,::::,::,:**, +# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used # Defualt config is 32KB DL1 and 96KB shared memory # In Volta, we assign the remaining shared memory to L1 cache # if the assigned shd mem = 0, then L1 cache = 128KB diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index b3384af..a14ae75 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -137,8 +137,8 @@ -gpgpu_dual_issue_diff_exec_units 1 ## L1/shared memory configuration -# :::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo +# :::,::::,::,:**, +# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used # Defualt config is 32KB DL1 and 96KB shared memory # In Volta, we assign the remaining shared memory to L1 cache # if the assigned shd mem = 0, then L1 cache = 128KB diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index c37aaf0..b48f370 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -107,8 +107,8 @@ -gpgpu_dual_issue_diff_exec_units 1 ## L1/shared memory configuration -# :::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo +# :::,::::,::,:**, +# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used # Defualt config is 32KB DL1 and 96KB shared memory # In Volta, we assign the remaining shared memory to L1 cache # if the assigned shd mem = 0, then L1 cache = 128KB diff --git a/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config b/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config index d26b1a6..c884541 100644 --- a/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config +++ b/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config @@ -83,8 +83,8 @@ -gpgpu_dual_issue_diff_exec_units 1 ## L1/shared memory configuration -# :::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo +# :::,::::,::,:**, +# ** Optional parameter - Required when mshr_type==Texture Fifo, set to 0 if not used # In adaptive cache, we adaptively assign the remaining shared memory to L1 cache # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x -gpgpu_adaptive_cache_config 1 diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 65462cc..3f84d42 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -377,14 +377,14 @@ void shader_core_config::reg_options(class OptionParser *opp) { "per-shader L1 data cache config " " {:::,::<" "alloc>::,::,<" - "mq>:, | none | none}", + "mq>:, | none}", "none"); option_parser_register(opp, "-gpgpu_cache:dl1PrefShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, "per-shader L1 data cache config " " {:::,::<" "alloc>::,::,<" - "mq>:, | none | none}", + "mq>:, | none}", "none"); option_parser_register(opp, "-gpgpu_gmem_skip_L1D", OPT_BOOL, &gmem_skip_L1D, "global memory access skip L1D cache (implements " -- cgit v1.3