From 2dee85bd4e7558e190880e2ade20764131945569 Mon Sep 17 00:00:00 2001 From: Guillermo Julián Date: Fri, 10 Jul 2015 14:05:33 +0200 Subject: Increase line buffer size --- src/cuda-sim/ptx.l | 4 ++-- src/cuda-sim/ptx_parser.cc | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index dfed936..98d0b6c 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -36,7 +36,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "ptx.tab.h" #include -char linebuf[1024]; +char linebuf[4096]; unsigned col = 0; #define TC col+=strlen(ptx_text); #define CHECK_UNSIGNED \ @@ -370,7 +370,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; "//"[^\n]* TC; // eat single -\n.* col=0; strncpy(linebuf, yytext + 1, 1024); yyless( 1 ); +\n.* col=0; strncpy(linebuf, yytext + 1, sizeof(linebuf)); yyless( 1 ); " " TC; "\t" TC; diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index 824714a..2e5ed8e 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -240,7 +240,7 @@ void parse_assert_impl( int test_value, const char *file, unsigned line, const c parse_error_impl(file,line, msg); } -extern char linebuf[1024]; +extern char linebuf[4096]; void set_return() -- cgit v1.3 From 6d99ddf6d366302c29890a98f217a3885ce3d0e2 Mon Sep 17 00:00:00 2001 From: Guillermo Julián Date: Sat, 11 Jul 2015 11:16:42 +0200 Subject: Allow visible directives in variable specifications --- src/cuda-sim/ptx.y | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 79faddf..a6cdfda 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -320,6 +320,7 @@ var_spec_list: var_spec var_spec: space_spec | type_spec | align_spec + | VISIBLE_DIRECTIVE | EXTERN_DIRECTIVE { add_extern_spec(); } ; -- cgit v1.3 From b1fd283c064222579ee5174a980abf72e8e6ef26 Mon Sep 17 00:00:00 2001 From: Guillermo Julián Date: Sat, 11 Jul 2015 11:20:52 +0200 Subject: Allow const directives in the parameter specification --- src/cuda-sim/ptx.y | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index a6cdfda..8f47867 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -259,6 +259,7 @@ ptr_spec: /*empty*/ ptr_space_spec: GLOBAL_DIRECTIVE { add_ptr_spec(global_space); } | LOCAL_DIRECTIVE { add_ptr_spec(local_space); } | SHARED_DIRECTIVE { add_ptr_spec(shared_space); } + | CONST_DIRECTIVE { add_ptr_spec(global_space); } ptr_align_spec: ALIGN_DIRECTIVE INT_OPERAND -- cgit v1.3 From 91b2afe09dbeb0fa1c5eb57cd4b416a5eb24bf60 Mon Sep 17 00:00:00 2001 From: sspenst Date: Mon, 4 Jul 2016 16:25:11 -0700 Subject: Initial SST recognition from PTX parser --- src/cuda-sim/instructions.cc | 5 +++++ src/cuda-sim/opcodes.def | 1 + src/cuda-sim/ptx.l | 1 + 3 files changed, 7 insertions(+) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 7b0f4fa..36aa29f 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3734,6 +3734,11 @@ void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) thread->set_operand_value(dst,d, i_type, thread, pI); } +void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + printf("SST instruction found.\n"); +} + void ssy_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { //printf("Execution Warning: unimplemented ssy instruction is treated as a nop\n"); diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 2ee6976..0c0eda9 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -103,6 +103,7 @@ OP_DEF(SHR_OP,shr_impl,"shr",1,1) OP_DEF(SIN_OP,sin_impl,"sin",1,4) OP_DEF(SLCT_OP,slct_impl,"slct",1,1) OP_DEF(SQRT_OP,sqrt_impl,"sqrt",1,4) +OP_DEF(SST_OP,sst_impl,"sst",1,1) OP_DEF(SSY_OP,ssy_impl,"ssy",0,3) OP_DEF(ST_OP,st_impl,"st",0,5) OP_DEF(SUB_OP,sub_impl,"sub",1,1) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 88ccf6a..1ac047c 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -120,6 +120,7 @@ shr TC; ptx_lval.int_value = SHR_OP; return OPCODE; sin TC; ptx_lval.int_value = SIN_OP; return OPCODE; slct TC; ptx_lval.int_value = SLCT_OP; return OPCODE; sqrt TC; ptx_lval.int_value = SQRT_OP; return OPCODE; +sst TC; ptx_lval.int_value = SST_OP; return OPCODE; ssy TC; ptx_lval.int_value = SSY_OP; return OPCODE; st TC; ptx_lval.int_value = ST_OP; return OPCODE; st.volatile TC; ptx_lval.int_value = ST_OP; return OPCODE; -- cgit v1.3 From fa63d925c3d73d4c1dd7b27799d501c90917aa84 Mon Sep 17 00:00:00 2001 From: sspenst Date: Tue, 5 Jul 2016 11:58:39 -0700 Subject: Slight addition to the parser for CPTX aesthetics. You now begin and end your custom inserted PTX with CPTX_BEGIN and CPTX_END, respectively. --- src/cuda-sim/ptx.l | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 1ac047c..49fd790 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -148,6 +148,8 @@ nop TC; ptx_lval.int_value = NOP_OP; return OPCODE; break TC; ptx_lval.int_value = BREAK_OP; return OPCODE; breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; +"CPTX_END" printf("ENDING CUSTOM PTX.\n"); BEGIN(IN_COMMENT); + { \.align TC; return ALIGN_DIRECTIVE; @@ -393,9 +395,9 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; { "*/" BEGIN(INITIAL); "CPTX_BEGIN" printf("BEGINNING CUSTOM PTX.\n"); BEGIN(INITIAL); -[^C*\n]+ // eat comment in chunks -"C" -"*" // eat the lone star +[^C*\n]+ // eat comment in chunks +"C" // eat the lone C +"*" // eat the lone star \n TC; } -- cgit v1.3 From 35cf76f383ec8de6de901bbbcd8fb478f69e46e4 Mon Sep 17 00:00:00 2001 From: sspenst Date: Wed, 6 Jul 2016 13:56:52 -0700 Subject: Added sstarr memory, which works the same as shared memory --- cuobjdump_to_ptxplus/ptx_parser.h | 1 + src/abstract_hardware_model.h | 1 + src/cuda-sim/cuda-sim.cc | 8 +++++ src/cuda-sim/instructions.cc | 65 +++++++++++++++++++++++++++++++++++++++ src/cuda-sim/ptx.l | 1 + src/cuda-sim/ptx.y | 2 ++ src/cuda-sim/ptx_ir.h | 6 ++++ src/cuda-sim/ptx_parser.cc | 14 +++++++++ src/cuda-sim/ptx_sim.cc | 1 + src/cuda-sim/ptx_sim.h | 1 + 10 files changed, 100 insertions(+) diff --git a/cuobjdump_to_ptxplus/ptx_parser.h b/cuobjdump_to_ptxplus/ptx_parser.h index 1c96b46..22377b2 100644 --- a/cuobjdump_to_ptxplus/ptx_parser.h +++ b/cuobjdump_to_ptxplus/ptx_parser.h @@ -58,6 +58,7 @@ enum _memory_space_t { reg_space, local_space, shared_space, + sstarr_space, param_space_unclassified, param_space_kernel, /* global to all threads in a kernel : read-only */ param_space_local, /* local to a thread : read-writable */ diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index b29f918..750eb6a 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -41,6 +41,7 @@ enum _memory_space_t { reg_space, local_space, shared_space, + sstarr_space, param_space_unclassified, param_space_kernel, /* global to all threads in a kernel : read-only */ param_space_local, /* local to a thread : read-writable */ diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 09e9a81..57da23f 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1407,6 +1407,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, std::list &active_threads = kernel.active_threads(); static std::map shared_memory_lookup; + static std::map sstarr_memory_lookup; static std::map ptx_cta_lookup; static std::map > local_memory_lookup; @@ -1450,6 +1451,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, //initializing new CTA ptx_cta_info *cta_info = NULL; memory_space *shared_mem = NULL; + memory_space *sstarr_mem = NULL; unsigned cta_size = kernel.threads_per_cta(); unsigned max_cta_per_sm = num_threads/cta_size; // e.g., 256 / 48 = 5 @@ -1466,6 +1468,9 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, snprintf(buf,512,"shared_%u", sid); shared_mem = new memory_space_impl<16*1024>(buf,4); shared_memory_lookup[sm_idx] = shared_mem; + snprintf(buf,512,"sstarr_%u", sid); + sstarr_mem = new memory_space_impl<16*1024>(buf,4); + sstarr_memory_lookup[sm_idx] = sstarr_mem; cta_info = new ptx_cta_info(sm_idx); ptx_cta_lookup[sm_idx] = cta_info; } else { @@ -1474,6 +1479,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, sm_idx, sid, max_cta_per_sm ); } shared_mem = shared_memory_lookup[sm_idx]; + sstarr_mem = sstarr_memory_lookup[sm_idx]; cta_info = ptx_cta_lookup[sm_idx]; cta_info->check_cta_thread_status_and_reset(); } @@ -1506,9 +1512,11 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, thd->cpy_tid_to_reg(tid3d); thd->set_valid(); thd->m_shared_mem = shared_mem; + thd->m_sstarr_mem = sstarr_mem; function_info *finfo = thd->func_info(); symbol_table *st = finfo->get_symtab(); thd->func_info()->param_to_shared(thd->m_shared_mem,st); + thd->func_info()->param_to_shared(thd->m_sstarr_mem,st); thd->m_cta_info = cta_info; cta_info->add_thread(thd); thd->m_local_mem = local_mem; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 36aa29f..4eb5ce3 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -130,6 +130,8 @@ ptx_reg_t ptx_thread_info::get_operand_value( const operand_info &op, operand_in result.u64 = sym->get_address() + op.get_addr_offset(); } else if ( op.is_shared() ) { result.u64 = op.get_symbol()->get_address() + op.get_addr_offset(); + } else if ( op.is_sstarr() ) { + result.u64 = op.get_symbol()->get_address() + op.get_addr_offset(); } else { const char *name = op.name().c_str(); printf("GPGPU-Sim PTX: ERROR ** get_operand_value : unknown memory operand type for %s\n", name ); @@ -142,6 +144,8 @@ ptx_reg_t ptx_thread_info::get_operand_value( const operand_info &op, operand_in result.u64 = op.get_symbol()->get_address(); } else if ( op.is_shared() ) { result.u64 = op.get_symbol()->get_address(); + } else if ( op.is_sstarr() ) { + result.u64 = op.get_symbol()->get_address(); } else if ( op.is_const() ) { result.u64 = op.get_symbol()->get_address(); } else if ( op.is_global() ) { @@ -2347,6 +2351,7 @@ void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand case surf_space: mem = thread->get_surf_memory(); break; case param_space_kernel: mem = thread->get_param_memory(); break; case shared_space: mem = thread->m_shared_mem; break; + case sstarr_space: mem = thread->m_sstarr_mem; break; case const_space: mem = thread->get_global_memory(); break; case generic_space: if( thread->get_ptx_version().ver() >= 2.0 ) { @@ -3736,7 +3741,67 @@ void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { + const operand_info &src1 = pI->src1(); + const operand_info &src3 = pI->src3(); //may be scalar or vector of regs + unsigned type = pI->get_type(); + ptx_reg_t addr_reg = thread->get_operand_value(src1, src1, type, thread, 1); + ptx_reg_t src3_data; + memory_space_t space = pI->get_space(); + + memory_space *mem = NULL; + addr_t addr = addr_reg.u32; + + decode_space(space,thread,src1,mem,addr); + + size_t size; + int t; + type_info_key::type_decode(type,size,t); + + src3_data = thread->get_operand_value(src3, src1, type, thread, 1); + mem->write(addr,size/8,&src3_data.s64,thread,pI); + thread->m_last_effective_address = addr; + thread->m_last_memory_space = space; + + printf("SST instruction found.\n"); + + /*const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + + unsigned type = pI->get_type(); + ptx_reg_t addr_reg = thread->get_operand_value(src1, src1, type, thread, 1); + memory_space_t space = pI->get_space(); + + memory_space *mem = NULL; + addr_t addr = addr_reg.u32; + + decode_space(space,thread,src1,mem,addr); + + size_t size; + int t; + type_info_key::type_decode(type,size,t); + + ptx_reg_t src2_data = thread->get_operand_value(src2, src1, type, thread, 1); + ptx_reg_t src3_data = thread->get_operand_value(src3, src1, type, thread, 1); + mem->write(addr,size/8,&src3_data.s64,thread,pI);*/ + + /* + switch ( i_type ) { + case U32_TYPE: + data.u64 = (src1_data.u64 & 0xFFFFFFFF) + (src2_data.u64 & 0xFFFFFFFF); + carry = (data.u64 & 0x100000000)>>32; + break; + case U64_TYPE: + data.u64 = src1_data.u64 + src2_data.u64; + break; + default: assert(0); break; + }*/ + + //thread->set_operand_value(dst, data, i_type, thread, pI, overflow, carry ); + //thread->m_last_effective_address = addr; + //thread->m_last_memory_space = space; } void ssy_impl( const ptx_instruction *pI, ptx_thread_info *thread ) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 49fd790..69349a0 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -177,6 +177,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.section TC; return SECTION_DIRECTIVE; \.shared TC; return SHARED_DIRECTIVE; \.sreg TC; return SREG_DIRECTIVE; +\.sstarr TC; return SSTARR_DIRECTIVE; \.struct TC; return STRUCT_DIRECTIVE; \.surf TC; return SURF_DIRECTIVE; /* not in PTX 2.1 */ \.target TC; return TARGET_DIRECTIVE; diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 4de39d1..97f4ff2 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -64,6 +64,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token SECTION_DIRECTIVE %token SHARED_DIRECTIVE %token SREG_DIRECTIVE +%token SSTARR_DIRECTIVE %token STRUCT_DIRECTIVE %token SURF_DIRECTIVE %token TARGET_DIRECTIVE @@ -339,6 +340,7 @@ addressable_spec: CONST_DIRECTIVE { add_space_spec(const_space,$1); } | LOCAL_DIRECTIVE { add_space_spec(local_space,0); } | PARAM_DIRECTIVE { add_space_spec(param_space_unclassified,0); } | SHARED_DIRECTIVE { add_space_spec(shared_space,0); } + | SSTARR_DIRECTIVE { add_space_spec(sstarr_space,0); } | SURF_DIRECTIVE { add_space_spec(surf_space,0); } | TEX_DIRECTIVE { add_space_spec(tex_space,0); } ; diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 601a13d..7724443 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -222,6 +222,7 @@ public: bool is_label() const { return m_is_label;} bool is_shared() const { return m_is_shared;} + bool is_sstarr() const { return m_is_sstarr;} bool is_const() const { return m_is_const;} bool is_global() const { return m_is_global;} bool is_local() const { return m_is_local;} @@ -279,6 +280,7 @@ private: bool m_address_valid; bool m_is_label; bool m_is_shared; + bool m_is_sstarr; bool m_is_const; bool m_is_global; bool m_is_local; @@ -313,10 +315,12 @@ public: void set_label_address( const symbol *label, unsigned addr ); unsigned next_reg_num() { return ++m_reg_allocator;} addr_t get_shared_next() { return m_shared_next;} + addr_t get_sstarr_next() { return m_sstarr_next;} addr_t get_global_next() { return m_global_next;} addr_t get_local_next() { return m_local_next;} addr_t get_tex_next() { return m_tex_next;} void alloc_shared( unsigned num_bytes ) { m_shared_next += num_bytes;} + void alloc_sstarr( unsigned num_bytes ) { m_sstarr_next += num_bytes;} void alloc_global( unsigned num_bytes ) { m_global_next += num_bytes;} void alloc_local( unsigned num_bytes ) { m_local_next += num_bytes;} void alloc_tex( unsigned num_bytes ) { m_tex_next += num_bytes;} @@ -333,6 +337,7 @@ public: private: unsigned m_reg_allocator; unsigned m_shared_next; + unsigned m_sstarr_next; unsigned m_const_next; unsigned m_global_next; unsigned m_local_next; @@ -703,6 +708,7 @@ public: } return m_value.m_symbolic->is_shared(); } + bool is_sstarr() const { return m_value.m_symbolic->is_sstarr();} bool is_const() const { return m_value.m_symbolic->is_const();} bool is_global() const { return m_value.m_symbolic->is_global();} bool is_local() const { return m_value.m_symbolic->is_local();} diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index 824714a..a53a8fe 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -415,6 +415,20 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident g_last_symbol->set_address( addr+addr_pad ); g_current_symbol_table->alloc_shared( num_bits/8 + addr_pad ); break; + case sstarr_space: + printf("GPGPU-Sim PTX: allocating sstarr region for \"%s\" ", + identifier); + fflush(stdout); + assert( (num_bits%8) == 0 ); + addr = g_current_symbol_table->get_sstarr_next(); + addr_pad = pad_address(addr, num_bits/8, 128); + printf("from 0x%x to 0x%lx (sstarr memory space)\n", + addr+addr_pad, + addr+addr_pad + num_bits/8); + fflush(stdout); + g_last_symbol->set_address( addr+addr_pad ); + g_current_symbol_table->alloc_sstarr( num_bits/8 + addr_pad ); + break; case const_space: if( array_ident == ARRAY_IDENTIFIER_NO_DIM ) { printf("GPGPU-Sim PTX: deferring allocation of constant region for \"%s\" (need size information)\n", identifier ); diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc index 09844ae..511e8d6 100644 --- a/src/cuda-sim/ptx_sim.cc +++ b/src/cuda-sim/ptx_sim.cc @@ -153,6 +153,7 @@ ptx_thread_info::ptx_thread_info( kernel_info_t &kernel ) m_last_memory_space = undefined_space; m_branch_taken = 0; m_shared_mem = NULL; + m_sstarr_mem = NULL; m_cta_info = NULL; m_local_mem = NULL; m_symbol_table = NULL; diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index f926e6d..c66b68c 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -424,6 +424,7 @@ public: memory_space_t m_last_memory_space; dram_callback_t m_last_dram_callback; memory_space *m_shared_mem; + memory_space *m_sstarr_mem; memory_space *m_local_mem; ptx_cta_info *m_cta_info; ptx_reg_t m_last_set_operand_value; -- cgit v1.3 From e841e5f21b9d86910a6cc10de3af016912c43ce0 Mon Sep 17 00:00:00 2001 From: sspenst Date: Wed, 6 Jul 2016 15:08:11 -0700 Subject: Added the ability to load from sstarr memory after data has been stored in it --- src/abstract_hardware_model.cc | 4 +++- src/gpgpu-sim/gpu-sim.cc | 3 +++ src/gpgpu-sim/shader.cc | 1 + src/gpgpu-sim/shader.h | 1 + 4 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index 84d165c..ab83ba4 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -213,6 +213,7 @@ void warp_inst_t::generate_mem_accesses() access_type = is_write? LOCAL_ACC_W: LOCAL_ACC_R; break; case shared_space: break; + case sstarr_space: break; default: assert(0); break; } @@ -220,7 +221,8 @@ void warp_inst_t::generate_mem_accesses() new_addr_type cache_block_size = 0; // in bytes switch( space.get_type() ) { - case shared_space: { + case shared_space: + case sstarr_space: { unsigned subwarp_size = m_config->warp_size / m_config->mem_warp_parts; unsigned total_accesses=0; for( unsigned subwarp=0; subwarp < m_config->mem_warp_parts; subwarp++ ) { diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index eafb909..e7ba8e5 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1049,6 +1049,9 @@ void shader_core_ctx::mem_instruction_stats(const warp_inst_t &inst) case shared_space: m_stats->gpgpu_n_shmem_insn += active_count; break; + case sstarr_space: + m_stats->gpgpu_n_sstarr_insn += active_count; + break; case const_space: m_stats->gpgpu_n_const_insn += active_count; break; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index ff2fac7..9c3f816 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -386,6 +386,7 @@ void shader_core_stats::print( FILE* fout ) const fprintf(fout, "gpgpu_n_load_insn = %d\n", gpgpu_n_load_insn); fprintf(fout, "gpgpu_n_store_insn = %d\n", gpgpu_n_store_insn); fprintf(fout, "gpgpu_n_shmem_insn = %d\n", gpgpu_n_shmem_insn); + fprintf(fout, "gpgpu_n_shmem_insn = %d\n", gpgpu_n_sstarr_insn); fprintf(fout, "gpgpu_n_tex_insn = %d\n", gpgpu_n_tex_insn); fprintf(fout, "gpgpu_n_const_mem_insn = %d\n", gpgpu_n_const_insn); fprintf(fout, "gpgpu_n_param_mem_insn = %d\n", gpgpu_n_param_insn); diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 38d09e9..3b9859f 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1372,6 +1372,7 @@ struct shader_core_stats_pod { unsigned gpgpu_n_load_insn; unsigned gpgpu_n_store_insn; unsigned gpgpu_n_shmem_insn; + unsigned gpgpu_n_sstarr_insn; unsigned gpgpu_n_tex_insn; unsigned gpgpu_n_const_insn; unsigned gpgpu_n_param_insn; -- cgit v1.3 From 7ce3005d27cfa68d6ed1fea001eb22cf0da628c2 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Wed, 6 Jul 2016 16:52:35 -0700 Subject: pull torque queue manger setup for github/travis --- .travis.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.travis.yml b/.travis.yml index 18fcd7a..525fa4a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,5 +1,7 @@ dist: trusty before_install: + - git clone https://github.com/gpgpu-sim/setup_torque_on_ubuntu_14.04.git + - ./setup_torque_on_ubuntu_14.04/install_torque.sh - wget http://developer.download.nvidia.com/compute/cuda/repos/ubuntu1404/x86_64/cuda-repo-ubuntu1404_7.5-18_amd64.deb - sudo dpkg -i cuda-repo-ubuntu1404_7.5-18_amd64.deb - sudo apt-get -qq update -- cgit v1.3 From 7758943c96d22cd65f3de30b36c71b27370de5ce Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Wed, 6 Jul 2016 17:03:58 -0700 Subject: dependencies and directory --- .travis.yml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/.travis.yml b/.travis.yml index 525fa4a..0564709 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,7 +1,8 @@ dist: trusty -before_install: +before_install: + - sudo apt-get install -y libssl-dev libxml2-dev libboost-all-dev - git clone https://github.com/gpgpu-sim/setup_torque_on_ubuntu_14.04.git - - ./setup_torque_on_ubuntu_14.04/install_torque.sh + - cd ./setup_torque_on_ubuntu_14.04; ./install_torque.sh; cd - - wget http://developer.download.nvidia.com/compute/cuda/repos/ubuntu1404/x86_64/cuda-repo-ubuntu1404_7.5-18_amd64.deb - sudo dpkg -i cuda-repo-ubuntu1404_7.5-18_amd64.deb - sudo apt-get -qq update -- cgit v1.3 From 320631e64d6d9e4ccdac175621858642b7b12265 Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 7 Jul 2016 09:35:49 -0700 Subject: Rough implementation of the SST instruction. It squeezes out the zeros that are in the sstarr memory and writes the data back into sstarr memory. --- src/cuda-sim/instructions.cc | 91 ++++++++++++++++++++++++-------------------- 1 file changed, 49 insertions(+), 42 deletions(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 4eb5ce3..47f7075 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3741,15 +3741,16 @@ void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { + // Step 1: store data in sstarr memory const operand_info &src1 = pI->src1(); - const operand_info &src3 = pI->src3(); //may be scalar or vector of regs + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); unsigned type = pI->get_type(); - ptx_reg_t addr_reg = thread->get_operand_value(src1, src1, type, thread, 1); - ptx_reg_t src3_data; + ptx_reg_t src1_data = thread->get_operand_value(src1, src1, type, thread, 1); + ptx_reg_t src2_data, src3_data; memory_space_t space = pI->get_space(); - memory_space *mem = NULL; - addr_t addr = addr_reg.u32; + addr_t addr = src1_data.u32; decode_space(space,thread,src1,mem,addr); @@ -3757,51 +3758,57 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) int t; type_info_key::type_decode(type,size,t); + src2_data = thread->get_operand_value(src2, src1, type, thread, 1); src3_data = thread->get_operand_value(src3, src1, type, thread, 1); mem->write(addr,size/8,&src3_data.s64,thread,pI); + thread->m_last_effective_address = addr; thread->m_last_memory_space = space; + // Step 2: __syncthreads() to make sure all data is stored in sstarr memory + // (function must be called with dst = 0 so that all threads execute bar.sync 0) + ptx_instruction * cpI = const_cast(pI); + const operand_info &dst = cpI->dst(); + ptx_reg_t dst_data; + dst_data = thread->get_operand_value(dst, dst, U32_TYPE, thread, 1); + cpI->set_bar_id(dst_data.u32); + + thread->m_last_dram_callback.function = bar_callback; + thread->m_last_dram_callback.instruction = pI; + + // Step 3: pick only one thread to load all of the data back from sstarr memory + // rearrange the data so that zeros are at the end of the array + // store this data back in the original array (each thread can maybe do this after another sync?) + int NUM_THREADS = 8; + if (src2_data.s64 == NUM_THREADS-1) { + addr -= (NUM_THREADS-1)*4; + unsigned offset = 0; + ptx_reg_t data; + // loop through all of the threads (how do you do this dynamically?) + for (int tid = 0; tid < NUM_THREADS; tid++) { + data.u64=0; + mem->read(addr+(tid*4),size/8,&data.s64); + + // store nonzero entries + if (data.s64 != 0) { + mem->write(addr+(offset*4),size/8,&data.s64,thread,pI); + thread->m_last_effective_address = addr+(offset*4); + offset++; + } + } + // fill the rest of the array with zeros + while (offset < NUM_THREADS) { + mem->write(addr+(offset*4),size/8,&src2_data.s64,thread,pI); + thread->m_last_effective_address = addr+(offset*4); + offset++; + } - printf("SST instruction found.\n"); - - /*const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - - unsigned type = pI->get_type(); - ptx_reg_t addr_reg = thread->get_operand_value(src1, src1, type, thread, 1); - memory_space_t space = pI->get_space(); - - memory_space *mem = NULL; - addr_t addr = addr_reg.u32; - - decode_space(space,thread,src1,mem,addr); + // Step 4: load from sstarr memory and store data back into original array - size_t size; - int t; - type_info_key::type_decode(type,size,t); + } - ptx_reg_t src2_data = thread->get_operand_value(src2, src1, type, thread, 1); - ptx_reg_t src3_data = thread->get_operand_value(src3, src1, type, thread, 1); - mem->write(addr,size/8,&src3_data.s64,thread,pI);*/ - - /* - switch ( i_type ) { - case U32_TYPE: - data.u64 = (src1_data.u64 & 0xFFFFFFFF) + (src2_data.u64 & 0xFFFFFFFF); - carry = (data.u64 & 0x100000000)>>32; - break; - case U64_TYPE: - data.u64 = src1_data.u64 + src2_data.u64; - break; - default: assert(0); break; - }*/ - - //thread->set_operand_value(dst, data, i_type, thread, pI, overflow, carry ); - //thread->m_last_effective_address = addr; - //thread->m_last_memory_space = space; + //if( type == S16_TYPE || type == S32_TYPE ) sign_extend(data,size,dst); + //thread->set_operand_value(dst,data, type, thread, pI); } void ssy_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -- cgit v1.3 From 19595382f05235b8887955c76794a976fad04833 Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 7 Jul 2016 11:53:56 -0700 Subject: SST instruction now updates the original array instead of storing the result in sstarr memory --- src/abstract_hardware_model.h | 1 + src/cuda-sim/instructions.cc | 49 ++++++++++++++++++++++++------------------- 2 files changed, 28 insertions(+), 22 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 750eb6a..6ed9b8e 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -554,6 +554,7 @@ public: return false; } enum _memory_space_t get_type() const { return m_type; } + void set_type( enum _memory_space_t t ) { m_type = t; } unsigned get_bank() const { return m_bank; } void set_bank( unsigned b ) { m_bank = b; } bool is_const() const { return (m_type == const_space) || (m_type == param_space_kernel); } diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 47f7075..d4b74fa 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3747,10 +3747,11 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) const operand_info &src3 = pI->src3(); unsigned type = pI->get_type(); ptx_reg_t src1_data = thread->get_operand_value(src1, src1, type, thread, 1); - ptx_reg_t src2_data, src3_data; + ptx_reg_t src2_data = thread->get_operand_value(src2, src1, type, thread, 1); + ptx_reg_t src3_data = thread->get_operand_value(src3, src1, type, thread, 1); memory_space_t space = pI->get_space(); memory_space *mem = NULL; - addr_t addr = src1_data.u32; + addr_t addr = src2_data.u32 * 4; // this assumes sstarr memory starts at address 0 decode_space(space,thread,src1,mem,addr); @@ -3758,13 +3759,8 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) int t; type_info_key::type_decode(type,size,t); - src2_data = thread->get_operand_value(src2, src1, type, thread, 1); - src3_data = thread->get_operand_value(src3, src1, type, thread, 1); mem->write(addr,size/8,&src3_data.s64,thread,pI); - thread->m_last_effective_address = addr; - thread->m_last_memory_space = space; - // Step 2: __syncthreads() to make sure all data is stored in sstarr memory // (function must be called with dst = 0 so that all threads execute bar.sync 0) ptx_instruction * cpI = const_cast(pI); @@ -3776,35 +3772,44 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) thread->m_last_dram_callback.function = bar_callback; thread->m_last_dram_callback.instruction = pI; - // Step 3: pick only one thread to load all of the data back from sstarr memory - // rearrange the data so that zeros are at the end of the array - // store this data back in the original array (each thread can maybe do this after another sync?) - int NUM_THREADS = 8; + + int NUM_THREADS = 8; // (how do you get this dynamically?) if (src2_data.s64 == NUM_THREADS-1) { - addr -= (NUM_THREADS-1)*4; + // Step 3: pick only one thread to load all of the data back from sstarr memory unsigned offset = 0; + addr -= (NUM_THREADS-1)*4; ptx_reg_t data; - // loop through all of the threads (how do you do this dynamically?) + float sstarr_fdata[NUM_THREADS]; + signed long long sstarr_ldata[NUM_THREADS]; + // loop through all of the threads for (int tid = 0; tid < NUM_THREADS; tid++) { data.u64=0; mem->read(addr+(tid*4),size/8,&data.s64); + sstarr_fdata[tid] = data.f32; + sstarr_ldata[tid] = data.s64; + } - // store nonzero entries - if (data.s64 != 0) { - mem->write(addr+(offset*4),size/8,&data.s64,thread,pI); - thread->m_last_effective_address = addr+(offset*4); + // Step 4: squeeze the zeros out of the array and store data back into original array + mem = NULL; + addr = src1_data.u32; + space.set_type(global_space); + decode_space(space,thread,src1,mem,addr); + // store nonzero entries + for (int tid = 0; tid < NUM_THREADS; tid++) { + if (sstarr_fdata[tid] != 0) { + mem->write(addr+(offset*4),size/8,&sstarr_ldata[tid],thread,pI); offset++; } } - // fill the rest of the array with zeros + + // fill the rest of the array with zeros (dst should always have a 0 in it) while (offset < NUM_THREADS) { - mem->write(addr+(offset*4),size/8,&src2_data.s64,thread,pI); - thread->m_last_effective_address = addr+(offset*4); + mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI); offset++; } - // Step 4: load from sstarr memory and store data back into original array - + thread->m_last_effective_address = addr+(NUM_THREADS-1)*4; + thread->m_last_memory_space = space; } //if( type == S16_TYPE || type == S32_TYPE ) sign_extend(data,size,dst); -- cgit v1.3 From e61a68f28a887fae5ed49533597349dfd074ebf9 Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 7 Jul 2016 12:43:10 -0700 Subject: SST instruction now returns the end address of the new sparse array --- src/cuda-sim/instructions.cc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index d4b74fa..9e2dfbb 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3802,6 +3802,11 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) } } + // store the return address + data = thread->get_operand_value(src1, dst, type, thread, 1); + data.s64 += 4*(offset-1); // set address to the last spot in the sparse array + thread->set_operand_value(dst, data, type, thread, pI); + // fill the rest of the array with zeros (dst should always have a 0 in it) while (offset < NUM_THREADS) { mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI); @@ -3811,9 +3816,6 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) thread->m_last_effective_address = addr+(NUM_THREADS-1)*4; thread->m_last_memory_space = space; } - - //if( type == S16_TYPE || type == S32_TYPE ) sign_extend(data,size,dst); - //thread->set_operand_value(dst,data, type, thread, pI); } void ssy_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -- cgit v1.3 From 64ad6d76929403d5d4de4e5f0a218cf4ea8cbfbf Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 7 Jul 2016 14:39:45 -0700 Subject: Indices are now stored corresponding to values. SST now returns the number of elements instead of the device memory address --- src/cuda-sim/instructions.cc | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 9e2dfbb..5a7382a 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3776,13 +3776,13 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) int NUM_THREADS = 8; // (how do you get this dynamically?) if (src2_data.s64 == NUM_THREADS-1) { // Step 3: pick only one thread to load all of the data back from sstarr memory - unsigned offset = 0; + long long offset = 0; addr -= (NUM_THREADS-1)*4; ptx_reg_t data; float sstarr_fdata[NUM_THREADS]; signed long long sstarr_ldata[NUM_THREADS]; // loop through all of the threads - for (int tid = 0; tid < NUM_THREADS; tid++) { + for (short tid = 0; tid < NUM_THREADS; tid++) { data.u64=0; mem->read(addr+(tid*4),size/8,&data.s64); sstarr_fdata[tid] = data.f32; @@ -3794,22 +3794,26 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) addr = src1_data.u32; space.set_type(global_space); decode_space(space,thread,src1,mem,addr); - // store nonzero entries + // store nonzero entries and indices for (int tid = 0; tid < NUM_THREADS; tid++) { if (sstarr_fdata[tid] != 0) { + float ftid = (float)tid; mem->write(addr+(offset*4),size/8,&sstarr_ldata[tid],thread,pI); + mem->write(addr+((NUM_THREADS+offset)*4),size/8,&ftid,thread,pI); offset++; } } // store the return address - data = thread->get_operand_value(src1, dst, type, thread, 1); - data.s64 += 4*(offset-1); // set address to the last spot in the sparse array + //data = thread->get_operand_value(src1, dst, type, thread, 1); + //data.s64 += 4*(offset-1); // set address to the last spot in the sparse array + data.s64 = offset-1; thread->set_operand_value(dst, data, type, thread, pI); // fill the rest of the array with zeros (dst should always have a 0 in it) while (offset < NUM_THREADS) { mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI); + mem->write(addr+((NUM_THREADS+offset)*4),size/8,&dst_data.s64,thread,pI); offset++; } -- cgit v1.3 From 1cb439dad25261b0b9617a8fb3e943cf0e0beac1 Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 7 Jul 2016 14:56:16 -0700 Subject: sst_impl cleanup --- src/cuda-sim/instructions.cc | 30 ++++++++++-------------------- 1 file changed, 10 insertions(+), 20 deletions(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 5a7382a..aeaf9e6 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3741,11 +3741,12 @@ void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { - // Step 1: store data in sstarr memory + const operand_info &dst = pI->dst(); const operand_info &src1 = pI->src1(); const operand_info &src2 = pI->src2(); const operand_info &src3 = pI->src3(); unsigned type = pI->get_type(); + ptx_reg_t dst_data = thread->get_operand_value(dst, dst, type, thread, 1); ptx_reg_t src1_data = thread->get_operand_value(src1, src1, type, thread, 1); ptx_reg_t src2_data = thread->get_operand_value(src2, src1, type, thread, 1); ptx_reg_t src3_data = thread->get_operand_value(src3, src1, type, thread, 1); @@ -3759,37 +3760,29 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) int t; type_info_key::type_decode(type,size,t); + // store data in sstarr memory mem->write(addr,size/8,&src3_data.s64,thread,pI); - // Step 2: __syncthreads() to make sure all data is stored in sstarr memory - // (function must be called with dst = 0 so that all threads execute bar.sync 0) - ptx_instruction * cpI = const_cast(pI); - const operand_info &dst = cpI->dst(); - ptx_reg_t dst_data; - dst_data = thread->get_operand_value(dst, dst, U32_TYPE, thread, 1); - cpI->set_bar_id(dst_data.u32); - - thread->m_last_dram_callback.function = bar_callback; - thread->m_last_dram_callback.instruction = pI; - + thread->m_last_effective_address = addr; + thread->m_last_memory_space = space; int NUM_THREADS = 8; // (how do you get this dynamically?) if (src2_data.s64 == NUM_THREADS-1) { - // Step 3: pick only one thread to load all of the data back from sstarr memory - long long offset = 0; + // pick only one thread to load all of the data back from sstarr memory + unsigned offset = 0; addr -= (NUM_THREADS-1)*4; ptx_reg_t data; float sstarr_fdata[NUM_THREADS]; signed long long sstarr_ldata[NUM_THREADS]; // loop through all of the threads - for (short tid = 0; tid < NUM_THREADS; tid++) { + for (int tid = 0; tid < NUM_THREADS; tid++) { data.u64=0; mem->read(addr+(tid*4),size/8,&data.s64); sstarr_fdata[tid] = data.f32; sstarr_ldata[tid] = data.s64; } - // Step 4: squeeze the zeros out of the array and store data back into original array + // squeeze the zeros out of the array and store data back into original array mem = NULL; addr = src1_data.u32; space.set_type(global_space); @@ -3803,10 +3796,7 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) offset++; } } - - // store the return address - //data = thread->get_operand_value(src1, dst, type, thread, 1); - //data.s64 += 4*(offset-1); // set address to the last spot in the sparse array + // store the number of nonzero elements in the array data.s64 = offset-1; thread->set_operand_value(dst, data, type, thread, pI); -- cgit v1.3 From 877cbd077ffaf112b68973fdb7db8f10505303ee Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 8 Jul 2016 12:57:56 -0700 Subject: SST should now properly simulate the barrier operation --- src/cuda-sim/cuda-sim.cc | 4 ++++ src/cuda-sim/instructions.cc | 8 +++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 57da23f..e194a2a 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -572,6 +572,9 @@ void ptx_instruction::set_bar_type() abort(); } } + else if(m_opcode==SST_OP) { + bar_type = SYNC; + } } @@ -635,6 +638,7 @@ void ptx_instruction::set_opcode_and_latency() case TEX_OP: op = LOAD_OP; mem_op=TEX; break; case ATOM_OP: op = LOAD_OP; break; case BAR_OP: op = BARRIER_OP; break; + case SST_OP: op = BARRIER_OP; break; case MEMBAR_OP: op = MEMORY_BARRIER_OP; break; case CALL_OP: { diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index aeaf9e6..8bdb94f 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3741,7 +3741,8 @@ void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { - const operand_info &dst = pI->dst(); + ptx_instruction * cpI = const_cast(pI); // constant + const operand_info &dst = cpI->dst(); const operand_info &src1 = pI->src1(); const operand_info &src2 = pI->src2(); const operand_info &src3 = pI->src3(); @@ -3763,8 +3764,13 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) // store data in sstarr memory mem->write(addr,size/8,&src3_data.s64,thread,pI); + // sync threads + cpI->set_bar_id(dst_data.u32); + thread->m_last_effective_address = addr; thread->m_last_memory_space = space; + thread->m_last_dram_callback.function = bar_callback; + thread->m_last_dram_callback.instruction = cpI; int NUM_THREADS = 8; // (how do you get this dynamically?) if (src2_data.s64 == NUM_THREADS-1) { -- cgit v1.3 From 6c1fb702e17b00fd7de72ac7dd4a31584d5978b9 Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 8 Jul 2016 14:51:44 -0700 Subject: Made gridDim and blockDim global variables so that they can be accessed from sst_impl --- libcuda/cuda_runtime_api.cc | 7 +++++-- src/abstract_hardware_model.h | 3 +++ src/cuda-sim/instructions.cc | 3 +-- src/cuda-sim/opcodes.def | 2 +- 4 files changed, 10 insertions(+), 5 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index e8a0e91..3eff4af 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -180,6 +180,9 @@ cudaError_t g_last_cudaError = cudaSuccess; extern stream_manager *g_stream_manager; +dim3 gridDim = (dim3){1,1,1}; +dim3 blockDim = (dim3){1,1,1}; + void register_ptx_function( const char *name, function_info *impl ) { // no longer need this @@ -959,8 +962,8 @@ __host__ cudaError_t CUDARTAPI cudaLaunch( const char *hostFun ) g_ptx_sim_mode?"functional simulation":"performance simulation", stream?stream->get_uid():0 ); kernel_info_t *grid = gpgpu_cuda_ptx_sim_init_grid(hostFun,config.get_args(),config.grid_dim(),config.block_dim(),context); std::string kname = grid->name(); - dim3 gridDim = config.grid_dim(); - dim3 blockDim = config.block_dim(); + gridDim = config.grid_dim(); + blockDim = config.block_dim(); printf("GPGPU-Sim PTX: pushing kernel \'%s\' to stream %u, gridDim= (%u,%u,%u) blockDim = (%u,%u,%u) \n", kname.c_str(), stream?stream->get_uid():0, gridDim.x,gridDim.y,gridDim.z,blockDim.x,blockDim.y,blockDim.z ); stream_operation op(grid,g_ptx_sim_mode,stream); diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 6ed9b8e..46c3279 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -162,6 +162,9 @@ struct dim3 { }; #endif +extern dim3 gridDim; +extern dim3 blockDim; + void increment_x_then_y_then_z( dim3 &i, const dim3 &bound); class kernel_info_t { diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 8bdb94f..fd3b1fa 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3772,7 +3772,7 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) thread->m_last_dram_callback.function = bar_callback; thread->m_last_dram_callback.instruction = cpI; - int NUM_THREADS = 8; // (how do you get this dynamically?) + int NUM_THREADS = blockDim.x * blockDim.y * blockDim.z; if (src2_data.s64 == NUM_THREADS-1) { // pick only one thread to load all of the data back from sstarr memory unsigned offset = 0; @@ -3809,7 +3809,6 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) // fill the rest of the array with zeros (dst should always have a 0 in it) while (offset < NUM_THREADS) { mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI); - mem->write(addr+((NUM_THREADS+offset)*4),size/8,&dst_data.s64,thread,pI); offset++; } diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 0c0eda9..1af04ea 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -103,7 +103,7 @@ OP_DEF(SHR_OP,shr_impl,"shr",1,1) OP_DEF(SIN_OP,sin_impl,"sin",1,4) OP_DEF(SLCT_OP,slct_impl,"slct",1,1) OP_DEF(SQRT_OP,sqrt_impl,"sqrt",1,4) -OP_DEF(SST_OP,sst_impl,"sst",1,1) +OP_DEF(SST_OP,sst_impl,"sst",1,5) OP_DEF(SSY_OP,ssy_impl,"ssy",0,3) OP_DEF(ST_OP,st_impl,"st",0,5) OP_DEF(SUB_OP,sub_impl,"sub",1,1) -- cgit v1.3 From adc311951d67b0685ebf2fab4ce6410f96f0039a Mon Sep 17 00:00:00 2001 From: sspenst Date: Mon, 11 Jul 2016 11:16:46 -0700 Subject: Reverted the previous commit to add a cleaner way of getting NUM_THREADS. Now, sst_impl doesn't functionally execute on the last indexed element of an array, but instead on the actual last thread that executes --- libcuda/cuda_runtime_api.cc | 7 ++----- src/abstract_hardware_model.h | 3 --- src/cuda-sim/instructions.cc | 13 ++++++++----- src/cuda-sim/ptx_sim.cc | 16 ++++++++++++++++ src/cuda-sim/ptx_sim.h | 4 ++++ 5 files changed, 30 insertions(+), 13 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 3eff4af..e8a0e91 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -180,9 +180,6 @@ cudaError_t g_last_cudaError = cudaSuccess; extern stream_manager *g_stream_manager; -dim3 gridDim = (dim3){1,1,1}; -dim3 blockDim = (dim3){1,1,1}; - void register_ptx_function( const char *name, function_info *impl ) { // no longer need this @@ -962,8 +959,8 @@ __host__ cudaError_t CUDARTAPI cudaLaunch( const char *hostFun ) g_ptx_sim_mode?"functional simulation":"performance simulation", stream?stream->get_uid():0 ); kernel_info_t *grid = gpgpu_cuda_ptx_sim_init_grid(hostFun,config.get_args(),config.grid_dim(),config.block_dim(),context); std::string kname = grid->name(); - gridDim = config.grid_dim(); - blockDim = config.block_dim(); + dim3 gridDim = config.grid_dim(); + dim3 blockDim = config.block_dim(); printf("GPGPU-Sim PTX: pushing kernel \'%s\' to stream %u, gridDim= (%u,%u,%u) blockDim = (%u,%u,%u) \n", kname.c_str(), stream?stream->get_uid():0, gridDim.x,gridDim.y,gridDim.z,blockDim.x,blockDim.y,blockDim.z ); stream_operation op(grid,g_ptx_sim_mode,stream); diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 46c3279..6ed9b8e 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -162,9 +162,6 @@ struct dim3 { }; #endif -extern dim3 gridDim; -extern dim3 blockDim; - void increment_x_then_y_then_z( dim3 &i, const dim3 &bound); class kernel_info_t { diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index fd3b1fa..b5a3db4 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3754,6 +3754,7 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) memory_space_t space = pI->get_space(); memory_space *mem = NULL; addr_t addr = src2_data.u32 * 4; // this assumes sstarr memory starts at address 0 + ptx_cta_info *cta_info = thread->m_cta_info; decode_space(space,thread,src1,mem,addr); @@ -3765,18 +3766,19 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) mem->write(addr,size/8,&src3_data.s64,thread,pI); // sync threads - cpI->set_bar_id(dst_data.u32); + cpI->set_bar_id(16); // use 16 for sst because bar uses an int from 0-15 thread->m_last_effective_address = addr; thread->m_last_memory_space = space; thread->m_last_dram_callback.function = bar_callback; thread->m_last_dram_callback.instruction = cpI; - int NUM_THREADS = blockDim.x * blockDim.y * blockDim.z; - if (src2_data.s64 == NUM_THREADS-1) { - // pick only one thread to load all of the data back from sstarr memory + // the last thread that executes loads all of the data back from sstarr memory + int NUM_THREADS = cta_info->num_threads(); + cta_info->inc_bar_threads(); + if (NUM_THREADS == cta_info->get_bar_threads()) { unsigned offset = 0; - addr -= (NUM_THREADS-1)*4; + addr = 0; ptx_reg_t data; float sstarr_fdata[NUM_THREADS]; signed long long sstarr_ldata[NUM_THREADS]; @@ -3812,6 +3814,7 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) offset++; } + cta_info->reset_bar_threads(); thread->m_last_effective_address = addr+(NUM_THREADS-1)*4; thread->m_last_memory_space = space; } diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc index 511e8d6..f48115b 100644 --- a/src/cuda-sim/ptx_sim.cc +++ b/src/cuda-sim/ptx_sim.cc @@ -44,6 +44,7 @@ ptx_cta_info::ptx_cta_info( unsigned sm_idx ) m_sm_idx = sm_idx; m_uid = g_ptx_cta_info_uid++; + m_bar_threads = 0; } void ptx_cta_info::add_thread( ptx_thread_info *thd ) @@ -128,6 +129,21 @@ unsigned ptx_cta_info::get_sm_idx() const return m_sm_idx; } +unsigned ptx_cta_info::get_bar_threads() const +{ + return m_bar_threads; +} + +void ptx_cta_info::inc_bar_threads() +{ + m_bar_threads++; +} + +void ptx_cta_info::reset_bar_threads() +{ + m_bar_threads = 0; +} + unsigned g_ptx_thread_info_uid_next=1; unsigned g_ptx_thread_info_delete_count=0; diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index c66b68c..4e748e9 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -158,8 +158,12 @@ public: void register_thread_exit( ptx_thread_info *thd ); void register_deleted_thread( ptx_thread_info *thd ); unsigned get_sm_idx() const; + unsigned get_bar_threads() const; + void inc_bar_threads(); + void reset_bar_threads(); private: + unsigned m_bar_threads; unsigned long long m_uid; unsigned m_sm_idx; std::set m_threads_in_cta; -- cgit v1.3 From e08fc0294fe919a198477b771a414c5102430188 Mon Sep 17 00:00:00 2001 From: sspenst Date: Mon, 11 Jul 2016 11:40:23 -0700 Subject: Changed sst return value to be the address instead of index offset --- src/cuda-sim/instructions.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index b5a3db4..b401bef 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3805,7 +3805,8 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) } } // store the number of nonzero elements in the array - data.s64 = offset-1; + data = thread->get_operand_value(src1, dst, type, thread, 1); + data.s64 += 4*(offset-1); thread->set_operand_value(dst, data, type, thread, pI); // fill the rest of the array with zeros (dst should always have a 0 in it) -- cgit v1.3 From feda07a5e0053ef2f2bfa382f5ba9a7a0b6c6bf5 Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 4 Aug 2016 13:09:41 -0700 Subject: A thread executing BSMAD is now able to access information from all threads in its warp --- src/abstract_hardware_model.h | 1 + src/cuda-sim/cuda-sim.cc | 14 ++++ src/cuda-sim/instructions.cc | 158 ++++++++++++++++++++++++++++++++++++++++++ src/cuda-sim/opcodes.def | 3 + src/cuda-sim/opcodes.h | 4 +- src/cuda-sim/ptx.l | 3 + 6 files changed, 182 insertions(+), 1 deletion(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 6ed9b8e..13dfce3 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1053,6 +1053,7 @@ class core_t { warp_inst_t getExecuteWarp(unsigned warpId); void get_pdom_stack_top_info( unsigned warpId, unsigned *pc, unsigned *rpc ) const; kernel_info_t * get_kernel_info(){ return m_kernel;} + class ptx_thread_info ** get_thread_info() { return m_thread; } unsigned get_warp_size() const { return m_warp_size; } void and_reduction(unsigned ctaid, unsigned barid, bool value) { reduction_storage[ctaid][barid] &= value; } void or_reduction(unsigned ctaid, unsigned barid, bool value) { reduction_storage[ctaid][barid] |= value; } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index e194a2a..059fbe2 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -849,8 +849,10 @@ void ptx_instruction::pre_decode() switch ( get_opcode() ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; #include "opcodes.def" #undef OP_DEF +#undef OP_W_DEF default: printf( "Execution error: Invalid opcode (0x%x)\n", get_opcode() ); break; @@ -1242,10 +1244,22 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) *((warp_inst_t*)pJ) = inst; // copy active mask information pI = pJ; } + /*const ptx_instruction **pA; + if( pI->get_opcode() == BSMAD_OP ) { + //pA = (const ptx_instruction**)malloc(get_core()->get_warp_size()*(sizeof(ptx_instruction*))); + pA = (const ptx_instruction**)malloc(8*(sizeof(ptx_instruction*))); + for (int i = 0; i < get_core()->get_warp_size() && inst.active(i); i++) { + //pA[i] = get_core()->get_thread_info()[inst.warp_id() * get_core()->get_warp_size() + i]->func_info()->get_instruction(pc+(i-lane_id)*(pI->inst_size())); + int tid = inst.warp_id() * get_core()->get_warp_size() + i; + pA[i] = get_core()->get_thread_info()[tid]->func_info()->get_instruction(pc); + } + }*/ switch ( pI->get_opcode() ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; #include "opcodes.def" #undef OP_DEF +#undef OP_W_DEF default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break; } delete pJ; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index b401bef..618add1 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -47,8 +47,10 @@ unsigned ptx_instruction::g_num_ptx_inst_uid=0; const char *g_opcode_string[NUM_OPCODES] = { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, #include "opcodes.def" #undef OP_DEF +#undef OP_W_DEF }; void inst_not_implemented( const ptx_instruction * pI ) ; @@ -1456,6 +1458,162 @@ void breakaddr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void brev_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) +{ + for (int i = 0; i < core->get_warp_size() && inst.active(i); i++) { + const operand_info &dst = pI->dst(); + unsigned type = pI->get_type(); + + int tid = inst.warp_id() * core->get_warp_size() + i; + ptx_thread_info *thread = core->get_thread_info()[tid]; + ptx_reg_t data = thread->get_operand_value(dst, dst, type, thread, 1); + printf("BSMAD - DATA FROM THREAD %d: %d\n", i, data.u32); + } + printf("\n"); + /*const unsigned OPERANDS = 9; + // 0 = output + // 1 = input precision + // 2 = output precision + // 3 = buffer0 + // 4 = buffer1 + // 5 = buffer2 + // 6 = buffer3 + // 7 = synapse value + // 8 = output value + // as a temporary solution, let 0 be the base address of output, which is an array of shared memory + // that will be filled when the last thread completes the bsmad instruction + // maybe you can store the addresses of other ptx_instruction in sstarr memory and then update dst later? + // not sure if that works + + //ptx_instruction * cpI = const_cast(pI); + const operand_info &src[OPERANDS]; + ptx_reg_t src_data[OPERANDS]; + unsigned type = pI->get_type(); + + for (int i = 0; i < OPERANDS; i++) { + src[i] = pI->operand_lookup(i); + src_data[i] = thread->get_operand_value(src[i], src[0], type, thread, 1); + } + + memory_space_t space = pI->get_space(); + memory_space *mem = NULL; + addr_t addr = thread->get_tid().x * 24; // 4 bytes per register * 6 registers per thread = 24 bytes + + decode_space(space,thread,src[0],mem,addr); + + size_t size; + int t; + type_info_key::type_decode(type,size,t); + + // store src_data[1:4] in sstarr memory + for (int i = 0; i < 6; i++) { + mem->write(addr + i*4,size/8,&src_data[i+3].s64,thread,pI); + } + + // sync threads + //cpI->set_bar_id(16); // use 16 for sst because bar uses an int from 0-15 + + thread->m_last_effective_address = addr; + thread->m_last_memory_space = space; + thread->m_last_dram_callback.function = bar_callback; + thread->m_last_dram_callback.instruction = cpI; + + // the last thread that executes loads all of the data back from sstarr memory + ptx_cta_info *cta_info = thread->m_cta_info;((32/ip)*4)/(32/op) + const int NUM_THREADS = cta_info->num_threads(); + cta_info->inc_bar_threads(); + if (NUM_THREADS == cta_info->get_bar_threads()) { + // load all things from sstarr memory + addr = 0; + ptx_reg_t data; + unsigned sstarr_data[NUM_THREADS*6]; + for (int i = 0; i < NUM_THREADS*6; i++) { + data.u64 = 0; + mem->read(addr+(i*4),size/8,&data.s64); + sstarr_data[i] = data.u32; + } + + // unpack registers, add data from across threads + unsigned ip = src_data[1].u32; + unsigned op = src_data[2].u32; + unsigned unpacked_output[(32/ip)*4]; + + for (unsigned i = 0; i < (32/ip)*4; i++) { + unsigned buf = i/(32/ip); + unsigned pos = i%(32/ip); + + unsigned mask = 0; + for (int b = 0; b < ip; b++) { + mask |= (1 << b); + } + mask <<= (pos*ip); + + int sum = 0; + for (int j = 0; j < NUM_THREADS; j++) { + sum += mask & sstarr_data[j*6 + buf]; + } + unpacked_output[i] = sum; + } + + // truncate result, repack, store in shared mem + unsigned output_regs[((32/ip)*4)/(32/op) + (((32/ip)*4)%(32/op) != 0)]; + + + + unsigned offset = 0; + addr = 0; + ptx_reg_t data; + float sstarr_fdata[NUM_THREADS]; + signed long long sstarr_ldata[NUM_THREADS]; + // loop through all of the threads + for (int tid = 0; tid < NUM_THREADS; tid++) { + data.u64=0; + mem->read(addr+(tid*4),size/8,&data.s64); + sstarr_fdata[tid] = data.f32; + sstarr_ldata[tid] = data.s64; + } + + // squeeze the zeros out of the array and store data back into original array + mem = NULL; + addr = src1_data.u32; + space.set_type(global_space); + decode_space(space,thread,src1,mem,addr); + // store nonzero entries and indices + for (int tid = 0; tid < NUM_THREADS; tid++) { + if (sstarr_fdata[tid] != 0) { + float ftid = (float)tid; + mem->write(addr+(offset*4),size/8,&sstarr_ldata[tid],thread,pI); + mem->write(addr+((NUM_THREADS+offset)*4),size/8,&ftid,thread,pI); + offset++; + } + } + // store the number of nonzero elements in the array + data = thread->get_op((32/ip)*4)/(32/op)erand_value(src1, dst, type, thread, 1); + data.s64 += 4*(offset-1); + thread->set_operand_value(dst, data, type, thread, pI); + + // fill the rest of the array with zeros (dst should always have a 0 in it) + while (offset < NUM_THREADS) { + mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI); + offset++; + } + + cta_info->reset_bar_threads(); + thread->m_last_effective_address = addr+(NUM_THREADS-1)*4; + thread->m_last_memory_space = space; + }*/ +} + +void bsmul_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + printf("BSMUL instruction found.\n"); +} + +void buf_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + printf("BUF instruction found.\n"); +} + void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { static unsigned call_uid_next = 1; diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 1af04ea..d0e6f25 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -52,6 +52,9 @@ OP_DEF(BRA_OP,bra_impl,"bra",0,3) OP_DEF(BRX_OP,brx_impl,"brx",0,3) OP_DEF(BREV_OP,brev_impl,"brev",1,1) OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9) +OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",0,1) +OP_DEF(BSMUL_OP,bsmul_impl,"bsmul",1,1) +OP_DEF(BUF_OP,buf_impl,"buf",0,5) OP_DEF(CALL_OP,call_impl,"call",1,3) OP_DEF(CALLP_OP,callp_impl,"callp",1,3) OP_DEF(CLZ_OP,clz_impl,"clz",1,1) diff --git a/src/cuda-sim/opcodes.h b/src/cuda-sim/opcodes.h index 871091c..aa133da 100644 --- a/src/cuda-sim/opcodes.h +++ b/src/cuda-sim/opcodes.h @@ -30,9 +30,11 @@ enum opcode_t { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) OP, +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) OP, #include "opcodes.def" - NUM_OPCODES + NUM_OPCODES #undef OP_DEF +#undef OP_W_DEF }; enum special_regs { diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 69349a0..e0d7b9d 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -68,6 +68,9 @@ bra TC; ptx_lval.int_value = BRA_OP; return OPCODE; brx TC; ptx_lval.int_value = BRX_OP; return OPCODE; brev TC; ptx_lval.int_value = BREV_OP; return OPCODE; brkpt TC; ptx_lval.int_value = BRKPT_OP; return OPCODE; +bsmad TC; ptx_lval.int_value = BSMAD_OP; return OPCODE; +bsmul TC; ptx_lval.int_value = BSMUL_OP; return OPCODE; +buf TC; ptx_lval.int_value = BUF_OP; return OPCODE; call TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode callp TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE; clz TC; ptx_lval.int_value = CLZ_OP; return OPCODE; -- cgit v1.3 From 9a6b68c5b11fbdb239d25afe60e5135bc2afa88d Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 5 Aug 2016 10:16:29 -0700 Subject: bsmad gives the correct output in the small cases I have tried, still need to complete the TODOs noted in bsmad_impl --- src/cuda-sim/cuda-sim.cc | 10 -- src/cuda-sim/instructions.cc | 211 +++++++++++++++++++------------------------ src/cuda-sim/opcodes.def | 2 - src/cuda-sim/ptx.l | 2 - 4 files changed, 95 insertions(+), 130 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 059fbe2..337463b 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1244,16 +1244,6 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) *((warp_inst_t*)pJ) = inst; // copy active mask information pI = pJ; } - /*const ptx_instruction **pA; - if( pI->get_opcode() == BSMAD_OP ) { - //pA = (const ptx_instruction**)malloc(get_core()->get_warp_size()*(sizeof(ptx_instruction*))); - pA = (const ptx_instruction**)malloc(8*(sizeof(ptx_instruction*))); - for (int i = 0; i < get_core()->get_warp_size() && inst.active(i); i++) { - //pA[i] = get_core()->get_thread_info()[inst.warp_id() * get_core()->get_warp_size() + i]->func_info()->get_instruction(pc+(i-lane_id)*(pI->inst_size())); - int tid = inst.warp_id() * get_core()->get_warp_size() + i; - pA[i] = get_core()->get_thread_info()[tid]->func_info()->get_instruction(pc); - } - }*/ switch ( pI->get_opcode() ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; #define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 618add1..f58c4f5 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1460,17 +1460,7 @@ void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { - for (int i = 0; i < core->get_warp_size() && inst.active(i); i++) { - const operand_info &dst = pI->dst(); - unsigned type = pI->get_type(); - - int tid = inst.warp_id() * core->get_warp_size() + i; - ptx_thread_info *thread = core->get_thread_info()[tid]; - ptx_reg_t data = thread->get_operand_value(dst, dst, type, thread, 1); - printf("BSMAD - DATA FROM THREAD %d: %d\n", i, data.u32); - } - printf("\n"); - /*const unsigned OPERANDS = 9; + // operands: // 0 = output // 1 = input precision // 2 = output precision @@ -1480,65 +1470,61 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) // 6 = buffer3 // 7 = synapse value // 8 = output value - // as a temporary solution, let 0 be the base address of output, which is an array of shared memory - // that will be filled when the last thread completes the bsmad instruction - // maybe you can store the addresses of other ptx_instruction in sstarr memory and then update dst later? - // not sure if that works - - //ptx_instruction * cpI = const_cast(pI); - const operand_info &src[OPERANDS]; - ptx_reg_t src_data[OPERANDS]; - unsigned type = pI->get_type(); - - for (int i = 0; i < OPERANDS; i++) { - src[i] = pI->operand_lookup(i); - src_data[i] = thread->get_operand_value(src[i], src[0], type, thread, 1); - } - - memory_space_t space = pI->get_space(); - memory_space *mem = NULL; - addr_t addr = thread->get_tid().x * 24; // 4 bytes per register * 6 registers per thread = 24 bytes - - decode_space(space,thread,src[0],mem,addr); - - size_t size; - int t; - type_info_key::type_decode(type,size,t); - - // store src_data[1:4] in sstarr memory - for (int i = 0; i < 6; i++) { - mem->write(addr + i*4,size/8,&src_data[i+3].s64,thread,pI); - } - - // sync threads - //cpI->set_bar_id(16); // use 16 for sst because bar uses an int from 0-15 - - thread->m_last_effective_address = addr; - thread->m_last_memory_space = space; - thread->m_last_dram_callback.function = bar_callback; - thread->m_last_dram_callback.instruction = cpI; - // the last thread that executes loads all of the data back from sstarr memory - ptx_cta_info *cta_info = thread->m_cta_info;((32/ip)*4)/(32/op) + // TODO: what should happen when the output precision is larger than the input precision? + // TODO: create a ptx_warp_info that can do the same thing that ptx_cta_info does here + ptx_cta_info *cta_info = core->get_thread_info()[inst.warp_id() * core->get_warp_size()]->m_cta_info; const int NUM_THREADS = cta_info->num_threads(); + const int NUM_BUFFERS = 4; cta_info->inc_bar_threads(); - if (NUM_THREADS == cta_info->get_bar_threads()) { - // load all things from sstarr memory - addr = 0; - ptx_reg_t data; - unsigned sstarr_data[NUM_THREADS*6]; - for (int i = 0; i < NUM_THREADS*6; i++) { - data.u64 = 0; - mem->read(addr+(i*4),size/8,&data.s64); - sstarr_data[i] = data.u32; - } - // unpack registers, add data from across threads - unsigned ip = src_data[1].u32; - unsigned op = src_data[2].u32; - unsigned unpacked_output[(32/ip)*4]; + // threads within the warp are executed sequentially by the simulator, store output in first four registers + if (cta_info->get_bar_threads() <= NUM_BUFFERS) { + unsigned ip, op; // only get these when i = 0 + unsigned buffer[inst.active_count()][NUM_BUFFERS]; + unsigned synapse[inst.active_count()]; + unsigned output[NUM_BUFFERS]; + + // loop through all threads in the warp and get all data + for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { + if (inst.active(i)) { + const operand_info dst = pI->dst(); + const operand_info src1 = pI->operand_lookup(1); + const operand_info src2 = pI->operand_lookup(2); + const operand_info src3 = pI->operand_lookup(3); + const operand_info src4 = pI->operand_lookup(4); + const operand_info src5 = pI->operand_lookup(5); + const operand_info src6 = pI->operand_lookup(6); + const operand_info src7 = pI->operand_lookup(7); + const operand_info src8 = pI->operand_lookup(8); + unsigned type = pI->get_type(); + + int tid = inst.warp_id() * core->get_warp_size() + i; + ptx_thread_info *thread = core->get_thread_info()[tid]; + + // only get precision data once + if (j == 0) { + ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; + op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; + } + // get buffer data and synapse data from each thread + buffer[j][0] = (thread->get_operand_value(src3, dst, type, thread, 1)).u32; + buffer[j][1] = (thread->get_operand_value(src4, dst, type, thread, 1)).u32; + buffer[j][2] = (thread->get_operand_value(src5, dst, type, thread, 1)).u32; + buffer[j][3] = (thread->get_operand_value(src6, dst, type, thread, 1)).u32; + synapse[j] = (thread->get_operand_value(src7, dst, type, thread, 1)).u32; + // get output data from the first 4 threads + if (j < NUM_BUFFERS) { + output[j] = (thread->get_operand_value(src8, dst, type, thread, 1)).u32; + } + j++; + } + } - for (unsigned i = 0; i < (32/ip)*4; i++) { + // unpack registers, compute enough outputs to fill an output register + unsigned *unpacked_output = (unsigned*)calloc(32/op,sizeof(unsigned)); + unsigned buffer_data_start = (32/op)*(cta_info->get_bar_threads()-1); + for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*NUM_BUFFERS; i++) { unsigned buf = i/(32/ip); unsigned pos = i%(32/ip); @@ -1550,68 +1536,61 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) int sum = 0; for (int j = 0; j < NUM_THREADS; j++) { - sum += mask & sstarr_data[j*6 + buf]; + sum += (mask & buffer[j][buf]) >> (pos*ip); } - unpacked_output[i] = sum; + unpacked_output[i - buffer_data_start] = sum; } - // truncate result, repack, store in shared mem - unsigned output_regs[((32/ip)*4)/(32/op) + (((32/ip)*4)%(32/op) != 0)]; - - + // truncate output + for (unsigned i = 0; i < 32/op; i++) { + int mask = 1, latest_one = -1; + unsigned data = unpacked_output[i]; + for (unsigned j = 0; j < sizeof(unsigned)*8; j++) { + int bit = data & mask; + if (bit == 1) latest_one = j; + data >>= 1; + } + if (latest_one >= op) { + // round_up is 1 if the most significant truncated digit is a 1, otherwise it is 0 + int round_up = (unpacked_output[i] & (1 << (latest_one-op))) >> (latest_one-op); + unsigned shifted_output = unpacked_output[i] >> (latest_one-op+1); + // if shifted_output is a number like 1111, don't round up + if (shifted_output == (pow(2,op)-1)) round_up = 0; + unpacked_output[i] = shifted_output + round_up; + } + } - unsigned offset = 0; - addr = 0; - ptx_reg_t data; - float sstarr_fdata[NUM_THREADS]; - signed long long sstarr_ldata[NUM_THREADS]; - // loop through all of the threads - for (int tid = 0; tid < NUM_THREADS; tid++) { - data.u64=0; - mem->read(addr+(tid*4),size/8,&data.s64); - sstarr_fdata[tid] = data.f32; - sstarr_ldata[tid] = data.s64; + // create mask of 1s + unsigned mask = 0; + for (int b = 0; b < op; b++) { + mask |= (1 << b); } - // squeeze the zeros out of the array and store data back into original array - mem = NULL; - addr = src1_data.u32; - space.set_type(global_space); - decode_space(space,thread,src1,mem,addr); - // store nonzero entries and indices - for (int tid = 0; tid < NUM_THREADS; tid++) { - if (sstarr_fdata[tid] != 0) { - float ftid = (float)tid; - mem->write(addr+(offset*4),size/8,&sstarr_ldata[tid],thread,pI); - mem->write(addr+((NUM_THREADS+offset)*4),size/8,&ftid,thread,pI); - offset++; - } + // pack the outputs into one register + unsigned output_data = 0; + for (int i = 0; i < 32/op; i++) { + output_data |= (unpacked_output[i] & mask) << (op*i); } - // store the number of nonzero elements in the array - data = thread->get_op((32/ip)*4)/(32/op)erand_value(src1, dst, type, thread, 1); - data.s64 += 4*(offset-1); - thread->set_operand_value(dst, data, type, thread, pI); - // fill the rest of the array with zeros (dst should always have a 0 in it) - while (offset < NUM_THREADS) { - mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI); - offset++; + // store the result in the correct thread's output register + for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { + if (inst.active(i)) j++; + if (j == cta_info->get_bar_threads()) { + const operand_info &dst = pI->dst(); + unsigned type = pI->get_type(); + int tid = inst.warp_id() * core->get_warp_size() + i; + ptx_thread_info *thread = core->get_thread_info()[tid]; + ptx_reg_t data; + data.u32 = output_data; + thread->set_operand_value(dst, data, type, thread, pI); + break; + } } + } + if (cta_info->get_bar_threads() == NUM_THREADS) { cta_info->reset_bar_threads(); - thread->m_last_effective_address = addr+(NUM_THREADS-1)*4; - thread->m_last_memory_space = space; - }*/ -} - -void bsmul_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - printf("BSMUL instruction found.\n"); -} - -void buf_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - printf("BUF instruction found.\n"); + } } void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index d0e6f25..021eed8 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -53,8 +53,6 @@ OP_DEF(BRX_OP,brx_impl,"brx",0,3) OP_DEF(BREV_OP,brev_impl,"brev",1,1) OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9) OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",0,1) -OP_DEF(BSMUL_OP,bsmul_impl,"bsmul",1,1) -OP_DEF(BUF_OP,buf_impl,"buf",0,5) OP_DEF(CALL_OP,call_impl,"call",1,3) OP_DEF(CALLP_OP,callp_impl,"callp",1,3) OP_DEF(CLZ_OP,clz_impl,"clz",1,1) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index e0d7b9d..001ec04 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -69,8 +69,6 @@ brx TC; ptx_lval.int_value = BRX_OP; return OPCODE; brev TC; ptx_lval.int_value = BREV_OP; return OPCODE; brkpt TC; ptx_lval.int_value = BRKPT_OP; return OPCODE; bsmad TC; ptx_lval.int_value = BSMAD_OP; return OPCODE; -bsmul TC; ptx_lval.int_value = BSMUL_OP; return OPCODE; -buf TC; ptx_lval.int_value = BUF_OP; return OPCODE; call TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode callp TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE; clz TC; ptx_lval.int_value = CLZ_OP; return OPCODE; -- cgit v1.3 From d1b45cf53a39261663a3eff0d409d6c1220d923d Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 5 Aug 2016 14:45:56 -0700 Subject: Added ptx_warp_info to know how many threads within a warp have executed --- src/abstract_hardware_model.h | 2 + src/cuda-sim/cuda-sim.cc | 10 +++++ src/cuda-sim/instructions.cc | 95 +++++++++++++++++++++++-------------------- src/cuda-sim/ptx_sim.cc | 21 ++++++++++ src/cuda-sim/ptx_sim.h | 12 ++++++ 5 files changed, 95 insertions(+), 45 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 13dfce3..cfa8c9f 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1028,6 +1028,7 @@ class core_t { m_warp_count += 1; } assert( m_warp_count * m_warp_size > 0 ); + //m_warp = ( ptx_warp_info** )calloc( m_warp_count, sizeof( ptx_warp_info* ) ); m_thread = ( ptx_thread_info** ) calloc( m_warp_count * m_warp_size, sizeof( ptx_thread_info* ) ); @@ -1063,6 +1064,7 @@ class core_t { class gpgpu_sim *m_gpu; kernel_info_t *m_kernel; simt_stack **m_simt_stack; // pdom based reconvergence context for each warp + //class ptx_warp_info ** m_warp; class ptx_thread_info ** m_thread; unsigned m_warp_size; unsigned m_warp_count; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 337463b..ba0d00b 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1417,6 +1417,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, static std::map shared_memory_lookup; static std::map sstarr_memory_lookup; static std::map ptx_cta_lookup; + static std::map ptx_warp_lookup; static std::map > local_memory_lookup; if ( *thread_info != NULL ) { @@ -1501,6 +1502,15 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, new_tid += tid; ptx_thread_info *thd = new ptx_thread_info(kernel); + ptx_warp_info *warp_info = NULL; + if ( ptx_warp_lookup.find(hw_warp_id) == ptx_warp_lookup.end() ) { + warp_info = new ptx_warp_info(); // num_threads should be threads in the warp + ptx_warp_lookup[hw_warp_id] = warp_info; + } else { + warp_info = ptx_warp_lookup[hw_warp_id]; + } + thd->m_warp_info = warp_info; + memory_space *local_mem = NULL; std::map::iterator l = local_mem_lookup.find(new_tid); if ( l != local_mem_lookup.end() ) { diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index f58c4f5..9dcc25c 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1471,74 +1471,81 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) // 7 = synapse value // 8 = output value - // TODO: what should happen when the output precision is larger than the input precision? - // TODO: create a ptx_warp_info that can do the same thing that ptx_cta_info does here - ptx_cta_info *cta_info = core->get_thread_info()[inst.warp_id() * core->get_warp_size()]->m_cta_info; - const int NUM_THREADS = cta_info->num_threads(); - const int NUM_BUFFERS = 4; - cta_info->inc_bar_threads(); + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + unsigned type = pI->get_type(); + int tid = inst.warp_id() * core->get_warp_size(); + ptx_thread_info *thread = core->get_thread_info()[tid]; + const int ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; + const int op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; + const int THREADS = inst.active_count(); + const int INBUFFERS = 4; + const int OUTBUFFERS = (((32/ip)*INBUFFERS) / (32/op)) + ((((32/ip)*INBUFFERS) % (32/op)) != 0); + if (OUTBUFFERS > THREADS) { + printf("GPGPU-Sim PTX: BSMAD ERROR - Number of output registers required (%d) is greater than the number available (%d)\n", OUTBUFFERS, THREADS); + abort(); + } + ptx_warp_info *warp_info = core->get_thread_info()[inst.warp_id() * core->get_warp_size()]->m_warp_info; + warp_info->inc_done_threads(); // threads within the warp are executed sequentially by the simulator, store output in first four registers - if (cta_info->get_bar_threads() <= NUM_BUFFERS) { - unsigned ip, op; // only get these when i = 0 - unsigned buffer[inst.active_count()][NUM_BUFFERS]; + if (warp_info->get_done_threads() <= OUTBUFFERS) { + unsigned buffer[inst.active_count()][INBUFFERS]; unsigned synapse[inst.active_count()]; - unsigned output[NUM_BUFFERS]; + unsigned output; // loop through all threads in the warp and get all data for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { if (inst.active(i)) { - const operand_info dst = pI->dst(); - const operand_info src1 = pI->operand_lookup(1); - const operand_info src2 = pI->operand_lookup(2); - const operand_info src3 = pI->operand_lookup(3); - const operand_info src4 = pI->operand_lookup(4); - const operand_info src5 = pI->operand_lookup(5); - const operand_info src6 = pI->operand_lookup(6); - const operand_info src7 = pI->operand_lookup(7); - const operand_info src8 = pI->operand_lookup(8); - unsigned type = pI->get_type(); - - int tid = inst.warp_id() * core->get_warp_size() + i; - ptx_thread_info *thread = core->get_thread_info()[tid]; - - // only get precision data once - if (j == 0) { - ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; - op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; - } + const operand_info &src3 = pI->operand_lookup(3); + const operand_info &src4 = pI->operand_lookup(4); + const operand_info &src5 = pI->operand_lookup(5); + const operand_info &src6 = pI->operand_lookup(6); + const operand_info &src7 = pI->operand_lookup(7); + const operand_info &src8 = pI->operand_lookup(8); + + thread = core->get_thread_info()[tid+i]; // get buffer data and synapse data from each thread buffer[j][0] = (thread->get_operand_value(src3, dst, type, thread, 1)).u32; buffer[j][1] = (thread->get_operand_value(src4, dst, type, thread, 1)).u32; buffer[j][2] = (thread->get_operand_value(src5, dst, type, thread, 1)).u32; buffer[j][3] = (thread->get_operand_value(src6, dst, type, thread, 1)).u32; synapse[j] = (thread->get_operand_value(src7, dst, type, thread, 1)).u32; + j++; // get output data from the first 4 threads - if (j < NUM_BUFFERS) { - output[j] = (thread->get_operand_value(src8, dst, type, thread, 1)).u32; + if (j == warp_info->get_done_threads()) { + output = (thread->get_operand_value(src8, dst, type, thread, 1)).u32; } - j++; } } // unpack registers, compute enough outputs to fill an output register unsigned *unpacked_output = (unsigned*)calloc(32/op,sizeof(unsigned)); - unsigned buffer_data_start = (32/op)*(cta_info->get_bar_threads()-1); - for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*NUM_BUFFERS; i++) { + unsigned buffer_data_start = (32/op)*(warp_info->get_done_threads()-1); + for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*INBUFFERS; i++) { unsigned buf = i/(32/ip); unsigned pos = i%(32/ip); - unsigned mask = 0; + int sum = 0; + // sum values from the buffers for (int b = 0; b < ip; b++) { mask |= (1 << b); } mask <<= (pos*ip); - int sum = 0; - for (int j = 0; j < NUM_THREADS; j++) { + for (int j = 0; j < THREADS; j++) { sum += (mask & buffer[j][buf]) >> (pos*ip); } - unpacked_output[i - buffer_data_start] = sum; + // get the previous output + mask = 0; + for (int b = 0; b < op; b++) { + mask |= (1 << b); + } + mask <<= (op*(i-buffer_data_start)); + int past_output = (mask & output) >> (op*(i-buffer_data_start)); + + unpacked_output[i-buffer_data_start] = sum + past_output; } // truncate output @@ -1575,11 +1582,8 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) // store the result in the correct thread's output register for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { if (inst.active(i)) j++; - if (j == cta_info->get_bar_threads()) { - const operand_info &dst = pI->dst(); - unsigned type = pI->get_type(); - int tid = inst.warp_id() * core->get_warp_size() + i; - ptx_thread_info *thread = core->get_thread_info()[tid]; + if (j == warp_info->get_done_threads()) { + thread = core->get_thread_info()[tid+i]; ptx_reg_t data; data.u32 = output_data; thread->set_operand_value(dst, data, type, thread, pI); @@ -1588,8 +1592,9 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) } } - if (cta_info->get_bar_threads() == NUM_THREADS) { - cta_info->reset_bar_threads(); + // once the warp has finished, set the number of completed threads back to 0 for the next warp + if (warp_info->get_done_threads() == THREADS) { + warp_info->reset_done_threads(); } } diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc index f48115b..820287d 100644 --- a/src/cuda-sim/ptx_sim.cc +++ b/src/cuda-sim/ptx_sim.cc @@ -144,6 +144,26 @@ void ptx_cta_info::reset_bar_threads() m_bar_threads = 0; } +ptx_warp_info::ptx_warp_info() +{ + reset_done_threads(); +} + +unsigned ptx_warp_info::get_done_threads() const +{ + return m_done_threads; +} + +void ptx_warp_info::inc_done_threads() +{ + m_done_threads++; +} + +void ptx_warp_info::reset_done_threads() +{ + m_done_threads = 0; +} + unsigned g_ptx_thread_info_uid_next=1; unsigned g_ptx_thread_info_delete_count=0; @@ -170,6 +190,7 @@ ptx_thread_info::ptx_thread_info( kernel_info_t &kernel ) m_branch_taken = 0; m_shared_mem = NULL; m_sstarr_mem = NULL; + m_warp_info = NULL; m_cta_info = NULL; m_local_mem = NULL; m_symbol_table = NULL; diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index 4e748e9..c62fa57 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -171,6 +171,17 @@ private: std::set m_dangling_pointers; }; +class ptx_warp_info { +public: + ptx_warp_info(); // add get_core or something, or threads? + unsigned get_done_threads() const; + void inc_done_threads(); + void reset_done_threads(); + +private: + unsigned m_done_threads; +}; + class symbol; struct stack_entry { @@ -430,6 +441,7 @@ public: memory_space *m_shared_mem; memory_space *m_sstarr_mem; memory_space *m_local_mem; + ptx_warp_info *m_warp_info; ptx_cta_info *m_cta_info; ptx_reg_t m_last_set_operand_value; -- cgit v1.3 From de21c009ca25fbbfd460047c3ae8a3cf59c31454 Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 5 Aug 2016 14:50:37 -0700 Subject: Deleted useless comments --- src/abstract_hardware_model.h | 2 -- src/cuda-sim/cuda-sim.cc | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index cfa8c9f..13dfce3 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1028,7 +1028,6 @@ class core_t { m_warp_count += 1; } assert( m_warp_count * m_warp_size > 0 ); - //m_warp = ( ptx_warp_info** )calloc( m_warp_count, sizeof( ptx_warp_info* ) ); m_thread = ( ptx_thread_info** ) calloc( m_warp_count * m_warp_size, sizeof( ptx_thread_info* ) ); @@ -1064,7 +1063,6 @@ class core_t { class gpgpu_sim *m_gpu; kernel_info_t *m_kernel; simt_stack **m_simt_stack; // pdom based reconvergence context for each warp - //class ptx_warp_info ** m_warp; class ptx_thread_info ** m_thread; unsigned m_warp_size; unsigned m_warp_count; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index ba0d00b..53ee25b 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1504,7 +1504,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, ptx_warp_info *warp_info = NULL; if ( ptx_warp_lookup.find(hw_warp_id) == ptx_warp_lookup.end() ) { - warp_info = new ptx_warp_info(); // num_threads should be threads in the warp + warp_info = new ptx_warp_info(); ptx_warp_lookup[hw_warp_id] = warp_info; } else { warp_info = ptx_warp_lookup[hw_warp_id]; -- cgit v1.3 From 8c264f2e77fe628987416269a925bb9930a1b813 Mon Sep 17 00:00:00 2001 From: sspenst Date: Mon, 8 Aug 2016 16:10:43 -0700 Subject: Forgot to multiply by the synapse --- src/abstract_hardware_model.h | 2 +- src/cuda-sim/instructions.cc | 35 ++++++++++++----------------------- 2 files changed, 13 insertions(+), 24 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 13dfce3..c009276 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -788,7 +788,7 @@ public: int src[MAX_REG_OPERANDS]; } arch_reg; //int arch_reg[MAX_REG_OPERANDS]; // register number for bank conflict evaluation - unsigned latency; // operation latency + unsigned latency; // operation latency unsigned initiation_interval; unsigned data_size; // what is the size of the word being operated on? diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 9dcc25c..3b938bb 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1486,13 +1486,13 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) printf("GPGPU-Sim PTX: BSMAD ERROR - Number of output registers required (%d) is greater than the number available (%d)\n", OUTBUFFERS, THREADS); abort(); } - ptx_warp_info *warp_info = core->get_thread_info()[inst.warp_id() * core->get_warp_size()]->m_warp_info; + ptx_warp_info *warp_info = thread->m_warp_info; warp_info->inc_done_threads(); // threads within the warp are executed sequentially by the simulator, store output in first four registers if (warp_info->get_done_threads() <= OUTBUFFERS) { - unsigned buffer[inst.active_count()][INBUFFERS]; - unsigned synapse[inst.active_count()]; + unsigned buffer[THREADS][INBUFFERS]; + unsigned synapse[THREADS]; unsigned output; // loop through all threads in the warp and get all data @@ -1526,25 +1526,15 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*INBUFFERS; i++) { unsigned buf = i/(32/ip); unsigned pos = i%(32/ip); - unsigned mask = 0; - int sum = 0; // sum values from the buffers - for (int b = 0; b < ip; b++) { - mask |= (1 << b); - } - mask <<= (pos*ip); - + int sum = 0; + unsigned mask = (unsigned)(pow(2,ip)-1) << (pos*ip); for (int j = 0; j < THREADS; j++) { - sum += (mask & buffer[j][buf]) >> (pos*ip); + sum += ((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j]; } // get the previous output - mask = 0; - for (int b = 0; b < op; b++) { - mask |= (1 << b); - } - mask <<= (op*(i-buffer_data_start)); + mask = (unsigned)(pow(2,op)-1) << (op*(i-buffer_data_start)); int past_output = (mask & output) >> (op*(i-buffer_data_start)); - unpacked_output[i-buffer_data_start] = sum + past_output; } @@ -1567,13 +1557,8 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) } } - // create mask of 1s - unsigned mask = 0; - for (int b = 0; b < op; b++) { - mask |= (1 << b); - } - // pack the outputs into one register + unsigned mask = pow(2,op)-1; unsigned output_data = 0; for (int i = 0; i < 32/op; i++) { output_data |= (unpacked_output[i] & mask) << (op*i); @@ -1596,6 +1581,10 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) if (warp_info->get_done_threads() == THREADS) { warp_info->reset_done_threads(); } + + // set the latency assuming 4 bits of each input get processed every cycle + // mutable latency variable??? + //pI->latency = (ip+3)/4; } void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -- cgit v1.3 From 45f95f05a11e916933480422b9075767a4cfdf90 Mon Sep 17 00:00:00 2001 From: sspenst Date: Tue, 9 Aug 2016 19:20:02 -0700 Subject: Changed bsmad_impl to match Ahmed's output. Added latency and initiation_interval numbers for bsmad --- src/cuda-sim/cuda-sim.cc | 29 +++++++++++++++++------------ src/cuda-sim/instructions.cc | 30 ++++++++++++++++++++++++++---- src/cuda-sim/opcodes.def | 2 +- 3 files changed, 44 insertions(+), 17 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 53ee25b..4bae236 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -66,9 +66,9 @@ char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp; void ptx_opcocde_latency_options (option_parser_t opp) { option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, - "Opcode latencies for integers " - "Default 1,1,19,25,145", - "1,1,19,25,145"); + "Opcode latencies for integers " + "Default 1,1,19,25,145,1", + "1,1,19,25,145,1"); option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp, "Opcode latencies for single precision floating points " "Default 1,1,1,1,30", @@ -78,9 +78,9 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Default 8,8,8,8,335", "8,8,8,8,335"); option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, - "Opcode initiation intervals for integers " - "Default 1,1,4,4,32", - "1,1,4,4,32"); + "Opcode initiation intervals for integers " + "Default 1,1,4,4,32,1", + "1,1,4,4,32,1"); option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp, "Opcode initiation intervals for single precision floating points " "Default 1,1,1,1,5", @@ -580,10 +580,10 @@ void ptx_instruction::set_bar_type() void ptx_instruction::set_opcode_and_latency() { - unsigned int_latency[5]; + unsigned int_latency[6]; unsigned fp_latency[5]; unsigned dp_latency[5]; - unsigned int_init[5]; + unsigned int_init[6]; unsigned fp_init[5]; unsigned dp_init[5]; /* @@ -592,19 +592,20 @@ void ptx_instruction::set_opcode_and_latency() * [2] MUL * [3] MAD * [4] DIV + * [5] BSMAD */ - sscanf(opcode_latency_int, "%u,%u,%u,%u,%u", + sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u", &int_latency[0],&int_latency[1],&int_latency[2], - &int_latency[3],&int_latency[4]); + &int_latency[3],&int_latency[4],&int_latency[5]); sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u", &fp_latency[0],&fp_latency[1],&fp_latency[2], &fp_latency[3],&fp_latency[4]); sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u", &dp_latency[0],&dp_latency[1],&dp_latency[2], &dp_latency[3],&dp_latency[4]); - sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u", + sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u", &int_init[0],&int_init[1],&int_init[2], - &int_init[3],&int_init[4]); + &int_init[3],&int_init[4],&int_init[5]); sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u", &fp_init[0],&fp_init[1],&fp_init[2], &fp_init[3],&fp_init[4]); @@ -773,6 +774,10 @@ void ptx_instruction::set_opcode_and_latency() initiation_interval = dp_init[2]; op = SFU_OP; break; + case BSMAD_OP: + latency = int_latency[5]; + initiation_interval = int_init[5]; + break; default: break; } diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 3b938bb..bb15621 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1458,6 +1458,26 @@ void breakaddr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void brev_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +unsigned trunc(unsigned num, unsigned precision) { + int mask = 1, latest_one = -1; + unsigned data = num; + for (unsigned j = 0; j < sizeof(unsigned)*8; j++) { + int bit = data & mask; + if (bit == 1) latest_one = j; + data >>= 1; + } + if (latest_one >= precision) { + // round_up is 1 if the most significant truncated digit is a 1, otherwise it is 0 + //int round_up = (num & (1 << (latest_one-precision))) >> (latest_one-precision); + //unsigned shifted_output = num >> (latest_one-precision+1); + // if shifted_output is a number like 1111, don't round up + //if (shifted_output == (pow(2,precision)-1)) round_up = 0; + //num = shifted_output + round_up; + num >>= (latest_one-precision+1); + } + return num; +} + void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { // operands: @@ -1530,16 +1550,18 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) int sum = 0; unsigned mask = (unsigned)(pow(2,ip)-1) << (pos*ip); for (int j = 0; j < THREADS; j++) { - sum += ((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j]; + //sum += ((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j]; + sum += trunc(((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j], op); } // get the previous output mask = (unsigned)(pow(2,op)-1) << (op*(i-buffer_data_start)); int past_output = (mask & output) >> (op*(i-buffer_data_start)); - unpacked_output[i-buffer_data_start] = sum + past_output; + unpacked_output[i-buffer_data_start] = trunc(trunc(sum,op) + past_output,op); + // truncate sum, truncate (truncated sum + past_output) } // truncate output - for (unsigned i = 0; i < 32/op; i++) { + /*for (unsigned i = 0; i < 32/op; i++) { int mask = 1, latest_one = -1; unsigned data = unpacked_output[i]; for (unsigned j = 0; j < sizeof(unsigned)*8; j++) { @@ -1555,7 +1577,7 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) if (shifted_output == (pow(2,op)-1)) round_up = 0; unpacked_output[i] = shifted_output + round_up; } - } + }*/ // pack the outputs into one register unsigned mask = pow(2,op)-1; diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 021eed8..b363dca 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -52,7 +52,7 @@ OP_DEF(BRA_OP,bra_impl,"bra",0,3) OP_DEF(BRX_OP,brx_impl,"brx",0,3) OP_DEF(BREV_OP,brev_impl,"brev",1,1) OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9) -OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",0,1) +OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",1,1) OP_DEF(CALL_OP,call_impl,"call",1,3) OP_DEF(CALLP_OP,callp_impl,"callp",1,3) OP_DEF(CLZ_OP,clz_impl,"clz",1,1) -- cgit v1.3 From 9ca55c4871597e12a161bedb607308c28ed434e2 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Sun, 9 Jul 2017 22:53:28 -0400 Subject: Fixing backgroup index bug --- src/gpgpu-sim/gpu-sim.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index a2d1b9b..7d92c66 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -195,7 +195,7 @@ struct memory_config { for (i=0; nbkt>0; i++) { nbkt = nbkt>>1; } - bk_tag_length = i; + bk_tag_length = i-1; assert(nbkgrp>0 && "Number of bank groups cannot be zero"); tRCDWR = tRCD-(WL+1); tRTW = (CL+(BL/data_command_freq_ratio)+2-WL); -- cgit v1.3 From 0751c1489add70d7494521c7f9d65f462e4391c6 Mon Sep 17 00:00:00 2001 From: speverel Date: Sun, 24 Sep 2017 21:12:40 -0700 Subject: Changed how warp level instructions are handled to avoid an assert that is guaranteed to fail in functional simulation only mode. Hopefully this shouldn't introduce any new issues. --- src/abstract_hardware_model.h | 4 ++++ src/cuda-sim/instructions.cc | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 607eda7..cdd9cf3 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -980,6 +980,10 @@ public: assert( !m_empty ); return m_warp_id; } + unsigned warp_id_func() const // to be used in functional simulations only + { + return m_warp_id; + } unsigned dynamic_warp_id() const { assert( !m_empty ); diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 159fd4c..493e307 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1500,7 +1500,7 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) const operand_info &src1 = pI->src1(); const operand_info &src2 = pI->src2(); unsigned type = pI->get_type(); - int tid = inst.warp_id() * core->get_warp_size(); + int tid = inst.warp_id_func() * core->get_warp_size(); ptx_thread_info *thread = core->get_thread_info()[tid]; const int ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; const int op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; @@ -3698,7 +3698,7 @@ void set_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void shfl_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { unsigned i_type = pI->get_type(); - int tid = inst.warp_id() * core->get_warp_size(); + int tid = inst.warp_id_func() * core->get_warp_size(); ptx_thread_info *thread = core->get_thread_info()[tid]; ptx_warp_info *warp_info = thread->m_warp_info; int lane = warp_info->get_done_threads(); -- cgit v1.3 From 8735428754d1bb944400922982f41f867f2f9b9c Mon Sep 17 00:00:00 2001 From: speverel Date: Sat, 4 Nov 2017 10:42:32 -0700 Subject: Added basic support for CUDA 9.0. --- Makefile | 1 + setup_environment | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index e83de9a..f0c3da9 100644 --- a/Makefile +++ b/Makefile @@ -161,6 +161,7 @@ $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib if [ ! -f $(SIM_LIB_DIR)/libcudart.so.6.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.6.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.7.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.7.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.8.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.8.0; fi + if [ ! -f $(SIM_LIB_DIR)/libcudart.so.9.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.9.0; fi $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib g++ -dynamiclib -Wl,-headerpad_max_install_names,-undefined,dynamic_lookup,-compatibility_version,1.1,-current_version,1.1\ diff --git a/setup_environment b/setup_environment index 854a335..0b0a6ff 100644 --- a/setup_environment +++ b/setup_environment @@ -43,7 +43,7 @@ CC_VERSION=`gcc --version | head -1 | awk '{for(i=1;i<=NF;i++){ if(match($i,/^[0 CUDA_VERSION_STRING=`$CUDA_INSTALL_PATH/bin/nvcc --version | awk '/release/ {print $5;}' | sed 's/,//'`; CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("%02u%02u", 10*int($1), 10*$2);}'` -if [ $CUDA_VERSION_NUMBER -gt 8000 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then +if [ $CUDA_VERSION_NUMBER -gt 9000 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then echo "ERROR ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; return elif [ $CUDA_VERSION_NUMBER -gt 4020 ]; then -- cgit v1.3 From 7c9b838bca837a3ccea5ea30f53c1cbd8e35252c Mon Sep 17 00:00:00 2001 From: Negar Date: Sun, 12 Nov 2017 19:03:27 -0800 Subject: Fix latency bug --- bsmad_test/.gdbinit | 97 ++ bsmad_test/Makefile | 6 + bsmad_test/bsmad | Bin 0 -> 2660316 bytes bsmad_test/bsmad_result.txt | 333 ++++ bsmad_test/bsmad_test.cu | 76 + bsmad_test/bsmadoutput.txt | 3004 +++++++++++++++++++++++++++++++++++ bsmad_test/config_fermi_islip.icnt | 70 + bsmad_test/d.log | 3049 ++++++++++++++++++++++++++++++++++++ bsmad_test/gpgpu_inst_stats.txt | 26 + bsmad_test/gpgpusim.config | 149 ++ bsmad_test/gpuwattch_gtx1080Ti.xml | 538 +++++++ bsmad_test/out.txt | 1837 ++++++++++++++++++++++ bsmad_test/output | 2338 +++++++++++++++++++++++++++ bsmad_test/output.txt | 2338 +++++++++++++++++++++++++++ bsmad_test/result | 2338 +++++++++++++++++++++++++++ src/cuda-sim/cuda-sim.cc | 30 +- 16 files changed, 16216 insertions(+), 13 deletions(-) create mode 100644 bsmad_test/.gdbinit create mode 100644 bsmad_test/Makefile create mode 100755 bsmad_test/bsmad create mode 100644 bsmad_test/bsmad_result.txt create mode 100644 bsmad_test/bsmad_test.cu create mode 100644 bsmad_test/bsmadoutput.txt create mode 100644 bsmad_test/config_fermi_islip.icnt create mode 100644 bsmad_test/d.log create mode 100644 bsmad_test/gpgpu_inst_stats.txt create mode 100644 bsmad_test/gpgpusim.config create mode 100755 bsmad_test/gpuwattch_gtx1080Ti.xml create mode 100644 bsmad_test/out.txt create mode 100644 bsmad_test/output create mode 100644 bsmad_test/output.txt create mode 100644 bsmad_test/result diff --git a/bsmad_test/.gdbinit b/bsmad_test/.gdbinit new file mode 100644 index 0000000..b456895 --- /dev/null +++ b/bsmad_test/.gdbinit @@ -0,0 +1,97 @@ +# Provides some useful debugging macros. To use this file, copy to your home +# directory or to your simulation directory then run GPGPU-Sim in gdb. + +printf "\n ** loading GPGPU-Sim debugging macros... ** \n\n" + +set print pretty +set print array-indexes +set unwindonsignal on + +define dp + call g_the_gpu->dump_pipeline((0x40|0x4|0x1),$arg0,0) +end + +document dp +Usage: dp +Display pipeline state. +: index of shader core you would like to see the pipeline state of + +This function displays the state of the pipeline on a single shader core +(setting different values for the first argument of the call to +dump_pipeline will cause different information to be displayed-- +see the source code for more details) +end + +define dpc + call g_the_gpu->dump_pipeline((0x40|0x4|0x1),$arg0,0) + continue +end + +document dpc +Usage: dpc +Display pipeline state, then continue to next breakpoint. +: index of shader core you would like to see the pipeline state of + +This version is useful if you set a breakpoint where gpu_sim_cycle is +incremented in gpu_sim_loop() in src/gpgpu-sim/gpu-sim.c +repeatly hitting enter will advance to show the pipeline contents on +the next cycle. +end + +define dm + call g_the_gpu->dump_pipeline(0x10000|0x10000000,0,$arg0) +end + +define ptxdis + set $addr=$arg0 + printf "disassemble instructions from 0x%x to 0x%x\n", $arg0, $arg1 + call fflush(stdout) + while ( $addr <= $arg1 ) + printf "0x%04x (%4u) : ", $addr, $addr + call ptx_print_insn( $addr, stdout ) + call fflush(stdout) + set $addr = $addr + ptx_print_insn::size + end +end + +document ptxdis +Usage: ptxdis +Disassemble PTX instructions between and (PCs). +end + +define ptxdis_func + set $sid = $arg0 + set $cluster = g_the_gpu_config.m_shader_config.sid_to_cluster($sid) + set $cid = g_the_gpu_config.m_shader_config.sid_to_cid($sid) + set $ptx_tinfo = g_the_gpu->m_cluster[$cluster]->m_core[$cid]->m_thread[$arg1] + set $finfo = $ptx_tinfo->m_func_info + set $minpc = $finfo->m_start_PC + set $maxpc = $minpc + $finfo->m_instr_mem_size + printf "disassembly of function %s (min pc = %u, max pc = %u):\n", $finfo->m_name.c_str(), $minpc, $maxpc + ptxdis $minpc $maxpc +end + +document ptxdis_func +Usage: ptxdis_func (requires debug build) +: shader core number +: thread ID +end + +define ptx_tids2pcs + set $i = 0 + while ( $i < $arg1 ) + set $tid = $arg0[$i] + set $cluster = g_the_gpu_config.m_shader_config.sid_to_cluster($sid); + set $cid = g_the_gpu_config.m_shader_config.sid_to_cid($sid); + set $addr = g_the_gpu->m_cluster[$cluster]->m_core[$cid]->m_thread[$tid]->m_PC + printf "%2u : tid = %3u => pc = %d\n", $i, $tid, $addr + set $i = $i + 1 + end +end + +document ptx_tids2pcs +Usage: ptx_tids2pcs +: array of tids +: length of array +: shader core number +end diff --git a/bsmad_test/Makefile b/bsmad_test/Makefile new file mode 100644 index 0000000..b841c6b --- /dev/null +++ b/bsmad_test/Makefile @@ -0,0 +1,6 @@ +all: bsmad_test.cu + nvcc --gpu-architecture=compute_50 --gpu-code=compute_50 -lcudart -g -o bsmad bsmad_test.cu + +.PHONY: +clean: + rm bsmad diff --git a/bsmad_test/bsmad b/bsmad_test/bsmad new file mode 100755 index 0000000..56020ff Binary files /dev/null and b/bsmad_test/bsmad differ diff --git a/bsmad_test/bsmad_result.txt b/bsmad_test/bsmad_result.txt new file mode 100644 index 0000000..968a990 --- /dev/null +++ b/bsmad_test/bsmad_result.txt @@ -0,0 +1,333 @@ +GNU gdb (GDB) SUSE (7.5.1-2.5.1) +Copyright (C) 2012 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. Type "show copying" +and "show warranty" for details. +This GDB was configured as "x86_64-suse-linux". +For bug reporting instructions, please see: +... +Reading symbols from /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad...done. +To enable execution of this file add + add-auto-load-safe-path /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/.gdbinit +line to your configuration file "/home/negargoli93/.gdbinit". +To completely disable this security protection add + set auto-load safe-path / +line to your configuration file "/home/negargoli93/.gdbinit". +For more information about this security protection see the +"Auto-loading safe path" section in the GDB manual. E.g., run from the shell: + info "(gdb)Auto-loading safe path" +(gdb) r^C(gdb) r +Starting program: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +[Thread debugging using libthread_db enabled] +Using host libthread_db library "/lib64/libthread_db.so.1". + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-0751c1489add70d7494521c7f9d65f462e4391c6_modified_0] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace[New Thread 0x7ffff4512700 (LWP 5117)] +[Thread 0x7ffff4512700 (LWP 5117) exited] +[New Thread 0x7ffff4512700 (LWP 5120)] + +Program received signal SIGINT, Interrupt. +0x00007ffff6f78fef in pthread_join () from /lib64/libpthread.so.0 +Missing separate debuginfos, use: zypper install Mesa-libGL1-debuginfo-8.0.4-20.27.1.x86_64 Mesa-libglapi0-debuginfo-8.0.4-20.27.1.x86_64 glibc-debuginfo-2.15-22.17.1.x86_64 libX11-6-debuginfo-1.5.0-2.7.1.x86_64 libX11-xcb1-debuginfo-1.5.0-2.7.1.x86_64 libXau6-debuginfo-1.0.7-2.1.2.x86_64 libXdamage1-debuginfo-1.1.3-2.1.2.x86_64 libXext6-debuginfo-1.3.1-2.4.1.x86_64 libXfixes3-debuginfo-5.0-2.4.1.x86_64 libXxf86vm1-debuginfo-1.1.2-2.7.1.x86_64 libdrm2-debuginfo-2.4.33-2.3.2.x86_64 libgcc47-debuginfo-4.7.1_20120723-1.1.1.x86_64 libstdc++47-debuginfo-4.7.1_20120723-1.1.1.x86_64 libxcb-glx0-debuginfo-1.8.1-2.8.1.x86_64 libxcb1-debuginfo-1.8.1-2.8.1.x86_64 zlib-debuginfo-1.2.7-2.1.2.x86_64 +(gdb) +(gdb) quit +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? (y or n) Please answer y or n. +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? 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(y or n) EOF [assumed Y] diff --git a/bsmad_test/bsmad_test.cu b/bsmad_test/bsmad_test.cu new file mode 100644 index 0000000..9be6e74 --- /dev/null +++ b/bsmad_test/bsmad_test.cu @@ -0,0 +1,76 @@ +#include +#define SIZE 1024 +#define THREADS_PER_BLOCK 32 +#define PART_THREADS 1 +#define NUM_BLOCKS 1 +#define I_PREC 4 +#define O_PREC 4 + +__global__ void vector_add(int* A, int* B, int* res) +{ + int tid = threadIdx.x + blockIdx.x * blockDim.x; + res[tid] = A[tid] + B[tid]; +} + +__global__ void digit_serial_mad(unsigned* i_buffer, unsigned* i_synapse, unsigned* result, unsigned* accum) +{ + unsigned tid = threadIdx.x + blockIdx.x * blockDim.x; + unsigned buffer; + unsigned synapse; + if (tid < PART_THREADS) + { + buffer = i_buffer[tid]; + synapse = i_synapse[tid]; + } + + asm("/*"); + asm("CPTX_BEGIN"); + asm("bsmad.s32 %0, %1, %2, %3, %4, %5, %6, %7, %8;" : "=r"(result[tid]) : + "r"(I_PREC), "r"(O_PREC), "r"(buffer), "r"(0), "r"(0), "r"(0), "r"(synapse), "r"(accum[tid])); + asm("CPTX_END"); + asm("*/"); +} + +int main() +{ + // host values + unsigned *buffer = (unsigned*)malloc(sizeof(unsigned)); + unsigned *synapse = (unsigned*)malloc(sizeof(unsigned)); + unsigned *result = (unsigned*)calloc(THREADS_PER_BLOCK, sizeof(unsigned)); + unsigned *accum = (unsigned*)calloc(THREADS_PER_BLOCK, sizeof(unsigned)); + // assign host values + *buffer = 0x5000003F; + *synapse = 0x00000002; + *accum = 0; + // device pointers + unsigned *d_buffer; + unsigned *d_synapse; + unsigned *d_result; + unsigned *d_accum; + // allocate device memory + cudaMalloc(&d_buffer, sizeof(unsigned)); + cudaMalloc(&d_synapse, sizeof(unsigned)); + cudaMalloc(&d_result, sizeof(unsigned)); + cudaMalloc(&d_accum, sizeof(unsigned)); + // copy data to device + cudaMemcpy(d_buffer, buffer, sizeof(unsigned), cudaMemcpyHostToDevice); + cudaMemcpy(d_synapse, synapse, sizeof(unsigned), cudaMemcpyHostToDevice); + cudaMemcpy(d_result, result, sizeof(unsigned) * THREADS_PER_BLOCK, cudaMemcpyHostToDevice); + cudaMemcpy(d_accum, accum, sizeof(unsigned) * THREADS_PER_BLOCK, cudaMemcpyHostToDevice); + // call kernel + digit_serial_mad<<>>(d_buffer, d_synapse, d_result, d_accum); + // copy data back to host + cudaMemcpy(result, d_result, sizeof(unsigned) * THREADS_PER_BLOCK, cudaMemcpyDeviceToHost); + // read out result + printf("Result: %#X\n", result[0]); + // clean up device memory + cudaFree(d_buffer); + cudaFree(d_synapse); + cudaFree(d_result); + cudaFree(d_accum); + // clean up host memory + free(buffer); + free(synapse); + free(result); + free(accum); +} diff --git a/bsmad_test/bsmadoutput.txt b/bsmad_test/bsmadoutput.txt new file mode 100644 index 0000000..7c5f9d5 --- /dev/null +++ b/bsmad_test/bsmadoutput.txt @@ -0,0 +1,3004 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4 # Opcode latencies for integers Default 1,1,19,25,145,1 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +057a78a8e028f9794c162a7c4e45415d /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_A4Dkbu +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_3lcy4c" +Running: cat _ptx_3lcy4c | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_6DnMXV +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_6DnMXV --output-file /dev/null 2> _ptx_3lcy4cinfo" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_3lcy4c _ptx2_6DnMXV _ptx_3lcy4cinfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 + 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) +bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 17:28:53 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA +GPGPU-Sim uArch: Shader 1 finished CTA #0 (1081,0), 0 CTAs running +GPGPU-Sim uArch: Shader 1 empty (last released kernel 1 '_Z16digit_serial_madPjS_S_S_'). +GPGPU-Sim uArch: GPU detected kernel 1 '_Z16digit_serial_madPjS_S_S_' finished on shader 1. +Destroy streams for kernel 1: size 0 +kernel_name = _Z16digit_serial_madPjS_S_S_ +kernel_launch_uid = 1 +gpu_sim_cycle = 1082 +gpu_sim_insn = 675 +gpu_ipc = 0.6238 +gpu_tot_sim_cycle = 1082 +gpu_tot_sim_insn = 675 +gpu_tot_ipc = 0.6238 +gpu_tot_issued_cta = 1 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=675 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 13 + L1I_total_cache_misses = 2 + L1I_total_cache_miss_rate = 0.1538 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 4 + L1C_total_cache_misses = 4 + L1C_total_cache_miss_rate = 1.0000 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 800 +gpgpu_n_tot_w_icount = 25 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 3 +gpgpu_n_mem_write_global = 1 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 1 +gpgpu_n_load_insn = 34 +gpgpu_n_store_insn = 32 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 128 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:1902 W0_Scoreboard:294 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 +traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} +traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} +traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} +traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} +maxmrqlatency = 7 +maxdqlatency = 0 +maxmflatency = 252 +averagemflatency = 250 +max_icnt2mem_latency = 6 +max_icnt2sh_latency = 1081 +mrq_lat_table:7 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 4 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 750 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 759 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1066 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1038 0 0 0 0 228 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 2.000000 -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan 1.000000 +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 8/6 = 1.333333 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 7 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 1 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 252 none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none 250 none none none none none +dram[2]: none none none none none none none none none none 250 none none none none none +dram[3]: none none none none none none none none none none 122 none none none none none +dram[4]: none none none none none none none none none none 252 none none none none 0 +dram[5]: none none none none none none none none none none none none none none 0 none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 244 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 252 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 +n_activity=40 dram_eff=0.2 +bk0: 4a 1989i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 +n_activity=40 dram_eff=0.2 +bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 4a 1989i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 0a 2007i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 +n_activity=40 dram_eff=0.2 +bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 4a 1989i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 0a 2007i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents +MSHR: tag=0x3e20200, atomic=0 1 entries : 0x7f51d804c750 : mf: uid= 22, sid01:w00, part=3, addr=0x3e20200, load , size=128, unknown status = IN_PARTITION_DRAM (1081), + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2000 n_act=1 n_pre=0 n_req=2 n_rd=3 n_write=4 bw_util=0.006972 +n_activity=29 dram_eff=0.4828 +bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 3a 1979i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 0a 2007i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=1 avg=0.0059761 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=1998 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007968 +n_activity=80 dram_eff=0.2 +bk0: 0a 2006i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 4a 1989i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 4a 1988i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 +n_activity=40 dram_eff=0.2 +bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2009i bk14: 4a 1989i bk15: 0a 2007i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 7 +L2_total_cache_misses = 7 +L2_total_cache_miss_rate = 1.0000 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 3 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 1 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.001 + +icnt_total_pkts_mem_to_simt=23 +icnt_total_pkts_simt_to_mem=11 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = 7.42857 + minimum = 6 + maximum = 10 +Network latency average = 7.42857 + minimum = 6 + maximum = 10 +Slowest packet = 1 +Flit latency average = 6 + minimum = 6 + maximum = 6 +Slowest flit = 0 +Fragmentation average = 0 + minimum = 0 + maximum = 0 +Injected packet rate average = 0.00012951 + minimum = 0 (at node 0) + maximum = 0.00323774 (at node 1) +Accepted packet rate average = 0.00012951 + minimum = 0 (at node 0) + maximum = 0.00323774 (at node 1) +Injected flit rate average = 0.000314524 + minimum = 0 (at node 0) + maximum = 0.00508788 (at node 1) +Accepted flit rate average= 0.000314524 + minimum = 0 (at node 0) + maximum = 0.0106383 (at node 1) +Injected packet length average = 2.42857 +Accepted packet length average = 2.42857 +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Network latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Flit latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Fragmentation average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Injected packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected packet size average = -nan (5 samples) +Accepted packet size average = -nan (5 samples) +Hops average = -nan (5 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- + + +gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 1 sec (1 sec) +gpgpu_simulation_rate = 675 (inst/sec) +gpgpu_simulation_rate = 1082 (cycle/sec) +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 1082 +gpu_tot_sim_insn = 675 +gpu_tot_ipc = 0.6238 +gpu_tot_issued_cta = 1 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=675 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 13 + L1I_total_cache_misses = 2 + L1I_total_cache_miss_rate = 0.1538 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 4 + L1C_total_cache_misses = 4 + L1C_total_cache_miss_rate = 1.0000 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 800 +gpgpu_n_tot_w_icount = 25 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 3 +gpgpu_n_mem_write_global = 1 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 1 +gpgpu_n_load_insn = 34 +gpgpu_n_store_insn = 32 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 128 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:1902 W0_Scoreboard:294 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 +traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} +traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} +traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} +traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} +Result: 0XA000006F diff --git a/bsmad_test/config_fermi_islip.icnt b/bsmad_test/config_fermi_islip.icnt new file mode 100644 index 0000000..2a69ddd --- /dev/null +++ b/bsmad_test/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 50; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/bsmad_test/d.log b/bsmad_test/d.log new file mode 100644 index 0000000..50ba43f --- /dev/null +++ b/bsmad_test/d.log @@ -0,0 +1,3049 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers Default 1,1,19,25,145,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +e1ffbb239b1e632822e743b7e0c60b46 /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_8Ypfya +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_CMkVsP" +Running: cat _ptx_CMkVsP | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_bVrCnu +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_bVrCnu --output-file /dev/null 2> _ptx_CMkVsPinfo" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_CMkVsP _ptx2_bVrCnu _ptx_CMkVsPinfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +Number of Memory Banks Accessed per Memory Operation per Warp (from 0): +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Average # of Memory Banks Accessed per Memory Operation per Warp=-nan + +position of mrq chosen +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +average position of mrq chosen = -nan +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +Number of Memory Banks Accessed per Memory Operation per Warp (from 0): +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Average # of Memory Banks Accessed per Memory Operation per Warp=-nan + +position of mrq chosen +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +average position of mrq chosen = -nan +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +Number of Memory Banks Accessed per Memory Operation per Warp (from 0): +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Average # of Memory Banks Accessed per Memory Operation per Warp=-nan + +position of mrq chosen +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +average position of mrq chosen = -nan +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 + +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) + -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +Number of Memory Banks Accessed per Memory Operation per Warp (from 0): +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Average # of Memory Banks Accessed per Memory Operation per Warp=-nan + +position of mrq chosen +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +average position of mrq chosen = -nan +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 18:22:19 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA +GPGPU-Sim uArch: Shader 1 finished CTA #0 (1079,0), 0 CTAs running +GPGPU-Sim uArch: Shader 1 empty (last released kernel 1 '_Z16digit_serial_madPjS_S_S_'). +GPGPU-Sim uArch: GPU detected kernel 1 '_Z16digit_serial_madPjS_S_S_' finished on shader 1. +Destroy streams for kernel 1: size 0 +kernel_name = _Z16digit_serial_madPjS_S_S_ +kernel_launch_uid = 1 +gpu_sim_cycle = 1080 +gpu_sim_insn = 675 +gpu_ipc = 0.6250 +gpu_tot_sim_cycle = 1080 +gpu_tot_sim_insn = 675 +gpu_tot_ipc = 0.6250 +gpu_tot_issued_cta = 1 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=675 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 13 + L1I_total_cache_misses = 2 + L1I_total_cache_miss_rate = 0.1538 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 4 + L1C_total_cache_misses = 4 + L1C_total_cache_miss_rate = 1.0000 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 800 +gpgpu_n_tot_w_icount = 25 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 3 +gpgpu_n_mem_write_global = 1 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 1 +gpgpu_n_load_insn = 34 +gpgpu_n_store_insn = 32 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 128 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:1900 W0_Scoreboard:292 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 +traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} +traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} +traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} +traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} +maxmrqlatency = 7 +maxdqlatency = 0 +maxmflatency = 252 +averagemflatency = 250 +max_icnt2mem_latency = 6 +max_icnt2sh_latency = 1079 +mrq_lat_table:7 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 4 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 750 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 759 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1064 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1038 0 0 0 0 228 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 2.000000 -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan 1.000000 +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 8/6 = 1.333333 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 7 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 1 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 252 none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none 250 none none none none none +dram[2]: none none none none none none none none none none 250 none none none none none +dram[3]: none none none none none none none none none none 122 none none none none none +dram[4]: none none none none none none none none none none 252 none none none none 0 +dram[5]: none none none none none none none none none none none none none none 0 none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 244 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 252 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +Number of Memory Banks Accessed per Memory Operation per Warp (from 0): +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Average # of Memory Banks Accessed per Memory Operation per Warp=-nan + +position of mrq chosen +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +average position of mrq chosen = -nan +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 +n_activity=40 dram_eff=0.2 +bk0: 4a 1985i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 +n_activity=40 dram_eff=0.2 +bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 +n_activity=40 dram_eff=0.2 +bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents +MSHR: tag=0x3e20200, atomic=0 1 entries : 0x7f6d3018f8f0 : mf: uid= 22, sid01:w00, part=3, addr=0x3e20200, load , size=128, unknown status = IN_PARTITION_DRAM (1079), + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1996 n_act=1 n_pre=0 n_req=2 n_rd=3 n_write=4 bw_util=0.006986 +n_activity=29 dram_eff=0.4828 +bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 3a 1975i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=1 avg=0.00598802 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1994 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007984 +n_activity=80 dram_eff=0.2 +bk0: 0a 2002i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 4a 1984i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 +n_activity=40 dram_eff=0.2 +bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2005i bk14: 4a 1985i bk15: 0a 2003i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 7 +L2_total_cache_misses = 7 +L2_total_cache_miss_rate = 1.0000 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 3 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 1 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.001 + +icnt_total_pkts_mem_to_simt=23 +icnt_total_pkts_simt_to_mem=11 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = 7.42857 + minimum = 6 + maximum = 10 +Network latency average = 7.42857 + minimum = 6 + maximum = 10 +Slowest packet = 1 +Flit latency average = 6 + minimum = 6 + maximum = 6 +Slowest flit = 0 +Fragmentation average = 0 + minimum = 0 + maximum = 0 +Injected packet rate average = 0.00012975 + minimum = 0 (at node 0) + maximum = 0.00324374 (at node 1) +Accepted packet rate average = 0.00012975 + minimum = 0 (at node 0) + maximum = 0.00324374 (at node 1) +Injected flit rate average = 0.000315107 + minimum = 0 (at node 0) + maximum = 0.00509731 (at node 1) +Accepted flit rate average= 0.000315107 + minimum = 0 (at node 0) + maximum = 0.010658 (at node 1) +Injected packet length average = 2.42857 +Accepted packet length average = 2.42857 +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Network latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Flit latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Fragmentation average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Injected packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected packet size average = -nan (5 samples) +Accepted packet size average = -nan (5 samples) +Hops average = -nan (5 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- + + +gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 1 sec (1 sec) +gpgpu_simulation_rate = 675 (inst/sec) +gpgpu_simulation_rate = 1080 (cycle/sec) +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 1080 +gpu_tot_sim_insn = 675 +gpu_tot_ipc = 0.6250 +gpu_tot_issued_cta = 1 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=675 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 13 + L1I_total_cache_misses = 2 + L1I_total_cache_miss_rate = 0.1538 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +Result: 0XA000006F + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 4 + L1C_total_cache_misses = 4 + L1C_total_cache_miss_rate = 1.0000 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 800 +gpgpu_n_tot_w_icount = 25 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 3 +gpgpu_n_mem_write_global = 1 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 1 +gpgpu_n_load_insn = 34 +gpgpu_n_store_insn = 32 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 128 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:1900 W0_Scoreboard:292 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 +traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} +traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} +traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} +traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} diff --git a/bsmad_test/gpgpu_inst_stats.txt b/bsmad_test/gpgpu_inst_stats.txt new file mode 100644 index 0000000..96fa69d --- /dev/null +++ b/bsmad_test/gpgpu_inst_stats.txt @@ -0,0 +1,26 @@ +kernel line : count latency dram_traffic smem_bk_conflicts smem_warp gmem_access_generated gmem_warp exposed_latency warp_divergence +_1.ptx 92 : 32 160 128 0 0 1 1 0 0 +_1.ptx 90 : 32 448 0 0 0 0 0 0 0 +_1.ptx 67 : 32 186 0 0 0 0 0 0 1 +_1.ptx 66 : 32 224 0 0 0 0 0 0 0 +_1.ptx 65 : 32 416 0 0 0 0 0 0 0 +_1.ptx 88 : 32 192 0 0 0 0 0 0 0 +_1.ptx 64 : 32 192 0 0 0 0 0 0 0 +_1.ptx 87 : 32 192 0 0 0 0 0 0 0 +_1.ptx 63 : 32 192 0 0 0 0 0 0 0 +_1.ptx 86 : 32 8256 128 0 0 1 1 0 0 +_1.ptx 99 : 32 192 0 0 0 0 0 0 0 +_1.ptx 62 : 32 192 0 0 0 0 0 0 0 +_1.ptx 85 : 32 352 0 0 0 0 0 0 0 +_1.ptx 61 : 32 8192 0 0 0 0 0 0 0 +_1.ptx 84 : 32 352 0 0 0 0 0 0 0 +_1.ptx 60 : 32 8192 0 0 0 0 0 0 0 +_1.ptx 83 : 32 320 0 0 0 0 0 0 0 +_1.ptx 59 : 32 8224 0 0 0 0 0 0 0 +_1.ptx 58 : 32 8224 128 0 0 0 0 0 0 +_1.ptx 69 : 1 7 0 0 0 0 0 0 0 +_1.ptx 70 : 1 256 128 0 0 1 1 0 0 +_1.ptx 71 : 1 7 0 0 0 0 0 0 0 +_1.ptx 72 : 1 256 128 0 0 1 1 0 0 +_1.ptx 75 : 32 224 0 0 0 0 0 0 0 +_1.ptx 76 : 32 224 0 0 0 0 0 0 0 diff --git a/bsmad_test/gpgpusim.config b/bsmad_test/gpgpusim.config new file mode 100644 index 0000000..6b512ba --- /dev/null +++ b/bsmad_test/gpgpusim.config @@ -0,0 +1,149 @@ +# This config models the Pascal GP102 (GeForceGTX 1080Ti) + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 60 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 11 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145,4,4 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 1,2,1,1,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The default is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_shmem_size 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 +-gpgpu_cache:dl2_texture_only 0 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +# gpgpu_num_reg_banks should be increased to 32, but it gives an error! +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) +# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" + +# Pascal has four schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/bsmad_test/gpuwattch_gtx1080Ti.xml b/bsmad_test/gpuwattch_gtx1080Ti.xml new file mode 100755 index 0000000..02619ff --- /dev/null +++ b/bsmad_test/gpuwattch_gtx1080Ti.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsmad_test/out.txt b/bsmad_test/out.txt new file mode 100644 index 0000000..4e95cb1 --- /dev/null +++ b/bsmad_test/out.txt @@ -0,0 +1,1837 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers Default 1,1,19,25,145,1 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +1739ba94823ccfb8e12f742738e8e16e /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_leydyg +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_8pgp00" +Running: cat _ptx_8pgp00 | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_ZhKBsL +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_ZhKBsL --output-file /dev/null 2> _ptx_8pgp00info" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_8pgp00 _ptx2_ZhKBsL _ptx_8pgp00info" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 +bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 16:03:17 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/bsmad_test/output b/bsmad_test/output new file mode 100644 index 0000000..db0d524 --- /dev/null +++ b/bsmad_test/output @@ -0,0 +1,2338 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers Default 1,1,19,25,145,1 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +733602e7cd2fc7896e7fece60068330a /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_Fvj0UD +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_qiCCrA" +Running: cat _ptx_qiCCrA | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_zIGfYw +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_zIGfYw --output-file /dev/null 2> _ptx_qiCCrAinfo" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_qiCCrA _ptx2_zIGfYw _ptx_qiCCrAinfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 13:33:51 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/bsmad_test/output.txt b/bsmad_test/output.txt new file mode 100644 index 0000000..7414f61 --- /dev/null +++ b/bsmad_test/output.txt @@ -0,0 +1,2338 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers Default 1,1,19,25,145,1 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +1739ba94823ccfb8e12f742738e8e16e /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_r35nHZ +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_hSOoDH" +Running: cat _ptx_hSOoDH | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_FSgqzp +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_FSgqzp --output-file /dev/null 2> _ptx_hSOoDHinfo" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_hSOoDH _ptx2_FSgqzp _ptx_hSOoDHinfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 + +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) + 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 16:02:01 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/bsmad_test/result b/bsmad_test/result new file mode 100644 index 0000000..210fed9 --- /dev/null +++ b/bsmad_test/result @@ -0,0 +1,2338 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers Default 1,1,19,25,145,1 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +1739ba94823ccfb8e12f742738e8e16e /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_ppZXax +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_D0f3bm" +Running: cat _ptx_D0f3bm | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_ctl9cb +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_ctl9cb --output-file /dev/null 2> _ptx_D0f3bminfo" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_D0f3bm _ptx2_ctl9cb _ptx_D0f3bminfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 16:27:07 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index b5b79e7..54d8796 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -69,9 +69,9 @@ unsigned cdp_latency[5]; void ptx_opcocde_latency_options (option_parser_t opp) { option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, - "Opcode latencies for integers " - "Default 1,1,19,25,145,1", - "1,1,19,25,145,1"); + "Opcode latencies for integers " + "Default 1,1,19,25,145,1,4", + "1,1,19,25,145,1,4"); option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp, "Opcode latencies for single precision floating points " "Default 1,1,1,1,30", @@ -81,8 +81,8 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Default 8,8,8,8,335", "8,8,8,8,335"); option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, - "Opcode initiation intervals for integers " - "Default 1,1,4,4,32,1", + "Opcode initiation intervals for integers " + "Default 1,1,4,4,32,1,1", "1,1,4,4,32,1"); option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp, "Opcode initiation intervals for single precision floating points " @@ -589,10 +589,14 @@ void ptx_instruction::set_bar_type() void ptx_instruction::set_opcode_and_latency() { - unsigned int_latency[6]; + unsigned int_latency[5]; + unsigned int_precision; + unsigned int_lane_width; unsigned fp_latency[5]; unsigned dp_latency[5]; - unsigned int_init[6]; + unsigned int_init[5]; + unsigned int_init_precision; + unsigned int_init_lane_width; unsigned fp_init[5]; unsigned dp_init[5]; /* @@ -603,18 +607,18 @@ void ptx_instruction::set_opcode_and_latency() * [4] DIV * [5] BSMAD */ - sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u", + sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u,%u", &int_latency[0],&int_latency[1],&int_latency[2], - &int_latency[3],&int_latency[4],&int_latency[5]); + &int_latency[3],&int_latency[4],&int_precision,&int_lane_width); sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u", &fp_latency[0],&fp_latency[1],&fp_latency[2], &fp_latency[3],&fp_latency[4]); sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u", &dp_latency[0],&dp_latency[1],&dp_latency[2], &dp_latency[3],&dp_latency[4]); - sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u", + sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u, %u", &int_init[0],&int_init[1],&int_init[2], - &int_init[3],&int_init[4],&int_init[5]); + &int_init[3],&int_init[4],&int_init_precision,&int_init_lane_width); sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u", &fp_init[0],&fp_init[1],&fp_init[2], &fp_init[3],&fp_init[4]); @@ -789,8 +793,8 @@ void ptx_instruction::set_opcode_and_latency() op = SFU_OP; break; case BSMAD_OP: - latency = int_latency[5]; - initiation_interval = int_init[5]; + latency = int_precision/int_lane_width; + initiation_interval = int_init_precision/int_init_lane_width; break; case SHFL_OP: latency = 32; -- cgit v1.3 From dd3b1fa1bda98de0d1c97cde46413043bcdbc8c2 Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Tue, 20 Feb 2018 19:38:14 -0600 Subject: Added cudaDeviceGetAttribute --- libcuda/cuda_runtime_api.cc | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index cbe8a11..79cca04 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -816,6 +816,50 @@ __host__ cudaError_t CUDARTAPI cudaGetDeviceProperties(struct cudaDeviceProp *pr } } +__host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDeviceAttr attr, int device) +{ + const struct cudaDeviceProp *prop; + _cuda_device_id *dev = GPGPUSim_Init(); + if (device <= dev->num_devices() ) { + prop = dev->get_prop(); + switch (attr) { + case 5: + *value= prop->maxGridSize[0]; + break; + case 6: + *value= prop->maxGridSize[1]; + break; + case 7: + *value= prop->maxGridSize[2]; + break; + case 10: + *value= prop->warpSize; + break; + case 12: + *value= prop->regsPerBlock; + break; + case 14: + *value= prop->textureAlignment ; + break; + case 16: + *value= prop->multiProcessorCount ; + break; + case 39: + *value= dev->get_gpgpu()->threads_per_core(); + break; + case 75: + *value= 8 ; + break; + case 76: + *value= 3 ; + break; + } + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorInvalidDevice; + } +} + __host__ cudaError_t CUDARTAPI cudaChooseDevice(int *device, const struct cudaDeviceProp *prop) { _cuda_device_id *dev = GPGPUSim_Init(); -- cgit v1.3 From 325c8951b18b257acefd62f5c25873a33fdcc59c Mon Sep 17 00:00:00 2001 From: letr63jd56 Date: Mon, 19 Mar 2018 12:38:09 -0700 Subject: temporary fixes to parsing issues --- src/cuda-sim/ptx.l | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 5471d6f..ea1e9da 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -162,6 +162,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.file TC; BEGIN(INITIAL); return FILE_DIRECTIVE; \.func TC; BEGIN(IN_FUNC_DECL); return FUNC_DIRECTIVE; // blocking opcode parsing in case the function has the same name as an opcode (e.g. sin(), cos()) \.global TC; return GLOBAL_DIRECTIVE; +\.global.volatile TC; return GLOBAL_DIRECTIVE; //AMRUTH: TODO: fix this! \.local TC; return LOCAL_DIRECTIVE; \.loc TC; return LOC_DIRECTIVE; \.maxnctapersm TC; return MAXNCTAPERSM_DIRECTIVE; @@ -233,6 +234,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.u32 TC; return U32_TYPE; \.u64 TC; return U64_TYPE; \.f16 TC; return F16_TYPE; +\.f16x2 TC; return F16_TYPE; /* AMRUTH: TODO: figure out what this should really be */ \.f32 TC; return F32_TYPE; \.f64 TC; return F64_TYPE; \.ff64 TC; return FF64_TYPE; -- cgit v1.3 From c6fcfc7e9509b087f932057f18fc4fe71b955382 Mon Sep 17 00:00:00 2001 From: letr63jd56 Date: Tue, 20 Mar 2018 11:33:18 -0700 Subject: code to load the embedded ptx directly and prevent cuobjdump to dump everytime we execute the code --- libcuda/cuda_runtime_api.cc | 34 ++++++++++++++++++++++++---------- src/cuda-sim/cuda-sim.cc | 4 +++- src/cuda-sim/ptx.l | 4 ++-- 3 files changed, 29 insertions(+), 13 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 79cca04..e7952e2 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1393,13 +1393,17 @@ std::string get_app_binary(){ * It is also responsible for extracting the libraries linked to the binary if the option is * enabled * */ + void extract_code_using_cuobjdump(){ - CUctx_st *context = GPGPUSim_Context(); + CUctx_st *context = GPGPUSim_Context(); + //prevent the dumping by cuobjdump everytime we execute the code! + const char *override_cuobjdump = getenv("CUOBJDUMP_SIM_FILE"); + + char fname[1024]; + if (override_cuobjdump == NULL) { char command[1000]; + std::string app_binary = get_app_binary(); - std::string app_binary = get_app_binary(); - - char fname[1024]; snprintf(fname,1024,"_cuobjdump_complete_output_XXXXXX"); int fd=mkstemp(fname); close(fd); @@ -1410,10 +1414,11 @@ void extract_code_using_cuobjdump(){ // Running cuobjdump using dynamic link to current process // Needs the option '-all' to extract PTX from CDP-enabled binary extern bool g_cdp_enabled; + //dump only for specific arch - TODO: will it save memory? if(!g_cdp_enabled) - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass %s > %s", app_binary.c_str(), fname); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_60 %s > %s", app_binary.c_str(), fname); else - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_60 -all %s > %s", app_binary.c_str(), fname); bool parse_output = true; int result = system(command); if(result) { @@ -1493,6 +1498,10 @@ void extract_code_using_cuobjdump(){ //Restore the original section list cuobjdumpSectionList = tmpsl; } + } else { + printf("GPGPU-Sim PTX: overriding cuobjdump with '%s' (CUOBJDUMP_SIM_FILE is set)\n", override_cuobjdump); + snprintf(fname,1024,override_cuobjdump); + } } //! Read file into char* @@ -1724,8 +1733,10 @@ cuobjdumpPTXSection* findPTXSection(const std::string identifier){ void cuobjdumpInit(){ CUctx_st *context = GPGPUSim_Context(); extract_code_using_cuobjdump(); //extract all the output of cuobjdump to _cuobjdump_*.* - cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); - cuobjdumpSectionList = mergeSections(cuobjdumpSectionList); + if (getenv("CUOBJDUMP_SIM_FILE")==NULL){ + cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); + cuobjdumpSectionList = mergeSections(cuobjdumpSectionList); + } } std::map fatbinmap; @@ -1760,7 +1771,9 @@ void cuobjdumpParseBinary(unsigned int handle){ } if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); - cuobjdumpPTXSection* ptx = findPTXSection(fname); + cuobjdumpPTXSection* ptx = NULL; + if(getenv("CUOBJDUMP_SIM_FILE")==NULL) + ptx = findPTXSection(fname); symbol_table *symtab; char *ptxcode; const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); @@ -1784,7 +1797,8 @@ void cuobjdumpParseBinary(unsigned int handle){ delete[] ptxplus_str; } else { symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxcode, handle); - printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); + //if CUOBJDUMP_SIM_FILE is not set, ptx is NULL. So comment below. + //printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); context->add_binary(symtab, handle); gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability ); } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index d4ace76..f51f57d 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -212,7 +212,9 @@ void function_info::ptx_assemble() m_start_PC = PC; addr_t n=0; // offset in m_instr_mem - s_g_pc_to_insn.reserve(s_g_pc_to_insn.size() + MAX_INST_SIZE*m_instructions.size()); + //Why s_g_pc_to_insn.size() is needed to reserve additional memory for insts? reserve is cumulative. + //s_g_pc_to_insn.reserve(s_g_pc_to_insn.size() + MAX_INST_SIZE*m_instructions.size()); + s_g_pc_to_insn.reserve(MAX_INST_SIZE*m_instructions.size()); for ( i=m_instructions.begin(); i != m_instructions.end(); i++ ) { ptx_instruction *pI = *i; if ( pI->is_label() ) { diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index ea1e9da..1b5d7f6 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -162,7 +162,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.file TC; BEGIN(INITIAL); return FILE_DIRECTIVE; \.func TC; BEGIN(IN_FUNC_DECL); return FUNC_DIRECTIVE; // blocking opcode parsing in case the function has the same name as an opcode (e.g. sin(), cos()) \.global TC; return GLOBAL_DIRECTIVE; -\.global.volatile TC; return GLOBAL_DIRECTIVE; //AMRUTH: TODO: fix this! +\.global.volatile TC; return GLOBAL_DIRECTIVE; //TODO: fix this! \.local TC; return LOCAL_DIRECTIVE; \.loc TC; return LOC_DIRECTIVE; \.maxnctapersm TC; return MAXNCTAPERSM_DIRECTIVE; @@ -234,7 +234,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.u32 TC; return U32_TYPE; \.u64 TC; return U64_TYPE; \.f16 TC; return F16_TYPE; -\.f16x2 TC; return F16_TYPE; /* AMRUTH: TODO: figure out what this should really be */ +\.f16x2 TC; return F16_TYPE; /* TODO: figure out what this should really be */ \.f32 TC; return F32_TYPE; \.f64 TC; return F64_TYPE; \.ff64 TC; return FF64_TYPE; -- cgit v1.3 From e87f15a76c5b3225911850fcdb4074c16682ae50 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Wed, 21 Mar 2018 13:40:06 -0400 Subject: Change 124 by jain156@akshayj-lt1 on 2016/12/08 20:17:53 Added Memory divergence stats Data shows same divergence characteristics across PTX and PTX+ --- src/gpgpu-sim/shader.cc | 9 +++++++++ src/gpgpu-sim/shader.h | 4 ++++ 2 files changed, 13 insertions(+) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index bf482fb..72e0266 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -438,6 +438,9 @@ void shader_core_stats::print( FILE* fout ) const fprintf(fout,"gpgpu_n_mem_texture = %d\n", gpgpu_n_mem_texture); fprintf(fout,"gpgpu_n_mem_const = %d\n", gpgpu_n_mem_const); + fprintf(fout,"gpgpu_n_times_gmem_accesses_by_warps = %lld\n", gpgpu_n_times_gmem_accesses_by_warps); + fprintf(fout,"gpgpu_n_total_gmem_accesses_by_warps = %lld\n", gpgpu_n_total_gmem_accesses_by_warps); + fprintf(fout, "gpgpu_n_load_insn = %d\n", gpgpu_n_load_insn); fprintf(fout, "gpgpu_n_store_insn = %d\n", gpgpu_n_store_insn); fprintf(fout, "gpgpu_n_shmem_insn = %d\n", gpgpu_n_shmem_insn); @@ -740,9 +743,15 @@ void shader_core_ctx::fetch() void shader_core_ctx::func_exec_inst( warp_inst_t &inst ) { + unsigned starting_queue_size; execute_warp_inst_t(inst); if( inst.is_load() || inst.is_store() ) + starting_queue_size = inst.accessq_count(); inst.generate_mem_accesses(); + if ( inst.space.get_type() == global_space ) { + m_stats->gpgpu_n_times_gmem_accesses_by_warps++; + m_stats->gpgpu_n_total_gmem_accesses_by_warps += inst.accessq_count() - starting_queue_size; + } } void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* next_inst, const active_mask_t &active_mask, unsigned warp_id ) diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 5b41c06..2475677 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1470,6 +1470,10 @@ struct shader_core_stats_pod { int gpgpu_n_mem_read_global; int gpgpu_n_mem_write_global; int gpgpu_n_mem_read_inst; + + //warps memory divergence count + unsigned long long gpgpu_n_times_gmem_accesses_by_warps; + unsigned long long gpgpu_n_total_gmem_accesses_by_warps; int gpgpu_n_mem_l2_writeback; int gpgpu_n_mem_l1_write_allocate; -- cgit v1.3 From 2d8d4455aa710914e87c5611cbb71f9330cdbc73 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Thu, 22 Mar 2018 03:53:50 -0400 Subject: Change 180 by jain156@akshayj-lt1 on 2017/03/30 11:48:07 Added Memory Access breakdown statistics. Divided INST stats into INST type and INST Mem accesses. --- src/cuda-sim/cuda-sim.cc | 44 ++++++++++++++++++++------------------------ src/cuda-sim/cuda-sim.h | 2 ++ src/cuda-sim/opcodes.def | 2 ++ src/gpgpu-sim/gpu-sim.cc | 7 ++++--- 4 files changed, 28 insertions(+), 27 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 2f166aa..17a7798 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -52,8 +52,10 @@ int gpgpu_ptx_instruction_classification; void ** g_inst_classification_stat = NULL; +void ** g_inst_mem_classification_stat = NULL; void ** g_inst_op_classification_stat= NULL; int g_ptx_kernel_count = -1; // used for classification stat collection purposes +int g_ptx_kernel_count_prev = -1; // used for classification stat collection purposes int g_debug_execution = 0; int g_debug_thread_uid = 0; addr_t g_debug_pc = 0xBEEF1518; @@ -1240,12 +1242,16 @@ void init_inst_classification_stat() #define MAX_CLASS_KER 1024 char kernelname[MAX_CLASS_KER] =""; if (!g_inst_classification_stat) g_inst_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); - snprintf(kernelname, MAX_CLASS_KER, "Kernel %d Classification\n",g_ptx_kernel_count ); + snprintf(kernelname, MAX_CLASS_KER, "Kernel %d INST Classification",g_ptx_kernel_count ); assert( g_ptx_kernel_count < MAX_CLASS_KER ) ; // a static limit on number of kernels increase it if it fails! g_inst_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,20); + if (!g_inst_mem_classification_stat) g_inst_mem_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); + snprintf(kernelname, MAX_CLASS_KER, "Kernel %d MEM Classification",g_ptx_kernel_count ); + g_inst_mem_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,20); if (!g_inst_op_classification_stat) g_inst_op_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); - snprintf(kernelname, MAX_CLASS_KER, "Kernel %d OP Classification\n",g_ptx_kernel_count ); + snprintf(kernelname, MAX_CLASS_KER, "Kernel %d OP Classification",g_ptx_kernel_count ); g_inst_op_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,100); + g_ptx_kernel_count_prev++; } static unsigned get_tex_datasize( const ptx_instruction *pI, ptx_thread_info *thread ) @@ -1323,6 +1329,15 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) delete pJ; pI = pI_saved; + if ( gpgpu_ptx_instruction_classification ) { + init_inst_classification_stat(); + if (op_classification) + StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], op_classification); + if (pI->get_space().get_type()) + StatAddSample( g_inst_mem_classification_stat[g_ptx_kernel_count], ( int )pI->get_space().get_type()); + StatAddSample( g_inst_op_classification_stat[g_ptx_kernel_count], (int) pI->get_opcode() ); + } + // Run exit instruction if exit option included if(pI->is_exit()) exit_impl(pI,this); @@ -1408,27 +1423,6 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) if(!(this->m_functionalSimulationMode)) ptx_file_line_stats_add_exec_count(pI); - if ( gpgpu_ptx_instruction_classification ) { - init_inst_classification_stat(); - unsigned space_type=0; - switch ( pI->get_space().get_type() ) { - case global_space: space_type = 10; break; - case local_space: space_type = 11; break; - case tex_space: space_type = 12; break; - case surf_space: space_type = 13; break; - case param_space_kernel: - case param_space_local: - space_type = 14; break; - case shared_space: space_type = 15; break; - case const_space: space_type = 16; break; - default: - space_type = 0 ; - break; - } - StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], op_classification); - if (space_type) StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], ( int )space_type); - StatAddSample( g_inst_op_classification_stat[g_ptx_kernel_count], (int) pI->get_opcode() ); - } if ( (g_ptx_sim_num_insn % 100000) == 0 ) { dim3 ctaid = get_ctaid(); dim3 tid = get_tid(); @@ -1848,8 +1842,10 @@ void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL ) //******PRINTING******* printf( "GPGPU-Sim: Done functional simulation (%u instructions simulated).\n", g_ptx_sim_num_insn ); + fflush(stdout); if ( gpgpu_ptx_instruction_classification ) { - StatDisp( g_inst_classification_stat[g_ptx_kernel_count]); + StatDisp ( g_inst_classification_stat[g_ptx_kernel_count]); + StatDisp ( g_inst_mem_classification_stat[g_ptx_kernel_count]); StatDisp ( g_inst_op_classification_stat[g_ptx_kernel_count]); } diff --git a/src/cuda-sim/cuda-sim.h b/src/cuda-sim/cuda-sim.h index 958daba..ef9549f 100644 --- a/src/cuda-sim/cuda-sim.h +++ b/src/cuda-sim/cuda-sim.h @@ -44,8 +44,10 @@ extern int g_ptx_sim_mode; extern int g_debug_execution; extern int g_debug_thread_uid; extern void ** g_inst_classification_stat; +extern void ** g_inst_mem_classification_stat; extern void ** g_inst_op_classification_stat; extern int g_ptx_kernel_count; // used for classification stat collection purposes +extern int g_ptx_kernel_count_prev; // used for classification stat collection purposes void ptx_opcocde_latency_options (option_parser_t opp); extern class kernel_info_t *gpgpu_opencl_ptx_sim_init_grid(class function_info *entry, diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index e1b1422..ccf64d8 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -35,7 +35,9 @@ SFU 4 Mem(except Tex) 5 Tex 6 Nop 7 +Breakpoint 9 Other 10 +Scalar video 11 */ OP_DEF(ABS_OP,abs_impl,"abs",1,1) OP_DEF(ADD_OP,add_impl,"add",1,1) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 17f1714..121e079 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -445,7 +445,7 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) "1"); option_parser_register(opp, "-gpgpu_ptx_instruction_classification", OPT_INT32, &gpgpu_ptx_instruction_classification, - "if enabled will classify ptx instruction types per kernel (Max 255 kernels now)", + "if enabled will classify ptx instruction types per kernel (Max 1024 kernels now)", "0"); option_parser_register(opp, "-gpgpu_ptx_sim_mode", OPT_INT32, &g_ptx_sim_mode, "Select between Performance (default) or Functional simulation (1)", @@ -1076,8 +1076,9 @@ void gpgpu_sim::gpu_print_stat() insn_warp_occ_print(stdout); } if ( gpgpu_ptx_instruction_classification ) { - StatDisp( g_inst_classification_stat[g_ptx_kernel_count]); - StatDisp( g_inst_op_classification_stat[g_ptx_kernel_count]); + StatDisp( g_inst_classification_stat[g_ptx_kernel_count_prev]); + StatDisp( g_inst_mem_classification_stat[g_ptx_kernel_count_prev]); + StatDisp( g_inst_op_classification_stat[g_ptx_kernel_count_prev]); } #ifdef GPGPUSIM_POWER_MODEL -- cgit v1.3 From 777ab7fd6761a6250bc8e4f37994125a3f8d331b Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Thu, 22 Mar 2018 04:20:13 -0400 Subject: Change 252 by jain156@akshayj-lt1 on 2017/05/29 10:51:32 Checking in the data footprint stats as reported in the micro paper. The implementation uses gpgpu pointer, due to which I don't feel fine pushing to mainline. May be I can do the stats check and increment in l2cache.cc through a public function to avoid exposing gpgpu pointer to public --- src/gpgpu-sim/gpu-sim.cc | 2 +- src/gpgpu-sim/gpu-sim.h | 3 +++ src/gpgpu-sim/l2cache.cc | 20 ++++++++++++++++---- src/gpgpu-sim/l2cache.h | 8 ++++++-- src/gpgpusim_entrypoint.cc | 1 + 5 files changed, 27 insertions(+), 7 deletions(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 121e079..9a28b55 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -668,7 +668,7 @@ gpgpu_sim::gpgpu_sim( const gpgpu_sim_config &config ) m_memory_partition_unit = new memory_partition_unit*[m_memory_config->m_n_mem]; m_memory_sub_partition = new memory_sub_partition*[m_memory_config->m_n_mem_sub_partition]; for (unsigned i=0;im_n_mem;i++) { - m_memory_partition_unit[i] = new memory_partition_unit(i, m_memory_config, m_memory_stats); + m_memory_partition_unit[i] = new memory_partition_unit(i, m_memory_config, m_memory_stats, this); for (unsigned p = 0; p < m_memory_config->m_n_sub_partition_per_memory_channel; p++) { unsigned submpid = i * m_memory_config->m_n_sub_partition_per_memory_channel + p; m_memory_sub_partition[submpid] = m_memory_partition_unit[i]->get_sub_partition(p); diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 1778008..f9b5dad 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -36,6 +36,7 @@ #include #include #include +#include #include @@ -428,6 +429,8 @@ public: void perf_memcpy_to_gpu( size_t dst_start_addr, size_t count ); + std::unordered_set data_footprint_stats; + //The next three functions added to be used by the functional simulation function //! Get shader core configuration diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index b1465a8..a4aaf28 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -62,15 +62,16 @@ mem_fetch * partition_mf_allocator::alloc(new_addr_type addr, mem_access_type ty memory_partition_unit::memory_partition_unit( unsigned partition_id, const struct memory_config *config, - class memory_stats_t *stats ) -: m_id(partition_id), m_config(config), m_stats(stats), m_arbitration_metadata(config) + class memory_stats_t *stats, + class gpgpu_sim *gpu) +: m_id(partition_id), m_config(config), m_stats(stats), m_arbitration_metadata(config), m_gpu(gpu) { m_dram = new dram_t(m_id,m_config,m_stats,this); m_sub_partition = new memory_sub_partition*[m_config->m_n_sub_partition_per_memory_channel]; for (unsigned p = 0; p < m_config->m_n_sub_partition_per_memory_channel; p++) { unsigned sub_partition_id = m_id * m_config->m_n_sub_partition_per_memory_channel + p; - m_sub_partition[p] = new memory_sub_partition(sub_partition_id, m_config, stats); + m_sub_partition[p] = new memory_sub_partition(sub_partition_id, m_config, stats, m_gpu); } } @@ -310,11 +311,13 @@ void memory_partition_unit::print( FILE *fp ) const memory_sub_partition::memory_sub_partition( unsigned sub_partition_id, const struct memory_config *config, - class memory_stats_t *stats ) + class memory_stats_t *stats , + class gpgpu_sim *gpu) { m_id = sub_partition_id; m_config=config; m_stats=stats; + m_gpu=gpu; m_memcpy_cycle_offset = 0; assert(m_id < m_config->m_n_mem_sub_partition); @@ -410,6 +413,15 @@ void memory_sub_partition::cache_cycle( unsigned cycle ) bool read_sent = was_read_sent(events); MEM_SUBPART_DPRINTF("Probing L2 cache Address=%llx, status=%u\n", mf->get_addr(), status); + if ( (mf->get_access_type() == GLOBAL_ACC_R) || + (mf->get_access_type() == GLOBAL_ACC_W) || + (mf->get_access_type() == LOCAL_ACC_R) || + (mf->get_access_type() == LOCAL_ACC_W) || + (mf->get_access_type() == CONST_ACC_R) ) { + if (!m_gpu->data_footprint_stats.count(mf->get_addr())) + m_gpu->data_footprint_stats.insert(mf->get_addr()); + } + if ( status == HIT ) { if( !write_sent ) { // L2 cache replies diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index 2d13918..6aa7505 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -58,7 +58,7 @@ private: class memory_partition_unit { public: - memory_partition_unit( unsigned partition_id, const struct memory_config *config, class memory_stats_t *stats ); + memory_partition_unit( unsigned partition_id, const struct memory_config *config, class memory_stats_t *stats , class gpgpu_sim *gpu); ~memory_partition_unit(); bool busy() const; @@ -93,6 +93,8 @@ public: unsigned get_mpid() const { return m_id; } + gpgpu_sim *m_gpu; + private: unsigned m_id; @@ -145,7 +147,7 @@ private: class memory_sub_partition { public: - memory_sub_partition( unsigned sub_partition_id, const struct memory_config *config, class memory_stats_t *stats ); + memory_sub_partition( unsigned sub_partition_id, const struct memory_config *config, class memory_stats_t *stats, class gpgpu_sim *gpu); ~memory_sub_partition(); unsigned get_id() const { return m_id; } @@ -185,6 +187,8 @@ public: m_memcpy_cycle_offset += 1; } + gpgpu_sim *m_gpu; + private: // data unsigned m_id; //< the global sub partition ID diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index ad4587a..1ee980a 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -263,6 +263,7 @@ void print_simulation_time() s = difference - 60*(m + 60*(h + 24*d)); fflush(stderr); + printf("gpgpu_data_footprint = %u requests at L2\n", g_the_gpu->data_footprint_stats.size()); printf("\n\ngpgpu_simulation_time = %u days, %u hrs, %u min, %u sec (%u sec)\n", (unsigned)d, (unsigned)h, (unsigned)m, (unsigned)s, (unsigned)difference ); printf("gpgpu_simulation_rate = %u (inst/sec)\n", (unsigned)(g_the_gpu->gpu_tot_sim_insn / difference) ); -- cgit v1.3 From 160db7d46af433d12288505005ebd8c41be59922 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Thu, 22 Mar 2018 04:34:40 -0400 Subject: Change 253 by jain156@akshayj-lt1 on 2017/05/30 00:40:03 Replaced the mem div stats with mem div histogram --- src/gpgpu-sim/shader.cc | 8 ++++---- src/gpgpu-sim/shader.h | 9 ++++++--- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 72e0266..e7204c8 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -438,8 +438,9 @@ void shader_core_stats::print( FILE* fout ) const fprintf(fout,"gpgpu_n_mem_texture = %d\n", gpgpu_n_mem_texture); fprintf(fout,"gpgpu_n_mem_const = %d\n", gpgpu_n_mem_const); - fprintf(fout,"gpgpu_n_times_gmem_accesses_by_warps = %lld\n", gpgpu_n_times_gmem_accesses_by_warps); - fprintf(fout,"gpgpu_n_total_gmem_accesses_by_warps = %lld\n", gpgpu_n_total_gmem_accesses_by_warps); + fprintf(fout,"gpgpu_mem_divergence_hist "); + gpgpu_mem_divergence_hist->fprint(fout); + fprintf(fout,"\n"); fprintf(fout, "gpgpu_n_load_insn = %d\n", gpgpu_n_load_insn); fprintf(fout, "gpgpu_n_store_insn = %d\n", gpgpu_n_store_insn); @@ -749,8 +750,7 @@ void shader_core_ctx::func_exec_inst( warp_inst_t &inst ) starting_queue_size = inst.accessq_count(); inst.generate_mem_accesses(); if ( inst.space.get_type() == global_space ) { - m_stats->gpgpu_n_times_gmem_accesses_by_warps++; - m_stats->gpgpu_n_total_gmem_accesses_by_warps += inst.accessq_count() - starting_queue_size; + m_stats->gpgpu_mem_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); } } diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 2475677..45658ac 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -53,6 +53,8 @@ #include "stats.h" #include "gpu-cache.h" #include "traffic_breakdown.h" +#include "histogram.h" + @@ -1471,9 +1473,8 @@ struct shader_core_stats_pod { int gpgpu_n_mem_write_global; int gpgpu_n_mem_read_inst; - //warps memory divergence count - unsigned long long gpgpu_n_times_gmem_accesses_by_warps; - unsigned long long gpgpu_n_total_gmem_accesses_by_warps; + //warps combined memory divergence histogram + linear_histogram* gpgpu_mem_divergence_hist; int gpgpu_n_mem_l2_writeback; int gpgpu_n_mem_l1_write_allocate; @@ -1543,6 +1544,7 @@ public: m_incoming_traffic_stats = new traffic_breakdown("memtocore"); gpgpu_n_shmem_bank_access = (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); + gpgpu_mem_divergence_hist = new linear_histogram(1, "", config->warp_size+1); m_shader_dynamic_warp_issue_distro.resize( config->num_shader() ); m_shader_warp_slot_issue_distro.resize( config->num_shader() ); @@ -1557,6 +1559,7 @@ public: free(m_n_diverge); free(shader_cycle_distro); free(last_shader_cycle_distro); + free(gpgpu_mem_divergence_hist); } void new_grid() -- cgit v1.3 From 0241bdee08d2bdf95b7f6f9518403c22f8f0bc53 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Thu, 22 Mar 2018 04:37:36 -0400 Subject: Change 257 by jain156@akshayj-lt1 on 2017/06/03 16:32:52 Adding gpuwattch power stats to the output. Enabled inst and mem breakdown stats in config file. --- configs/GTX480/gpgpusim.config | 2 +- src/gpgpu-sim/gpu-sim.cc | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config index 03fcda1..bff5d16 100644 --- a/configs/GTX480/gpgpusim.config +++ b/configs/GTX480/gpgpusim.config @@ -1,5 +1,5 @@ # functional simulator specification --gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_instruction_classification 1 -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 20 diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 9a28b55..fb57a1e 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1024,6 +1024,7 @@ void gpgpu_sim::gpu_print_stat() shader_print_scheduler_stat( stdout, false ); m_shader_stats->print(stdout); + m_power_stats->print(stdout); #ifdef GPGPUSIM_POWER_MODEL if(m_config.g_power_simulation_enabled){ m_gpgpusim_wrapper->print_power_kernel_stats(gpu_sim_cycle, gpu_tot_sim_cycle, gpu_tot_sim_insn + gpu_sim_insn, kernel_info_str, true ); -- cgit v1.3 From 525f177a1d4f1fc309d22197bc8af26ee8d4c454 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Thu, 22 Mar 2018 04:40:44 -0400 Subject: Change 283 by jain156@akshayj-lt1 on 2017/07/03 19:52:55 Adding the global load and store divergence statistics. The previous histogram has been modified to look at all memory requests, but that is not meaningful - so it can as well be removed. --- src/gpgpu-sim/shader.cc | 15 +++++++++++++-- src/gpgpu-sim/shader.h | 8 +++++++- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index e7204c8..db6a532 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -441,6 +441,12 @@ void shader_core_stats::print( FILE* fout ) const fprintf(fout,"gpgpu_mem_divergence_hist "); gpgpu_mem_divergence_hist->fprint(fout); fprintf(fout,"\n"); + fprintf(fout,"gpgpu_gmem_ld_divergence_hist "); + gpgpu_gmem_ld_divergence_hist->fprint(fout); + fprintf(fout,"\n"); + fprintf(fout,"gpgpu_gmem_st_divergence_hist "); + gpgpu_gmem_st_divergence_hist->fprint(fout); + fprintf(fout,"\n"); fprintf(fout, "gpgpu_n_load_insn = %d\n", gpgpu_n_load_insn); fprintf(fout, "gpgpu_n_store_insn = %d\n", gpgpu_n_store_insn); @@ -746,12 +752,17 @@ void shader_core_ctx::func_exec_inst( warp_inst_t &inst ) { unsigned starting_queue_size; execute_warp_inst_t(inst); - if( inst.is_load() || inst.is_store() ) + if( inst.is_load() || inst.is_store() ) { starting_queue_size = inst.accessq_count(); inst.generate_mem_accesses(); if ( inst.space.get_type() == global_space ) { - m_stats->gpgpu_mem_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); + if (inst.is_load()) + m_stats->gpgpu_gmem_ld_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); + else if (inst.is_store()) + m_stats->gpgpu_gmem_st_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); } + m_stats->gpgpu_mem_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); + } } void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* next_inst, const active_mask_t &active_mask, unsigned warp_id ) diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 45658ac..da7eb32 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1475,7 +1475,9 @@ struct shader_core_stats_pod { //warps combined memory divergence histogram linear_histogram* gpgpu_mem_divergence_hist; - + linear_histogram* gpgpu_gmem_ld_divergence_hist; + linear_histogram* gpgpu_gmem_st_divergence_hist; + int gpgpu_n_mem_l2_writeback; int gpgpu_n_mem_l1_write_allocate; int gpgpu_n_mem_l2_write_allocate; @@ -1545,6 +1547,8 @@ public: gpgpu_n_shmem_bank_access = (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); gpgpu_mem_divergence_hist = new linear_histogram(1, "", config->warp_size+1); + gpgpu_gmem_ld_divergence_hist = new linear_histogram(1, "", config->warp_size+1); + gpgpu_gmem_st_divergence_hist = new linear_histogram(1, "", config->warp_size+1); m_shader_dynamic_warp_issue_distro.resize( config->num_shader() ); m_shader_warp_slot_issue_distro.resize( config->num_shader() ); @@ -1560,6 +1564,8 @@ public: free(shader_cycle_distro); free(last_shader_cycle_distro); free(gpgpu_mem_divergence_hist); + free(gpgpu_gmem_ld_divergence_hist); + free(gpgpu_gmem_st_divergence_hist); } void new_grid() -- cgit v1.3 From b43b94569734d9f27b2e4bbb22272aa4243fbd56 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Thu, 22 Mar 2018 04:45:59 -0400 Subject: Change 332 by jain156@akshayj-lt1 on 2018/02/01 05:20:33 Added shmem_divergence_hist and warp_inst_classification --- src/abstract_hardware_model.h | 7 +++++++ src/cuda-sim/cuda-sim.cc | 4 +++- src/gpgpu-sim/shader.cc | 13 +++++++++++++ src/gpgpu-sim/shader.h | 7 +++++++ 4 files changed, 30 insertions(+), 1 deletion(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index cec75f9..9ba31d9 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -798,6 +798,7 @@ public: arch_reg.dst[i] = -1; } isize=0; + op_classification = 0; } bool valid() const { return m_decoded; } virtual void print_insn( FILE *fp ) const @@ -816,6 +817,7 @@ public: address_type pc; // program counter address of instruction unsigned isize; // size of instruction in bytes op_type op; // opcode (uarch visible) + int op_classification; // classification of opcode for statistics purpopses barrier_type bar_type; reduction_type red_type; @@ -1023,6 +1025,11 @@ public: return cycles > 0; } + unsigned get_cycles() + { + return cycles; + } + void print( FILE *fout ) const; unsigned get_uid() const { return m_uid; } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 17a7798..169c491 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1331,8 +1331,10 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) if ( gpgpu_ptx_instruction_classification ) { init_inst_classification_stat(); - if (op_classification) + if (op_classification) { StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], op_classification); + inst.op_classification = op_classification; + } if (pI->get_space().get_type()) StatAddSample( g_inst_mem_classification_stat[g_ptx_kernel_count], ( int )pI->get_space().get_type()); StatAddSample( g_inst_op_classification_stat[g_ptx_kernel_count], (int) pI->get_opcode() ); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index db6a532..905139c 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -447,6 +447,12 @@ void shader_core_stats::print( FILE* fout ) const fprintf(fout,"gpgpu_gmem_st_divergence_hist "); gpgpu_gmem_st_divergence_hist->fprint(fout); fprintf(fout,"\n"); + fprintf(fout,"gpgpu_shmem_divergence_hist "); + gpgpu_shmem_divergence_hist->fprint(fout); + fprintf(fout,"\n"); + fprintf(fout,"warp_inst_classification "); + warp_inst_classification->fprint(fout); + fprintf(fout,"\n"); fprintf(fout, "gpgpu_n_load_insn = %d\n", gpgpu_n_load_insn); fprintf(fout, "gpgpu_n_store_insn = %d\n", gpgpu_n_store_insn); @@ -752,6 +758,9 @@ void shader_core_ctx::func_exec_inst( warp_inst_t &inst ) { unsigned starting_queue_size; execute_warp_inst_t(inst); + if (inst.op_classification) { + m_stats->warp_inst_classification->add2bin(inst.op_classification); + } if( inst.is_load() || inst.is_store() ) { starting_queue_size = inst.accessq_count(); inst.generate_mem_accesses(); @@ -761,6 +770,10 @@ void shader_core_ctx::func_exec_inst( warp_inst_t &inst ) else if (inst.is_store()) m_stats->gpgpu_gmem_st_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); } + else if ( inst.space.get_type() == shared_space ) { + m_stats->gpgpu_shmem_divergence_hist->add2bin(inst.get_cycles()); + } + m_stats->gpgpu_mem_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); } } diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index da7eb32..9fd1ecb 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1477,6 +1477,9 @@ struct shader_core_stats_pod { linear_histogram* gpgpu_mem_divergence_hist; linear_histogram* gpgpu_gmem_ld_divergence_hist; linear_histogram* gpgpu_gmem_st_divergence_hist; + linear_histogram* gpgpu_shmem_divergence_hist; + + linear_histogram* warp_inst_classification; int gpgpu_n_mem_l2_writeback; int gpgpu_n_mem_l1_write_allocate; @@ -1549,6 +1552,9 @@ public: gpgpu_mem_divergence_hist = new linear_histogram(1, "", config->warp_size+1); gpgpu_gmem_ld_divergence_hist = new linear_histogram(1, "", config->warp_size+1); gpgpu_gmem_st_divergence_hist = new linear_histogram(1, "", config->warp_size+1); + gpgpu_shmem_divergence_hist = new linear_histogram(1, "", config->warp_size+1); + + warp_inst_classification = new linear_histogram(1, "", 12); m_shader_dynamic_warp_issue_distro.resize( config->num_shader() ); m_shader_warp_slot_issue_distro.resize( config->num_shader() ); @@ -1566,6 +1572,7 @@ public: free(gpgpu_mem_divergence_hist); free(gpgpu_gmem_ld_divergence_hist); free(gpgpu_gmem_st_divergence_hist); + free(warp_inst_classification); } void new_grid() -- cgit v1.3 From 742c4dc4c2c85329754043d38c60b2a37fefdaa1 Mon Sep 17 00:00:00 2001 From: Amruth Date: Fri, 23 Mar 2018 19:13:00 -0700 Subject: dynamic pdom analysis at runtime --- libcuda/cuda_runtime_api.cc | 19 +++++++++++++++---- src/cuda-sim/cuda-sim.cc | 12 ++++++++++++ src/cuda-sim/ptx_ir.cc | 26 ++++++++++++++++++++++++++ src/cuda-sim/ptx_ir.h | 5 ++++- 4 files changed, 57 insertions(+), 5 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index e7952e2..948d81d 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1013,7 +1013,16 @@ __host__ cudaError_t CUDARTAPI cudaLaunch( const char *hostFun ) printf("\nGPGPU-Sim PTX: cudaLaunch for 0x%p (mode=%s) on stream %u\n", hostFun, g_ptx_sim_mode?"functional simulation":"performance simulation", stream?stream->get_uid():0 ); kernel_info_t *grid = gpgpu_cuda_ptx_sim_init_grid(hostFun,config.get_args(),config.grid_dim(),config.block_dim(),context); + //do dynamic PDOM analysis for performance simulation scenario std::string kname = grid->name(); + function_info *kernel_func_info = grid->entry(); + if (kernel_func_info->is_pdom_set()) { + printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", kname.c_str() ); + } else { + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", kname.c_str() ); + kernel_func_info->do_pdom(); + kernel_func_info->set_pdom(); + } dim3 gridDim = config.grid_dim(); dim3 blockDim = config.block_dim(); printf("GPGPU-Sim PTX: pushing kernel \'%s\' to stream %u, gridDim= (%u,%u,%u) blockDim = (%u,%u,%u) \n", @@ -1400,7 +1409,7 @@ void extract_code_using_cuobjdump(){ const char *override_cuobjdump = getenv("CUOBJDUMP_SIM_FILE"); char fname[1024]; - if (override_cuobjdump == NULL) { + if ((override_cuobjdump == NULL) || (strlen(override_cuobjdump)==0)) { char command[1000]; std::string app_binary = get_app_binary(); @@ -1733,7 +1742,8 @@ cuobjdumpPTXSection* findPTXSection(const std::string identifier){ void cuobjdumpInit(){ CUctx_st *context = GPGPUSim_Context(); extract_code_using_cuobjdump(); //extract all the output of cuobjdump to _cuobjdump_*.* - if (getenv("CUOBJDUMP_SIM_FILE")==NULL){ + const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); + if (pre_load ==NULL || strlen(pre_load)==0){ cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); cuobjdumpSectionList = mergeSections(cuobjdumpSectionList); } @@ -1772,12 +1782,13 @@ void cuobjdumpParseBinary(unsigned int handle){ if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); cuobjdumpPTXSection* ptx = NULL; - if(getenv("CUOBJDUMP_SIM_FILE")==NULL) + const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); + if(pre_load==NULL || strlen(pre_load)==0) ptx = findPTXSection(fname); symbol_table *symtab; char *ptxcode; const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); - if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL) { + if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL or strlen(getenv("PTX_SIM_USE_PTX_FILE"))==0) { ptxcode = readfile(ptx->getPTXfilename()); } else { printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index f51f57d..39a04dd 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -257,6 +257,8 @@ void function_info::ptx_assemble() fflush(stdout); printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", m_name.c_str() ); + //disable pdom analysis here and do it at runtime +#if 0 create_basic_blocks(); connect_basic_blocks(); bool modified = false; @@ -280,6 +282,7 @@ void function_info::ptx_assemble() print_postdominators(); print_ipostdominators(); } +#endif printf("GPGPU-Sim PTX: pre-decoding instructions for \'%s\'...\n", m_name.c_str() ); for ( unsigned ii=0; ii < n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions @@ -1801,6 +1804,15 @@ void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL ) //using a shader core object for book keeping, it is not needed but as most function built for performance simulation need it we use it here extern gpgpu_sim *g_the_gpu; + //before we execute, we should do PDOM analysis for functional simulation scenario. + function_info *kernel_func_info = kernel.entry(); + if (kernel_func_info->is_pdom_set()) { + printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", kernel.name().c_str() ); + } else { + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", kernel.name().c_str() ); + kernel_func_info->do_pdom(); + kernel_func_info->set_pdom(); + } //we excute the kernel one CTA (Block) at the time, as synchronization functions work block wise while(!kernel.no_more_ctas_to_run()){ diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 8ebdcf8..6a17eaf 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -575,6 +575,31 @@ bool function_info::connect_break_targets() //connecting break instructions with return modified; } +void function_info::do_pdom() { + create_basic_blocks(); + connect_basic_blocks(); + bool modified = false; + do { + find_dominators(); + find_idominators(); + modified = connect_break_targets(); + } while (modified == true); + + if ( g_debug_execution>=50 ) { + print_basic_blocks(); + print_basic_block_links(); + print_basic_block_dot(); + } + if ( g_debug_execution>=2 ) { + print_dominators(); + } + find_postdominators(); + find_ipostdominators(); + if ( g_debug_execution>=50 ) { + print_postdominators(); + print_ipostdominators(); + } +} void intersect( std::set &A, const std::set &B ) { // return intersection of A and B in A @@ -1305,6 +1330,7 @@ function_info::function_info(int entry_point ) m_kernel_info.smem = 0; m_local_mem_framesize = 0; m_args_aligned_size = -1; + pdom_done = false; //initialize it to false } unsigned function_info::print_insn( unsigned pc, FILE * fp ) const diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 9ad1571..26a2839 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1178,7 +1178,7 @@ public: //Muchnick's Adv. Compiler Design & Implemmntation Fig 7.15 void find_ipostdominators( ); void print_ipostdominators(); - + void do_pdom(); //function to call pdom analysis unsigned get_num_reconvergence_pairs(); @@ -1274,6 +1274,8 @@ public: m_local_mem_framesize = sz; } bool is_entry_point() const { return m_entry_point; } + bool is_pdom_set() const { return pdom_done; } //return pdom flag + void set_pdom() { pdom_done = true; } //set pdom flag private: unsigned m_uid; @@ -1281,6 +1283,7 @@ private: bool m_entry_point; bool m_extern; bool m_assembled; + bool pdom_done; //flag to check whether pdom is completed or not std::string m_name; ptx_instruction **m_instr_mem; unsigned m_start_PC; -- cgit v1.3 From 26b9853cc1f6a3b17de0e319b40f28a5703ad6bf Mon Sep 17 00:00:00 2001 From: Amruth Date: Sun, 25 Mar 2018 16:01:22 -0700 Subject: code for removing duplicates in embedded ptx --- libcuda/cuda_runtime_api.cc | 247 ++++++++++++++++++++++++++++---------------- src/cuda-sim/ptx_loader.cc | 155 +++++++++++++++++---------- src/cuda-sim/ptx_loader.h | 1 + 3 files changed, 255 insertions(+), 148 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 948d81d..f74c4eb 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -145,6 +145,8 @@ #include #endif +int no_of_ptx=0; + extern void synchronize(); extern void exit_simulation(); @@ -1394,6 +1396,26 @@ std::string get_app_binary(){ return self_exe_path; } +//above func gives abs path whereas this give just the name of application. +char* get_app_binary_name(std::string abs_path){ + char *self_exe_path; +#ifdef __APPLE__ + //TODO: get apple device and check the result. + printf("WARNING: not tested for Apple-mac devices \n"); + abort(); +#else + char* buf = strdup(abs_path.c_str()); + char *token = strtok(buf, "/"); + while(token !=NULL){ + self_exe_path = token; + token = strtok(NULL,"/"); + } +#endif + self_exe_path = strtok(self_exe_path, "."); + printf("self exe links to: %s\n", self_exe_path); + return self_exe_path; +} + //! Call cuobjdump to extract everything (-elf -sass -ptx) /*! * This Function extract the whole PTX (for all the files) using cuobjdump @@ -1402,114 +1424,152 @@ std::string get_app_binary(){ * It is also responsible for extracting the libraries linked to the binary if the option is * enabled * */ - void extract_code_using_cuobjdump(){ CUctx_st *context = GPGPUSim_Context(); + unsigned forced_max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); + //prevent the dumping by cuobjdump everytime we execute the code! const char *override_cuobjdump = getenv("CUOBJDUMP_SIM_FILE"); - + char command[1000], ptx_file[1000]; + std::string app_binary = get_app_binary(); + //Running cuobjdump using dynamic link to current process + snprintf(command,1000,"md5sum %s ", app_binary.c_str()); + printf("Running md5sum using \"%s\"\n", command); + system(command); + // Running cuobjdump using dynamic link to current process + // Needs the option '-all' to extract PTX from CDP-enabled binary + extern bool g_cdp_enabled; + + //dump ptx for all individial ptx files into sepearte files which is later used by ptxas. + char fname2[1024]; + snprintf(fname2,1024,"_cuobjdump_list_ptx_XXXXXX"); + int fd2=mkstemp(fname2); + close(fd2); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -lptx -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname2); + int result = system(command); + if( result != 0 ) { + printf("WARNING: Failed to execute cuobjdump to get list of ptx files \n"); + exit(0); + } else { + /* + as we got list of ptx files, we need to extract one by one into seperate files so that ptxas can understand it. + In this way, the duplicate definitions in a single embedded file can be prevented. + No of lines in the file is equal to no of ptx fileis available. + */ + FILE *fp = fopen(fname2,"r"); + if (fp==NULL) { + printf("WARNING: cuobjdump file error! Could not open file %s \n", fname2); + exit(0); + } else { + for (char c = getc(fp); c != EOF; c = getc(fp)) + if (c == '\n') + no_of_ptx = no_of_ptx + 1; + fclose(fp); + } + } + //based on the list above, dump ptx files individually. Format of dumped ptx file is prog_name.unique_no.sm_<>.ptx + for (int index=1; index<= no_of_ptx; index++){ + snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", get_app_binary_name(app_binary), index, forced_max_capability); + printf("Extracting specific PTX file named %s \n",ptx_file); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -arch=sm_%u -xptx %s %s", forced_max_capability, ptx_file, app_binary.c_str()); + if (system(command)!=0) { + printf("ERROR: command: %s failed \n",command); + exit(0); + } + } + //TODO: redundant to dump twice. how can it be prevented? + //dump only for specific arch char fname[1024]; if ((override_cuobjdump == NULL) || (strlen(override_cuobjdump)==0)) { - char command[1000]; - std::string app_binary = get_app_binary(); - snprintf(fname,1024,"_cuobjdump_complete_output_XXXXXX"); int fd=mkstemp(fname); close(fd); - // Running cuobjdump using dynamic link to current process - snprintf(command,1000,"md5sum %s ", app_binary.c_str()); - printf("Running md5sum using \"%s\"\n", command); - system(command); - // Running cuobjdump using dynamic link to current process - // Needs the option '-all' to extract PTX from CDP-enabled binary - extern bool g_cdp_enabled; - //dump only for specific arch - TODO: will it save memory? if(!g_cdp_enabled) - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_60 %s > %s", app_binary.c_str(), fname); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname); else - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_60 -all %s > %s", app_binary.c_str(), fname); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_%u -all %s > %s", forced_max_capability, app_binary.c_str(), fname); bool parse_output = true; - int result = system(command); + result = system(command); if(result) { - if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support() && (result == 65280)) { - // Some CUDA application may exclusively use kernels provided by CUDA - // libraries (e.g. CUBLAS). Skipping cuobjdump extraction from the - // executable for this case. - // 65280 is the return code from cuobjdump denoting the specific error (tested on CUDA 4.0/4.1/4.2) - printf("WARNING: Failed to execute: %s\n", command); - printf(" Executable binary does not contain any GPU kernel.\n"); - parse_output = false; - } else { - printf("ERROR: Failed to execute: %s\n", command); - exit(1); - } - } - - if (parse_output) { - printf("Parsing file %s\n", fname); - cuobjdump_in = fopen(fname, "r"); - - cuobjdump_parse(); - fclose(cuobjdump_in); - printf("Done parsing!!!\n"); - } else { - printf("Parsing skipped for %s\n", fname); - } + if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support() && (result == 65280)) { + // Some CUDA application may exclusively use kernels provided by CUDA + // libraries (e.g. CUBLAS). Skipping cuobjdump extraction from the + // executable for this case. + // 65280 is the return code from cuobjdump denoting the specific error (tested on CUDA 4.0/4.1/4.2) + printf("WARNING: Failed to execute: %s\n", command); + printf(" Executable binary does not contain any GPU kernel.\n"); + parse_output = false; + } else { + printf("ERROR: Failed to execute: %s\n", command); + exit(1); + } + } - if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ - //Experimental library support - //Currently only for cufft + if (parse_output) { + printf("Parsing file %s\n", fname); + cuobjdump_in = fopen(fname, "r"); - std::stringstream cmd; - cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; - int result = system(cmd.str().c_str()); - if(result){ - std::cout << "Failed to execute: " << cmd << std::endl; - exit(1); - } - std::ifstream libsf; - libsf.open("_tempfile_.txt"); - if(!libsf.is_open()) { - std::cout << "Failed to open: _tempfile_.txt" << std::endl; - exit(1); - } - - //Save the original section list - std::list tmpsl = cuobjdumpSectionList; - cuobjdumpSectionList.clear(); - - std::string line; - std::getline(libsf, line); - std::cout << "DOING: " << line << std::endl; - int cnt=1; - while(libsf.good()){ - std::stringstream libcodfn; - libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; - cmd.str(""); //resetting - cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; - cmd << line; - cmd << " > "; - cmd << libcodfn.str(); - std::cout << "Running cuobjdump on " << line << std::endl; - std::cout << "Using command: " << cmd.str() << std::endl; - result = system(cmd.str().c_str()); - if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} - std::cout << "Done" << std::endl; - - std::cout << "Trying to parse " << libcodfn << std::endl; - cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); - cuobjdump_parse(); - fclose(cuobjdump_in); - std::getline(libsf, line); - } - libSectionList = cuobjdumpSectionList; + cuobjdump_parse(); + fclose(cuobjdump_in); + printf("Done parsing!!!\n"); + } else { + printf("Parsing skipped for %s\n", fname); + } - //Restore the original section list - cuobjdumpSectionList = tmpsl; - } + if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ + //Experimental library support + //Currently only for cufft + + std::stringstream cmd; + cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; + int result = system(cmd.str().c_str()); + if(result){ + std::cout << "Failed to execute: " << cmd << std::endl; + exit(1); + } + std::ifstream libsf; + libsf.open("_tempfile_.txt"); + if(!libsf.is_open()) { + std::cout << "Failed to open: _tempfile_.txt" << std::endl; + exit(1); + } + + //Save the original section list + std::list tmpsl = cuobjdumpSectionList; + cuobjdumpSectionList.clear(); + + std::string line; + std::getline(libsf, line); + std::cout << "DOING: " << line << std::endl; + int cnt=1; + while(libsf.good()){ + std::stringstream libcodfn; + libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; + cmd.str(""); //resetting + cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; + cmd << line; + cmd << " > "; + cmd << libcodfn.str(); + std::cout << "Running cuobjdump on " << line << std::endl; + std::cout << "Using command: " << cmd.str() << std::endl; + result = system(cmd.str().c_str()); + if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} + std::cout << "Done" << std::endl; + + std::cout << "Trying to parse " << libcodfn << std::endl; + cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); + cuobjdump_parse(); + fclose(cuobjdump_in); + std::getline(libsf, line); + } + libSectionList = cuobjdumpSectionList; + + //Restore the original section list + cuobjdumpSectionList = tmpsl; + } } else { - printf("GPGPU-Sim PTX: overriding cuobjdump with '%s' (CUOBJDUMP_SIM_FILE is set)\n", override_cuobjdump); - snprintf(fname,1024,override_cuobjdump); + printf("GPGPU-Sim PTX: overriding cuobjdump with '%s' (CUOBJDUMP_SIM_FILE is set)\n", override_cuobjdump); + snprintf(fname,1024, "%s",override_cuobjdump); } } @@ -1772,6 +1832,8 @@ void cuobjdumpParseBinary(unsigned int handle){ return; } + //Why to search for capability value if we can directly find it in device info? + #if 0 unsigned max_capability = 0; for ( std::list::iterator iter = cuobjdumpSectionList.begin(); iter != cuobjdumpSectionList.end(); @@ -1780,6 +1842,8 @@ void cuobjdumpParseBinary(unsigned int handle){ if (capability > max_capability) max_capability = capability; } if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); + #endif + unsigned max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); @@ -1926,6 +1990,7 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) return (void**)fat_cubin_handle; } #endif + return 0; } void __cudaUnregisterFatBinary(void **fatCubinHandle) diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 6c1b595..d98ca07 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -32,6 +32,7 @@ #include #include #include +#include /// globals @@ -287,56 +288,87 @@ void fix_duplicate_errors(char fname2[1024]) { } } +//we need the application name here too. +char* get_app_binary_name(){ + char exe_path[1025]; + char *self_exe_path; +#ifdef __APPLE__ + //AMRUTH: get apple device and check the result. + printf("WARNING: not tested for Apple-mac devices \n"); + abort(); +#else + std::stringstream exec_link; + exec_link << "/proc/self/exe"; + ssize_t path_length = readlink(exec_link.str().c_str(), exe_path, 1024); + assert(path_length != -1); + exe_path[path_length] = '\0'; + + char *token = strtok(exe_path, "/"); + while(token !=NULL){ + self_exe_path = token; + token = strtok(NULL,"/"); + } +#endif + self_exe_path = strtok(self_exe_path, "."); + printf("self exe links to: %s\n", self_exe_path); + return self_exe_path; +} + void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version ) { - char fname[1024]; - snprintf(fname,1024,"_ptx_XXXXXX"); - int fd=mkstemp(fname); - close(fd); - - printf("GPGPU-Sim PTX: extracting embedded .ptx to temporary file \"%s\"\n", fname); - FILE *ptxfile = fopen(fname,"w"); - fprintf(ptxfile,"%s", p_for_info); - fclose(ptxfile); - - char fname2[1024]; - snprintf(fname2,1024,"_ptx2_XXXXXX"); - fd=mkstemp(fname2); - close(fd); - char commandline2[4096]; - snprintf(commandline2,4096,"cat %s | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\\(\\.extern \\.const\\[1\\] .b8 \\w\\+\\)\\[\\]/\\1\\[1\\]/' | sed 's/const\\[.\\]/const\\[0\\]/g' > %s", fname, fname2); - printf("Running: %s\n", commandline2); - int result = system(commandline2); - if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); - printf(" Ensure you have write access to simulation directory\n"); - printf(" and have \'cat\' and \'sed\' in your path.\n"); - exit(1); - } - - char tempfile_ptxinfo[1024]; - snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); - char commandline[1024]; - char extra_flags[1024]; - extra_flags[0]=0; - -#if CUDART_VERSION >= 3000 - if (sm_version == 0) sm_version = 20; - extern bool g_cdp_enabled; - if(!g_cdp_enabled) - snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); - else - snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version); -#endif + //do ptxas for individual files instead of one big embedded ptx. This prevents the duplicate defs and declarations. + char ptx_file[1000]; + char *name=get_app_binary_name(); + char commandline[4096], fname[1024], fname2[1024]; + for (int index=1; index <= no_of_ptx; index++){ + snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", name, index, sm_version); + snprintf(fname,1024,"_ptx_XXXXXX"); + int fd=mkstemp(fname); + close(fd); - snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", + printf("GPGPU-Sim PTX: extracting embedded .ptx to temporary file \"%s\"\n", fname); + snprintf(commandline,4096,"cat %s > %s",ptx_file, fname); + if (system(commandline) !=0) { + printf("ERROR: %s command failed\n", commandline); + exit(0); + } + + snprintf(fname2,1024,"_ptx2_XXXXXX"); + fd=mkstemp(fname2); + close(fd); + char commandline2[4096]; + snprintf(commandline2,4096,"cat %s | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\\(\\.extern \\.const\\[1\\] .b8 \\w\\+\\)\\[\\]/\\1\\[1\\]/' | sed 's/const\\[.\\]/const\\[0\\]/g' > %s", fname, fname2); + printf("Running: %s\n", commandline2); + int result = system(commandline2); + if( result != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); + printf(" Ensure you have write access to simulation directory\n"); + printf(" and have \'cat\' and \'sed\' in your path.\n"); + exit(1); + } + + char tempfile_ptxinfo[1024]; + snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); + char extra_flags[1024]; + extra_flags[0]=0; + + #if CUDART_VERSION >= 3000 + if (sm_version == 0) sm_version = 20; + extern bool g_cdp_enabled; + if(!g_cdp_enabled) + snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); + else + snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version); + #endif + + snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", extra_flags, fname2, tempfile_ptxinfo); - printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); - result = system(commandline); - if( result != 0 ) { - // 65280 = duplicate errors - if (result == 65280) { - ptxinfo_in = fopen(tempfile_ptxinfo,"r"); + printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); + result = system(commandline); + if( result != 0 ) { + // 65280 = duplicate errors + if (result == 65280) { + ptxinfo_in = fopen(tempfile_ptxinfo,"r"); g_ptxinfo_filename = tempfile_ptxinfo; ptxinfo_parse(); @@ -345,26 +377,35 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num extra_flags, fname2, tempfile_ptxinfo); printf("GPGPU-Sim PTX: regenerating ptxinfo using \"%s\"\n", commandline); result = system(commandline); - } - if (result != 0) { + } + if (result != 0) { printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); printf(" Ensure ptxas is in your path.\n"); exit(1); - } + } + } } - - ptxinfo_in = fopen(tempfile_ptxinfo,"r"); - g_ptxinfo_filename = tempfile_ptxinfo; + //Now that we got resource usage per kernel in a ptx file, we dump all into one file and pass it to rest of the code as usual. + char commandline3[4096]; + char final_tempfile_ptxinfo[1024]; + snprintf(final_tempfile_ptxinfo,1024,"f_tempfile_ptx"); + snprintf(commandline3,4096, "cat *info > %s", final_tempfile_ptxinfo); + if (system(commandline3)!=0) { + printf("ERROR: Either we dont have info files or cat is not working \n"); + printf("ERROR: %s command failed\n",commandline3); + exit(1); + } + + ptxinfo_in = fopen(final_tempfile_ptxinfo,"r"); + g_ptxinfo_filename = final_tempfile_ptxinfo; ptxinfo_parse(); if( ! g_save_embedded_ptx ) { - snprintf(commandline,1024,"rm -f %s %s %s", fname, fname2, tempfile_ptxinfo); + snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, final_tempfile_ptxinfo); printf("GPGPU-Sim PTX: removing ptxinfo using \"%s\"\n", commandline); - result = system(commandline); - if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (c) %d\n", result); + if( system(commandline) != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while removing temporary files\n"); exit(1); } } } - diff --git a/src/cuda-sim/ptx_loader.h b/src/cuda-sim/ptx_loader.h index d3d0c92..a8ecda3 100644 --- a/src/cuda-sim/ptx_loader.h +++ b/src/cuda-sim/ptx_loader.h @@ -30,6 +30,7 @@ #include extern bool g_override_embedded_ptx; +extern int no_of_ptx; //counter to track number of ptx files to be extracted in an application. class symbol_table *gpgpu_ptx_sim_load_ptx_from_string( const char *p, unsigned source_num ); void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version=20 ); -- cgit v1.3 From 8b40edc95b301269f1c0f43fdb94b3adc6b21845 Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Mon, 26 Mar 2018 19:08:58 -0400 Subject: .call instruction may have an empty argument list --- src/cuda-sim/ptx.y | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index e00aa4b..a66f508 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -513,7 +513,8 @@ compare_spec:EQ_OPTION { add_option(EQ_OPTION); } | NAN_OPTION { add_option(NAN_OPTION); } ; -operand_list: operand +operand_list: /* empty*/ + | operand | operand COMMA operand_list; operand: IDENTIFIER { add_scalar_operand( $1 ); } -- cgit v1.3 From 7a47f490efb7e7e7e4b960107f9bae79c5ab4a3d Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Mon, 26 Mar 2018 19:09:59 -0400 Subject: Remove duplicate token in PTX parser --- src/cuda-sim/ptx.y | 1 - 1 file changed, 1 deletion(-) diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index a66f508..4edae5d 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -47,7 +47,6 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token PTR_DIRECTIVE %token ENTRY_DIRECTIVE %token EXTERN_DIRECTIVE -%token WEAK_DIRECTIVE %token FILE_DIRECTIVE %token FUNC_DIRECTIVE %token GLOBAL_DIRECTIVE -- cgit v1.3 From c7d21017fcec06ef9d0d87e0a94c38deab5e1e1c Mon Sep 17 00:00:00 2001 From: Nathan J Conrad Date: Sat, 24 Mar 2018 11:39:14 -0400 Subject: Add vim swap files to gitignore --- .gitignore | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 53fadb5..0d84ba2 100644 --- a/.gitignore +++ b/.gitignore @@ -26,4 +26,5 @@ cuobjdump_to_ptxplus/sass_parser.cc cuobjdump_to_ptxplus/sass_parser.hh cuobjdump_to_ptxplus/sass_parser.output -build/* \ No newline at end of file +build/* +*.swp -- cgit v1.3 From d82197eba40f13a08784e8d873f6737b93f5bc41 Mon Sep 17 00:00:00 2001 From: Nathan J Conrad Date: Sat, 24 Mar 2018 15:01:12 -0400 Subject: Ignore generated docs in gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 0d84ba2..887b605 100644 --- a/.gitignore +++ b/.gitignore @@ -8,6 +8,7 @@ libcuda/cuobjdump_parser.h libcuda/cuobjdump_parser.output lib/* +doc/doxygen/html cuobjdump_to_ptxplus/elf_lexer.cc cuobjdump_to_ptxplus/elf_parser.cc -- cgit v1.3 From 6b7d14e294d8cb73e2281b7e18a4083e3271a85e Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Mon, 26 Mar 2018 19:20:24 -0400 Subject: Provide portable (non-x86) breakpoint method which should work on all linuxes. Tested on PowerPC. --- src/gpgpu-sim/gpu-sim.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 58a5d16..3829861 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -32,6 +32,7 @@ #include #include #include +#include #include "zlib.h" @@ -1440,7 +1441,7 @@ void gpgpu_sim::cycle() if( g_single_step && ((gpu_sim_cycle+gpu_tot_sim_cycle) >= g_single_step) ) { - asm("int $03"); + raise(SIGTRAP); // Debug breakpoint } gpu_sim_cycle++; if( g_interactive_debugger_enabled ) -- cgit v1.3 From 17ff26759ca0fb41095d2d0afaaed3059e6360ad Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Mon, 26 Mar 2018 19:35:41 -0400 Subject: Don't directly pass strings to printf (beacuse they wouldn't be escapped). Clang gives warnings about this. --- libcuda/cuobjdump.l | 6 ++---- src/cuda-sim/ptx_parser.cc | 10 +++++----- 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/libcuda/cuobjdump.l b/libcuda/cuobjdump.l index f63ee73..0953ea1 100644 --- a/libcuda/cuobjdump.l +++ b/libcuda/cuobjdump.l @@ -159,8 +159,6 @@ newlines {newline}+ %% void cuobjdump_error(const char* message) { - printf(" "); printf(message); printf(" near \""); printf(yytext); printf("\""); - printf(" on line "); - char line[5]; sprintf(line, "%i", yylineno); printf(line); - printf("\n"); + printf(" %s near \"%s\"",message, yytext); + printf(" on line %i\n",yylineno); } diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index baa3bcd..a180da9 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -433,7 +433,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_shared_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (shared memory space)\n", + printf("from 0x%llx to 0x%llx (shared memory space)\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); @@ -450,7 +450,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_global_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (global memory space) %u\n", + printf("from 0x%llx to 0x%llx (global memory space) %u\n", addr+addr_pad, addr+addr_pad + num_bits/8, g_const_alloc++); @@ -471,7 +471,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_global_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (global memory space)\n", + printf("from 0x%llx to 0x%llx (global memory space)\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); @@ -488,7 +488,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_local_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (local memory space)\n", + printf("from 0x%llx to 0x%llx (local memory space)\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); @@ -501,7 +501,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_local_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx\n", + printf("from 0x%llx to 0x%llx\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); -- cgit v1.3 From 89c198ba1f271bfc12a6c7d9c471e62a8daa5634 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Tue, 27 Mar 2018 04:21:38 -0400 Subject: Correcting the segfault in stats print. It was because print_stats() was called before g_ptx_kernel_count was initialized --- src/gpgpusim_entrypoint.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index 1ee980a..fe9e419 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -156,7 +156,7 @@ void *gpgpu_sim_thread_concurrent(void*) printf("GPGPU-Sim: ** STOP simulation thread (no work) **\n"); fflush(stdout); } - g_the_gpu->print_stats(); + //g_the_gpu->print_stats(); if(sim_cycles) { g_the_gpu->update_stats(); print_simulation_time(); -- cgit v1.3 From 5e8b10d9a0ea518dcb6c3c88b0a9cfd143363bcd Mon Sep 17 00:00:00 2001 From: Amruth Date: Tue, 27 Mar 2018 14:12:05 -0700 Subject: support for pinned memories - temporary fix --- libcuda/cuda_runtime_api.cc | 53 +++++++++++++++++++++++++++++++++++++++++-- src/abstract_hardware_model.h | 3 +++ src/cuda-sim/ptx_ir.cc | 6 +++-- 3 files changed, 58 insertions(+), 4 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index f74c4eb..97d702c 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -145,6 +145,8 @@ #include #endif +std::map pinned_memory; //support for pinned memories added +std::map pinned_memory_size; int no_of_ptx=0; extern void synchronize(); @@ -476,6 +478,8 @@ __host__ cudaError_t CUDARTAPI cudaMallocHost(void **ptr, size_t size) GPGPUSim_Context(); *ptr = malloc(size); if ( *ptr ) { + //track pinned memory size allocated in the host so that same amount of memory is also allocated in GPU. + pinned_memory_size[*ptr]=size; return g_last_cudaError = cudaSuccess; } else { return g_last_cudaError = cudaErrorMemoryAllocation; @@ -766,6 +770,16 @@ __host__ cudaError_t CUDARTAPI cudaMemset(void *mem, int c, size_t count) return g_last_cudaError = cudaSuccess; } +//memset operation is done but i think its not async? +__host__ cudaError_t CUDARTAPI cudaMemsetAsync(void *mem, int c, size_t count, cudaStream_t stream=0) +{ + printf("GPGPU-Sim PTX: WARNING: Asynchronous memset not supported (%s)\n", __my_func__); + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + gpu->gpu_memset((size_t)mem, c, count); + return g_last_cudaError = cudaSuccess; +} + __host__ cudaError_t CUDARTAPI cudaMemset2D(void *mem, size_t pitch, int c, size_t width, size_t height) { cuda_not_implemented(__my_func__,__LINE__); @@ -855,6 +869,12 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 76: *value= 3 ; break; + case 78: + *value= 0 ; //TODO: as of now, we dont support stream priorities. + break; + default: + printf("ERROR: implement the attribute numbered %d \n",attr); + abort(); } return g_last_cudaError = cudaSuccess; } else { @@ -1054,6 +1074,15 @@ __host__ cudaError_t CUDARTAPI cudaStreamCreate(cudaStream_t *stream) return g_last_cudaError = cudaSuccess; } +//TODO: introduce priorities +__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithPriority(cudaStream_t *stream, unsigned int flags, int priority) { + return cudaStreamCreate(stream); +} + +__host__ __device__ cudaError_t CUDARTAPI cudaDeviceGetStreamPriorityRange(int* leastPriority, int* greatestPriority) { + return cudaSuccess; +} + __host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *stream, unsigned int flags) { return cudaStreamCreate(stream); } @@ -2206,6 +2235,9 @@ cudaError_t cudaGLUnregisterBufferObject(GLuint bufferObj) cudaError_t CUDARTAPI cudaHostAlloc(void **pHost, size_t bytes, unsigned int flags) { *pHost = malloc(bytes); + //need to track the size allocated so that cudaHostGetDevicePointer() can function properly. + //TODO: vary this function behavior based on flags value (following nvidia documentation) + pinned_memory_size[*pHost]=bytes; if( *pHost ) return g_last_cudaError = cudaSuccess; else @@ -2214,8 +2246,25 @@ cudaError_t CUDARTAPI cudaHostAlloc(void **pHost, size_t bytes, unsigned int fl cudaError_t CUDARTAPI cudaHostGetDevicePointer(void **pDevice, void *pHost, unsigned int flags) { - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; + //only cpu memory allocation happens in cudaHostAlloc. Linking with device pointer to pinned memory happens here. + //TODO: once kernel is executed, the contents in global pointer of GPU must be copied back to CPU host pointer! + flags=0; + CUctx_st* context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + std::map::const_iterator i = pinned_memory_size.find(pHost); + assert(i != pinned_memory_size.end()); + size_t size = i->second; + *pDevice = gpu->gpu_malloc(size); + if(g_debug_execution >= 3) + printf("GPGPU-Sim PTX: cudaMallocing %zu bytes starting at 0x%llx..\n",size, (unsigned long long) *pDevice); + if ( *pDevice ) { + pinned_memory[pHost]=pDevice; + //Copy contents in cpu to gpu + gpu->memcpy_to_gpu((size_t)*pDevice,pHost,size); + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorMemoryAllocation; + } } cudaError_t CUDARTAPI cudaSetValidDevices(int *device_arr, int len) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index aaa4b00..67b36c7 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -182,6 +182,9 @@ void increment_x_then_y_then_z( dim3 &i, const dim3 &bound); class stream_manager; struct CUstream_st; extern stream_manager * g_stream_manager; +//support for pinned memories added +extern std::map pinned_memory; +extern std::map pinned_memory_size; class kernel_info_t { public: diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 6a17eaf..17e91df 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -280,8 +280,10 @@ type_info *symbol_table::get_array_type( type_info *base_type, unsigned array_di { type_info_key t = base_type->get_key(); t.set_array_dim(array_dim); - type_info *pt; - pt = m_types[t] = new type_info(this,t); + type_info *pt = new type_info(this,t); + //Where else is m_types being used? As of now, I dont find any use of it and causing seg fault. So disabling m_types. + //TODO: find where m_types can be used in future and solve the seg fault. + //pt = m_types[t] = new type_info(this,t); return pt; } -- cgit v1.3 From 0d07b73b58224724cff0576d91878817ec3c01c1 Mon Sep 17 00:00:00 2001 From: Amruth Date: Tue, 27 Mar 2018 15:52:52 -0700 Subject: considered CDP scenario --- libcuda/cuda_runtime_api.cc | 24 +++++++------- src/cuda-sim/ptx_loader.cc | 77 +++++++++++++++++++++++++++++++++++++-------- 2 files changed, 77 insertions(+), 24 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 97d702c..57c5ea1 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1083,8 +1083,8 @@ __host__ __device__ cudaError_t CUDARTAPI cudaDeviceGetStreamPriorityRange(int* return cudaSuccess; } -__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *stream, unsigned int flags) { - return cudaStreamCreate(stream); +__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *pStream, unsigned int flags) { + return cudaStreamCreate(pStream); } __host__ cudaError_t CUDARTAPI cudaStreamDestroy(cudaStream_t stream) @@ -1496,14 +1496,16 @@ void extract_code_using_cuobjdump(){ fclose(fp); } } - //based on the list above, dump ptx files individually. Format of dumped ptx file is prog_name.unique_no.sm_<>.ptx - for (int index=1; index<= no_of_ptx; index++){ - snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", get_app_binary_name(app_binary), index, forced_max_capability); - printf("Extracting specific PTX file named %s \n",ptx_file); - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -arch=sm_%u -xptx %s %s", forced_max_capability, ptx_file, app_binary.c_str()); - if (system(command)!=0) { - printf("ERROR: command: %s failed \n",command); - exit(0); + if(!g_cdp_enabled) { + //based on the list above, dump ptx files individually. Format of dumped ptx file is prog_name.unique_no.sm_<>.ptx + for (int index=1; index<= no_of_ptx; index++){ + snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", get_app_binary_name(app_binary), index, forced_max_capability); + printf("Extracting specific PTX file named %s \n",ptx_file); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -arch=sm_%u -xptx %s %s", forced_max_capability, ptx_file, app_binary.c_str()); + if (system(command)!=0) { + printf("ERROR: command: %s failed \n",command); + exit(0); + } } } //TODO: redundant to dump twice. how can it be prevented? @@ -1516,7 +1518,7 @@ void extract_code_using_cuobjdump(){ if(!g_cdp_enabled) snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname); else - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_%u -all %s > %s", forced_max_capability, app_binary.c_str(), fname); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); bool parse_output = true; result = system(command); if(result) { diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index d98ca07..9ff0859 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -319,7 +319,7 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num //do ptxas for individual files instead of one big embedded ptx. This prevents the duplicate defs and declarations. char ptx_file[1000]; char *name=get_app_binary_name(); - char commandline[4096], fname[1024], fname2[1024]; + char commandline[4096], fname[1024], fname2[1024], final_tempfile_ptxinfo[1024], tempfile_ptxinfo[1024]; for (int index=1; index <= no_of_ptx; index++){ snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", name, index, sm_version); snprintf(fname,1024,"_ptx_XXXXXX"); @@ -347,7 +347,6 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num exit(1); } - char tempfile_ptxinfo[1024]; snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); char extra_flags[1024]; extra_flags[0]=0; @@ -385,23 +384,75 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num } } } + + //TODO: duplicate code! move it into a function so that it can be reused! + if(no_of_ptx==0) { + //For CDP, we dump everything. So no_of_ptx will be 0. + snprintf(fname,1024,"_ptx_XXXXXX"); + int fd=mkstemp(fname); + close(fd); + + printf("GPGPU-Sim PTX: extracting embedded .ptx to temporary file \"%s\"\n", fname); + FILE *ptxfile = fopen(fname,"w"); + fprintf(ptxfile,"%s", p_for_info); + fclose(ptxfile); + + snprintf(fname2,1024,"_ptx2_XXXXXX"); + fd=mkstemp(fname2); + close(fd); + char commandline2[4096]; + snprintf(commandline2,4096,"cat %s | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\\(\\.extern \\.const\\[1\\] .b8 \\w\\+\\)\\[\\]/\\1\\[1\\]/' | sed 's/const\\[.\\]/const\\[0\\]/g' > %s", fname, fname2); + printf("Running: %s\n", commandline2); + int result = system(commandline2); + if( result != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); + printf(" Ensure you have write access to simulation directory\n"); + printf(" and have \'cat\' and \'sed\' in your path.\n"); + exit(1); + } + char tempfile_ptxinfo[1024]; + snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); + char extra_flags[1024]; + extra_flags[0]=0; +#if CUDART_VERSION >= 3000 + snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); +#endif + + snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", + extra_flags, fname2, tempfile_ptxinfo); + printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); + result = system(commandline); + if( result != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); + printf(" Ensure ptxas is in your path.\n"); + exit(1); + } + } + //Now that we got resource usage per kernel in a ptx file, we dump all into one file and pass it to rest of the code as usual. - char commandline3[4096]; - char final_tempfile_ptxinfo[1024]; - snprintf(final_tempfile_ptxinfo,1024,"f_tempfile_ptx"); - snprintf(commandline3,4096, "cat *info > %s", final_tempfile_ptxinfo); - if (system(commandline3)!=0) { - printf("ERROR: Either we dont have info files or cat is not working \n"); - printf("ERROR: %s command failed\n",commandline3); - exit(1); - } + if(no_of_ptx>0){ + char commandline3[4096]; + snprintf(final_tempfile_ptxinfo,1024,"f_tempfile_ptx"); + snprintf(commandline3,4096, "cat *info > %s", final_tempfile_ptxinfo); + if (system(commandline3)!=0) { + printf("ERROR: Either we dont have info files or cat is not working \n"); + printf("ERROR: %s command failed\n",commandline3); + exit(1); + } + } ptxinfo_in = fopen(final_tempfile_ptxinfo,"r"); - g_ptxinfo_filename = final_tempfile_ptxinfo; + if(no_of_ptx>0) + g_ptxinfo_filename = final_tempfile_ptxinfo; + else + g_ptxinfo_filename = tempfile_ptxinfo; ptxinfo_parse(); if( ! g_save_embedded_ptx ) { - snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, final_tempfile_ptxinfo); + if(no_of_ptx>0) + snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, final_tempfile_ptxinfo); + else + snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, tempfile_ptxinfo); printf("GPGPU-Sim PTX: removing ptxinfo using \"%s\"\n", commandline); if( system(commandline) != 0 ) { printf("GPGPU-Sim PTX: ERROR ** while removing temporary files\n"); -- cgit v1.3 From 3d2a9cc1b4a32237eb8a6fa84e999962001c715e Mon Sep 17 00:00:00 2001 From: Amruth Date: Tue, 27 Mar 2018 16:48:51 -0700 Subject: small corrections --- libcuda/cuda_runtime_api.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 57c5ea1..c622720 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1075,11 +1075,11 @@ __host__ cudaError_t CUDARTAPI cudaStreamCreate(cudaStream_t *stream) } //TODO: introduce priorities -__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithPriority(cudaStream_t *stream, unsigned int flags, int priority) { +__host__ cudaError_t CUDARTAPI cudaStreamCreateWithPriority(cudaStream_t *stream, unsigned int flags, int priority) { return cudaStreamCreate(stream); } -__host__ __device__ cudaError_t CUDARTAPI cudaDeviceGetStreamPriorityRange(int* leastPriority, int* greatestPriority) { +__host__ cudaError_t CUDARTAPI cudaDeviceGetStreamPriorityRange(int* leastPriority, int* greatestPriority) { return cudaSuccess; } -- cgit v1.3 From 9cdab90a180aea4d063d7b75bc085c4e8285bc49 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 12:55:07 -0400 Subject: Our internal Jenkinsfile --- Jenkinsfile | 120 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Jenkinsfile diff --git a/Jenkinsfile b/Jenkinsfile new file mode 100644 index 0000000..a8bd7f7 --- /dev/null +++ b/Jenkinsfile @@ -0,0 +1,120 @@ +pipeline { + agent { + label "purdue-cluster" + } + + options { + disableConcurrentBuilds() + } + + stages { + stage('simulator-build') { + steps { + parallel "4.2": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + make -j' + }, "9.1" : { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + make -j' + } + } + } + stage('simulations-build'){ + steps{ + sh 'rm -rf gpgpu-sim_simulations' + sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ + cd gpgpu-sim_simulations && \ + git checkout purdue-cluster && \ + git pull && \ + rm -r ./benchmarks/data_dirs && ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + cd gpgpu-sim_simulations && \ + source ./benchmarks/src/setup_environment && \ + make -j -C ./benchmarks/src rodinia_2.0-ft sdk-4.2 && \ + make -C ./benchmarks/src data' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + cd gpgpu-sim_simulations && \ + source ./benchmarks/src/setup_environment && \ + make -j -C ./benchmarks/src/ rodinia_2.0-ft sdk-4.2 && \ + make -C ./benchmarks/src data' + } + } + stage('regress'){ + steps { + + parallel "4.2-rodinia": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS -N regress-$$ && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + }, "9.1-rodinia": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N regress-$$ && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + }, "4.2-sdk-4.2": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480 -N regress-$$ && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + }, "9.1-sdk-4.2": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + } + } + } + stage('4.2-correlate'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS > stats-4.2.csv && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ + ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-4.2.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ + scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' + } + } + stage('9.1-correlate'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C TITANX-P102,P100-HBM > stats-9.1.csv && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ + ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ + scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' + } + } + } + post { + success { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - Success!", + to: 'tgrogers@purdue.edu' + } + failure { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - ${currentBuild.result}", + to: 'tgrogers@purdue.edu' + } + } +} + -- cgit v1.3 From 998ee2c94154f0fcd402fac1a05ca17bdd1482f6 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 13:03:10 -0400 Subject: Explicitly loggin in with Jenkins --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index a8bd7f7..f0a7935 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -24,7 +24,7 @@ pipeline { stage('simulations-build'){ steps{ sh 'rm -rf gpgpu-sim_simulations' - sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ + sh 'git clone jenkin99@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ cd gpgpu-sim_simulations && \ git checkout purdue-cluster && \ git pull && \ -- cgit v1.3 From b0ea6b829d1dc459c602e67818787ecbfd4be571 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 13:04:23 -0400 Subject: Mirroring the internal setup_env that enables Jenkins to work --- setup_environment | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/setup_environment b/setup_environment index 854a335..f6a16c5 100644 --- a/setup_environment +++ b/setup_environment @@ -1,12 +1,16 @@ # see README before running this -ps -p $$ | awk '/bash/ || / sh/ || /zsh/ {exit 1;}' && echo "ERROR ** source setup_environment must be run in a bash, zsh or sh shell; see README" && exit +ps -p $$ | awk '/bash/ || / sh/ || /zsh/ {exit 1;}' && echo "WARNING ** source setup_environment must be run in a bash, zsh or sh shell; see README" export GPGPUSIM_SETUP_ENVIRONMENT_WAS_RUN= export GPGPUSIM_ROOT="$( cd "$( dirname "$BASH_SOURCE" )" && pwd )" GPGPUSIM_VERSION_STRING=`cat $GPGPUSIM_ROOT/version | awk '/Version/ {print $8}'` -GPGPUSIM_BUILD_STRING=`cat $GPGPUSIM_ROOT/version | awk '/Change/ {print $6}'` +#Detect Git branch and commit # +GIT_COMMIT=`git log -n 1 | head -1 | sed -re 's/commit (.*)/\1/'` +GIT_FILES_CHANGED=`git diff --numstat --cached && git diff --numstat | wc | sed -re 's/^\s+([0-9]+).*/\1/'` +GPGPUSIM_BUILD_STRING="gpgpu-sim_git-commit-$GIT_COMMIT-modified_$GIT_FILES_CHANGED" + echo -n "GPGPU-Sim version $GPGPUSIM_VERSION_STRING (build $GPGPUSIM_BUILD_STRING) "; if [ ! -n "$CUDA_INSTALL_PATH" ]; then @@ -43,11 +47,9 @@ CC_VERSION=`gcc --version | head -1 | awk '{for(i=1;i<=NF;i++){ if(match($i,/^[0 CUDA_VERSION_STRING=`$CUDA_INSTALL_PATH/bin/nvcc --version | awk '/release/ {print $5;}' | sed 's/,//'`; CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("%02u%02u", 10*int($1), 10*$2);}'` -if [ $CUDA_VERSION_NUMBER -gt 8000 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then +if [ $CUDA_VERSION_NUMBER -gt 9100 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then echo "ERROR ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; return -elif [ $CUDA_VERSION_NUMBER -gt 4020 ]; then - echo "WARNING ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not fully tested with CUDA version $CUDA_VERSION_STRING (please see README)"; fi if [ $# = '1' ] ; -- cgit v1.3 From 996ec14f61526ac2d50e338f874f37a180f6dfa0 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 13:14:52 -0400 Subject: This does not exist in older CUDAs - only compile it for >5. Not sure if 5 is appropraite - but we test 4.2 and it fails --- libcuda/cuda_runtime_api.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index c622720..eda8d8e 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -832,6 +832,7 @@ __host__ cudaError_t CUDARTAPI cudaGetDeviceProperties(struct cudaDeviceProp *pr } } +#if (CUDART_VERSION > 5000) __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDeviceAttr attr, int device) { const struct cudaDeviceProp *prop; @@ -881,6 +882,7 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic return g_last_cudaError = cudaErrorInvalidDevice; } } +#endif __host__ cudaError_t CUDARTAPI cudaChooseDevice(int *device, const struct cudaDeviceProp *prop) { -- cgit v1.3 From 9acbc174a4c54d3ffa3d78feede017deb45922ec Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 13:21:08 -0400 Subject: This was a useless commmit - there were other problems with pulling the simulation repos --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index f0a7935..a8bd7f7 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -24,7 +24,7 @@ pipeline { stage('simulations-build'){ steps{ sh 'rm -rf gpgpu-sim_simulations' - sh 'git clone jenkin99@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ + sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ cd gpgpu-sim_simulations && \ git checkout purdue-cluster && \ git pull && \ -- cgit v1.3 From a9fe78437c825116500e866799cd6fab04a1f9a5 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 13:31:01 -0400 Subject: Do not run our private configs - just the public configs --- Jenkinsfile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index a8bd7f7..806231e 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -56,7 +56,7 @@ pipeline { }, "9.1-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX1080Ti -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N regress-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' @@ -70,7 +70,7 @@ pipeline { }, "9.1-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX1080Ti -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' @@ -92,7 +92,7 @@ pipeline { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C TITANX-P102,P100-HBM > stats-9.1.csv && \ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C GTX1080Ti > stats-9.1.csv && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ -- cgit v1.3 From bcb7b8f86f7b487ff0b106e3a2f37f95d989fd07 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 16:55:28 -0400 Subject: 20 makes no sense for this part --- configs/GeForceGTX1080Ti/gpgpusim.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/GeForceGTX1080Ti/gpgpusim.config b/configs/GeForceGTX1080Ti/gpgpusim.config index 47c2b6a..a5ada34 100644 --- a/configs/GeForceGTX1080Ti/gpgpusim.config +++ b/configs/GeForceGTX1080Ti/gpgpusim.config @@ -3,7 +3,7 @@ # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 20 +-gpgpu_ptx_force_max_capability 61 # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -- cgit v1.3 From 635366fe3e9b596318647b9c5bcdd546c522d52a Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Wed, 28 Mar 2018 14:37:43 -0700 Subject: fix compile errors on Ubuntu LTS 16.04 --- libcuda/cuda_runtime_api.cc | 18 +++++++++++------- src/abstract_hardware_model.h | 2 +- src/cuda-sim/cuda-math.h | 2 +- src/cuda-sim/instructions.cc | 8 ++++---- 4 files changed, 17 insertions(+), 13 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index cbe8a11..b7f25bf 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1406,7 +1406,7 @@ void extract_code_using_cuobjdump(){ cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; int result = system(cmd.str().c_str()); if(result){ - std::cout << "Failed to execute: " << cmd << std::endl; + std::cout << "Failed to execute: " << cmd.str() << std::endl; exit(1); } std::ifstream libsf; @@ -1438,7 +1438,7 @@ void extract_code_using_cuobjdump(){ if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} std::cout << "Done" << std::endl; - std::cout << "Trying to parse " << libcodfn << std::endl; + std::cout << "Trying to parse " << libcodfn.str() << std::endl; cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); cuobjdump_parse(); fclose(cuobjdump_in); @@ -1540,7 +1540,7 @@ std::list pruneSectionList(std::list cuobj //! Merge all PTX sections that have a specific identifier into one file std::list mergeMatchingSections(std::list cuobjdumpSectionList, std::string identifier){ - char *ptxcode = ""; + const char *ptxcode = ""; std::list::iterator old_iter; cuobjdumpPTXSection* old_ptxsection = NULL; cuobjdumpPTXSection* ptxsection; @@ -1689,7 +1689,7 @@ std::mapfatbin_registered; std::map name_symtab; //! Keep track of the association between filename and cubin handle -void cuobjdumpRegisterFatBinary(unsigned int handle, char* filename){ +void cuobjdumpRegisterFatBinary(unsigned int handle, const char* filename){ fatbinmap[handle] = filename; } @@ -1764,6 +1764,7 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) if (sizeof(void*) == 4) printf("GPGPU-Sim PTX: FatBin file name extraction has not been tested on 32-bit system.\n"); + #if (CUDART_VERSION <= 6000) // FatBin handle from the .fatbin.c file (one of the intermediate files generated by NVCC) typedef struct {int m; int v; const unsigned long long* d; char* f;} __fatDeviceText __attribute__ ((aligned (8))); __fatDeviceText * fatDeviceText = (__fatDeviceText *) fatCubin; @@ -1772,12 +1773,11 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) // - Obtains the pointer to the actual fatbin structure from the FatBin handle (fatCubin). // - An integer inside the fatbin structure contains the relative offset to the source code file name. // - This offset differs among different CUDA and GCC versions. - #if (CUDART_VERSION <= 6000) char * pfatbin = (char*) fatDeviceText->d; int offset = *((int*)(pfatbin+48)); char * filename = (pfatbin+16+offset); #else - char * filename = "default"; + const char * filename = "default"; #endif // The extracted file name is associated with a fat_cubin_handle passed // into cudaLaunch(). Inside cudaLaunch(), the associated file name is @@ -1798,7 +1798,7 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) return (void**)fat_cubin_handle; } - #if (CUDART_VERSION < 8000) +#if (CUDART_VERSION < 8000) else { static unsigned source_num=1; unsigned long long fat_cubin_handle = next_fat_bin_handle++; @@ -1857,6 +1857,10 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) return (void**)fat_cubin_handle; } #endif + else { + printf("ERROR ** __cudaRegisterFatBinary() needs to be updated\n"); + abort(); + } } void __cudaUnregisterFatBinary(void **fatCubinHandle) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index aaa4b00..7125b6b 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -383,7 +383,7 @@ protected: std::deque m_stack; }; -#define GLOBAL_HEAP_START 0x703E20000 +#define GLOBAL_HEAP_START 0xC0000000 // start allocating from this address (lower values used for allocating globals in .ptx file) #define SHARED_MEM_SIZE_MAX (64*1024) #define LOCAL_MEM_SIZE_MAX (8*1024) diff --git a/src/cuda-sim/cuda-math.h b/src/cuda-sim/cuda-math.h index 4721e8a..a3db0df 100644 --- a/src/cuda-sim/cuda-math.h +++ b/src/cuda-sim/cuda-math.h @@ -321,7 +321,7 @@ float __internal_accurate_fdividef(float a, float b) float __saturatef(float a) { float b; - if (isnan(a)) b = 0.0f; + if (std::isnan(a)) b = 0.0f; else if (a >= 1.0f) b = 1.0f; else if (a <= 0.0f) b = 0.0f; else b = a; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 011c285..71286c9 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1961,7 +1961,7 @@ ptx_reg_t d2d( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, y.f64 = x.f64; break; } - if (isnan(y.f64)) { + if (std::isnan(y.f64)) { y.u64 = 0xfff8000000000000ull; } else if (saturation_mode) { y.f64 = cuda_math::__saturatef(y.f64); @@ -2086,7 +2086,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) } } if ((type == F64_TYPE)||(type == FF64_TYPE)) { - if (isnan(data.f64)) { + if (std::isnan(data.f64)) { data.u64 = 0xfff8000000000000ull; } } @@ -2648,12 +2648,12 @@ void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry bool isNaN(float x) { - return isnan(x); + return std::isnan(x); } bool isNaN(double x) { - return isnan(x); + return std::isnan(x); } void max_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -- cgit v1.3 From c9cc4281bf84ad6cff77d20389b59d14a534ad6b Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Wed, 28 Mar 2018 16:16:38 -0700 Subject: (attempt to) fix compile error in last checkin --- libcuda/cuda_runtime_api.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index b7f25bf..9bdb993 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1856,11 +1856,12 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) } return (void**)fat_cubin_handle; } - #endif +#else else { printf("ERROR ** __cudaRegisterFatBinary() needs to be updated\n"); abort(); } +#endif } void __cudaUnregisterFatBinary(void **fatCubinHandle) -- cgit v1.3 From 6b6002d8f8f2e23de4a7c5e9dbc45467e846993c Mon Sep 17 00:00:00 2001 From: tgrogers-purdue Date: Thu, 29 Mar 2018 00:44:43 +0000 Subject: Initial Bitbucket Pipelines configuration --- bitbucket-pipelines.yml | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 bitbucket-pipelines.yml diff --git a/bitbucket-pipelines.yml b/bitbucket-pipelines.yml new file mode 100644 index 0000000..b15cc7c --- /dev/null +++ b/bitbucket-pipelines.yml @@ -0,0 +1,13 @@ +# This is a sample build configuration for C++ – Make. +# Check our guides at https://confluence.atlassian.com/x/5Q4SMw for more examples. +# Only use spaces to indent your .yml configuration. +# ----- +# You can specify a custom docker image from Docker Hub as your build environment. +image: gcc:6.1 + +pipelines: + default: + - step: + script: # Modify the commands below to build your repository. + - source setup_environment + - make -j \ No newline at end of file -- cgit v1.3 From 206b46ab50b58a629412f16ff261749e71dcca55 Mon Sep 17 00:00:00 2001 From: tgrogers-purdue Date: Thu, 29 Mar 2018 00:50:47 +0000 Subject: bitbucket-pipelines.yml edited online with Bitbucket --- bitbucket-pipelines.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bitbucket-pipelines.yml b/bitbucket-pipelines.yml index b15cc7c..f03c52a 100644 --- a/bitbucket-pipelines.yml +++ b/bitbucket-pipelines.yml @@ -1,9 +1,9 @@ -# This is a sample build configuration for C++ – Make. +# This is a sample build configuration for C++ Make. # Check our guides at https://confluence.atlassian.com/x/5Q4SMw for more examples. # Only use spaces to indent your .yml configuration. # ----- # You can specify a custom docker image from Docker Hub as your build environment. -image: gcc:6.1 +image: tgrogers/gpgpu-sim_regress:latest pipelines: default: -- cgit v1.3 From 2a451799316abe72571343c8c94f1f2934f57108 Mon Sep 17 00:00:00 2001 From: tgrogers-purdue Date: Thu, 29 Mar 2018 00:57:10 +0000 Subject: Can I just do the exact same thing as Travis? --- bitbucket-pipelines.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/bitbucket-pipelines.yml b/bitbucket-pipelines.yml index f03c52a..2c53081 100644 --- a/bitbucket-pipelines.yml +++ b/bitbucket-pipelines.yml @@ -9,5 +9,4 @@ pipelines: default: - step: script: # Modify the commands below to build your repository. - - source setup_environment - - make -j \ No newline at end of file + - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" \ No newline at end of file -- cgit v1.3 From 14a8d4ecf7d26e4cf516b788b7a9ff83976204df Mon Sep 17 00:00:00 2001 From: tgrogers-purdue Date: Thu, 29 Mar 2018 01:02:54 +0000 Subject: bitbucket-pipelines.yml edited online with Bitbucket --- bitbucket-pipelines.yml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/bitbucket-pipelines.yml b/bitbucket-pipelines.yml index 2c53081..4b2d7a0 100644 --- a/bitbucket-pipelines.yml +++ b/bitbucket-pipelines.yml @@ -9,4 +9,6 @@ pipelines: default: - step: script: # Modify the commands below to build your repository. - - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" \ No newline at end of file + - ./start_torque.sh + - chown -R runner /home/runner/gpgpu-sim_distribution + - su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" \ No newline at end of file -- cgit v1.3 From acad8ce81a1ea8b6ce516aa913238963136ad5f9 Mon Sep 17 00:00:00 2001 From: tgrogers-purdue Date: Thu, 29 Mar 2018 01:13:30 +0000 Subject: bitbucket-pipelines.yml edited online with Bitbucket --- bitbucket-pipelines.yml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/bitbucket-pipelines.yml b/bitbucket-pipelines.yml index 4b2d7a0..e9c92db 100644 --- a/bitbucket-pipelines.yml +++ b/bitbucket-pipelines.yml @@ -9,6 +9,7 @@ pipelines: default: - step: script: # Modify the commands below to build your repository. - - ./start_torque.sh - - chown -R runner /home/runner/gpgpu-sim_distribution - - su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" \ No newline at end of file + - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "export CONFIG=configs.gtx1080ti.yml; ./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" + services: + - docker + \ No newline at end of file -- cgit v1.3 From e76a32ee85ef8a132a11cbce69a854084215e728 Mon Sep 17 00:00:00 2001 From: tgrogers-purdue Date: Thu, 29 Mar 2018 01:19:27 +0000 Subject: bitbucket-pipelines.yml edited online with Bitbucket --- bitbucket-pipelines.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bitbucket-pipelines.yml b/bitbucket-pipelines.yml index e9c92db..6e331d4 100644 --- a/bitbucket-pipelines.yml +++ b/bitbucket-pipelines.yml @@ -9,7 +9,7 @@ pipelines: default: - step: script: # Modify the commands below to build your repository. - - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "export CONFIG=configs.gtx1080ti.yml; ./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" + - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.gtx1080ti.yml -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" services: - docker \ No newline at end of file -- cgit v1.3 From 638e18c04bc634fc510236a53d5aa8c22ef3e1ae Mon Sep 17 00:00:00 2001 From: Amruth Date: Thu, 29 Mar 2018 00:25:23 -0700 Subject: cuobjdump -lptx flag is not supported by cuda 5 and lower --- libcuda/cuda_runtime_api.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index eda8d8e..abe5337 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1472,6 +1472,7 @@ void extract_code_using_cuobjdump(){ extern bool g_cdp_enabled; //dump ptx for all individial ptx files into sepearte files which is later used by ptxas. +#if (CUDART_VERSION >= 6000) char fname2[1024]; snprintf(fname2,1024,"_cuobjdump_list_ptx_XXXXXX"); int fd2=mkstemp(fname2); @@ -1510,6 +1511,7 @@ void extract_code_using_cuobjdump(){ } } } +#endif //TODO: redundant to dump twice. how can it be prevented? //dump only for specific arch char fname[1024]; -- cgit v1.3 From 66107577251189900ba06cce0e8bce036d13079d Mon Sep 17 00:00:00 2001 From: Amruth Date: Thu, 29 Mar 2018 00:32:09 -0700 Subject: compilation fix --- libcuda/cuda_runtime_api.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index abe5337..8426b8e 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1472,13 +1472,14 @@ void extract_code_using_cuobjdump(){ extern bool g_cdp_enabled; //dump ptx for all individial ptx files into sepearte files which is later used by ptxas. + int result=0; #if (CUDART_VERSION >= 6000) char fname2[1024]; snprintf(fname2,1024,"_cuobjdump_list_ptx_XXXXXX"); int fd2=mkstemp(fname2); close(fd2); snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -lptx -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname2); - int result = system(command); + result = system(command); if( result != 0 ) { printf("WARNING: Failed to execute cuobjdump to get list of ptx files \n"); exit(0); -- cgit v1.3 From 24dc02cd1c46ff304fe7d8717c60c24c4b257785 Mon Sep 17 00:00:00 2001 From: Amruth Date: Thu, 29 Mar 2018 01:43:59 -0700 Subject: arch is also not supported for cuda 5 or lower --- libcuda/cuda_runtime_api.cc | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 8426b8e..5452ed0 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1520,10 +1520,15 @@ void extract_code_using_cuobjdump(){ snprintf(fname,1024,"_cuobjdump_complete_output_XXXXXX"); int fd=mkstemp(fname); close(fd); - if(!g_cdp_enabled) + if(!g_cdp_enabled) { +#if (CUDART_VERSION >= 6000) snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname); - else +#else + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass %s > %s", app_binary.c_str(), fname); +#endif + } else { snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); + } bool parse_output = true; result = system(command); if(result) { -- cgit v1.3 From 177d02254ae38b6331b17dd6cd139b570a03c589 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sat, 31 Mar 2018 06:01:23 +0000 Subject: restore code that selects ptx code that exists --- libcuda/cuda_runtime_api.cc | 4 ---- 1 file changed, 4 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index e4ae251..6cf21dd 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1873,8 +1873,6 @@ void cuobjdumpParseBinary(unsigned int handle){ return; } - //Why to search for capability value if we can directly find it in device info? - #if 0 unsigned max_capability = 0; for ( std::list::iterator iter = cuobjdumpSectionList.begin(); iter != cuobjdumpSectionList.end(); @@ -1883,8 +1881,6 @@ void cuobjdumpParseBinary(unsigned int handle){ if (capability > max_capability) max_capability = capability; } if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); - #endif - unsigned max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); -- cgit v1.3 From 6d36a6a20f6e0c7082243c0dabe1a6b734c5002b Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sat, 31 Mar 2018 08:48:47 -0700 Subject: masked declaration leading to using unitialized buffer as file name, leading to crash this still fails regressions --- src/cuda-sim/ptx_loader.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 9ff0859..34870c4 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -410,7 +410,7 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num printf(" and have \'cat\' and \'sed\' in your path.\n"); exit(1); } - char tempfile_ptxinfo[1024]; + //char tempfile_ptxinfo[1024]; snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); char extra_flags[1024]; extra_flags[0]=0; -- cgit v1.3 From 0c6928caf8814bf9bd37602bffe6b7b0021f2585 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Sun, 1 Apr 2018 12:48:14 -0400 Subject: Stats are now printing properly. Checked in bfs --- src/stream_manager.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 3b6cbd5..21115c6 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -230,7 +230,7 @@ bool stream_manager::operation( bool * sim) { bool check=check_finished_kernel(); pthread_mutex_lock(&m_lock); -// if(check)m_gpu->print_stats(); + if(check)m_gpu->print_stats(); stream_operation op =front(); if(!op.do_operation( m_gpu )) //not ready to execute { -- cgit v1.3 From 48c9d92e2be9a9fe264d3783b0b3ee7af8295b53 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sun, 1 Apr 2018 16:33:59 -0700 Subject: add pdom analysis for function calls -- doesn't fix regressions --- src/cuda-sim/cuda-sim.cc | 2 +- src/cuda-sim/instructions.cc | 9 ++++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 39a04dd..987e3f2 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -255,10 +255,10 @@ void function_info::ptx_assemble() printf(" done.\n"); fflush(stdout); - printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", m_name.c_str() ); //disable pdom analysis here and do it at runtime #if 0 + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", m_name.c_str() ); create_basic_blocks(); connect_basic_blocks(); bool modified = false; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 71286c9..5d97287 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1466,7 +1466,14 @@ void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) const operand_info &target = pI->func_addr(); assert( target.is_function_address() ); const symbol *func_addr = target.get_symbol(); - const function_info *target_func = func_addr->get_pc(); + function_info *target_func = func_addr->get_pc(); + if (target_func->is_pdom_set()) { + printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", target_func->get_name().c_str() ); + } else { + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", target_func->get_name().c_str() ); + target_func->do_pdom(); + target_func->set_pdom(); + } // check that number of args and return match function requirements if( pI->has_return() ^ target_func->has_return() ) { -- cgit v1.3 From deee9038d3d67e60f106776be3dd0a846dd11df9 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sun, 1 Apr 2018 17:31:14 -0700 Subject: fix regressions -- move call to pre_decode into do_pdom --- src/cuda-sim/cuda-sim.cc | 4 ++-- src/cuda-sim/ptx_ir.cc | 57 ++++++++++++++++++++++++++++-------------------- src/cuda-sim/ptx_ir.h | 2 ++ 3 files changed, 37 insertions(+), 26 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 987e3f2..dce35ca 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -252,7 +252,7 @@ void function_info::ptx_assemble() target.set_type(label_t); } } - + m_n = n; printf(" done.\n"); fflush(stdout); @@ -282,7 +282,6 @@ void function_info::ptx_assemble() print_postdominators(); print_ipostdominators(); } -#endif printf("GPGPU-Sim PTX: pre-decoding instructions for \'%s\'...\n", m_name.c_str() ); for ( unsigned ii=0; ii < n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions @@ -293,6 +292,7 @@ void function_info::ptx_assemble() fflush(stdout); m_assembled = true; +#endif } addr_t shared_to_generic( unsigned smid, addr_t addr ) diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 17e91df..be25dbe 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -577,30 +577,39 @@ bool function_info::connect_break_targets() //connecting break instructions with return modified; } -void function_info::do_pdom() { - create_basic_blocks(); - connect_basic_blocks(); - bool modified = false; - do { - find_dominators(); - find_idominators(); - modified = connect_break_targets(); - } while (modified == true); - - if ( g_debug_execution>=50 ) { - print_basic_blocks(); - print_basic_block_links(); - print_basic_block_dot(); - } - if ( g_debug_execution>=2 ) { - print_dominators(); - } - find_postdominators(); - find_ipostdominators(); - if ( g_debug_execution>=50 ) { - print_postdominators(); - print_ipostdominators(); - } +void function_info::do_pdom() +{ + create_basic_blocks(); + connect_basic_blocks(); + bool modified = false; + do { + find_dominators(); + find_idominators(); + modified = connect_break_targets(); + } while (modified == true); + + if ( g_debug_execution>=50 ) { + print_basic_blocks(); + print_basic_block_links(); + print_basic_block_dot(); + } + if ( g_debug_execution>=2 ) { + print_dominators(); + } + find_postdominators(); + find_ipostdominators(); + if ( g_debug_execution>=50 ) { + print_postdominators(); + print_ipostdominators(); + } + printf("GPGPU-Sim PTX: pre-decoding instructions for \'%s\'...\n", m_name.c_str() ); + for ( unsigned ii=0; ii < m_n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions + ptx_instruction *pI = m_instr_mem[ii]; + pI->pre_decode(); + } + printf("GPGPU-Sim PTX: ... done pre-decoding instructions for \'%s\'.\n", m_name.c_str() ); + fflush(stdout); + m_assembled = true; } void intersect( std::set &A, const std::set &B ) { diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 26a2839..85b2a3b 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1308,6 +1308,8 @@ private: //parameter size for device kernels int m_args_aligned_size; + + addr_t m_n; // offset in m_instr_mem (used in do_pdom) }; class arg_buffer_t { -- cgit v1.3 From c5da0034dd329976c77e2951e2f879095ea8cdac Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 2 Apr 2018 15:23:44 -0400 Subject: Adding in Mahmoud's changes to the print cache stats --- src/gpgpu-sim/gpu-cache.cc | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 5ea4190..8886398 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -517,18 +517,28 @@ void cache_stats::print_stats(FILE *fout, const char *cache_name) const{ /// the provided name is used. /// The printed format is "[][] = " /// + std::vector< unsigned > total_access; + total_access.resize(NUM_MEM_ACCESS_TYPE, 0); std::string m_cache_name = cache_name; for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) { for (unsigned status = 0; status < NUM_CACHE_REQUEST_STATUS; ++status) { - if(m_stats[type][status] > 0){ - fprintf(fout, "\t%s[%s][%s] = %u\n", - m_cache_name.c_str(), - mem_access_type_str((enum mem_access_type)type), - cache_request_status_str((enum cache_request_status)status), - m_stats[type][status]); - } + fprintf(fout, "\t%s[%s][%s] = %u\n", + m_cache_name.c_str(), + mem_access_type_str((enum mem_access_type)type), + cache_request_status_str((enum cache_request_status)status), + m_stats[type][status]); + if(status != RESERVATION_FAIL) + total_access[type]+= m_stats[type][status]; } } + for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) { + if(total_access[type] > 0) + fprintf(fout, "\t%s[%s][%s] = %u\n", + m_cache_name.c_str(), + mem_access_type_str((enum mem_access_type)type), + "TOTAL_ACCESS", + total_access[type]); + } } void cache_sub_stats::print_port_stats(FILE *fout, const char *cache_name) const -- cgit v1.3 From 26476592e3650e796b51c94dd1a25c162eb1aa64 Mon Sep 17 00:00:00 2001 From: Amruth Date: Tue, 3 Apr 2018 11:43:46 -0700 Subject: crash when print() is sent to pdom analysis --- libcuda/cuda_runtime_api.cc | 15 +- libcuda/cuda_runtime_api.cc~ | 2515 +++++++++++++++++++++++ src/cuda-sim/cuda-sim.cc~ | 2155 ++++++++++++++++++++ src/cuda-sim/instructions.cc | 7 +- src/cuda-sim/instructions.cc~ | 4517 +++++++++++++++++++++++++++++++++++++++++ src/cuda-sim/ptx_loader.cc~ | 462 +++++ 6 files changed, 9663 insertions(+), 8 deletions(-) create mode 100644 libcuda/cuda_runtime_api.cc~ create mode 100644 src/cuda-sim/cuda-sim.cc~ create mode 100644 src/cuda-sim/instructions.cc~ create mode 100644 src/cuda-sim/ptx_loader.cc~ diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 6cf21dd..ded1aee 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1499,6 +1499,12 @@ void extract_code_using_cuobjdump(){ no_of_ptx = no_of_ptx + 1; fclose(fp); } + if(no_of_ptx==0){ + printf("WARNING: Number of ptx in the executable file are 0. One of the reasons might be\n"); + printf("\t1. CDP is enabled\n"); + printf("\t2. cuobjdump -lptx doesnt recognize sm_%u\n",forced_max_capability); + printf("\t3. the application was not compiled with nvcc flag sm_%u\n",forced_max_capability); + } } if(!g_cdp_enabled) { //based on the list above, dump ptx files individually. Format of dumped ptx file is prog_name.unique_no.sm_<>.ptx @@ -1520,15 +1526,10 @@ void extract_code_using_cuobjdump(){ snprintf(fname,1024,"_cuobjdump_complete_output_XXXXXX"); int fd=mkstemp(fname); close(fd); - if(!g_cdp_enabled) { -#if (CUDART_VERSION >= 6000) - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname); -#else + if(!g_cdp_enabled) snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass %s > %s", app_binary.c_str(), fname); -#endif - } else { + else snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); - } bool parse_output = true; result = system(command); if(result) { diff --git a/libcuda/cuda_runtime_api.cc~ b/libcuda/cuda_runtime_api.cc~ new file mode 100644 index 0000000..de7f5e9 --- /dev/null +++ b/libcuda/cuda_runtime_api.cc~ @@ -0,0 +1,2515 @@ +// This file created from cuda_runtime_api.h distributed with CUDA 1.1 +// Changes Copyright 2009, Tor M. Aamodt, Ali Bakhoda and George L. Yuan +// University of British Columbia + +/* + * cuda_runtime_api.cc + * + * Copyright © 2009 by Tor M. Aamodt, Wilson W. L. Fung, Ali Bakhoda, + * George L. Yuan and the University of British Columbia, Vancouver, + * BC V6T 1Z4, All Rights Reserved. + * + * THIS IS A LEGAL DOCUMENT BY DOWNLOADING GPGPU-SIM, YOU ARE AGREEING TO THESE + * TERMS AND CONDITIONS. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * NOTE: The files libcuda/cuda_runtime_api.c and src/cuda-sim/cuda-math.h + * are derived from the CUDA Toolset available from http://www.nvidia.com/cuda + * (property of NVIDIA). The files benchmarks/BlackScholes/ and + * benchmarks/template/ are derived from the CUDA SDK available from + * http://www.nvidia.com/cuda (also property of NVIDIA). The files from + * src/intersim/ are derived from Booksim (a simulator provided with the + * textbook "Principles and Practices of Interconnection Networks" available + * from http://cva.stanford.edu/books/ppin/). As such, those files are bound by + * the corresponding legal terms and conditions set forth separately (original + * copyright notices are left in files from these sources and where we have + * modified a file our copyright notice appears before the original copyright + * notice). + * + * Using this version of GPGPU-Sim requires a complete installation of CUDA + * which is distributed seperately by NVIDIA under separate terms and + * conditions. To use this version of GPGPU-Sim with OpenCL requires a + * recent version of NVIDIA's drivers which support OpenCL. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the University of British Columbia nor the names of + * its contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * 4. This version of GPGPU-SIM is distributed freely for non-commercial use only. + * + * 5. No nonprofit user may place any restrictions on the use of this software, + * including as modified by the user, by any other authorized user. + * + * 6. GPGPU-SIM was developed primarily by Tor M. Aamodt, Wilson W. L. Fung, + * Ali Bakhoda, George L. Yuan, at the University of British Columbia, + * Vancouver, BC V6T 1Z4 + */ + +/* + * Copyright 1993-2007 NVIDIA Corporation. All rights reserved. + * + * NOTICE TO USER: + * + * This source code is subject to NVIDIA ownership rights under U.S. and + * international Copyright laws. Users and possessors of this source code + * are hereby granted a nonexclusive, royalty-free license to use this code + * in individual and commercial software. + * + * NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE + * CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR + * IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE. + * IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS + * OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE + * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE + * OR PERFORMANCE OF THIS SOURCE CODE. + * + * U.S. Government End Users. This source code is a "commercial item" as + * that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of + * "commercial computer software" and "commercial computer software + * documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995) + * and is provided to the U.S. Government only as a commercial end item. + * Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through + * 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the + * source code with only those rights set forth herein. + * + * Any use of this source code in individual and commercial software must + * include, in the user documentation and internal comments to the code, + * the above Disclaimer and U.S. Government End Users Notice. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef OPENGL_SUPPORT +#define GL_GLEXT_PROTOTYPES +#ifdef __APPLE__ +#include // Apple's version of GLUT is here +#else +#include +#endif +#endif + +#define __CUDA_RUNTIME_API_H__ + +#include "host_defines.h" +#include "builtin_types.h" +#include "driver_types.h" +#if (CUDART_VERSION < 8000) +#include "__cudaFatFormat.h" +#endif +#include "../src/gpgpu-sim/gpu-sim.h" +#include "../src/cuda-sim/ptx_loader.h" +#include "../src/cuda-sim/cuda-sim.h" +#include "../src/cuda-sim/ptx_ir.h" +#include "../src/cuda-sim/ptx_parser.h" +#include "../src/gpgpusim_entrypoint.h" +#include "../src/stream_manager.h" +#include "../src/abstract_hardware_model.h" + +#include +#include + +#ifdef __APPLE__ +#include +#endif + +std::map pinned_memory; //support for pinned memories added +std::map pinned_memory_size; +int no_of_ptx=0; + +extern void synchronize(); +extern void exit_simulation(); + +static int load_static_globals( symbol_table *symtab, unsigned min_gaddr, unsigned max_gaddr, gpgpu_t *gpu ); +static int load_constants( symbol_table *symtab, addr_t min_gaddr, gpgpu_t *gpu ); + +static kernel_info_t *gpgpu_cuda_ptx_sim_init_grid( const char *kernel_key, + gpgpu_ptx_sim_arg_list_t args, + struct dim3 gridDim, + struct dim3 blockDim, + struct CUctx_st* context ); + +/*DEVICE_BUILTIN*/ +struct cudaArray +{ + void *devPtr; + int devPtr32; + struct cudaChannelFormatDesc desc; + int width; + int height; + int size; //in bytes + unsigned dimensions; +}; + +#if !defined(__dv) +#if defined(__cplusplus) +#define __dv(v) \ + = v +#else /* __cplusplus */ +#define __dv(v) +#endif /* __cplusplus */ +#endif /* !__dv */ + +cudaError_t g_last_cudaError = cudaSuccess; + +extern stream_manager *g_stream_manager; + +void register_ptx_function( const char *name, function_info *impl ) +{ + // no longer need this +} + +#if defined __APPLE__ +# define __my_func__ __PRETTY_FUNCTION__ +#else +# if defined __cplusplus ? __GNUC_PREREQ (2, 6) : __GNUC_PREREQ (2, 4) +# define __my_func__ __PRETTY_FUNCTION__ +# else +# if defined __STDC_VERSION__ && __STDC_VERSION__ >= 199901L +# define __my_func__ __func__ +# else +# define __my_func__ ((__const char *) 0) +# endif +# endif +#endif + +struct _cuda_device_id { + _cuda_device_id(gpgpu_sim* gpu) {m_id = 0; m_next = NULL; m_gpgpu=gpu;} + struct _cuda_device_id *next() { return m_next; } + unsigned num_shader() const { return m_gpgpu->get_config().num_shader(); } + int num_devices() const { + if( m_next == NULL ) return 1; + else return 1 + m_next->num_devices(); + } + struct _cuda_device_id *get_device( unsigned n ) + { + assert( n < (unsigned)num_devices() ); + struct _cuda_device_id *p=this; + for(unsigned i=0; im_next; + return p; + } + const struct cudaDeviceProp *get_prop() const + { + return m_gpgpu->get_prop(); + } + unsigned get_id() const { return m_id; } + + gpgpu_sim *get_gpgpu() { return m_gpgpu; } +private: + unsigned m_id; + class gpgpu_sim *m_gpgpu; + struct _cuda_device_id *m_next; +}; + +struct CUctx_st { + CUctx_st( _cuda_device_id *gpu ) + { + m_gpu = gpu; + m_binary_info.cmem = 0; + m_binary_info.gmem = 0; + } + + _cuda_device_id *get_device() { return m_gpu; } + + void add_binary( symbol_table *symtab, unsigned fat_cubin_handle ) + { + m_code[fat_cubin_handle] = symtab; + m_last_fat_cubin_handle = fat_cubin_handle; + } + + void add_ptxinfo( const char *deviceFun, const struct gpgpu_ptx_sim_info &info ) + { + symbol *s = m_code[m_last_fat_cubin_handle]->lookup(deviceFun); + assert( s != NULL ); + function_info *f = s->get_pc(); + assert( f != NULL ); + f->set_kernel_info(info); + } + + void add_ptxinfo( const struct gpgpu_ptx_sim_info &info ) + { + m_binary_info = info; + } + + void register_function( unsigned fat_cubin_handle, const char *hostFun, const char *deviceFun ) + { + if( m_code.find(fat_cubin_handle) != m_code.end() ) { + symbol *s = m_code[fat_cubin_handle]->lookup(deviceFun); + if(s != NULL) { + function_info *f = s->get_pc(); + assert( f != NULL ); + m_kernel_lookup[hostFun] = f; + } + else { + printf("Warning: cannot find deviceFun %s\n", deviceFun); + m_kernel_lookup[hostFun] = NULL; + } + // assert( s != NULL ); + // function_info *f = s->get_pc(); + // assert( f != NULL ); + // m_kernel_lookup[hostFun] = f; + } else { + m_kernel_lookup[hostFun] = NULL; + } + } + + function_info *get_kernel(const char *hostFun) + { + std::map::iterator i=m_kernel_lookup.find(hostFun); + assert( i != m_kernel_lookup.end() ); + return i->second; + } + +private: + _cuda_device_id *m_gpu; // selected gpu + std::map m_code; // fat binary handle => global symbol table + unsigned m_last_fat_cubin_handle; + std::map m_kernel_lookup; // unique id (CUDA app function address) => kernel entry point + struct gpgpu_ptx_sim_info m_binary_info; + +}; + +class kernel_config { +public: + kernel_config( dim3 GridDim, dim3 BlockDim, size_t sharedMem, struct CUstream_st *stream ) + { + m_GridDim=GridDim; + m_BlockDim=BlockDim; + m_sharedMem=sharedMem; + m_stream = stream; + } + void set_arg( const void *arg, size_t size, size_t offset ) + { + m_args.push_front( gpgpu_ptx_sim_arg(arg,size,offset) ); + } + dim3 grid_dim() const { return m_GridDim; } + dim3 block_dim() const { return m_BlockDim; } + gpgpu_ptx_sim_arg_list_t get_args() { return m_args; } + struct CUstream_st *get_stream() { return m_stream; } + +private: + dim3 m_GridDim; + dim3 m_BlockDim; + size_t m_sharedMem; + struct CUstream_st *m_stream; + gpgpu_ptx_sim_arg_list_t m_args; +}; + +class _cuda_device_id *GPGPUSim_Init() +{ + static _cuda_device_id *the_device = NULL; + if( !the_device ) { + gpgpu_sim *the_gpu = gpgpu_ptx_sim_init_perf(); + + cudaDeviceProp *prop = (cudaDeviceProp *) calloc(sizeof(cudaDeviceProp),1); + snprintf(prop->name,256,"GPGPU-Sim_v%s", g_gpgpusim_version_string ); + prop->major = 5; + prop->minor = 2; + prop->totalGlobalMem = 0x80000000 /* 2 GB */; + prop->memPitch = 0; + prop->maxThreadsPerBlock = 512; + prop->maxThreadsDim[0] = 512; + prop->maxThreadsDim[1] = 512; + prop->maxThreadsDim[2] = 512; + prop->maxGridSize[0] = 0x40000000; + prop->maxGridSize[1] = 0x40000000; + prop->maxGridSize[2] = 0x40000000; + prop->totalConstMem = 0x40000000; + prop->textureAlignment = 0; + prop->sharedMemPerBlock = the_gpu->shared_mem_size(); + prop->regsPerBlock = the_gpu->num_registers_per_core(); + prop->warpSize = the_gpu->wrp_size(); + prop->clockRate = the_gpu->shader_clock(); +#if (CUDART_VERSION >= 2010) + prop->multiProcessorCount = the_gpu->get_config().num_shader(); +#endif + the_gpu->set_prop(prop); + the_device = new _cuda_device_id(the_gpu); + } + start_sim_thread(1); + return the_device; +} + +static CUctx_st* GPGPUSim_Context() +{ + static CUctx_st *the_context = NULL; + if( the_context == NULL ) { + _cuda_device_id *the_gpu = GPGPUSim_Init(); + the_context = new CUctx_st(the_gpu); + } + return the_context; +} + + void ptxinfo_addinfo() +{ + if(!get_ptxinfo_kname()){ + /* This info is not per kernel (since CUDA 5.0 some info (e.g. gmem, and cmem) is added at the beginning for the whole binary ) */ + CUctx_st *context = GPGPUSim_Context(); + print_ptxinfo(); + context->add_ptxinfo(get_ptxinfo()); + clear_ptxinfo(); + return; + } + if( !strcmp("__cuda_dummy_entry__",get_ptxinfo_kname()) ) { + // this string produced by ptxas for empty ptx files (e.g., bandwidth test) + clear_ptxinfo(); + return; + } + CUctx_st *context = GPGPUSim_Context(); + print_ptxinfo(); + context->add_ptxinfo( get_ptxinfo_kname(), get_ptxinfo() ); + clear_ptxinfo(); +} + +void cuda_not_implemented( const char* func, unsigned line ) +{ + fflush(stdout); + fflush(stderr); + printf("\n\nGPGPU-Sim PTX: Execution error: CUDA API function \"%s()\" has not been implemented yet.\n" + " [$GPGPUSIM_ROOT/libcuda/%s around line %u]\n\n\n", + func,__FILE__, line ); + fflush(stdout); + abort(); +} + + +#define gpgpusim_ptx_error(msg, ...) gpgpusim_ptx_error_impl(__func__, __FILE__,__LINE__, msg, ##__VA_ARGS__) +#define gpgpusim_ptx_assert(cond,msg, ...) gpgpusim_ptx_assert_impl((cond),__func__, __FILE__,__LINE__, msg, ##__VA_ARGS__) + +void gpgpusim_ptx_error_impl( const char *func, const char *file, unsigned line, const char *msg, ... ) +{ + va_list ap; + char buf[1024]; + va_start(ap,msg); + vsnprintf(buf,1024,msg,ap); + va_end(ap); + + printf("GPGPU-Sim CUDA API: %s\n", buf); + printf(" [%s:%u : %s]\n", file, line, func ); + abort(); +} + +void gpgpusim_ptx_assert_impl( int test_value, const char *func, const char *file, unsigned line, const char *msg, ... ) +{ + va_list ap; + char buf[1024]; + va_start(ap,msg); + vsnprintf(buf,1024,msg,ap); + va_end(ap); + + if ( test_value == 0 ) + gpgpusim_ptx_error_impl(func, file, line, msg); +} + + +typedef std::map event_tracker_t; + +int CUevent_st::m_next_event_uid; +event_tracker_t g_timer_events; +int g_active_device = 0; //active gpu that runs the code +std::list g_cuda_launch_stack; + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +extern "C" { + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ +cudaError_t cudaPeekAtLastError(void) +{ + return g_last_cudaError; +} + +__host__ cudaError_t CUDARTAPI cudaMalloc(void **devPtr, size_t size) +{ + CUctx_st* context = GPGPUSim_Context(); + *devPtr = context->get_device()->get_gpgpu()->gpu_malloc(size); + if(g_debug_execution >= 3) + printf("GPGPU-Sim PTX: cudaMallocing %zu bytes starting at 0x%llx..\n",size, (unsigned long long) *devPtr); + if ( *devPtr ) { + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorMemoryAllocation; + } +} + +__host__ cudaError_t CUDARTAPI cudaMallocHost(void **ptr, size_t size) +{ + GPGPUSim_Context(); + *ptr = malloc(size); + if ( *ptr ) { + //track pinned memory size allocated in the host so that same amount of memory is also allocated in GPU. + pinned_memory_size[*ptr]=size; + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorMemoryAllocation; + } +} +__host__ cudaError_t CUDARTAPI cudaMallocPitch(void **devPtr, size_t *pitch, size_t width, size_t height) +{ + unsigned malloc_width_inbytes = width; + printf("GPGPU-Sim PTX: cudaMallocPitch (width = %d)\n", malloc_width_inbytes); + CUctx_st* ctx = GPGPUSim_Context(); + *devPtr = ctx->get_device()->get_gpgpu()->gpu_malloc(malloc_width_inbytes*height); + pitch[0] = malloc_width_inbytes; + if ( *devPtr ) { + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorMemoryAllocation; + } +} + +__host__ cudaError_t CUDARTAPI cudaMallocArray(struct cudaArray **array, const struct cudaChannelFormatDesc *desc, size_t width, size_t height __dv(1)) +{ + unsigned size = width * height * ((desc->x + desc->y + desc->z + desc->w)/8); + CUctx_st* context = GPGPUSim_Context(); + (*array) = (struct cudaArray*) malloc(sizeof(struct cudaArray)); + (*array)->desc = *desc; + (*array)->width = width; + (*array)->height = height; + (*array)->size = size; + (*array)->dimensions = 2; + ((*array)->devPtr32)= (int) (long long)context->get_device()->get_gpgpu()->gpu_mallocarray(size); + printf("GPGPU-Sim PTX: cudaMallocArray: devPtr32 = %d\n", ((*array)->devPtr32)); + ((*array)->devPtr) = (void*) (long long) ((*array)->devPtr32); + if ( ((*array)->devPtr) ) { + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorMemoryAllocation; + } +} + +__host__ cudaError_t CUDARTAPI cudaFree(void *devPtr) +{ + // TODO... manage g_global_mem space? + return g_last_cudaError = cudaSuccess; +} +__host__ cudaError_t CUDARTAPI cudaFreeHost(void *ptr) +{ + free (ptr); // this will crash the system if called twice + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaFreeArray(struct cudaArray *array) +{ + // TODO... manage g_global_mem space? + return g_last_cudaError = cudaSuccess; +}; + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaMemcpy(void *dst, const void *src, size_t count, enum cudaMemcpyKind kind) +{ + //CUctx_st *context = GPGPUSim_Context(); + //gpgpu_t *gpu = context->get_device()->get_gpgpu(); + if(g_debug_execution >= 3) + printf("GPGPU-Sim PTX: cudaMemcpy(): devPtr = %p\n", dst); + if( kind == cudaMemcpyHostToDevice ) + g_stream_manager->push( stream_operation(src,(size_t)dst,count,0) ); + else if( kind == cudaMemcpyDeviceToHost ) + g_stream_manager->push( stream_operation((size_t)src,dst,count,0) ); + else if( kind == cudaMemcpyDeviceToDevice ) + g_stream_manager->push( stream_operation((size_t)src,(size_t)dst,count,0) ); + else if ( kind == cudaMemcpyDefault ) { + if ((size_t)src >= GLOBAL_HEAP_START) { + if ((size_t)dst >= GLOBAL_HEAP_START) + g_stream_manager->push( stream_operation((size_t)src,(size_t)dst,count,0) ); // device to device + else + g_stream_manager->push( stream_operation((size_t)src,dst,count,0) ); // device to host + } + else { + if ((size_t)dst >= GLOBAL_HEAP_START) + g_stream_manager->push( stream_operation(src,(size_t)dst,count,0) ); + else { + printf("GPGPU-Sim PTX: cudaMemcpy - ERROR : unsupported transfer: host to host\n"); + abort(); + } + } + } + else { + printf("GPGPU-Sim PTX: cudaMemcpy - ERROR : unsupported cudaMemcpyKind\n"); + abort(); + } + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaMemcpyToArray(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t count, enum cudaMemcpyKind kind) +{ + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + size_t size = count; + printf("GPGPU-Sim PTX: cudaMemcpyToArray\n"); + if( kind == cudaMemcpyHostToDevice ) + gpu->memcpy_to_gpu( (size_t)(dst->devPtr), src, size); + else if( kind == cudaMemcpyDeviceToHost ) + gpu->memcpy_from_gpu( dst->devPtr, (size_t)src, size); + else if( kind == cudaMemcpyDeviceToDevice ) + gpu->memcpy_gpu_to_gpu( (size_t)(dst->devPtr), (size_t)src, size); + else { + printf("GPGPU-Sim PTX: cudaMemcpyToArray - ERROR : unsupported cudaMemcpyKind\n"); + abort(); + } + dst->devPtr32 = (unsigned) (size_t)(dst->devPtr); + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpyFromArray(void *dst, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t count, enum cudaMemcpyKind kind) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpyArrayToArray(struct cudaArray *dst, size_t wOffsetDst, size_t hOffsetDst, const struct cudaArray *src, size_t wOffsetSrc, size_t hOffsetSrc, size_t count, enum cudaMemcpyKind kind __dv(cudaMemcpyDeviceToDevice)) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpy2D(void *dst, size_t dpitch, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind) +{ + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + size_t size = spitch*height; + gpgpusim_ptx_assert( (dpitch==spitch), "different src and dst pitch not supported yet" ); + if( kind == cudaMemcpyHostToDevice ) + gpu->memcpy_to_gpu( (size_t)dst, src, size ); + else if( kind == cudaMemcpyDeviceToHost ) + gpu->memcpy_from_gpu( dst, (size_t)src, size ); + else if( kind == cudaMemcpyDeviceToDevice ) + gpu->memcpy_gpu_to_gpu( (size_t)dst, (size_t)src, size); + else { + printf("GPGPU-Sim PTX: cudaMemcpy2D - ERROR : unsupported cudaMemcpyKind\n"); + abort(); + } + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpy2DToArray(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind) +{ + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + size_t size = spitch*height; + size_t channel_size = dst->desc.w+dst->desc.x+dst->desc.y+dst->desc.z; + gpgpusim_ptx_assert( ((channel_size%8) == 0), "none byte multiple destination channel size not supported (sz=%u)", channel_size ); + unsigned elem_size = channel_size/8; + gpgpusim_ptx_assert( (dst->dimensions==2), "copy to none 2D array not supported" ); + gpgpusim_ptx_assert( (wOffset==0), "non-zero wOffset not yet supported" ); + gpgpusim_ptx_assert( (hOffset==0), "non-zero hOffset not yet supported" ); + gpgpusim_ptx_assert( (dst->height == (int)height), "partial copy not supported" ); + gpgpusim_ptx_assert( (elem_size*dst->width == width), "partial copy not supported" ); + gpgpusim_ptx_assert( (spitch == width), "spitch != width not supported" ); + if( kind == cudaMemcpyHostToDevice ) + gpu->memcpy_to_gpu( (size_t)(dst->devPtr), src, size); + else if( kind == cudaMemcpyDeviceToHost ) + gpu->memcpy_from_gpu( dst->devPtr, (size_t)src, size); + else if( kind == cudaMemcpyDeviceToDevice ) + gpu->memcpy_gpu_to_gpu( (size_t)dst->devPtr, (size_t)src, size); + else { + printf("GPGPU-Sim PTX: cudaMemcpy2D - ERROR : unsupported cudaMemcpyKind\n"); + abort(); + } + dst->devPtr32 = (unsigned) (size_t)(dst->devPtr); + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpy2DFromArray(void *dst, size_t dpitch, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t width, size_t height, enum cudaMemcpyKind kind) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpy2DArrayToArray(struct cudaArray *dst, size_t wOffsetDst, size_t hOffsetDst, const struct cudaArray *src, size_t wOffsetSrc, size_t hOffsetSrc, size_t width, size_t height, enum cudaMemcpyKind kind __dv(cudaMemcpyDeviceToDevice)) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpyToSymbol(const char *symbol, const void *src, size_t count, size_t offset __dv(0), enum cudaMemcpyKind kind __dv(cudaMemcpyHostToDevice)) +{ + //CUctx_st *context = GPGPUSim_Context(); + assert(kind == cudaMemcpyHostToDevice); + printf("GPGPU-Sim PTX: cudaMemcpyToSymbol: symbol = %p\n", symbol); + //stream_operation( const char *symbol, const void *src, size_t count, size_t offset ) + g_stream_manager->push( stream_operation(src,symbol,count,offset,0) ); + //gpgpu_ptx_sim_memcpy_symbol(symbol,src,count,offset,1,context->get_device()->get_gpgpu()); + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpyFromSymbol(void *dst, const char *symbol, size_t count, size_t offset __dv(0), enum cudaMemcpyKind kind __dv(cudaMemcpyDeviceToHost)) +{ + //CUctx_st *context = GPGPUSim_Context(); + assert(kind == cudaMemcpyDeviceToHost); + printf("GPGPU-Sim PTX: cudaMemcpyFromSymbol: symbol = %p\n", symbol); + g_stream_manager->push( stream_operation(symbol,dst,count,offset,0) ); + //gpgpu_ptx_sim_memcpy_symbol(symbol,dst,count,offset,0,context->get_device()->get_gpgpu()); + return g_last_cudaError = cudaSuccess; +} + + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaMemcpyAsync(void *dst, const void *src, size_t count, enum cudaMemcpyKind kind, cudaStream_t stream) +{ + struct CUstream_st *s = (struct CUstream_st *)stream; + switch( kind ) { + case cudaMemcpyHostToDevice: g_stream_manager->push( stream_operation(src,(size_t)dst,count,s) ); break; + case cudaMemcpyDeviceToHost: g_stream_manager->push( stream_operation((size_t)src,dst,count,s) ); break; + case cudaMemcpyDeviceToDevice: g_stream_manager->push( stream_operation((size_t)src,(size_t)dst,count,s) ); break; + default: + abort(); + } + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpyToArrayAsync(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t count, enum cudaMemcpyKind kind, cudaStream_t stream) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpyFromArrayAsync(void *dst, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t count, enum cudaMemcpyKind kind, cudaStream_t stream) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpy2DAsync(void *dst, size_t dpitch, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind, cudaStream_t stream) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpy2DToArrayAsync(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind, cudaStream_t stream) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpy2DFromArrayAsync(void *dst, size_t dpitch, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t width, size_t height, enum cudaMemcpyKind kind, cudaStream_t stream) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaMemset(void *mem, int c, size_t count) +{ + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + gpu->gpu_memset((size_t)mem, c, count); + return g_last_cudaError = cudaSuccess; +} + +//memset operation is done but i think its not async? +__host__ cudaError_t CUDARTAPI cudaMemsetAsync(void *mem, int c, size_t count, cudaStream_t stream=0) +{ + printf("GPGPU-Sim PTX: WARNING: Asynchronous memset not supported (%s)\n", __my_func__); + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + gpu->gpu_memset((size_t)mem, c, count); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaMemset2D(void *mem, size_t pitch, int c, size_t width, size_t height) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaGetSymbolAddress(void **devPtr, const char *symbol) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaGetSymbolSize(size_t *size, const char *symbol) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ +__host__ cudaError_t CUDARTAPI cudaGetDeviceCount(int *count) +{ + _cuda_device_id *dev = GPGPUSim_Init(); + *count = dev->num_devices(); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaGetDeviceProperties(struct cudaDeviceProp *prop, int device) +{ + _cuda_device_id *dev = GPGPUSim_Init(); + if (device <= dev->num_devices() ) { + *prop= *dev->get_prop(); + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorInvalidDevice; + } +} + +#if (CUDART_VERSION > 5000) +__host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDeviceAttr attr, int device) +{ + const struct cudaDeviceProp *prop; + _cuda_device_id *dev = GPGPUSim_Init(); + if (device <= dev->num_devices() ) { + prop = dev->get_prop(); + switch (attr) { + case 5: + *value= prop->maxGridSize[0]; + break; + case 6: + *value= prop->maxGridSize[1]; + break; + case 7: + *value= prop->maxGridSize[2]; + break; + case 10: + *value= prop->warpSize; + break; + case 12: + *value= prop->regsPerBlock; + break; + case 14: + *value= prop->textureAlignment ; + break; + case 16: + *value= prop->multiProcessorCount ; + break; + case 39: + *value= dev->get_gpgpu()->threads_per_core(); + break; + case 75: + *value= 8 ; + break; + case 76: + *value= 3 ; + break; + case 78: + *value= 0 ; //TODO: as of now, we dont support stream priorities. + break; + default: + printf("ERROR: implement the attribute numbered %d \n",attr); + abort(); + } + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorInvalidDevice; + } +} +#endif + +__host__ cudaError_t CUDARTAPI cudaChooseDevice(int *device, const struct cudaDeviceProp *prop) +{ + _cuda_device_id *dev = GPGPUSim_Init(); + *device = dev->get_id(); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaSetDevice(int device) +{ + //set the active device to run cuda + if ( device <= GPGPUSim_Init()->num_devices() ) { + g_active_device = device; + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorInvalidDevice; + } +} + +__host__ cudaError_t CUDARTAPI cudaGetDevice(int *device) +{ + *device = g_active_device; + return g_last_cudaError = cudaSuccess; +} + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaBindTexture(size_t *offset, + const struct textureReference *texref, + const void *devPtr, + const struct cudaChannelFormatDesc *desc, + size_t size __dv(UINT_MAX)) +{ + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + printf("GPGPU-Sim PTX: in cudaBindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); + struct cudaArray *array; + array = (struct cudaArray*) malloc(sizeof(struct cudaArray)); + array->desc = *desc; + array->size = size; + array->width = size; + array->height = 1; + array->dimensions = 1; + array->devPtr = (void*)devPtr; + array->devPtr32 = (int)(long long)devPtr; + offset = 0; + printf("GPGPU-Sim PTX: size = %zu\n", size); + printf("GPGPU-Sim PTX: texref = %p, array = %p\n", texref, array); + printf("GPGPU-Sim PTX: devPtr32 = %x\n", array->devPtr32); + printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); + printf("GPGPU-Sim PTX: ChannelFormatDesc: x=%d, y=%d, z=%d, w=%d\n", desc->x, desc->y, desc->z, desc->w); + printf("GPGPU-Sim PTX: Texture Normalized? = %d\n", texref->normalized); + gpu->gpgpu_ptx_sim_bindTextureToArray(texref, array); + devPtr = (void*)(long long)array->devPtr32; + printf("GPGPU-Sim PTX: devPtr = %p\n", devPtr); + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureReference *texref, const struct cudaArray *array, const struct cudaChannelFormatDesc *desc) +{ + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + printf("GPGPU-Sim PTX: in cudaBindTextureToArray: %p %p\n", texref, array); + printf("GPGPU-Sim PTX: devPtr32 = %x\n", array->devPtr32); + printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); + printf("GPGPU-Sim PTX: Texture Normalized? = %d\n", texref->normalized); + gpu->gpgpu_ptx_sim_bindTextureToArray(texref, array); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) +{ + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaGetTextureAlignmentOffset(size_t *offset, const struct textureReference *texref) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + +__host__ cudaError_t CUDARTAPI cudaGetTextureReference(const struct textureReference **texref, const char *symbol) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + +__host__ cudaError_t CUDARTAPI cudaGetChannelDesc(struct cudaChannelFormatDesc *desc, const struct cudaArray *array) +{ + *desc = array->desc; + return g_last_cudaError = cudaSuccess; +} + + +__host__ struct cudaChannelFormatDesc CUDARTAPI cudaCreateChannelDesc(int x, int y, int z, int w, enum cudaChannelFormatKind f) +{ + struct cudaChannelFormatDesc dummy; + dummy.x = x; + dummy.y = y; + dummy.z = z; + dummy.w = w; + dummy.f = f; + return dummy; +} + +__host__ cudaError_t CUDARTAPI cudaGetLastError(void) +{ + return g_last_cudaError; +} + +__host__ const char* CUDARTAPI cudaGetErrorString(cudaError_t error) +{ + if( g_last_cudaError == cudaSuccess ) + return "no error"; + char buf[1024]; + snprintf(buf,1024,"<>", g_last_cudaError); + return strdup(buf); +} + +__host__ cudaError_t CUDARTAPI cudaConfigureCall(dim3 gridDim, dim3 blockDim, size_t sharedMem, cudaStream_t stream) +{ + struct CUstream_st *s = (struct CUstream_st *)stream; + g_cuda_launch_stack.push_back( kernel_config(gridDim,blockDim,sharedMem,s) ); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaSetupArgument(const void *arg, size_t size, size_t offset) +{ + gpgpusim_ptx_assert( !g_cuda_launch_stack.empty(), "empty launch stack" ); + kernel_config &config = g_cuda_launch_stack.back(); + config.set_arg(arg,size,offset); + + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaLaunch( const char *hostFun ) +{ + CUctx_st* context = GPGPUSim_Context(); + char *mode = getenv("PTX_SIM_MODE_FUNC"); + if( mode ) + sscanf(mode,"%u", &g_ptx_sim_mode); + gpgpusim_ptx_assert( !g_cuda_launch_stack.empty(), "empty launch stack" ); + kernel_config config = g_cuda_launch_stack.back(); + struct CUstream_st *stream = config.get_stream(); + printf("\nGPGPU-Sim PTX: cudaLaunch for 0x%p (mode=%s) on stream %u\n", hostFun, + g_ptx_sim_mode?"functional simulation":"performance simulation", stream?stream->get_uid():0 ); + kernel_info_t *grid = gpgpu_cuda_ptx_sim_init_grid(hostFun,config.get_args(),config.grid_dim(),config.block_dim(),context); + //do dynamic PDOM analysis for performance simulation scenario + std::string kname = grid->name(); + function_info *kernel_func_info = grid->entry(); + if (kernel_func_info->is_pdom_set()) { + printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", kname.c_str() ); + } else { + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", kname.c_str() ); + kernel_func_info->do_pdom(); + kernel_func_info->set_pdom(); + } + dim3 gridDim = config.grid_dim(); + dim3 blockDim = config.block_dim(); + printf("GPGPU-Sim PTX: pushing kernel \'%s\' to stream %u, gridDim= (%u,%u,%u) blockDim = (%u,%u,%u) \n", + kname.c_str(), stream?stream->get_uid():0, gridDim.x,gridDim.y,gridDim.z,blockDim.x,blockDim.y,blockDim.z ); + stream_operation op(grid,g_ptx_sim_mode,stream); + g_stream_manager->push(op); + g_cuda_launch_stack.pop_back(); + return g_last_cudaError = cudaSuccess; +} + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaStreamCreate(cudaStream_t *stream) +{ + printf("GPGPU-Sim PTX: cudaStreamCreate\n"); +#if (CUDART_VERSION >= 3000) + *stream = new struct CUstream_st(); + g_stream_manager->add_stream(*stream); +#else + *stream = 0; + printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); +#endif + return g_last_cudaError = cudaSuccess; +} + +//TODO: introduce priorities +__host__ cudaError_t CUDARTAPI cudaStreamCreateWithPriority(cudaStream_t *stream, unsigned int flags, int priority) { + return cudaStreamCreate(stream); +} + +__host__ cudaError_t CUDARTAPI cudaDeviceGetStreamPriorityRange(int* leastPriority, int* greatestPriority) { + return cudaSuccess; +} + +__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *pStream, unsigned int flags) { + return cudaStreamCreate(pStream); +} + +__host__ cudaError_t CUDARTAPI cudaStreamDestroy(cudaStream_t stream) +{ +#if (CUDART_VERSION >= 3000) + g_stream_manager->destroy_stream(stream); +#endif + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaStreamSynchronize(cudaStream_t stream) +{ +#if (CUDART_VERSION >= 3000) + if( stream == NULL ) + synchronize(); + return g_last_cudaError = cudaSuccess; + stream->synchronize(); +#else + printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); +#endif + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) +{ +#if (CUDART_VERSION >= 3000) + if( stream == NULL ) + return g_last_cudaError = cudaErrorInvalidResourceHandle; + return g_last_cudaError = stream->empty()?cudaSuccess:cudaErrorNotReady; +#else + printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); + return g_last_cudaError = cudaSuccess; // it is always success because all cuda calls are synchronous +#endif +} + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaEventCreate(cudaEvent_t *event) +{ + CUevent_st *e = new CUevent_st(false); + g_timer_events[e->get_uid()] = e; +#if CUDART_VERSION >= 3000 + *event = e; +#else + *event = e->get_uid(); +#endif + return g_last_cudaError = cudaSuccess; +} + +CUevent_st *get_event(cudaEvent_t event) +{ + unsigned event_uid; +#if CUDART_VERSION >= 3000 + event_uid = event->get_uid(); +#else + event_uid = event; +#endif + event_tracker_t::iterator e = g_timer_events.find(event_uid); + if( e == g_timer_events.end() ) + return NULL; + return e->second; +} + +__host__ cudaError_t CUDARTAPI cudaEventRecord(cudaEvent_t event, cudaStream_t stream) +{ + CUevent_st *e = get_event(event); + if( !e ) return g_last_cudaError = cudaErrorUnknown; + struct CUstream_st *s = (struct CUstream_st *)stream; + stream_operation op(e,s); + g_stream_manager->push(op); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaEventQuery(cudaEvent_t event) +{ + CUevent_st *e = get_event(event); + if( e == NULL ) { + return g_last_cudaError = cudaErrorInvalidValue; + } else if( e->done() ) { + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorNotReady; + } +} + +__host__ cudaError_t CUDARTAPI cudaEventSynchronize(cudaEvent_t event) +{ + printf("GPGPU-Sim API: cudaEventSynchronize ** waiting for event\n"); + fflush(stdout); + CUevent_st *e = (CUevent_st*) event; + while( !e->done() ) + ; + printf("GPGPU-Sim API: cudaEventSynchronize ** event detected\n"); + fflush(stdout); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaEventDestroy(cudaEvent_t event) +{ + CUevent_st *e = get_event(event); + unsigned event_uid = e->get_uid(); + event_tracker_t::iterator pe = g_timer_events.find(event_uid); + if( pe == g_timer_events.end() ) + return g_last_cudaError = cudaErrorInvalidValue; + g_timer_events.erase(pe); + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaEventElapsedTime(float *ms, cudaEvent_t start, cudaEvent_t end) +{ + time_t elapsed_time; + CUevent_st *s = get_event(start); + CUevent_st *e = get_event(end); + if( s==NULL || e==NULL ) + return g_last_cudaError = cudaErrorUnknown; + elapsed_time = e->clock() - s->clock(); + *ms = 1000*elapsed_time; + return g_last_cudaError = cudaSuccess; +} + + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaThreadExit(void) +{ + exit_simulation(); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaThreadSynchronize(void) +{ + //Called on host side + synchronize(); + return g_last_cudaError = cudaSuccess; +}; + +int CUDARTAPI __cudaSynchronizeThreads(void**, void*) +{ + return cudaThreadExit(); +} + + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +#if (CUDART_VERSION >= 3010) + +typedef struct CUuuid_st { /**< CUDA definition of UUID */ + char bytes[16]; +} CUuuid; + +/** + * CUDA UUID types + */ +// typedef __device_builtin__ struct CUuuid_st cudaUUID_t; + +__host__ cudaError_t CUDARTAPI cudaGetExportTable(const void **ppExportTable, const cudaUUID_t *pExportTableId) +{ + printf("cudaGetExportTable: UUID = "); + for (int s = 0; s < 16; s++) { + printf("%#2x ", (unsigned char) (pExportTableId->bytes[s])); + } + printf("\n"); + return g_last_cudaError = cudaSuccess; +} + +#endif + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +//#include "../../cuobjdump_to_ptxplus/cuobjdump_parser.h" + +enum cuobjdumpSectionType { + PTXSECTION=0, + ELFSECTION +}; + + +class cuobjdumpSection { +public: + //Constructor + cuobjdumpSection() { + arch = 0; + identifier = ""; + } + virtual ~cuobjdumpSection() {} + unsigned getArch() {return arch;} + void setArch(unsigned a) {arch = a;} + std::string getIdentifier() {return identifier;} + void setIdentifier(std::string i) {identifier = i;} + virtual void print(){std::cout << "cuobjdump Section: unknown type" << std::endl;} +private: + unsigned arch; + std::string identifier; +}; + +class cuobjdumpELFSection : public cuobjdumpSection +{ +public: + cuobjdumpELFSection() {} + virtual ~cuobjdumpELFSection() { + elffilename = ""; + sassfilename = ""; + } + std::string getELFfilename() {return elffilename;} + void setELFfilename(std::string f) {elffilename = f;} + std::string getSASSfilename() {return sassfilename;} + void setSASSfilename(std::string f) {sassfilename = f;} + virtual void print() { + std::cout << "ELF Section:" << std::endl; + std::cout << "arch: sm_" << getArch() << std::endl; + std::cout << "identifier: " << getIdentifier() << std::endl; + std::cout << "elf filename: " << getELFfilename() << std::endl; + std::cout << "sass filename: " << getSASSfilename() << std::endl; + std::cout << std::endl; + } +private: + std::string elffilename; + std::string sassfilename; +}; + +class cuobjdumpPTXSection : public cuobjdumpSection +{ +public: + cuobjdumpPTXSection(){ + ptxfilename = ""; + } + std::string getPTXfilename() {return ptxfilename;} + void setPTXfilename(std::string f) {ptxfilename = f;} + virtual void print() { + std::cout << "PTX Section:" << std::endl; + std::cout << "arch: sm_" << getArch() << std::endl; + std::cout << "identifier: " << getIdentifier() << std::endl; + std::cout << "ptx filename: " << getPTXfilename() << std::endl; + std::cout << std::endl; + } +private: + std::string ptxfilename; +}; + +std::list cuobjdumpSectionList; +std::list libSectionList; + +// sectiontype: 0 for ptx, 1 for elf +void addCuobjdumpSection(int sectiontype){ + if (sectiontype) + cuobjdumpSectionList.push_front(new cuobjdumpELFSection()); + else + cuobjdumpSectionList.push_front(new cuobjdumpPTXSection()); + printf("## Adding new section %s\n", sectiontype?"ELF":"PTX"); +} + +void setCuobjdumparch(const char* arch){ + unsigned archnum; + sscanf(arch, "sm_%u", &archnum); + assert (archnum && "cannot have sm_0"); + printf("Adding arch: %s\n", arch); + cuobjdumpSectionList.front()->setArch(archnum); +} + +void setCuobjdumpidentifier(const char* identifier){ + printf("Adding identifier: %s\n", identifier); + cuobjdumpSectionList.front()->setIdentifier(identifier); +} + +void setCuobjdumpptxfilename(const char* filename){ + printf("Adding ptx filename: %s\n", filename); + cuobjdumpSection* x = cuobjdumpSectionList.front(); + if (dynamic_cast(x) == NULL){ + assert (0 && "You shouldn't be trying to add a ptxfilename to an elf section"); + } + (dynamic_cast(x))->setPTXfilename(filename); +} + +void setCuobjdumpelffilename(const char* filename){ + if (dynamic_cast(cuobjdumpSectionList.front()) == NULL){ + assert (0 && "You shouldn't be trying to add a elffilename to an ptx section"); + } + (dynamic_cast(cuobjdumpSectionList.front()))->setELFfilename(filename); +} + +void setCuobjdumpsassfilename(const char* filename){ + if (dynamic_cast(cuobjdumpSectionList.front()) == NULL){ + assert (0 && "You shouldn't be trying to add a sassfilename to an ptx section"); + } + (dynamic_cast(cuobjdumpSectionList.front()))->setSASSfilename(filename); +} +extern int cuobjdump_parse(); +extern FILE *cuobjdump_in; + +//! Return the executable file of the process containing the PTX/SASS code +//! +//! This Function returns the executable file ran by the process. This +//! executable is supposed to contain the PTX/SASS code. It provides workaround +//! for processes running on valgrind by dereferencing /proc//exe within the +//! GPGPU-Sim process before calling cuobjdump to extract PTX/SASS. This is +//! needed because valgrind uses x86 emulation to detect memory leak. Other +//! processes (e.g. cuobjdump) reading /proc//exe will see the emulator +//! executable instead of the application binary. +//! +std::string get_app_binary(){ + char self_exe_path[1025]; +#ifdef __APPLE__ + uint32_t size = sizeof(self_exe_path); + if( _NSGetExecutablePath(self_exe_path,&size) != 0 ) { + printf("GPGPU-Sim ** ERROR: _NSGetExecutablePath input buffer too small\n"); + exit(1); + } +#else + std::stringstream exec_link; + exec_link << "/proc/self/exe"; + + ssize_t path_length = readlink(exec_link.str().c_str(), self_exe_path, 1024); + assert(path_length != -1); + self_exe_path[path_length] = '\0'; +#endif + + printf("self exe links to: %s\n", self_exe_path); + return self_exe_path; +} + +//above func gives abs path whereas this give just the name of application. +char* get_app_binary_name(std::string abs_path){ + char *self_exe_path; +#ifdef __APPLE__ + //TODO: get apple device and check the result. + printf("WARNING: not tested for Apple-mac devices \n"); + abort(); +#else + char* buf = strdup(abs_path.c_str()); + char *token = strtok(buf, "/"); + while(token !=NULL){ + self_exe_path = token; + token = strtok(NULL,"/"); + } +#endif + self_exe_path = strtok(self_exe_path, "."); + printf("self exe links to: %s\n", self_exe_path); + return self_exe_path; +} + +//! Call cuobjdump to extract everything (-elf -sass -ptx) +/*! + * This Function extract the whole PTX (for all the files) using cuobjdump + * to _cuobjdump_complete_output_XXXXXX then runs a parser to chop it up with each binary in + * its own file + * It is also responsible for extracting the libraries linked to the binary if the option is + * enabled + * */ +void extract_code_using_cuobjdump(){ + CUctx_st *context = GPGPUSim_Context(); + unsigned forced_max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); + + //prevent the dumping by cuobjdump everytime we execute the code! + const char *override_cuobjdump = getenv("CUOBJDUMP_SIM_FILE"); + char command[1000], ptx_file[1000]; + std::string app_binary = get_app_binary(); + //Running cuobjdump using dynamic link to current process + snprintf(command,1000,"md5sum %s ", app_binary.c_str()); + printf("Running md5sum using \"%s\"\n", command); + system(command); + // Running cuobjdump using dynamic link to current process + // Needs the option '-all' to extract PTX from CDP-enabled binary + extern bool g_cdp_enabled; + + //dump ptx for all individial ptx files into sepearte files which is later used by ptxas. + int result=0; +#if (CUDART_VERSION >= 6000) + char fname2[1024]; + snprintf(fname2,1024,"_cuobjdump_list_ptx_XXXXXX"); + int fd2=mkstemp(fname2); + close(fd2); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -lptx -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname2); + result = system(command); + if( result != 0 ) { + printf("WARNING: Failed to execute cuobjdump to get list of ptx files \n"); + exit(0); + } else { + /* + as we got list of ptx files, we need to extract one by one into seperate files so that ptxas can understand it. + In this way, the duplicate definitions in a single embedded file can be prevented. + No of lines in the file is equal to no of ptx fileis available. + */ + FILE *fp = fopen(fname2,"r"); + if (fp==NULL) { + printf("WARNING: cuobjdump file error! Could not open file %s \n", fname2); + exit(0); + } else { + for (char c = getc(fp); c != EOF; c = getc(fp)) + if (c == '\n') + no_of_ptx = no_of_ptx + 1; + fclose(fp); + } + if(no_of_ptx==0){ + printf("WARNING: Number of ptx in the executable file are 0. One of the reasons might be\n"); + printf("\t1. CDP is enabled\n"); + printf("\t2. cuobjdump -lptx doesnt recognize sm_%u\n",forced_max_capability); + printf("\t3. the application was not compiled iwth nvcc flag sm_%u\n",forced_max_capability); + } + } + if(!g_cdp_enabled) { + //based on the list above, dump ptx files individually. Format of dumped ptx file is prog_name.unique_no.sm_<>.ptx + for (int index=1; index<= no_of_ptx; index++){ + snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", get_app_binary_name(app_binary), index, forced_max_capability); + printf("Extracting specific PTX file named %s \n",ptx_file); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -arch=sm_%u -xptx %s %s", forced_max_capability, ptx_file, app_binary.c_str()); + if (system(command)!=0) { + printf("ERROR: command: %s failed \n",command); + exit(0); + } + } + } +#endif + //TODO: redundant to dump twice. how can it be prevented? + //dump only for specific arch + char fname[1024]; + if ((override_cuobjdump == NULL) || (strlen(override_cuobjdump)==0)) { + snprintf(fname,1024,"_cuobjdump_complete_output_XXXXXX"); + int fd=mkstemp(fname); + close(fd); + if(!g_cdp_enabled) + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass %s > %s", app_binary.c_str(), fname); + else + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); + bool parse_output = true; + result = system(command); + if(result) { + if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support() && (result == 65280)) { + // Some CUDA application may exclusively use kernels provided by CUDA + // libraries (e.g. CUBLAS). Skipping cuobjdump extraction from the + // executable for this case. + // 65280 is the return code from cuobjdump denoting the specific error (tested on CUDA 4.0/4.1/4.2) + printf("WARNING: Failed to execute: %s\n", command); + printf(" Executable binary does not contain any GPU kernel.\n"); + parse_output = false; + } else { + printf("ERROR: Failed to execute: %s\n", command); + exit(1); + } + } + + if (parse_output) { + printf("Parsing file %s\n", fname); + cuobjdump_in = fopen(fname, "r"); + + cuobjdump_parse(); + fclose(cuobjdump_in); + printf("Done parsing!!!\n"); + } else { + printf("Parsing skipped for %s\n", fname); + } + + if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ + //Experimental library support + //Currently only for cufft + + std::stringstream cmd; + cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; + int result = system(cmd.str().c_str()); + if(result){ + std::cout << "Failed to execute: " << cmd.str() << std::endl; + exit(1); + } + std::ifstream libsf; + libsf.open("_tempfile_.txt"); + if(!libsf.is_open()) { + std::cout << "Failed to open: _tempfile_.txt" << std::endl; + exit(1); + } + + //Save the original section list + std::list tmpsl = cuobjdumpSectionList; + cuobjdumpSectionList.clear(); + + std::string line; + std::getline(libsf, line); + std::cout << "DOING: " << line << std::endl; + int cnt=1; + while(libsf.good()){ + std::stringstream libcodfn; + libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; + cmd.str(""); //resetting + cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; + cmd << line; + cmd << " > "; + cmd << libcodfn.str(); + std::cout << "Running cuobjdump on " << line << std::endl; + std::cout << "Using command: " << cmd.str() << std::endl; + result = system(cmd.str().c_str()); + if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} + std::cout << "Done" << std::endl; + + std::cout << "Trying to parse " << libcodfn.str() << std::endl; + cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); + cuobjdump_parse(); + fclose(cuobjdump_in); + std::getline(libsf, line); + } + libSectionList = cuobjdumpSectionList; + + //Restore the original section list + cuobjdumpSectionList = tmpsl; + } + } else { + printf("GPGPU-Sim PTX: overriding cuobjdump with '%s' (CUOBJDUMP_SIM_FILE is set)\n", override_cuobjdump); + snprintf(fname,1024, "%s",override_cuobjdump); + } +} + +//! Read file into char* +//TODO: convert this to C++ streams, will be way cleaner +char* readfile (const std::string filename){ + assert (filename != ""); + FILE* fp = fopen(filename.c_str(),"r"); + if (!fp) { + std::cout << "ERROR: Could not open file %s for reading\n" << filename << std::endl; + assert (0); + } + // finding size of the file + int filesize= 0; + fseek (fp , 0 , SEEK_END); + + filesize = ftell (fp); + fseek (fp, 0, SEEK_SET); + // allocate and copy the entire ptx + char* ret = (char*)malloc((filesize +1)* sizeof(char)); + fread(ret,1,filesize,fp); + ret[filesize]='\0'; + fclose(fp); + return ret; +} + +//! Function that helps debugging +void printSectionList(std::list sl) { + std::list::iterator iter; + for ( iter = sl.begin(); + iter != sl.end(); + iter++ + ){ + (*iter)->print(); + } +} + +//! Remove unecessary sm versions from the section list +std::list pruneSectionList(std::list cuobjdumpSectionList, CUctx_st *context) { + unsigned forced_max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); + + //For ptxplus, force the max capability to 19 if it's higher or unspecified(0) + if (context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus()){ + if ( (forced_max_capability == 0) || + (forced_max_capability >= 20)){ + printf("GPGPU-Sim: WARNING: Capability >= 20 are not supported in PTXPlus\n\tSetting forced_max_capability to 19\n"); + forced_max_capability = 19; + } + } + + std::list prunedList; + + //Find the highest capability (that is lower than the forced maximum) for each cubin file + //and set it in cuobjdumpSectionMap. Do this only for ptx sections + std::map cuobjdumpSectionMap; + int min_ptx_capability_found=0; + for ( std::list::iterator iter = cuobjdumpSectionList.begin(); + iter != cuobjdumpSectionList.end(); + iter++){ + unsigned capability = (*iter)->getArch(); + if(dynamic_cast(*iter) != NULL){ + if(capabilitygetIdentifier())==cuobjdumpSectionMap.end()) + || (cuobjdumpSectionMap[(*iter)->getIdentifier()] < capability)) + cuobjdumpSectionMap[(*iter)->getIdentifier()] = capability; + } + } + } + + //Throw away the sections with the lower capabilites and push those with the highest in + //the pruned list + for ( std::list::iterator iter = cuobjdumpSectionList.begin(); + iter != cuobjdumpSectionList.end(); + iter++){ + unsigned capability = (*iter)->getArch(); + if(capability == cuobjdumpSectionMap[(*iter)->getIdentifier()]){ + prunedList.push_back(*iter); + } else { + delete *iter; + } + } + if(prunedList.empty()){ + printf("Error: No PTX sections found with sm capability that is lower than current forced maximum capability \n minimum ptx capability found = %u, maximum forced ptx capability = %u \n User might want to change either the forced maximum capability from gpgpusim configuration or update the compilation to generate the required PTX version\n",min_ptx_capability_found,forced_max_capability); + abort(); + } + return prunedList; +} + +//! Merge all PTX sections that have a specific identifier into one file +std::list mergeMatchingSections(std::list cuobjdumpSectionList, std::string identifier){ + const char *ptxcode = ""; + std::list::iterator old_iter; + cuobjdumpPTXSection* old_ptxsection = NULL; + cuobjdumpPTXSection* ptxsection; + std::list mergedList; + + for ( std::list::iterator iter = cuobjdumpSectionList.begin(); + iter != cuobjdumpSectionList.end(); + iter++){ + if((ptxsection=dynamic_cast(*iter)) != NULL && + strcmp(ptxsection->getIdentifier().c_str(), identifier.c_str()) == 0){ + // Read and remove the last PTX section + if (old_ptxsection != NULL) { + ptxcode = readfile(old_ptxsection->getPTXfilename()); + // remove ptx file? + delete *old_iter; + } + + // Append all the PTX from the last PTX section into the current PTX section + // Add 50 to ptxcode to ignore the information regarding version/target/address_size + if (strlen(ptxcode) >= 50) { + FILE *ptxfile = fopen((ptxsection->getPTXfilename()).c_str(), "a"); + fprintf(ptxfile, "%s", ptxcode + 50); + fclose(ptxfile); + } + + old_iter = iter; + old_ptxsection = ptxsection; + } + // Store all non-PTX sections and PTX sections with non-matching identifiers + else { + mergedList.push_back(*iter); + } + } + + // Store the final PTX section + mergedList.push_back(*old_iter); + + return mergedList; +} + +//! Merge any PTX sections with matching identifiers +std::list mergeSections(std::list cuobjdumpSectionList){ + std::vector identifier; + cuobjdumpPTXSection* ptxsection; + + // Add all identifiers present in PTX sections to a vector + for ( std::list::iterator iter = cuobjdumpSectionList.begin(); + iter != cuobjdumpSectionList.end(); + iter++){ + if((ptxsection=dynamic_cast(*iter)) != NULL){ + std::string current_id = ptxsection->getIdentifier(); + + // If we haven't yet seen a given identifier, add it to the vector + if (std::find(identifier.begin(), identifier.end(), current_id) == identifier.end()) { + identifier.push_back(current_id); + } + } + } + + // Call mergeMatchingSections on all identifiers in the vector + for ( std::vector::iterator iter = identifier.begin(); + iter != identifier.end(); + iter++) { + cuobjdumpSectionList = mergeMatchingSections(cuobjdumpSectionList, *iter); + } + + return cuobjdumpSectionList; +} + + +//! Within the section list, find the ELF section corresponding to a given identifier +cuobjdumpELFSection* findELFSectionInList(std::list sectionlist, const std::string identifier){ + + std::list::iterator iter; + for ( iter = sectionlist.begin(); + iter != sectionlist.end(); + iter++ + ){ + cuobjdumpELFSection* elfsection; + if((elfsection=dynamic_cast(*iter)) != NULL){ + if(elfsection->getIdentifier() == identifier) + return elfsection; + } + } + return NULL; +} + +//! Find an ELF section in all the known lists +cuobjdumpELFSection* findELFSection(const std::string identifier){ + cuobjdumpELFSection* sec = findELFSectionInList(cuobjdumpSectionList, identifier); + if (sec!=NULL)return sec; + sec = findELFSectionInList(libSectionList, identifier); + if (sec!=NULL)return sec; + std::cout << "Could not find " << identifier << std::endl; + assert(0 && "Could not find the required ELF section"); + return NULL; +} + +//! Within the section list, find the PTX section corresponding to a given identifier +cuobjdumpPTXSection* findPTXSectionInList(std::list sectionlist, const std::string identifier){ + std::list::iterator iter; + for ( iter = sectionlist.begin(); + iter != sectionlist.end(); + iter++ + ){ + cuobjdumpPTXSection* ptxsection; + if((ptxsection=dynamic_cast(*iter)) != NULL){ + if(ptxsection->getIdentifier() == identifier) + return ptxsection; + else { + extern bool g_cdp_enabled; + if(g_cdp_enabled) { + printf("Warning: __cudaRegisterFatBinary needs %s, but find PTX section with %s\n", + identifier.c_str(), ptxsection->getIdentifier().c_str()); + return ptxsection; + } + } + } + } + return NULL; +} + +//! Find an PTX section in all the known lists +cuobjdumpPTXSection* findPTXSection(const std::string identifier){ + cuobjdumpPTXSection* sec = findPTXSectionInList(cuobjdumpSectionList, identifier); + if (sec!=NULL)return sec; + sec = findPTXSectionInList(libSectionList, identifier); + if (sec!=NULL)return sec; + std::cout << "Could not find " << identifier << std::endl; + assert(0 && "Could not find the required PTX section"); + return NULL; +} + + + +//! Extract the code using cuobjdump and remove unnecessary sections +void cuobjdumpInit(){ + CUctx_st *context = GPGPUSim_Context(); + extract_code_using_cuobjdump(); //extract all the output of cuobjdump to _cuobjdump_*.* + const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); + if (pre_load ==NULL || strlen(pre_load)==0){ + cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); + cuobjdumpSectionList = mergeSections(cuobjdumpSectionList); + } +} + +std::map fatbinmap; +std::mapfatbin_registered; +std::map name_symtab; + +//! Keep track of the association between filename and cubin handle +void cuobjdumpRegisterFatBinary(unsigned int handle, const char* filename){ + fatbinmap[handle] = filename; +} + +//! Either submit PTX for simulation or convert SASS to PTXPlus and submit it +void cuobjdumpParseBinary(unsigned int handle){ + + if(fatbin_registered[handle]) return; + fatbin_registered[handle] = true; + CUctx_st *context = GPGPUSim_Context(); + std::string fname = fatbinmap[handle]; + + if (name_symtab.find(fname) != name_symtab.end()) { + symbol_table *symtab = name_symtab[fname]; + context->add_binary(symtab, handle); + return; + } + + unsigned max_capability = 0; + for ( std::list::iterator iter = cuobjdumpSectionList.begin(); + iter != cuobjdumpSectionList.end(); + iter++){ + unsigned capability = (*iter)->getArch(); + if (capability > max_capability) max_capability = capability; + } + if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); + + cuobjdumpPTXSection* ptx = NULL; + const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); + if(pre_load==NULL || strlen(pre_load)==0) + ptx = findPTXSection(fname); + symbol_table *symtab; + char *ptxcode; + const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); + if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL or strlen(getenv("PTX_SIM_USE_PTX_FILE"))==0) { + ptxcode = readfile(ptx->getPTXfilename()); + } else { + printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); + ptxcode = readfile(override_ptx_name); + } + if(context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() ) { + cuobjdumpELFSection* elfsection = findELFSection(ptx->getIdentifier()); + assert (elfsection!= NULL); + char *ptxplus_str = gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus( + ptx->getPTXfilename(), + elfsection->getELFfilename(), + elfsection->getSASSfilename()); + symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxplus_str, handle); + printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); + context->add_binary(symtab, handle); + gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability ); + delete[] ptxplus_str; + } else { + symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxcode, handle); + //if CUOBJDUMP_SIM_FILE is not set, ptx is NULL. So comment below. + //printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); + context->add_binary(symtab, handle); + gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability ); + } + load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu()); + load_constants(symtab,STATIC_ALLOC_LIMIT,context->get_device()->get_gpgpu()); + name_symtab[fname] = symtab; + + //TODO: Remove temporarily files as per configurations +} + +void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) +{ +#if (CUDART_VERSION < 2010) + printf("GPGPU-Sim PTX: ERROR ** this version of GPGPU-Sim requires CUDA 2.1 or higher\n"); + exit(1); +#endif + CUctx_st *context = GPGPUSim_Context(); + static unsigned next_fat_bin_handle = 1; + if(context->get_device()->get_gpgpu()->get_config().use_cuobjdump()) { + // The following workaround has only been verified on 64-bit systems. + if (sizeof(void*) == 4) + printf("GPGPU-Sim PTX: FatBin file name extraction has not been tested on 32-bit system.\n"); + + #if (CUDART_VERSION <= 6000) + // FatBin handle from the .fatbin.c file (one of the intermediate files generated by NVCC) + typedef struct {int m; int v; const unsigned long long* d; char* f;} __fatDeviceText __attribute__ ((aligned (8))); + __fatDeviceText * fatDeviceText = (__fatDeviceText *) fatCubin; + + // Extract the source code file name that generate the given FatBin. + // - Obtains the pointer to the actual fatbin structure from the FatBin handle (fatCubin). + // - An integer inside the fatbin structure contains the relative offset to the source code file name. + // - This offset differs among different CUDA and GCC versions. + char * pfatbin = (char*) fatDeviceText->d; + int offset = *((int*)(pfatbin+48)); + char * filename = (pfatbin+16+offset); + #else + const char * filename = "default"; + #endif + // The extracted file name is associated with a fat_cubin_handle passed + // into cudaLaunch(). Inside cudaLaunch(), the associated file name is + // used to find the PTX/SASS section from cuobjdump, which contains the + // PTX/SASS code for the launched kernel function. + // This allows us to work around the fact that cuobjdump only outputs the + // file name associated with each section. + unsigned long long fat_cubin_handle = next_fat_bin_handle; + next_fat_bin_handle++; + printf("GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = %llu, filename=%s\n", fat_cubin_handle, filename); + /*! + * This function extracts all data from all files in first call + * then for next calls, only returns the appropriate number + */ + assert(fat_cubin_handle >= 1); + if (fat_cubin_handle==1) cuobjdumpInit(); + cuobjdumpRegisterFatBinary(fat_cubin_handle, filename); + + return (void**)fat_cubin_handle; + } +#if (CUDART_VERSION < 8000) + else { + static unsigned source_num=1; + unsigned long long fat_cubin_handle = next_fat_bin_handle++; + __cudaFatCudaBinary *info = (__cudaFatCudaBinary *)fatCubin; + assert( info->version >= 3 ); + unsigned num_ptx_versions=0; + unsigned max_capability=0; + unsigned selected_capability=0; + bool found=false; + unsigned forced_max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); + if (!info->ptx){ + printf("ERROR: Cannot find ptx code in cubin file\n" + "\tIf you are using CUDA 4.0 or higher, please enable -gpgpu_ptx_use_cuobjdump or downgrade to CUDA 3.1\n"); + exit(1); + } + while( info->ptx[num_ptx_versions].gpuProfileName != NULL ) { + unsigned capability=0; + sscanf(info->ptx[num_ptx_versions].gpuProfileName,"compute_%u",&capability); + printf("GPGPU-Sim PTX: __cudaRegisterFatBinary found PTX versions for '%s', ", info->ident); + printf("capability = %s\n", info->ptx[num_ptx_versions].gpuProfileName ); + if( forced_max_capability ) { + if( capability > max_capability && capability <= forced_max_capability ) { + found = true; + max_capability=capability; + selected_capability = num_ptx_versions; + } + } else { + if( capability > max_capability ) { + found = true; + max_capability=capability; + selected_capability = num_ptx_versions; + } + } + num_ptx_versions++; + } + if( found ) { + printf("GPGPU-Sim PTX: Loading PTX for %s, capability = %s\n", + info->ident, info->ptx[selected_capability].gpuProfileName ); + symbol_table *symtab; + const char *ptx = info->ptx[selected_capability].ptx; + if(context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() ) { + printf("GPGPU-Sim PTX: ERROR ** PTXPlus is only supported through cuobjdump\n" + "\tEither enable cuobjdump or disable PTXPlus in your configuration file\n"); + exit(1); + } else { + symtab=gpgpu_ptx_sim_load_ptx_from_string(ptx,source_num); + context->add_binary(symtab,fat_cubin_handle); + gpgpu_ptxinfo_load_from_string( ptx, source_num, max_capability ); + } + source_num++; + load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu()); + load_constants(symtab,STATIC_ALLOC_LIMIT,context->get_device()->get_gpgpu()); + } else { + printf("GPGPU-Sim PTX: warning -- did not find an appropriate PTX in cubin\n"); + } + return (void**)fat_cubin_handle; + } +#else + else { + printf("ERROR ** __cudaRegisterFatBinary() needs to be updated\n"); + abort(); + } +#endif +} + +void __cudaUnregisterFatBinary(void **fatCubinHandle) +{ + ; +} + +cudaError_t cudaDeviceReset ( void ) { + // Should reset the simulated GPU + return g_last_cudaError = cudaSuccess; +} +cudaError_t CUDARTAPI cudaDeviceSynchronize(void){ + // I don't know what this should do + return g_last_cudaError = cudaSuccess; +} + + +void CUDARTAPI __cudaRegisterFunction( + void **fatCubinHandle, + const char *hostFun, + char *deviceFun, + const char *deviceName, + int thread_limit, + uint3 *tid, + uint3 *bid, + dim3 *bDim, + dim3 *gDim +) +{ + CUctx_st *context = GPGPUSim_Context(); + unsigned fat_cubin_handle = (unsigned)(unsigned long long)fatCubinHandle; + printf("GPGPU-Sim PTX: __cudaRegisterFunction %s : hostFun 0x%p, fat_cubin_handle = %u\n", + deviceFun, hostFun, fat_cubin_handle); + if(context->get_device()->get_gpgpu()->get_config().use_cuobjdump()) + cuobjdumpParseBinary(fat_cubin_handle); + context->register_function( fat_cubin_handle, hostFun, deviceFun ); +} + +extern void __cudaRegisterVar( + void **fatCubinHandle, + char *hostVar, //pointer to...something + char *deviceAddress, //name of variable + const char *deviceName, //name of variable (same as above) + int ext, + int size, + int constant, + int global ) +{ + printf("GPGPU-Sim PTX: __cudaRegisterVar: hostVar = %p; deviceAddress = %s; deviceName = %s\n", hostVar, deviceAddress, deviceName); + printf("GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of %d bytes\n", size); + if(GPGPUSim_Context()->get_device()->get_gpgpu()->get_config().use_cuobjdump()) + cuobjdumpParseBinary((unsigned)(unsigned long long)fatCubinHandle); + fflush(stdout); + if ( constant && !global && !ext ) { + gpgpu_ptx_sim_register_const_variable(hostVar,deviceName,size); + } else if ( !constant && !global && !ext ) { + gpgpu_ptx_sim_register_global_variable(hostVar,deviceName,size); + } else cuda_not_implemented(__my_func__,__LINE__); +} + + +void __cudaRegisterShared( + void **fatCubinHandle, + void **devicePtr +) +{ + // we don't do anything here + printf("GPGPU-Sim PTX: __cudaRegisterShared\n" ); +} + +void CUDARTAPI __cudaRegisterSharedVar( + void **fatCubinHandle, + void **devicePtr, + size_t size, + size_t alignment, + int storage +) +{ + // we don't do anything here + printf("GPGPU-Sim PTX: __cudaRegisterSharedVar\n" ); +} + +void __cudaRegisterTexture( + void **fatCubinHandle, + const struct textureReference *hostVar, + const void **deviceAddress, + const char *deviceName, + int dim, + int norm, + int ext +) //passes in a newly created textureReference +{ + std::string devStr (deviceName); + #if (CUDART_VERSION > 4020) + if (devStr.size() > 2 && devStr.data()[0] == ':' && devStr.data()[1] == ':') + devStr = devStr.replace(0, 2, ""); + #endif + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + printf("GPGPU-Sim PTX: in __cudaRegisterTexture:\n"); + gpu->gpgpu_ptx_sim_bindNameToTexture(devStr.data(), hostVar, dim, norm, ext); + printf("GPGPU-Sim PTX: int dim = %d\n", dim); + printf("GPGPU-Sim PTX: int norm = %d\n", norm); + printf("GPGPU-Sim PTX: int ext = %d\n", ext); + printf("GPGPU-Sim PTX: Execution warning: Not finished implementing \"%s\"\n", __my_func__ ); +} + +#ifndef OPENGL_SUPPORT +typedef unsigned long GLuint; +#endif + +cudaError_t cudaGLRegisterBufferObject(GLuint bufferObj) +{ + printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); + return g_last_cudaError = cudaSuccess; +} + +struct glbmap_entry { + GLuint m_bufferObj; + void *m_devPtr; + size_t m_size; + struct glbmap_entry *m_next; +}; +typedef struct glbmap_entry glbmap_entry_t; + +glbmap_entry_t* g_glbmap = NULL; + +cudaError_t cudaGLMapBufferObject(void** devPtr, GLuint bufferObj) +{ +#ifdef OPENGL_SUPPORT + GLint buffer_size=0; + CUctx_st* ctx = GPGPUSim_Context(); + + glbmap_entry_t *p = g_glbmap; + while ( p && p->m_bufferObj != bufferObj ) + p = p->m_next; + if ( p == NULL ) { + glBindBuffer(GL_ARRAY_BUFFER,bufferObj); + glGetBufferParameteriv(GL_ARRAY_BUFFER,GL_BUFFER_SIZE,&buffer_size); + assert( buffer_size != 0 ); + *devPtr = ctx->get_device()->get_gpgpu()->gpu_malloc(buffer_size); + + // create entry and insert to front of list + glbmap_entry_t *n = (glbmap_entry_t *) calloc(1,sizeof(glbmap_entry_t)); + n->m_next = g_glbmap; + g_glbmap = n; + + // initialize entry + n->m_bufferObj = bufferObj; + n->m_devPtr = *devPtr; + n->m_size = buffer_size; + + p = n; + } else { + buffer_size = p->m_size; + *devPtr = p->m_devPtr; + } + + if ( *devPtr ) { + char *data = (char *) calloc(p->m_size,1); + glGetBufferSubData(GL_ARRAY_BUFFER,0,buffer_size,data); + memcpy_to_gpu( (size_t) *devPtr, data, buffer_size ); + free(data); + printf("GPGPU-Sim PTX: cudaGLMapBufferObject %zu bytes starting at 0x%llx..\n", (size_t)buffer_size, + (unsigned long long) *devPtr); + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorMemoryAllocation; + } + + return g_last_cudaError = cudaSuccess; +#else + fflush(stdout); + fflush(stderr); + printf("GPGPU-Sim PTX: GPGPU-Sim support for OpenGL integration disabled -- exiting\n"); + fflush(stdout); + exit(50); +#endif +} + +cudaError_t cudaGLUnmapBufferObject(GLuint bufferObj) +{ +#ifdef OPENGL_SUPPORT + glbmap_entry_t *p = g_glbmap; + while ( p && p->m_bufferObj != bufferObj ) + p = p->m_next; + if ( p == NULL ) + return g_last_cudaError = cudaErrorUnknown; + + char *data = (char *) calloc(p->m_size,1); + memcpy_from_gpu( data,(size_t)p->m_devPtr,p->m_size ); + glBufferSubData(GL_ARRAY_BUFFER,0,p->m_size,data); + free(data); + + return g_last_cudaError = cudaSuccess; +#else + fflush(stdout); + fflush(stderr); + printf("GPGPU-Sim PTX: support for OpenGL integration disabled -- exiting\n"); + fflush(stdout); + exit(50); +#endif +} + +cudaError_t cudaGLUnregisterBufferObject(GLuint bufferObj) +{ + printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); + return g_last_cudaError = cudaSuccess; +} + +#if (CUDART_VERSION >= 2010) + +cudaError_t CUDARTAPI cudaHostAlloc(void **pHost, size_t bytes, unsigned int flags) +{ + *pHost = malloc(bytes); + //need to track the size allocated so that cudaHostGetDevicePointer() can function properly. + //TODO: vary this function behavior based on flags value (following nvidia documentation) + pinned_memory_size[*pHost]=bytes; + if( *pHost ) + return g_last_cudaError = cudaSuccess; + else + return g_last_cudaError = cudaErrorMemoryAllocation; +} + +cudaError_t CUDARTAPI cudaHostGetDevicePointer(void **pDevice, void *pHost, unsigned int flags) +{ + //only cpu memory allocation happens in cudaHostAlloc. Linking with device pointer to pinned memory happens here. + //TODO: once kernel is executed, the contents in global pointer of GPU must be copied back to CPU host pointer! + flags=0; + CUctx_st* context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + std::map::const_iterator i = pinned_memory_size.find(pHost); + assert(i != pinned_memory_size.end()); + size_t size = i->second; + *pDevice = gpu->gpu_malloc(size); + if(g_debug_execution >= 3) + printf("GPGPU-Sim PTX: cudaMallocing %zu bytes starting at 0x%llx..\n",size, (unsigned long long) *pDevice); + if ( *pDevice ) { + pinned_memory[pHost]=pDevice; + //Copy contents in cpu to gpu + gpu->memcpy_to_gpu((size_t)*pDevice,pHost,size); + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorMemoryAllocation; + } +} + +cudaError_t CUDARTAPI cudaSetValidDevices(int *device_arr, int len) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + +cudaError_t CUDARTAPI cudaSetDeviceFlags( int flags ) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + +cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, const char *hostFun ) +{ + CUctx_st *context = GPGPUSim_Context(); + function_info *entry = context->get_kernel(hostFun); + if( entry ) { + const struct gpgpu_ptx_sim_info *kinfo = entry->get_kernel_info(); + attr->sharedSizeBytes = kinfo->smem; + attr->constSizeBytes = kinfo->cmem; + attr->localSizeBytes = kinfo->lmem; + attr->numRegs = kinfo->regs; + attr->maxThreadsPerBlock = 0; // from pragmas? +#if CUDART_VERSION >= 3000 + attr->ptxVersion = kinfo->ptx_version; + attr->binaryVersion = kinfo->sm_target; +#endif + } + return g_last_cudaError = cudaSuccess; +} + +cudaError_t CUDARTAPI cudaEventCreateWithFlags(cudaEvent_t *event, int flags) +{ + CUevent_st *e = new CUevent_st(flags==cudaEventBlockingSync); + g_timer_events[e->get_uid()] = e; +#if CUDART_VERSION >= 3000 + *event = e; +#else + *event = e->get_uid(); +#endif + return g_last_cudaError = cudaSuccess; +} + +cudaError_t CUDARTAPI cudaDriverGetVersion(int *driverVersion) +{ + *driverVersion = CUDART_VERSION; + return g_last_cudaError = cudaErrorUnknown; +} + +cudaError_t CUDARTAPI cudaRuntimeGetVersion(int *runtimeVersion) +{ + *runtimeVersion = CUDART_VERSION; + return g_last_cudaError = cudaErrorUnknown; +} + +#if CUDART_VERSION >= 3000 +__host__ cudaError_t CUDARTAPI cudaFuncSetCacheConfig(const char *func, enum cudaFuncCache cacheConfig ) +{ + CUctx_st *context = GPGPUSim_Context(); + context->get_device()->get_gpgpu()->set_cache_config(context->get_kernel(func)->get_name(), (FuncCache)cacheConfig); + return g_last_cudaError = cudaSuccess; +} + +//Jin: hack for cdp +__host__ cudaError_t CUDARTAPI cudaDeviceSetLimit(enum cudaLimit limit, size_t value) { + return g_last_cudaError = cudaSuccess; +} +#endif + +#endif + +cudaError_t CUDARTAPI cudaGLSetGLDevice(int device) +{ + printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); + return g_last_cudaError = cudaErrorUnknown; +} + +typedef void* HGPUNV; + +cudaError_t CUDARTAPI cudaWGLGetDevice(int *device, HGPUNV hGpu) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + +void CUDARTAPI __cudaMutexOperation(int lock) +{ + cuda_not_implemented(__my_func__,__LINE__); +} + +void CUDARTAPI __cudaTextureFetch(const void *tex, void *index, int integer, void *val) +{ + cuda_not_implemented(__my_func__,__LINE__); +} + +} + +namespace cuda_math { + +void CUDARTAPI __cudaMutexOperation(int lock) +{ + cuda_not_implemented(__my_func__,__LINE__); +} + +void CUDARTAPI __cudaTextureFetch(const void *tex, void *index, int integer, void *val) +{ + cuda_not_implemented(__my_func__,__LINE__); +} + +int CUDARTAPI __cudaSynchronizeThreads(void**, void*) +{ + //TODO This function should syncronize if we support Asyn kernel calls + return g_last_cudaError = cudaSuccess; +} + +} + +//////// + +extern int ptx_parse(); +extern int ptx__scan_string(const char*); +extern FILE *ptx_in; + +extern int ptxinfo_parse(); +extern int ptxinfo_debug; +extern FILE *ptxinfo_in; + +/// static functions + +static int load_static_globals( symbol_table *symtab, unsigned min_gaddr, unsigned max_gaddr, gpgpu_t *gpu ) +{ + printf( "GPGPU-Sim PTX: loading globals with explicit initializers... \n" ); + fflush(stdout); + int ng_bytes=0; + symbol_table::iterator g=symtab->global_iterator_begin(); + + for ( ; g!=symtab->global_iterator_end(); g++) { + symbol *global = *g; + if ( global->has_initializer() ) { + printf( "GPGPU-Sim PTX: initializing '%s' ... ", global->name().c_str() ); + unsigned addr=global->get_address(); + const type_info *type = global->type(); + type_info_key ti=type->get_key(); + size_t size; + int t; + ti.type_decode(size,t); + int nbytes = size/8; + int offset=0; + std::list init_list = global->get_initializer(); + for ( std::list::iterator i=init_list.begin(); i!=init_list.end(); i++ ) { + operand_info op = *i; + ptx_reg_t value = op.get_literal_value(); + assert( (addr+offset+nbytes) < min_gaddr ); // min_gaddr is start of "heap" for cudaMalloc + gpu->get_global_memory()->write(addr+offset,nbytes,&value,NULL,NULL); // assuming little endian here + offset+=nbytes; + ng_bytes+=nbytes; + } + printf(" wrote %u bytes\n", offset ); + } + } + printf( "GPGPU-Sim PTX: finished loading globals (%u bytes total).\n", ng_bytes ); + fflush(stdout); + return ng_bytes; +} + +static int load_constants( symbol_table *symtab, addr_t min_gaddr, gpgpu_t *gpu ) +{ + printf( "GPGPU-Sim PTX: loading constants with explicit initializers... " ); + fflush(stdout); + int nc_bytes = 0; + symbol_table::iterator g=symtab->const_iterator_begin(); + + for ( ; g!=symtab->const_iterator_end(); g++) { + symbol *constant = *g; + if ( constant->is_const() && constant->has_initializer() ) { + + // get the constant element data size + int basic_type; + size_t num_bits; + constant->type()->get_key().type_decode(num_bits,basic_type); + + std::list init_list = constant->get_initializer(); + int nbytes_written = 0; + for ( std::list::iterator i=init_list.begin(); i!=init_list.end(); i++ ) { + operand_info op = *i; + ptx_reg_t value = op.get_literal_value(); + int nbytes = num_bits/8; + switch ( op.get_type() ) { + case int_t: assert(nbytes >= 1); break; + case float_op_t: assert(nbytes == 4); break; + case double_op_t: assert(nbytes >= 4); break; // account for double DEMOTING + default: + abort(); + } + unsigned addr=constant->get_address() + nbytes_written; + assert( addr+nbytes < min_gaddr ); + + gpu->get_global_memory()->write(addr,nbytes,&value,NULL,NULL); // assume little endian (so u8 is the first byte in u32) + nc_bytes+=nbytes; + nbytes_written += nbytes; + } + } + } + printf( " done.\n"); + fflush(stdout); + return nc_bytes; +} + +kernel_info_t *gpgpu_cuda_ptx_sim_init_grid( const char *hostFun, + gpgpu_ptx_sim_arg_list_t args, + struct dim3 gridDim, + struct dim3 blockDim, + CUctx_st* context ) +{ + function_info *entry = context->get_kernel(hostFun); + kernel_info_t *result = new kernel_info_t(gridDim,blockDim,entry); + if( entry == NULL ) { + printf("GPGPU-Sim PTX: ERROR launching kernel -- no PTX implementation found for %p\n", hostFun); + abort(); + } + unsigned argcount=args.size(); + unsigned argn=1; + for( gpgpu_ptx_sim_arg_list_t::iterator a = args.begin(); a != args.end(); a++ ) { + entry->add_param_data(argcount-argn,&(*a)); + argn++; + } + + entry->finalize(result->get_param_memory()); + g_ptx_kernel_count++; + fflush(stdout); + + return result; +} diff --git a/src/cuda-sim/cuda-sim.cc~ b/src/cuda-sim/cuda-sim.cc~ new file mode 100644 index 0000000..cfd901f --- /dev/null +++ b/src/cuda-sim/cuda-sim.cc~ @@ -0,0 +1,2155 @@ +// Copyright (c) 2009-2011, Tor M. Aamodt, Ali Bakhoda, Wilson W.L. Fung, +// George L. Yuan, Jimmy Kwa +// The University of British Columbia +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// Redistributions in binary form must reproduce the above copyright notice, this +// list of conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. +// Neither the name of The University of British Columbia nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#include "cuda-sim.h" + +#include "instructions.h" +#include "ptx_ir.h" +#include "ptx.tab.h" +#include "ptx_sim.h" +#include + +#include "opcodes.h" +#include "../statwrapper.h" +#include +#include +#include "../abstract_hardware_model.h" +#include "memory.h" +#include "ptx-stats.h" +#include "ptx_loader.h" +#include "ptx_parser.h" +#include "../gpgpu-sim/gpu-sim.h" +#include "ptx_sim.h" +#include "../gpgpusim_entrypoint.h" +#include "decuda_pred_table/decuda_pred_table.h" +#include "../stream_manager.h" +#include "cuda_device_runtime.h" + +int gpgpu_ptx_instruction_classification; +void ** g_inst_classification_stat = NULL; +void ** g_inst_op_classification_stat= NULL; +int g_ptx_kernel_count = -1; // used for classification stat collection purposes +int g_debug_execution = 0; +int g_debug_thread_uid = 0; +addr_t g_debug_pc = 0xBEEF1518; +// Output debug information to file options + +unsigned g_ptx_sim_num_insn = 0; +unsigned gpgpu_param_num_shaders = 0; + +char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp; +char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp; +char *cdp_latency_str; +unsigned cdp_latency[5]; + +void ptx_opcocde_latency_options (option_parser_t opp) { + option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, + "Opcode latencies for integers " + "Default 1,1,19,25,145", + "1,1,19,25,145"); + option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp, + "Opcode latencies for single precision floating points " + "Default 1,1,1,1,30", + "1,1,1,1,30"); + option_parser_register(opp, "-ptx_opcode_latency_dp", OPT_CSTR, &opcode_latency_dp, + "Opcode latencies for double precision floating points " + "Default 8,8,8,8,335", + "8,8,8,8,335"); + option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, + "Opcode initiation intervals for integers " + "Default 1,1,4,4,32", + "1,1,4,4,32"); + option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp, + "Opcode initiation intervals for single precision floating points " + "Default 1,1,1,1,5", + "1,1,1,1,5"); + option_parser_register(opp, "-ptx_opcode_initiation_dp", OPT_CSTR, &opcode_initiation_dp, + "Opcode initiation intervals for double precision floating points " + "Default 8,8,8,8,130", + "8,8,8,8,130"); + option_parser_register(opp, "-cdp_latency", OPT_CSTR, &cdp_latency_str, + "CDP API latency " + "Default 7200,8000,100,12000,1600", + "7200,8000,100,12000,1600"); +} + +static address_type get_converge_point(address_type pc); + +void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) +{ + std::string texname(name); + m_NameToTextureRef[texname] = texref; + const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); + m_TextureRefToAttribute[texref] = texAttr; +} + +const char* gpgpu_t::gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref) +{ + std::map::iterator itr = m_NameToTextureRef.begin(); + while (itr != m_NameToTextureRef.end()) { + if ((*itr).second == texref) { + const char *p = ((*itr).first).c_str(); + return p; + } + itr++; + } + return NULL; +} + +unsigned int intLOGB2( unsigned int v ) { + unsigned int shift; + unsigned int r; + + r = 0; + + shift = (( v & 0xFFFF0000) != 0 ) << 4; v >>= shift; r |= shift; + shift = (( v & 0xFF00 ) != 0 ) << 3; v >>= shift; r |= shift; + shift = (( v & 0xF0 ) != 0 ) << 2; v >>= shift; r |= shift; + shift = (( v & 0xC ) != 0 ) << 1; v >>= shift; r |= shift; + shift = (( v & 0x2 ) != 0 ) << 0; v >>= shift; r |= shift; + + return r; +} + +void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) +{ + m_TextureRefToCudaArray[texref] = array; + unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; + unsigned int texel_size = texel_size_bits/8; + unsigned int Tx, Ty; + int r; + + printf("GPGPU-Sim PTX: texel size = %d\n", texel_size); + printf("GPGPU-Sim PTX: texture cache linesize = %d\n", m_function_model_config.get_texcache_linesize()); + //first determine base Tx size for given linesize + switch (m_function_model_config.get_texcache_linesize()) { + case 16: Tx = 4; break; + case 32: Tx = 8; break; + case 64: Tx = 8; break; + case 128: Tx = 16; break; + case 256: Tx = 16; break; + default: + printf("GPGPU-Sim PTX: Line size of %d bytes currently not supported.\n", m_function_model_config.get_texcache_linesize()); + assert(0); + break; + } + r = texel_size >> 2; + //modify base Tx size to take into account size of each texel in bytes + while (r != 0) { + Tx = Tx >> 1; + r = r >> 2; + } + //by now, got the correct Tx size, calculate correct Ty size + Ty = m_function_model_config.get_texcache_linesize()/(Tx*texel_size); + + printf("GPGPU-Sim PTX: Tx = %d; Ty = %d, Tx_numbits = %d, Ty_numbits = %d\n", Tx, Ty, intLOGB2(Tx), intLOGB2(Ty)); + printf("GPGPU-Sim PTX: Texel size = %d bytes; texel_size_numbits = %d\n", texel_size, intLOGB2(texel_size)); + printf("GPGPU-Sim PTX: Binding texture to array starting at devPtr32 = 0x%x\n", array->devPtr32); + printf("GPGPU-Sim PTX: Texel size = %d bytes\n", texel_size); + struct textureInfo* texInfo = (struct textureInfo*) malloc(sizeof(struct textureInfo)); + texInfo->Tx = Tx; + texInfo->Ty = Ty; + texInfo->Tx_numbits = intLOGB2(Tx); + texInfo->Ty_numbits = intLOGB2(Ty); + texInfo->texel_size = texel_size; + texInfo->texel_size_numbits = intLOGB2(texel_size); + m_TextureRefToTexureInfo[texref] = texInfo; +} + +unsigned g_assemble_code_next_pc=0; +std::map g_pc_to_finfo; +std::vector function_info::s_g_pc_to_insn; + +#define MAX_INST_SIZE 8 /*bytes*/ + +void function_info::ptx_assemble() +{ + if( m_assembled ) { + return; + } + + // get the instructions into instruction memory... + unsigned num_inst = m_instructions.size(); + m_instr_mem_size = MAX_INST_SIZE*(num_inst+1); + m_instr_mem = new ptx_instruction*[ m_instr_mem_size ]; + + printf("GPGPU-Sim PTX: instruction assembly for function \'%s\'... ", m_name.c_str() ); + fflush(stdout); + std::list::iterator i; + + addr_t PC = g_assemble_code_next_pc; // globally unique address (across functions) + // start function on an aligned address + for( unsigned i=0; i < (PC%MAX_INST_SIZE); i++ ) + s_g_pc_to_insn.push_back((ptx_instruction*)NULL); + PC += PC%MAX_INST_SIZE; + m_start_PC = PC; + + addr_t n=0; // offset in m_instr_mem + //Why s_g_pc_to_insn.size() is needed to reserve additional memory for insts? reserve is cumulative. + //s_g_pc_to_insn.reserve(s_g_pc_to_insn.size() + MAX_INST_SIZE*m_instructions.size()); + s_g_pc_to_insn.reserve(MAX_INST_SIZE*m_instructions.size()); + for ( i=m_instructions.begin(); i != m_instructions.end(); i++ ) { + ptx_instruction *pI = *i; + if ( pI->is_label() ) { + const symbol *l = pI->get_label(); + labels[l->name()] = n; + } else { + g_pc_to_finfo[PC] = this; + m_instr_mem[n] = pI; + s_g_pc_to_insn.push_back(pI); + assert(pI == s_g_pc_to_insn[PC]); + pI->set_m_instr_mem_index(n); + pI->set_PC(PC); + assert( pI->inst_size() <= MAX_INST_SIZE ); + for( unsigned i=1; i < pI->inst_size(); i++ ) { + s_g_pc_to_insn.push_back((ptx_instruction*)NULL); + m_instr_mem[n+i]=NULL; + } + n += pI->inst_size(); + PC += pI->inst_size(); + } + } + g_assemble_code_next_pc=PC; + for ( unsigned ii=0; ii < n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions + ptx_instruction *pI = m_instr_mem[ii]; + if ( pI->get_opcode() == BRA_OP || pI->get_opcode() == BREAKADDR_OP || pI->get_opcode() == CALLP_OP) { + operand_info &target = pI->dst(); //get operand, e.g. target name + if ( labels.find(target.name()) == labels.end() ) { + printf("GPGPU-Sim PTX: Loader error (%s:%u): Branch label \"%s\" does not appear in assembly code.", + pI->source_file(),pI->source_line(), target.name().c_str() ); + abort(); + } + unsigned index = labels[ target.name() ]; //determine address from name + unsigned PC = m_instr_mem[index]->get_PC(); + m_symtab->set_label_address( target.get_symbol(), PC ); + target.set_type(label_t); + } + } + m_n = n; + printf(" done.\n"); + fflush(stdout); + + //disable pdom analysis here and do it at runtime + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", m_name.c_str() ); + create_basic_blocks(); + connect_basic_blocks(); + bool modified = false; + do { + find_dominators(); + find_idominators(); + modified = connect_break_targets(); + } while (modified == true); + + if ( g_debug_execution>=50 ) { + print_basic_blocks(); + print_basic_block_links(); + print_basic_block_dot(); + } + if ( g_debug_execution>=2 ) { + print_dominators(); + } + find_postdominators(); + find_ipostdominators(); + if ( g_debug_execution>=50 ) { + print_postdominators(); + print_ipostdominators(); + } + + printf("GPGPU-Sim PTX: pre-decoding instructions for \'%s\'...\n", m_name.c_str() ); + for ( unsigned ii=0; ii < n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions + ptx_instruction *pI = m_instr_mem[ii]; + pI->pre_decode(); + } + printf("GPGPU-Sim PTX: ... done pre-decoding instructions for \'%s\'.\n", m_name.c_str() ); + fflush(stdout); + + m_assembled = true; +} + +addr_t shared_to_generic( unsigned smid, addr_t addr ) +{ + assert( addr < SHARED_MEM_SIZE_MAX ); + return SHARED_GENERIC_START + smid*SHARED_MEM_SIZE_MAX + addr; +} + +addr_t global_to_generic( addr_t addr ) +{ + return addr; +} + +bool isspace_shared( unsigned smid, addr_t addr ) +{ + addr_t start = SHARED_GENERIC_START + smid*SHARED_MEM_SIZE_MAX; + addr_t end = SHARED_GENERIC_START + (smid+1)*SHARED_MEM_SIZE_MAX; + if( (addr >= end) || (addr < start) ) + return false; + return true; +} + +bool isspace_global( addr_t addr ) +{ + return (addr >= GLOBAL_HEAP_START) || (addr < STATIC_ALLOC_LIMIT); +} + +memory_space_t whichspace( addr_t addr ) +{ + if( (addr >= GLOBAL_HEAP_START) || (addr < STATIC_ALLOC_LIMIT) ) { + return global_space; + } else if( addr >= SHARED_GENERIC_START ) { + return shared_space; + } else { + return local_space; + } +} + +addr_t generic_to_shared( unsigned smid, addr_t addr ) +{ + assert(isspace_shared(smid,addr)); + return addr - (SHARED_GENERIC_START + smid*SHARED_MEM_SIZE_MAX); +} + +addr_t local_to_generic( unsigned smid, unsigned hwtid, addr_t addr ) +{ + assert(addr < LOCAL_MEM_SIZE_MAX); + return LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * hwtid) + addr; +} + +bool isspace_local( unsigned smid, unsigned hwtid, addr_t addr ) +{ + addr_t start = LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * hwtid); + addr_t end = LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * (hwtid+1)); + if( (addr >= end) || (addr < start) ) + return false; + return true; +} + +addr_t generic_to_local( unsigned smid, unsigned hwtid, addr_t addr ) +{ + assert(isspace_local(smid,hwtid,addr)); + return addr - (LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * hwtid)); +} + +addr_t generic_to_global( addr_t addr ) +{ + return addr; +} + + +void* gpgpu_t::gpu_malloc( size_t size ) +{ + unsigned long long result = m_dev_malloc; + if(g_debug_execution >= 3) { + printf("GPGPU-Sim PTX: allocating %zu bytes on GPU starting at address 0x%Lx\n", size, m_dev_malloc ); + fflush(stdout); + } + m_dev_malloc += size; + if (size%256) m_dev_malloc += (256 - size%256); //align to 256 byte boundaries + return(void*) result; +} + +void* gpgpu_t::gpu_mallocarray( size_t size ) +{ + unsigned long long result = m_dev_malloc; + if(g_debug_execution >= 3) { + printf("GPGPU-Sim PTX: allocating %zu bytes on GPU starting at address 0x%Lx\n", size, m_dev_malloc ); + fflush(stdout); + } + m_dev_malloc += size; + if (size%256) m_dev_malloc += (256 - size%256); //align to 256 byte boundaries + return(void*) result; +} + + +void gpgpu_t::memcpy_to_gpu( size_t dst_start_addr, const void *src, size_t count ) +{ + if(g_debug_execution >= 3) { + printf("GPGPU-Sim PTX: copying %zu bytes from CPU[0x%Lx] to GPU[0x%Lx] ... ", count, (unsigned long long) src, (unsigned long long) dst_start_addr ); + fflush(stdout); + } + char *src_data = (char*)src; + for (unsigned n=0; n < count; n ++ ) + m_global_mem->write(dst_start_addr+n,1, src_data+n,NULL,NULL); + if(g_debug_execution >= 3) { + printf( " done.\n"); + fflush(stdout); + } +} + +void gpgpu_t::memcpy_from_gpu( void *dst, size_t src_start_addr, size_t count ) +{ + if(g_debug_execution >= 3) { + printf("GPGPU-Sim PTX: copying %zu bytes from GPU[0x%Lx] to CPU[0x%Lx] ...", count, (unsigned long long) src_start_addr, (unsigned long long) dst ); + fflush(stdout); + } + unsigned char *dst_data = (unsigned char*)dst; + for (unsigned n=0; n < count; n ++ ) + m_global_mem->read(src_start_addr+n,1,dst_data+n); + if(g_debug_execution >= 3) { + printf( " done.\n"); + fflush(stdout); + } +} + +void gpgpu_t::memcpy_gpu_to_gpu( size_t dst, size_t src, size_t count ) +{ + if(g_debug_execution >= 3) { + printf("GPGPU-Sim PTX: copying %zu bytes from GPU[0x%Lx] to GPU[0x%Lx] ...", count, + (unsigned long long) src, (unsigned long long) dst ); + fflush(stdout); + } + for (unsigned n=0; n < count; n ++ ) { + unsigned char tmp; + m_global_mem->read(src+n,1,&tmp); + m_global_mem->write(dst+n,1, &tmp,NULL,NULL); + } + if(g_debug_execution >= 3) { + printf( " done.\n"); + fflush(stdout); + } +} + +void gpgpu_t::gpu_memset( size_t dst_start_addr, int c, size_t count ) +{ + if(g_debug_execution >= 3) { + printf("GPGPU-Sim PTX: setting %zu bytes of memory to 0x%x starting at 0x%Lx... ", + count, (unsigned char) c, (unsigned long long) dst_start_addr ); + fflush(stdout); + } + unsigned char c_value = (unsigned char)c; + for (unsigned n=0; n < count; n ++ ) + m_global_mem->write(dst_start_addr+n,1,&c_value,NULL,NULL); + if(g_debug_execution >= 3) { + printf( " done.\n"); + fflush(stdout); + } +} + +void ptx_print_insn( address_type pc, FILE *fp ) +{ + std::map::iterator f = g_pc_to_finfo.find(pc); + if( f == g_pc_to_finfo.end() ) { + fprintf(fp,"", pc ); + return; + } + function_info *finfo = f->second; + assert( finfo ); + finfo->print_insn(pc,fp); +} + +std::string ptx_get_insn_str( address_type pc ) +{ + std::map::iterator f = g_pc_to_finfo.find(pc); + if( f == g_pc_to_finfo.end() ) { + #define STR_SIZE 255 + char buff[STR_SIZE]; + buff[STR_SIZE - 1] = '\0'; + snprintf(buff, STR_SIZE,"", pc ); + return std::string(buff); + } + function_info *finfo = f->second; + assert( finfo ); + return finfo->get_insn_str(pc); +} + +void ptx_instruction::set_fp_or_int_archop(){ + oprnd_type=UN_OP; + if((m_opcode == MEMBAR_OP)||(m_opcode == SSY_OP )||(m_opcode == BRA_OP) || (m_opcode == BAR_OP) || (m_opcode == RET_OP) || (m_opcode == RETP_OP) || (m_opcode == NOP_OP) || (m_opcode == EXIT_OP) || (m_opcode == CALLP_OP) || (m_opcode == CALL_OP)){ + // do nothing + }else if((m_opcode == CVT_OP || m_opcode == SET_OP || m_opcode == SLCT_OP)){ + if(get_type2()==F16_TYPE || get_type2()==F32_TYPE || get_type2() == F64_TYPE || get_type2() == FF64_TYPE){ + oprnd_type= FP_OP; + }else oprnd_type=INT_OP; + + }else{ + if(get_type()==F16_TYPE || get_type()==F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE){ + oprnd_type= FP_OP; + }else oprnd_type=INT_OP; + } +} +void ptx_instruction::set_mul_div_or_other_archop(){ + sp_op=OTHER_OP; + if((m_opcode != MEMBAR_OP) && (m_opcode != SSY_OP) && (m_opcode != BRA_OP) && (m_opcode != BAR_OP) && (m_opcode != EXIT_OP) && (m_opcode != NOP_OP) && (m_opcode != RETP_OP) && (m_opcode != RET_OP) && (m_opcode != CALLP_OP) && (m_opcode != CALL_OP)){ + if(get_type()==F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE){ + switch(get_opcode()){ + case MUL_OP: + case MAD_OP: + sp_op=FP_MUL_OP; + break; + case DIV_OP: + sp_op=FP_DIV_OP; + break; + case LG2_OP: + sp_op=FP_LG_OP; + break; + case RSQRT_OP: + case SQRT_OP: + sp_op=FP_SQRT_OP; + break; + case RCP_OP: + sp_op=FP_DIV_OP; + break; + case SIN_OP: + case COS_OP: + sp_op=FP_SIN_OP; + break; + case EX2_OP: + sp_op=FP_EXP_OP; + break; + default: + if(op==ALU_OP) + sp_op=FP__OP; + break; + + } + }else { + switch(get_opcode()){ + case MUL24_OP: + case MAD24_OP: + sp_op=INT_MUL24_OP; + break; + case MUL_OP: + case MAD_OP: + if(get_type()==U32_TYPE || get_type()==S32_TYPE || get_type()==B32_TYPE) + sp_op=INT_MUL32_OP; + else + sp_op=INT_MUL_OP; + break; + case DIV_OP: + sp_op=INT_DIV_OP; + break; + default: + if(op==ALU_OP) + sp_op=INT__OP; + break; + } + } + } + +} + + + +void ptx_instruction::set_bar_type() +{ + if(m_opcode==BAR_OP) { + switch(m_barrier_op){ + case SYNC_OPTION: + bar_type = SYNC; + break; + case ARRIVE_OPTION: + bar_type = ARRIVE; + break; + case RED_OPTION: + bar_type = RED; + switch(m_atomic_spec){ + case ATOMIC_POPC: + red_type = POPC_RED; + break; + case ATOMIC_AND: + red_type = AND_RED; + break; + case ATOMIC_OR: + red_type = OR_RED; + break; + } + break; + default: + abort(); + } + } +} + + +void ptx_instruction::set_opcode_and_latency() +{ + unsigned int_latency[5]; + unsigned fp_latency[5]; + unsigned dp_latency[5]; + unsigned int_init[5]; + unsigned fp_init[5]; + unsigned dp_init[5]; + /* + * [0] ADD,SUB + * [1] MAX,Min + * [2] MUL + * [3] MAD + * [4] DIV + */ + sscanf(opcode_latency_int, "%u,%u,%u,%u,%u", + &int_latency[0],&int_latency[1],&int_latency[2], + &int_latency[3],&int_latency[4]); + sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u", + &fp_latency[0],&fp_latency[1],&fp_latency[2], + &fp_latency[3],&fp_latency[4]); + sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u", + &dp_latency[0],&dp_latency[1],&dp_latency[2], + &dp_latency[3],&dp_latency[4]); + sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u", + &int_init[0],&int_init[1],&int_init[2], + &int_init[3],&int_init[4]); + sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u", + &fp_init[0],&fp_init[1],&fp_init[2], + &fp_init[3],&fp_init[4]); + sscanf(opcode_initiation_dp, "%u,%u,%u,%u,%u", + &dp_init[0],&dp_init[1],&dp_init[2], + &dp_init[3],&dp_init[4]); + sscanf(cdp_latency_str, "%u,%u,%u,%u,%u", + &cdp_latency[0],&cdp_latency[1],&cdp_latency[2], + &cdp_latency[3],&cdp_latency[4]); + + if(!m_operands.empty()){ + std::vector::iterator it; + for(it=++m_operands.begin();it!=m_operands.end();it++){ + num_operands++; + if((it->is_reg() || it->is_vector())){ + num_regs++; + } + } + } + op = ALU_OP; + mem_op= NOT_TEX; + initiation_interval = latency = 1; + switch( m_opcode ) { + case MOV_OP: + assert( !(has_memory_read() && has_memory_write()) ); + if ( has_memory_read() ) op = LOAD_OP; + if ( has_memory_write() ) op = STORE_OP; + break; + case LD_OP: op = LOAD_OP; break; + case LDU_OP: op = LOAD_OP; break; + case ST_OP: op = STORE_OP; break; + case BRA_OP: op = BRANCH_OP; break; + case BREAKADDR_OP: op = BRANCH_OP; break; + case TEX_OP: op = LOAD_OP; mem_op=TEX; break; + case ATOM_OP: op = LOAD_OP; break; + case BAR_OP: op = BARRIER_OP; break; + case MEMBAR_OP: op = MEMORY_BARRIER_OP; break; + case CALL_OP: + { + if(m_is_printf || m_is_cdp) { + op = ALU_OP; + } + else + op = CALL_OPS; + break; + } + case CALLP_OP: + { + if(m_is_printf || m_is_cdp) { + op = ALU_OP; + } + else + op = CALL_OPS; + break; + } + case RET_OP: case RETP_OP: op = RET_OPS;break; + case ADD_OP: case ADDP_OP: case ADDC_OP: case SUB_OP: case SUBC_OP: + //ADD,SUB latency + switch(get_type()){ + case F32_TYPE: + latency = fp_latency[0]; + initiation_interval = fp_init[0]; + break; + case F64_TYPE: + case FF64_TYPE: + latency = dp_latency[0]; + initiation_interval = dp_init[0]; + break; + case B32_TYPE: + case U32_TYPE: + case S32_TYPE: + default: //Use int settings for default + latency = int_latency[0]; + initiation_interval = int_init[0]; + break; + } + break; + case MAX_OP: case MIN_OP: + //MAX,MIN latency + switch(get_type()){ + case F32_TYPE: + latency = fp_latency[1]; + initiation_interval = fp_init[1]; + break; + case F64_TYPE: + case FF64_TYPE: + latency = dp_latency[1]; + initiation_interval = dp_init[1]; + break; + case B32_TYPE: + case U32_TYPE: + case S32_TYPE: + default: //Use int settings for default + latency = int_latency[1]; + initiation_interval = int_init[1]; + break; + } + break; + case MUL_OP: + //MUL latency + switch(get_type()){ + case F32_TYPE: + latency = fp_latency[2]; + initiation_interval = fp_init[2]; + op = ALU_SFU_OP; + break; + case F64_TYPE: + case FF64_TYPE: + latency = dp_latency[2]; + initiation_interval = dp_init[2]; + op = ALU_SFU_OP; + break; + case B32_TYPE: + case U32_TYPE: + case S32_TYPE: + default: //Use int settings for default + latency = int_latency[2]; + initiation_interval = int_init[2]; + op = SFU_OP; + break; + } + break; + case MAD_OP: case MADC_OP: case MADP_OP: + //MAD latency + switch(get_type()){ + case F32_TYPE: + latency = fp_latency[3]; + initiation_interval = fp_init[3]; + break; + case F64_TYPE: + case FF64_TYPE: + latency = dp_latency[3]; + initiation_interval = dp_init[3]; + break; + case B32_TYPE: + case U32_TYPE: + case S32_TYPE: + default: //Use int settings for default + latency = int_latency[3]; + initiation_interval = int_init[3]; + op = SFU_OP; + break; + } + break; + case DIV_OP: + // Floating point only + op = SFU_OP; + switch(get_type()){ + case F32_TYPE: + latency = fp_latency[4]; + initiation_interval = fp_init[4]; + break; + case F64_TYPE: + case FF64_TYPE: + latency = dp_latency[4]; + initiation_interval = dp_init[4]; + break; + case B32_TYPE: + case U32_TYPE: + case S32_TYPE: + default: //Use int settings for default + latency = int_latency[4]; + initiation_interval = int_init[4]; + break; + } + break; + case SQRT_OP: case SIN_OP: case COS_OP: case EX2_OP: case LG2_OP: case RSQRT_OP: case RCP_OP: + //Using double to approximate those + latency = dp_latency[2]; + initiation_interval = dp_init[2]; + op = SFU_OP; + break; + case SHFL_OP: + latency = 32; + initiation_interval = 15; + break; + default: + break; + } + set_fp_or_int_archop(); + set_mul_div_or_other_archop(); + +} + +void ptx_thread_info::ptx_fetch_inst( inst_t &inst ) const +{ + addr_t pc = get_pc(); + const ptx_instruction *pI = m_func_info->get_instruction(pc); + inst = (const inst_t&)*pI; + assert( inst.valid() ); +} + +static unsigned datatype2size( unsigned data_type ) +{ + unsigned data_size; + switch ( data_type ) { + case B8_TYPE: + case S8_TYPE: + case U8_TYPE: + data_size = 1; break; + case B16_TYPE: + case S16_TYPE: + case U16_TYPE: + case F16_TYPE: + data_size = 2; break; + case B32_TYPE: + case S32_TYPE: + case U32_TYPE: + case F32_TYPE: + data_size = 4; break; + case B64_TYPE: + case BB64_TYPE: + case S64_TYPE: + case U64_TYPE: + case F64_TYPE: + case FF64_TYPE: + data_size = 8; break; + case BB128_TYPE: + data_size = 16; break; + default: assert(0); break; + } + return data_size; +} + +void ptx_instruction::pre_decode() +{ + pc = m_PC; + isize = m_inst_size; + for( unsigned i=0; i<4; i++) { + out[i] = 0; + in[i] = 0; + } + is_vectorin = 0; + is_vectorout = 0; + std::fill_n(arch_reg.src, MAX_REG_OPERANDS, -1); + std::fill_n(arch_reg.dst, MAX_REG_OPERANDS, -1); + pred = 0; + ar1 = 0; + ar2 = 0; + space = m_space_spec; + memory_op = no_memory_op; + data_size = 0; + if ( has_memory_read() || has_memory_write() ) { + unsigned to_type = get_type(); + data_size = datatype2size(to_type); + memory_op = has_memory_read() ? memory_load : memory_store; + } + + bool has_dst = false ; + + switch ( get_opcode() ) { +#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; +#include "opcodes.def" +#undef OP_DEF +#undef OP_W_DEF + default: + printf( "Execution error: Invalid opcode (0x%x)\n", get_opcode() ); + break; + } + + switch( m_cache_option ) { + case CA_OPTION: cache_op = CACHE_ALL; break; + case CG_OPTION: cache_op = CACHE_GLOBAL; break; + case CS_OPTION: cache_op = CACHE_STREAMING; break; + case LU_OPTION: cache_op = CACHE_LAST_USE; break; + case CV_OPTION: cache_op = CACHE_VOLATILE; break; + case WB_OPTION: cache_op = CACHE_WRITE_BACK; break; + case WT_OPTION: cache_op = CACHE_WRITE_THROUGH; break; + default: + if( m_opcode == LD_OP || m_opcode == LDU_OP ) + cache_op = CACHE_ALL; + else if( m_opcode == ST_OP ) + cache_op = CACHE_WRITE_BACK; + else if( m_opcode == ATOM_OP ) + cache_op = CACHE_GLOBAL; + break; + } + + set_opcode_and_latency(); + set_bar_type(); + // Get register operands + int n=0,m=0; + ptx_instruction::const_iterator opr=op_iter_begin(); + for ( ; opr != op_iter_end(); opr++, n++ ) { //process operands + const operand_info &o = *opr; + if ( has_dst && n==0 ) { + // Do not set the null register "_" as an architectural register + if ( o.is_reg() && !o.is_non_arch_reg() ) { + out[0] = o.reg_num(); + arch_reg.dst[0] = o.arch_reg_num(); + } else if ( o.is_vector() ) { + is_vectorin = 1; + unsigned num_elem = o.get_vect_nelem(); + if( num_elem >= 1 ) out[0] = o.reg1_num(); + if( num_elem >= 2 ) out[1] = o.reg2_num(); + if( num_elem >= 3 ) out[2] = o.reg3_num(); + if( num_elem >= 4 ) out[3] = o.reg4_num(); + for (int i = 0; i < num_elem; i++) + arch_reg.dst[i] = o.arch_reg_num(i); + } + } else { + if ( o.is_reg() && !o.is_non_arch_reg() ) { + int reg_num = o.reg_num(); + arch_reg.src[m] = o.arch_reg_num(); + switch ( m ) { + case 0: in[0] = reg_num; break; + case 1: in[1] = reg_num; break; + case 2: in[2] = reg_num; break; + default: break; + } + m++; + } else if ( o.is_vector() ) { + //assert(m == 0); //only support 1 vector operand (for textures) right now + is_vectorout = 1; + unsigned num_elem = o.get_vect_nelem(); + if( num_elem >= 1 ) in[0] = o.reg1_num(); + if( num_elem >= 2 ) in[1] = o.reg2_num(); + if( num_elem >= 3 ) in[2] = o.reg3_num(); + if( num_elem >= 4 ) in[3] = o.reg4_num(); + for (int i = 0; i < num_elem; i++) + arch_reg.src[i] = o.arch_reg_num(i); + m+=4; + } + } + } + + // Get predicate + if(has_pred()) { + const operand_info &p = get_pred(); + pred = p.reg_num(); + } + + // Get address registers inside memory operands. + // Assuming only one memory operand per instruction, + // and maximum of two address registers for one memory operand. + if( has_memory_read() || has_memory_write() ) { + ptx_instruction::const_iterator op=op_iter_begin(); + for ( ; op != op_iter_end(); op++, n++ ) { //process operands + const operand_info &o = *op; + + if(o.is_memory_operand()) { + // We do not support the null register as a memory operand + assert( !o.is_non_arch_reg() ); + + // Check PTXPlus-type operand + // memory operand with addressing (ex. s[0x4] or g[$r1]) + if(o.is_memory_operand2()) { + + // memory operand with one address register (ex. g[$r1+0x4] or s[$r2+=0x4]) + if(o.get_double_operand_type() == 0 || o.get_double_operand_type() == 3){ + ar1 = o.reg_num(); + arch_reg.src[4] = o.arch_reg_num(); + // TODO: address register in $r2+=0x4 should be an output register as well + } + // memory operand with two address register (ex. s[$r1+$r1] or g[$r1+=$r2]) + else if(o.get_double_operand_type() == 1 || o.get_double_operand_type() == 2) { + ar1 = o.reg1_num(); + arch_reg.src[4] = o.arch_reg_num(); + ar2 = o.reg2_num(); + arch_reg.src[5] = o.arch_reg_num(); + // TODO: first address register in $r1+=$r2 should be an output register as well + } + } + else if(o.is_immediate_address()){ + + } + // Regular PTX operand + else if (o.get_symbol()->type()->get_key().is_reg()) { // Memory operand contains a register + ar1 = o.reg_num(); + arch_reg.src[4] = o.arch_reg_num(); + } + + } + } + } + + // get reconvergence pc + reconvergence_pc = get_converge_point(pc); + + m_decoded=true; +} + +void function_info::add_param_name_type_size( unsigned index, std::string name, int type, size_t size, bool ptr, memory_space_t space ) +{ + unsigned parsed_index; + char buffer[2048]; + snprintf(buffer,2048,"%s_param_%%u", m_name.c_str() ); + int ntokens = sscanf(name.c_str(),buffer,&parsed_index); + if( ntokens == 1 ) { + assert( m_ptx_kernel_param_info.find(parsed_index) == m_ptx_kernel_param_info.end() ); + m_ptx_kernel_param_info[parsed_index] = param_info(name, type, size, ptr, space); + } else { + assert( m_ptx_kernel_param_info.find(index) == m_ptx_kernel_param_info.end() ); + m_ptx_kernel_param_info[index] = param_info(name, type, size, ptr, space); + } +} + +void function_info::add_param_data( unsigned argn, struct gpgpu_ptx_sim_arg *args ) +{ + const void *data = args->m_start; + + bool scratchpad_memory_param = false; // Is this parameter in CUDA shared memory or OpenCL local memory + + std::map::iterator i=m_ptx_kernel_param_info.find(argn); + if( i != m_ptx_kernel_param_info.end() ) { + if (i->second.is_ptr_shared()) { + assert(args->m_start == NULL && "OpenCL parameter pointer to local memory must have NULL as value"); + scratchpad_memory_param = true; + } else { + param_t tmp; + tmp.pdata = args->m_start; + tmp.size = args->m_nbytes; + tmp.offset = args->m_offset; + tmp.type = 0; + i->second.add_data(tmp); + i->second.add_offset((unsigned) args->m_offset); + } + } else { + scratchpad_memory_param = true; + } + + if (scratchpad_memory_param) { + // This should only happen for OpenCL: + // + // The LLVM PTX compiler in NVIDIA's driver (version 190.29) + // does not generate an argument in the function declaration + // for __constant arguments. + // + // The associated constant memory space can be allocated in two + // ways. It can be explicitly initialized in the .ptx file where + // it is declared. Or, it can be allocated using the clCreateBuffer + // on the host. In this later case, the .ptx file will contain + // a global declaration of the parameter, but it will have an unknown + // array size. Thus, the symbol's address will not be set and we need + // to set it here before executing the PTX. + + char buffer[2048]; + snprintf(buffer,2048,"%s_param_%u",m_name.c_str(),argn); + + symbol *p = m_symtab->lookup(buffer); + if( p == NULL ) { + printf("GPGPU-Sim PTX: ERROR ** could not locate symbol for \'%s\' : cannot bind buffer\n", buffer); + abort(); + } + if( data ) + p->set_address((addr_t)*(size_t*)data); + else { + // clSetKernelArg was passed NULL pointer for data... + // this is used for dynamically sized shared memory on NVIDIA platforms + bool is_ptr_shared = false; + if( i != m_ptx_kernel_param_info.end() ) { + is_ptr_shared = i->second.is_ptr_shared(); + } + + if( !is_ptr_shared and !p->is_shared() ) { + printf("GPGPU-Sim PTX: ERROR ** clSetKernelArg passed NULL but arg not shared memory\n"); + abort(); + } + unsigned num_bits = 8*args->m_nbytes; + printf("GPGPU-Sim PTX: deferred allocation of shared region for \"%s\" from 0x%x to 0x%x (shared memory space)\n", + p->name().c_str(), + m_symtab->get_shared_next(), + m_symtab->get_shared_next() + num_bits/8 ); + fflush(stdout); + assert( (num_bits%8) == 0 ); + addr_t addr = m_symtab->get_shared_next(); + addr_t addr_pad = num_bits ? (((num_bits/8) - (addr % (num_bits/8))) % (num_bits/8)) : 0; + p->set_address( addr+addr_pad ); + m_symtab->alloc_shared( num_bits/8 + addr_pad ); + } + } +} + +unsigned function_info::get_args_aligned_size() { + + if(m_args_aligned_size >= 0) + return m_args_aligned_size; + + unsigned param_address = 0; + unsigned int total_size = 0; + for( std::map::iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { + param_info &p = i->second; + std::string name = p.get_name(); + symbol *param = m_symtab->lookup(name.c_str()); + + size_t arg_size = p.get_size() / 8; // size of param in bytes + total_size = (total_size + arg_size - 1) / arg_size * arg_size; //aligned + p.add_offset(total_size); + param->set_address(param_address + total_size); + total_size += arg_size; + } + + m_args_aligned_size = (total_size + 3) / 4 * 4; //final size aligned to word + + return m_args_aligned_size; + +} + + +void function_info::finalize( memory_space *param_mem ) +{ + unsigned param_address = 0; + for( std::map::iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { + param_info &p = i->second; + if (p.is_ptr_shared()) continue; // Pointer to local memory: Should we pass the allocated shared memory address to the param memory space? + std::string name = p.get_name(); + int type = p.get_type(); + param_t param_value = p.get_value(); + param_value.type = type; + symbol *param = m_symtab->lookup(name.c_str()); + unsigned xtype = param->type()->get_key().scalar_type(); + assert(xtype==(unsigned)type); + size_t size; + size = param_value.size; // size of param in bytes + // assert(param_value.offset == param_address); + if( size != p.get_size() / 8) { + printf("GPGPU-Sim PTX: WARNING actual kernel paramter size = %zu bytes vs. formal size = %zu (using smaller of two)\n", + size, p.get_size()/8); + size = (size<(p.get_size()/8))?size:(p.get_size()/8); + } + // copy the parameter over word-by-word so that parameter that crosses a memory page can be copied over + //Jin: copy parameter using aligned rules + const size_t word_size = 4; + param_address = (param_address + size - 1) / size * size; //aligned with size + for (size_t idx = 0; idx < size; idx += word_size) { + const char *pdata = reinterpret_cast(param_value.pdata) + idx; // cast to char * for ptr arithmetic + param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); + } + unsigned offset = p.get_offset(); + assert(offset == param_address); + param->set_address(param_address); + param_address += size; + } +} + +void function_info::param_to_shared( memory_space *shared_mem, symbol_table *symtab ) +{ + // TODO: call this only for PTXPlus with GT200 models + extern gpgpu_sim* g_the_gpu; + if (not g_the_gpu->get_config().convert_to_ptxplus()) return; + + // copies parameters into simulated shared memory + for( std::map::iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { + param_info &p = i->second; + if (p.is_ptr_shared()) continue; // Pointer to local memory: Should we pass the allocated shared memory address to the param memory space? + std::string name = p.get_name(); + int type = p.get_type(); + param_t value = p.get_value(); + value.type = type; + symbol *param = symtab->lookup(name.c_str()); + unsigned xtype = param->type()->get_key().scalar_type(); + assert(xtype==(unsigned)type); + + int tmp; + size_t size; + unsigned offset = p.get_offset(); + type_info_key::type_decode(xtype,size,tmp); + + // Write to shared memory - offset + 0x10 + shared_mem->write(offset+0x10,size/8,value.pdata,NULL,NULL); + } +} + + +void function_info::list_param( FILE *fout ) const +{ + for( std::map::const_iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { + const param_info &p = i->second; + std::string name = p.get_name(); + symbol *param = m_symtab->lookup(name.c_str()); + addr_t param_addr = param->get_address(); + fprintf(fout, "%s: %#08x\n", name.c_str(), param_addr); + } + fflush(fout); +} + +template +bool ptx_debug_exec_dump_cond(int thd_uid, addr_t pc) +{ + if (g_debug_execution >= activate_level) { + // check each type of debug dump constraint to filter out dumps + if ( (g_debug_thread_uid != 0) && (thd_uid != (unsigned)g_debug_thread_uid) ) { + return false; + } + if ( (g_debug_pc != 0xBEEF1518) && (pc != g_debug_pc) ) { + return false; + } + + return true; + } + + return false; +} + +void init_inst_classification_stat() +{ + static std::set init; + if( init.find(g_ptx_kernel_count) != init.end() ) + return; + init.insert(g_ptx_kernel_count); + + #define MAX_CLASS_KER 1024 + char kernelname[MAX_CLASS_KER] =""; + if (!g_inst_classification_stat) g_inst_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); + snprintf(kernelname, MAX_CLASS_KER, "Kernel %d Classification\n",g_ptx_kernel_count ); + assert( g_ptx_kernel_count < MAX_CLASS_KER ) ; // a static limit on number of kernels increase it if it fails! + g_inst_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,20); + if (!g_inst_op_classification_stat) g_inst_op_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); + snprintf(kernelname, MAX_CLASS_KER, "Kernel %d OP Classification\n",g_ptx_kernel_count ); + g_inst_op_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,100); +} + +static unsigned get_tex_datasize( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &src1 = pI->src1(); //the name of the texture + std::string texname = src1.name(); + + gpgpu_t *gpu = thread->get_gpu(); + const struct textureReference* texref = gpu->get_texref(texname); + const struct textureInfo* texInfo = gpu->get_texinfo(texref); + + unsigned data_size = texInfo->texel_size; + return data_size; +} + +void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) +{ + + bool skip = false; + int op_classification = 0; + addr_t pc = next_instr(); + assert( pc == inst.pc ); // make sure timing model and functional model are in sync + const ptx_instruction *pI = m_func_info->get_instruction(pc); + set_npc( pc + pI->inst_size() ); + + + try { + + clearRPC(); + m_last_set_operand_value.u64 = 0; + + if(is_done()) + { + printf("attempted to execute instruction on a thread that is already done.\n"); + assert(0); + } + + if ( g_debug_execution >= 6 || m_gpu->get_config().get_ptx_inst_debug_to_file()) { + if ( (g_debug_thread_uid==0) || (get_uid() == (unsigned)g_debug_thread_uid) ) { + + clear_modifiedregs(); + enable_debug_trace(); + } + } + + + if( pI->has_pred() ) { + const operand_info &pred = pI->get_pred(); + ptx_reg_t pred_value = get_operand_value(pred, pred, PRED_TYPE, this, 0); + if(pI->get_pred_mod() == -1) { + skip = (pred_value.pred & 0x0001) ^ pI->get_pred_neg(); //ptxplus inverts the zero flag + } else { + skip = !pred_lookup(pI->get_pred_mod(), pred_value.pred & 0x000F); + } + } + + if( skip ) { + inst.set_not_active(lane_id); + } else { + const ptx_instruction *pI_saved = pI; + ptx_instruction *pJ = NULL; + if( pI->get_opcode() == VOTE_OP ) { + pJ = new ptx_instruction(*pI); + *((warp_inst_t*)pJ) = inst; // copy active mask information + pI = pJ; + } + switch ( pI->get_opcode() ) { +#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; +#include "opcodes.def" +#undef OP_DEF +#undef OP_W_DEF + default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break; + } + delete pJ; + pI = pI_saved; + + // Run exit instruction if exit option included + if(pI->is_exit()) + exit_impl(pI,this); + } + + + + const gpgpu_functional_sim_config &config = m_gpu->get_config(); + + // Output instruction information to file and stdout + if( config.get_ptx_inst_debug_to_file() != 0 && + (config.get_ptx_inst_debug_thread_uid() == 0 || config.get_ptx_inst_debug_thread_uid() == get_uid()) ) { + fprintf(m_gpu->get_ptx_inst_debug_file(), + "[thd=%u] : (%s:%u - %s)\n", + get_uid(), + pI->source_file(), pI->source_line(), pI->get_source() ); + //fprintf(ptx_inst_debug_file, "has memory read=%d, has memory write=%d\n", pI->has_memory_read(), pI->has_memory_write()); + fflush(m_gpu->get_ptx_inst_debug_file()); + } + + if ( ptx_debug_exec_dump_cond<5>(get_uid(), pc) ) { + dim3 ctaid = get_ctaid(); + dim3 tid = get_tid(); + printf("%u [thd=%u][i=%u] : ctaid=(%u,%u,%u) tid=(%u,%u,%u) icount=%u [pc=%u] (%s:%u - %s) [0x%llx]\n", + g_ptx_sim_num_insn, + get_uid(), + pI->uid(), ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z, + get_icount(), + pc, pI->source_file(), pI->source_line(), pI->get_source(), + m_last_set_operand_value.u64 ); + fflush(stdout); + } + + addr_t insn_memaddr = 0xFEEBDAED; + memory_space_t insn_space = undefined_space; + _memory_op_t insn_memory_op = no_memory_op; + unsigned insn_data_size = 0; + if ( (pI->has_memory_read() || pI->has_memory_write()) ) { + insn_memaddr = last_eaddr(); + insn_space = last_space(); + unsigned to_type = pI->get_type(); + insn_data_size = datatype2size(to_type); + insn_memory_op = pI->has_memory_read() ? memory_load : memory_store; + } + + if ( pI->get_opcode() == BAR_OP && pI->barrier_op() == RED_OPTION) { + inst.add_callback( lane_id, last_callback().function, last_callback().instruction, this,false /*not atomic*/); + } + + if ( pI->get_opcode() == ATOM_OP ) { + insn_memaddr = last_eaddr(); + insn_space = last_space(); + inst.add_callback( lane_id, last_callback().function, last_callback().instruction, this,true /*atomic*/); + unsigned to_type = pI->get_type(); + insn_data_size = datatype2size(to_type); + } + + if (pI->get_opcode() == TEX_OP) { + inst.set_addr(lane_id, last_eaddr() ); + assert( inst.space == last_space() ); + insn_data_size = get_tex_datasize(pI, this); // texture obtain its data granularity from the texture info + } + + // Output register information to file and stdout + if( config.get_ptx_inst_debug_to_file()!=0 && + (config.get_ptx_inst_debug_thread_uid()==0||config.get_ptx_inst_debug_thread_uid()==get_uid()) ) { + dump_modifiedregs(m_gpu->get_ptx_inst_debug_file()); + dump_regs(m_gpu->get_ptx_inst_debug_file()); + } + + if ( g_debug_execution >= 6 ) { + if ( ptx_debug_exec_dump_cond<6>(get_uid(), pc) ) + dump_modifiedregs(stdout); + } + if ( g_debug_execution >= 10 ) { + if ( ptx_debug_exec_dump_cond<10>(get_uid(), pc) ) + dump_regs(stdout); + } + update_pc(); + g_ptx_sim_num_insn++; + + //not using it with functional simulation mode + if(!(this->m_functionalSimulationMode)) + ptx_file_line_stats_add_exec_count(pI); + + if ( gpgpu_ptx_instruction_classification ) { + init_inst_classification_stat(); + unsigned space_type=0; + switch ( pI->get_space().get_type() ) { + case global_space: space_type = 10; break; + case local_space: space_type = 11; break; + case tex_space: space_type = 12; break; + case surf_space: space_type = 13; break; + case param_space_kernel: + case param_space_local: + space_type = 14; break; + case shared_space: space_type = 15; break; + case const_space: space_type = 16; break; + default: + space_type = 0 ; + break; + } + StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], op_classification); + if (space_type) StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], ( int )space_type); + StatAddSample( g_inst_op_classification_stat[g_ptx_kernel_count], (int) pI->get_opcode() ); + } + if ( (g_ptx_sim_num_insn % 100000) == 0 ) { + dim3 ctaid = get_ctaid(); + dim3 tid = get_tid(); + printf("GPGPU-Sim PTX: %u instructions simulated : ctaid=(%u,%u,%u) tid=(%u,%u,%u)\n", + g_ptx_sim_num_insn, ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z ); + fflush(stdout); + } + + // "Return values" + if(!skip) { + inst.space = insn_space; + inst.set_addr(lane_id, insn_memaddr); + inst.data_size = insn_data_size; // simpleAtomicIntrinsics + assert( inst.memory_op == insn_memory_op ); + } + + } catch ( int x ) { + printf("GPGPU-Sim PTX: ERROR (%d) executing intruction (%s:%u)\n", x, pI->source_file(), pI->source_line() ); + printf("GPGPU-Sim PTX: '%s'\n", pI->get_source() ); + abort(); + } + +} + +void set_param_gpgpu_num_shaders(int num_shaders) +{ + gpgpu_param_num_shaders = num_shaders; +} + +const struct gpgpu_ptx_sim_info* ptx_sim_kernel_info(const function_info *kernel) +{ + return kernel->get_kernel_info(); +} + +const warp_inst_t *ptx_fetch_inst( address_type pc ) +{ + return function_info::pc_to_instruction(pc); +} + +unsigned ptx_sim_init_thread( kernel_info_t &kernel, + ptx_thread_info** thread_info, + int sid, + unsigned tid, + unsigned threads_left, + unsigned num_threads, + core_t *core, + unsigned hw_cta_id, + unsigned hw_warp_id, + gpgpu_t *gpu, + bool isInFunctionalSimulationMode) +{ + std::list &active_threads = kernel.active_threads(); + + static std::map shared_memory_lookup; + static std::map ptx_cta_lookup; + static std::map ptx_warp_lookup; + static std::map > local_memory_lookup; + + if ( *thread_info != NULL ) { + ptx_thread_info *thd = *thread_info; + assert( thd->is_done() ); + if ( g_debug_execution==-1 ) { + dim3 ctaid = thd->get_ctaid(); + dim3 t = thd->get_tid(); + printf("GPGPU-Sim PTX simulator: thread exiting ctaid=(%u,%u,%u) tid=(%u,%u,%u) uid=%u\n", + ctaid.x,ctaid.y,ctaid.z,t.x,t.y,t.z, thd->get_uid() ); + fflush(stdout); + } + thd->m_cta_info->register_deleted_thread(thd); + delete thd; + *thread_info = NULL; + } + + if ( !active_threads.empty() ) { + assert( active_threads.size() <= threads_left ); + ptx_thread_info *thd = active_threads.front(); + active_threads.pop_front(); + *thread_info = thd; + thd->init(gpu, core, sid, hw_cta_id, hw_warp_id, tid, isInFunctionalSimulationMode ); + return 1; + } + + if ( kernel.no_more_ctas_to_run() ) { + return 0; //finished! + } + + if ( threads_left < kernel.threads_per_cta() ) { + return 0; + } + + if ( g_debug_execution==-1 ) { + printf("GPGPU-Sim PTX simulator: STARTING THREAD ALLOCATION --> \n"); + fflush(stdout); + } + + //initializing new CTA + ptx_cta_info *cta_info = NULL; + memory_space *shared_mem = NULL; + + unsigned cta_size = kernel.threads_per_cta(); + unsigned max_cta_per_sm = num_threads/cta_size; // e.g., 256 / 48 = 5 + assert( max_cta_per_sm > 0 ); + + //unsigned sm_idx = (tid/cta_size)*gpgpu_param_num_shaders + sid; + unsigned sm_idx = hw_cta_id*gpgpu_param_num_shaders + sid; + + if ( shared_memory_lookup.find(sm_idx) == shared_memory_lookup.end() ) { + if ( g_debug_execution >= 1 ) { + printf(" : sm_idx=%u sid=%u max_cta_per_sm=%u\n", + sm_idx, sid, max_cta_per_sm ); + } + char buf[512]; + snprintf(buf,512,"shared_%u", sid); + shared_mem = new memory_space_impl<16*1024>(buf,4); + shared_memory_lookup[sm_idx] = shared_mem; + cta_info = new ptx_cta_info(sm_idx); + ptx_cta_lookup[sm_idx] = cta_info; + } else { + if ( g_debug_execution >= 1 ) { + printf(" : sm_idx=%u sid=%u max_cta_per_sm=%u\n", + sm_idx, sid, max_cta_per_sm ); + } + shared_mem = shared_memory_lookup[sm_idx]; + cta_info = ptx_cta_lookup[sm_idx]; + cta_info->check_cta_thread_status_and_reset(); + } + + std::map &local_mem_lookup = local_memory_lookup[sid]; + while( kernel.more_threads_in_cta() ) { + dim3 ctaid3d = kernel.get_next_cta_id(); + unsigned new_tid = kernel.get_next_thread_id(); + dim3 tid3d = kernel.get_next_thread_id_3d(); + kernel.increment_thread_id(); + new_tid += tid; + ptx_thread_info *thd = new ptx_thread_info(kernel); + + ptx_warp_info *warp_info = NULL; + if ( ptx_warp_lookup.find(hw_warp_id) == ptx_warp_lookup.end() ) { + warp_info = new ptx_warp_info(); + ptx_warp_lookup[hw_warp_id] = warp_info; + } else { + warp_info = ptx_warp_lookup[hw_warp_id]; + } + thd->m_warp_info = warp_info; + + memory_space *local_mem = NULL; + std::map::iterator l = local_mem_lookup.find(new_tid); + if ( l != local_mem_lookup.end() ) { + local_mem = l->second; + } else { + char buf[512]; + snprintf(buf,512,"local_%u_%u", sid, new_tid); + local_mem = new memory_space_impl<32>(buf,32); + local_mem_lookup[new_tid] = local_mem; + } + thd->set_info(kernel.entry()); + thd->set_nctaid(kernel.get_grid_dim()); + thd->set_ntid(kernel.get_cta_dim()); + thd->set_ctaid(ctaid3d); + thd->set_tid(tid3d); + if( kernel.entry()->get_ptx_version().extensions() ) + thd->cpy_tid_to_reg(tid3d); + thd->set_valid(); + thd->m_shared_mem = shared_mem; + function_info *finfo = thd->func_info(); + symbol_table *st = finfo->get_symtab(); + thd->func_info()->param_to_shared(thd->m_shared_mem,st); + thd->m_cta_info = cta_info; + cta_info->add_thread(thd); + thd->m_local_mem = local_mem; + if ( g_debug_execution==-1 ) { + printf("GPGPU-Sim PTX simulator: allocating thread ctaid=(%u,%u,%u) tid=(%u,%u,%u) @ 0x%Lx\n", + ctaid3d.x,ctaid3d.y,ctaid3d.z,tid3d.x,tid3d.y,tid3d.z, (unsigned long long)thd ); + fflush(stdout); + } + active_threads.push_back(thd); + } + if ( g_debug_execution==-1 ) { + printf("GPGPU-Sim PTX simulator: <-- FINISHING THREAD ALLOCATION\n"); + fflush(stdout); + } + + kernel.increment_cta_id(); + + assert( active_threads.size() <= threads_left ); + *thread_info = active_threads.front(); + (*thread_info)->init(gpu, core, sid, hw_cta_id, hw_warp_id, tid,isInFunctionalSimulationMode ); + active_threads.pop_front(); + return 1; +} + +size_t get_kernel_code_size( class function_info *entry ) +{ + return entry->get_function_size(); +} + + +kernel_info_t *gpgpu_opencl_ptx_sim_init_grid(class function_info *entry, + gpgpu_ptx_sim_arg_list_t args, + struct dim3 gridDim, + struct dim3 blockDim, + gpgpu_t *gpu ) +{ + kernel_info_t *result = new kernel_info_t(gridDim,blockDim,entry); + unsigned argcount=args.size(); + unsigned argn=1; + for( gpgpu_ptx_sim_arg_list_t::iterator a = args.begin(); a != args.end(); a++ ) { + entry->add_param_data(argcount-argn,&(*a)); + argn++; + } + entry->finalize(result->get_param_memory()); + g_ptx_kernel_count++; + fflush(stdout); + + return result; +} + +#include "../../version" +#include "detailed_version" + +void print_splash() +{ + static int splash_printed=0; + if ( !splash_printed ) { + fprintf(stdout, "\n\n *** %s [build %s] ***\n\n\n", g_gpgpusim_version_string, g_gpgpusim_build_string ); + splash_printed=1; + } +} + +std::map g_const_name_lookup; // indexed by hostVar +std::map g_global_name_lookup; // indexed by hostVar +std::set g_globals; +std::set g_constants; + +void gpgpu_ptx_sim_register_const_variable(void *hostVar, const char *deviceName, size_t size ) +{ + printf("GPGPU-Sim PTX registering constant %s (%zu bytes) to name mapping\n", deviceName, size ); + g_const_name_lookup[hostVar] = deviceName; +} + +void gpgpu_ptx_sim_register_global_variable(void *hostVar, const char *deviceName, size_t size ) +{ + printf("GPGPU-Sim PTX registering global %s hostVar to name mapping\n", deviceName ); + g_global_name_lookup[hostVar] = deviceName; +} + +void gpgpu_ptx_sim_memcpy_symbol(const char *hostVar, const void *src, size_t count, size_t offset, int to, gpgpu_t *gpu ) +{ + printf("GPGPU-Sim PTX: starting gpgpu_ptx_sim_memcpy_symbol with hostVar 0x%p\n", hostVar); + bool found_sym = false; + memory_space_t mem_region = undefined_space; + std::string sym_name; + + std::map::iterator c=g_const_name_lookup.find(hostVar); + if ( c!=g_const_name_lookup.end() ) { + found_sym = true; + sym_name = c->second; + mem_region = const_space; + } + std::map::iterator g=g_global_name_lookup.find(hostVar); + if ( g!=g_global_name_lookup.end() ) { + if ( found_sym ) { + printf("Execution error: PTX symbol \"%s\" w/ hostVar=0x%Lx is declared both const and global?\n", + sym_name.c_str(), (unsigned long long)hostVar ); + abort(); + } + found_sym = true; + sym_name = g->second; + mem_region = global_space; + } + if( g_globals.find(hostVar) != g_globals.end() ) { + found_sym = true; + sym_name = hostVar; + mem_region = global_space; + } + if( g_constants.find(hostVar) != g_constants.end() ) { + found_sym = true; + sym_name = hostVar; + mem_region = const_space; + } + + if ( !found_sym ) { + printf("Execution error: No information for PTX symbol w/ hostVar=0x%Lx\n", (unsigned long long)hostVar ); + abort(); + } else printf("GPGPU-Sim PTX: gpgpu_ptx_sim_memcpy_symbol: Found PTX symbol w/ hostVar=0x%Lx\n", (unsigned long long)hostVar ); + const char *mem_name = NULL; + memory_space *mem = NULL; + + std::map::iterator st = g_sym_name_to_symbol_table.find(sym_name.c_str()); + assert( st != g_sym_name_to_symbol_table.end() ); + symbol_table *symtab = st->second; + + symbol *sym = symtab->lookup(sym_name.c_str()); + assert(sym); + unsigned dst = sym->get_address() + offset; + switch (mem_region.get_type()) { + case const_space: + mem = gpu->get_global_memory(); + mem_name = "const"; + break; + case global_space: + mem = gpu->get_global_memory(); + mem_name = "global"; + break; + default: + abort(); + } + printf("GPGPU-Sim PTX: gpgpu_ptx_sim_memcpy_symbol: copying %s memory %zu bytes %s symbol %s+%zu @0x%x ...\n", + mem_name, count, (to?" to ":"from"), sym_name.c_str(), offset, dst ); + for ( unsigned n=0; n < count; n++ ) { + if( to ) mem->write(dst+n,1,((char*)src)+n,NULL,NULL); + else mem->read(dst+n,1,((char*)src)+n); + } + fflush(stdout); +} + +int g_ptx_sim_mode; // if non-zero run functional simulation only (i.e., no notion of a clock cycle) + +extern int ptx_debug; + +bool g_cuda_launch_blocking = false; + +void read_sim_environment_variables() +{ + ptx_debug = 0; + g_debug_execution = 0; + g_interactive_debugger_enabled = false; + + char *mode = getenv("PTX_SIM_MODE_FUNC"); + if ( mode ) + sscanf(mode,"%u", &g_ptx_sim_mode); + printf("GPGPU-Sim PTX: simulation mode %d (can change with PTX_SIM_MODE_FUNC environment variable:\n", g_ptx_sim_mode); + printf(" 1=functional simulation only, 0=detailed performance simulator)\n"); + char *dbg_inter = getenv("GPGPUSIM_DEBUG"); + if ( dbg_inter && strlen(dbg_inter) ) { + printf("GPGPU-Sim PTX: enabling interactive debugger\n"); + fflush(stdout); + g_interactive_debugger_enabled = true; + } + char *dbg_level = getenv("PTX_SIM_DEBUG"); + if ( dbg_level && strlen(dbg_level) ) { + printf("GPGPU-Sim PTX: setting debug level to %s\n", dbg_level ); + fflush(stdout); + sscanf(dbg_level,"%d", &g_debug_execution); + } + char *dbg_thread = getenv("PTX_SIM_DEBUG_THREAD_UID"); + if ( dbg_thread && strlen(dbg_thread) ) { + printf("GPGPU-Sim PTX: printing debug information for thread uid %s\n", dbg_thread ); + fflush(stdout); + sscanf(dbg_thread,"%d", &g_debug_thread_uid); + } + char *dbg_pc = getenv("PTX_SIM_DEBUG_PC"); + if ( dbg_pc && strlen(dbg_pc) ) { + printf("GPGPU-Sim PTX: printing debug information for instruction with PC = %s\n", dbg_pc ); + fflush(stdout); + sscanf(dbg_pc,"%d", &g_debug_pc); + } + +#if CUDART_VERSION > 1010 + g_override_embedded_ptx = false; + char *usefile = getenv("PTX_SIM_USE_PTX_FILE"); + if (usefile && strlen(usefile)) { + printf("GPGPU-Sim PTX: overriding embedded ptx with ptx file (PTX_SIM_USE_PTX_FILE is set)\n"); + fflush(stdout); + g_override_embedded_ptx = true; + } + char *blocking = getenv("CUDA_LAUNCH_BLOCKING"); + if( blocking && !strcmp(blocking,"1") ) { + g_cuda_launch_blocking = true; + } +#else + g_cuda_launch_blocking = true; + g_override_embedded_ptx = true; +#endif + + if ( g_debug_execution >= 40 ) { + ptx_debug = 1; + } +} + +ptx_cta_info *g_func_cta_info = NULL; + +#define MAX(a,b) (((a)>(b))?(a):(b)) + +/*! +This function simulates the CUDA code functionally, it takes a kernel_info_t parameter +which holds the data for the CUDA kernel to be executed +!*/ +void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL ) +{ + printf("GPGPU-Sim: Performing Functional Simulation, executing kernel %s...\n",kernel.name().c_str()); + + //using a shader core object for book keeping, it is not needed but as most function built for performance simulation need it we use it here + extern gpgpu_sim *g_the_gpu; + //before we execute, we should do PDOM analysis for functional simulation scenario. + function_info *kernel_func_info = kernel.entry(); + if (kernel_func_info->is_pdom_set()) { + printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", kernel.name().c_str() ); + } else { + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", kernel.name().c_str() ); + //kernel_func_info->do_pdom(); + kernel_func_info->set_pdom(); + } + + //we excute the kernel one CTA (Block) at the time, as synchronization functions work block wise + while(!kernel.no_more_ctas_to_run()){ + functionalCoreSim cta( + &kernel, + g_the_gpu, + g_the_gpu->getShaderCoreConfig()->warp_size + ); + cta.execute(); + +#if (CUDART_VERSION >= 5000) + launch_all_device_kernels(); +#endif + } + + //registering this kernel as done + + //openCL kernel simulation calls don't register the kernel so we don't register its exit + if(!openCL) { + extern stream_manager *g_stream_manager; + g_stream_manager->register_finished_kernel(kernel.get_uid()); + } + + //******PRINTING******* + printf( "GPGPU-Sim: Done functional simulation (%u instructions simulated).\n", g_ptx_sim_num_insn ); + if ( gpgpu_ptx_instruction_classification ) { + StatDisp( g_inst_classification_stat[g_ptx_kernel_count]); + StatDisp ( g_inst_op_classification_stat[g_ptx_kernel_count]); + } + + //time_t variables used to calculate the total simulation time + //the start time of simulation is hold by the global variable g_simulation_starttime + //g_simulation_starttime is initilized by gpgpu_ptx_sim_init_perf() in gpgpusim_entrypoint.cc upon starting gpgpu-sim + time_t end_time, elapsed_time, days, hrs, minutes, sec; + end_time = time((time_t *)NULL); + elapsed_time = MAX(end_time - g_simulation_starttime, 1); + + + //calculating and printing simulation time in terms of days, hours, minutes and seconds + days = elapsed_time/(3600*24); + hrs = elapsed_time/3600 - 24*days; + minutes = elapsed_time/60 - 60*(hrs + 24*days); + sec = elapsed_time - 60*(minutes + 60*(hrs + 24*days)); + + fflush(stderr); + printf("\n\ngpgpu_simulation_time = %u days, %u hrs, %u min, %u sec (%u sec)\n", + (unsigned)days, (unsigned)hrs, (unsigned)minutes, (unsigned)sec, (unsigned)elapsed_time ); + printf("gpgpu_simulation_rate = %u (inst/sec)\n", (unsigned)(g_ptx_sim_num_insn / elapsed_time) ); + fflush(stdout); +} + +void functionalCoreSim::initializeCTA() +{ + int ctaLiveThreads=0; + + for(int i=0; i< m_warp_count; i++){ + m_warpAtBarrier[i]=false; + m_liveThreadCount[i]=0; + } + for(int i=0; i< m_warp_count*m_warp_size;i++) + m_thread[i]=NULL; + + //get threads for a cta + for(unsigned i=0; ithreads_per_cta();i++) { + ptx_sim_init_thread(*m_kernel,&m_thread[i],0,i,m_kernel->threads_per_cta()-i,m_kernel->threads_per_cta(),this,0,i/m_warp_size,(gpgpu_t*)m_gpu, true); + assert(m_thread[i]!=NULL && !m_thread[i]->is_done()); + ctaLiveThreads++; + } + + for(int k=0;klaunch(m_thread[warpId*m_warp_size]->get_pc(),initialMask); + m_liveThreadCount[warpId]= liveThreadsCount; +} + +void functionalCoreSim::execute() + { + initializeCTA(); + + //start executing the CTA + while(true){ + bool someOneLive= false; + bool allAtBarrier = true; + for(unsigned i=0;i0) someOneLive=true; + if(!m_warpAtBarrier[i]&& m_liveThreadCount[i]>0) allAtBarrier = false; +} + +unsigned translate_pc_to_ptxlineno(unsigned pc) +{ + // this function assumes that the kernel fits inside a single PTX file + // function_info *pFunc = g_func_info; // assume that the current kernel is the one in query + const ptx_instruction *pInsn = function_info::pc_to_instruction(pc); + unsigned ptx_line_number = pInsn->source_line(); + + return ptx_line_number; +} + +// ptxinfo parser + +extern std::map get_duplicate(); + +int g_ptxinfo_error_detected; + +static char *g_ptxinfo_kname = NULL; +static struct gpgpu_ptx_sim_info g_ptxinfo; +static std::map g_duplicate; +static const char *g_last_dup_type; + +const char *get_ptxinfo_kname() +{ + return g_ptxinfo_kname; +} + +void print_ptxinfo() +{ + if(! get_ptxinfo_kname()){ + printf ("GPGPU-Sim PTX: Binary info : gmem=%u, cmem=%u\n", + g_ptxinfo.gmem, + g_ptxinfo.cmem); + } + if(get_ptxinfo_kname()){ + printf ("GPGPU-Sim PTX: Kernel \'%s\' : regs=%u, lmem=%u, smem=%u, cmem=%u\n", + get_ptxinfo_kname(), + g_ptxinfo.regs, + g_ptxinfo.lmem, + g_ptxinfo.smem, + g_ptxinfo.cmem ); + } +} + + +struct gpgpu_ptx_sim_info get_ptxinfo() +{ + return g_ptxinfo; +} + +std::map get_duplicate() +{ + return g_duplicate; +} + +void ptxinfo_linenum( unsigned linenum ) +{ + g_duplicate[linenum] = g_last_dup_type; +} + +void ptxinfo_dup_type( const char *dup_type ) +{ + g_last_dup_type = dup_type; +} + +void ptxinfo_function(const char *fname ) +{ + clear_ptxinfo(); + g_ptxinfo_kname = strdup(fname); +} + +void ptxinfo_regs( unsigned nregs ) +{ + g_ptxinfo.regs=nregs; +} + +void ptxinfo_lmem( unsigned declared, unsigned system ) +{ + g_ptxinfo.lmem=declared+system; +} + +void ptxinfo_gmem( unsigned declared, unsigned system ) +{ + g_ptxinfo.gmem=declared+system; +} + +void ptxinfo_smem( unsigned declared, unsigned system ) +{ + g_ptxinfo.smem=declared+system; +} + +void ptxinfo_cmem( unsigned nbytes, unsigned bank ) +{ + g_ptxinfo.cmem+=nbytes; +} + +void clear_ptxinfo() +{ + free(g_ptxinfo_kname); + g_ptxinfo_kname=NULL; + g_ptxinfo.regs=0; + g_ptxinfo.lmem=0; + g_ptxinfo.smem=0; + g_ptxinfo.cmem=0; + g_ptxinfo.gmem=0; + g_ptxinfo.ptx_version=0; + g_ptxinfo.sm_target=0; +} + + +void ptxinfo_opencl_addinfo( std::map &kernels ) +{ + + if(! g_ptxinfo_kname) { + printf ("GPGPU-Sim PTX: Binary info : gmem=%u, cmem=%u\n", + g_ptxinfo.gmem, + g_ptxinfo.cmem); + clear_ptxinfo(); + return; + } + + if( !strcmp("__cuda_dummy_entry__",g_ptxinfo_kname) ) { + // this string produced by ptxas for empty ptx files (e.g., bandwidth test) + clear_ptxinfo(); + return; + } + std::map::iterator k=kernels.find(g_ptxinfo_kname); + if( k==kernels.end() ) { + printf ("GPGPU-Sim PTX: ERROR ** implementation for '%s' not found.\n", g_ptxinfo_kname ); + abort(); + } else { + printf ("GPGPU-Sim PTX: Kernel \'%s\' : regs=%u, lmem=%u, smem=%u, cmem=%u\n", + g_ptxinfo_kname, + g_ptxinfo.regs, + g_ptxinfo.lmem, + g_ptxinfo.smem, + g_ptxinfo.cmem ); + function_info *finfo = k->second; + assert(finfo!=NULL); + finfo->set_kernel_info( g_ptxinfo ); + } + clear_ptxinfo(); +} + +struct rec_pts { + gpgpu_recon_t *s_kernel_recon_points; + int s_num_recon; +}; + +struct std::map g_rpts; + +struct rec_pts find_reconvergence_points( function_info *finfo ) +{ + rec_pts tmp; + std::map::iterator r=g_rpts.find(finfo); + + if( r==g_rpts.end() ) { + int num_recon = finfo->get_num_reconvergence_pairs(); + + gpgpu_recon_t *kernel_recon_points = (struct gpgpu_recon_t*) calloc(num_recon, sizeof(struct gpgpu_recon_t)); + finfo->get_reconvergence_pairs(kernel_recon_points); + printf("GPGPU-Sim PTX: reconvergence points for %s...\n", finfo->get_name().c_str() ); + for (int i=0;iprint_insn(); + printf("\n"); + printf("GPGPU-Sim PTX: immediate post dominator @ " ); + if( kernel_recon_points[i].target_inst ) + kernel_recon_points[i].target_inst->print_insn(); + printf("\n"); + } + printf("GPGPU-Sim PTX: ... end of reconvergence points for %s\n", finfo->get_name().c_str() ); + + tmp.s_kernel_recon_points = kernel_recon_points; + tmp.s_num_recon = num_recon; + g_rpts[finfo] = tmp; + } else { + tmp = r->second; + } + return tmp; +} + +address_type get_return_pc( void *thd ) +{ + // function call return + ptx_thread_info *the_thread = (ptx_thread_info*)thd; + assert( the_thread != NULL ); + return the_thread->get_return_PC(); +} + +address_type get_converge_point( address_type pc ) +{ + // the branch could encode the reconvergence point and/or a bit that indicates the + // reconvergence point is the return PC on the call stack in the case the branch has + // no immediate postdominator in the function (i.e., due to multiple return points). + + std::map::iterator f=g_pc_to_finfo.find(pc); + assert( f != g_pc_to_finfo.end() ); + function_info *finfo = f->second; + rec_pts tmp = find_reconvergence_points(finfo); + + int i=0; + for (; i < tmp.s_num_recon; ++i) { + if (tmp.s_kernel_recon_points[i].source_pc == pc) { + if( tmp.s_kernel_recon_points[i].target_pc == (unsigned) -2 ) { + return RECONVERGE_RETURN_PC; + } else { + return tmp.s_kernel_recon_points[i].target_pc; + } + } + } + return NO_BRANCH_DIVERGENCE; +} + +void functionalCoreSim::warp_exit( unsigned warp_id ) +{ + for(int i=0;im_cta_info->register_deleted_thread(m_thread[i]); + delete m_thread[i]; + } + } +} diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 5d97287..0025c52 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1471,7 +1471,12 @@ void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", target_func->get_name().c_str() ); } else { printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", target_func->get_name().c_str() ); - target_func->do_pdom(); + /* + * Some of the instructions like printf() gives the gpgpusim the wrong impression that it is a function call. + * As printf() doesnt have a body like functions do, doing pdom analysis for printf() causes a crash. + */ + if (target_func->get_function_size() >0) + target_func->do_pdom(); target_func->set_pdom(); } diff --git a/src/cuda-sim/instructions.cc~ b/src/cuda-sim/instructions.cc~ new file mode 100644 index 0000000..0e6f530 --- /dev/null +++ b/src/cuda-sim/instructions.cc~ @@ -0,0 +1,4517 @@ +// Copyright (c) 2009-2011, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda, +// Jimmy Kwa, George L. Yuan +// The University of British Columbia +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// Redistributions in binary form must reproduce the above copyright notice, this +// list of conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. +// Neither the name of The University of British Columbia nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#include "instructions.h" +#include "ptx_ir.h" +#include "opcodes.h" +#include "ptx_sim.h" +#include "ptx.tab.h" +#include +#include +#include +#include "cuda-math.h" +#include "../abstract_hardware_model.h" +#include "ptx_loader.h" +#include "cuda_device_printf.h" +#include "../gpgpu-sim/gpu-sim.h" +#include "../gpgpu-sim/shader.h" + +//Jin: include device runtime for CDP +#include "cuda_device_runtime.h" + +#include + +unsigned ptx_instruction::g_num_ptx_inst_uid=0; + +const char *g_opcode_string[NUM_OPCODES] = { +#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, +#include "opcodes.def" +#undef OP_DEF +#undef OP_W_DEF +}; + +void inst_not_implemented( const ptx_instruction * pI ) ; +ptx_reg_t srcOperandModifiers(ptx_reg_t opData, operand_info opInfo, operand_info dstInfo, unsigned type, ptx_thread_info *thread); + +void sign_extend( ptx_reg_t &data, unsigned src_size, const operand_info &dst ); + +void ptx_thread_info::set_reg( const symbol *reg, const ptx_reg_t &value ) +{ + assert( reg != NULL ); + if( reg->name() == "_" ) return; + assert( !m_regs.empty() ); + assert( reg->uid() > 0 ); + m_regs.back()[ reg ] = value; + if (m_enable_debug_trace ) + m_debug_trace_regs_modified.back()[ reg ] = value; + m_last_set_operand_value = value; +} + +ptx_reg_t ptx_thread_info::get_reg( const symbol *reg ) +{ + static bool unfound_register_warned = false; + assert( reg != NULL ); + assert( !m_regs.empty() ); + reg_map_t::iterator regs_iter = m_regs.back().find(reg); + if (regs_iter == m_regs.back().end()) { + assert( reg->type()->get_key().is_reg() ); + const std::string &name = reg->name(); + unsigned call_uid = m_callstack.back().m_call_uid; + ptx_reg_t uninit_reg; + uninit_reg.u32 = 0x0; + set_reg(reg, uninit_reg); // give it a value since we are going to warn the user anyway + std::string file_loc = get_location(); + if( !unfound_register_warned ) { + printf("GPGPU-Sim PTX: WARNING (%s) ** reading undefined register \'%s\' (cuid:%u). Setting to 0X00000000. This is okay if you are simulating the native ISA" + "\n", + file_loc.c_str(), name.c_str(), call_uid ); + unfound_register_warned = true; + } + regs_iter = m_regs.back().find(reg); + } + if (m_enable_debug_trace ) + m_debug_trace_regs_read.back()[ reg ] = regs_iter->second; + return regs_iter->second; +} + +ptx_reg_t ptx_thread_info::get_operand_value( const operand_info &op, operand_info dstInfo, unsigned opType, ptx_thread_info *thread, int derefFlag ) +{ + ptx_reg_t result, tmp; + + + if(op.get_double_operand_type() == 0) { + if(((opType != BB128_TYPE) && (opType != BB64_TYPE) && (opType != FF64_TYPE)) || (op.get_addr_space() != undefined_space)) { + if ( op.is_reg() ) { + result = get_reg( op.get_symbol() ); + } else if ( op.is_builtin()) { + result.u32 = get_builtin( op.get_int(), op.get_addr_offset() ); + } else if(op.is_immediate_address()){ + result.u64 = op.get_addr_offset(); + } else if ( op.is_memory_operand() ) { + // a few options here... + const symbol *sym = op.get_symbol(); + const type_info *type = sym->type(); + const type_info_key &info = type->get_key(); + + if ( info.is_reg() ) { + const symbol *name = op.get_symbol(); + result.u64 = get_reg(name).u64 + op.get_addr_offset(); + } else if ( info.is_param_kernel() ) { + result.u64 = sym->get_address() + op.get_addr_offset(); + } else if ( info.is_param_local() ) { + result.u64 = sym->get_address() + op.get_addr_offset(); + } else if ( info.is_global() ) { + assert( op.get_addr_offset() == 0 ); + result.u64 = sym->get_address(); + } else if ( info.is_local() ) { + result.u64 = sym->get_address() + op.get_addr_offset(); + } else if ( info.is_const() ) { + result.u64 = sym->get_address() + op.get_addr_offset(); + } else if ( op.is_shared() ) { + result.u64 = op.get_symbol()->get_address() + op.get_addr_offset(); + } else { + const char *name = op.name().c_str(); + printf("GPGPU-Sim PTX: ERROR ** get_operand_value : unknown memory operand type for %s\n", name ); + abort(); + } + + } else if ( op.is_literal() ) { + result = op.get_literal_value(); + } else if ( op.is_label() ) { + result.u64 = op.get_symbol()->get_address(); + } else if ( op.is_shared() ) { + result.u64 = op.get_symbol()->get_address(); + } else if ( op.is_const() ) { + result.u64 = op.get_symbol()->get_address(); + } else if ( op.is_global() ) { + result.u64 = op.get_symbol()->get_address(); + } else if ( op.is_local() ) { + result.u64 = op.get_symbol()->get_address(); + } else if ( op.is_function_address() ) { + result.u64 = (size_t)op.get_symbol()->get_pc(); + } else { + const char *name = op.name().c_str(); + printf("GPGPU-Sim PTX: ERROR ** get_operand_value : unknown operand type for %s\n", name ); + assert(0); + } + + if(op.get_operand_lohi() == 1) + result.u64 = result.u64 & 0xFFFF; + else if(op.get_operand_lohi() == 2) + result.u64 = (result.u64>>16) & 0xFFFF; + } else if (opType == BB128_TYPE) { + // b128 + result.u128.lowest = get_reg( op.vec_symbol(0) ).u32; + result.u128.low = get_reg( op.vec_symbol(1) ).u32; + result.u128.high = get_reg( op.vec_symbol(2) ).u32; + result.u128.highest = get_reg( op.vec_symbol(3) ).u32; + } else { + // bb64 or ff64 + result.bits.ls = get_reg( op.vec_symbol(0) ).u32; + result.bits.ms = get_reg( op.vec_symbol(1) ).u32; + } + } else if (op.get_double_operand_type() == 1) { + ptx_reg_t firstHalf, secondHalf; + firstHalf.u64 = get_reg( op.vec_symbol(0) ).u64; + secondHalf.u64 = get_reg( op.vec_symbol(1) ).u64; + if(op.get_operand_lohi() == 1) + secondHalf.u64 = secondHalf.u64 & 0xFFFF; + else if(op.get_operand_lohi() == 2) + secondHalf.u64 = (secondHalf.u64>>16) & 0xFFFF; + result.u64 = firstHalf.u64 + secondHalf.u64; + } else if (op.get_double_operand_type() == 2) { + // s[reg1 += reg2] + // reg1 is incremented after value is returned: the value returned is s[reg1] + ptx_reg_t firstHalf, secondHalf; + firstHalf.u64 = get_reg(op.vec_symbol(0)).u64; + secondHalf.u64 = get_reg(op.vec_symbol(1)).u64; + if(op.get_operand_lohi() == 1) + secondHalf.u64 = secondHalf.u64 & 0xFFFF; + else if(op.get_operand_lohi() == 2) + secondHalf.u64 = (secondHalf.u64>>16) & 0xFFFF; + result.u64 = firstHalf.u64; + firstHalf.u64 = firstHalf.u64 + secondHalf.u64; + set_reg(op.vec_symbol(0),firstHalf); + } else if (op.get_double_operand_type() == 3) { + // s[reg += immediate] + // reg is incremented after value is returned: the value returned is s[reg] + ptx_reg_t firstHalf; + firstHalf.u64 = get_reg(op.get_symbol()).u64; + result.u64 = firstHalf.u64; + firstHalf.u64 = firstHalf.u64 + op.get_addr_offset(); + set_reg(op.get_symbol(),firstHalf); + } + + ptx_reg_t finalResult; + memory_space *mem = NULL; + size_t size=0; + int t=0; + finalResult.u64=0; + + //complete other cases for reading from memory, such as reading from other const memory + if((op.get_addr_space() == global_space)&&(derefFlag)) { + // global memory - g[4], g[$r0] + mem = thread->get_global_memory(); + type_info_key::type_decode(opType,size,t); + mem->read(result.u32,size/8,&finalResult.u128); + thread->m_last_effective_address = result.u32; + thread->m_last_memory_space = global_space; + + if( opType == S16_TYPE || opType == S32_TYPE ) + sign_extend(finalResult,size,dstInfo); + } else if((op.get_addr_space() == shared_space)&&(derefFlag)) { + // shared memory - s[4], s[$r0] + mem = thread->m_shared_mem; + type_info_key::type_decode(opType,size,t); + mem->read(result.u32,size/8,&finalResult.u128); + thread->m_last_effective_address = result.u32; + thread->m_last_memory_space = shared_space; + + if( opType == S16_TYPE || opType == S32_TYPE ) + sign_extend(finalResult,size,dstInfo); + } else if((op.get_addr_space() == const_space)&&(derefFlag)) { + // const memory - ce0c1[4], ce0c1[$r0] + mem = thread->get_global_memory(); + type_info_key::type_decode(opType,size,t); + mem->read((result.u32 + op.get_const_mem_offset()),size/8,&finalResult.u128); + thread->m_last_effective_address = result.u32; + thread->m_last_memory_space = const_space; + if( opType == S16_TYPE || opType == S32_TYPE ) + sign_extend(finalResult,size,dstInfo); + } else if((op.get_addr_space() == local_space)&&(derefFlag)) { + // local memory - l0[4], l0[$r0] + mem = thread->m_local_mem; + type_info_key::type_decode(opType,size,t); + mem->read(result.u32,size/8,&finalResult.u128); + thread->m_last_effective_address = result.u32; + thread->m_last_memory_space = local_space; + if( opType == S16_TYPE || opType == S32_TYPE ) + sign_extend(finalResult,size,dstInfo); + } else { + finalResult = result; + } + + if((op.get_operand_neg() == true)&&(derefFlag)) { + switch( opType ) { + // Default to f32 for now, need to add support for others + case S8_TYPE: + case U8_TYPE: + case B8_TYPE: + finalResult.s8 = -finalResult.s8; + break; + case S16_TYPE: + case U16_TYPE: + case B16_TYPE: + finalResult.s16 = -finalResult.s16; + break; + case S32_TYPE: + case U32_TYPE: + case B32_TYPE: + finalResult.s32 = -finalResult.s32; + break; + case S64_TYPE: + case U64_TYPE: + case B64_TYPE: + finalResult.s64 = -finalResult.s64; + break; + case F16_TYPE: + finalResult.f16 = -finalResult.f16; + break; + case F32_TYPE: + finalResult.f32 = -finalResult.f32; + break; + case F64_TYPE: + case FF64_TYPE: + finalResult.f64 = -finalResult.f64; + break; + default: + assert(0); + } + + } + + return finalResult; + +} + +unsigned get_operand_nbits( const operand_info &op ) +{ + if ( op.is_reg() ) { + const symbol *sym = op.get_symbol(); + const type_info *typ = sym->type(); + type_info_key t = typ->get_key(); + switch( t.scalar_type() ) { + case PRED_TYPE: + return 1; + case B8_TYPE: case S8_TYPE: case U8_TYPE: + return 8; + case S16_TYPE: case U16_TYPE: case F16_TYPE: case B16_TYPE: + return 16; + case S32_TYPE: case U32_TYPE: case F32_TYPE: case B32_TYPE: + return 32; + case S64_TYPE: case U64_TYPE: case F64_TYPE: case B64_TYPE: + return 64; + default: + printf("ERROR: unknown register type\n"); + fflush(stdout); + abort(); + } + } else { + printf("ERROR: Need to implement get_operand_nbits() for currently unsupported operand_info type\n"); + fflush(stdout); + abort(); + } + + return 0; +} + +void ptx_thread_info::get_vector_operand_values( const operand_info &op, ptx_reg_t* ptx_regs, unsigned num_elements ) +{ + assert( op.is_vector() ); + assert( num_elements <= 4 ); // max 4 elements in a vector + + for (int idx = num_elements - 1; idx >= 0; --idx) { + const symbol *sym = NULL; + sym = op.vec_symbol(idx); + if( strcmp(sym->name().c_str(),"_") != 0) { + reg_map_t::iterator reg_iter = m_regs.back().find(sym); + assert( reg_iter != m_regs.back().end() ); + ptx_regs[idx] = reg_iter->second; + } + } +} + +void sign_extend( ptx_reg_t &data, unsigned src_size, const operand_info &dst ) +{ + if( !dst.is_reg() ) + return; + unsigned dst_size = get_operand_nbits( dst ); + if( src_size >= dst_size ) + return; + // src_size < dst_size + unsigned long long mask = 1; + mask <<= (src_size-1); + if( (mask & data.u64) == 0 ) { + // no need to sign extend + return; + } + // need to sign extend + mask = 1; + mask <<= dst_size-src_size; + mask -= 1; + mask <<= src_size; + data.u64 |= mask; +} + +void ptx_thread_info::set_operand_value( const operand_info &dst, const ptx_reg_t &data, unsigned type, ptx_thread_info *thread, const ptx_instruction *pI, int overflow, int carry ) +{ + thread->set_operand_value( dst, data, type, thread, pI ); + + if (dst.get_double_operand_type() == -2) + { + ptx_reg_t predValue; + + const symbol *sym = dst.vec_symbol(0); + predValue.u64 = (m_regs.back()[ sym ].u64) & ~(0x0C); + predValue.u64 |= ((overflow & 0x01)<<3); + predValue.u64 |= ((carry & 0x01)<<2); + + set_reg(sym,predValue); + } + else if (dst.get_double_operand_type() == 0) + { + //intentionally do nothing + } + else + { + printf("Unexpected double destination\n"); + assert(0); + } + +} + +void ptx_thread_info::set_operand_value( const operand_info &dst, const ptx_reg_t &data, unsigned type, ptx_thread_info *thread, const ptx_instruction *pI ) +{ + ptx_reg_t dstData; + memory_space *mem = NULL; + size_t size; + int t; + + type_info_key::type_decode(type,size,t); + + /*complete this section for other cases*/ + if(dst.get_addr_space() == undefined_space) + { + ptx_reg_t setValue; + setValue.u64 = data.u64; + + // Double destination in set instruction ($p0|$p1) - second is negation of first + if (dst.get_double_operand_type() == -1) + { + ptx_reg_t setValue2; + const symbol *name1 = dst.vec_symbol(0); + const symbol *name2 = dst.vec_symbol(1); + + if ( (type==F16_TYPE)||(type==F32_TYPE)||(type==F64_TYPE)||(type==FF64_TYPE) ) { + setValue2.f32 = (setValue.u64==0)?1.0f:0.0f; + } else { + setValue2.u32 = (setValue.u64==0)?0xFFFFFFFF:0; + } + + set_reg(name1,setValue); + set_reg(name2,setValue2); + } + + // Double destination in cvt,shr,mul,etc. instruction ($p0|$r4) - second register operand receives data, first predicate operand + // is set as $p0=($r4!=0) + // Also for Double destination in set instruction ($p0/$r1) + else if ((dst.get_double_operand_type() == -2)||(dst.get_double_operand_type() == -3)) + { + ptx_reg_t predValue; + const symbol *predName = dst.vec_symbol(0); + const symbol *regName = dst.vec_symbol(1); + predValue.u64 = 0; + + switch ( type ) { + case S8_TYPE: + if((setValue.s8 & 0x7F) == 0) + predValue.u64 |= 1; + break; + case S16_TYPE: + if((setValue.s16 & 0x7FFF) == 0) + predValue.u64 |= 1; + break; + case S32_TYPE: + if((setValue.s32 & 0x7FFFFFFF) == 0) + predValue.u64 |= 1; + break; + case S64_TYPE: + if((setValue.s64 & 0x7FFFFFFFFFFFFFFF) == 0) + predValue.u64 |= 1; + break; + case U8_TYPE: + case B8_TYPE: + if(setValue.u8 == 0) + predValue.u64 |= 1; + break; + case U16_TYPE: + case B16_TYPE: + if(setValue.u16 == 0) + predValue.u64 |= 1; + break; + case U32_TYPE: + case B32_TYPE: + if(setValue.u32 == 0) + predValue.u64 |= 1; + break; + case U64_TYPE: + case B64_TYPE: + if(setValue.u64 == 0) + predValue.u64 |= 1; + break; + case F16_TYPE: + if(setValue.f16 == 0) + predValue.u64 |= 1; + break; + case F32_TYPE: + if(setValue.f32 == 0) + predValue.u64 |= 1; + break; + case F64_TYPE: + case FF64_TYPE: + if(setValue.f64 == 0) + predValue.u64 |= 1; + break; + default: assert(0); break; + } + + + if ( (type==S8_TYPE)||(type==S16_TYPE)||(type==S32_TYPE)||(type==S64_TYPE)|| + (type==U8_TYPE)||(type==U16_TYPE)||(type==U32_TYPE)||(type==U64_TYPE)|| + (type==B8_TYPE)||(type==B16_TYPE)||(type==B32_TYPE)||(type==B64_TYPE)) { + if((setValue.u32 & (1<<(size-1))) != 0) + predValue.u64 |= 1<<1; + } + if ( type==F32_TYPE ) { + if(setValue.f32 < 0) + predValue.u64 |= 1<<1; + } + + if(dst.get_operand_lohi() == 1) + { + setValue.u64 = ((m_regs.back()[ regName ].u64) & (~(0xFFFF))) + (data.u64 & 0xFFFF); + } + else if(dst.get_operand_lohi() == 2) + { + setValue.u64 = ((m_regs.back()[ regName ].u64) & (~(0xFFFF0000))) + ((data.u64<<16) & 0xFFFF0000); + } + + set_reg(predName,predValue); + set_reg(regName,setValue); + } + else if (type == BB128_TYPE) + { + //b128 stuff here. + ptx_reg_t setValue2, setValue3, setValue4; + setValue.u64 = 0; + setValue2.u64 = 0; + setValue3.u64 = 0; + setValue4.u64 = 0; + setValue.u32 = data.u128.lowest; + setValue2.u32 = data.u128.low; + setValue3.u32 = data.u128.high; + setValue4.u32 = data.u128.highest; + + const symbol *name1, *name2, *name3, *name4 = NULL; + + name1 = dst.vec_symbol(0); + name2 = dst.vec_symbol(1); + name3 = dst.vec_symbol(2); + name4 = dst.vec_symbol(3); + + set_reg(name1,setValue); + set_reg(name2,setValue2); + set_reg(name3,setValue3); + set_reg(name4,setValue4); + } + else if (type == BB64_TYPE || type == FF64_TYPE) + { + //ptxplus version of storing 64 bit values to registers stores to two adjacent registers + ptx_reg_t setValue2; + setValue.u32 = 0; + setValue2.u32 = 0; + + setValue.u32 = data.bits.ls; + setValue2.u32 = data.bits.ms; + + const symbol *name1, *name2 = NULL; + + name1 = dst.vec_symbol(0); + name2 = dst.vec_symbol(1); + + set_reg(name1,setValue); + set_reg(name2,setValue2); + } + else + { + if(dst.get_operand_lohi() == 1) + { + setValue.u64 = ((m_regs.back()[ dst.get_symbol() ].u64) & (~(0xFFFF))) + (data.u64 & 0xFFFF); + } + else if(dst.get_operand_lohi() == 2) + { + setValue.u64 = ((m_regs.back()[ dst.get_symbol() ].u64) & (~(0xFFFF0000))) + ((data.u64<<16) & 0xFFFF0000); + } + set_reg(dst.get_symbol(),setValue); + } + } + + // global memory - g[4], g[$r0] + else if(dst.get_addr_space() == global_space) + { + dstData = thread->get_operand_value(dst, dst, type, thread, 0); + mem = thread->get_global_memory(); + type_info_key::type_decode(type,size,t); + + mem->write(dstData.u32,size/8,&data.u128,thread,pI); + thread->m_last_effective_address = dstData.u32; + thread->m_last_memory_space = global_space; + } + + // shared memory - s[4], s[$r0] + else if(dst.get_addr_space() == shared_space) + { + dstData = thread->get_operand_value(dst, dst, type, thread, 0); + mem = thread->m_shared_mem; + type_info_key::type_decode(type,size,t); + + mem->write(dstData.u32,size/8,&data.u128,thread,pI); + thread->m_last_effective_address = dstData.u32; + thread->m_last_memory_space = shared_space; + } + + // local memory - l0[4], l0[$r0] + else if(dst.get_addr_space() == local_space) + { + dstData = thread->get_operand_value(dst, dst, type, thread, 0); + mem = thread->m_local_mem; + type_info_key::type_decode(type,size,t); + + mem->write(dstData.u32,size/8,&data.u128,thread,pI); + thread->m_last_effective_address = dstData.u32; + thread->m_last_memory_space = local_space; + } + + else + { + printf("Destination stores to unknown location."); + assert(0); + } + + +} + +void ptx_thread_info::set_vector_operand_values( const operand_info &dst, + const ptx_reg_t &data1, + const ptx_reg_t &data2, + const ptx_reg_t &data3, + const ptx_reg_t &data4 ) +{ + unsigned num_elements = dst.get_vect_nelem(); + if (num_elements > 0) { + set_reg(dst.vec_symbol(0), data1); + if (num_elements > 1) { + set_reg(dst.vec_symbol(1), data2); + if (num_elements > 2) { + set_reg(dst.vec_symbol(2), data3); + if (num_elements > 3) { + set_reg(dst.vec_symbol(3), data4); + } + } + } + } + + m_last_set_operand_value = data1; +} + +#define my_abs(a) (((a)<0)?(-a):(a)) + +#define MY_MAX_I(a,b) (a > b) ? a : b +#define MY_MAX_F(a,b) isNaN(a) ? b : isNaN(b) ? a : (a > b) ? a : b + +#define MY_MIN_I(a,b) (a < b) ? a : b +#define MY_MIN_F(a,b) isNaN(a) ? b : isNaN(b) ? a : (a < b) ? a : b + +#define MY_INC_I(a,b) (a >= b) ? 0 : a+1 +#define MY_DEC_I(a,b) ((a == 0) || (a > b)) ? b : a-1 + +#define MY_CAS_I(a,b,c) (a == b) ? c : a + +#define MY_EXCH(a,b) b + +void abs_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case S16_TYPE: d.s16 = my_abs(a.s16); break; + case S32_TYPE: d.s32 = my_abs(a.s32); break; + case S64_TYPE: d.s64 = my_abs(a.s64); break; + case U16_TYPE: d.s16 = my_abs(a.u16); break; + case U32_TYPE: d.s32 = my_abs(a.u32); break; + case U64_TYPE: d.s64 = my_abs(a.u64); break; + case F32_TYPE: d.f32 = my_abs(a.f32); break; + case F64_TYPE: case FF64_TYPE: d.f64 = my_abs(a.f64); break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void addp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + //PTXPlus add instruction with carry (carry is kept in a predicate) register + ptx_reg_t src1_data, src2_data, src3_data, data; + int overflow = 0; + int carry = 0; + + const operand_info &dst = pI->dst(); //get operand info of sources and destination + const operand_info &src1 = pI->src1(); //use them to determine that they are of type 'register' + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + src3_data = thread->get_operand_value(src3, dst, i_type, thread, 1); + + unsigned rounding_mode = pI->rounding_mode(); + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + + //performs addition. Sets carry and overflow if needed. + //src3_data.pred&0x4 is the carry flag + switch ( i_type ) { + case S8_TYPE: + data.s64 = (src1_data.s64 & 0x0000000FF) + (src2_data.s64 & 0x0000000FF) + (src3_data.pred & 0x4); + if(((src1_data.s64 & 0x80)-(src2_data.s64 & 0x80)) == 0) {overflow=((src1_data.s64 & 0x80)-(data.s64 & 0x80))==0?0:1; } + carry = (data.u64 & 0x000000100)>>8; + break; + case S16_TYPE: + data.s64 = (src1_data.s64 & 0x00000FFFF) + (src2_data.s64 & 0x00000FFFF) + (src3_data.pred & 0x4); + if(((src1_data.s64 & 0x8000)-(src2_data.s64 & 0x8000)) == 0) {overflow=((src1_data.s64 & 0x8000)-(data.s64 & 0x8000))==0?0:1; } + carry = (data.u64 & 0x000010000)>>16; + break; + case S32_TYPE: + data.s64 = (src1_data.s64 & 0x0FFFFFFFF) + (src2_data.s64 & 0x0FFFFFFFF) + (src3_data.pred & 0x4); + if(((src1_data.s64 & 0x80000000)-(src2_data.s64 & 0x80000000)) == 0) {overflow=((src1_data.s64 & 0x80000000)-(data.s64 & 0x80000000))==0?0:1; } + carry = (data.u64 & 0x100000000)>>32; + break; + case S64_TYPE: + data.s64 = src1_data.s64 + src2_data.s64 + (src3_data.pred & 0x4); + break; + case U8_TYPE: + data.u64 = (src1_data.u64 & 0xFF) + (src2_data.u64 & 0xFF) + (src3_data.pred & 0x4); + carry = (data.u64 & 0x100)>>8; + break; + case U16_TYPE: + data.u64 = (src1_data.u64 & 0xFFFF) + (src2_data.u64 & 0xFFFF) + (src3_data.pred & 0x4); + carry = (data.u64 & 0x10000)>>16; + break; + case U32_TYPE: + data.u64 = (src1_data.u64 & 0xFFFFFFFF) + (src2_data.u64 & 0xFFFFFFFF) + (src3_data.pred & 0x4); + carry = (data.u64 & 0x100000000)>>32; + break; + case U64_TYPE: + data.s64 = src1_data.s64 + src2_data.s64 + (src3_data.pred & 0x4); + break; + case F16_TYPE: assert(0); break; + case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break; + case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break; + default: assert(0); break; + } + fesetround( orig_rm ); + + thread->set_operand_value(dst, data, i_type, thread, pI, overflow, carry ); +} + +void add_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + int overflow = 0; + int carry = 0; + + const operand_info &dst = pI->dst(); //get operand info of sources and destination + const operand_info &src1 = pI->src1(); //use them to determine that they are of type 'register' + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + unsigned rounding_mode = pI->rounding_mode(); + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + + //performs addition. Sets carry and overflow if needed. + switch ( i_type ) { + case S8_TYPE: + data.s64 = (src1_data.s64 & 0x0000000FF) + (src2_data.s64 & 0x0000000FF); + if(((src1_data.s64 & 0x80)-(src2_data.s64 & 0x80)) == 0) {overflow=((src1_data.s64 & 0x80)-(data.s64 & 0x80))==0?0:1; } + carry = (data.u64 & 0x000000100)>>8; + break; + case S16_TYPE: + data.s64 = (src1_data.s64 & 0x00000FFFF) + (src2_data.s64 & 0x00000FFFF); + if(((src1_data.s64 & 0x8000)-(src2_data.s64 & 0x8000)) == 0) {overflow=((src1_data.s64 & 0x8000)-(data.s64 & 0x8000))==0?0:1; } + carry = (data.u64 & 0x000010000)>>16; + break; + case S32_TYPE: + data.s64 = (src1_data.s64 & 0x0FFFFFFFF) + (src2_data.s64 & 0x0FFFFFFFF); + if(((src1_data.s64 & 0x80000000)-(src2_data.s64 & 0x80000000)) == 0) {overflow=((src1_data.s64 & 0x80000000)-(data.s64 & 0x80000000))==0?0:1; } + carry = (data.u64 & 0x100000000)>>32; + break; + case S64_TYPE: + data.s64 = src1_data.s64 + src2_data.s64; + break; + case U8_TYPE: + data.u64 = (src1_data.u64 & 0xFF) + (src2_data.u64 & 0xFF); + carry = (data.u64 & 0x100)>>8; + break; + case U16_TYPE: + data.u64 = (src1_data.u64 & 0xFFFF) + (src2_data.u64 & 0xFFFF); + carry = (data.u64 & 0x10000)>>16; + break; + case U32_TYPE: + data.u64 = (src1_data.u64 & 0xFFFFFFFF) + (src2_data.u64 & 0xFFFFFFFF); + carry = (data.u64 & 0x100000000)>>32; + break; + case U64_TYPE: + data.u64 = src1_data.u64 + src2_data.u64; + break; + case F16_TYPE: assert(0); break; + case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break; + case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break; + default: assert(0); break; + } + fesetround( orig_rm ); + + thread->set_operand_value(dst, data, i_type, thread, pI, overflow, carry ); +} + +void addc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } + +void and_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + //the way ptxplus handles predicates: 1 = false and 0 = true + if(i_type == PRED_TYPE) + data.pred = ~(~(src1_data.pred) & ~(src2_data.pred)); + else + data.u64 = src1_data.u64 & src2_data.u64; + + thread->set_operand_value(dst,data, i_type, thread, pI); +} + +void andn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + switch ( i_type ) { + case B16_TYPE: src2_data.u16 = ~src2_data.u16; break; + case B32_TYPE: src2_data.u32 = ~src2_data.u32; break; + case B64_TYPE: src2_data.u64 = ~src2_data.u64; break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + data.u64 = src1_data.u64 & src2_data.u64; + + thread->set_operand_value(dst,data, i_type, thread, pI); +} + +void bar_callback( const inst_t* inst, ptx_thread_info* thread) +{ + unsigned ctaid = thread->get_cta_uid(); + unsigned barid = inst->bar_id; + unsigned value = thread->get_reduction_value(ctaid,barid); + const ptx_instruction *pI = dynamic_cast(inst); + const operand_info &dst = pI->dst(); + ptx_reg_t data; + data.u32 = value; + thread->set_operand_value(dst,value, U32_TYPE, thread, pI); +} + +void atom_callback( const inst_t* inst, ptx_thread_info* thread) +{ + const ptx_instruction *pI = dynamic_cast(inst); + + // "Decode" the output type + unsigned to_type = pI->get_type(); + size_t size; + int t; + type_info_key::type_decode(to_type, size, t); + + // Set up operand variables + ptx_reg_t data; // d + ptx_reg_t src1_data; // a + ptx_reg_t src2_data; // b + ptx_reg_t op_result; // temp variable to hold operation result + + bool data_ready = false; + + // Get operand info of sources and destination + const operand_info &dst = pI->dst(); // d + const operand_info &src1 = pI->src1(); // a + const operand_info &src2 = pI->src2(); // b + + // Get operand values + src1_data = thread->get_operand_value(src1, src1, to_type, thread, 1); // a + if (dst.get_symbol()->type()){ + src2_data = thread->get_operand_value(src2, dst, to_type, thread, 1); // b + } else { + //This is the case whent he first argument (dest) is '_' + src2_data = thread->get_operand_value(src2, src1, to_type, thread, 1); // b + } + + // Check state space + addr_t effective_address = src1_data.u64; + memory_space_t space = pI->get_space(); + if (space == undefined_space) { + // generic space - determine space via address + if( whichspace(effective_address) == global_space ) { + effective_address = generic_to_global(effective_address); + space = global_space; + } else if( whichspace(effective_address) == shared_space ) { + unsigned smid = thread->get_hw_sid(); + effective_address = generic_to_shared(smid,effective_address); + space = shared_space; + } else { + abort(); + } + } + assert( space == global_space || space == shared_space ); + + memory_space *mem = NULL; + if(space == global_space) + mem = thread->get_global_memory(); + else if(space == shared_space) + mem = thread->m_shared_mem; + else + abort(); + + // Copy value pointed to in operand 'a' into register 'd' + // (i.e. copy src1_data to dst) + mem->read(effective_address,size/8,&data.s64); + if (dst.get_symbol()->type()){ + thread->set_operand_value(dst, data, to_type, thread, pI); // Write value into register 'd' + } + + // Get the atomic operation to be performed + unsigned m_atomic_spec = pI->get_atomic(); + + switch ( m_atomic_spec ) { + // AND + case ATOMIC_AND: + { + + switch ( to_type ) { + case B32_TYPE: + case U32_TYPE: + op_result.u32 = data.u32 & src2_data.u32; + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = data.s32 & src2_data.s32; + data_ready = true; + break; + default: + printf("Execution error: type mismatch (%x) with instruction\natom.AND only accepts b32\n", to_type); + assert(0); + break; + } + + break; + } + // OR + case ATOMIC_OR: + { + + switch ( to_type ) { + case B32_TYPE: + case U32_TYPE: + op_result.u32 = data.u32 | src2_data.u32; + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = data.s32 | src2_data.s32; + data_ready = true; + break; + default: + printf("Execution error: type mismatch (%x) with instruction\natom.OR only accepts b32\n", to_type); + assert(0); + break; + } + + break; + } + // XOR + case ATOMIC_XOR: + { + + switch ( to_type ) { + case B32_TYPE: + case U32_TYPE: + op_result.u32 = data.u32 ^ src2_data.u32; + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = data.s32 ^ src2_data.s32; + data_ready = true; + break; + default: + printf("Execution error: type mismatch (%x) with instruction\natom.XOR only accepts b32\n", to_type); + assert(0); + break; + } + + break; + } + // CAS + case ATOMIC_CAS: + { + + ptx_reg_t src3_data; + const operand_info &src3 = pI->src3(); + src3_data = thread->get_operand_value(src3, dst, to_type, thread, 1); + + switch ( to_type ) { + case B32_TYPE: + case U32_TYPE: + op_result.u32 = MY_CAS_I(data.u32, src2_data.u32, src3_data.u32); + data_ready = true; + break; + case B64_TYPE: + case U64_TYPE: + op_result.u64 = MY_CAS_I(data.u64, src2_data.u64, src3_data.u64); + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = MY_CAS_I(data.s32, src2_data.s32, src3_data.s32); + data_ready = true; + break; + default: + printf("Execution error: type mismatch (%x) with instruction\natom.CAS only accepts b32 and b64\n", to_type); + assert(0); + break; + } + + break; + } + // EXCH + case ATOMIC_EXCH: + { + switch ( to_type ) { + case B32_TYPE: + case U32_TYPE: + op_result.u32 = MY_EXCH(data.u32, src2_data.u32); + data_ready = true; + break; + case B64_TYPE: + case U64_TYPE: + op_result.u64 = MY_EXCH(data.u64, src2_data.u64); + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = MY_EXCH(data.s32, src2_data.s32); + data_ready = true; + break; + default: + printf("Execution error: type mismatch (%x) with instruction\natom.EXCH only accepts b32\n", to_type); + assert(0); + break; + } + + break; + } + // ADD + case ATOMIC_ADD: + { + + switch ( to_type ) { + case U32_TYPE: + op_result.u32 = data.u32 + src2_data.u32; + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = data.s32 + src2_data.s32; + data_ready = true; + break; + case U64_TYPE: + op_result.u64 = data.u64 + src2_data.u64; + data_ready = true; + break; + case F32_TYPE: + op_result.f32 = data.f32 + src2_data.f32; + data_ready = true; + break; + default: + printf("Execution error: type mismatch with instruction\natom.ADD only accepts u32, s32, u64, and f32\n"); + assert(0); + break; + } + + break; + } + // INC + case ATOMIC_INC: + { + switch ( to_type ) { + case U32_TYPE: + op_result.u32 = MY_INC_I(data.u32, src2_data.u32); + data_ready = true; + break; + default: + printf("Execution error: type mismatch with instruction\natom.INC only accepts u32 and s32\n"); + assert(0); + break; + } + + break; + } + // DEC + case ATOMIC_DEC: + { + switch ( to_type ) { + case U32_TYPE: + op_result.u32 = MY_DEC_I(data.u32, src2_data.u32); + data_ready = true; + break; + default: + printf("Execution error: type mismatch with instruction\natom.DEC only accepts u32 and s32\n"); + assert(0); + break; + } + + break; + } + // MIN + case ATOMIC_MIN: + { + switch ( to_type ) { + case U32_TYPE: + op_result.u32 = MY_MIN_I(data.u32, src2_data.u32); + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = MY_MIN_I(data.s32, src2_data.s32); + data_ready = true; + break; + default: + printf("Execution error: type mismatch with instruction\natom.MIN only accepts u32 and s32\n"); + assert(0); + break; + } + + break; + } + // MAX + case ATOMIC_MAX: + { + switch ( to_type ) { + case U32_TYPE: + op_result.u32 = MY_MAX_I(data.u32, src2_data.u32); + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = MY_MAX_I(data.s32, src2_data.s32); + data_ready = true; + break; + default: + printf("Execution error: type mismatch with instruction\natom.MAX only accepts u32 and s32\n"); + assert(0); + break; + } + + break; + } + // DEFAULT + default: + { + assert(0); + break; + } + } + + // Write operation result into memory + // (i.e. copy src1_data to dst) + if ( data_ready ) { + mem->write(effective_address,size/8,&op_result.s64,thread,pI); + } else { + printf("Execution error: data_ready not set\n"); + assert(0); + } +} + +// atom_impl will now result in a callback being called in mem_ctrl_pop (gpu-sim.c) +void atom_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + // SYNTAX + // atom.space.operation.type d, a, b[, c]; (now read in callback) + + // obtain memory space of the operation + memory_space_t space = pI->get_space(); + + // get the memory address + const operand_info &src1 = pI->src1(); + // const operand_info &dst = pI->dst(); // not needed for effective address calculation + unsigned i_type = pI->get_type(); + ptx_reg_t src1_data; + src1_data = thread->get_operand_value(src1, src1, i_type, thread, 1); + addr_t effective_address = src1_data.u64; + + addr_t effective_address_final; + + // handle generic memory space by converting it to global + if ( space == undefined_space ) { + if( whichspace(effective_address) == global_space ) { + effective_address_final = generic_to_global(effective_address); + space = global_space; + } else if( whichspace(effective_address) == shared_space ) { + unsigned smid = thread->get_hw_sid(); + effective_address_final = generic_to_shared(smid,effective_address); + space = shared_space; + } else { + abort(); + } + } else { + assert( space == global_space || space == shared_space ); + effective_address_final = effective_address; + } + + // Check state space + assert( space == global_space || space == shared_space ); + + thread->m_last_effective_address = effective_address_final; + thread->m_last_memory_space = space; + thread->m_last_dram_callback.function = atom_callback; + thread->m_last_dram_callback.instruction = pI; +} + +void bar_impl( const ptx_instruction *pIin, ptx_thread_info *thread ) +{ + ptx_instruction * pI = const_cast(pIin); + unsigned bar_op = pI->barrier_op(); + unsigned red_op = pI->get_atomic(); + unsigned ctaid = thread->get_cta_uid(); + + switch(bar_op){ + case SYNC_OPTION: + { + if(pI->get_num_operands()>1){ + const operand_info &op0 = pI->dst(); + const operand_info &op1 = pI->src1(); + ptx_reg_t op0_data; + ptx_reg_t op1_data; + op0_data = thread->get_operand_value(op0, op0, U32_TYPE, thread, 1); + op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); + pI->set_bar_id(op0_data.u32); + pI->set_bar_count(op1_data.u32); + }else{ + const operand_info &op0 = pI->dst(); + ptx_reg_t op0_data; + op0_data = thread->get_operand_value(op0, op0, U32_TYPE, thread, 1); + pI->set_bar_id(op0_data.u32); + } + break; + } + case ARRIVE_OPTION: + { + const operand_info &op0 = pI->dst(); + const operand_info &op1 = pI->src1(); + ptx_reg_t op0_data; + ptx_reg_t op1_data; + op0_data = thread->get_operand_value(op0, op0, U32_TYPE, thread, 1); + op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); + pI->set_bar_id(op0_data.u32); + pI->set_bar_count(op1_data.u32); + break; + } + case RED_OPTION: + { + if(pI->get_num_operands()>3){ + const operand_info &op1 = pI->src1(); + const operand_info &op2 = pI->src2(); + const operand_info &op3 = pI->src3(); + ptx_reg_t op1_data; + ptx_reg_t op2_data; + ptx_reg_t op3_data; + op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); + op2_data = thread->get_operand_value(op2, op2, U32_TYPE, thread, 1); + op3_data = thread->get_operand_value(op3, op3, PRED_TYPE, thread, 1); + op3_data.u32=!(op3_data.pred & 0x0001); + pI->set_bar_id(op1_data.u32); + pI->set_bar_count(op2_data.u32); + switch(red_op){ + case ATOMIC_POPC: + thread->popc_reduction(ctaid,op1_data.u32,op3_data.u32); + break; + case ATOMIC_AND: + thread->and_reduction(ctaid,op1_data.u32,op3_data.u32); + break; + case ATOMIC_OR: + thread->or_reduction(ctaid,op1_data.u32,op3_data.u32); + break; + default: + abort(); + break; + } + }else{ + const operand_info &op1 = pI->src1(); + const operand_info &op2 = pI->src2(); + ptx_reg_t op1_data; + ptx_reg_t op2_data; + op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); + op2_data = thread->get_operand_value(op2, op2, PRED_TYPE, thread, 1); + op2_data.u32=!(op2_data.pred & 0x0001); + pI->set_bar_id(op1_data.u32); + switch(red_op){ + case ATOMIC_POPC: + thread->popc_reduction(ctaid,op1_data.u32,op2_data.u32); + break; + case ATOMIC_AND: + thread->and_reduction(ctaid,op1_data.u32,op2_data.u32); + break; + case ATOMIC_OR: + thread->or_reduction(ctaid,op1_data.u32,op2_data.u32); + break; + default: + abort(); + break; + } + } + break; + } + default: + abort(); + break; + } + + thread->m_last_dram_callback.function = bar_callback; + thread->m_last_dram_callback.instruction = pIin; +} + +void bfe_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + unsigned i_type = pI->get_type(); + unsigned msb = (i_type == U32_TYPE || i_type == S32_TYPE) ? 31 : 63; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); + ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); + ptx_reg_t c = thread->get_operand_value(src3, dst, i_type, thread, 1); + unsigned pos = b.u32 & 0xFF; + unsigned len = c.u32 & 0xFF; + unsigned d = 0; + switch (i_type) + { + case U32_TYPE: + { + unsigned mask; + d = a.u32 >> pos; + mask = 0xFFFFFFFF >> (32 - len); + d &= mask; + break; + } + case U64_TYPE: + { + unsigned long mask; + d = a.u64 >> pos; + mask = 0xFFFFFFFFFFFFFFFF >> (64 - len); + d &= mask; + break; + } + case S32_TYPE: + { + unsigned mask; + unsigned min = MY_MIN_I(pos + len - 1, msb); + unsigned sbit = len == 0 ? 0 : (a.s32 >> min) & 0x1; + d = a.s32 >> pos; + if (sbit > 0) + { + mask = 0xFFFFFFFF << len; + d |= mask; + } + else + { + mask = 0xFFFFFFFF >> (32 - len); + d &= mask; + } + break; + } + case S64_TYPE: + { + unsigned long mask; + unsigned min = MY_MIN_I(pos + len - 1, msb); + unsigned sbit = len == 0 ? 0 : (a.s64 >> min) & 0x1; + d = a.s64 >> pos; + if (sbit > 0) + { + mask = 0xFFFFFFFFFFFFFFFF << len; + d |= mask; + } + else + { + mask = 0xFFFFFFFFFFFFFFFF >> (64 - len); + d &= mask; + } + break; + } + default: + printf("Operand type not supported for BFE instruction.\n"); + abort(); + return; + } + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void bfi_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void bfind_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } + +void bra_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &target = pI->dst(); + ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); + + thread->m_branch_taken = true; + thread->set_npc(target_pc); +} + +void brx_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &target = pI->dst(); + ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); + + thread->m_branch_taken = true; + thread->set_npc(target_pc); +} + +void break_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &target = thread->pop_breakaddr(); + ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); + + thread->m_branch_taken = true; + thread->set_npc(target_pc); +} + +void breakaddr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &target = pI->dst(); + thread->push_breakaddr(target); + assert(pI->has_pred() == false); // pdom analysis cannot handle if this instruction is predicated +} + +void brev_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } + +void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + static unsigned call_uid_next = 1; + + const operand_info &target = pI->func_addr(); + assert( target.is_function_address() ); + const symbol *func_addr = target.get_symbol(); + function_info *target_func = func_addr->get_pc(); + if (target_func->is_pdom_set()) { + printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", target_func->get_name().c_str() ); + } else { + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", target_func->get_name().c_str() ); + if (target_func->get_function_size() >0) + target_func->do_pdom(); + target_func->set_pdom(); + } + + // check that number of args and return match function requirements + if( pI->has_return() ^ target_func->has_return() ) { + printf("GPGPU-Sim PTX: Execution error - mismatch in number of return values between\n" + " call instruction and function declaration\n"); + abort(); + } + unsigned n_return = target_func->has_return(); + unsigned n_args = target_func->num_args(); + unsigned n_operands = pI->get_num_operands(); + + if( n_operands != (n_return+1+n_args) ) { + printf("GPGPU-Sim PTX: Execution error - mismatch in number of arguements between\n" + " call instruction and function declaration\n"); + abort(); + } + + // handle intrinsic functions + std::string fname = target_func->get_name(); + if( fname == "vprintf" ) { + gpgpusim_cuda_vprintf(pI, thread, target_func); + return; + } + +#if (CUDART_VERSION >= 5000) + //Jin: handle device runtime apis for CDP + else if(fname == "cudaGetParameterBufferV2") { + gpgpusim_cuda_getParameterBufferV2(pI, thread, target_func); + return; + } + else if(fname == "cudaLaunchDeviceV2") { + gpgpusim_cuda_launchDeviceV2(pI, thread, target_func); + return; + } + else if(fname == "cudaStreamCreateWithFlags") { + gpgpusim_cuda_streamCreateWithFlags(pI, thread, target_func); + return; + } +#endif + + // read source arguements into register specified in declaration of function + arg_buffer_list_t arg_values; + copy_args_into_buffer_list(pI, thread, target_func, arg_values); + + // record local for return value (we only support a single return value) + const symbol *return_var_src = NULL; + const symbol *return_var_dst = NULL; + if( target_func->has_return() ) { + return_var_dst = pI->dst().get_symbol(); + return_var_src = target_func->get_return_var(); + } + + gpgpu_sim *gpu = thread->get_gpu(); + unsigned callee_pc=0, callee_rpc=0; + if( gpu->simd_model() == POST_DOMINATOR ) { + thread->get_core()->get_pdom_stack_top_info(thread->get_hw_wid(),&callee_pc,&callee_rpc); + assert( callee_pc == thread->get_pc() ); + } + + thread->callstack_push(callee_pc + pI->inst_size(), callee_rpc, return_var_src, return_var_dst, call_uid_next++); + + copy_buffer_list_into_frame(thread, arg_values); + + thread->set_npc(target_func); +} + +//Ptxplus version of call instruction. Jumps to a label not a different Kernel. +void callp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + + static unsigned call_uid_next = 1; + + const operand_info &target = pI->dst(); + ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); + + const symbol *return_var_src = NULL; + const symbol *return_var_dst = NULL; + + gpgpu_sim *gpu = thread->get_gpu(); + unsigned callee_pc=0, callee_rpc=0; + if( gpu->simd_model() == POST_DOMINATOR ) { + thread->get_core()->get_pdom_stack_top_info(thread->get_hw_wid(),&callee_pc,&callee_rpc); + assert( callee_pc == thread->get_pc() ); + } + + thread->callstack_push_plus(callee_pc + pI->inst_size(), callee_rpc, return_var_src, return_var_dst, call_uid_next++); + thread->set_npc(target_pc); +} + +void clz_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + int max; + unsigned long long mask; + d.u64 = 0; + + switch ( i_type ) { + case B32_TYPE: + max = 32; + mask = 0x80000000; + break; + case B64_TYPE: + max = 64; + mask = 0x8000000000000000; + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + while ((d.u32 < max) && ((a.u64&mask) == 0) ) { + d.u32++; + a.u64 = a.u64 << 1; + } + + thread->set_operand_value(dst,d, B32_TYPE, thread, pI); +} + +void cnot_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + switch ( i_type ) { + case PRED_TYPE: d.pred = ((a.pred & 0x0001) == 0)?1:0; break; + case B16_TYPE: d.u16 = (a.u16 == 0)?1:0; break; + case B32_TYPE: d.u32 = (a.u32 == 0)?1:0; break; + case B64_TYPE: d.u64 = (a.u64 == 0)?1:0; break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void cos_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case F32_TYPE: + d.f32 = cos(a.f32); + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +ptx_reg_t chop( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + switch ( to_width ) { + case 8: x.mask_and(0,0xFF); break; + case 16: x.mask_and(0,0xFFFF); break; + case 32: x.mask_and(0,0xFFFFFFFF); break; + case 64: break; + default: assert(0); + } + return x; +} + +ptx_reg_t sext( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + x=chop(x,0,from_width,0,rounding_mode,saturation_mode); + switch ( from_width ) { + case 8: if ( x.get_bit(7) ) x.mask_or(0xFFFFFFFF,0xFFFFFF00);break; + case 16:if ( x.get_bit(15) ) x.mask_or(0xFFFFFFFF,0xFFFF0000);break; + case 32: if ( x.get_bit(31) ) x.mask_or(0xFFFFFFFF,0x00000000);break; + case 64: break; + default: assert(0); + } + return x; +} + +// sign extend depending on the destination register size - hack to get SobelFilter working in CUDA 4.2 +ptx_reg_t sexd( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + x=chop(x,0,from_width,0,rounding_mode,saturation_mode); + switch ( to_width ) { + case 8: if ( x.get_bit(7) ) x.mask_or(0xFFFFFFFF,0xFFFFFF00);break; + case 16:if ( x.get_bit(15) ) x.mask_or(0xFFFFFFFF,0xFFFF0000);break; + case 32: if ( x.get_bit(31) ) x.mask_or(0xFFFFFFFF,0x00000000);break; + case 64: break; + default: assert(0); + } + return x; +} + +ptx_reg_t zext( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + return chop(x,0,from_width,0,rounding_mode,saturation_mode); +} + +int saturatei(int a, int max, int min) +{ + if (a > max) a = max; + else if (a < min) a = min; + return a; +} + +unsigned int saturatei(unsigned int a, unsigned int max) +{ + if (a > max) a = max; + return a; +} + +ptx_reg_t f2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + assert( from_width == 32); + + enum cuda_math::cudaRoundMode mode = cuda_math::cudaRoundZero; + switch (rounding_mode) { + case RZI_OPTION: mode = cuda_math::cudaRoundZero; break; + case RNI_OPTION: mode = cuda_math::cudaRoundNearest; break; + case RMI_OPTION: mode = cuda_math::cudaRoundMinInf; break; + case RPI_OPTION: mode = cuda_math::cudaRoundPosInf; break; + default: break; + } + + ptx_reg_t y; + if ( to_sign == 1 ) { // convert to 64-bit number first? + int tmp = cuda_math::float2int(x.f32, mode); + if ((x.u32 & 0x7f800000) == 0) + tmp = 0; // round denorm. FP to 0 + if (saturation_mode && to_width < 32) { + tmp = saturatei(tmp, (1< max) a = max; + else if (a < min) a = min; + return a; +} + +ptx_reg_t d2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + assert( from_width == 64); + + double tmp; + switch (rounding_mode) { + case RZI_OPTION: tmp = trunc(x.f64); break; + case RNI_OPTION: tmp = nearbyint(x.f64); break; + case RMI_OPTION: tmp = floor(x.f64); break; + case RPI_OPTION: tmp = ceil(x.f64); break; + default: tmp = x.f64; break; + } + + ptx_reg_t y; + if ( to_sign == 1 ) { + tmp = saturated2i(tmp, ((1<<(to_width - 1)) - 1), (1<<(to_width - 1)) ); + switch ( to_width ) { + case 8: y.s8 = (char)tmp; break; + case 16: y.s16 = (short)tmp; break; + case 32: y.s32 = (int)tmp; break; + case 64: y.s64 = (long long)tmp; break; + default: assert(0); break; + } + } else if ( to_sign == 0 ) { + tmp = saturated2i(tmp, ((1<<(to_width - 1)) - 1), 0); + switch ( to_width ) { + case 8: y.u8 = (unsigned char)tmp; break; + case 16: y.u16 = (unsigned short)tmp; break; + case 32: y.u32 = (unsigned int)tmp; break; + case 64: y.u64 = (unsigned long long)tmp; break; + default: assert(0); break; + } + } else { + switch ( to_width ) { + case 16: assert(0); break; + case 32: + y.f32 = x.f64; + break; + case 64: + y.f64 = x.f64; // should be handled by d2d + break; + default: assert(0); break; + } + } + return y; +} + +ptx_reg_t s2f( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + ptx_reg_t y; + + if (from_width < 64) { // 32-bit conversion + y = sext(x,from_width,32,0,rounding_mode,saturation_mode); + + switch ( to_width ) { + case 16: assert(0); break; + case 32: + switch (rounding_mode) { + case RZ_OPTION: y.f32 = cuda_math::__int2float_rz(y.s32); break; + case RN_OPTION: y.f32 = cuda_math::__int2float_rn(y.s32); break; + case RM_OPTION: y.f32 = cuda_math::__int2float_rd(y.s32); break; + case RP_OPTION: y.f32 = cuda_math::__int2float_ru(y.s32); break; + default: break; + } + break; + case 64: y.f64 = y.s32; break; // no rounding needed + default: assert(0); break; + } + } else { + switch ( to_width ) { + case 16: assert(0); break; + case 32: + switch (rounding_mode) { + case RZ_OPTION: y.f32 = cuda_math::__ll2float_rz(y.s64); break; + case RN_OPTION: y.f32 = cuda_math::__ll2float_rn(y.s64); break; + case RM_OPTION: y.f32 = cuda_math::__ll2float_rd(y.s64); break; + case RP_OPTION: y.f32 = cuda_math::__ll2float_ru(y.s64); break; + default: break; + } + break; + case 64: y.f64 = y.s64; break; // no internal implementation found + default: assert(0); break; + } + } + + // saturating an integer to 1 or 0? + return y; +} + +ptx_reg_t u2f( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + ptx_reg_t y; + + if (from_width < 64) { // 32-bit conversion + y = zext(x,from_width,32,0,rounding_mode,saturation_mode); + + switch ( to_width ) { + case 16: assert(0); break; + case 32: + switch (rounding_mode) { + case RZ_OPTION: y.f32 = cuda_math::__uint2float_rz(y.u32); break; + case RN_OPTION: y.f32 = cuda_math::__uint2float_rn(y.u32); break; + case RM_OPTION: y.f32 = cuda_math::__uint2float_rd(y.u32); break; + case RP_OPTION: y.f32 = cuda_math::__uint2float_ru(y.u32); break; + default: break; + } + break; + case 64: y.f64 = y.u32; break; // no rounding needed + default: assert(0); break; + } + } else { + switch ( to_width ) { + case 16: assert(0); break; + case 32: + switch (rounding_mode) { + case RZ_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; + case RN_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; + case RM_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; + case RP_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; + default: break; + } + break; + case 64: y.f64 = y.u64; break; // no internal implementation found + default: assert(0); break; + } + } + + // saturating an integer to 1 or 0? + return y; +} + +ptx_reg_t f2f( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + ptx_reg_t y; + switch ( rounding_mode ) { + case RZI_OPTION: + y.f32 = truncf(x.f32); + break; + case RNI_OPTION: +#if CUDART_VERSION >= 3000 + y.f32 = nearbyintf(x.f32); +#else + y.f32 = cuda_math::__internal_nearbyintf(x.f32); +#endif + break; + case RMI_OPTION: + if ((x.u32 & 0x7f800000) == 0) { + y.u32 = x.u32 & 0x80000000; // round denorm. FP to 0, keeping sign + } else { + y.f32 = floorf(x.f32); + } + break; + case RPI_OPTION: + if ((x.u32 & 0x7f800000) == 0) { + y.u32 = x.u32 & 0x80000000; // round denorm. FP to 0, keeping sign + } else { + y.f32 = ceilf(x.f32); + } + break; + default: + if ((x.u32 & 0x7f800000) == 0) { + y.u32 = x.u32 & 0x80000000; // round denorm. FP to 0, keeping sign + } else { + y.f32 = x.f32; + } + break; + } +#if CUDART_VERSION >= 3000 + if (isnanf(y.f32)) +#else + if (cuda_math::__cuda___isnanf(y.f32)) +#endif + { + y.u32 = 0x7fffffff; + } else if (saturation_mode) { + y.f32 = cuda_math::__saturatef(y.f32); + } + + return y; +} + +ptx_reg_t d2d( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + ptx_reg_t y; + switch ( rounding_mode ) { + case RZI_OPTION: + y.f64 = trunc(x.f64); + break; + case RNI_OPTION: +#if CUDART_VERSION >= 3000 + y.f64 = nearbyint(x.f64); +#else + y.f64 = cuda_math::__internal_nearbyintf(x.f64); +#endif + break; + case RMI_OPTION: + y.f64 = floor(x.f64); + break; + case RPI_OPTION: + y.f64 = ceil(x.f64); + break; + default: + y.f64 = x.f64; + break; + } + if (std::isnan(y.f64)) { + y.u64 = 0xfff8000000000000ull; + } else if (saturation_mode) { + y.f64 = cuda_math::__saturatef(y.f64); + } + return y; +} + +ptx_reg_t (*g_cvt_fn[11][11])( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, + int rounding_mode, int saturation_mode ) = { + { NULL, sext, sext, sext, NULL, sext, sext, sext, s2f, s2f, s2f}, + { chop, NULL, sext, sext, chop, NULL, sext, sext, s2f, s2f, s2f}, + { chop, sexd, NULL, sext, chop, chop, NULL, sext, s2f, s2f, s2f}, + { chop, chop, chop, NULL, chop, chop, chop, NULL, s2f, s2f, s2f}, + { NULL, zext, zext, zext, NULL, zext, zext, zext, u2f, u2f, u2f}, + { chop, NULL, zext, zext, chop, NULL, zext, zext, u2f, u2f, u2f}, + { chop, chop, NULL, zext, chop, chop, NULL, zext, u2f, u2f, u2f}, + { chop, chop, chop, NULL, chop, chop, chop, NULL, u2f, u2f, u2f}, + { f2x , f2x , f2x , f2x , f2x , f2x , f2x , f2x , NULL,f2x, f2x}, + { f2x , f2x , f2x , f2x , f2x , f2x , f2x , f2x , f2x, f2f, f2x}, + { d2x , d2x , d2x , d2x , d2x , d2x , d2x , d2x , d2x, d2x, d2d} +}; + +void ptx_round(ptx_reg_t& data, int rounding_mode, int type) +{ + if (rounding_mode == RN_OPTION) { + return; + } + switch ( rounding_mode ) { + case RZI_OPTION: + switch ( type ) { + case S8_TYPE: + case S16_TYPE: + case S32_TYPE: + case S64_TYPE: + case U8_TYPE: + case U16_TYPE: + case U32_TYPE: + case U64_TYPE: + printf("Trying to round an integer??\n"); assert(0); break; + case F16_TYPE: assert(0); break; + case F32_TYPE: + data.f32 = truncf(data.f32); + break; + case F64_TYPE: + case FF64_TYPE: + if (data.f64 < 0) data.f64 = ceil(data.f64); //negative + else data.f64 = floor(data.f64); //positive + break; + default: assert(0); break; + } + break; + case RNI_OPTION: + switch ( type ) { + case S8_TYPE: + case S16_TYPE: + case S32_TYPE: + case S64_TYPE: + case U8_TYPE: + case U16_TYPE: + case U32_TYPE: + case U64_TYPE: + printf("Trying to round an integer??\n"); assert(0); break; + case F16_TYPE: assert(0); break; + case F32_TYPE: +#if CUDART_VERSION >= 3000 + data.f32 = nearbyintf(data.f32); +#else + data.f32 = cuda_math::__cuda_nearbyintf(data.f32); +#endif + break; + case F64_TYPE: case FF64_TYPE: data.f64 = round(data.f64); break; + default: assert(0); break; + } + break; + case RMI_OPTION: + switch ( type ) { + case S8_TYPE: + case S16_TYPE: + case S32_TYPE: + case S64_TYPE: + case U8_TYPE: + case U16_TYPE: + case U32_TYPE: + case U64_TYPE: + printf("Trying to round an integer??\n"); assert(0); break; + case F16_TYPE: assert(0); break; + case F32_TYPE: + data.f32 = floorf(data.f32); + break; + case F64_TYPE: case FF64_TYPE: data.f64 = floor(data.f64); break; + default: assert(0); break; + } + break; + case RPI_OPTION: + switch ( type ) { + case S8_TYPE: + case S16_TYPE: + case S32_TYPE: + case S64_TYPE: + case U8_TYPE: + case U16_TYPE: + case U32_TYPE: + case U64_TYPE: + printf("Trying to round an integer??\n"); assert(0); break; + case F16_TYPE: assert(0); break; + case F32_TYPE: data.f32 = ceilf(data.f32); break; + case F64_TYPE: case FF64_TYPE: data.f64 = ceil(data.f64); break; + default: assert(0); break; + } + break; + default: break; + } + + if (type == F32_TYPE) { +#if CUDART_VERSION >= 3000 + if (isnanf(data.f32)) +#else + if (cuda_math::__cuda___isnanf(data.f32)) +#endif + { + data.u32 = 0x7fffffff; + } + } + if ((type == F64_TYPE)||(type == FF64_TYPE)) { + if (std::isnan(data.f64)) { + data.u64 = 0xfff8000000000000ull; + } + } +} + +void ptx_saturate(ptx_reg_t& data, int saturation_mode, int type) +{ + if (!saturation_mode) { + return; + } + switch ( type ) { + case S8_TYPE: + case S16_TYPE: + case S32_TYPE: + case S64_TYPE: + case U8_TYPE: + case U16_TYPE: + case U32_TYPE: + case U64_TYPE: + printf("Trying to clamp an integer to 1??\n"); assert(0); break; + case F16_TYPE: assert(0); break; + case F32_TYPE: + if (data.f32 > 1.0f) data.f32 = 1.0f; //negative + if (data.f32 < 0.0f) data.f32 = 0.0f; //positive + break; + case F64_TYPE: + case FF64_TYPE: + if (data.f64 > 1.0f) data.f64 = 1.0f; //negative + if (data.f64 < 0.0f) data.f64 = 0.0f; //positive + break; + default: assert(0); break; + } + +} + +void cvt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + unsigned to_type = pI->get_type(); + unsigned from_type = pI->get_type2(); + unsigned rounding_mode = pI->rounding_mode(); + unsigned saturation_mode = pI->saturation_mode(); + + if ( to_type == F16_TYPE || from_type == F16_TYPE ) + abort(); + + int to_sign, from_sign; + size_t from_width, to_width; + unsigned src_fmt = type_info_key::type_decode(from_type, from_width, from_sign); + unsigned dst_fmt = type_info_key::type_decode(to_type, to_width, to_sign); + + ptx_reg_t data = thread->get_operand_value(src1, dst, from_type, thread, 1); + + if(pI->is_neg()){ + + switch( from_type ) { + // Default to f32 for now, need to add support for others + case S8_TYPE: + case U8_TYPE: + case B8_TYPE: + data.s8 = -data.s8; + break; + case S16_TYPE: + case U16_TYPE: + case B16_TYPE: + data.s16 = -data.s16; + break; + case S32_TYPE: + case U32_TYPE: + case B32_TYPE: + data.s32 = -data.s32; + break; + case S64_TYPE: + case U64_TYPE: + case B64_TYPE: + data.s64 = -data.s64; + break; + case F16_TYPE: + data.f16 = -data.f16; + break; + case F32_TYPE: + data.f32 = -data.f32; + break; + case F64_TYPE: + case FF64_TYPE: + data.f64 = -data.f64; + break; + default: + assert(0); + } + + } + + + if ( g_cvt_fn[src_fmt][dst_fmt] != NULL ) { + ptx_reg_t result = g_cvt_fn[src_fmt][dst_fmt](data,from_width,to_width,to_sign, rounding_mode, saturation_mode); + data = result; + } + + thread->set_operand_value(dst, data, to_type, thread, pI ); +} + +void cvta_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + memory_space_t space = pI->get_space(); + bool to_non_generic = pI->is_to(); + + unsigned i_type = pI->get_type(); + ptx_reg_t from_addr = thread->get_operand_value(src1,dst,i_type,thread,1); + addr_t from_addr_hw = (addr_t)from_addr.u64; + addr_t to_addr_hw = 0; + unsigned smid = thread->get_hw_sid(); + unsigned hwtid = thread->get_hw_tid(); + + if( to_non_generic ) { + switch( space.get_type() ) { + case shared_space: to_addr_hw = generic_to_shared( smid, from_addr_hw ); break; + case local_space: to_addr_hw = generic_to_local( smid, hwtid, from_addr_hw ); break; + case global_space: to_addr_hw = generic_to_global(from_addr_hw ); break; + default: abort(); + } + } else { + switch( space.get_type() ) { + case shared_space: to_addr_hw = shared_to_generic( smid, from_addr_hw ); break; + case local_space: to_addr_hw = local_to_generic( smid, hwtid, from_addr_hw ) + + thread->get_local_mem_stack_pointer(); break; // add stack ptr here so that it can be passed as a pointer at function call + case global_space: to_addr_hw = global_to_generic( from_addr_hw ); break; + default: abort(); + } + } + + ptx_reg_t to_addr; + to_addr.u64 = to_addr_hw; + thread->set_reg(dst.get_symbol(),to_addr); +} + +void div_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + + ptx_reg_t src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + ptx_reg_t src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + switch ( i_type ) { + case S8_TYPE: + data.s8 = src1_data.s8 / src2_data.s8 ; break; + case S16_TYPE: + data.s16 = src1_data.s16 / src2_data.s16; break; + case S32_TYPE: + data.s32 = src1_data.s32 / src2_data.s32; break; + case S64_TYPE: + data.s64 = src1_data.s64 / src2_data.s64; break; + case U8_TYPE: + data.u8 = src1_data.u8 / src2_data.u8 ; break; + case U16_TYPE: + data.u16 = src1_data.u16 / src2_data.u16; break; + case U32_TYPE: + data.u32 = src1_data.u32 / src2_data.u32; break; + case U64_TYPE: + data.u64 = src1_data.u64 / src2_data.u64; break; + case B8_TYPE: + data.u8 = src1_data.u8 / src2_data.u8 ; break; + case B16_TYPE: + data.u16 = src1_data.u16 / src2_data.u16; break; + case B32_TYPE: + data.u32 = src1_data.u32 / src2_data.u32; break; + case B64_TYPE: + data.u64 = src1_data.u64 / src2_data.u64; break; + case F16_TYPE: assert(0); break; + case F32_TYPE: data.f32 = src1_data.f32 / src2_data.f32; break; + case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 / src2_data.f64; break; + default: assert(0); break; + } + thread->set_operand_value(dst,data, i_type, thread,pI); +} + +void ex2_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case F32_TYPE: + data.f32 = cuda_math::__powf(2.0, src1_data.f32); + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,data, i_type, thread,pI); +} + +void exit_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + thread->set_done(); + thread->exitCore(); + thread->registerExit(); +} + +void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry = false ); + +void fma_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + mad_def(pI,thread); +} + +void isspacep_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a; + bool t=false; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + memory_space_t space = pI->get_space(); + + a = thread->get_reg(src1.get_symbol()); + addr_t addr = (addr_t)a.u64; + unsigned smid = thread->get_hw_sid(); + unsigned hwtid = thread->get_hw_tid(); + + switch( space.get_type() ) { + case shared_space: t = isspace_shared( smid, addr ); + case local_space: t = isspace_local( smid, hwtid, addr ); + case global_space: t = isspace_global( addr ); + default: abort(); + } + + ptx_reg_t p; + p.pred = t?1:0; + + thread->set_reg(dst.get_symbol(),p); +} + +void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand_info &op, memory_space *&mem, addr_t &addr) +{ + unsigned smid = thread->get_hw_sid(); + unsigned hwtid = thread->get_hw_tid(); + + if( space == param_space_unclassified ) { + // need to op to determine whether it refers to a kernel param or local param + const symbol *s = op.get_symbol(); + const type_info *t = s->type(); + type_info_key ti = t->get_key(); + if( ti.is_param_kernel() ) + space = param_space_kernel; + else if( ti.is_param_local() ) { + space = param_space_local; + } else { + printf("GPGPU-Sim PTX: ERROR ** cannot resolve .param space for '%s'\n", s->name().c_str() ); + abort(); + } + } + switch ( space.get_type() ) { + case global_space: mem = thread->get_global_memory(); break; + case param_space_local: + case local_space: + mem = thread->m_local_mem; + addr += thread->get_local_mem_stack_pointer(); + break; + case tex_space: mem = thread->get_tex_memory(); break; + case surf_space: mem = thread->get_surf_memory(); break; + case param_space_kernel: mem = thread->get_param_memory(); break; + case shared_space: mem = thread->m_shared_mem; break; + case const_space: mem = thread->get_global_memory(); break; + case generic_space: + if( thread->get_ptx_version().ver() >= 2.0 ) { + // convert generic address to memory space address + space = whichspace(addr); + switch ( space.get_type() ) { + case global_space: mem = thread->get_global_memory(); addr = generic_to_global(addr); break; + case local_space: mem = thread->m_local_mem; addr = generic_to_local(smid,hwtid,addr); break; + case shared_space: mem = thread->m_shared_mem; addr = generic_to_shared(smid,addr); break; + default: abort(); + } + } else { + abort(); + } + break; + case param_space_unclassified: + case undefined_space: + default: + abort(); + } +} + +void ld_exec( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned type = pI->get_type(); + + ptx_reg_t src1_data = thread->get_operand_value(src1, dst, type, thread, 1); + ptx_reg_t data; + memory_space_t space = pI->get_space(); + unsigned vector_spec = pI->get_vector(); + + memory_space *mem = NULL; + addr_t addr = src1_data.u32; + + decode_space(space,thread,src1,mem,addr); + + size_t size; + int t; + data.u64=0; + type_info_key::type_decode(type,size,t); + if (!vector_spec) { + mem->read(addr,size/8,&data.s64); + if( type == S16_TYPE || type == S32_TYPE ) + sign_extend(data,size,dst); + thread->set_operand_value(dst,data, type, thread, pI); + } else { + ptx_reg_t data1, data2, data3, data4; + mem->read(addr,size/8,&data1.s64); + mem->read(addr+size/8,size/8,&data2.s64); + if (vector_spec != V2_TYPE) { //either V3 or V4 + mem->read(addr+2*size/8,size/8,&data3.s64); + if (vector_spec != V3_TYPE) { //v4 + mem->read(addr+3*size/8,size/8,&data4.s64); + thread->set_vector_operand_values(dst,data1,data2,data3,data4); + } else //v3 + thread->set_vector_operand_values(dst,data1,data2,data3,data3); + } else //v2 + thread->set_vector_operand_values(dst,data1,data2,data2,data2); + } + thread->m_last_effective_address = addr; + thread->m_last_memory_space = space; +} + +void ld_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ld_exec(pI,thread); +} +void ldu_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ld_exec(pI,thread); +} + +void lg2_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case F32_TYPE: + d.f32 = log(a.f32)/log(2); + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void mad24_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + ptx_reg_t d, t; + + unsigned i_type = pI->get_type(); + ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); + ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); + ptx_reg_t c = thread->get_operand_value(src3, dst, i_type, thread, 1); + + unsigned sat_mode = pI->saturation_mode(); + + assert( !pI->is_wide() ); + + switch ( i_type ) { + case S32_TYPE: + t.s64 = a.s32 * b.s32; + if ( pI->is_hi() ) { + d.s64 = (t.s64>>16) + c.s32; + if ( sat_mode ) { + if ( d.s64 > (int)0x7FFFFFFF ) + d.s64 = (int)0x7FFFFFFF; + else if ( d.s64 < (int)0x80000000 ) + d.s64 = (int)0x80000000; + } + } else if ( pI->is_lo() ) d.s64 = t.s32 + c.s32; + else assert(0); + break; + case U32_TYPE: + t.u64 = a.u32 * b.u32; + if ( pI->is_hi() ) d.u64 = (t.u64>>16) + c.u32; + else if ( pI->is_lo() ) d.u64 = t.u32 + c.u32; + else assert(0); + break; + default: + assert(0); + break; + } + + thread->set_operand_value(dst, d, i_type, thread, pI); +} + +void mad_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + mad_def(pI, thread, false); +} + +void madp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + mad_def(pI, thread, true); +} + +void madc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + mad_def(pI, thread, true); +} + +void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + ptx_reg_t d, t; + + int carry=0; + int overflow=0; + + unsigned i_type = pI->get_type(); + ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); + ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); + ptx_reg_t c = thread->get_operand_value(src3, dst, i_type, thread, 1); + + // take the carry bit, it should be the 4th operand + ptx_reg_t carry_bit; + carry_bit.u64 = 0; + if (use_carry) { + const operand_info &carry = pI->operand_lookup(4); + carry_bit = thread->get_operand_value(carry, dst, PRED_TYPE, thread, 0); + carry_bit.pred &= 0x4; + carry_bit.pred >>=2; + } + + unsigned rounding_mode = pI->rounding_mode(); + + switch ( i_type ) { + case S16_TYPE: + t.s32 = a.s16 * b.s16; + if ( pI->is_wide() ) d.s32 = t.s32 + c.s32 + carry_bit.pred; + else if ( pI->is_hi() ) d.s16 = (t.s32>>16) + c.s16 + carry_bit.pred; + else if ( pI->is_lo() ) d.s16 = t.s16 + c.s16 + carry_bit.pred; + else assert(0); + carry = ((long long int)(t.s32 + c.s32 + carry_bit.pred)&0x100000000)>>32; + break; + case S32_TYPE: + t.s64 = a.s32 * b.s32; + if ( pI->is_wide() ) d.s64 = t.s64 + c.s64 + carry_bit.pred; + else if ( pI->is_hi() ) d.s32 = (t.s64>>32) + c.s32 + carry_bit.pred; + else if ( pI->is_lo() ) d.s32 = t.s32 + c.s32 + carry_bit.pred; + else assert(0); + break; + case S64_TYPE: + t.s64 = a.s64 * b.s64; + assert( !pI->is_wide() ); + assert( !pI->is_hi() ); + assert( use_carry == false); + if ( pI->is_lo() ) d.s64 = t.s64 + c.s64 + carry_bit.pred; + else assert(0); + break; + case U16_TYPE: + t.u32 = a.u16 * b.u16; + if ( pI->is_wide() ) d.u32 = t.u32 + c.u32 + carry_bit.pred; + else if ( pI->is_hi() ) d.u16 = (t.u32 + c.u16 + carry_bit.pred)>>16; + else if ( pI->is_lo() ) d.u16 = t.u16 + c.u16 + carry_bit.pred; + else assert(0); + carry = ((long long int)((long long int)t.u32 + c.u32 + carry_bit.pred)&0x100000000)>>32; + break; + case U32_TYPE: + t.u64 = a.u32 * b.u32; + if ( pI->is_wide() ) d.u64 = t.u64 + c.u64 + carry_bit.pred; + else if ( pI->is_hi() ) d.u32 = (t.u64 + c.u32 + carry_bit.pred)>>32; + else if ( pI->is_lo() ) d.u32 = t.u32 + c.u32 + carry_bit.pred; + else assert(0); + break; + case U64_TYPE: + t.u64 = a.u64 * b.u64; + assert( !pI->is_wide() ); + assert( !pI->is_hi() ); + assert( use_carry == false); + if ( pI->is_lo() ) d.u64 = t.u64 + c.u64 + carry_bit.pred; + else assert(0); + break; + case F16_TYPE: + assert(0); + break; + case F32_TYPE: { + assert( use_carry == false); + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + d.f32 = a.f32 * b.f32 + c.f32; + if ( pI->saturation_mode() ) { + if ( d.f32 < 0 ) d.f32 = 0; + else if ( d.f32 > 1.0f ) d.f32 = 1.0f; + } + fesetround( orig_rm ); + break; + } + case F64_TYPE: case FF64_TYPE: { + assert( use_carry == false); + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + d.f64 = a.f64 * b.f64 + c.f64; + if ( pI->saturation_mode() ) { + if ( d.f64 < 0 ) d.f64 = 0; + else if ( d.f64 > 1.0f ) d.f64 = 1.0; + } + fesetround( orig_rm ); + break; + } + default: + assert(0); + break; + } + thread->set_operand_value(dst, d, i_type, thread, pI, overflow, carry); +} + +bool isNaN(float x) +{ + return std::isnan(x); +} + +bool isNaN(double x) +{ + return std::isnan(x); +} + +void max_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + b = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + switch ( i_type ) { + case U16_TYPE: d.u16 = MY_MAX_I(a.u16,b.u16); break; + case U32_TYPE: d.u32 = MY_MAX_I(a.u32,b.u32); break; + case U64_TYPE: d.u64 = MY_MAX_I(a.u64,b.u64); break; + case S16_TYPE: d.s16 = MY_MAX_I(a.s16,b.s16); break; + case S32_TYPE: d.s32 = MY_MAX_I(a.s32,b.s32); break; + case S64_TYPE: d.s64 = MY_MAX_I(a.s64,b.s64); break; + case F32_TYPE: d.f32 = MY_MAX_F(a.f32,b.f32); break; + case F64_TYPE: case FF64_TYPE: d.f64 = MY_MAX_F(a.f64,b.f64); break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void membar_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + // handled by timing simulator +} + +void min_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + b = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + switch ( i_type ) { + case U16_TYPE: d.u16 = MY_MIN_I(a.u16,b.u16); break; + case U32_TYPE: d.u32 = MY_MIN_I(a.u32,b.u32); break; + case U64_TYPE: d.u64 = MY_MIN_I(a.u64,b.u64); break; + case S16_TYPE: d.s16 = MY_MIN_I(a.s16,b.s16); break; + case S32_TYPE: d.s32 = MY_MIN_I(a.s32,b.s32); break; + case S64_TYPE: d.s64 = MY_MIN_I(a.s64,b.s64); break; + case F32_TYPE: d.f32 = MY_MIN_F(a.f32,b.f32); break; + case F64_TYPE: case FF64_TYPE: d.f64 = MY_MIN_F(a.f64,b.f64); break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void mov_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + unsigned i_type = pI->get_type(); + + if( (src1.is_vector() || dst.is_vector()) && (i_type != BB64_TYPE) && (i_type != BB128_TYPE) && (i_type != FF64_TYPE) ) { + // pack or unpack operation + unsigned nbits_to_move; + ptx_reg_t tmp_bits; + + switch( pI->get_type() ) { + case B16_TYPE: nbits_to_move = 16; break; + case B32_TYPE: nbits_to_move = 32; break; + case B64_TYPE: nbits_to_move = 64; break; + default: printf("Execution error: mov pack/unpack with unsupported type qualifier\n"); assert(0); break; + } + + if( src1.is_vector() ) { + unsigned nelem = src1.get_vect_nelem(); + ptx_reg_t v[4]; + thread->get_vector_operand_values(src1, v, nelem ); + + unsigned bits_per_src_elem = nbits_to_move / nelem; + for( unsigned i=0; i < nelem; i++ ) { + switch(bits_per_src_elem) { + case 8: tmp_bits.u64 |= ((unsigned long long)(v[i].u8) << (8*i)); break; + case 16: tmp_bits.u64 |= ((unsigned long long)(v[i].u16) << (16*i)); break; + case 32: tmp_bits.u64 |= ((unsigned long long)(v[i].u32) << (32*i)); break; + default: printf("Execution error: mov pack/unpack with unsupported source/dst size ratio (src)\n"); assert(0); break; + } + } + } else { + data = thread->get_operand_value(src1, dst, i_type, thread, 1); + + switch( pI->get_type() ) { + case B16_TYPE: tmp_bits.u16 = data.u16; break; + case B32_TYPE: tmp_bits.u32 = data.u32; break; + case B64_TYPE: tmp_bits.u64 = data.u64; break; + default: assert(0); break; + } + } + + if( dst.is_vector() ) { + unsigned nelem = dst.get_vect_nelem(); + ptx_reg_t v[4]; + unsigned bits_per_dst_elem = nbits_to_move / nelem; + for( unsigned i=0; i < nelem; i++ ) { + switch(bits_per_dst_elem) { + case 8: v[i].u8 = (tmp_bits.u64 >> (8*i)) & ((unsigned long long) 0xFF); break; + case 16: v[i].u16 = (tmp_bits.u64 >> (16*i)) & ((unsigned long long) 0xFFFF); break; + case 32: v[i].u32 = (tmp_bits.u64 >> (32*i)) & ((unsigned long long) 0xFFFFFFFF); break; + default: + printf("Execution error: mov pack/unpack with unsupported source/dst size ratio (dst)\n"); + assert(0); + break; + } + } + thread->set_vector_operand_values(dst,v[0],v[1],v[2],v[3]); + } else { + thread->set_operand_value(dst,tmp_bits, i_type, thread, pI); + } + } else if (i_type == PRED_TYPE and src1.is_literal() == true) { + // in ptx, literal input translate to predicate as 0 = false and 1 = true + // we have adopted the opposite to simplify implementation of zero flags in ptxplus + data = thread->get_operand_value(src1, dst, i_type, thread, 1); + + ptx_reg_t finaldata; + finaldata.pred = (data.u32 == 0)? 1 : 0; // setting zero-flag in predicate + thread->set_operand_value(dst, finaldata, i_type, thread, pI); + } else { + + data = thread->get_operand_value(src1, dst, i_type, thread, 1); + + thread->set_operand_value(dst, data, i_type, thread, pI); + + } +} + +void mul24_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + //src1_data = srcOperandModifiers(src1_data, src1, dst, i_type, thread); + //src2_data = srcOperandModifiers(src2_data, src2, dst, i_type, thread); + + src1_data.mask_and(0,0x00FFFFFF); + src2_data.mask_and(0,0x00FFFFFF); + + switch ( i_type ) { + case S32_TYPE: + if( src1_data.get_bit(23) ) + src1_data.mask_or(0xFFFFFFFF,0xFF000000); + if( src2_data.get_bit(23) ) + src2_data.mask_or(0xFFFFFFFF,0xFF000000); + data.s64 = src1_data.s64 * src2_data.s64; + break; + case U32_TYPE: + data.u64 = src1_data.u64 * src2_data.u64; + break; + default: + printf("GPGPU-Sim PTX: Execution error - type mismatch with instruction\n"); + assert(0); + break; + } + + if ( pI->is_hi() ) { + data.u64 = data.u64 >> 16; + data.mask_and(0,0xFFFFFFFF); + } else if (pI->is_lo()) { + data.mask_and(0,0xFFFFFFFF); + } + + thread->set_operand_value(dst, data, i_type, thread, pI); +} + +void mul_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + ptx_reg_t d, t; + + unsigned i_type = pI->get_type(); + ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); + ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); + + unsigned rounding_mode = pI->rounding_mode(); + + switch ( i_type ) { + case S16_TYPE: + t.s32 = ((int)a.s16) * ((int)b.s16); + if ( pI->is_wide() ) d.s32 = t.s32; + else if ( pI->is_hi() ) d.s16 = (t.s32>>16); + else if ( pI->is_lo() ) d.s16 = t.s16; + else assert(0); + break; + case S32_TYPE: + t.s64 = ((long long)a.s32) * ((long long)b.s32); + if ( pI->is_wide() ) d.s64 = t.s64; + else if ( pI->is_hi() ) d.s32 = (t.s64>>32); + else if ( pI->is_lo() ) d.s32 = t.s32; + else assert(0); + break; + case S64_TYPE: + t.s64 = a.s64 * b.s64; + assert( !pI->is_wide() ); + assert( !pI->is_hi() ); + if ( pI->is_lo() ) d.s64 = t.s64; + else assert(0); + break; + case U16_TYPE: + t.u32 = ((unsigned)a.u16) * ((unsigned)b.u16); + if ( pI->is_wide() ) d.u32 = t.u32; + else if ( pI->is_lo() ) d.u16 = t.u16; + else if ( pI->is_hi() ) d.u16 = (t.u32>>16); + else assert(0); + break; + case U32_TYPE: + t.u64 = ((unsigned long long)a.u32) * ((unsigned long long)b.u32); + if ( pI->is_wide() ) d.u64 = t.u64; + else if ( pI->is_lo() ) d.u32 = t.u32; + else if ( pI->is_hi() ) d.u32 = (t.u64>>32); + else assert(0); + break; + case U64_TYPE: + t.u64 = a.u64 * b.u64; + assert( !pI->is_wide() ); + assert( !pI->is_hi() ); + if ( pI->is_lo() ) d.u64 = t.u64; + else assert(0); + break; + case F16_TYPE: + assert(0); + break; + case F32_TYPE: { + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + + d.f32 = a.f32 * b.f32; + + if ( pI->saturation_mode() ) { + if ( d.f32 < 0 ) d.f32 = 0; + else if ( d.f32 > 1.0f ) d.f32 = 1.0f; + } + fesetround( orig_rm ); + break; + } + case F64_TYPE: case FF64_TYPE:{ + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + d.f64 = a.f64 * b.f64; + if ( pI->saturation_mode() ) { + if ( d.f64 < 0 ) d.f64 = 0; + else if ( d.f64 > 1.0f ) d.f64 = 1.0; + } + fesetround( orig_rm ); + break; + } + default: + assert(0); + break; + } + + thread->set_operand_value(dst, d, i_type, thread, pI); +} + +void neg_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned to_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, to_type, thread, 1); + + + switch ( to_type ) { + case S8_TYPE: + case S16_TYPE: + case S32_TYPE: + case S64_TYPE: + data.s64 = 0 - src1_data.s64; break; // seems buggy, but not (just ignore higher bits) + case U8_TYPE: + case U16_TYPE: + case U32_TYPE: + case U64_TYPE: + assert(0); break; + case F16_TYPE: assert(0); break; + case F32_TYPE: data.f32 = 0.0f - src1_data.f32; break; + case F64_TYPE: case FF64_TYPE: data.f64 = 0.0f - src1_data.f64; break; + default: assert(0); break; + } + + thread->set_operand_value(dst,data, to_type, thread, pI); +} + +//nandn bitwise negates second operand then bitwise nands with the first operand +void nandn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + //the way ptxplus handles predicates: 1 = false and 0 = true + if(i_type == PRED_TYPE) + data.pred = (~src1_data.pred & src2_data.pred); + else + data.u64 = ~(src1_data.u64 & ~src2_data.u64); + + thread->set_operand_value(dst,data, i_type, thread, pI); + +} + +//norn bitwise negates first operand then bitwise ands with the second operand +void norn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + //the way ptxplus handles predicates: 1 = false and 0 = true + if(i_type == PRED_TYPE) + data.pred = ~(src1_data.pred & ~(src2_data.pred)); + else + data.u64 = ~(src1_data.u64) & src2_data.u64; + + thread->set_operand_value(dst,data, i_type, thread, pI); + +} + +void not_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case PRED_TYPE: d.pred = (~(a.pred) & 0x000F); break; + case B16_TYPE: d.u16 = ~a.u16; break; + case B32_TYPE: d.u32 = ~a.u32; break; + case B64_TYPE: d.u64 = ~a.u64; break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void or_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + //the way ptxplus handles predicates: 1 = false and 0 = true + if(i_type == PRED_TYPE) + data.pred = ~(~(src1_data.pred) | ~(src2_data.pred)); + else + data.u64 = src1_data.u64 | src2_data.u64; + + thread->set_operand_value(dst,data, i_type, thread, pI); +} + +void orn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + //the way ptxplus handles predicates: 1 = false and 0 = true + if(i_type == PRED_TYPE) + data.pred = ~(~(src1_data.pred) | (src2_data.pred)); + else + data.u64 = src1_data.u64 | ~src2_data.u64; + + thread->set_operand_value(dst,data, i_type, thread, pI); +} + +void pmevent_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void popc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src_data, data; + const operand_info &dst = pI->dst(); + const operand_info &src = pI->src1(); + + unsigned i_type = pI->get_type(); + src_data = thread->get_operand_value(src, dst, i_type, thread, 1); + + switch ( i_type ) { + case B32_TYPE: { + std::bitset<32> mask(src_data.u32); + data.u32 = mask.count(); + } break; + case B64_TYPE: { + std::bitset<64> mask(src_data.u64); + data.u32 = mask.count(); + } break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,data, i_type, thread, pI); +} +void prefetch_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void prefetchu_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void prmt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } + +void rcp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case F32_TYPE: + data.f32 = 1.0f / src1_data.f32; + break; + case F64_TYPE: + case FF64_TYPE: + data.f64 = 1.0f / src1_data.f64; + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,data, i_type, thread, pI); +} + +void red_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } + +void rem_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + data.u64 = src1_data.u64 % src2_data.u64; + + thread->set_operand_value(dst,data, i_type, thread, pI); +} + +void ret_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + bool empty = thread->callstack_pop(); + if( empty ) { + thread->set_done(); + thread->exitCore(); + thread->registerExit(); + } +} + +//Ptxplus version of ret instruction. +void retp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + bool empty = thread->callstack_pop_plus(); + if( empty ) { + thread->set_done(); + thread->exitCore(); + thread->registerExit(); + } +} + +void rsqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case F32_TYPE: + if ( a.f32 < 0 ) { + d.u64 = 0; + d.u64 = 0x7fc00000; // NaN + } else if ( a.f32 == 0 ) { + d.u64 = 0; + d.u32 = 0x7f800000; // Inf + } else + d.f32 = cuda_math::__internal_accurate_fdividef(1.0f, sqrtf(a.f32)); + break; + case F64_TYPE: + case FF64_TYPE: + if ( a.f32 < 0 ) { + d.u64 = 0; + d.u32 = 0x7fc00000; // NaN + float x = d.f32; + d.f64 = (double)x; + } else if ( a.f32 == 0 ) { + d.u64 = 0; + d.u32 = 0x7f800000; // Inf + float x = d.f32; + d.f64 = (double)x; + } else + d.f64 = 1.0 / sqrt(a.f64); + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +#define SAD(d,a,b,c) d = c + ((adst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + b = thread->get_operand_value(src2, dst, i_type, thread, 1); + c = thread->get_operand_value(src3, dst, i_type, thread, 1); + + + switch ( i_type ) { + case U16_TYPE: SAD(d.u16,a.u16,b.u16,c.u16); break; + case U32_TYPE: SAD(d.u32,a.u32,b.u32,c.u32); break; + case U64_TYPE: SAD(d.u64,a.u64,b.u64,c.u64); break; + case S16_TYPE: SAD(d.s16,a.s16,b.s16,c.s16); break; + case S32_TYPE: SAD(d.s32,a.s32,b.s32,c.s32); break; + case S64_TYPE: SAD(d.s64,a.s64,b.s64,c.s64); break; + case F32_TYPE: SAD(d.f32,a.f32,b.f32,c.f32); break; + case F64_TYPE: case FF64_TYPE: SAD(d.f64,a.f64,b.f64,c.f64); break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void selp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + + ptx_reg_t a, b, c, d; + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + b = thread->get_operand_value(src2, dst, i_type, thread, 1); + c = thread->get_operand_value(src3, dst, i_type, thread, 1); + + //predicate value was changed so the lowest bit being set means the zero flag is set. + //As a result, the value of c.pred must be inverted to get proper behavior + d = (!(c.pred & 0x0001))?a:b; + + thread->set_operand_value(dst,d, PRED_TYPE, thread, pI); +} + +bool isFloat(int type) +{ + switch ( type ) { + case F16_TYPE: + case F32_TYPE: + case F64_TYPE: + case FF64_TYPE: + return true; + default: + return false; + } +} + +bool CmpOp( int type, ptx_reg_t a, ptx_reg_t b, unsigned cmpop ) +{ + bool t = false; + + switch ( type ) { + case B16_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.u16 == b.u16); break; + case NE_OPTION: t = (a.u16 != b.u16); break; + default: + assert(0); + } + + case B32_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.u32 == b.u32); break; + case NE_OPTION: t = (a.u32 != b.u32); break; + default: + assert(0); + } + case B64_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.u64 == b.u64); break; + case NE_OPTION: t = (a.u64 != b.u64); break; + default: + assert(0); + } + break; + case S8_TYPE: + case S16_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.s16 == b.s16); break; + case NE_OPTION: t = (a.s16 != b.s16); break; + case LT_OPTION: t = (a.s16 < b.s16); break; + case LE_OPTION: t = (a.s16 <= b.s16); break; + case GT_OPTION: t = (a.s16 > b.s16); break; + case GE_OPTION: t = (a.s16 >= b.s16); break; + default: + assert(0); + } + break; + case S32_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.s32 == b.s32); break; + case NE_OPTION: t = (a.s32 != b.s32); break; + case LT_OPTION: t = (a.s32 < b.s32); break; + case LE_OPTION: t = (a.s32 <= b.s32); break; + case GT_OPTION: t = (a.s32 > b.s32); break; + case GE_OPTION: t = (a.s32 >= b.s32); break; + default: + assert(0); + } + break; + case S64_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.s64 == b.s64); break; + case NE_OPTION: t = (a.s64 != b.s64); break; + case LT_OPTION: t = (a.s64 < b.s64); break; + case LE_OPTION: t = (a.s64 <= b.s64); break; + case GT_OPTION: t = (a.s64 > b.s64); break; + case GE_OPTION: t = (a.s64 >= b.s64); break; + default: + assert(0); + } + break; + case U8_TYPE: + case U16_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.u16 == b.u16); break; + case NE_OPTION: t = (a.u16 != b.u16); break; + case LT_OPTION: t = (a.u16 < b.u16); break; + case LE_OPTION: t = (a.u16 <= b.u16); break; + case GT_OPTION: t = (a.u16 > b.u16); break; + case GE_OPTION: t = (a.u16 >= b.u16); break; + case LO_OPTION: t = (a.u16 < b.u16); break; + case LS_OPTION: t = (a.u16 <= b.u16); break; + case HI_OPTION: t = (a.u16 > b.u16); break; + case HS_OPTION: t = (a.u16 >= b.u16); break; + default: + assert(0); + } + break; + case U32_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.u32 == b.u32); break; + case NE_OPTION: t = (a.u32 != b.u32); break; + case LT_OPTION: t = (a.u32 < b.u32); break; + case LE_OPTION: t = (a.u32 <= b.u32); break; + case GT_OPTION: t = (a.u32 > b.u32); break; + case GE_OPTION: t = (a.u32 >= b.u32); break; + case LO_OPTION: t = (a.u32 < b.u32); break; + case LS_OPTION: t = (a.u32 <= b.u32); break; + case HI_OPTION: t = (a.u32 > b.u32); break; + case HS_OPTION: t = (a.u32 >= b.u32); break; + default: + assert(0); + } + break; + case U64_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.u64 == b.u64); break; + case NE_OPTION: t = (a.u64 != b.u64); break; + case LT_OPTION: t = (a.u64 < b.u64); break; + case LE_OPTION: t = (a.u64 <= b.u64); break; + case GT_OPTION: t = (a.u64 > b.u64); break; + case GE_OPTION: t = (a.u64 >= b.u64); break; + case LO_OPTION: t = (a.u64 < b.u64); break; + case LS_OPTION: t = (a.u64 <= b.u64); break; + case HI_OPTION: t = (a.u64 > b.u64); break; + case HS_OPTION: t = (a.u64 >= b.u64); break; + default: + assert(0); + } + break; + case F16_TYPE: assert(0); break; + case F32_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.f32 == b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; + case NE_OPTION: t = (a.f32 != b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; + case LT_OPTION: t = (a.f32 < b.f32 ) && !isNaN(a.f32) && !isNaN(b.f32); break; + case LE_OPTION: t = (a.f32 <= b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; + case GT_OPTION: t = (a.f32 > b.f32 ) && !isNaN(a.f32) && !isNaN(b.f32); break; + case GE_OPTION: t = (a.f32 >= b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; + case EQU_OPTION: t = (a.f32 == b.f32) || isNaN(a.f32) || isNaN(b.f32); break; + case NEU_OPTION: t = (a.f32 != b.f32) || isNaN(a.f32) || isNaN(b.f32); break; + case LTU_OPTION: t = (a.f32 < b.f32 ) || isNaN(a.f32) || isNaN(b.f32); break; + case LEU_OPTION: t = (a.f32 <= b.f32) || isNaN(a.f32) || isNaN(b.f32); break; + case GTU_OPTION: t = (a.f32 > b.f32 ) || isNaN(a.f32) || isNaN(b.f32); break; + case GEU_OPTION: t = (a.f32 >= b.f32) || isNaN(a.f32) || isNaN(b.f32); break; + case NUM_OPTION: t = !isNaN(a.f32) && !isNaN(b.f32); break; + case NAN_OPTION: t = isNaN(a.f32) || isNaN(b.f32); break; + default: + assert(0); + } + break; + case F64_TYPE: + case FF64_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.f64 == b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; + case NE_OPTION: t = (a.f64 != b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; + case LT_OPTION: t = (a.f64 < b.f64 ) && !isNaN(a.f64) && !isNaN(b.f64); break; + case LE_OPTION: t = (a.f64 <= b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; + case GT_OPTION: t = (a.f64 > b.f64 ) && !isNaN(a.f64) && !isNaN(b.f64); break; + case GE_OPTION: t = (a.f64 >= b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; + case EQU_OPTION: t = (a.f64 == b.f64) || isNaN(a.f64) || isNaN(b.f64); break; + case NEU_OPTION: t = (a.f64 != b.f64) || isNaN(a.f64) || isNaN(b.f64); break; + case LTU_OPTION: t = (a.f64 < b.f64 ) || isNaN(a.f64) || isNaN(b.f64); break; + case LEU_OPTION: t = (a.f64 <= b.f64) || isNaN(a.f64) || isNaN(b.f64); break; + case GTU_OPTION: t = (a.f64 > b.f64 ) || isNaN(a.f64) || isNaN(b.f64); break; + case GEU_OPTION: t = (a.f64 >= b.f64) || isNaN(a.f64) || isNaN(b.f64); break; + case NUM_OPTION: t = !isNaN(a.f64) && !isNaN(b.f64); break; + case NAN_OPTION: t = isNaN(a.f64) || isNaN(b.f64); break; + default: + assert(0); + } + break; + default: assert(0); break; + } + + return t; +} + +void setp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b; + + int t=0; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + assert( pI->get_num_operands() < 4 ); // or need to deal with "c" operand / boolOp + + unsigned type = pI->get_type(); + unsigned cmpop = pI->get_cmpop(); + a = thread->get_operand_value(src1, dst, type, thread, 1); + b = thread->get_operand_value(src2, dst, type, thread, 1); + + t = CmpOp(type,a,b,cmpop); + + ptx_reg_t data; + + //the way ptxplus handles the zero flag, 1 = false and 0 = true + data.pred = (t==0); //inverting predicate since ptxplus uses "1" for a set zero flag + + thread->set_operand_value(dst,data, PRED_TYPE, thread, pI); +} + +void set_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b; + + int t=0; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + assert( pI->get_num_operands() < 4 ); // or need to deal with "c" operand / boolOp + + unsigned src_type = pI->get_type2(); + unsigned cmpop = pI->get_cmpop(); + + a = thread->get_operand_value(src1, dst, src_type, thread, 1); + b = thread->get_operand_value(src2, dst, src_type, thread, 1); + + // Take abs of first operand if needed + if(pI->is_abs()) { + switch ( src_type ) { + case S16_TYPE: a.s16 = my_abs(a.s16); break; + case S32_TYPE: a.s32 = my_abs(a.s32); break; + case S64_TYPE: a.s64 = my_abs(a.s64); break; + case U16_TYPE: a.u16 = a.u16; break; + case U32_TYPE: a.u32 = my_abs(a.u32); break; + case U64_TYPE: a.u64 = my_abs(a.u64); break; + case F32_TYPE: a.f32 = my_abs(a.f32); break; + case F64_TYPE: case FF64_TYPE: a.f64 = my_abs(a.f64); break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + } + + t = CmpOp(src_type,a,b,cmpop); + + ptx_reg_t data; + if ( isFloat(pI->get_type()) ) { + data.f32 = (t!=0)?1.0f:0.0f; + } else { + data.u32 = (t!=0)?0xFFFFFFFF:0; + } + + thread->set_operand_value(dst, data, pI->get_type(), thread, pI); + +} + +void shfl_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) +{ + unsigned i_type = pI->get_type(); + int tid = inst.warp_id() * core->get_warp_size(); + ptx_thread_info *thread = core->get_thread_info()[tid]; + ptx_warp_info *warp_info = thread->m_warp_info; + int lane = warp_info->get_done_threads(); + thread = core->get_thread_info()[tid + lane]; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + int bval = (thread->get_operand_value(src2, dst, i_type, thread, 1)).u32; + int cval = (thread->get_operand_value(src3, dst, i_type, thread, 1)).u32; + int mask = cval >> 8; + bval &= 0x1F; + cval &= 0x1F; + + int maxLane = (lane & mask) | (cval & ~mask); + int minLane = lane & mask; + + int src_idx; + unsigned p; + switch(pI->shfl_op()) { + case UP_OPTION: + src_idx = lane - bval; + p = (src_idx >= maxLane); + break; + case DOWN_OPTION: + src_idx = lane + bval; + p = (src_idx <= maxLane); + break; + case BFLY_OPTION: + src_idx = lane ^ bval; + p = (src_idx <= maxLane); + break; + case IDX_OPTION: + src_idx = minLane | (bval & ~mask); + p = (src_idx <= maxLane); + break; + default: + printf("GPGPU-Sim PTX: ERROR: Invalid shfl option\n"); + assert(0); + break; + } + // copy from own lane + if (!p) src_idx = lane; + + // copy input from lane src_idx + ptx_reg_t data; + if (inst.active(src_idx)) { + ptx_thread_info *source = core->get_thread_info()[tid + src_idx]; + data = source->get_operand_value(src1, dst, i_type, source, 1); + } else { + printf("GPGPU-Sim PTX: WARNING: shfl input value unpredictable for inactive threads in a warp\n"); + data.u32 = 0; + } + thread->set_operand_value(dst, data, i_type, thread, pI); + + /* + TODO: deal with predicates appropriately using the following pseudocode: + if (!isGuardPredicateTrue(src_idx)) { + printf("GPGPU-Sim PTX: WARNING: shfl input value unpredictable for predicated-off threads in a warp\n"); + } + if (dest predicate selected) data.pred = p; + */ + + // keep track of the number of threads that have executed in the warp + warp_info->inc_done_threads(); + if (warp_info->get_done_threads() == inst.active_count()) { + warp_info->reset_done_threads(); + } +} + +void shl_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + b = thread->get_operand_value(src2, dst, i_type, thread, 1); + + switch ( i_type ) { + case B16_TYPE: + case U16_TYPE: + if ( b.u16 >= 16 ) + d.u16 = 0; + else + d.u16 = (unsigned short) ((a.u16 << b.u16) & 0xFFFF); + break; + case B32_TYPE: + case U32_TYPE: + if ( b.u32 >= 32 ) + d.u32 = 0; + else + d.u32 = (unsigned) ((a.u32 << b.u32) & 0xFFFFFFFF); + break; + case B64_TYPE: + case U64_TYPE: + if ( b.u32 >= 64 ) + d.u64 = 0; + else + d.u64 = (a.u64 << b.u64); + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst, d, i_type, thread, pI); +} + +void shr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + b = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + switch ( i_type ) { + case U16_TYPE: + case B16_TYPE: + if ( b.u16 < 16 ) + d.u16 = (unsigned short) ((a.u16 >> b.u16) & 0xFFFF); + else + d.u16 = 0; + break; + case U32_TYPE: + case B32_TYPE: + if ( b.u32 < 32 ) + d.u32 = (unsigned) ((a.u32 >> b.u32) & 0xFFFFFFFF); + else + d.u32 = 0; + break; + case U64_TYPE: + case B64_TYPE: + if ( b.u32 < 64 ) + d.u64 = (a.u64 >> b.u64); + else + d.u64 = 0; + break; + case S16_TYPE: + if ( b.u16 < 16 ) + d.s64 = (a.s16 >> b.s16); + else { + if ( a.s16 < 0 ) { + d.s64 = -1; + } else { + d.s64 = 0; + } + } + break; + case S32_TYPE: + if ( b.u32 < 32 ) + d.s64 = (a.s32 >> b.s32); + else { + if ( a.s32 < 0 ) { + d.s64 = -1; + } else { + d.s64 = 0; + } + } + break; + case S64_TYPE: + if ( b.u64 < 64 ) + d.s64 = (a.s64 >> b.u64); + else { + if ( a.s64 < 0 ) { + if ( b.s32 < 0 ) { + d.u64 = -1; + d.s32 = 0; + } else { + d.s64 = -1; + } + } else { + d.s64 = 0; + } + } + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void sin_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case F32_TYPE: + d.f32 = sin(a.f32); + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void slct_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + + ptx_reg_t a, b, c, d; + + unsigned i_type = pI->get_type(); + unsigned c_type = pI->get_type2(); + bool t = false; + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + b = thread->get_operand_value(src2, dst, i_type, thread, 1); + c = thread->get_operand_value(src3, dst, c_type, thread, 1); + + switch ( c_type ) { + case S32_TYPE: t = c.s32 >= 0; break; + case F32_TYPE: t = c.f32 >= 0; break; + default: assert(0); + } + + switch ( i_type ) { + case B16_TYPE: + case S16_TYPE: + case U16_TYPE: d.u16 = t?a.u16:b.u16; break; + case F32_TYPE: + case B32_TYPE: + case S32_TYPE: + case U32_TYPE: d.u32 = t?a.u32:b.u32; break; + case F64_TYPE: + case FF64_TYPE: + case B64_TYPE: + case S64_TYPE: + case U64_TYPE: d.u64 = t?a.u64:b.u64; break; + default: assert(0); + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case F32_TYPE: + if ( a.f32 < 0 ) + d.f32 = nanf(""); + else + d.f32 = sqrt(a.f32); break; + case F64_TYPE: + case FF64_TYPE: + if ( a.f64 < 0 ) + d.f64 = nan(""); + else + d.f64 = sqrt(a.f64); break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void ssy_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + //printf("Execution Warning: unimplemented ssy instruction is treated as a nop\n"); + // TODO: add implementation +} + +void st_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); //may be scalar or vector of regs + unsigned type = pI->get_type(); + ptx_reg_t addr_reg = thread->get_operand_value(dst, dst, type, thread, 1); + ptx_reg_t data; + memory_space_t space = pI->get_space(); + unsigned vector_spec = pI->get_vector(); + + memory_space *mem = NULL; + addr_t addr = addr_reg.u32; + + decode_space(space,thread,dst,mem,addr); + + size_t size; + int t; + type_info_key::type_decode(type,size,t); + + if (!vector_spec) { + data = thread->get_operand_value(src1, dst, type, thread, 1); + mem->write(addr,size/8,&data.s64,thread,pI); + } else { + if (vector_spec == V2_TYPE) { + ptx_reg_t* ptx_regs = new ptx_reg_t[2]; + thread->get_vector_operand_values(src1, ptx_regs, 2); + mem->write(addr,size/8,&ptx_regs[0].s64,thread,pI); + mem->write(addr+size/8,size/8,&ptx_regs[1].s64,thread,pI); + delete [] ptx_regs; + } + if (vector_spec == V3_TYPE) { + ptx_reg_t* ptx_regs = new ptx_reg_t[3]; + thread->get_vector_operand_values(src1, ptx_regs, 3); + mem->write(addr,size/8,&ptx_regs[0].s64,thread,pI); + mem->write(addr+size/8,size/8,&ptx_regs[1].s64,thread,pI); + mem->write(addr+2*size/8,size/8,&ptx_regs[2].s64,thread,pI); + delete [] ptx_regs; + } + if (vector_spec == V4_TYPE) { + ptx_reg_t* ptx_regs = new ptx_reg_t[4]; + thread->get_vector_operand_values(src1, ptx_regs, 4); + mem->write(addr,size/8,&ptx_regs[0].s64,thread,pI); + mem->write(addr+size/8,size/8,&ptx_regs[1].s64,thread,pI); + mem->write(addr+2*size/8,size/8,&ptx_regs[2].s64,thread,pI); + mem->write(addr+3*size/8,size/8,&ptx_regs[3].s64,thread,pI); + delete [] ptx_regs; + } + } + thread->m_last_effective_address = addr; + thread->m_last_memory_space = space; +} + +void sub_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t data; + int overflow = 0; + int carry = 0; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + ptx_reg_t src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + ptx_reg_t src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + //performs addition. Sets carry and overflow if needed. + //the constant is added in during subtraction so the carry bit is set properly. + switch ( i_type ) { + case S8_TYPE: + data.s64 = (src1_data.s64 & 0xFF) - (src2_data.s64 & 0xFF) + 0x100; + if(((src1_data.s64 & 0x80)-(src2_data.s64 & 0x80)) != 0) {overflow=((src1_data.s64 & 0x80)-(data.s64 & 0x80))==0?0:1; } + carry = (data.s32 & 0x100)>>8; + break; + case S16_TYPE: + data.s64 = (src1_data.s64 & 0xFFFF) - (src2_data.s64 & 0xFFFF) + 0x10000; + if(((src1_data.s64 & 0x8000)-(src2_data.s64 & 0x8000)) != 0) {overflow=((src1_data.s64 & 0x8000)-(data.s64 & 0x8000))==0?0:1; } + carry = (data.s32 & 0x10000)>>16; + break; + case S32_TYPE: + data.s64 = (src1_data.s64 & 0xFFFFFFFF) - (src2_data.s64 & 0xFFFFFFFF) + 0x100000000; + if(((src1_data.s64 & 0x80000000)-(src2_data.s64 & 0x80000000)) != 0) {overflow=((src1_data.s64 & 0x80000000)-(data.s64 & 0x80000000))==0?0:1; } + carry = ((data.u64)>>32) & 0x0001; + break; + case S64_TYPE: + data.s64 = src1_data.s64 - src2_data.s64; break; + case B8_TYPE: + case U8_TYPE: + data.u64 = (src1_data.u64 & 0xFF) - (src2_data.u64 & 0xFF) + 0x100; + carry = (data.u64 & 0x100)>>8; + break; + case B16_TYPE: + case U16_TYPE: + data.u64 = (src1_data.u64 & 0xFFFF) - (src2_data.u64 & 0xFFFF) + 0x10000; + carry = (data.u64 & 0x10000)>>16; + break; + case B32_TYPE: + case U32_TYPE: + data.u64 = (src1_data.u64 & 0xFFFFFFFF) - (src2_data.u64 & 0xFFFFFFFF) + 0x100000000; + carry = (data.u64 & 0x100000000)>>32; + break; + case B64_TYPE: + case U64_TYPE: + data.u64 = src1_data.u64 - src2_data.u64; break; + case F16_TYPE: assert(0); break; + case F32_TYPE: data.f32 = src1_data.f32 - src2_data.f32; break; + case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 - src2_data.f64; break; + default: assert(0); break; + } + + thread->set_operand_value(dst,data, i_type, thread, pI, overflow, carry); +} + +void nop_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + // Do nothing +} + +void subc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void suld_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void sured_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void sust_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void suq_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } + +ptx_reg_t* ptx_tex_regs = NULL; + +union intfloat { + int a; + float b; +}; + +float reduce_precision( float x, unsigned bits ) +{ + intfloat tmp; + tmp.b = x; + int v = tmp.a; + int man = v & ((1<<23)-1); + int mask = ((1<= mx) nx -= elem_size; + unsigned ny = (y >= my)? my - 1 : y; + return nx + mx*ny; +} + +typedef unsigned (*texAddr_t) (unsigned x, unsigned y, unsigned mx, unsigned my, size_t elem_size); +float tex_linf_sampling(memory_space* mem, unsigned tex_array_base, + int x, int y, unsigned int width, unsigned int height, size_t elem_size, + float alpha, float beta, texAddr_t b_lim) +{ + float Tij; + float Ti1j; + float Tij1; + float Ti1j1; + + mem->read(tex_array_base + b_lim(x,y,width,height,elem_size), 4, &Tij); + mem->read(tex_array_base + b_lim(x+elem_size,y,width,height,elem_size), 4, &Ti1j); + mem->read(tex_array_base + b_lim(x,y+1,width,height,elem_size), 4, &Tij1); + mem->read(tex_array_base + b_lim(x+elem_size,y+1,width,height,elem_size), 4, &Ti1j1); + + float sample = (1-alpha)*(1-beta)*Tij + + alpha*(1-beta)*Ti1j + + (1-alpha)*beta*Tij1 + + alpha*beta*Ti1j1; + + return sample; +} + +float textureNormalizeElementSigned(int element, int bits) +{ + if (bits) { + int maxN = (1 << bits) - 1; + // removing upper bits + element &= maxN; + // normalizing the number to [-1.0,1.0] + maxN >>= 1; + float output = (float) element / maxN; + if (output < -1.0f) output = -1.0f; + return output; + } else { + return 0.0f; + } +} + +float textureNormalizeElementUnsigned(unsigned int element, int bits) +{ + if (bits) { + unsigned int maxN = (1 << bits) - 1; + // removing upper bits and normalizing the number to [0.0,1.0] + return (float)(element & maxN) / maxN; + } else { + return 0.0f; + } +} + +void textureNormalizeOutput( const struct cudaChannelFormatDesc& desc, ptx_reg_t& datax, ptx_reg_t& datay, ptx_reg_t& dataz, ptx_reg_t& dataw ) +{ + if (desc.f == cudaChannelFormatKindSigned) { + datax.f32 = textureNormalizeElementSigned( datax.s32, desc.x ); + datay.f32 = textureNormalizeElementSigned( datay.s32, desc.y ); + dataz.f32 = textureNormalizeElementSigned( dataz.s32, desc.z ); + dataw.f32 = textureNormalizeElementSigned( dataw.s32, desc.w ); + } else if (desc.f == cudaChannelFormatKindUnsigned) { + datax.f32 = textureNormalizeElementUnsigned( datax.u32, desc.x ); + datay.f32 = textureNormalizeElementUnsigned( datay.u32, desc.y ); + dataz.f32 = textureNormalizeElementUnsigned( dataz.u32, desc.z ); + dataw.f32 = textureNormalizeElementUnsigned( dataw.u32, desc.w ); + } else { + assert(0 && "Undefined texture read mode: cudaReadModeNormalizedFloat expect integer elements"); + } +} + +void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + unsigned dimension = pI->dimension(); + const operand_info &dst = pI->dst(); //the registers to which fetched texel will be placed + const operand_info &src1 = pI->src1(); //the name of the texture + const operand_info &src2 = pI->src2(); //the vector registers containing coordinates of the texel to be fetched + + std::string texname = src1.name(); + unsigned to_type = pI->get_type(); + unsigned c_type = pI->get_type2(); + fflush(stdout); + ptx_reg_t data1, data2, data3, data4; + if (!ptx_tex_regs) ptx_tex_regs = new ptx_reg_t[4]; + unsigned nelem = src2.get_vect_nelem(); + thread->get_vector_operand_values(src2, ptx_tex_regs, nelem); //ptx_reg should be 4 entry vector type...coordinates into texture + + gpgpu_t *gpu = thread->get_gpu(); + const struct textureReference* texref = gpu->get_texref(texname); + const struct cudaArray* cuArray = gpu->get_texarray(texref); + const struct textureInfo* texInfo = gpu->get_texinfo(texref); + const struct textureReferenceAttr* texAttr = gpu->get_texattr(texref); + + //assume always 2D f32 input + //access array with src2 coordinates + memory_space *mem = thread->get_global_memory(); + float x_f32, y_f32; + size_t size; + int t; + unsigned tex_array_base; + unsigned int width = 0, height = 0; + int x = 0; + int y = 0; + unsigned tex_array_index; + float alpha=0, beta=0; + + type_info_key::type_decode(to_type,size,t); + tex_array_base = cuArray->devPtr32; + + switch (dimension) { + case GEOM_MODIFIER_1D: + width = cuArray->width; + height = cuArray->height; + if (texref->normalized) { + assert(c_type == F32_TYPE); + x_f32 = ptx_tex_regs[0].f32; + if (texref->addressMode[0] == cudaAddressModeClamp) { + x_f32 = (x_f32 > 1.0)? 1.0 : x_f32; + x_f32 = (x_f32 < 0.0)? 0.0 : x_f32; + } else if (texref->addressMode[0] == cudaAddressModeWrap) { + x_f32 = x_f32 - floor(x_f32); + } + + if( texref->filterMode == cudaFilterModeLinear ) { + float xb = x_f32 * width - 0.5; + alpha = xb - floor(xb); + alpha = reduce_precision(alpha,9); + beta = 0.0; + + x = (int)floor(xb); + y = 0; + } else { + x = (int) floor(x_f32 * width); + y = 0; + } + } else { + switch ( c_type ) { + case S32_TYPE: + x = ptx_tex_regs[0].s32; + assert(texref->filterMode == cudaFilterModePoint); + break; + case F32_TYPE: + x_f32 = ptx_tex_regs[0].f32; + alpha = x_f32 - floor(x_f32); // offset into subtexel (for linear sampling) + x = (int) x_f32; + break; + default: assert(0 && "Unsupported texture coordinate type."); + } + // handle texture fetch that exceeded boundaries + if (texref->addressMode[0] == cudaAddressModeClamp) { + x = (x > width - 1)? (width - 1) : x; + x = (x < 0)? 0 : x; + } else if (texref->addressMode[0] == cudaAddressModeWrap) { + x = x % width; + } + } + width *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; + x *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; + tex_array_index = tex_array_base + x; + + break; + case GEOM_MODIFIER_2D: + width = cuArray->width; + height = cuArray->height; + if (texref->normalized) { + x_f32 = reduce_precision(ptx_tex_regs[0].f32,16); + y_f32 = reduce_precision(ptx_tex_regs[1].f32,15); + + if (texref->addressMode[0]) {//clamp + if (x_f32<0) x_f32 = 0; + if (x_f32>=1) x_f32 = 1 - 1/x_f32; + } else {//wrap + x_f32 = x_f32 - floor(x_f32); + } + if (texref->addressMode[1]) {//clamp + if (y_f32<0) y_f32 = 0; + if (y_f32>=1) y_f32 = 1 - 1/y_f32; + } else {//wrap + y_f32 = y_f32 - floor(y_f32); + } + + if( texref->filterMode == cudaFilterModeLinear ) { + float xb = x_f32 * width - 0.5; + float yb = y_f32 * height - 0.5; + alpha = xb - floor(xb); + beta = yb - floor(yb); + alpha = reduce_precision(alpha,9); + beta = reduce_precision(beta,9); + + x = (int)floor(xb); + y = (int)floor(yb); + } else { + x = (int) floor(x_f32 * width); + y = (int) floor(y_f32 * height); + } + } else { + x_f32 = ptx_tex_regs[0].f32; + y_f32 = ptx_tex_regs[1].f32; + + alpha = x_f32 - floor(x_f32); + beta = y_f32 - floor(y_f32); + + x = (int) x_f32; + y = (int) y_f32; + if (texref->addressMode[0]) {//clamp + if (x<0) x = 0; + if (x>= (int)width) x = width-1; + } else {//wrap + x = x % width; + if (x < 0) x*= -1; + } + if (texref->addressMode[1]) {//clamp + if (y<0) y = 0; + if (y>= (int)height) y = height -1; + } else {//wrap + y = y % height; + if (y < 0) y *= -1; + } + } + + width *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; + x *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; + tex_array_index = tex_array_base + (x + width*y); + break; + default: + assert(0); break; + } + switch ( to_type ) { + case U8_TYPE: + case U16_TYPE: + case U32_TYPE: + case B8_TYPE: + case B16_TYPE: + case B32_TYPE: + case S8_TYPE: + case S16_TYPE: + case S32_TYPE: { + unsigned long long elementOffset = 0; // offset into the next element + mem->read( tex_array_index, cuArray->desc.x/8, &data1.u32); + elementOffset += cuArray->desc.x/8; + if (cuArray->desc.y) { + mem->read( tex_array_index + elementOffset, cuArray->desc.y/8, &data2.u32); + elementOffset += cuArray->desc.y/8; + if (cuArray->desc.z) { + mem->read( tex_array_index + elementOffset, cuArray->desc.z/8, &data3.u32); + elementOffset += cuArray->desc.z/8; + if (cuArray->desc.w) + mem->read( tex_array_index + elementOffset, cuArray->desc.w/8, &data4.u32); + } + } + break; + } + case B64_TYPE: + case U64_TYPE: + case S64_TYPE: + mem->read( tex_array_index, 8, &data1.u64); + if (cuArray->desc.y) { + mem->read( tex_array_index+8, 8, &data2.u64); + if (cuArray->desc.z) { + mem->read( tex_array_index+16, 8, &data3.u64); + if (cuArray->desc.w) + mem->read( tex_array_index+24, 8, &data4.u64); + } + } + break; + case F16_TYPE: assert(0); break; + case F32_TYPE: { + if( texref->filterMode == cudaFilterModeLinear ) { + texAddr_t b_lim = wrap; + if ( texref->addressMode[0] == cudaAddressModeClamp ) { + b_lim = clamp; + } + size_t elem_size = (cuArray->desc.x + cuArray->desc.y + cuArray->desc.z + cuArray->desc.w) / 8; + size_t elem_ofst = 0; + + data1.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); + elem_ofst += cuArray->desc.x / 8; + if (cuArray->desc.y) { + data2.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); + elem_ofst += cuArray->desc.y / 8; + if (cuArray->desc.z) { + data3.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); + elem_ofst += cuArray->desc.z / 8; + if (cuArray->desc.w) + data4.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); + } + } + } else { + mem->read( tex_array_index, cuArray->desc.x/8, &data1.f32); + if (cuArray->desc.y) { + mem->read( tex_array_index+4, cuArray->desc.y/8, &data2.f32); + if (cuArray->desc.z) { + mem->read( tex_array_index+8, cuArray->desc.z/8, &data3.f32); + if (cuArray->desc.w) + mem->read( tex_array_index+12, cuArray->desc.w/8, &data4.f32); + } + } + } + } break; + case F64_TYPE: + case FF64_TYPE: + mem->read( tex_array_index, 8, &data1.f64); + if (cuArray->desc.y) { + mem->read( tex_array_index+8, 8, &data2.f64); + if (cuArray->desc.z) { + mem->read( tex_array_index+16, 8, &data3.f64); + if (cuArray->desc.w) + mem->read( tex_array_index+24, 8, &data4.f64); + } + } + break; + default: assert(0); break; + } + int x_block_coord, y_block_coord, memreqindex, blockoffset; + + switch (dimension) { + case GEOM_MODIFIER_1D: + thread->m_last_effective_address = tex_array_index; + break; + case GEOM_MODIFIER_2D: + x_block_coord = x >> (texInfo->Tx_numbits + texInfo->texel_size_numbits); + y_block_coord = y >> texInfo->Ty_numbits; + + memreqindex = ((y_block_coord*cuArray->width/texInfo->Tx)+x_block_coord)<<6; + + blockoffset = (x%(texInfo->Tx*texInfo->texel_size) + (y%(texInfo->Ty)<<(texInfo->Tx_numbits + texInfo->texel_size_numbits))); + memreqindex += blockoffset; + thread->m_last_effective_address = tex_array_base + memreqindex;//tex_array_index; + break; + default: + assert(0); + } + thread->m_last_memory_space = tex_space; + + // normalize output into floating point numbers according to the texture read mode + if (texAttr->m_readmode == cudaReadModeNormalizedFloat) { + textureNormalizeOutput(cuArray->desc, data1, data2, data3, data4); + } else { + assert(texAttr->m_readmode == cudaReadModeElementType); + } + + thread->set_vector_operand_values(dst,data1,data2,data3,data4); +} + +void txq_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void trap_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vabsdiff_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vadd_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vmad_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vmax_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vmin_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vset_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vshl_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vshr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vsub_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } + +void vote_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + static bool first_in_warp = true; + static bool and_all; + static bool or_all; + static unsigned int ballot_result; + static std::list threads_in_warp; + static unsigned last_tid; + + if( first_in_warp ) { + first_in_warp = false; + threads_in_warp.clear(); + and_all = true; + or_all = false; + ballot_result = 0; + int offset=31; + while( (offset>=0) && !pI->active(offset) ) + offset--; + assert( offset >= 0 ); + last_tid = (thread->get_hw_tid() - (thread->get_hw_tid()%pI->warp_size())) + offset; + } + + ptx_reg_t src1_data; + const operand_info &src1 = pI->src1(); + src1_data = thread->get_operand_value(src1, pI->dst(), PRED_TYPE, thread, 1); + + //predicate value was changed so the lowest bit being set means the zero flag is set. + //As a result, the value of src1_data.pred must be inverted to get proper behavior + bool pred_value = !(src1_data.pred & 0x0001); + bool invert = src1.is_neg_pred(); + + threads_in_warp.push_back(thread); + and_all &= (invert ^ pred_value); + or_all |= (invert ^ pred_value); + + // vote.ballot + if (invert ^ pred_value) { + int lane_id = thread->get_hw_tid() % pI->warp_size(); + ballot_result |= (1 << lane_id); + } + + if( thread->get_hw_tid() == last_tid ) { + if (pI->vote_mode() == ptx_instruction::vote_ballot) { + ptx_reg_t data = ballot_result; + for( std::list::iterator t=threads_in_warp.begin(); t!=threads_in_warp.end(); ++t ) { + const operand_info &dst = pI->dst(); + (*t)->set_operand_value(dst,data, pI->get_type(), (*t), pI); + } + } else { + bool pred_value = false; + + switch( pI->vote_mode() ) { + case ptx_instruction::vote_any: pred_value = or_all; break; + case ptx_instruction::vote_all: pred_value = and_all; break; + case ptx_instruction::vote_uni: pred_value = (or_all ^ and_all); break; + default: + abort(); + } + ptx_reg_t data; + data.pred = pred_value?0:1; //the way ptxplus handles the zero flag, 1 = false and 0 = true + + for( std::list::iterator t=threads_in_warp.begin(); t!=threads_in_warp.end(); ++t ) { + const operand_info &dst = pI->dst(); + (*t)->set_operand_value(dst,data, PRED_TYPE, (*t), pI); + } + } + first_in_warp = true; + } +} + +void xor_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + //the way ptxplus handles predicates: 1 = false and 0 = true + if(i_type == PRED_TYPE) + data.pred = ~(~(src1_data.pred) ^ ~(src2_data.pred)); + else + data.u64 = src1_data.u64 ^ src2_data.u64; + + thread->set_operand_value(dst,data, i_type, thread, pI); +} + +void inst_not_implemented( const ptx_instruction * pI ) +{ + printf("GPGPU-Sim PTX: ERROR (%s:%u) instruction \"%s\" not (yet) implemented\n", + pI->source_file(), + pI->source_line(), + pI->get_opcode_cstr() ); + abort(); +} + +ptx_reg_t srcOperandModifiers(ptx_reg_t opData, operand_info opInfo, operand_info dstInfo, unsigned type, ptx_thread_info *thread) +{ + ptx_reg_t result; + memory_space *mem = NULL; + size_t size; + int t; + result.u64=0; + + //complete other cases for reading from memory, such as reading from other const memory + if(opInfo.get_addr_space() == global_space) + { + mem = thread->get_global_memory(); + type_info_key::type_decode(type,size,t); + mem->read(opData.u32,size/8,&result.u64); + if( type == S16_TYPE || type == S32_TYPE ) + sign_extend(result,size,dstInfo); + } + else if(opInfo.get_addr_space() == shared_space) + { + mem = thread->m_shared_mem; + type_info_key::type_decode(type,size,t); + mem->read(opData.u32,size/8,&result.u64); + + if( type == S16_TYPE || type == S32_TYPE ) + sign_extend(result,size,dstInfo); + + } + else if(opInfo.get_addr_space() == const_space) + { + mem = thread->get_global_memory(); + type_info_key::type_decode(type,size,t); + + mem->read((opData.u32 + opInfo.get_const_mem_offset()),size/8,&result.u64); + + if( type == S16_TYPE || type == S32_TYPE ) + sign_extend(result,size,dstInfo); + } + else + { + result = opData; + } + + if(opInfo.get_operand_lohi() == 1) + { + result.u64 = result.u64 & 0xFFFF; + } + else if(opInfo.get_operand_lohi() == 2) + { + result.u64 = (result.u64>>16) & 0xFFFF; + } + + if(opInfo.get_operand_neg() == true) { + result.f32 = -result.f32; + } + + return result; +} + diff --git a/src/cuda-sim/ptx_loader.cc~ b/src/cuda-sim/ptx_loader.cc~ new file mode 100644 index 0000000..c922b18 --- /dev/null +++ b/src/cuda-sim/ptx_loader.cc~ @@ -0,0 +1,462 @@ +// Copyright (c) 2009-2011, Tor M. Aamodt +// The University of British Columbia +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// Redistributions in binary form must reproduce the above copyright notice, this +// list of conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. +// Neither the name of The University of British Columbia nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#include "ptx_loader.h" +#include "ptx_ir.h" +#include "cuda-sim.h" +#include "ptx_parser.h" +#include +#include +#include +#include + +/// globals + +memory_space *g_global_mem; +memory_space *g_tex_mem; +memory_space *g_surf_mem; +memory_space *g_param_mem; +bool g_override_embedded_ptx = false; + +/// extern prototypes + +extern int ptx_parse(); +extern int ptx__scan_string(const char*); + +extern std::map get_duplicate(); + +const char *g_ptxinfo_filename; +extern int ptxinfo_parse(); +extern int ptxinfo_debug; +extern FILE *ptxinfo_in; + +static bool g_save_embedded_ptx; +bool g_keep_intermediate_files; +bool m_ptx_save_converted_ptxplus; + +bool keep_intermediate_files() {return g_keep_intermediate_files;} + +void ptx_reg_options(option_parser_t opp) +{ + option_parser_register(opp, "-save_embedded_ptx", OPT_BOOL, &g_save_embedded_ptx, + "saves ptx files embedded in binary as .ptx", + "0"); + option_parser_register(opp, "-keep", OPT_BOOL, &g_keep_intermediate_files, + "keep intermediate files created by GPGPU-Sim when interfacing with external programs", + "0"); + option_parser_register(opp, "-gpgpu_ptx_save_converted_ptxplus", OPT_BOOL, + &m_ptx_save_converted_ptxplus, + "Saved converted ptxplus to a file", + "0"); +} + +void print_ptx_file( const char *p, unsigned source_num, const char *filename ) +{ + printf("\nGPGPU-Sim PTX: file _%u.ptx contents:\n\n", source_num ); + char *s = strdup(p); + char *t = s; + unsigned n=1; + while ( *t != '\0' ) { + char *u = t; + while ( (*u != '\n') && (*u != '\0') ) u++; + unsigned last = (*u == '\0'); + *u = '\0'; + const ptx_instruction *pI = ptx_instruction_lookup(filename,n); + char pc[64]; + if( pI && pI->get_PC() ) + snprintf(pc,64,"%4u", pI->get_PC() ); + else + snprintf(pc,64," "); + printf(" _%u.ptx %4u (pc=%s): %s\n", source_num, n, pc, t ); + if ( last ) break; + t = u+1; + n++; + } + free(s); + fflush(stdout); +} + +char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptxfilename, const std::string elffilename, const std::string sassfilename) +{ + + printf("GPGPU-Sim PTX: converting EMBEDDED .ptx file to ptxplus \n"); + + char fname_ptxplus[1024]; + snprintf(fname_ptxplus,1024,"_ptxplus_XXXXXX"); + int fd4=mkstemp(fname_ptxplus); + close(fd4); + + // Run cuobjdump_to_ptxplus + char commandline[1024]; + int result; + snprintf(commandline, 1024, "$GPGPUSIM_ROOT/build/$GPGPUSIM_CONFIG/cuobjdump_to_ptxplus/cuobjdump_to_ptxplus %s %s %s %s", + ptxfilename.c_str(), + sassfilename.c_str(), + elffilename.c_str(), + fname_ptxplus); + fflush(stdout); + printf("GPGPU-Sim PTX: calling cuobjdump_to_ptxplus\ncommandline: %s\n", commandline); + result = system(commandline); + if(result){printf("GPGPU-Sim PTX: ERROR ** could not execute %s\n", commandline); exit(1);} + + + // Get ptxplus from file + std::ifstream fileStream(fname_ptxplus, std::ios::in); + std::string text, line; + while(getline(fileStream,line)) { + text += (line + "\n"); + } + fileStream.close(); + + char* ptxplus_str = new char [strlen(text.c_str())+1]; + strcpy(ptxplus_str, text.c_str()); + + if (!m_ptx_save_converted_ptxplus){ + char rm_commandline[1024]; + + snprintf(rm_commandline,1024,"rm -f %s", fname_ptxplus); + + printf("GPGPU-Sim PTX: removing temporary files using \"%s\"\n", rm_commandline); + int rm_result = system(rm_commandline); + if( rm_result != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while removing temporary files %d\n", rm_result); + exit(1); + } + } + printf("GPGPU-Sim PTX: DONE converting EMBEDDED .ptx file to ptxplus \n"); + + return ptxplus_str; +} + + +symbol_table *gpgpu_ptx_sim_load_ptx_from_string( const char *p, unsigned source_num ) +{ + char buf[1024]; + snprintf(buf,1024,"_%u.ptx", source_num ); + if( g_save_embedded_ptx ) { + FILE *fp = fopen(buf,"w"); + fprintf(fp,"%s",p); + fclose(fp); + } + symbol_table *symtab=init_parser(buf); + ptx__scan_string(p); + int errors = ptx_parse (); + if ( errors ) { + char fname[1024]; + snprintf(fname,1024,"_ptx_errors_XXXXXX"); + int fd=mkstemp(fname); + close(fd); + printf("GPGPU-Sim PTX: parser error detected, exiting... but first extracting .ptx to \"%s\"\n", fname); + FILE *ptxfile = fopen(fname,"w"); + fprintf(ptxfile,"%s", p ); + fclose(ptxfile); + abort(); + exit(40); + } + + //if ( g_debug_execution >= 100 ) + print_ptx_file(p,source_num,buf); + + printf("GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file %s\n",buf); + return symtab; +} + +void fix_duplicate_errors(char fname2[1024]) { + char tempfile[1024] = "_temp_ptx"; + char commandline[1024]; + + // change the name of the ptx file to _temp_ptx + snprintf(commandline,1024,"mv %s %s",fname2,tempfile); + printf("Running: %s\n", commandline); + int result = system(commandline); + if (result != 0) { + printf("GPGPU-Sim PTX: ERROR ** while changing filename from %s to %s", fname2, tempfile); + exit(1); + } + + // store all of the ptx into a char array + FILE *ptxsource = fopen(tempfile,"r"); + fseek(ptxsource, 0, SEEK_END); + long filesize = ftell(ptxsource); + rewind(ptxsource); + char *ptxdata = (char*)malloc((filesize+1)*sizeof(char)); + fread(ptxdata, filesize, 1, ptxsource); + fclose(ptxsource); + + FILE *ptxdest = fopen(fname2,"w"); + std::map duplicate = get_duplicate(); + unsigned offset; + unsigned oldlinenum = 1; + unsigned linenum; + char *startptr = ptxdata; + char *funcptr; + char *tempptr = ptxdata - 1; + char *lineptr = ptxdata - 1; + + // recreate the ptx file without duplications + for ( std::map::iterator iter = duplicate.begin(); + iter != duplicate.end(); + iter++){ + // find the line of the next error + linenum = iter->first; + for (int i = oldlinenum; i < linenum; i++) { + lineptr = strchr(lineptr + 1, '\n'); + } + + // find the end of the current section to be copied over + // then find the start of the next section that will be copied + if (strcmp("function", iter->second) == 0) { + // get location of most recent .func + while (tempptr < lineptr && tempptr != NULL) { + funcptr = tempptr; + tempptr = strstr(funcptr + 1, ".func"); + } + + // get the start of the previous line + offset = 0; + while (*(funcptr - offset) != '\n') offset++; + + fwrite(startptr, sizeof(char), funcptr - offset + 1 - startptr, ptxdest); + + //find next location of startptr + if (*(lineptr + 3) == ';') { + // for function definitions + startptr = lineptr + 5; + } else if (*(lineptr + 3) == '{') { + // for functions enclosed with curly brackets + offset = 5; + unsigned bracket = 1; + while (bracket != 0) { + if (*(lineptr + offset) == '{') bracket++; + else if (*(lineptr + offset) == '}') bracket--; + offset++; + } + startptr = lineptr + offset + 1; + } else { + printf("GPGPU-Sim PTX: ERROR ** Unrecognized function format\n"); + abort(); + } + } else if (strcmp("variable", iter->second) == 0) { + fwrite(startptr, sizeof(char), (int)(lineptr + 1 - startptr), ptxdest); + + //find next location of startptr + offset = 1; + while (*(lineptr + offset) != '\n') offset++; + startptr = lineptr + offset + 1; + } else { + printf("GPGPU-Sim PTX: ERROR ** Unsupported duplicate type: %s\n", iter->second); + } + + oldlinenum = linenum; + } + // copy over the rest of the file + fwrite(startptr, sizeof(char), ptxdata + filesize - startptr, ptxdest); + + // cleanup + free(ptxdata); + fclose(ptxdest); + snprintf(commandline,1024,"rm -f %s",tempfile); + printf("Running: %s\n", commandline); + result = system(commandline); + if (result != 0) { + printf("GPGPU-Sim PTX: ERROR ** while deleting %s", tempfile); + exit(1); + } +} + +//we need the application name here too. +char* get_app_binary_name(){ + char exe_path[1025]; + char *self_exe_path; +#ifdef __APPLE__ + //AMRUTH: get apple device and check the result. + printf("WARNING: not tested for Apple-mac devices \n"); + abort(); +#else + std::stringstream exec_link; + exec_link << "/proc/self/exe"; + ssize_t path_length = readlink(exec_link.str().c_str(), exe_path, 1024); + assert(path_length != -1); + exe_path[path_length] = '\0'; + + char *token = strtok(exe_path, "/"); + while(token !=NULL){ + self_exe_path = token; + token = strtok(NULL,"/"); + } +#endif + self_exe_path = strtok(self_exe_path, "."); + printf("self exe links to: %s\n", self_exe_path); + return self_exe_path; +} + +void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version ) +{ + //do ptxas for individual files instead of one big embedded ptx. This prevents the duplicate defs and declarations. + char ptx_file[1000]; + char *name=get_app_binary_name(); + char commandline[4096], fname[1024], fname2[1024], final_tempfile_ptxinfo[1024], tempfile_ptxinfo[1024]; + for (int index=1; index <= no_of_ptx; index++){ + snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", name, index, sm_version); + snprintf(fname,1024,"_ptx_XXXXXX"); + int fd=mkstemp(fname); + close(fd); + + printf("GPGPU-Sim PTX: extracting embedded .ptx to temporary file \"%s\"\n", fname); + snprintf(commandline,4096,"cat %s > %s",ptx_file, fname); + if (system(commandline) !=0) { + printf("ERROR: %s command failed\n", commandline); + exit(0); + } + + snprintf(fname2,1024,"_ptx2_XXXXXX"); + fd=mkstemp(fname2); + close(fd); + char commandline2[4096]; + snprintf(commandline2,4096,"cat %s | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\\(\\.extern \\.const\\[1\\] .b8 \\w\\+\\)\\[\\]/\\1\\[1\\]/' | sed 's/const\\[.\\]/const\\[0\\]/g' > %s", fname, fname2); + printf("Running: %s\n", commandline2); + int result = system(commandline2); + if( result != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); + printf(" Ensure you have write access to simulation directory\n"); + printf(" and have \'cat\' and \'sed\' in your path.\n"); + exit(1); + } + + snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); + char extra_flags[1024]; + extra_flags[0]=0; + + #if CUDART_VERSION >= 3000 + if (sm_version == 0) sm_version = 20; + extern bool g_cdp_enabled; + if(!g_cdp_enabled) + snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); + else + snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version); + #endif + + snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", + extra_flags, fname2, tempfile_ptxinfo); + printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); + result = system(commandline); + if( result != 0 ) { + // 65280 = duplicate errors + if (result == 65280) { + ptxinfo_in = fopen(tempfile_ptxinfo,"r"); + g_ptxinfo_filename = tempfile_ptxinfo; + ptxinfo_parse(); + + fix_duplicate_errors(fname2); + snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", + extra_flags, fname2, tempfile_ptxinfo); + printf("GPGPU-Sim PTX: regenerating ptxinfo using \"%s\"\n", commandline); + result = system(commandline); + } + if (result != 0) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); + printf(" Ensure ptxas is in your path.\n"); + exit(1); + } + } + } + + //TODO: duplicate code! move it into a function so that it can be reused! + if(no_of_ptx==0) { + //For CDP, we dump everything. So no_of_ptx will be 0. + snprintf(fname,1024,"_ptx_XXXXXX"); + int fd=mkstemp(fname); + close(fd); + + printf("GPGPU-Sim PTX: extracting embedded .ptx to temporary file \"%s\"\n", fname); + FILE *ptxfile = fopen(fname,"w"); + fprintf(ptxfile,"%s", p_for_info); + fclose(ptxfile); + + snprintf(fname2,1024,"_ptx2_XXXXXX"); + fd=mkstemp(fname2); + close(fd); + char commandline2[4096]; + snprintf(commandline2,4096,"cat %s | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\\(\\.extern \\.const\\[1\\] .b8 \\w\\+\\)\\[\\]/\\1\\[1\\]/' | sed 's/const\\[.\\]/const\\[0\\]/g' > %s", fname, fname2); + printf("Running: %s\n", commandline2); + int result = system(commandline2); + if( result != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); + printf(" Ensure you have write access to simulation directory\n"); + printf(" and have \'cat\' and \'sed\' in your path.\n"); + exit(1); + } + //char tempfile_ptxinfo[1024]; + snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); + char extra_flags[1024]; + extra_flags[0]=0; +#if CUDART_VERSION >= 3000 + snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); +#endif + + snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", + extra_flags, fname2, tempfile_ptxinfo); + printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); + result = system(commandline); + if( result != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); + printf(" Ensure ptxas is in your path.\n"); + exit(1); + } + } + + //Now that we got resource usage per kernel in a ptx file, we dump all into one file and pass it to rest of the code as usual. + if(no_of_ptx>0){ + char commandline3[4096]; + snprintf(final_tempfile_ptxinfo,1024,"f_tempfile_ptx"); + snprintf(commandline3,4096, "cat *info > %s", final_tempfile_ptxinfo); + if (system(commandline3)!=0) { + printf("ERROR: Either we dont have info files or cat is not working \n"); + printf("ERROR: %s command failed\n",commandline3); + exit(1); + } + } + + ptxinfo_in = fopen(final_tempfile_ptxinfo,"r"); + if(no_of_ptx>0) + g_ptxinfo_filename = final_tempfile_ptxinfo; + else + g_ptxinfo_filename = tempfile_ptxinfo; + ptxinfo_parse(); + + if( ! g_save_embedded_ptx ) { + if(no_of_ptx>0) + snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, final_tempfile_ptxinfo); + else + snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, tempfile_ptxinfo); + printf("GPGPU-Sim PTX: removing ptxinfo using \"%s\"\n", commandline); + if( system(commandline) != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while removing temporary files\n"); + exit(1); + } + } +} -- cgit v1.3 -- cgit v1.3 From f9c42bd10a37b2e7556f006641eff11090762e7e Mon Sep 17 00:00:00 2001 From: Amruth Date: Tue, 3 Apr 2018 12:02:34 -0700 Subject: remove temporarily generated files --- libcuda/cuda_runtime_api.cc~ | 2515 ----------------------- src/cuda-sim/cuda-sim.cc~ | 2155 -------------------- src/cuda-sim/instructions.cc~ | 4517 ----------------------------------------- src/cuda-sim/ptx_loader.cc~ | 462 ----- 4 files changed, 9649 deletions(-) delete mode 100644 libcuda/cuda_runtime_api.cc~ delete mode 100644 src/cuda-sim/cuda-sim.cc~ delete mode 100644 src/cuda-sim/instructions.cc~ delete mode 100644 src/cuda-sim/ptx_loader.cc~ diff --git a/libcuda/cuda_runtime_api.cc~ b/libcuda/cuda_runtime_api.cc~ deleted file mode 100644 index de7f5e9..0000000 --- a/libcuda/cuda_runtime_api.cc~ +++ /dev/null @@ -1,2515 +0,0 @@ -// This file created from cuda_runtime_api.h distributed with CUDA 1.1 -// Changes Copyright 2009, Tor M. Aamodt, Ali Bakhoda and George L. Yuan -// University of British Columbia - -/* - * cuda_runtime_api.cc - * - * Copyright © 2009 by Tor M. Aamodt, Wilson W. L. Fung, Ali Bakhoda, - * George L. Yuan and the University of British Columbia, Vancouver, - * BC V6T 1Z4, All Rights Reserved. - * - * THIS IS A LEGAL DOCUMENT BY DOWNLOADING GPGPU-SIM, YOU ARE AGREEING TO THESE - * TERMS AND CONDITIONS. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNERS OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * NOTE: The files libcuda/cuda_runtime_api.c and src/cuda-sim/cuda-math.h - * are derived from the CUDA Toolset available from http://www.nvidia.com/cuda - * (property of NVIDIA). The files benchmarks/BlackScholes/ and - * benchmarks/template/ are derived from the CUDA SDK available from - * http://www.nvidia.com/cuda (also property of NVIDIA). The files from - * src/intersim/ are derived from Booksim (a simulator provided with the - * textbook "Principles and Practices of Interconnection Networks" available - * from http://cva.stanford.edu/books/ppin/). As such, those files are bound by - * the corresponding legal terms and conditions set forth separately (original - * copyright notices are left in files from these sources and where we have - * modified a file our copyright notice appears before the original copyright - * notice). - * - * Using this version of GPGPU-Sim requires a complete installation of CUDA - * which is distributed seperately by NVIDIA under separate terms and - * conditions. To use this version of GPGPU-Sim with OpenCL requires a - * recent version of NVIDIA's drivers which support OpenCL. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the University of British Columbia nor the names of - * its contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * 4. This version of GPGPU-SIM is distributed freely for non-commercial use only. - * - * 5. No nonprofit user may place any restrictions on the use of this software, - * including as modified by the user, by any other authorized user. - * - * 6. GPGPU-SIM was developed primarily by Tor M. Aamodt, Wilson W. L. Fung, - * Ali Bakhoda, George L. Yuan, at the University of British Columbia, - * Vancouver, BC V6T 1Z4 - */ - -/* - * Copyright 1993-2007 NVIDIA Corporation. All rights reserved. - * - * NOTICE TO USER: - * - * This source code is subject to NVIDIA ownership rights under U.S. and - * international Copyright laws. Users and possessors of this source code - * are hereby granted a nonexclusive, royalty-free license to use this code - * in individual and commercial software. - * - * NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE - * CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR - * IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH - * REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE. - * IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, - * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS - * OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE - * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE - * OR PERFORMANCE OF THIS SOURCE CODE. - * - * U.S. Government End Users. This source code is a "commercial item" as - * that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of - * "commercial computer software" and "commercial computer software - * documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995) - * and is provided to the U.S. Government only as a commercial end item. - * Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through - * 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the - * source code with only those rights set forth herein. - * - * Any use of this source code in individual and commercial software must - * include, in the user documentation and internal comments to the code, - * the above Disclaimer and U.S. Government End Users Notice. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef OPENGL_SUPPORT -#define GL_GLEXT_PROTOTYPES -#ifdef __APPLE__ -#include // Apple's version of GLUT is here -#else -#include -#endif -#endif - -#define __CUDA_RUNTIME_API_H__ - -#include "host_defines.h" -#include "builtin_types.h" -#include "driver_types.h" -#if (CUDART_VERSION < 8000) -#include "__cudaFatFormat.h" -#endif -#include "../src/gpgpu-sim/gpu-sim.h" -#include "../src/cuda-sim/ptx_loader.h" -#include "../src/cuda-sim/cuda-sim.h" -#include "../src/cuda-sim/ptx_ir.h" -#include "../src/cuda-sim/ptx_parser.h" -#include "../src/gpgpusim_entrypoint.h" -#include "../src/stream_manager.h" -#include "../src/abstract_hardware_model.h" - -#include -#include - -#ifdef __APPLE__ -#include -#endif - -std::map pinned_memory; //support for pinned memories added -std::map pinned_memory_size; -int no_of_ptx=0; - -extern void synchronize(); -extern void exit_simulation(); - -static int load_static_globals( symbol_table *symtab, unsigned min_gaddr, unsigned max_gaddr, gpgpu_t *gpu ); -static int load_constants( symbol_table *symtab, addr_t min_gaddr, gpgpu_t *gpu ); - -static kernel_info_t *gpgpu_cuda_ptx_sim_init_grid( const char *kernel_key, - gpgpu_ptx_sim_arg_list_t args, - struct dim3 gridDim, - struct dim3 blockDim, - struct CUctx_st* context ); - -/*DEVICE_BUILTIN*/ -struct cudaArray -{ - void *devPtr; - int devPtr32; - struct cudaChannelFormatDesc desc; - int width; - int height; - int size; //in bytes - unsigned dimensions; -}; - -#if !defined(__dv) -#if defined(__cplusplus) -#define __dv(v) \ - = v -#else /* __cplusplus */ -#define __dv(v) -#endif /* __cplusplus */ -#endif /* !__dv */ - -cudaError_t g_last_cudaError = cudaSuccess; - -extern stream_manager *g_stream_manager; - -void register_ptx_function( const char *name, function_info *impl ) -{ - // no longer need this -} - -#if defined __APPLE__ -# define __my_func__ __PRETTY_FUNCTION__ -#else -# if defined __cplusplus ? __GNUC_PREREQ (2, 6) : __GNUC_PREREQ (2, 4) -# define __my_func__ __PRETTY_FUNCTION__ -# else -# if defined __STDC_VERSION__ && __STDC_VERSION__ >= 199901L -# define __my_func__ __func__ -# else -# define __my_func__ ((__const char *) 0) -# endif -# endif -#endif - -struct _cuda_device_id { - _cuda_device_id(gpgpu_sim* gpu) {m_id = 0; m_next = NULL; m_gpgpu=gpu;} - struct _cuda_device_id *next() { return m_next; } - unsigned num_shader() const { return m_gpgpu->get_config().num_shader(); } - int num_devices() const { - if( m_next == NULL ) return 1; - else return 1 + m_next->num_devices(); - } - struct _cuda_device_id *get_device( unsigned n ) - { - assert( n < (unsigned)num_devices() ); - struct _cuda_device_id *p=this; - for(unsigned i=0; im_next; - return p; - } - const struct cudaDeviceProp *get_prop() const - { - return m_gpgpu->get_prop(); - } - unsigned get_id() const { return m_id; } - - gpgpu_sim *get_gpgpu() { return m_gpgpu; } -private: - unsigned m_id; - class gpgpu_sim *m_gpgpu; - struct _cuda_device_id *m_next; -}; - -struct CUctx_st { - CUctx_st( _cuda_device_id *gpu ) - { - m_gpu = gpu; - m_binary_info.cmem = 0; - m_binary_info.gmem = 0; - } - - _cuda_device_id *get_device() { return m_gpu; } - - void add_binary( symbol_table *symtab, unsigned fat_cubin_handle ) - { - m_code[fat_cubin_handle] = symtab; - m_last_fat_cubin_handle = fat_cubin_handle; - } - - void add_ptxinfo( const char *deviceFun, const struct gpgpu_ptx_sim_info &info ) - { - symbol *s = m_code[m_last_fat_cubin_handle]->lookup(deviceFun); - assert( s != NULL ); - function_info *f = s->get_pc(); - assert( f != NULL ); - f->set_kernel_info(info); - } - - void add_ptxinfo( const struct gpgpu_ptx_sim_info &info ) - { - m_binary_info = info; - } - - void register_function( unsigned fat_cubin_handle, const char *hostFun, const char *deviceFun ) - { - if( m_code.find(fat_cubin_handle) != m_code.end() ) { - symbol *s = m_code[fat_cubin_handle]->lookup(deviceFun); - if(s != NULL) { - function_info *f = s->get_pc(); - assert( f != NULL ); - m_kernel_lookup[hostFun] = f; - } - else { - printf("Warning: cannot find deviceFun %s\n", deviceFun); - m_kernel_lookup[hostFun] = NULL; - } - // assert( s != NULL ); - // function_info *f = s->get_pc(); - // assert( f != NULL ); - // m_kernel_lookup[hostFun] = f; - } else { - m_kernel_lookup[hostFun] = NULL; - } - } - - function_info *get_kernel(const char *hostFun) - { - std::map::iterator i=m_kernel_lookup.find(hostFun); - assert( i != m_kernel_lookup.end() ); - return i->second; - } - -private: - _cuda_device_id *m_gpu; // selected gpu - std::map m_code; // fat binary handle => global symbol table - unsigned m_last_fat_cubin_handle; - std::map m_kernel_lookup; // unique id (CUDA app function address) => kernel entry point - struct gpgpu_ptx_sim_info m_binary_info; - -}; - -class kernel_config { -public: - kernel_config( dim3 GridDim, dim3 BlockDim, size_t sharedMem, struct CUstream_st *stream ) - { - m_GridDim=GridDim; - m_BlockDim=BlockDim; - m_sharedMem=sharedMem; - m_stream = stream; - } - void set_arg( const void *arg, size_t size, size_t offset ) - { - m_args.push_front( gpgpu_ptx_sim_arg(arg,size,offset) ); - } - dim3 grid_dim() const { return m_GridDim; } - dim3 block_dim() const { return m_BlockDim; } - gpgpu_ptx_sim_arg_list_t get_args() { return m_args; } - struct CUstream_st *get_stream() { return m_stream; } - -private: - dim3 m_GridDim; - dim3 m_BlockDim; - size_t m_sharedMem; - struct CUstream_st *m_stream; - gpgpu_ptx_sim_arg_list_t m_args; -}; - -class _cuda_device_id *GPGPUSim_Init() -{ - static _cuda_device_id *the_device = NULL; - if( !the_device ) { - gpgpu_sim *the_gpu = gpgpu_ptx_sim_init_perf(); - - cudaDeviceProp *prop = (cudaDeviceProp *) calloc(sizeof(cudaDeviceProp),1); - snprintf(prop->name,256,"GPGPU-Sim_v%s", g_gpgpusim_version_string ); - prop->major = 5; - prop->minor = 2; - prop->totalGlobalMem = 0x80000000 /* 2 GB */; - prop->memPitch = 0; - prop->maxThreadsPerBlock = 512; - prop->maxThreadsDim[0] = 512; - prop->maxThreadsDim[1] = 512; - prop->maxThreadsDim[2] = 512; - prop->maxGridSize[0] = 0x40000000; - prop->maxGridSize[1] = 0x40000000; - prop->maxGridSize[2] = 0x40000000; - prop->totalConstMem = 0x40000000; - prop->textureAlignment = 0; - prop->sharedMemPerBlock = the_gpu->shared_mem_size(); - prop->regsPerBlock = the_gpu->num_registers_per_core(); - prop->warpSize = the_gpu->wrp_size(); - prop->clockRate = the_gpu->shader_clock(); -#if (CUDART_VERSION >= 2010) - prop->multiProcessorCount = the_gpu->get_config().num_shader(); -#endif - the_gpu->set_prop(prop); - the_device = new _cuda_device_id(the_gpu); - } - start_sim_thread(1); - return the_device; -} - -static CUctx_st* GPGPUSim_Context() -{ - static CUctx_st *the_context = NULL; - if( the_context == NULL ) { - _cuda_device_id *the_gpu = GPGPUSim_Init(); - the_context = new CUctx_st(the_gpu); - } - return the_context; -} - - void ptxinfo_addinfo() -{ - if(!get_ptxinfo_kname()){ - /* This info is not per kernel (since CUDA 5.0 some info (e.g. gmem, and cmem) is added at the beginning for the whole binary ) */ - CUctx_st *context = GPGPUSim_Context(); - print_ptxinfo(); - context->add_ptxinfo(get_ptxinfo()); - clear_ptxinfo(); - return; - } - if( !strcmp("__cuda_dummy_entry__",get_ptxinfo_kname()) ) { - // this string produced by ptxas for empty ptx files (e.g., bandwidth test) - clear_ptxinfo(); - return; - } - CUctx_st *context = GPGPUSim_Context(); - print_ptxinfo(); - context->add_ptxinfo( get_ptxinfo_kname(), get_ptxinfo() ); - clear_ptxinfo(); -} - -void cuda_not_implemented( const char* func, unsigned line ) -{ - fflush(stdout); - fflush(stderr); - printf("\n\nGPGPU-Sim PTX: Execution error: CUDA API function \"%s()\" has not been implemented yet.\n" - " [$GPGPUSIM_ROOT/libcuda/%s around line %u]\n\n\n", - func,__FILE__, line ); - fflush(stdout); - abort(); -} - - -#define gpgpusim_ptx_error(msg, ...) gpgpusim_ptx_error_impl(__func__, __FILE__,__LINE__, msg, ##__VA_ARGS__) -#define gpgpusim_ptx_assert(cond,msg, ...) gpgpusim_ptx_assert_impl((cond),__func__, __FILE__,__LINE__, msg, ##__VA_ARGS__) - -void gpgpusim_ptx_error_impl( const char *func, const char *file, unsigned line, const char *msg, ... ) -{ - va_list ap; - char buf[1024]; - va_start(ap,msg); - vsnprintf(buf,1024,msg,ap); - va_end(ap); - - printf("GPGPU-Sim CUDA API: %s\n", buf); - printf(" [%s:%u : %s]\n", file, line, func ); - abort(); -} - -void gpgpusim_ptx_assert_impl( int test_value, const char *func, const char *file, unsigned line, const char *msg, ... ) -{ - va_list ap; - char buf[1024]; - va_start(ap,msg); - vsnprintf(buf,1024,msg,ap); - va_end(ap); - - if ( test_value == 0 ) - gpgpusim_ptx_error_impl(func, file, line, msg); -} - - -typedef std::map event_tracker_t; - -int CUevent_st::m_next_event_uid; -event_tracker_t g_timer_events; -int g_active_device = 0; //active gpu that runs the code -std::list g_cuda_launch_stack; - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -extern "C" { - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ -cudaError_t cudaPeekAtLastError(void) -{ - return g_last_cudaError; -} - -__host__ cudaError_t CUDARTAPI cudaMalloc(void **devPtr, size_t size) -{ - CUctx_st* context = GPGPUSim_Context(); - *devPtr = context->get_device()->get_gpgpu()->gpu_malloc(size); - if(g_debug_execution >= 3) - printf("GPGPU-Sim PTX: cudaMallocing %zu bytes starting at 0x%llx..\n",size, (unsigned long long) *devPtr); - if ( *devPtr ) { - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorMemoryAllocation; - } -} - -__host__ cudaError_t CUDARTAPI cudaMallocHost(void **ptr, size_t size) -{ - GPGPUSim_Context(); - *ptr = malloc(size); - if ( *ptr ) { - //track pinned memory size allocated in the host so that same amount of memory is also allocated in GPU. - pinned_memory_size[*ptr]=size; - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorMemoryAllocation; - } -} -__host__ cudaError_t CUDARTAPI cudaMallocPitch(void **devPtr, size_t *pitch, size_t width, size_t height) -{ - unsigned malloc_width_inbytes = width; - printf("GPGPU-Sim PTX: cudaMallocPitch (width = %d)\n", malloc_width_inbytes); - CUctx_st* ctx = GPGPUSim_Context(); - *devPtr = ctx->get_device()->get_gpgpu()->gpu_malloc(malloc_width_inbytes*height); - pitch[0] = malloc_width_inbytes; - if ( *devPtr ) { - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorMemoryAllocation; - } -} - -__host__ cudaError_t CUDARTAPI cudaMallocArray(struct cudaArray **array, const struct cudaChannelFormatDesc *desc, size_t width, size_t height __dv(1)) -{ - unsigned size = width * height * ((desc->x + desc->y + desc->z + desc->w)/8); - CUctx_st* context = GPGPUSim_Context(); - (*array) = (struct cudaArray*) malloc(sizeof(struct cudaArray)); - (*array)->desc = *desc; - (*array)->width = width; - (*array)->height = height; - (*array)->size = size; - (*array)->dimensions = 2; - ((*array)->devPtr32)= (int) (long long)context->get_device()->get_gpgpu()->gpu_mallocarray(size); - printf("GPGPU-Sim PTX: cudaMallocArray: devPtr32 = %d\n", ((*array)->devPtr32)); - ((*array)->devPtr) = (void*) (long long) ((*array)->devPtr32); - if ( ((*array)->devPtr) ) { - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorMemoryAllocation; - } -} - -__host__ cudaError_t CUDARTAPI cudaFree(void *devPtr) -{ - // TODO... manage g_global_mem space? - return g_last_cudaError = cudaSuccess; -} -__host__ cudaError_t CUDARTAPI cudaFreeHost(void *ptr) -{ - free (ptr); // this will crash the system if called twice - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaFreeArray(struct cudaArray *array) -{ - // TODO... manage g_global_mem space? - return g_last_cudaError = cudaSuccess; -}; - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaMemcpy(void *dst, const void *src, size_t count, enum cudaMemcpyKind kind) -{ - //CUctx_st *context = GPGPUSim_Context(); - //gpgpu_t *gpu = context->get_device()->get_gpgpu(); - if(g_debug_execution >= 3) - printf("GPGPU-Sim PTX: cudaMemcpy(): devPtr = %p\n", dst); - if( kind == cudaMemcpyHostToDevice ) - g_stream_manager->push( stream_operation(src,(size_t)dst,count,0) ); - else if( kind == cudaMemcpyDeviceToHost ) - g_stream_manager->push( stream_operation((size_t)src,dst,count,0) ); - else if( kind == cudaMemcpyDeviceToDevice ) - g_stream_manager->push( stream_operation((size_t)src,(size_t)dst,count,0) ); - else if ( kind == cudaMemcpyDefault ) { - if ((size_t)src >= GLOBAL_HEAP_START) { - if ((size_t)dst >= GLOBAL_HEAP_START) - g_stream_manager->push( stream_operation((size_t)src,(size_t)dst,count,0) ); // device to device - else - g_stream_manager->push( stream_operation((size_t)src,dst,count,0) ); // device to host - } - else { - if ((size_t)dst >= GLOBAL_HEAP_START) - g_stream_manager->push( stream_operation(src,(size_t)dst,count,0) ); - else { - printf("GPGPU-Sim PTX: cudaMemcpy - ERROR : unsupported transfer: host to host\n"); - abort(); - } - } - } - else { - printf("GPGPU-Sim PTX: cudaMemcpy - ERROR : unsupported cudaMemcpyKind\n"); - abort(); - } - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaMemcpyToArray(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t count, enum cudaMemcpyKind kind) -{ - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - size_t size = count; - printf("GPGPU-Sim PTX: cudaMemcpyToArray\n"); - if( kind == cudaMemcpyHostToDevice ) - gpu->memcpy_to_gpu( (size_t)(dst->devPtr), src, size); - else if( kind == cudaMemcpyDeviceToHost ) - gpu->memcpy_from_gpu( dst->devPtr, (size_t)src, size); - else if( kind == cudaMemcpyDeviceToDevice ) - gpu->memcpy_gpu_to_gpu( (size_t)(dst->devPtr), (size_t)src, size); - else { - printf("GPGPU-Sim PTX: cudaMemcpyToArray - ERROR : unsupported cudaMemcpyKind\n"); - abort(); - } - dst->devPtr32 = (unsigned) (size_t)(dst->devPtr); - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpyFromArray(void *dst, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t count, enum cudaMemcpyKind kind) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpyArrayToArray(struct cudaArray *dst, size_t wOffsetDst, size_t hOffsetDst, const struct cudaArray *src, size_t wOffsetSrc, size_t hOffsetSrc, size_t count, enum cudaMemcpyKind kind __dv(cudaMemcpyDeviceToDevice)) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpy2D(void *dst, size_t dpitch, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind) -{ - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - size_t size = spitch*height; - gpgpusim_ptx_assert( (dpitch==spitch), "different src and dst pitch not supported yet" ); - if( kind == cudaMemcpyHostToDevice ) - gpu->memcpy_to_gpu( (size_t)dst, src, size ); - else if( kind == cudaMemcpyDeviceToHost ) - gpu->memcpy_from_gpu( dst, (size_t)src, size ); - else if( kind == cudaMemcpyDeviceToDevice ) - gpu->memcpy_gpu_to_gpu( (size_t)dst, (size_t)src, size); - else { - printf("GPGPU-Sim PTX: cudaMemcpy2D - ERROR : unsupported cudaMemcpyKind\n"); - abort(); - } - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpy2DToArray(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind) -{ - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - size_t size = spitch*height; - size_t channel_size = dst->desc.w+dst->desc.x+dst->desc.y+dst->desc.z; - gpgpusim_ptx_assert( ((channel_size%8) == 0), "none byte multiple destination channel size not supported (sz=%u)", channel_size ); - unsigned elem_size = channel_size/8; - gpgpusim_ptx_assert( (dst->dimensions==2), "copy to none 2D array not supported" ); - gpgpusim_ptx_assert( (wOffset==0), "non-zero wOffset not yet supported" ); - gpgpusim_ptx_assert( (hOffset==0), "non-zero hOffset not yet supported" ); - gpgpusim_ptx_assert( (dst->height == (int)height), "partial copy not supported" ); - gpgpusim_ptx_assert( (elem_size*dst->width == width), "partial copy not supported" ); - gpgpusim_ptx_assert( (spitch == width), "spitch != width not supported" ); - if( kind == cudaMemcpyHostToDevice ) - gpu->memcpy_to_gpu( (size_t)(dst->devPtr), src, size); - else if( kind == cudaMemcpyDeviceToHost ) - gpu->memcpy_from_gpu( dst->devPtr, (size_t)src, size); - else if( kind == cudaMemcpyDeviceToDevice ) - gpu->memcpy_gpu_to_gpu( (size_t)dst->devPtr, (size_t)src, size); - else { - printf("GPGPU-Sim PTX: cudaMemcpy2D - ERROR : unsupported cudaMemcpyKind\n"); - abort(); - } - dst->devPtr32 = (unsigned) (size_t)(dst->devPtr); - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpy2DFromArray(void *dst, size_t dpitch, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t width, size_t height, enum cudaMemcpyKind kind) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpy2DArrayToArray(struct cudaArray *dst, size_t wOffsetDst, size_t hOffsetDst, const struct cudaArray *src, size_t wOffsetSrc, size_t hOffsetSrc, size_t width, size_t height, enum cudaMemcpyKind kind __dv(cudaMemcpyDeviceToDevice)) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpyToSymbol(const char *symbol, const void *src, size_t count, size_t offset __dv(0), enum cudaMemcpyKind kind __dv(cudaMemcpyHostToDevice)) -{ - //CUctx_st *context = GPGPUSim_Context(); - assert(kind == cudaMemcpyHostToDevice); - printf("GPGPU-Sim PTX: cudaMemcpyToSymbol: symbol = %p\n", symbol); - //stream_operation( const char *symbol, const void *src, size_t count, size_t offset ) - g_stream_manager->push( stream_operation(src,symbol,count,offset,0) ); - //gpgpu_ptx_sim_memcpy_symbol(symbol,src,count,offset,1,context->get_device()->get_gpgpu()); - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpyFromSymbol(void *dst, const char *symbol, size_t count, size_t offset __dv(0), enum cudaMemcpyKind kind __dv(cudaMemcpyDeviceToHost)) -{ - //CUctx_st *context = GPGPUSim_Context(); - assert(kind == cudaMemcpyDeviceToHost); - printf("GPGPU-Sim PTX: cudaMemcpyFromSymbol: symbol = %p\n", symbol); - g_stream_manager->push( stream_operation(symbol,dst,count,offset,0) ); - //gpgpu_ptx_sim_memcpy_symbol(symbol,dst,count,offset,0,context->get_device()->get_gpgpu()); - return g_last_cudaError = cudaSuccess; -} - - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaMemcpyAsync(void *dst, const void *src, size_t count, enum cudaMemcpyKind kind, cudaStream_t stream) -{ - struct CUstream_st *s = (struct CUstream_st *)stream; - switch( kind ) { - case cudaMemcpyHostToDevice: g_stream_manager->push( stream_operation(src,(size_t)dst,count,s) ); break; - case cudaMemcpyDeviceToHost: g_stream_manager->push( stream_operation((size_t)src,dst,count,s) ); break; - case cudaMemcpyDeviceToDevice: g_stream_manager->push( stream_operation((size_t)src,(size_t)dst,count,s) ); break; - default: - abort(); - } - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpyToArrayAsync(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t count, enum cudaMemcpyKind kind, cudaStream_t stream) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpyFromArrayAsync(void *dst, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t count, enum cudaMemcpyKind kind, cudaStream_t stream) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpy2DAsync(void *dst, size_t dpitch, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind, cudaStream_t stream) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpy2DToArrayAsync(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind, cudaStream_t stream) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpy2DFromArrayAsync(void *dst, size_t dpitch, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t width, size_t height, enum cudaMemcpyKind kind, cudaStream_t stream) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaMemset(void *mem, int c, size_t count) -{ - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - gpu->gpu_memset((size_t)mem, c, count); - return g_last_cudaError = cudaSuccess; -} - -//memset operation is done but i think its not async? -__host__ cudaError_t CUDARTAPI cudaMemsetAsync(void *mem, int c, size_t count, cudaStream_t stream=0) -{ - printf("GPGPU-Sim PTX: WARNING: Asynchronous memset not supported (%s)\n", __my_func__); - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - gpu->gpu_memset((size_t)mem, c, count); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaMemset2D(void *mem, size_t pitch, int c, size_t width, size_t height) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaGetSymbolAddress(void **devPtr, const char *symbol) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaGetSymbolSize(size_t *size, const char *symbol) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ -__host__ cudaError_t CUDARTAPI cudaGetDeviceCount(int *count) -{ - _cuda_device_id *dev = GPGPUSim_Init(); - *count = dev->num_devices(); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaGetDeviceProperties(struct cudaDeviceProp *prop, int device) -{ - _cuda_device_id *dev = GPGPUSim_Init(); - if (device <= dev->num_devices() ) { - *prop= *dev->get_prop(); - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorInvalidDevice; - } -} - -#if (CUDART_VERSION > 5000) -__host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDeviceAttr attr, int device) -{ - const struct cudaDeviceProp *prop; - _cuda_device_id *dev = GPGPUSim_Init(); - if (device <= dev->num_devices() ) { - prop = dev->get_prop(); - switch (attr) { - case 5: - *value= prop->maxGridSize[0]; - break; - case 6: - *value= prop->maxGridSize[1]; - break; - case 7: - *value= prop->maxGridSize[2]; - break; - case 10: - *value= prop->warpSize; - break; - case 12: - *value= prop->regsPerBlock; - break; - case 14: - *value= prop->textureAlignment ; - break; - case 16: - *value= prop->multiProcessorCount ; - break; - case 39: - *value= dev->get_gpgpu()->threads_per_core(); - break; - case 75: - *value= 8 ; - break; - case 76: - *value= 3 ; - break; - case 78: - *value= 0 ; //TODO: as of now, we dont support stream priorities. - break; - default: - printf("ERROR: implement the attribute numbered %d \n",attr); - abort(); - } - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorInvalidDevice; - } -} -#endif - -__host__ cudaError_t CUDARTAPI cudaChooseDevice(int *device, const struct cudaDeviceProp *prop) -{ - _cuda_device_id *dev = GPGPUSim_Init(); - *device = dev->get_id(); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaSetDevice(int device) -{ - //set the active device to run cuda - if ( device <= GPGPUSim_Init()->num_devices() ) { - g_active_device = device; - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorInvalidDevice; - } -} - -__host__ cudaError_t CUDARTAPI cudaGetDevice(int *device) -{ - *device = g_active_device; - return g_last_cudaError = cudaSuccess; -} - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaBindTexture(size_t *offset, - const struct textureReference *texref, - const void *devPtr, - const struct cudaChannelFormatDesc *desc, - size_t size __dv(UINT_MAX)) -{ - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - printf("GPGPU-Sim PTX: in cudaBindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); - struct cudaArray *array; - array = (struct cudaArray*) malloc(sizeof(struct cudaArray)); - array->desc = *desc; - array->size = size; - array->width = size; - array->height = 1; - array->dimensions = 1; - array->devPtr = (void*)devPtr; - array->devPtr32 = (int)(long long)devPtr; - offset = 0; - printf("GPGPU-Sim PTX: size = %zu\n", size); - printf("GPGPU-Sim PTX: texref = %p, array = %p\n", texref, array); - printf("GPGPU-Sim PTX: devPtr32 = %x\n", array->devPtr32); - printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); - printf("GPGPU-Sim PTX: ChannelFormatDesc: x=%d, y=%d, z=%d, w=%d\n", desc->x, desc->y, desc->z, desc->w); - printf("GPGPU-Sim PTX: Texture Normalized? = %d\n", texref->normalized); - gpu->gpgpu_ptx_sim_bindTextureToArray(texref, array); - devPtr = (void*)(long long)array->devPtr32; - printf("GPGPU-Sim PTX: devPtr = %p\n", devPtr); - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureReference *texref, const struct cudaArray *array, const struct cudaChannelFormatDesc *desc) -{ - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - printf("GPGPU-Sim PTX: in cudaBindTextureToArray: %p %p\n", texref, array); - printf("GPGPU-Sim PTX: devPtr32 = %x\n", array->devPtr32); - printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); - printf("GPGPU-Sim PTX: Texture Normalized? = %d\n", texref->normalized); - gpu->gpgpu_ptx_sim_bindTextureToArray(texref, array); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) -{ - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaGetTextureAlignmentOffset(size_t *offset, const struct textureReference *texref) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - -__host__ cudaError_t CUDARTAPI cudaGetTextureReference(const struct textureReference **texref, const char *symbol) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - -__host__ cudaError_t CUDARTAPI cudaGetChannelDesc(struct cudaChannelFormatDesc *desc, const struct cudaArray *array) -{ - *desc = array->desc; - return g_last_cudaError = cudaSuccess; -} - - -__host__ struct cudaChannelFormatDesc CUDARTAPI cudaCreateChannelDesc(int x, int y, int z, int w, enum cudaChannelFormatKind f) -{ - struct cudaChannelFormatDesc dummy; - dummy.x = x; - dummy.y = y; - dummy.z = z; - dummy.w = w; - dummy.f = f; - return dummy; -} - -__host__ cudaError_t CUDARTAPI cudaGetLastError(void) -{ - return g_last_cudaError; -} - -__host__ const char* CUDARTAPI cudaGetErrorString(cudaError_t error) -{ - if( g_last_cudaError == cudaSuccess ) - return "no error"; - char buf[1024]; - snprintf(buf,1024,"<>", g_last_cudaError); - return strdup(buf); -} - -__host__ cudaError_t CUDARTAPI cudaConfigureCall(dim3 gridDim, dim3 blockDim, size_t sharedMem, cudaStream_t stream) -{ - struct CUstream_st *s = (struct CUstream_st *)stream; - g_cuda_launch_stack.push_back( kernel_config(gridDim,blockDim,sharedMem,s) ); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaSetupArgument(const void *arg, size_t size, size_t offset) -{ - gpgpusim_ptx_assert( !g_cuda_launch_stack.empty(), "empty launch stack" ); - kernel_config &config = g_cuda_launch_stack.back(); - config.set_arg(arg,size,offset); - - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaLaunch( const char *hostFun ) -{ - CUctx_st* context = GPGPUSim_Context(); - char *mode = getenv("PTX_SIM_MODE_FUNC"); - if( mode ) - sscanf(mode,"%u", &g_ptx_sim_mode); - gpgpusim_ptx_assert( !g_cuda_launch_stack.empty(), "empty launch stack" ); - kernel_config config = g_cuda_launch_stack.back(); - struct CUstream_st *stream = config.get_stream(); - printf("\nGPGPU-Sim PTX: cudaLaunch for 0x%p (mode=%s) on stream %u\n", hostFun, - g_ptx_sim_mode?"functional simulation":"performance simulation", stream?stream->get_uid():0 ); - kernel_info_t *grid = gpgpu_cuda_ptx_sim_init_grid(hostFun,config.get_args(),config.grid_dim(),config.block_dim(),context); - //do dynamic PDOM analysis for performance simulation scenario - std::string kname = grid->name(); - function_info *kernel_func_info = grid->entry(); - if (kernel_func_info->is_pdom_set()) { - printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", kname.c_str() ); - } else { - printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", kname.c_str() ); - kernel_func_info->do_pdom(); - kernel_func_info->set_pdom(); - } - dim3 gridDim = config.grid_dim(); - dim3 blockDim = config.block_dim(); - printf("GPGPU-Sim PTX: pushing kernel \'%s\' to stream %u, gridDim= (%u,%u,%u) blockDim = (%u,%u,%u) \n", - kname.c_str(), stream?stream->get_uid():0, gridDim.x,gridDim.y,gridDim.z,blockDim.x,blockDim.y,blockDim.z ); - stream_operation op(grid,g_ptx_sim_mode,stream); - g_stream_manager->push(op); - g_cuda_launch_stack.pop_back(); - return g_last_cudaError = cudaSuccess; -} - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaStreamCreate(cudaStream_t *stream) -{ - printf("GPGPU-Sim PTX: cudaStreamCreate\n"); -#if (CUDART_VERSION >= 3000) - *stream = new struct CUstream_st(); - g_stream_manager->add_stream(*stream); -#else - *stream = 0; - printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); -#endif - return g_last_cudaError = cudaSuccess; -} - -//TODO: introduce priorities -__host__ cudaError_t CUDARTAPI cudaStreamCreateWithPriority(cudaStream_t *stream, unsigned int flags, int priority) { - return cudaStreamCreate(stream); -} - -__host__ cudaError_t CUDARTAPI cudaDeviceGetStreamPriorityRange(int* leastPriority, int* greatestPriority) { - return cudaSuccess; -} - -__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *pStream, unsigned int flags) { - return cudaStreamCreate(pStream); -} - -__host__ cudaError_t CUDARTAPI cudaStreamDestroy(cudaStream_t stream) -{ -#if (CUDART_VERSION >= 3000) - g_stream_manager->destroy_stream(stream); -#endif - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaStreamSynchronize(cudaStream_t stream) -{ -#if (CUDART_VERSION >= 3000) - if( stream == NULL ) - synchronize(); - return g_last_cudaError = cudaSuccess; - stream->synchronize(); -#else - printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); -#endif - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) -{ -#if (CUDART_VERSION >= 3000) - if( stream == NULL ) - return g_last_cudaError = cudaErrorInvalidResourceHandle; - return g_last_cudaError = stream->empty()?cudaSuccess:cudaErrorNotReady; -#else - printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); - return g_last_cudaError = cudaSuccess; // it is always success because all cuda calls are synchronous -#endif -} - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaEventCreate(cudaEvent_t *event) -{ - CUevent_st *e = new CUevent_st(false); - g_timer_events[e->get_uid()] = e; -#if CUDART_VERSION >= 3000 - *event = e; -#else - *event = e->get_uid(); -#endif - return g_last_cudaError = cudaSuccess; -} - -CUevent_st *get_event(cudaEvent_t event) -{ - unsigned event_uid; -#if CUDART_VERSION >= 3000 - event_uid = event->get_uid(); -#else - event_uid = event; -#endif - event_tracker_t::iterator e = g_timer_events.find(event_uid); - if( e == g_timer_events.end() ) - return NULL; - return e->second; -} - -__host__ cudaError_t CUDARTAPI cudaEventRecord(cudaEvent_t event, cudaStream_t stream) -{ - CUevent_st *e = get_event(event); - if( !e ) return g_last_cudaError = cudaErrorUnknown; - struct CUstream_st *s = (struct CUstream_st *)stream; - stream_operation op(e,s); - g_stream_manager->push(op); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaEventQuery(cudaEvent_t event) -{ - CUevent_st *e = get_event(event); - if( e == NULL ) { - return g_last_cudaError = cudaErrorInvalidValue; - } else if( e->done() ) { - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorNotReady; - } -} - -__host__ cudaError_t CUDARTAPI cudaEventSynchronize(cudaEvent_t event) -{ - printf("GPGPU-Sim API: cudaEventSynchronize ** waiting for event\n"); - fflush(stdout); - CUevent_st *e = (CUevent_st*) event; - while( !e->done() ) - ; - printf("GPGPU-Sim API: cudaEventSynchronize ** event detected\n"); - fflush(stdout); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaEventDestroy(cudaEvent_t event) -{ - CUevent_st *e = get_event(event); - unsigned event_uid = e->get_uid(); - event_tracker_t::iterator pe = g_timer_events.find(event_uid); - if( pe == g_timer_events.end() ) - return g_last_cudaError = cudaErrorInvalidValue; - g_timer_events.erase(pe); - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaEventElapsedTime(float *ms, cudaEvent_t start, cudaEvent_t end) -{ - time_t elapsed_time; - CUevent_st *s = get_event(start); - CUevent_st *e = get_event(end); - if( s==NULL || e==NULL ) - return g_last_cudaError = cudaErrorUnknown; - elapsed_time = e->clock() - s->clock(); - *ms = 1000*elapsed_time; - return g_last_cudaError = cudaSuccess; -} - - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaThreadExit(void) -{ - exit_simulation(); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaThreadSynchronize(void) -{ - //Called on host side - synchronize(); - return g_last_cudaError = cudaSuccess; -}; - -int CUDARTAPI __cudaSynchronizeThreads(void**, void*) -{ - return cudaThreadExit(); -} - - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -#if (CUDART_VERSION >= 3010) - -typedef struct CUuuid_st { /**< CUDA definition of UUID */ - char bytes[16]; -} CUuuid; - -/** - * CUDA UUID types - */ -// typedef __device_builtin__ struct CUuuid_st cudaUUID_t; - -__host__ cudaError_t CUDARTAPI cudaGetExportTable(const void **ppExportTable, const cudaUUID_t *pExportTableId) -{ - printf("cudaGetExportTable: UUID = "); - for (int s = 0; s < 16; s++) { - printf("%#2x ", (unsigned char) (pExportTableId->bytes[s])); - } - printf("\n"); - return g_last_cudaError = cudaSuccess; -} - -#endif - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -//#include "../../cuobjdump_to_ptxplus/cuobjdump_parser.h" - -enum cuobjdumpSectionType { - PTXSECTION=0, - ELFSECTION -}; - - -class cuobjdumpSection { -public: - //Constructor - cuobjdumpSection() { - arch = 0; - identifier = ""; - } - virtual ~cuobjdumpSection() {} - unsigned getArch() {return arch;} - void setArch(unsigned a) {arch = a;} - std::string getIdentifier() {return identifier;} - void setIdentifier(std::string i) {identifier = i;} - virtual void print(){std::cout << "cuobjdump Section: unknown type" << std::endl;} -private: - unsigned arch; - std::string identifier; -}; - -class cuobjdumpELFSection : public cuobjdumpSection -{ -public: - cuobjdumpELFSection() {} - virtual ~cuobjdumpELFSection() { - elffilename = ""; - sassfilename = ""; - } - std::string getELFfilename() {return elffilename;} - void setELFfilename(std::string f) {elffilename = f;} - std::string getSASSfilename() {return sassfilename;} - void setSASSfilename(std::string f) {sassfilename = f;} - virtual void print() { - std::cout << "ELF Section:" << std::endl; - std::cout << "arch: sm_" << getArch() << std::endl; - std::cout << "identifier: " << getIdentifier() << std::endl; - std::cout << "elf filename: " << getELFfilename() << std::endl; - std::cout << "sass filename: " << getSASSfilename() << std::endl; - std::cout << std::endl; - } -private: - std::string elffilename; - std::string sassfilename; -}; - -class cuobjdumpPTXSection : public cuobjdumpSection -{ -public: - cuobjdumpPTXSection(){ - ptxfilename = ""; - } - std::string getPTXfilename() {return ptxfilename;} - void setPTXfilename(std::string f) {ptxfilename = f;} - virtual void print() { - std::cout << "PTX Section:" << std::endl; - std::cout << "arch: sm_" << getArch() << std::endl; - std::cout << "identifier: " << getIdentifier() << std::endl; - std::cout << "ptx filename: " << getPTXfilename() << std::endl; - std::cout << std::endl; - } -private: - std::string ptxfilename; -}; - -std::list cuobjdumpSectionList; -std::list libSectionList; - -// sectiontype: 0 for ptx, 1 for elf -void addCuobjdumpSection(int sectiontype){ - if (sectiontype) - cuobjdumpSectionList.push_front(new cuobjdumpELFSection()); - else - cuobjdumpSectionList.push_front(new cuobjdumpPTXSection()); - printf("## Adding new section %s\n", sectiontype?"ELF":"PTX"); -} - -void setCuobjdumparch(const char* arch){ - unsigned archnum; - sscanf(arch, "sm_%u", &archnum); - assert (archnum && "cannot have sm_0"); - printf("Adding arch: %s\n", arch); - cuobjdumpSectionList.front()->setArch(archnum); -} - -void setCuobjdumpidentifier(const char* identifier){ - printf("Adding identifier: %s\n", identifier); - cuobjdumpSectionList.front()->setIdentifier(identifier); -} - -void setCuobjdumpptxfilename(const char* filename){ - printf("Adding ptx filename: %s\n", filename); - cuobjdumpSection* x = cuobjdumpSectionList.front(); - if (dynamic_cast(x) == NULL){ - assert (0 && "You shouldn't be trying to add a ptxfilename to an elf section"); - } - (dynamic_cast(x))->setPTXfilename(filename); -} - -void setCuobjdumpelffilename(const char* filename){ - if (dynamic_cast(cuobjdumpSectionList.front()) == NULL){ - assert (0 && "You shouldn't be trying to add a elffilename to an ptx section"); - } - (dynamic_cast(cuobjdumpSectionList.front()))->setELFfilename(filename); -} - -void setCuobjdumpsassfilename(const char* filename){ - if (dynamic_cast(cuobjdumpSectionList.front()) == NULL){ - assert (0 && "You shouldn't be trying to add a sassfilename to an ptx section"); - } - (dynamic_cast(cuobjdumpSectionList.front()))->setSASSfilename(filename); -} -extern int cuobjdump_parse(); -extern FILE *cuobjdump_in; - -//! Return the executable file of the process containing the PTX/SASS code -//! -//! This Function returns the executable file ran by the process. This -//! executable is supposed to contain the PTX/SASS code. It provides workaround -//! for processes running on valgrind by dereferencing /proc//exe within the -//! GPGPU-Sim process before calling cuobjdump to extract PTX/SASS. This is -//! needed because valgrind uses x86 emulation to detect memory leak. Other -//! processes (e.g. cuobjdump) reading /proc//exe will see the emulator -//! executable instead of the application binary. -//! -std::string get_app_binary(){ - char self_exe_path[1025]; -#ifdef __APPLE__ - uint32_t size = sizeof(self_exe_path); - if( _NSGetExecutablePath(self_exe_path,&size) != 0 ) { - printf("GPGPU-Sim ** ERROR: _NSGetExecutablePath input buffer too small\n"); - exit(1); - } -#else - std::stringstream exec_link; - exec_link << "/proc/self/exe"; - - ssize_t path_length = readlink(exec_link.str().c_str(), self_exe_path, 1024); - assert(path_length != -1); - self_exe_path[path_length] = '\0'; -#endif - - printf("self exe links to: %s\n", self_exe_path); - return self_exe_path; -} - -//above func gives abs path whereas this give just the name of application. -char* get_app_binary_name(std::string abs_path){ - char *self_exe_path; -#ifdef __APPLE__ - //TODO: get apple device and check the result. - printf("WARNING: not tested for Apple-mac devices \n"); - abort(); -#else - char* buf = strdup(abs_path.c_str()); - char *token = strtok(buf, "/"); - while(token !=NULL){ - self_exe_path = token; - token = strtok(NULL,"/"); - } -#endif - self_exe_path = strtok(self_exe_path, "."); - printf("self exe links to: %s\n", self_exe_path); - return self_exe_path; -} - -//! Call cuobjdump to extract everything (-elf -sass -ptx) -/*! - * This Function extract the whole PTX (for all the files) using cuobjdump - * to _cuobjdump_complete_output_XXXXXX then runs a parser to chop it up with each binary in - * its own file - * It is also responsible for extracting the libraries linked to the binary if the option is - * enabled - * */ -void extract_code_using_cuobjdump(){ - CUctx_st *context = GPGPUSim_Context(); - unsigned forced_max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); - - //prevent the dumping by cuobjdump everytime we execute the code! - const char *override_cuobjdump = getenv("CUOBJDUMP_SIM_FILE"); - char command[1000], ptx_file[1000]; - std::string app_binary = get_app_binary(); - //Running cuobjdump using dynamic link to current process - snprintf(command,1000,"md5sum %s ", app_binary.c_str()); - printf("Running md5sum using \"%s\"\n", command); - system(command); - // Running cuobjdump using dynamic link to current process - // Needs the option '-all' to extract PTX from CDP-enabled binary - extern bool g_cdp_enabled; - - //dump ptx for all individial ptx files into sepearte files which is later used by ptxas. - int result=0; -#if (CUDART_VERSION >= 6000) - char fname2[1024]; - snprintf(fname2,1024,"_cuobjdump_list_ptx_XXXXXX"); - int fd2=mkstemp(fname2); - close(fd2); - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -lptx -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname2); - result = system(command); - if( result != 0 ) { - printf("WARNING: Failed to execute cuobjdump to get list of ptx files \n"); - exit(0); - } else { - /* - as we got list of ptx files, we need to extract one by one into seperate files so that ptxas can understand it. - In this way, the duplicate definitions in a single embedded file can be prevented. - No of lines in the file is equal to no of ptx fileis available. - */ - FILE *fp = fopen(fname2,"r"); - if (fp==NULL) { - printf("WARNING: cuobjdump file error! Could not open file %s \n", fname2); - exit(0); - } else { - for (char c = getc(fp); c != EOF; c = getc(fp)) - if (c == '\n') - no_of_ptx = no_of_ptx + 1; - fclose(fp); - } - if(no_of_ptx==0){ - printf("WARNING: Number of ptx in the executable file are 0. One of the reasons might be\n"); - printf("\t1. CDP is enabled\n"); - printf("\t2. cuobjdump -lptx doesnt recognize sm_%u\n",forced_max_capability); - printf("\t3. the application was not compiled iwth nvcc flag sm_%u\n",forced_max_capability); - } - } - if(!g_cdp_enabled) { - //based on the list above, dump ptx files individually. Format of dumped ptx file is prog_name.unique_no.sm_<>.ptx - for (int index=1; index<= no_of_ptx; index++){ - snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", get_app_binary_name(app_binary), index, forced_max_capability); - printf("Extracting specific PTX file named %s \n",ptx_file); - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -arch=sm_%u -xptx %s %s", forced_max_capability, ptx_file, app_binary.c_str()); - if (system(command)!=0) { - printf("ERROR: command: %s failed \n",command); - exit(0); - } - } - } -#endif - //TODO: redundant to dump twice. how can it be prevented? - //dump only for specific arch - char fname[1024]; - if ((override_cuobjdump == NULL) || (strlen(override_cuobjdump)==0)) { - snprintf(fname,1024,"_cuobjdump_complete_output_XXXXXX"); - int fd=mkstemp(fname); - close(fd); - if(!g_cdp_enabled) - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass %s > %s", app_binary.c_str(), fname); - else - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); - bool parse_output = true; - result = system(command); - if(result) { - if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support() && (result == 65280)) { - // Some CUDA application may exclusively use kernels provided by CUDA - // libraries (e.g. CUBLAS). Skipping cuobjdump extraction from the - // executable for this case. - // 65280 is the return code from cuobjdump denoting the specific error (tested on CUDA 4.0/4.1/4.2) - printf("WARNING: Failed to execute: %s\n", command); - printf(" Executable binary does not contain any GPU kernel.\n"); - parse_output = false; - } else { - printf("ERROR: Failed to execute: %s\n", command); - exit(1); - } - } - - if (parse_output) { - printf("Parsing file %s\n", fname); - cuobjdump_in = fopen(fname, "r"); - - cuobjdump_parse(); - fclose(cuobjdump_in); - printf("Done parsing!!!\n"); - } else { - printf("Parsing skipped for %s\n", fname); - } - - if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ - //Experimental library support - //Currently only for cufft - - std::stringstream cmd; - cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; - int result = system(cmd.str().c_str()); - if(result){ - std::cout << "Failed to execute: " << cmd.str() << std::endl; - exit(1); - } - std::ifstream libsf; - libsf.open("_tempfile_.txt"); - if(!libsf.is_open()) { - std::cout << "Failed to open: _tempfile_.txt" << std::endl; - exit(1); - } - - //Save the original section list - std::list tmpsl = cuobjdumpSectionList; - cuobjdumpSectionList.clear(); - - std::string line; - std::getline(libsf, line); - std::cout << "DOING: " << line << std::endl; - int cnt=1; - while(libsf.good()){ - std::stringstream libcodfn; - libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; - cmd.str(""); //resetting - cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; - cmd << line; - cmd << " > "; - cmd << libcodfn.str(); - std::cout << "Running cuobjdump on " << line << std::endl; - std::cout << "Using command: " << cmd.str() << std::endl; - result = system(cmd.str().c_str()); - if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} - std::cout << "Done" << std::endl; - - std::cout << "Trying to parse " << libcodfn.str() << std::endl; - cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); - cuobjdump_parse(); - fclose(cuobjdump_in); - std::getline(libsf, line); - } - libSectionList = cuobjdumpSectionList; - - //Restore the original section list - cuobjdumpSectionList = tmpsl; - } - } else { - printf("GPGPU-Sim PTX: overriding cuobjdump with '%s' (CUOBJDUMP_SIM_FILE is set)\n", override_cuobjdump); - snprintf(fname,1024, "%s",override_cuobjdump); - } -} - -//! Read file into char* -//TODO: convert this to C++ streams, will be way cleaner -char* readfile (const std::string filename){ - assert (filename != ""); - FILE* fp = fopen(filename.c_str(),"r"); - if (!fp) { - std::cout << "ERROR: Could not open file %s for reading\n" << filename << std::endl; - assert (0); - } - // finding size of the file - int filesize= 0; - fseek (fp , 0 , SEEK_END); - - filesize = ftell (fp); - fseek (fp, 0, SEEK_SET); - // allocate and copy the entire ptx - char* ret = (char*)malloc((filesize +1)* sizeof(char)); - fread(ret,1,filesize,fp); - ret[filesize]='\0'; - fclose(fp); - return ret; -} - -//! Function that helps debugging -void printSectionList(std::list sl) { - std::list::iterator iter; - for ( iter = sl.begin(); - iter != sl.end(); - iter++ - ){ - (*iter)->print(); - } -} - -//! Remove unecessary sm versions from the section list -std::list pruneSectionList(std::list cuobjdumpSectionList, CUctx_st *context) { - unsigned forced_max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); - - //For ptxplus, force the max capability to 19 if it's higher or unspecified(0) - if (context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus()){ - if ( (forced_max_capability == 0) || - (forced_max_capability >= 20)){ - printf("GPGPU-Sim: WARNING: Capability >= 20 are not supported in PTXPlus\n\tSetting forced_max_capability to 19\n"); - forced_max_capability = 19; - } - } - - std::list prunedList; - - //Find the highest capability (that is lower than the forced maximum) for each cubin file - //and set it in cuobjdumpSectionMap. Do this only for ptx sections - std::map cuobjdumpSectionMap; - int min_ptx_capability_found=0; - for ( std::list::iterator iter = cuobjdumpSectionList.begin(); - iter != cuobjdumpSectionList.end(); - iter++){ - unsigned capability = (*iter)->getArch(); - if(dynamic_cast(*iter) != NULL){ - if(capabilitygetIdentifier())==cuobjdumpSectionMap.end()) - || (cuobjdumpSectionMap[(*iter)->getIdentifier()] < capability)) - cuobjdumpSectionMap[(*iter)->getIdentifier()] = capability; - } - } - } - - //Throw away the sections with the lower capabilites and push those with the highest in - //the pruned list - for ( std::list::iterator iter = cuobjdumpSectionList.begin(); - iter != cuobjdumpSectionList.end(); - iter++){ - unsigned capability = (*iter)->getArch(); - if(capability == cuobjdumpSectionMap[(*iter)->getIdentifier()]){ - prunedList.push_back(*iter); - } else { - delete *iter; - } - } - if(prunedList.empty()){ - printf("Error: No PTX sections found with sm capability that is lower than current forced maximum capability \n minimum ptx capability found = %u, maximum forced ptx capability = %u \n User might want to change either the forced maximum capability from gpgpusim configuration or update the compilation to generate the required PTX version\n",min_ptx_capability_found,forced_max_capability); - abort(); - } - return prunedList; -} - -//! Merge all PTX sections that have a specific identifier into one file -std::list mergeMatchingSections(std::list cuobjdumpSectionList, std::string identifier){ - const char *ptxcode = ""; - std::list::iterator old_iter; - cuobjdumpPTXSection* old_ptxsection = NULL; - cuobjdumpPTXSection* ptxsection; - std::list mergedList; - - for ( std::list::iterator iter = cuobjdumpSectionList.begin(); - iter != cuobjdumpSectionList.end(); - iter++){ - if((ptxsection=dynamic_cast(*iter)) != NULL && - strcmp(ptxsection->getIdentifier().c_str(), identifier.c_str()) == 0){ - // Read and remove the last PTX section - if (old_ptxsection != NULL) { - ptxcode = readfile(old_ptxsection->getPTXfilename()); - // remove ptx file? - delete *old_iter; - } - - // Append all the PTX from the last PTX section into the current PTX section - // Add 50 to ptxcode to ignore the information regarding version/target/address_size - if (strlen(ptxcode) >= 50) { - FILE *ptxfile = fopen((ptxsection->getPTXfilename()).c_str(), "a"); - fprintf(ptxfile, "%s", ptxcode + 50); - fclose(ptxfile); - } - - old_iter = iter; - old_ptxsection = ptxsection; - } - // Store all non-PTX sections and PTX sections with non-matching identifiers - else { - mergedList.push_back(*iter); - } - } - - // Store the final PTX section - mergedList.push_back(*old_iter); - - return mergedList; -} - -//! Merge any PTX sections with matching identifiers -std::list mergeSections(std::list cuobjdumpSectionList){ - std::vector identifier; - cuobjdumpPTXSection* ptxsection; - - // Add all identifiers present in PTX sections to a vector - for ( std::list::iterator iter = cuobjdumpSectionList.begin(); - iter != cuobjdumpSectionList.end(); - iter++){ - if((ptxsection=dynamic_cast(*iter)) != NULL){ - std::string current_id = ptxsection->getIdentifier(); - - // If we haven't yet seen a given identifier, add it to the vector - if (std::find(identifier.begin(), identifier.end(), current_id) == identifier.end()) { - identifier.push_back(current_id); - } - } - } - - // Call mergeMatchingSections on all identifiers in the vector - for ( std::vector::iterator iter = identifier.begin(); - iter != identifier.end(); - iter++) { - cuobjdumpSectionList = mergeMatchingSections(cuobjdumpSectionList, *iter); - } - - return cuobjdumpSectionList; -} - - -//! Within the section list, find the ELF section corresponding to a given identifier -cuobjdumpELFSection* findELFSectionInList(std::list sectionlist, const std::string identifier){ - - std::list::iterator iter; - for ( iter = sectionlist.begin(); - iter != sectionlist.end(); - iter++ - ){ - cuobjdumpELFSection* elfsection; - if((elfsection=dynamic_cast(*iter)) != NULL){ - if(elfsection->getIdentifier() == identifier) - return elfsection; - } - } - return NULL; -} - -//! Find an ELF section in all the known lists -cuobjdumpELFSection* findELFSection(const std::string identifier){ - cuobjdumpELFSection* sec = findELFSectionInList(cuobjdumpSectionList, identifier); - if (sec!=NULL)return sec; - sec = findELFSectionInList(libSectionList, identifier); - if (sec!=NULL)return sec; - std::cout << "Could not find " << identifier << std::endl; - assert(0 && "Could not find the required ELF section"); - return NULL; -} - -//! Within the section list, find the PTX section corresponding to a given identifier -cuobjdumpPTXSection* findPTXSectionInList(std::list sectionlist, const std::string identifier){ - std::list::iterator iter; - for ( iter = sectionlist.begin(); - iter != sectionlist.end(); - iter++ - ){ - cuobjdumpPTXSection* ptxsection; - if((ptxsection=dynamic_cast(*iter)) != NULL){ - if(ptxsection->getIdentifier() == identifier) - return ptxsection; - else { - extern bool g_cdp_enabled; - if(g_cdp_enabled) { - printf("Warning: __cudaRegisterFatBinary needs %s, but find PTX section with %s\n", - identifier.c_str(), ptxsection->getIdentifier().c_str()); - return ptxsection; - } - } - } - } - return NULL; -} - -//! Find an PTX section in all the known lists -cuobjdumpPTXSection* findPTXSection(const std::string identifier){ - cuobjdumpPTXSection* sec = findPTXSectionInList(cuobjdumpSectionList, identifier); - if (sec!=NULL)return sec; - sec = findPTXSectionInList(libSectionList, identifier); - if (sec!=NULL)return sec; - std::cout << "Could not find " << identifier << std::endl; - assert(0 && "Could not find the required PTX section"); - return NULL; -} - - - -//! Extract the code using cuobjdump and remove unnecessary sections -void cuobjdumpInit(){ - CUctx_st *context = GPGPUSim_Context(); - extract_code_using_cuobjdump(); //extract all the output of cuobjdump to _cuobjdump_*.* - const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); - if (pre_load ==NULL || strlen(pre_load)==0){ - cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); - cuobjdumpSectionList = mergeSections(cuobjdumpSectionList); - } -} - -std::map fatbinmap; -std::mapfatbin_registered; -std::map name_symtab; - -//! Keep track of the association between filename and cubin handle -void cuobjdumpRegisterFatBinary(unsigned int handle, const char* filename){ - fatbinmap[handle] = filename; -} - -//! Either submit PTX for simulation or convert SASS to PTXPlus and submit it -void cuobjdumpParseBinary(unsigned int handle){ - - if(fatbin_registered[handle]) return; - fatbin_registered[handle] = true; - CUctx_st *context = GPGPUSim_Context(); - std::string fname = fatbinmap[handle]; - - if (name_symtab.find(fname) != name_symtab.end()) { - symbol_table *symtab = name_symtab[fname]; - context->add_binary(symtab, handle); - return; - } - - unsigned max_capability = 0; - for ( std::list::iterator iter = cuobjdumpSectionList.begin(); - iter != cuobjdumpSectionList.end(); - iter++){ - unsigned capability = (*iter)->getArch(); - if (capability > max_capability) max_capability = capability; - } - if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); - - cuobjdumpPTXSection* ptx = NULL; - const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); - if(pre_load==NULL || strlen(pre_load)==0) - ptx = findPTXSection(fname); - symbol_table *symtab; - char *ptxcode; - const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); - if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL or strlen(getenv("PTX_SIM_USE_PTX_FILE"))==0) { - ptxcode = readfile(ptx->getPTXfilename()); - } else { - printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); - ptxcode = readfile(override_ptx_name); - } - if(context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() ) { - cuobjdumpELFSection* elfsection = findELFSection(ptx->getIdentifier()); - assert (elfsection!= NULL); - char *ptxplus_str = gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus( - ptx->getPTXfilename(), - elfsection->getELFfilename(), - elfsection->getSASSfilename()); - symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxplus_str, handle); - printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); - context->add_binary(symtab, handle); - gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability ); - delete[] ptxplus_str; - } else { - symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxcode, handle); - //if CUOBJDUMP_SIM_FILE is not set, ptx is NULL. So comment below. - //printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); - context->add_binary(symtab, handle); - gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability ); - } - load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu()); - load_constants(symtab,STATIC_ALLOC_LIMIT,context->get_device()->get_gpgpu()); - name_symtab[fname] = symtab; - - //TODO: Remove temporarily files as per configurations -} - -void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) -{ -#if (CUDART_VERSION < 2010) - printf("GPGPU-Sim PTX: ERROR ** this version of GPGPU-Sim requires CUDA 2.1 or higher\n"); - exit(1); -#endif - CUctx_st *context = GPGPUSim_Context(); - static unsigned next_fat_bin_handle = 1; - if(context->get_device()->get_gpgpu()->get_config().use_cuobjdump()) { - // The following workaround has only been verified on 64-bit systems. - if (sizeof(void*) == 4) - printf("GPGPU-Sim PTX: FatBin file name extraction has not been tested on 32-bit system.\n"); - - #if (CUDART_VERSION <= 6000) - // FatBin handle from the .fatbin.c file (one of the intermediate files generated by NVCC) - typedef struct {int m; int v; const unsigned long long* d; char* f;} __fatDeviceText __attribute__ ((aligned (8))); - __fatDeviceText * fatDeviceText = (__fatDeviceText *) fatCubin; - - // Extract the source code file name that generate the given FatBin. - // - Obtains the pointer to the actual fatbin structure from the FatBin handle (fatCubin). - // - An integer inside the fatbin structure contains the relative offset to the source code file name. - // - This offset differs among different CUDA and GCC versions. - char * pfatbin = (char*) fatDeviceText->d; - int offset = *((int*)(pfatbin+48)); - char * filename = (pfatbin+16+offset); - #else - const char * filename = "default"; - #endif - // The extracted file name is associated with a fat_cubin_handle passed - // into cudaLaunch(). Inside cudaLaunch(), the associated file name is - // used to find the PTX/SASS section from cuobjdump, which contains the - // PTX/SASS code for the launched kernel function. - // This allows us to work around the fact that cuobjdump only outputs the - // file name associated with each section. - unsigned long long fat_cubin_handle = next_fat_bin_handle; - next_fat_bin_handle++; - printf("GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = %llu, filename=%s\n", fat_cubin_handle, filename); - /*! - * This function extracts all data from all files in first call - * then for next calls, only returns the appropriate number - */ - assert(fat_cubin_handle >= 1); - if (fat_cubin_handle==1) cuobjdumpInit(); - cuobjdumpRegisterFatBinary(fat_cubin_handle, filename); - - return (void**)fat_cubin_handle; - } -#if (CUDART_VERSION < 8000) - else { - static unsigned source_num=1; - unsigned long long fat_cubin_handle = next_fat_bin_handle++; - __cudaFatCudaBinary *info = (__cudaFatCudaBinary *)fatCubin; - assert( info->version >= 3 ); - unsigned num_ptx_versions=0; - unsigned max_capability=0; - unsigned selected_capability=0; - bool found=false; - unsigned forced_max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); - if (!info->ptx){ - printf("ERROR: Cannot find ptx code in cubin file\n" - "\tIf you are using CUDA 4.0 or higher, please enable -gpgpu_ptx_use_cuobjdump or downgrade to CUDA 3.1\n"); - exit(1); - } - while( info->ptx[num_ptx_versions].gpuProfileName != NULL ) { - unsigned capability=0; - sscanf(info->ptx[num_ptx_versions].gpuProfileName,"compute_%u",&capability); - printf("GPGPU-Sim PTX: __cudaRegisterFatBinary found PTX versions for '%s', ", info->ident); - printf("capability = %s\n", info->ptx[num_ptx_versions].gpuProfileName ); - if( forced_max_capability ) { - if( capability > max_capability && capability <= forced_max_capability ) { - found = true; - max_capability=capability; - selected_capability = num_ptx_versions; - } - } else { - if( capability > max_capability ) { - found = true; - max_capability=capability; - selected_capability = num_ptx_versions; - } - } - num_ptx_versions++; - } - if( found ) { - printf("GPGPU-Sim PTX: Loading PTX for %s, capability = %s\n", - info->ident, info->ptx[selected_capability].gpuProfileName ); - symbol_table *symtab; - const char *ptx = info->ptx[selected_capability].ptx; - if(context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() ) { - printf("GPGPU-Sim PTX: ERROR ** PTXPlus is only supported through cuobjdump\n" - "\tEither enable cuobjdump or disable PTXPlus in your configuration file\n"); - exit(1); - } else { - symtab=gpgpu_ptx_sim_load_ptx_from_string(ptx,source_num); - context->add_binary(symtab,fat_cubin_handle); - gpgpu_ptxinfo_load_from_string( ptx, source_num, max_capability ); - } - source_num++; - load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu()); - load_constants(symtab,STATIC_ALLOC_LIMIT,context->get_device()->get_gpgpu()); - } else { - printf("GPGPU-Sim PTX: warning -- did not find an appropriate PTX in cubin\n"); - } - return (void**)fat_cubin_handle; - } -#else - else { - printf("ERROR ** __cudaRegisterFatBinary() needs to be updated\n"); - abort(); - } -#endif -} - -void __cudaUnregisterFatBinary(void **fatCubinHandle) -{ - ; -} - -cudaError_t cudaDeviceReset ( void ) { - // Should reset the simulated GPU - return g_last_cudaError = cudaSuccess; -} -cudaError_t CUDARTAPI cudaDeviceSynchronize(void){ - // I don't know what this should do - return g_last_cudaError = cudaSuccess; -} - - -void CUDARTAPI __cudaRegisterFunction( - void **fatCubinHandle, - const char *hostFun, - char *deviceFun, - const char *deviceName, - int thread_limit, - uint3 *tid, - uint3 *bid, - dim3 *bDim, - dim3 *gDim -) -{ - CUctx_st *context = GPGPUSim_Context(); - unsigned fat_cubin_handle = (unsigned)(unsigned long long)fatCubinHandle; - printf("GPGPU-Sim PTX: __cudaRegisterFunction %s : hostFun 0x%p, fat_cubin_handle = %u\n", - deviceFun, hostFun, fat_cubin_handle); - if(context->get_device()->get_gpgpu()->get_config().use_cuobjdump()) - cuobjdumpParseBinary(fat_cubin_handle); - context->register_function( fat_cubin_handle, hostFun, deviceFun ); -} - -extern void __cudaRegisterVar( - void **fatCubinHandle, - char *hostVar, //pointer to...something - char *deviceAddress, //name of variable - const char *deviceName, //name of variable (same as above) - int ext, - int size, - int constant, - int global ) -{ - printf("GPGPU-Sim PTX: __cudaRegisterVar: hostVar = %p; deviceAddress = %s; deviceName = %s\n", hostVar, deviceAddress, deviceName); - printf("GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of %d bytes\n", size); - if(GPGPUSim_Context()->get_device()->get_gpgpu()->get_config().use_cuobjdump()) - cuobjdumpParseBinary((unsigned)(unsigned long long)fatCubinHandle); - fflush(stdout); - if ( constant && !global && !ext ) { - gpgpu_ptx_sim_register_const_variable(hostVar,deviceName,size); - } else if ( !constant && !global && !ext ) { - gpgpu_ptx_sim_register_global_variable(hostVar,deviceName,size); - } else cuda_not_implemented(__my_func__,__LINE__); -} - - -void __cudaRegisterShared( - void **fatCubinHandle, - void **devicePtr -) -{ - // we don't do anything here - printf("GPGPU-Sim PTX: __cudaRegisterShared\n" ); -} - -void CUDARTAPI __cudaRegisterSharedVar( - void **fatCubinHandle, - void **devicePtr, - size_t size, - size_t alignment, - int storage -) -{ - // we don't do anything here - printf("GPGPU-Sim PTX: __cudaRegisterSharedVar\n" ); -} - -void __cudaRegisterTexture( - void **fatCubinHandle, - const struct textureReference *hostVar, - const void **deviceAddress, - const char *deviceName, - int dim, - int norm, - int ext -) //passes in a newly created textureReference -{ - std::string devStr (deviceName); - #if (CUDART_VERSION > 4020) - if (devStr.size() > 2 && devStr.data()[0] == ':' && devStr.data()[1] == ':') - devStr = devStr.replace(0, 2, ""); - #endif - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - printf("GPGPU-Sim PTX: in __cudaRegisterTexture:\n"); - gpu->gpgpu_ptx_sim_bindNameToTexture(devStr.data(), hostVar, dim, norm, ext); - printf("GPGPU-Sim PTX: int dim = %d\n", dim); - printf("GPGPU-Sim PTX: int norm = %d\n", norm); - printf("GPGPU-Sim PTX: int ext = %d\n", ext); - printf("GPGPU-Sim PTX: Execution warning: Not finished implementing \"%s\"\n", __my_func__ ); -} - -#ifndef OPENGL_SUPPORT -typedef unsigned long GLuint; -#endif - -cudaError_t cudaGLRegisterBufferObject(GLuint bufferObj) -{ - printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); - return g_last_cudaError = cudaSuccess; -} - -struct glbmap_entry { - GLuint m_bufferObj; - void *m_devPtr; - size_t m_size; - struct glbmap_entry *m_next; -}; -typedef struct glbmap_entry glbmap_entry_t; - -glbmap_entry_t* g_glbmap = NULL; - -cudaError_t cudaGLMapBufferObject(void** devPtr, GLuint bufferObj) -{ -#ifdef OPENGL_SUPPORT - GLint buffer_size=0; - CUctx_st* ctx = GPGPUSim_Context(); - - glbmap_entry_t *p = g_glbmap; - while ( p && p->m_bufferObj != bufferObj ) - p = p->m_next; - if ( p == NULL ) { - glBindBuffer(GL_ARRAY_BUFFER,bufferObj); - glGetBufferParameteriv(GL_ARRAY_BUFFER,GL_BUFFER_SIZE,&buffer_size); - assert( buffer_size != 0 ); - *devPtr = ctx->get_device()->get_gpgpu()->gpu_malloc(buffer_size); - - // create entry and insert to front of list - glbmap_entry_t *n = (glbmap_entry_t *) calloc(1,sizeof(glbmap_entry_t)); - n->m_next = g_glbmap; - g_glbmap = n; - - // initialize entry - n->m_bufferObj = bufferObj; - n->m_devPtr = *devPtr; - n->m_size = buffer_size; - - p = n; - } else { - buffer_size = p->m_size; - *devPtr = p->m_devPtr; - } - - if ( *devPtr ) { - char *data = (char *) calloc(p->m_size,1); - glGetBufferSubData(GL_ARRAY_BUFFER,0,buffer_size,data); - memcpy_to_gpu( (size_t) *devPtr, data, buffer_size ); - free(data); - printf("GPGPU-Sim PTX: cudaGLMapBufferObject %zu bytes starting at 0x%llx..\n", (size_t)buffer_size, - (unsigned long long) *devPtr); - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorMemoryAllocation; - } - - return g_last_cudaError = cudaSuccess; -#else - fflush(stdout); - fflush(stderr); - printf("GPGPU-Sim PTX: GPGPU-Sim support for OpenGL integration disabled -- exiting\n"); - fflush(stdout); - exit(50); -#endif -} - -cudaError_t cudaGLUnmapBufferObject(GLuint bufferObj) -{ -#ifdef OPENGL_SUPPORT - glbmap_entry_t *p = g_glbmap; - while ( p && p->m_bufferObj != bufferObj ) - p = p->m_next; - if ( p == NULL ) - return g_last_cudaError = cudaErrorUnknown; - - char *data = (char *) calloc(p->m_size,1); - memcpy_from_gpu( data,(size_t)p->m_devPtr,p->m_size ); - glBufferSubData(GL_ARRAY_BUFFER,0,p->m_size,data); - free(data); - - return g_last_cudaError = cudaSuccess; -#else - fflush(stdout); - fflush(stderr); - printf("GPGPU-Sim PTX: support for OpenGL integration disabled -- exiting\n"); - fflush(stdout); - exit(50); -#endif -} - -cudaError_t cudaGLUnregisterBufferObject(GLuint bufferObj) -{ - printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); - return g_last_cudaError = cudaSuccess; -} - -#if (CUDART_VERSION >= 2010) - -cudaError_t CUDARTAPI cudaHostAlloc(void **pHost, size_t bytes, unsigned int flags) -{ - *pHost = malloc(bytes); - //need to track the size allocated so that cudaHostGetDevicePointer() can function properly. - //TODO: vary this function behavior based on flags value (following nvidia documentation) - pinned_memory_size[*pHost]=bytes; - if( *pHost ) - return g_last_cudaError = cudaSuccess; - else - return g_last_cudaError = cudaErrorMemoryAllocation; -} - -cudaError_t CUDARTAPI cudaHostGetDevicePointer(void **pDevice, void *pHost, unsigned int flags) -{ - //only cpu memory allocation happens in cudaHostAlloc. Linking with device pointer to pinned memory happens here. - //TODO: once kernel is executed, the contents in global pointer of GPU must be copied back to CPU host pointer! - flags=0; - CUctx_st* context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - std::map::const_iterator i = pinned_memory_size.find(pHost); - assert(i != pinned_memory_size.end()); - size_t size = i->second; - *pDevice = gpu->gpu_malloc(size); - if(g_debug_execution >= 3) - printf("GPGPU-Sim PTX: cudaMallocing %zu bytes starting at 0x%llx..\n",size, (unsigned long long) *pDevice); - if ( *pDevice ) { - pinned_memory[pHost]=pDevice; - //Copy contents in cpu to gpu - gpu->memcpy_to_gpu((size_t)*pDevice,pHost,size); - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorMemoryAllocation; - } -} - -cudaError_t CUDARTAPI cudaSetValidDevices(int *device_arr, int len) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - -cudaError_t CUDARTAPI cudaSetDeviceFlags( int flags ) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - -cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, const char *hostFun ) -{ - CUctx_st *context = GPGPUSim_Context(); - function_info *entry = context->get_kernel(hostFun); - if( entry ) { - const struct gpgpu_ptx_sim_info *kinfo = entry->get_kernel_info(); - attr->sharedSizeBytes = kinfo->smem; - attr->constSizeBytes = kinfo->cmem; - attr->localSizeBytes = kinfo->lmem; - attr->numRegs = kinfo->regs; - attr->maxThreadsPerBlock = 0; // from pragmas? -#if CUDART_VERSION >= 3000 - attr->ptxVersion = kinfo->ptx_version; - attr->binaryVersion = kinfo->sm_target; -#endif - } - return g_last_cudaError = cudaSuccess; -} - -cudaError_t CUDARTAPI cudaEventCreateWithFlags(cudaEvent_t *event, int flags) -{ - CUevent_st *e = new CUevent_st(flags==cudaEventBlockingSync); - g_timer_events[e->get_uid()] = e; -#if CUDART_VERSION >= 3000 - *event = e; -#else - *event = e->get_uid(); -#endif - return g_last_cudaError = cudaSuccess; -} - -cudaError_t CUDARTAPI cudaDriverGetVersion(int *driverVersion) -{ - *driverVersion = CUDART_VERSION; - return g_last_cudaError = cudaErrorUnknown; -} - -cudaError_t CUDARTAPI cudaRuntimeGetVersion(int *runtimeVersion) -{ - *runtimeVersion = CUDART_VERSION; - return g_last_cudaError = cudaErrorUnknown; -} - -#if CUDART_VERSION >= 3000 -__host__ cudaError_t CUDARTAPI cudaFuncSetCacheConfig(const char *func, enum cudaFuncCache cacheConfig ) -{ - CUctx_st *context = GPGPUSim_Context(); - context->get_device()->get_gpgpu()->set_cache_config(context->get_kernel(func)->get_name(), (FuncCache)cacheConfig); - return g_last_cudaError = cudaSuccess; -} - -//Jin: hack for cdp -__host__ cudaError_t CUDARTAPI cudaDeviceSetLimit(enum cudaLimit limit, size_t value) { - return g_last_cudaError = cudaSuccess; -} -#endif - -#endif - -cudaError_t CUDARTAPI cudaGLSetGLDevice(int device) -{ - printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); - return g_last_cudaError = cudaErrorUnknown; -} - -typedef void* HGPUNV; - -cudaError_t CUDARTAPI cudaWGLGetDevice(int *device, HGPUNV hGpu) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - -void CUDARTAPI __cudaMutexOperation(int lock) -{ - cuda_not_implemented(__my_func__,__LINE__); -} - -void CUDARTAPI __cudaTextureFetch(const void *tex, void *index, int integer, void *val) -{ - cuda_not_implemented(__my_func__,__LINE__); -} - -} - -namespace cuda_math { - -void CUDARTAPI __cudaMutexOperation(int lock) -{ - cuda_not_implemented(__my_func__,__LINE__); -} - -void CUDARTAPI __cudaTextureFetch(const void *tex, void *index, int integer, void *val) -{ - cuda_not_implemented(__my_func__,__LINE__); -} - -int CUDARTAPI __cudaSynchronizeThreads(void**, void*) -{ - //TODO This function should syncronize if we support Asyn kernel calls - return g_last_cudaError = cudaSuccess; -} - -} - -//////// - -extern int ptx_parse(); -extern int ptx__scan_string(const char*); -extern FILE *ptx_in; - -extern int ptxinfo_parse(); -extern int ptxinfo_debug; -extern FILE *ptxinfo_in; - -/// static functions - -static int load_static_globals( symbol_table *symtab, unsigned min_gaddr, unsigned max_gaddr, gpgpu_t *gpu ) -{ - printf( "GPGPU-Sim PTX: loading globals with explicit initializers... \n" ); - fflush(stdout); - int ng_bytes=0; - symbol_table::iterator g=symtab->global_iterator_begin(); - - for ( ; g!=symtab->global_iterator_end(); g++) { - symbol *global = *g; - if ( global->has_initializer() ) { - printf( "GPGPU-Sim PTX: initializing '%s' ... ", global->name().c_str() ); - unsigned addr=global->get_address(); - const type_info *type = global->type(); - type_info_key ti=type->get_key(); - size_t size; - int t; - ti.type_decode(size,t); - int nbytes = size/8; - int offset=0; - std::list init_list = global->get_initializer(); - for ( std::list::iterator i=init_list.begin(); i!=init_list.end(); i++ ) { - operand_info op = *i; - ptx_reg_t value = op.get_literal_value(); - assert( (addr+offset+nbytes) < min_gaddr ); // min_gaddr is start of "heap" for cudaMalloc - gpu->get_global_memory()->write(addr+offset,nbytes,&value,NULL,NULL); // assuming little endian here - offset+=nbytes; - ng_bytes+=nbytes; - } - printf(" wrote %u bytes\n", offset ); - } - } - printf( "GPGPU-Sim PTX: finished loading globals (%u bytes total).\n", ng_bytes ); - fflush(stdout); - return ng_bytes; -} - -static int load_constants( symbol_table *symtab, addr_t min_gaddr, gpgpu_t *gpu ) -{ - printf( "GPGPU-Sim PTX: loading constants with explicit initializers... " ); - fflush(stdout); - int nc_bytes = 0; - symbol_table::iterator g=symtab->const_iterator_begin(); - - for ( ; g!=symtab->const_iterator_end(); g++) { - symbol *constant = *g; - if ( constant->is_const() && constant->has_initializer() ) { - - // get the constant element data size - int basic_type; - size_t num_bits; - constant->type()->get_key().type_decode(num_bits,basic_type); - - std::list init_list = constant->get_initializer(); - int nbytes_written = 0; - for ( std::list::iterator i=init_list.begin(); i!=init_list.end(); i++ ) { - operand_info op = *i; - ptx_reg_t value = op.get_literal_value(); - int nbytes = num_bits/8; - switch ( op.get_type() ) { - case int_t: assert(nbytes >= 1); break; - case float_op_t: assert(nbytes == 4); break; - case double_op_t: assert(nbytes >= 4); break; // account for double DEMOTING - default: - abort(); - } - unsigned addr=constant->get_address() + nbytes_written; - assert( addr+nbytes < min_gaddr ); - - gpu->get_global_memory()->write(addr,nbytes,&value,NULL,NULL); // assume little endian (so u8 is the first byte in u32) - nc_bytes+=nbytes; - nbytes_written += nbytes; - } - } - } - printf( " done.\n"); - fflush(stdout); - return nc_bytes; -} - -kernel_info_t *gpgpu_cuda_ptx_sim_init_grid( const char *hostFun, - gpgpu_ptx_sim_arg_list_t args, - struct dim3 gridDim, - struct dim3 blockDim, - CUctx_st* context ) -{ - function_info *entry = context->get_kernel(hostFun); - kernel_info_t *result = new kernel_info_t(gridDim,blockDim,entry); - if( entry == NULL ) { - printf("GPGPU-Sim PTX: ERROR launching kernel -- no PTX implementation found for %p\n", hostFun); - abort(); - } - unsigned argcount=args.size(); - unsigned argn=1; - for( gpgpu_ptx_sim_arg_list_t::iterator a = args.begin(); a != args.end(); a++ ) { - entry->add_param_data(argcount-argn,&(*a)); - argn++; - } - - entry->finalize(result->get_param_memory()); - g_ptx_kernel_count++; - fflush(stdout); - - return result; -} diff --git a/src/cuda-sim/cuda-sim.cc~ b/src/cuda-sim/cuda-sim.cc~ deleted file mode 100644 index cfd901f..0000000 --- a/src/cuda-sim/cuda-sim.cc~ +++ /dev/null @@ -1,2155 +0,0 @@ -// Copyright (c) 2009-2011, Tor M. Aamodt, Ali Bakhoda, Wilson W.L. Fung, -// George L. Yuan, Jimmy Kwa -// The University of British Columbia -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// Redistributions in binary form must reproduce the above copyright notice, this -// list of conditions and the following disclaimer in the documentation and/or -// other materials provided with the distribution. -// Neither the name of The University of British Columbia nor the names of its -// contributors may be used to endorse or promote products derived from this -// software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -#include "cuda-sim.h" - -#include "instructions.h" -#include "ptx_ir.h" -#include "ptx.tab.h" -#include "ptx_sim.h" -#include - -#include "opcodes.h" -#include "../statwrapper.h" -#include -#include -#include "../abstract_hardware_model.h" -#include "memory.h" -#include "ptx-stats.h" -#include "ptx_loader.h" -#include "ptx_parser.h" -#include "../gpgpu-sim/gpu-sim.h" -#include "ptx_sim.h" -#include "../gpgpusim_entrypoint.h" -#include "decuda_pred_table/decuda_pred_table.h" -#include "../stream_manager.h" -#include "cuda_device_runtime.h" - -int gpgpu_ptx_instruction_classification; -void ** g_inst_classification_stat = NULL; -void ** g_inst_op_classification_stat= NULL; -int g_ptx_kernel_count = -1; // used for classification stat collection purposes -int g_debug_execution = 0; -int g_debug_thread_uid = 0; -addr_t g_debug_pc = 0xBEEF1518; -// Output debug information to file options - -unsigned g_ptx_sim_num_insn = 0; -unsigned gpgpu_param_num_shaders = 0; - -char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp; -char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp; -char *cdp_latency_str; -unsigned cdp_latency[5]; - -void ptx_opcocde_latency_options (option_parser_t opp) { - option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, - "Opcode latencies for integers " - "Default 1,1,19,25,145", - "1,1,19,25,145"); - option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp, - "Opcode latencies for single precision floating points " - "Default 1,1,1,1,30", - "1,1,1,1,30"); - option_parser_register(opp, "-ptx_opcode_latency_dp", OPT_CSTR, &opcode_latency_dp, - "Opcode latencies for double precision floating points " - "Default 8,8,8,8,335", - "8,8,8,8,335"); - option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, - "Opcode initiation intervals for integers " - "Default 1,1,4,4,32", - "1,1,4,4,32"); - option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp, - "Opcode initiation intervals for single precision floating points " - "Default 1,1,1,1,5", - "1,1,1,1,5"); - option_parser_register(opp, "-ptx_opcode_initiation_dp", OPT_CSTR, &opcode_initiation_dp, - "Opcode initiation intervals for double precision floating points " - "Default 8,8,8,8,130", - "8,8,8,8,130"); - option_parser_register(opp, "-cdp_latency", OPT_CSTR, &cdp_latency_str, - "CDP API latency " - "Default 7200,8000,100,12000,1600", - "7200,8000,100,12000,1600"); -} - -static address_type get_converge_point(address_type pc); - -void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) -{ - std::string texname(name); - m_NameToTextureRef[texname] = texref; - const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); - m_TextureRefToAttribute[texref] = texAttr; -} - -const char* gpgpu_t::gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref) -{ - std::map::iterator itr = m_NameToTextureRef.begin(); - while (itr != m_NameToTextureRef.end()) { - if ((*itr).second == texref) { - const char *p = ((*itr).first).c_str(); - return p; - } - itr++; - } - return NULL; -} - -unsigned int intLOGB2( unsigned int v ) { - unsigned int shift; - unsigned int r; - - r = 0; - - shift = (( v & 0xFFFF0000) != 0 ) << 4; v >>= shift; r |= shift; - shift = (( v & 0xFF00 ) != 0 ) << 3; v >>= shift; r |= shift; - shift = (( v & 0xF0 ) != 0 ) << 2; v >>= shift; r |= shift; - shift = (( v & 0xC ) != 0 ) << 1; v >>= shift; r |= shift; - shift = (( v & 0x2 ) != 0 ) << 0; v >>= shift; r |= shift; - - return r; -} - -void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) -{ - m_TextureRefToCudaArray[texref] = array; - unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; - unsigned int texel_size = texel_size_bits/8; - unsigned int Tx, Ty; - int r; - - printf("GPGPU-Sim PTX: texel size = %d\n", texel_size); - printf("GPGPU-Sim PTX: texture cache linesize = %d\n", m_function_model_config.get_texcache_linesize()); - //first determine base Tx size for given linesize - switch (m_function_model_config.get_texcache_linesize()) { - case 16: Tx = 4; break; - case 32: Tx = 8; break; - case 64: Tx = 8; break; - case 128: Tx = 16; break; - case 256: Tx = 16; break; - default: - printf("GPGPU-Sim PTX: Line size of %d bytes currently not supported.\n", m_function_model_config.get_texcache_linesize()); - assert(0); - break; - } - r = texel_size >> 2; - //modify base Tx size to take into account size of each texel in bytes - while (r != 0) { - Tx = Tx >> 1; - r = r >> 2; - } - //by now, got the correct Tx size, calculate correct Ty size - Ty = m_function_model_config.get_texcache_linesize()/(Tx*texel_size); - - printf("GPGPU-Sim PTX: Tx = %d; Ty = %d, Tx_numbits = %d, Ty_numbits = %d\n", Tx, Ty, intLOGB2(Tx), intLOGB2(Ty)); - printf("GPGPU-Sim PTX: Texel size = %d bytes; texel_size_numbits = %d\n", texel_size, intLOGB2(texel_size)); - printf("GPGPU-Sim PTX: Binding texture to array starting at devPtr32 = 0x%x\n", array->devPtr32); - printf("GPGPU-Sim PTX: Texel size = %d bytes\n", texel_size); - struct textureInfo* texInfo = (struct textureInfo*) malloc(sizeof(struct textureInfo)); - texInfo->Tx = Tx; - texInfo->Ty = Ty; - texInfo->Tx_numbits = intLOGB2(Tx); - texInfo->Ty_numbits = intLOGB2(Ty); - texInfo->texel_size = texel_size; - texInfo->texel_size_numbits = intLOGB2(texel_size); - m_TextureRefToTexureInfo[texref] = texInfo; -} - -unsigned g_assemble_code_next_pc=0; -std::map g_pc_to_finfo; -std::vector function_info::s_g_pc_to_insn; - -#define MAX_INST_SIZE 8 /*bytes*/ - -void function_info::ptx_assemble() -{ - if( m_assembled ) { - return; - } - - // get the instructions into instruction memory... - unsigned num_inst = m_instructions.size(); - m_instr_mem_size = MAX_INST_SIZE*(num_inst+1); - m_instr_mem = new ptx_instruction*[ m_instr_mem_size ]; - - printf("GPGPU-Sim PTX: instruction assembly for function \'%s\'... ", m_name.c_str() ); - fflush(stdout); - std::list::iterator i; - - addr_t PC = g_assemble_code_next_pc; // globally unique address (across functions) - // start function on an aligned address - for( unsigned i=0; i < (PC%MAX_INST_SIZE); i++ ) - s_g_pc_to_insn.push_back((ptx_instruction*)NULL); - PC += PC%MAX_INST_SIZE; - m_start_PC = PC; - - addr_t n=0; // offset in m_instr_mem - //Why s_g_pc_to_insn.size() is needed to reserve additional memory for insts? reserve is cumulative. - //s_g_pc_to_insn.reserve(s_g_pc_to_insn.size() + MAX_INST_SIZE*m_instructions.size()); - s_g_pc_to_insn.reserve(MAX_INST_SIZE*m_instructions.size()); - for ( i=m_instructions.begin(); i != m_instructions.end(); i++ ) { - ptx_instruction *pI = *i; - if ( pI->is_label() ) { - const symbol *l = pI->get_label(); - labels[l->name()] = n; - } else { - g_pc_to_finfo[PC] = this; - m_instr_mem[n] = pI; - s_g_pc_to_insn.push_back(pI); - assert(pI == s_g_pc_to_insn[PC]); - pI->set_m_instr_mem_index(n); - pI->set_PC(PC); - assert( pI->inst_size() <= MAX_INST_SIZE ); - for( unsigned i=1; i < pI->inst_size(); i++ ) { - s_g_pc_to_insn.push_back((ptx_instruction*)NULL); - m_instr_mem[n+i]=NULL; - } - n += pI->inst_size(); - PC += pI->inst_size(); - } - } - g_assemble_code_next_pc=PC; - for ( unsigned ii=0; ii < n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions - ptx_instruction *pI = m_instr_mem[ii]; - if ( pI->get_opcode() == BRA_OP || pI->get_opcode() == BREAKADDR_OP || pI->get_opcode() == CALLP_OP) { - operand_info &target = pI->dst(); //get operand, e.g. target name - if ( labels.find(target.name()) == labels.end() ) { - printf("GPGPU-Sim PTX: Loader error (%s:%u): Branch label \"%s\" does not appear in assembly code.", - pI->source_file(),pI->source_line(), target.name().c_str() ); - abort(); - } - unsigned index = labels[ target.name() ]; //determine address from name - unsigned PC = m_instr_mem[index]->get_PC(); - m_symtab->set_label_address( target.get_symbol(), PC ); - target.set_type(label_t); - } - } - m_n = n; - printf(" done.\n"); - fflush(stdout); - - //disable pdom analysis here and do it at runtime - printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", m_name.c_str() ); - create_basic_blocks(); - connect_basic_blocks(); - bool modified = false; - do { - find_dominators(); - find_idominators(); - modified = connect_break_targets(); - } while (modified == true); - - if ( g_debug_execution>=50 ) { - print_basic_blocks(); - print_basic_block_links(); - print_basic_block_dot(); - } - if ( g_debug_execution>=2 ) { - print_dominators(); - } - find_postdominators(); - find_ipostdominators(); - if ( g_debug_execution>=50 ) { - print_postdominators(); - print_ipostdominators(); - } - - printf("GPGPU-Sim PTX: pre-decoding instructions for \'%s\'...\n", m_name.c_str() ); - for ( unsigned ii=0; ii < n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions - ptx_instruction *pI = m_instr_mem[ii]; - pI->pre_decode(); - } - printf("GPGPU-Sim PTX: ... done pre-decoding instructions for \'%s\'.\n", m_name.c_str() ); - fflush(stdout); - - m_assembled = true; -} - -addr_t shared_to_generic( unsigned smid, addr_t addr ) -{ - assert( addr < SHARED_MEM_SIZE_MAX ); - return SHARED_GENERIC_START + smid*SHARED_MEM_SIZE_MAX + addr; -} - -addr_t global_to_generic( addr_t addr ) -{ - return addr; -} - -bool isspace_shared( unsigned smid, addr_t addr ) -{ - addr_t start = SHARED_GENERIC_START + smid*SHARED_MEM_SIZE_MAX; - addr_t end = SHARED_GENERIC_START + (smid+1)*SHARED_MEM_SIZE_MAX; - if( (addr >= end) || (addr < start) ) - return false; - return true; -} - -bool isspace_global( addr_t addr ) -{ - return (addr >= GLOBAL_HEAP_START) || (addr < STATIC_ALLOC_LIMIT); -} - -memory_space_t whichspace( addr_t addr ) -{ - if( (addr >= GLOBAL_HEAP_START) || (addr < STATIC_ALLOC_LIMIT) ) { - return global_space; - } else if( addr >= SHARED_GENERIC_START ) { - return shared_space; - } else { - return local_space; - } -} - -addr_t generic_to_shared( unsigned smid, addr_t addr ) -{ - assert(isspace_shared(smid,addr)); - return addr - (SHARED_GENERIC_START + smid*SHARED_MEM_SIZE_MAX); -} - -addr_t local_to_generic( unsigned smid, unsigned hwtid, addr_t addr ) -{ - assert(addr < LOCAL_MEM_SIZE_MAX); - return LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * hwtid) + addr; -} - -bool isspace_local( unsigned smid, unsigned hwtid, addr_t addr ) -{ - addr_t start = LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * hwtid); - addr_t end = LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * (hwtid+1)); - if( (addr >= end) || (addr < start) ) - return false; - return true; -} - -addr_t generic_to_local( unsigned smid, unsigned hwtid, addr_t addr ) -{ - assert(isspace_local(smid,hwtid,addr)); - return addr - (LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * hwtid)); -} - -addr_t generic_to_global( addr_t addr ) -{ - return addr; -} - - -void* gpgpu_t::gpu_malloc( size_t size ) -{ - unsigned long long result = m_dev_malloc; - if(g_debug_execution >= 3) { - printf("GPGPU-Sim PTX: allocating %zu bytes on GPU starting at address 0x%Lx\n", size, m_dev_malloc ); - fflush(stdout); - } - m_dev_malloc += size; - if (size%256) m_dev_malloc += (256 - size%256); //align to 256 byte boundaries - return(void*) result; -} - -void* gpgpu_t::gpu_mallocarray( size_t size ) -{ - unsigned long long result = m_dev_malloc; - if(g_debug_execution >= 3) { - printf("GPGPU-Sim PTX: allocating %zu bytes on GPU starting at address 0x%Lx\n", size, m_dev_malloc ); - fflush(stdout); - } - m_dev_malloc += size; - if (size%256) m_dev_malloc += (256 - size%256); //align to 256 byte boundaries - return(void*) result; -} - - -void gpgpu_t::memcpy_to_gpu( size_t dst_start_addr, const void *src, size_t count ) -{ - if(g_debug_execution >= 3) { - printf("GPGPU-Sim PTX: copying %zu bytes from CPU[0x%Lx] to GPU[0x%Lx] ... ", count, (unsigned long long) src, (unsigned long long) dst_start_addr ); - fflush(stdout); - } - char *src_data = (char*)src; - for (unsigned n=0; n < count; n ++ ) - m_global_mem->write(dst_start_addr+n,1, src_data+n,NULL,NULL); - if(g_debug_execution >= 3) { - printf( " done.\n"); - fflush(stdout); - } -} - -void gpgpu_t::memcpy_from_gpu( void *dst, size_t src_start_addr, size_t count ) -{ - if(g_debug_execution >= 3) { - printf("GPGPU-Sim PTX: copying %zu bytes from GPU[0x%Lx] to CPU[0x%Lx] ...", count, (unsigned long long) src_start_addr, (unsigned long long) dst ); - fflush(stdout); - } - unsigned char *dst_data = (unsigned char*)dst; - for (unsigned n=0; n < count; n ++ ) - m_global_mem->read(src_start_addr+n,1,dst_data+n); - if(g_debug_execution >= 3) { - printf( " done.\n"); - fflush(stdout); - } -} - -void gpgpu_t::memcpy_gpu_to_gpu( size_t dst, size_t src, size_t count ) -{ - if(g_debug_execution >= 3) { - printf("GPGPU-Sim PTX: copying %zu bytes from GPU[0x%Lx] to GPU[0x%Lx] ...", count, - (unsigned long long) src, (unsigned long long) dst ); - fflush(stdout); - } - for (unsigned n=0; n < count; n ++ ) { - unsigned char tmp; - m_global_mem->read(src+n,1,&tmp); - m_global_mem->write(dst+n,1, &tmp,NULL,NULL); - } - if(g_debug_execution >= 3) { - printf( " done.\n"); - fflush(stdout); - } -} - -void gpgpu_t::gpu_memset( size_t dst_start_addr, int c, size_t count ) -{ - if(g_debug_execution >= 3) { - printf("GPGPU-Sim PTX: setting %zu bytes of memory to 0x%x starting at 0x%Lx... ", - count, (unsigned char) c, (unsigned long long) dst_start_addr ); - fflush(stdout); - } - unsigned char c_value = (unsigned char)c; - for (unsigned n=0; n < count; n ++ ) - m_global_mem->write(dst_start_addr+n,1,&c_value,NULL,NULL); - if(g_debug_execution >= 3) { - printf( " done.\n"); - fflush(stdout); - } -} - -void ptx_print_insn( address_type pc, FILE *fp ) -{ - std::map::iterator f = g_pc_to_finfo.find(pc); - if( f == g_pc_to_finfo.end() ) { - fprintf(fp,"", pc ); - return; - } - function_info *finfo = f->second; - assert( finfo ); - finfo->print_insn(pc,fp); -} - -std::string ptx_get_insn_str( address_type pc ) -{ - std::map::iterator f = g_pc_to_finfo.find(pc); - if( f == g_pc_to_finfo.end() ) { - #define STR_SIZE 255 - char buff[STR_SIZE]; - buff[STR_SIZE - 1] = '\0'; - snprintf(buff, STR_SIZE,"", pc ); - return std::string(buff); - } - function_info *finfo = f->second; - assert( finfo ); - return finfo->get_insn_str(pc); -} - -void ptx_instruction::set_fp_or_int_archop(){ - oprnd_type=UN_OP; - if((m_opcode == MEMBAR_OP)||(m_opcode == SSY_OP )||(m_opcode == BRA_OP) || (m_opcode == BAR_OP) || (m_opcode == RET_OP) || (m_opcode == RETP_OP) || (m_opcode == NOP_OP) || (m_opcode == EXIT_OP) || (m_opcode == CALLP_OP) || (m_opcode == CALL_OP)){ - // do nothing - }else if((m_opcode == CVT_OP || m_opcode == SET_OP || m_opcode == SLCT_OP)){ - if(get_type2()==F16_TYPE || get_type2()==F32_TYPE || get_type2() == F64_TYPE || get_type2() == FF64_TYPE){ - oprnd_type= FP_OP; - }else oprnd_type=INT_OP; - - }else{ - if(get_type()==F16_TYPE || get_type()==F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE){ - oprnd_type= FP_OP; - }else oprnd_type=INT_OP; - } -} -void ptx_instruction::set_mul_div_or_other_archop(){ - sp_op=OTHER_OP; - if((m_opcode != MEMBAR_OP) && (m_opcode != SSY_OP) && (m_opcode != BRA_OP) && (m_opcode != BAR_OP) && (m_opcode != EXIT_OP) && (m_opcode != NOP_OP) && (m_opcode != RETP_OP) && (m_opcode != RET_OP) && (m_opcode != CALLP_OP) && (m_opcode != CALL_OP)){ - if(get_type()==F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE){ - switch(get_opcode()){ - case MUL_OP: - case MAD_OP: - sp_op=FP_MUL_OP; - break; - case DIV_OP: - sp_op=FP_DIV_OP; - break; - case LG2_OP: - sp_op=FP_LG_OP; - break; - case RSQRT_OP: - case SQRT_OP: - sp_op=FP_SQRT_OP; - break; - case RCP_OP: - sp_op=FP_DIV_OP; - break; - case SIN_OP: - case COS_OP: - sp_op=FP_SIN_OP; - break; - case EX2_OP: - sp_op=FP_EXP_OP; - break; - default: - if(op==ALU_OP) - sp_op=FP__OP; - break; - - } - }else { - switch(get_opcode()){ - case MUL24_OP: - case MAD24_OP: - sp_op=INT_MUL24_OP; - break; - case MUL_OP: - case MAD_OP: - if(get_type()==U32_TYPE || get_type()==S32_TYPE || get_type()==B32_TYPE) - sp_op=INT_MUL32_OP; - else - sp_op=INT_MUL_OP; - break; - case DIV_OP: - sp_op=INT_DIV_OP; - break; - default: - if(op==ALU_OP) - sp_op=INT__OP; - break; - } - } - } - -} - - - -void ptx_instruction::set_bar_type() -{ - if(m_opcode==BAR_OP) { - switch(m_barrier_op){ - case SYNC_OPTION: - bar_type = SYNC; - break; - case ARRIVE_OPTION: - bar_type = ARRIVE; - break; - case RED_OPTION: - bar_type = RED; - switch(m_atomic_spec){ - case ATOMIC_POPC: - red_type = POPC_RED; - break; - case ATOMIC_AND: - red_type = AND_RED; - break; - case ATOMIC_OR: - red_type = OR_RED; - break; - } - break; - default: - abort(); - } - } -} - - -void ptx_instruction::set_opcode_and_latency() -{ - unsigned int_latency[5]; - unsigned fp_latency[5]; - unsigned dp_latency[5]; - unsigned int_init[5]; - unsigned fp_init[5]; - unsigned dp_init[5]; - /* - * [0] ADD,SUB - * [1] MAX,Min - * [2] MUL - * [3] MAD - * [4] DIV - */ - sscanf(opcode_latency_int, "%u,%u,%u,%u,%u", - &int_latency[0],&int_latency[1],&int_latency[2], - &int_latency[3],&int_latency[4]); - sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u", - &fp_latency[0],&fp_latency[1],&fp_latency[2], - &fp_latency[3],&fp_latency[4]); - sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u", - &dp_latency[0],&dp_latency[1],&dp_latency[2], - &dp_latency[3],&dp_latency[4]); - sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u", - &int_init[0],&int_init[1],&int_init[2], - &int_init[3],&int_init[4]); - sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u", - &fp_init[0],&fp_init[1],&fp_init[2], - &fp_init[3],&fp_init[4]); - sscanf(opcode_initiation_dp, "%u,%u,%u,%u,%u", - &dp_init[0],&dp_init[1],&dp_init[2], - &dp_init[3],&dp_init[4]); - sscanf(cdp_latency_str, "%u,%u,%u,%u,%u", - &cdp_latency[0],&cdp_latency[1],&cdp_latency[2], - &cdp_latency[3],&cdp_latency[4]); - - if(!m_operands.empty()){ - std::vector::iterator it; - for(it=++m_operands.begin();it!=m_operands.end();it++){ - num_operands++; - if((it->is_reg() || it->is_vector())){ - num_regs++; - } - } - } - op = ALU_OP; - mem_op= NOT_TEX; - initiation_interval = latency = 1; - switch( m_opcode ) { - case MOV_OP: - assert( !(has_memory_read() && has_memory_write()) ); - if ( has_memory_read() ) op = LOAD_OP; - if ( has_memory_write() ) op = STORE_OP; - break; - case LD_OP: op = LOAD_OP; break; - case LDU_OP: op = LOAD_OP; break; - case ST_OP: op = STORE_OP; break; - case BRA_OP: op = BRANCH_OP; break; - case BREAKADDR_OP: op = BRANCH_OP; break; - case TEX_OP: op = LOAD_OP; mem_op=TEX; break; - case ATOM_OP: op = LOAD_OP; break; - case BAR_OP: op = BARRIER_OP; break; - case MEMBAR_OP: op = MEMORY_BARRIER_OP; break; - case CALL_OP: - { - if(m_is_printf || m_is_cdp) { - op = ALU_OP; - } - else - op = CALL_OPS; - break; - } - case CALLP_OP: - { - if(m_is_printf || m_is_cdp) { - op = ALU_OP; - } - else - op = CALL_OPS; - break; - } - case RET_OP: case RETP_OP: op = RET_OPS;break; - case ADD_OP: case ADDP_OP: case ADDC_OP: case SUB_OP: case SUBC_OP: - //ADD,SUB latency - switch(get_type()){ - case F32_TYPE: - latency = fp_latency[0]; - initiation_interval = fp_init[0]; - break; - case F64_TYPE: - case FF64_TYPE: - latency = dp_latency[0]; - initiation_interval = dp_init[0]; - break; - case B32_TYPE: - case U32_TYPE: - case S32_TYPE: - default: //Use int settings for default - latency = int_latency[0]; - initiation_interval = int_init[0]; - break; - } - break; - case MAX_OP: case MIN_OP: - //MAX,MIN latency - switch(get_type()){ - case F32_TYPE: - latency = fp_latency[1]; - initiation_interval = fp_init[1]; - break; - case F64_TYPE: - case FF64_TYPE: - latency = dp_latency[1]; - initiation_interval = dp_init[1]; - break; - case B32_TYPE: - case U32_TYPE: - case S32_TYPE: - default: //Use int settings for default - latency = int_latency[1]; - initiation_interval = int_init[1]; - break; - } - break; - case MUL_OP: - //MUL latency - switch(get_type()){ - case F32_TYPE: - latency = fp_latency[2]; - initiation_interval = fp_init[2]; - op = ALU_SFU_OP; - break; - case F64_TYPE: - case FF64_TYPE: - latency = dp_latency[2]; - initiation_interval = dp_init[2]; - op = ALU_SFU_OP; - break; - case B32_TYPE: - case U32_TYPE: - case S32_TYPE: - default: //Use int settings for default - latency = int_latency[2]; - initiation_interval = int_init[2]; - op = SFU_OP; - break; - } - break; - case MAD_OP: case MADC_OP: case MADP_OP: - //MAD latency - switch(get_type()){ - case F32_TYPE: - latency = fp_latency[3]; - initiation_interval = fp_init[3]; - break; - case F64_TYPE: - case FF64_TYPE: - latency = dp_latency[3]; - initiation_interval = dp_init[3]; - break; - case B32_TYPE: - case U32_TYPE: - case S32_TYPE: - default: //Use int settings for default - latency = int_latency[3]; - initiation_interval = int_init[3]; - op = SFU_OP; - break; - } - break; - case DIV_OP: - // Floating point only - op = SFU_OP; - switch(get_type()){ - case F32_TYPE: - latency = fp_latency[4]; - initiation_interval = fp_init[4]; - break; - case F64_TYPE: - case FF64_TYPE: - latency = dp_latency[4]; - initiation_interval = dp_init[4]; - break; - case B32_TYPE: - case U32_TYPE: - case S32_TYPE: - default: //Use int settings for default - latency = int_latency[4]; - initiation_interval = int_init[4]; - break; - } - break; - case SQRT_OP: case SIN_OP: case COS_OP: case EX2_OP: case LG2_OP: case RSQRT_OP: case RCP_OP: - //Using double to approximate those - latency = dp_latency[2]; - initiation_interval = dp_init[2]; - op = SFU_OP; - break; - case SHFL_OP: - latency = 32; - initiation_interval = 15; - break; - default: - break; - } - set_fp_or_int_archop(); - set_mul_div_or_other_archop(); - -} - -void ptx_thread_info::ptx_fetch_inst( inst_t &inst ) const -{ - addr_t pc = get_pc(); - const ptx_instruction *pI = m_func_info->get_instruction(pc); - inst = (const inst_t&)*pI; - assert( inst.valid() ); -} - -static unsigned datatype2size( unsigned data_type ) -{ - unsigned data_size; - switch ( data_type ) { - case B8_TYPE: - case S8_TYPE: - case U8_TYPE: - data_size = 1; break; - case B16_TYPE: - case S16_TYPE: - case U16_TYPE: - case F16_TYPE: - data_size = 2; break; - case B32_TYPE: - case S32_TYPE: - case U32_TYPE: - case F32_TYPE: - data_size = 4; break; - case B64_TYPE: - case BB64_TYPE: - case S64_TYPE: - case U64_TYPE: - case F64_TYPE: - case FF64_TYPE: - data_size = 8; break; - case BB128_TYPE: - data_size = 16; break; - default: assert(0); break; - } - return data_size; -} - -void ptx_instruction::pre_decode() -{ - pc = m_PC; - isize = m_inst_size; - for( unsigned i=0; i<4; i++) { - out[i] = 0; - in[i] = 0; - } - is_vectorin = 0; - is_vectorout = 0; - std::fill_n(arch_reg.src, MAX_REG_OPERANDS, -1); - std::fill_n(arch_reg.dst, MAX_REG_OPERANDS, -1); - pred = 0; - ar1 = 0; - ar2 = 0; - space = m_space_spec; - memory_op = no_memory_op; - data_size = 0; - if ( has_memory_read() || has_memory_write() ) { - unsigned to_type = get_type(); - data_size = datatype2size(to_type); - memory_op = has_memory_read() ? memory_load : memory_store; - } - - bool has_dst = false ; - - switch ( get_opcode() ) { -#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; -#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; -#include "opcodes.def" -#undef OP_DEF -#undef OP_W_DEF - default: - printf( "Execution error: Invalid opcode (0x%x)\n", get_opcode() ); - break; - } - - switch( m_cache_option ) { - case CA_OPTION: cache_op = CACHE_ALL; break; - case CG_OPTION: cache_op = CACHE_GLOBAL; break; - case CS_OPTION: cache_op = CACHE_STREAMING; break; - case LU_OPTION: cache_op = CACHE_LAST_USE; break; - case CV_OPTION: cache_op = CACHE_VOLATILE; break; - case WB_OPTION: cache_op = CACHE_WRITE_BACK; break; - case WT_OPTION: cache_op = CACHE_WRITE_THROUGH; break; - default: - if( m_opcode == LD_OP || m_opcode == LDU_OP ) - cache_op = CACHE_ALL; - else if( m_opcode == ST_OP ) - cache_op = CACHE_WRITE_BACK; - else if( m_opcode == ATOM_OP ) - cache_op = CACHE_GLOBAL; - break; - } - - set_opcode_and_latency(); - set_bar_type(); - // Get register operands - int n=0,m=0; - ptx_instruction::const_iterator opr=op_iter_begin(); - for ( ; opr != op_iter_end(); opr++, n++ ) { //process operands - const operand_info &o = *opr; - if ( has_dst && n==0 ) { - // Do not set the null register "_" as an architectural register - if ( o.is_reg() && !o.is_non_arch_reg() ) { - out[0] = o.reg_num(); - arch_reg.dst[0] = o.arch_reg_num(); - } else if ( o.is_vector() ) { - is_vectorin = 1; - unsigned num_elem = o.get_vect_nelem(); - if( num_elem >= 1 ) out[0] = o.reg1_num(); - if( num_elem >= 2 ) out[1] = o.reg2_num(); - if( num_elem >= 3 ) out[2] = o.reg3_num(); - if( num_elem >= 4 ) out[3] = o.reg4_num(); - for (int i = 0; i < num_elem; i++) - arch_reg.dst[i] = o.arch_reg_num(i); - } - } else { - if ( o.is_reg() && !o.is_non_arch_reg() ) { - int reg_num = o.reg_num(); - arch_reg.src[m] = o.arch_reg_num(); - switch ( m ) { - case 0: in[0] = reg_num; break; - case 1: in[1] = reg_num; break; - case 2: in[2] = reg_num; break; - default: break; - } - m++; - } else if ( o.is_vector() ) { - //assert(m == 0); //only support 1 vector operand (for textures) right now - is_vectorout = 1; - unsigned num_elem = o.get_vect_nelem(); - if( num_elem >= 1 ) in[0] = o.reg1_num(); - if( num_elem >= 2 ) in[1] = o.reg2_num(); - if( num_elem >= 3 ) in[2] = o.reg3_num(); - if( num_elem >= 4 ) in[3] = o.reg4_num(); - for (int i = 0; i < num_elem; i++) - arch_reg.src[i] = o.arch_reg_num(i); - m+=4; - } - } - } - - // Get predicate - if(has_pred()) { - const operand_info &p = get_pred(); - pred = p.reg_num(); - } - - // Get address registers inside memory operands. - // Assuming only one memory operand per instruction, - // and maximum of two address registers for one memory operand. - if( has_memory_read() || has_memory_write() ) { - ptx_instruction::const_iterator op=op_iter_begin(); - for ( ; op != op_iter_end(); op++, n++ ) { //process operands - const operand_info &o = *op; - - if(o.is_memory_operand()) { - // We do not support the null register as a memory operand - assert( !o.is_non_arch_reg() ); - - // Check PTXPlus-type operand - // memory operand with addressing (ex. s[0x4] or g[$r1]) - if(o.is_memory_operand2()) { - - // memory operand with one address register (ex. g[$r1+0x4] or s[$r2+=0x4]) - if(o.get_double_operand_type() == 0 || o.get_double_operand_type() == 3){ - ar1 = o.reg_num(); - arch_reg.src[4] = o.arch_reg_num(); - // TODO: address register in $r2+=0x4 should be an output register as well - } - // memory operand with two address register (ex. s[$r1+$r1] or g[$r1+=$r2]) - else if(o.get_double_operand_type() == 1 || o.get_double_operand_type() == 2) { - ar1 = o.reg1_num(); - arch_reg.src[4] = o.arch_reg_num(); - ar2 = o.reg2_num(); - arch_reg.src[5] = o.arch_reg_num(); - // TODO: first address register in $r1+=$r2 should be an output register as well - } - } - else if(o.is_immediate_address()){ - - } - // Regular PTX operand - else if (o.get_symbol()->type()->get_key().is_reg()) { // Memory operand contains a register - ar1 = o.reg_num(); - arch_reg.src[4] = o.arch_reg_num(); - } - - } - } - } - - // get reconvergence pc - reconvergence_pc = get_converge_point(pc); - - m_decoded=true; -} - -void function_info::add_param_name_type_size( unsigned index, std::string name, int type, size_t size, bool ptr, memory_space_t space ) -{ - unsigned parsed_index; - char buffer[2048]; - snprintf(buffer,2048,"%s_param_%%u", m_name.c_str() ); - int ntokens = sscanf(name.c_str(),buffer,&parsed_index); - if( ntokens == 1 ) { - assert( m_ptx_kernel_param_info.find(parsed_index) == m_ptx_kernel_param_info.end() ); - m_ptx_kernel_param_info[parsed_index] = param_info(name, type, size, ptr, space); - } else { - assert( m_ptx_kernel_param_info.find(index) == m_ptx_kernel_param_info.end() ); - m_ptx_kernel_param_info[index] = param_info(name, type, size, ptr, space); - } -} - -void function_info::add_param_data( unsigned argn, struct gpgpu_ptx_sim_arg *args ) -{ - const void *data = args->m_start; - - bool scratchpad_memory_param = false; // Is this parameter in CUDA shared memory or OpenCL local memory - - std::map::iterator i=m_ptx_kernel_param_info.find(argn); - if( i != m_ptx_kernel_param_info.end() ) { - if (i->second.is_ptr_shared()) { - assert(args->m_start == NULL && "OpenCL parameter pointer to local memory must have NULL as value"); - scratchpad_memory_param = true; - } else { - param_t tmp; - tmp.pdata = args->m_start; - tmp.size = args->m_nbytes; - tmp.offset = args->m_offset; - tmp.type = 0; - i->second.add_data(tmp); - i->second.add_offset((unsigned) args->m_offset); - } - } else { - scratchpad_memory_param = true; - } - - if (scratchpad_memory_param) { - // This should only happen for OpenCL: - // - // The LLVM PTX compiler in NVIDIA's driver (version 190.29) - // does not generate an argument in the function declaration - // for __constant arguments. - // - // The associated constant memory space can be allocated in two - // ways. It can be explicitly initialized in the .ptx file where - // it is declared. Or, it can be allocated using the clCreateBuffer - // on the host. In this later case, the .ptx file will contain - // a global declaration of the parameter, but it will have an unknown - // array size. Thus, the symbol's address will not be set and we need - // to set it here before executing the PTX. - - char buffer[2048]; - snprintf(buffer,2048,"%s_param_%u",m_name.c_str(),argn); - - symbol *p = m_symtab->lookup(buffer); - if( p == NULL ) { - printf("GPGPU-Sim PTX: ERROR ** could not locate symbol for \'%s\' : cannot bind buffer\n", buffer); - abort(); - } - if( data ) - p->set_address((addr_t)*(size_t*)data); - else { - // clSetKernelArg was passed NULL pointer for data... - // this is used for dynamically sized shared memory on NVIDIA platforms - bool is_ptr_shared = false; - if( i != m_ptx_kernel_param_info.end() ) { - is_ptr_shared = i->second.is_ptr_shared(); - } - - if( !is_ptr_shared and !p->is_shared() ) { - printf("GPGPU-Sim PTX: ERROR ** clSetKernelArg passed NULL but arg not shared memory\n"); - abort(); - } - unsigned num_bits = 8*args->m_nbytes; - printf("GPGPU-Sim PTX: deferred allocation of shared region for \"%s\" from 0x%x to 0x%x (shared memory space)\n", - p->name().c_str(), - m_symtab->get_shared_next(), - m_symtab->get_shared_next() + num_bits/8 ); - fflush(stdout); - assert( (num_bits%8) == 0 ); - addr_t addr = m_symtab->get_shared_next(); - addr_t addr_pad = num_bits ? (((num_bits/8) - (addr % (num_bits/8))) % (num_bits/8)) : 0; - p->set_address( addr+addr_pad ); - m_symtab->alloc_shared( num_bits/8 + addr_pad ); - } - } -} - -unsigned function_info::get_args_aligned_size() { - - if(m_args_aligned_size >= 0) - return m_args_aligned_size; - - unsigned param_address = 0; - unsigned int total_size = 0; - for( std::map::iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { - param_info &p = i->second; - std::string name = p.get_name(); - symbol *param = m_symtab->lookup(name.c_str()); - - size_t arg_size = p.get_size() / 8; // size of param in bytes - total_size = (total_size + arg_size - 1) / arg_size * arg_size; //aligned - p.add_offset(total_size); - param->set_address(param_address + total_size); - total_size += arg_size; - } - - m_args_aligned_size = (total_size + 3) / 4 * 4; //final size aligned to word - - return m_args_aligned_size; - -} - - -void function_info::finalize( memory_space *param_mem ) -{ - unsigned param_address = 0; - for( std::map::iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { - param_info &p = i->second; - if (p.is_ptr_shared()) continue; // Pointer to local memory: Should we pass the allocated shared memory address to the param memory space? - std::string name = p.get_name(); - int type = p.get_type(); - param_t param_value = p.get_value(); - param_value.type = type; - symbol *param = m_symtab->lookup(name.c_str()); - unsigned xtype = param->type()->get_key().scalar_type(); - assert(xtype==(unsigned)type); - size_t size; - size = param_value.size; // size of param in bytes - // assert(param_value.offset == param_address); - if( size != p.get_size() / 8) { - printf("GPGPU-Sim PTX: WARNING actual kernel paramter size = %zu bytes vs. formal size = %zu (using smaller of two)\n", - size, p.get_size()/8); - size = (size<(p.get_size()/8))?size:(p.get_size()/8); - } - // copy the parameter over word-by-word so that parameter that crosses a memory page can be copied over - //Jin: copy parameter using aligned rules - const size_t word_size = 4; - param_address = (param_address + size - 1) / size * size; //aligned with size - for (size_t idx = 0; idx < size; idx += word_size) { - const char *pdata = reinterpret_cast(param_value.pdata) + idx; // cast to char * for ptr arithmetic - param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); - } - unsigned offset = p.get_offset(); - assert(offset == param_address); - param->set_address(param_address); - param_address += size; - } -} - -void function_info::param_to_shared( memory_space *shared_mem, symbol_table *symtab ) -{ - // TODO: call this only for PTXPlus with GT200 models - extern gpgpu_sim* g_the_gpu; - if (not g_the_gpu->get_config().convert_to_ptxplus()) return; - - // copies parameters into simulated shared memory - for( std::map::iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { - param_info &p = i->second; - if (p.is_ptr_shared()) continue; // Pointer to local memory: Should we pass the allocated shared memory address to the param memory space? - std::string name = p.get_name(); - int type = p.get_type(); - param_t value = p.get_value(); - value.type = type; - symbol *param = symtab->lookup(name.c_str()); - unsigned xtype = param->type()->get_key().scalar_type(); - assert(xtype==(unsigned)type); - - int tmp; - size_t size; - unsigned offset = p.get_offset(); - type_info_key::type_decode(xtype,size,tmp); - - // Write to shared memory - offset + 0x10 - shared_mem->write(offset+0x10,size/8,value.pdata,NULL,NULL); - } -} - - -void function_info::list_param( FILE *fout ) const -{ - for( std::map::const_iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { - const param_info &p = i->second; - std::string name = p.get_name(); - symbol *param = m_symtab->lookup(name.c_str()); - addr_t param_addr = param->get_address(); - fprintf(fout, "%s: %#08x\n", name.c_str(), param_addr); - } - fflush(fout); -} - -template -bool ptx_debug_exec_dump_cond(int thd_uid, addr_t pc) -{ - if (g_debug_execution >= activate_level) { - // check each type of debug dump constraint to filter out dumps - if ( (g_debug_thread_uid != 0) && (thd_uid != (unsigned)g_debug_thread_uid) ) { - return false; - } - if ( (g_debug_pc != 0xBEEF1518) && (pc != g_debug_pc) ) { - return false; - } - - return true; - } - - return false; -} - -void init_inst_classification_stat() -{ - static std::set init; - if( init.find(g_ptx_kernel_count) != init.end() ) - return; - init.insert(g_ptx_kernel_count); - - #define MAX_CLASS_KER 1024 - char kernelname[MAX_CLASS_KER] =""; - if (!g_inst_classification_stat) g_inst_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); - snprintf(kernelname, MAX_CLASS_KER, "Kernel %d Classification\n",g_ptx_kernel_count ); - assert( g_ptx_kernel_count < MAX_CLASS_KER ) ; // a static limit on number of kernels increase it if it fails! - g_inst_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,20); - if (!g_inst_op_classification_stat) g_inst_op_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); - snprintf(kernelname, MAX_CLASS_KER, "Kernel %d OP Classification\n",g_ptx_kernel_count ); - g_inst_op_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,100); -} - -static unsigned get_tex_datasize( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &src1 = pI->src1(); //the name of the texture - std::string texname = src1.name(); - - gpgpu_t *gpu = thread->get_gpu(); - const struct textureReference* texref = gpu->get_texref(texname); - const struct textureInfo* texInfo = gpu->get_texinfo(texref); - - unsigned data_size = texInfo->texel_size; - return data_size; -} - -void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) -{ - - bool skip = false; - int op_classification = 0; - addr_t pc = next_instr(); - assert( pc == inst.pc ); // make sure timing model and functional model are in sync - const ptx_instruction *pI = m_func_info->get_instruction(pc); - set_npc( pc + pI->inst_size() ); - - - try { - - clearRPC(); - m_last_set_operand_value.u64 = 0; - - if(is_done()) - { - printf("attempted to execute instruction on a thread that is already done.\n"); - assert(0); - } - - if ( g_debug_execution >= 6 || m_gpu->get_config().get_ptx_inst_debug_to_file()) { - if ( (g_debug_thread_uid==0) || (get_uid() == (unsigned)g_debug_thread_uid) ) { - - clear_modifiedregs(); - enable_debug_trace(); - } - } - - - if( pI->has_pred() ) { - const operand_info &pred = pI->get_pred(); - ptx_reg_t pred_value = get_operand_value(pred, pred, PRED_TYPE, this, 0); - if(pI->get_pred_mod() == -1) { - skip = (pred_value.pred & 0x0001) ^ pI->get_pred_neg(); //ptxplus inverts the zero flag - } else { - skip = !pred_lookup(pI->get_pred_mod(), pred_value.pred & 0x000F); - } - } - - if( skip ) { - inst.set_not_active(lane_id); - } else { - const ptx_instruction *pI_saved = pI; - ptx_instruction *pJ = NULL; - if( pI->get_opcode() == VOTE_OP ) { - pJ = new ptx_instruction(*pI); - *((warp_inst_t*)pJ) = inst; // copy active mask information - pI = pJ; - } - switch ( pI->get_opcode() ) { -#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; -#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; -#include "opcodes.def" -#undef OP_DEF -#undef OP_W_DEF - default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break; - } - delete pJ; - pI = pI_saved; - - // Run exit instruction if exit option included - if(pI->is_exit()) - exit_impl(pI,this); - } - - - - const gpgpu_functional_sim_config &config = m_gpu->get_config(); - - // Output instruction information to file and stdout - if( config.get_ptx_inst_debug_to_file() != 0 && - (config.get_ptx_inst_debug_thread_uid() == 0 || config.get_ptx_inst_debug_thread_uid() == get_uid()) ) { - fprintf(m_gpu->get_ptx_inst_debug_file(), - "[thd=%u] : (%s:%u - %s)\n", - get_uid(), - pI->source_file(), pI->source_line(), pI->get_source() ); - //fprintf(ptx_inst_debug_file, "has memory read=%d, has memory write=%d\n", pI->has_memory_read(), pI->has_memory_write()); - fflush(m_gpu->get_ptx_inst_debug_file()); - } - - if ( ptx_debug_exec_dump_cond<5>(get_uid(), pc) ) { - dim3 ctaid = get_ctaid(); - dim3 tid = get_tid(); - printf("%u [thd=%u][i=%u] : ctaid=(%u,%u,%u) tid=(%u,%u,%u) icount=%u [pc=%u] (%s:%u - %s) [0x%llx]\n", - g_ptx_sim_num_insn, - get_uid(), - pI->uid(), ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z, - get_icount(), - pc, pI->source_file(), pI->source_line(), pI->get_source(), - m_last_set_operand_value.u64 ); - fflush(stdout); - } - - addr_t insn_memaddr = 0xFEEBDAED; - memory_space_t insn_space = undefined_space; - _memory_op_t insn_memory_op = no_memory_op; - unsigned insn_data_size = 0; - if ( (pI->has_memory_read() || pI->has_memory_write()) ) { - insn_memaddr = last_eaddr(); - insn_space = last_space(); - unsigned to_type = pI->get_type(); - insn_data_size = datatype2size(to_type); - insn_memory_op = pI->has_memory_read() ? memory_load : memory_store; - } - - if ( pI->get_opcode() == BAR_OP && pI->barrier_op() == RED_OPTION) { - inst.add_callback( lane_id, last_callback().function, last_callback().instruction, this,false /*not atomic*/); - } - - if ( pI->get_opcode() == ATOM_OP ) { - insn_memaddr = last_eaddr(); - insn_space = last_space(); - inst.add_callback( lane_id, last_callback().function, last_callback().instruction, this,true /*atomic*/); - unsigned to_type = pI->get_type(); - insn_data_size = datatype2size(to_type); - } - - if (pI->get_opcode() == TEX_OP) { - inst.set_addr(lane_id, last_eaddr() ); - assert( inst.space == last_space() ); - insn_data_size = get_tex_datasize(pI, this); // texture obtain its data granularity from the texture info - } - - // Output register information to file and stdout - if( config.get_ptx_inst_debug_to_file()!=0 && - (config.get_ptx_inst_debug_thread_uid()==0||config.get_ptx_inst_debug_thread_uid()==get_uid()) ) { - dump_modifiedregs(m_gpu->get_ptx_inst_debug_file()); - dump_regs(m_gpu->get_ptx_inst_debug_file()); - } - - if ( g_debug_execution >= 6 ) { - if ( ptx_debug_exec_dump_cond<6>(get_uid(), pc) ) - dump_modifiedregs(stdout); - } - if ( g_debug_execution >= 10 ) { - if ( ptx_debug_exec_dump_cond<10>(get_uid(), pc) ) - dump_regs(stdout); - } - update_pc(); - g_ptx_sim_num_insn++; - - //not using it with functional simulation mode - if(!(this->m_functionalSimulationMode)) - ptx_file_line_stats_add_exec_count(pI); - - if ( gpgpu_ptx_instruction_classification ) { - init_inst_classification_stat(); - unsigned space_type=0; - switch ( pI->get_space().get_type() ) { - case global_space: space_type = 10; break; - case local_space: space_type = 11; break; - case tex_space: space_type = 12; break; - case surf_space: space_type = 13; break; - case param_space_kernel: - case param_space_local: - space_type = 14; break; - case shared_space: space_type = 15; break; - case const_space: space_type = 16; break; - default: - space_type = 0 ; - break; - } - StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], op_classification); - if (space_type) StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], ( int )space_type); - StatAddSample( g_inst_op_classification_stat[g_ptx_kernel_count], (int) pI->get_opcode() ); - } - if ( (g_ptx_sim_num_insn % 100000) == 0 ) { - dim3 ctaid = get_ctaid(); - dim3 tid = get_tid(); - printf("GPGPU-Sim PTX: %u instructions simulated : ctaid=(%u,%u,%u) tid=(%u,%u,%u)\n", - g_ptx_sim_num_insn, ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z ); - fflush(stdout); - } - - // "Return values" - if(!skip) { - inst.space = insn_space; - inst.set_addr(lane_id, insn_memaddr); - inst.data_size = insn_data_size; // simpleAtomicIntrinsics - assert( inst.memory_op == insn_memory_op ); - } - - } catch ( int x ) { - printf("GPGPU-Sim PTX: ERROR (%d) executing intruction (%s:%u)\n", x, pI->source_file(), pI->source_line() ); - printf("GPGPU-Sim PTX: '%s'\n", pI->get_source() ); - abort(); - } - -} - -void set_param_gpgpu_num_shaders(int num_shaders) -{ - gpgpu_param_num_shaders = num_shaders; -} - -const struct gpgpu_ptx_sim_info* ptx_sim_kernel_info(const function_info *kernel) -{ - return kernel->get_kernel_info(); -} - -const warp_inst_t *ptx_fetch_inst( address_type pc ) -{ - return function_info::pc_to_instruction(pc); -} - -unsigned ptx_sim_init_thread( kernel_info_t &kernel, - ptx_thread_info** thread_info, - int sid, - unsigned tid, - unsigned threads_left, - unsigned num_threads, - core_t *core, - unsigned hw_cta_id, - unsigned hw_warp_id, - gpgpu_t *gpu, - bool isInFunctionalSimulationMode) -{ - std::list &active_threads = kernel.active_threads(); - - static std::map shared_memory_lookup; - static std::map ptx_cta_lookup; - static std::map ptx_warp_lookup; - static std::map > local_memory_lookup; - - if ( *thread_info != NULL ) { - ptx_thread_info *thd = *thread_info; - assert( thd->is_done() ); - if ( g_debug_execution==-1 ) { - dim3 ctaid = thd->get_ctaid(); - dim3 t = thd->get_tid(); - printf("GPGPU-Sim PTX simulator: thread exiting ctaid=(%u,%u,%u) tid=(%u,%u,%u) uid=%u\n", - ctaid.x,ctaid.y,ctaid.z,t.x,t.y,t.z, thd->get_uid() ); - fflush(stdout); - } - thd->m_cta_info->register_deleted_thread(thd); - delete thd; - *thread_info = NULL; - } - - if ( !active_threads.empty() ) { - assert( active_threads.size() <= threads_left ); - ptx_thread_info *thd = active_threads.front(); - active_threads.pop_front(); - *thread_info = thd; - thd->init(gpu, core, sid, hw_cta_id, hw_warp_id, tid, isInFunctionalSimulationMode ); - return 1; - } - - if ( kernel.no_more_ctas_to_run() ) { - return 0; //finished! - } - - if ( threads_left < kernel.threads_per_cta() ) { - return 0; - } - - if ( g_debug_execution==-1 ) { - printf("GPGPU-Sim PTX simulator: STARTING THREAD ALLOCATION --> \n"); - fflush(stdout); - } - - //initializing new CTA - ptx_cta_info *cta_info = NULL; - memory_space *shared_mem = NULL; - - unsigned cta_size = kernel.threads_per_cta(); - unsigned max_cta_per_sm = num_threads/cta_size; // e.g., 256 / 48 = 5 - assert( max_cta_per_sm > 0 ); - - //unsigned sm_idx = (tid/cta_size)*gpgpu_param_num_shaders + sid; - unsigned sm_idx = hw_cta_id*gpgpu_param_num_shaders + sid; - - if ( shared_memory_lookup.find(sm_idx) == shared_memory_lookup.end() ) { - if ( g_debug_execution >= 1 ) { - printf(" : sm_idx=%u sid=%u max_cta_per_sm=%u\n", - sm_idx, sid, max_cta_per_sm ); - } - char buf[512]; - snprintf(buf,512,"shared_%u", sid); - shared_mem = new memory_space_impl<16*1024>(buf,4); - shared_memory_lookup[sm_idx] = shared_mem; - cta_info = new ptx_cta_info(sm_idx); - ptx_cta_lookup[sm_idx] = cta_info; - } else { - if ( g_debug_execution >= 1 ) { - printf(" : sm_idx=%u sid=%u max_cta_per_sm=%u\n", - sm_idx, sid, max_cta_per_sm ); - } - shared_mem = shared_memory_lookup[sm_idx]; - cta_info = ptx_cta_lookup[sm_idx]; - cta_info->check_cta_thread_status_and_reset(); - } - - std::map &local_mem_lookup = local_memory_lookup[sid]; - while( kernel.more_threads_in_cta() ) { - dim3 ctaid3d = kernel.get_next_cta_id(); - unsigned new_tid = kernel.get_next_thread_id(); - dim3 tid3d = kernel.get_next_thread_id_3d(); - kernel.increment_thread_id(); - new_tid += tid; - ptx_thread_info *thd = new ptx_thread_info(kernel); - - ptx_warp_info *warp_info = NULL; - if ( ptx_warp_lookup.find(hw_warp_id) == ptx_warp_lookup.end() ) { - warp_info = new ptx_warp_info(); - ptx_warp_lookup[hw_warp_id] = warp_info; - } else { - warp_info = ptx_warp_lookup[hw_warp_id]; - } - thd->m_warp_info = warp_info; - - memory_space *local_mem = NULL; - std::map::iterator l = local_mem_lookup.find(new_tid); - if ( l != local_mem_lookup.end() ) { - local_mem = l->second; - } else { - char buf[512]; - snprintf(buf,512,"local_%u_%u", sid, new_tid); - local_mem = new memory_space_impl<32>(buf,32); - local_mem_lookup[new_tid] = local_mem; - } - thd->set_info(kernel.entry()); - thd->set_nctaid(kernel.get_grid_dim()); - thd->set_ntid(kernel.get_cta_dim()); - thd->set_ctaid(ctaid3d); - thd->set_tid(tid3d); - if( kernel.entry()->get_ptx_version().extensions() ) - thd->cpy_tid_to_reg(tid3d); - thd->set_valid(); - thd->m_shared_mem = shared_mem; - function_info *finfo = thd->func_info(); - symbol_table *st = finfo->get_symtab(); - thd->func_info()->param_to_shared(thd->m_shared_mem,st); - thd->m_cta_info = cta_info; - cta_info->add_thread(thd); - thd->m_local_mem = local_mem; - if ( g_debug_execution==-1 ) { - printf("GPGPU-Sim PTX simulator: allocating thread ctaid=(%u,%u,%u) tid=(%u,%u,%u) @ 0x%Lx\n", - ctaid3d.x,ctaid3d.y,ctaid3d.z,tid3d.x,tid3d.y,tid3d.z, (unsigned long long)thd ); - fflush(stdout); - } - active_threads.push_back(thd); - } - if ( g_debug_execution==-1 ) { - printf("GPGPU-Sim PTX simulator: <-- FINISHING THREAD ALLOCATION\n"); - fflush(stdout); - } - - kernel.increment_cta_id(); - - assert( active_threads.size() <= threads_left ); - *thread_info = active_threads.front(); - (*thread_info)->init(gpu, core, sid, hw_cta_id, hw_warp_id, tid,isInFunctionalSimulationMode ); - active_threads.pop_front(); - return 1; -} - -size_t get_kernel_code_size( class function_info *entry ) -{ - return entry->get_function_size(); -} - - -kernel_info_t *gpgpu_opencl_ptx_sim_init_grid(class function_info *entry, - gpgpu_ptx_sim_arg_list_t args, - struct dim3 gridDim, - struct dim3 blockDim, - gpgpu_t *gpu ) -{ - kernel_info_t *result = new kernel_info_t(gridDim,blockDim,entry); - unsigned argcount=args.size(); - unsigned argn=1; - for( gpgpu_ptx_sim_arg_list_t::iterator a = args.begin(); a != args.end(); a++ ) { - entry->add_param_data(argcount-argn,&(*a)); - argn++; - } - entry->finalize(result->get_param_memory()); - g_ptx_kernel_count++; - fflush(stdout); - - return result; -} - -#include "../../version" -#include "detailed_version" - -void print_splash() -{ - static int splash_printed=0; - if ( !splash_printed ) { - fprintf(stdout, "\n\n *** %s [build %s] ***\n\n\n", g_gpgpusim_version_string, g_gpgpusim_build_string ); - splash_printed=1; - } -} - -std::map g_const_name_lookup; // indexed by hostVar -std::map g_global_name_lookup; // indexed by hostVar -std::set g_globals; -std::set g_constants; - -void gpgpu_ptx_sim_register_const_variable(void *hostVar, const char *deviceName, size_t size ) -{ - printf("GPGPU-Sim PTX registering constant %s (%zu bytes) to name mapping\n", deviceName, size ); - g_const_name_lookup[hostVar] = deviceName; -} - -void gpgpu_ptx_sim_register_global_variable(void *hostVar, const char *deviceName, size_t size ) -{ - printf("GPGPU-Sim PTX registering global %s hostVar to name mapping\n", deviceName ); - g_global_name_lookup[hostVar] = deviceName; -} - -void gpgpu_ptx_sim_memcpy_symbol(const char *hostVar, const void *src, size_t count, size_t offset, int to, gpgpu_t *gpu ) -{ - printf("GPGPU-Sim PTX: starting gpgpu_ptx_sim_memcpy_symbol with hostVar 0x%p\n", hostVar); - bool found_sym = false; - memory_space_t mem_region = undefined_space; - std::string sym_name; - - std::map::iterator c=g_const_name_lookup.find(hostVar); - if ( c!=g_const_name_lookup.end() ) { - found_sym = true; - sym_name = c->second; - mem_region = const_space; - } - std::map::iterator g=g_global_name_lookup.find(hostVar); - if ( g!=g_global_name_lookup.end() ) { - if ( found_sym ) { - printf("Execution error: PTX symbol \"%s\" w/ hostVar=0x%Lx is declared both const and global?\n", - sym_name.c_str(), (unsigned long long)hostVar ); - abort(); - } - found_sym = true; - sym_name = g->second; - mem_region = global_space; - } - if( g_globals.find(hostVar) != g_globals.end() ) { - found_sym = true; - sym_name = hostVar; - mem_region = global_space; - } - if( g_constants.find(hostVar) != g_constants.end() ) { - found_sym = true; - sym_name = hostVar; - mem_region = const_space; - } - - if ( !found_sym ) { - printf("Execution error: No information for PTX symbol w/ hostVar=0x%Lx\n", (unsigned long long)hostVar ); - abort(); - } else printf("GPGPU-Sim PTX: gpgpu_ptx_sim_memcpy_symbol: Found PTX symbol w/ hostVar=0x%Lx\n", (unsigned long long)hostVar ); - const char *mem_name = NULL; - memory_space *mem = NULL; - - std::map::iterator st = g_sym_name_to_symbol_table.find(sym_name.c_str()); - assert( st != g_sym_name_to_symbol_table.end() ); - symbol_table *symtab = st->second; - - symbol *sym = symtab->lookup(sym_name.c_str()); - assert(sym); - unsigned dst = sym->get_address() + offset; - switch (mem_region.get_type()) { - case const_space: - mem = gpu->get_global_memory(); - mem_name = "const"; - break; - case global_space: - mem = gpu->get_global_memory(); - mem_name = "global"; - break; - default: - abort(); - } - printf("GPGPU-Sim PTX: gpgpu_ptx_sim_memcpy_symbol: copying %s memory %zu bytes %s symbol %s+%zu @0x%x ...\n", - mem_name, count, (to?" to ":"from"), sym_name.c_str(), offset, dst ); - for ( unsigned n=0; n < count; n++ ) { - if( to ) mem->write(dst+n,1,((char*)src)+n,NULL,NULL); - else mem->read(dst+n,1,((char*)src)+n); - } - fflush(stdout); -} - -int g_ptx_sim_mode; // if non-zero run functional simulation only (i.e., no notion of a clock cycle) - -extern int ptx_debug; - -bool g_cuda_launch_blocking = false; - -void read_sim_environment_variables() -{ - ptx_debug = 0; - g_debug_execution = 0; - g_interactive_debugger_enabled = false; - - char *mode = getenv("PTX_SIM_MODE_FUNC"); - if ( mode ) - sscanf(mode,"%u", &g_ptx_sim_mode); - printf("GPGPU-Sim PTX: simulation mode %d (can change with PTX_SIM_MODE_FUNC environment variable:\n", g_ptx_sim_mode); - printf(" 1=functional simulation only, 0=detailed performance simulator)\n"); - char *dbg_inter = getenv("GPGPUSIM_DEBUG"); - if ( dbg_inter && strlen(dbg_inter) ) { - printf("GPGPU-Sim PTX: enabling interactive debugger\n"); - fflush(stdout); - g_interactive_debugger_enabled = true; - } - char *dbg_level = getenv("PTX_SIM_DEBUG"); - if ( dbg_level && strlen(dbg_level) ) { - printf("GPGPU-Sim PTX: setting debug level to %s\n", dbg_level ); - fflush(stdout); - sscanf(dbg_level,"%d", &g_debug_execution); - } - char *dbg_thread = getenv("PTX_SIM_DEBUG_THREAD_UID"); - if ( dbg_thread && strlen(dbg_thread) ) { - printf("GPGPU-Sim PTX: printing debug information for thread uid %s\n", dbg_thread ); - fflush(stdout); - sscanf(dbg_thread,"%d", &g_debug_thread_uid); - } - char *dbg_pc = getenv("PTX_SIM_DEBUG_PC"); - if ( dbg_pc && strlen(dbg_pc) ) { - printf("GPGPU-Sim PTX: printing debug information for instruction with PC = %s\n", dbg_pc ); - fflush(stdout); - sscanf(dbg_pc,"%d", &g_debug_pc); - } - -#if CUDART_VERSION > 1010 - g_override_embedded_ptx = false; - char *usefile = getenv("PTX_SIM_USE_PTX_FILE"); - if (usefile && strlen(usefile)) { - printf("GPGPU-Sim PTX: overriding embedded ptx with ptx file (PTX_SIM_USE_PTX_FILE is set)\n"); - fflush(stdout); - g_override_embedded_ptx = true; - } - char *blocking = getenv("CUDA_LAUNCH_BLOCKING"); - if( blocking && !strcmp(blocking,"1") ) { - g_cuda_launch_blocking = true; - } -#else - g_cuda_launch_blocking = true; - g_override_embedded_ptx = true; -#endif - - if ( g_debug_execution >= 40 ) { - ptx_debug = 1; - } -} - -ptx_cta_info *g_func_cta_info = NULL; - -#define MAX(a,b) (((a)>(b))?(a):(b)) - -/*! -This function simulates the CUDA code functionally, it takes a kernel_info_t parameter -which holds the data for the CUDA kernel to be executed -!*/ -void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL ) -{ - printf("GPGPU-Sim: Performing Functional Simulation, executing kernel %s...\n",kernel.name().c_str()); - - //using a shader core object for book keeping, it is not needed but as most function built for performance simulation need it we use it here - extern gpgpu_sim *g_the_gpu; - //before we execute, we should do PDOM analysis for functional simulation scenario. - function_info *kernel_func_info = kernel.entry(); - if (kernel_func_info->is_pdom_set()) { - printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", kernel.name().c_str() ); - } else { - printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", kernel.name().c_str() ); - //kernel_func_info->do_pdom(); - kernel_func_info->set_pdom(); - } - - //we excute the kernel one CTA (Block) at the time, as synchronization functions work block wise - while(!kernel.no_more_ctas_to_run()){ - functionalCoreSim cta( - &kernel, - g_the_gpu, - g_the_gpu->getShaderCoreConfig()->warp_size - ); - cta.execute(); - -#if (CUDART_VERSION >= 5000) - launch_all_device_kernels(); -#endif - } - - //registering this kernel as done - - //openCL kernel simulation calls don't register the kernel so we don't register its exit - if(!openCL) { - extern stream_manager *g_stream_manager; - g_stream_manager->register_finished_kernel(kernel.get_uid()); - } - - //******PRINTING******* - printf( "GPGPU-Sim: Done functional simulation (%u instructions simulated).\n", g_ptx_sim_num_insn ); - if ( gpgpu_ptx_instruction_classification ) { - StatDisp( g_inst_classification_stat[g_ptx_kernel_count]); - StatDisp ( g_inst_op_classification_stat[g_ptx_kernel_count]); - } - - //time_t variables used to calculate the total simulation time - //the start time of simulation is hold by the global variable g_simulation_starttime - //g_simulation_starttime is initilized by gpgpu_ptx_sim_init_perf() in gpgpusim_entrypoint.cc upon starting gpgpu-sim - time_t end_time, elapsed_time, days, hrs, minutes, sec; - end_time = time((time_t *)NULL); - elapsed_time = MAX(end_time - g_simulation_starttime, 1); - - - //calculating and printing simulation time in terms of days, hours, minutes and seconds - days = elapsed_time/(3600*24); - hrs = elapsed_time/3600 - 24*days; - minutes = elapsed_time/60 - 60*(hrs + 24*days); - sec = elapsed_time - 60*(minutes + 60*(hrs + 24*days)); - - fflush(stderr); - printf("\n\ngpgpu_simulation_time = %u days, %u hrs, %u min, %u sec (%u sec)\n", - (unsigned)days, (unsigned)hrs, (unsigned)minutes, (unsigned)sec, (unsigned)elapsed_time ); - printf("gpgpu_simulation_rate = %u (inst/sec)\n", (unsigned)(g_ptx_sim_num_insn / elapsed_time) ); - fflush(stdout); -} - -void functionalCoreSim::initializeCTA() -{ - int ctaLiveThreads=0; - - for(int i=0; i< m_warp_count; i++){ - m_warpAtBarrier[i]=false; - m_liveThreadCount[i]=0; - } - for(int i=0; i< m_warp_count*m_warp_size;i++) - m_thread[i]=NULL; - - //get threads for a cta - for(unsigned i=0; ithreads_per_cta();i++) { - ptx_sim_init_thread(*m_kernel,&m_thread[i],0,i,m_kernel->threads_per_cta()-i,m_kernel->threads_per_cta(),this,0,i/m_warp_size,(gpgpu_t*)m_gpu, true); - assert(m_thread[i]!=NULL && !m_thread[i]->is_done()); - ctaLiveThreads++; - } - - for(int k=0;klaunch(m_thread[warpId*m_warp_size]->get_pc(),initialMask); - m_liveThreadCount[warpId]= liveThreadsCount; -} - -void functionalCoreSim::execute() - { - initializeCTA(); - - //start executing the CTA - while(true){ - bool someOneLive= false; - bool allAtBarrier = true; - for(unsigned i=0;i0) someOneLive=true; - if(!m_warpAtBarrier[i]&& m_liveThreadCount[i]>0) allAtBarrier = false; -} - -unsigned translate_pc_to_ptxlineno(unsigned pc) -{ - // this function assumes that the kernel fits inside a single PTX file - // function_info *pFunc = g_func_info; // assume that the current kernel is the one in query - const ptx_instruction *pInsn = function_info::pc_to_instruction(pc); - unsigned ptx_line_number = pInsn->source_line(); - - return ptx_line_number; -} - -// ptxinfo parser - -extern std::map get_duplicate(); - -int g_ptxinfo_error_detected; - -static char *g_ptxinfo_kname = NULL; -static struct gpgpu_ptx_sim_info g_ptxinfo; -static std::map g_duplicate; -static const char *g_last_dup_type; - -const char *get_ptxinfo_kname() -{ - return g_ptxinfo_kname; -} - -void print_ptxinfo() -{ - if(! get_ptxinfo_kname()){ - printf ("GPGPU-Sim PTX: Binary info : gmem=%u, cmem=%u\n", - g_ptxinfo.gmem, - g_ptxinfo.cmem); - } - if(get_ptxinfo_kname()){ - printf ("GPGPU-Sim PTX: Kernel \'%s\' : regs=%u, lmem=%u, smem=%u, cmem=%u\n", - get_ptxinfo_kname(), - g_ptxinfo.regs, - g_ptxinfo.lmem, - g_ptxinfo.smem, - g_ptxinfo.cmem ); - } -} - - -struct gpgpu_ptx_sim_info get_ptxinfo() -{ - return g_ptxinfo; -} - -std::map get_duplicate() -{ - return g_duplicate; -} - -void ptxinfo_linenum( unsigned linenum ) -{ - g_duplicate[linenum] = g_last_dup_type; -} - -void ptxinfo_dup_type( const char *dup_type ) -{ - g_last_dup_type = dup_type; -} - -void ptxinfo_function(const char *fname ) -{ - clear_ptxinfo(); - g_ptxinfo_kname = strdup(fname); -} - -void ptxinfo_regs( unsigned nregs ) -{ - g_ptxinfo.regs=nregs; -} - -void ptxinfo_lmem( unsigned declared, unsigned system ) -{ - g_ptxinfo.lmem=declared+system; -} - -void ptxinfo_gmem( unsigned declared, unsigned system ) -{ - g_ptxinfo.gmem=declared+system; -} - -void ptxinfo_smem( unsigned declared, unsigned system ) -{ - g_ptxinfo.smem=declared+system; -} - -void ptxinfo_cmem( unsigned nbytes, unsigned bank ) -{ - g_ptxinfo.cmem+=nbytes; -} - -void clear_ptxinfo() -{ - free(g_ptxinfo_kname); - g_ptxinfo_kname=NULL; - g_ptxinfo.regs=0; - g_ptxinfo.lmem=0; - g_ptxinfo.smem=0; - g_ptxinfo.cmem=0; - g_ptxinfo.gmem=0; - g_ptxinfo.ptx_version=0; - g_ptxinfo.sm_target=0; -} - - -void ptxinfo_opencl_addinfo( std::map &kernels ) -{ - - if(! g_ptxinfo_kname) { - printf ("GPGPU-Sim PTX: Binary info : gmem=%u, cmem=%u\n", - g_ptxinfo.gmem, - g_ptxinfo.cmem); - clear_ptxinfo(); - return; - } - - if( !strcmp("__cuda_dummy_entry__",g_ptxinfo_kname) ) { - // this string produced by ptxas for empty ptx files (e.g., bandwidth test) - clear_ptxinfo(); - return; - } - std::map::iterator k=kernels.find(g_ptxinfo_kname); - if( k==kernels.end() ) { - printf ("GPGPU-Sim PTX: ERROR ** implementation for '%s' not found.\n", g_ptxinfo_kname ); - abort(); - } else { - printf ("GPGPU-Sim PTX: Kernel \'%s\' : regs=%u, lmem=%u, smem=%u, cmem=%u\n", - g_ptxinfo_kname, - g_ptxinfo.regs, - g_ptxinfo.lmem, - g_ptxinfo.smem, - g_ptxinfo.cmem ); - function_info *finfo = k->second; - assert(finfo!=NULL); - finfo->set_kernel_info( g_ptxinfo ); - } - clear_ptxinfo(); -} - -struct rec_pts { - gpgpu_recon_t *s_kernel_recon_points; - int s_num_recon; -}; - -struct std::map g_rpts; - -struct rec_pts find_reconvergence_points( function_info *finfo ) -{ - rec_pts tmp; - std::map::iterator r=g_rpts.find(finfo); - - if( r==g_rpts.end() ) { - int num_recon = finfo->get_num_reconvergence_pairs(); - - gpgpu_recon_t *kernel_recon_points = (struct gpgpu_recon_t*) calloc(num_recon, sizeof(struct gpgpu_recon_t)); - finfo->get_reconvergence_pairs(kernel_recon_points); - printf("GPGPU-Sim PTX: reconvergence points for %s...\n", finfo->get_name().c_str() ); - for (int i=0;iprint_insn(); - printf("\n"); - printf("GPGPU-Sim PTX: immediate post dominator @ " ); - if( kernel_recon_points[i].target_inst ) - kernel_recon_points[i].target_inst->print_insn(); - printf("\n"); - } - printf("GPGPU-Sim PTX: ... end of reconvergence points for %s\n", finfo->get_name().c_str() ); - - tmp.s_kernel_recon_points = kernel_recon_points; - tmp.s_num_recon = num_recon; - g_rpts[finfo] = tmp; - } else { - tmp = r->second; - } - return tmp; -} - -address_type get_return_pc( void *thd ) -{ - // function call return - ptx_thread_info *the_thread = (ptx_thread_info*)thd; - assert( the_thread != NULL ); - return the_thread->get_return_PC(); -} - -address_type get_converge_point( address_type pc ) -{ - // the branch could encode the reconvergence point and/or a bit that indicates the - // reconvergence point is the return PC on the call stack in the case the branch has - // no immediate postdominator in the function (i.e., due to multiple return points). - - std::map::iterator f=g_pc_to_finfo.find(pc); - assert( f != g_pc_to_finfo.end() ); - function_info *finfo = f->second; - rec_pts tmp = find_reconvergence_points(finfo); - - int i=0; - for (; i < tmp.s_num_recon; ++i) { - if (tmp.s_kernel_recon_points[i].source_pc == pc) { - if( tmp.s_kernel_recon_points[i].target_pc == (unsigned) -2 ) { - return RECONVERGE_RETURN_PC; - } else { - return tmp.s_kernel_recon_points[i].target_pc; - } - } - } - return NO_BRANCH_DIVERGENCE; -} - -void functionalCoreSim::warp_exit( unsigned warp_id ) -{ - for(int i=0;im_cta_info->register_deleted_thread(m_thread[i]); - delete m_thread[i]; - } - } -} diff --git a/src/cuda-sim/instructions.cc~ b/src/cuda-sim/instructions.cc~ deleted file mode 100644 index 0e6f530..0000000 --- a/src/cuda-sim/instructions.cc~ +++ /dev/null @@ -1,4517 +0,0 @@ -// Copyright (c) 2009-2011, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda, -// Jimmy Kwa, George L. Yuan -// The University of British Columbia -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// Redistributions in binary form must reproduce the above copyright notice, this -// list of conditions and the following disclaimer in the documentation and/or -// other materials provided with the distribution. -// Neither the name of The University of British Columbia nor the names of its -// contributors may be used to endorse or promote products derived from this -// software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -#include "instructions.h" -#include "ptx_ir.h" -#include "opcodes.h" -#include "ptx_sim.h" -#include "ptx.tab.h" -#include -#include -#include -#include "cuda-math.h" -#include "../abstract_hardware_model.h" -#include "ptx_loader.h" -#include "cuda_device_printf.h" -#include "../gpgpu-sim/gpu-sim.h" -#include "../gpgpu-sim/shader.h" - -//Jin: include device runtime for CDP -#include "cuda_device_runtime.h" - -#include - -unsigned ptx_instruction::g_num_ptx_inst_uid=0; - -const char *g_opcode_string[NUM_OPCODES] = { -#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, -#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, -#include "opcodes.def" -#undef OP_DEF -#undef OP_W_DEF -}; - -void inst_not_implemented( const ptx_instruction * pI ) ; -ptx_reg_t srcOperandModifiers(ptx_reg_t opData, operand_info opInfo, operand_info dstInfo, unsigned type, ptx_thread_info *thread); - -void sign_extend( ptx_reg_t &data, unsigned src_size, const operand_info &dst ); - -void ptx_thread_info::set_reg( const symbol *reg, const ptx_reg_t &value ) -{ - assert( reg != NULL ); - if( reg->name() == "_" ) return; - assert( !m_regs.empty() ); - assert( reg->uid() > 0 ); - m_regs.back()[ reg ] = value; - if (m_enable_debug_trace ) - m_debug_trace_regs_modified.back()[ reg ] = value; - m_last_set_operand_value = value; -} - -ptx_reg_t ptx_thread_info::get_reg( const symbol *reg ) -{ - static bool unfound_register_warned = false; - assert( reg != NULL ); - assert( !m_regs.empty() ); - reg_map_t::iterator regs_iter = m_regs.back().find(reg); - if (regs_iter == m_regs.back().end()) { - assert( reg->type()->get_key().is_reg() ); - const std::string &name = reg->name(); - unsigned call_uid = m_callstack.back().m_call_uid; - ptx_reg_t uninit_reg; - uninit_reg.u32 = 0x0; - set_reg(reg, uninit_reg); // give it a value since we are going to warn the user anyway - std::string file_loc = get_location(); - if( !unfound_register_warned ) { - printf("GPGPU-Sim PTX: WARNING (%s) ** reading undefined register \'%s\' (cuid:%u). Setting to 0X00000000. This is okay if you are simulating the native ISA" - "\n", - file_loc.c_str(), name.c_str(), call_uid ); - unfound_register_warned = true; - } - regs_iter = m_regs.back().find(reg); - } - if (m_enable_debug_trace ) - m_debug_trace_regs_read.back()[ reg ] = regs_iter->second; - return regs_iter->second; -} - -ptx_reg_t ptx_thread_info::get_operand_value( const operand_info &op, operand_info dstInfo, unsigned opType, ptx_thread_info *thread, int derefFlag ) -{ - ptx_reg_t result, tmp; - - - if(op.get_double_operand_type() == 0) { - if(((opType != BB128_TYPE) && (opType != BB64_TYPE) && (opType != FF64_TYPE)) || (op.get_addr_space() != undefined_space)) { - if ( op.is_reg() ) { - result = get_reg( op.get_symbol() ); - } else if ( op.is_builtin()) { - result.u32 = get_builtin( op.get_int(), op.get_addr_offset() ); - } else if(op.is_immediate_address()){ - result.u64 = op.get_addr_offset(); - } else if ( op.is_memory_operand() ) { - // a few options here... - const symbol *sym = op.get_symbol(); - const type_info *type = sym->type(); - const type_info_key &info = type->get_key(); - - if ( info.is_reg() ) { - const symbol *name = op.get_symbol(); - result.u64 = get_reg(name).u64 + op.get_addr_offset(); - } else if ( info.is_param_kernel() ) { - result.u64 = sym->get_address() + op.get_addr_offset(); - } else if ( info.is_param_local() ) { - result.u64 = sym->get_address() + op.get_addr_offset(); - } else if ( info.is_global() ) { - assert( op.get_addr_offset() == 0 ); - result.u64 = sym->get_address(); - } else if ( info.is_local() ) { - result.u64 = sym->get_address() + op.get_addr_offset(); - } else if ( info.is_const() ) { - result.u64 = sym->get_address() + op.get_addr_offset(); - } else if ( op.is_shared() ) { - result.u64 = op.get_symbol()->get_address() + op.get_addr_offset(); - } else { - const char *name = op.name().c_str(); - printf("GPGPU-Sim PTX: ERROR ** get_operand_value : unknown memory operand type for %s\n", name ); - abort(); - } - - } else if ( op.is_literal() ) { - result = op.get_literal_value(); - } else if ( op.is_label() ) { - result.u64 = op.get_symbol()->get_address(); - } else if ( op.is_shared() ) { - result.u64 = op.get_symbol()->get_address(); - } else if ( op.is_const() ) { - result.u64 = op.get_symbol()->get_address(); - } else if ( op.is_global() ) { - result.u64 = op.get_symbol()->get_address(); - } else if ( op.is_local() ) { - result.u64 = op.get_symbol()->get_address(); - } else if ( op.is_function_address() ) { - result.u64 = (size_t)op.get_symbol()->get_pc(); - } else { - const char *name = op.name().c_str(); - printf("GPGPU-Sim PTX: ERROR ** get_operand_value : unknown operand type for %s\n", name ); - assert(0); - } - - if(op.get_operand_lohi() == 1) - result.u64 = result.u64 & 0xFFFF; - else if(op.get_operand_lohi() == 2) - result.u64 = (result.u64>>16) & 0xFFFF; - } else if (opType == BB128_TYPE) { - // b128 - result.u128.lowest = get_reg( op.vec_symbol(0) ).u32; - result.u128.low = get_reg( op.vec_symbol(1) ).u32; - result.u128.high = get_reg( op.vec_symbol(2) ).u32; - result.u128.highest = get_reg( op.vec_symbol(3) ).u32; - } else { - // bb64 or ff64 - result.bits.ls = get_reg( op.vec_symbol(0) ).u32; - result.bits.ms = get_reg( op.vec_symbol(1) ).u32; - } - } else if (op.get_double_operand_type() == 1) { - ptx_reg_t firstHalf, secondHalf; - firstHalf.u64 = get_reg( op.vec_symbol(0) ).u64; - secondHalf.u64 = get_reg( op.vec_symbol(1) ).u64; - if(op.get_operand_lohi() == 1) - secondHalf.u64 = secondHalf.u64 & 0xFFFF; - else if(op.get_operand_lohi() == 2) - secondHalf.u64 = (secondHalf.u64>>16) & 0xFFFF; - result.u64 = firstHalf.u64 + secondHalf.u64; - } else if (op.get_double_operand_type() == 2) { - // s[reg1 += reg2] - // reg1 is incremented after value is returned: the value returned is s[reg1] - ptx_reg_t firstHalf, secondHalf; - firstHalf.u64 = get_reg(op.vec_symbol(0)).u64; - secondHalf.u64 = get_reg(op.vec_symbol(1)).u64; - if(op.get_operand_lohi() == 1) - secondHalf.u64 = secondHalf.u64 & 0xFFFF; - else if(op.get_operand_lohi() == 2) - secondHalf.u64 = (secondHalf.u64>>16) & 0xFFFF; - result.u64 = firstHalf.u64; - firstHalf.u64 = firstHalf.u64 + secondHalf.u64; - set_reg(op.vec_symbol(0),firstHalf); - } else if (op.get_double_operand_type() == 3) { - // s[reg += immediate] - // reg is incremented after value is returned: the value returned is s[reg] - ptx_reg_t firstHalf; - firstHalf.u64 = get_reg(op.get_symbol()).u64; - result.u64 = firstHalf.u64; - firstHalf.u64 = firstHalf.u64 + op.get_addr_offset(); - set_reg(op.get_symbol(),firstHalf); - } - - ptx_reg_t finalResult; - memory_space *mem = NULL; - size_t size=0; - int t=0; - finalResult.u64=0; - - //complete other cases for reading from memory, such as reading from other const memory - if((op.get_addr_space() == global_space)&&(derefFlag)) { - // global memory - g[4], g[$r0] - mem = thread->get_global_memory(); - type_info_key::type_decode(opType,size,t); - mem->read(result.u32,size/8,&finalResult.u128); - thread->m_last_effective_address = result.u32; - thread->m_last_memory_space = global_space; - - if( opType == S16_TYPE || opType == S32_TYPE ) - sign_extend(finalResult,size,dstInfo); - } else if((op.get_addr_space() == shared_space)&&(derefFlag)) { - // shared memory - s[4], s[$r0] - mem = thread->m_shared_mem; - type_info_key::type_decode(opType,size,t); - mem->read(result.u32,size/8,&finalResult.u128); - thread->m_last_effective_address = result.u32; - thread->m_last_memory_space = shared_space; - - if( opType == S16_TYPE || opType == S32_TYPE ) - sign_extend(finalResult,size,dstInfo); - } else if((op.get_addr_space() == const_space)&&(derefFlag)) { - // const memory - ce0c1[4], ce0c1[$r0] - mem = thread->get_global_memory(); - type_info_key::type_decode(opType,size,t); - mem->read((result.u32 + op.get_const_mem_offset()),size/8,&finalResult.u128); - thread->m_last_effective_address = result.u32; - thread->m_last_memory_space = const_space; - if( opType == S16_TYPE || opType == S32_TYPE ) - sign_extend(finalResult,size,dstInfo); - } else if((op.get_addr_space() == local_space)&&(derefFlag)) { - // local memory - l0[4], l0[$r0] - mem = thread->m_local_mem; - type_info_key::type_decode(opType,size,t); - mem->read(result.u32,size/8,&finalResult.u128); - thread->m_last_effective_address = result.u32; - thread->m_last_memory_space = local_space; - if( opType == S16_TYPE || opType == S32_TYPE ) - sign_extend(finalResult,size,dstInfo); - } else { - finalResult = result; - } - - if((op.get_operand_neg() == true)&&(derefFlag)) { - switch( opType ) { - // Default to f32 for now, need to add support for others - case S8_TYPE: - case U8_TYPE: - case B8_TYPE: - finalResult.s8 = -finalResult.s8; - break; - case S16_TYPE: - case U16_TYPE: - case B16_TYPE: - finalResult.s16 = -finalResult.s16; - break; - case S32_TYPE: - case U32_TYPE: - case B32_TYPE: - finalResult.s32 = -finalResult.s32; - break; - case S64_TYPE: - case U64_TYPE: - case B64_TYPE: - finalResult.s64 = -finalResult.s64; - break; - case F16_TYPE: - finalResult.f16 = -finalResult.f16; - break; - case F32_TYPE: - finalResult.f32 = -finalResult.f32; - break; - case F64_TYPE: - case FF64_TYPE: - finalResult.f64 = -finalResult.f64; - break; - default: - assert(0); - } - - } - - return finalResult; - -} - -unsigned get_operand_nbits( const operand_info &op ) -{ - if ( op.is_reg() ) { - const symbol *sym = op.get_symbol(); - const type_info *typ = sym->type(); - type_info_key t = typ->get_key(); - switch( t.scalar_type() ) { - case PRED_TYPE: - return 1; - case B8_TYPE: case S8_TYPE: case U8_TYPE: - return 8; - case S16_TYPE: case U16_TYPE: case F16_TYPE: case B16_TYPE: - return 16; - case S32_TYPE: case U32_TYPE: case F32_TYPE: case B32_TYPE: - return 32; - case S64_TYPE: case U64_TYPE: case F64_TYPE: case B64_TYPE: - return 64; - default: - printf("ERROR: unknown register type\n"); - fflush(stdout); - abort(); - } - } else { - printf("ERROR: Need to implement get_operand_nbits() for currently unsupported operand_info type\n"); - fflush(stdout); - abort(); - } - - return 0; -} - -void ptx_thread_info::get_vector_operand_values( const operand_info &op, ptx_reg_t* ptx_regs, unsigned num_elements ) -{ - assert( op.is_vector() ); - assert( num_elements <= 4 ); // max 4 elements in a vector - - for (int idx = num_elements - 1; idx >= 0; --idx) { - const symbol *sym = NULL; - sym = op.vec_symbol(idx); - if( strcmp(sym->name().c_str(),"_") != 0) { - reg_map_t::iterator reg_iter = m_regs.back().find(sym); - assert( reg_iter != m_regs.back().end() ); - ptx_regs[idx] = reg_iter->second; - } - } -} - -void sign_extend( ptx_reg_t &data, unsigned src_size, const operand_info &dst ) -{ - if( !dst.is_reg() ) - return; - unsigned dst_size = get_operand_nbits( dst ); - if( src_size >= dst_size ) - return; - // src_size < dst_size - unsigned long long mask = 1; - mask <<= (src_size-1); - if( (mask & data.u64) == 0 ) { - // no need to sign extend - return; - } - // need to sign extend - mask = 1; - mask <<= dst_size-src_size; - mask -= 1; - mask <<= src_size; - data.u64 |= mask; -} - -void ptx_thread_info::set_operand_value( const operand_info &dst, const ptx_reg_t &data, unsigned type, ptx_thread_info *thread, const ptx_instruction *pI, int overflow, int carry ) -{ - thread->set_operand_value( dst, data, type, thread, pI ); - - if (dst.get_double_operand_type() == -2) - { - ptx_reg_t predValue; - - const symbol *sym = dst.vec_symbol(0); - predValue.u64 = (m_regs.back()[ sym ].u64) & ~(0x0C); - predValue.u64 |= ((overflow & 0x01)<<3); - predValue.u64 |= ((carry & 0x01)<<2); - - set_reg(sym,predValue); - } - else if (dst.get_double_operand_type() == 0) - { - //intentionally do nothing - } - else - { - printf("Unexpected double destination\n"); - assert(0); - } - -} - -void ptx_thread_info::set_operand_value( const operand_info &dst, const ptx_reg_t &data, unsigned type, ptx_thread_info *thread, const ptx_instruction *pI ) -{ - ptx_reg_t dstData; - memory_space *mem = NULL; - size_t size; - int t; - - type_info_key::type_decode(type,size,t); - - /*complete this section for other cases*/ - if(dst.get_addr_space() == undefined_space) - { - ptx_reg_t setValue; - setValue.u64 = data.u64; - - // Double destination in set instruction ($p0|$p1) - second is negation of first - if (dst.get_double_operand_type() == -1) - { - ptx_reg_t setValue2; - const symbol *name1 = dst.vec_symbol(0); - const symbol *name2 = dst.vec_symbol(1); - - if ( (type==F16_TYPE)||(type==F32_TYPE)||(type==F64_TYPE)||(type==FF64_TYPE) ) { - setValue2.f32 = (setValue.u64==0)?1.0f:0.0f; - } else { - setValue2.u32 = (setValue.u64==0)?0xFFFFFFFF:0; - } - - set_reg(name1,setValue); - set_reg(name2,setValue2); - } - - // Double destination in cvt,shr,mul,etc. instruction ($p0|$r4) - second register operand receives data, first predicate operand - // is set as $p0=($r4!=0) - // Also for Double destination in set instruction ($p0/$r1) - else if ((dst.get_double_operand_type() == -2)||(dst.get_double_operand_type() == -3)) - { - ptx_reg_t predValue; - const symbol *predName = dst.vec_symbol(0); - const symbol *regName = dst.vec_symbol(1); - predValue.u64 = 0; - - switch ( type ) { - case S8_TYPE: - if((setValue.s8 & 0x7F) == 0) - predValue.u64 |= 1; - break; - case S16_TYPE: - if((setValue.s16 & 0x7FFF) == 0) - predValue.u64 |= 1; - break; - case S32_TYPE: - if((setValue.s32 & 0x7FFFFFFF) == 0) - predValue.u64 |= 1; - break; - case S64_TYPE: - if((setValue.s64 & 0x7FFFFFFFFFFFFFFF) == 0) - predValue.u64 |= 1; - break; - case U8_TYPE: - case B8_TYPE: - if(setValue.u8 == 0) - predValue.u64 |= 1; - break; - case U16_TYPE: - case B16_TYPE: - if(setValue.u16 == 0) - predValue.u64 |= 1; - break; - case U32_TYPE: - case B32_TYPE: - if(setValue.u32 == 0) - predValue.u64 |= 1; - break; - case U64_TYPE: - case B64_TYPE: - if(setValue.u64 == 0) - predValue.u64 |= 1; - break; - case F16_TYPE: - if(setValue.f16 == 0) - predValue.u64 |= 1; - break; - case F32_TYPE: - if(setValue.f32 == 0) - predValue.u64 |= 1; - break; - case F64_TYPE: - case FF64_TYPE: - if(setValue.f64 == 0) - predValue.u64 |= 1; - break; - default: assert(0); break; - } - - - if ( (type==S8_TYPE)||(type==S16_TYPE)||(type==S32_TYPE)||(type==S64_TYPE)|| - (type==U8_TYPE)||(type==U16_TYPE)||(type==U32_TYPE)||(type==U64_TYPE)|| - (type==B8_TYPE)||(type==B16_TYPE)||(type==B32_TYPE)||(type==B64_TYPE)) { - if((setValue.u32 & (1<<(size-1))) != 0) - predValue.u64 |= 1<<1; - } - if ( type==F32_TYPE ) { - if(setValue.f32 < 0) - predValue.u64 |= 1<<1; - } - - if(dst.get_operand_lohi() == 1) - { - setValue.u64 = ((m_regs.back()[ regName ].u64) & (~(0xFFFF))) + (data.u64 & 0xFFFF); - } - else if(dst.get_operand_lohi() == 2) - { - setValue.u64 = ((m_regs.back()[ regName ].u64) & (~(0xFFFF0000))) + ((data.u64<<16) & 0xFFFF0000); - } - - set_reg(predName,predValue); - set_reg(regName,setValue); - } - else if (type == BB128_TYPE) - { - //b128 stuff here. - ptx_reg_t setValue2, setValue3, setValue4; - setValue.u64 = 0; - setValue2.u64 = 0; - setValue3.u64 = 0; - setValue4.u64 = 0; - setValue.u32 = data.u128.lowest; - setValue2.u32 = data.u128.low; - setValue3.u32 = data.u128.high; - setValue4.u32 = data.u128.highest; - - const symbol *name1, *name2, *name3, *name4 = NULL; - - name1 = dst.vec_symbol(0); - name2 = dst.vec_symbol(1); - name3 = dst.vec_symbol(2); - name4 = dst.vec_symbol(3); - - set_reg(name1,setValue); - set_reg(name2,setValue2); - set_reg(name3,setValue3); - set_reg(name4,setValue4); - } - else if (type == BB64_TYPE || type == FF64_TYPE) - { - //ptxplus version of storing 64 bit values to registers stores to two adjacent registers - ptx_reg_t setValue2; - setValue.u32 = 0; - setValue2.u32 = 0; - - setValue.u32 = data.bits.ls; - setValue2.u32 = data.bits.ms; - - const symbol *name1, *name2 = NULL; - - name1 = dst.vec_symbol(0); - name2 = dst.vec_symbol(1); - - set_reg(name1,setValue); - set_reg(name2,setValue2); - } - else - { - if(dst.get_operand_lohi() == 1) - { - setValue.u64 = ((m_regs.back()[ dst.get_symbol() ].u64) & (~(0xFFFF))) + (data.u64 & 0xFFFF); - } - else if(dst.get_operand_lohi() == 2) - { - setValue.u64 = ((m_regs.back()[ dst.get_symbol() ].u64) & (~(0xFFFF0000))) + ((data.u64<<16) & 0xFFFF0000); - } - set_reg(dst.get_symbol(),setValue); - } - } - - // global memory - g[4], g[$r0] - else if(dst.get_addr_space() == global_space) - { - dstData = thread->get_operand_value(dst, dst, type, thread, 0); - mem = thread->get_global_memory(); - type_info_key::type_decode(type,size,t); - - mem->write(dstData.u32,size/8,&data.u128,thread,pI); - thread->m_last_effective_address = dstData.u32; - thread->m_last_memory_space = global_space; - } - - // shared memory - s[4], s[$r0] - else if(dst.get_addr_space() == shared_space) - { - dstData = thread->get_operand_value(dst, dst, type, thread, 0); - mem = thread->m_shared_mem; - type_info_key::type_decode(type,size,t); - - mem->write(dstData.u32,size/8,&data.u128,thread,pI); - thread->m_last_effective_address = dstData.u32; - thread->m_last_memory_space = shared_space; - } - - // local memory - l0[4], l0[$r0] - else if(dst.get_addr_space() == local_space) - { - dstData = thread->get_operand_value(dst, dst, type, thread, 0); - mem = thread->m_local_mem; - type_info_key::type_decode(type,size,t); - - mem->write(dstData.u32,size/8,&data.u128,thread,pI); - thread->m_last_effective_address = dstData.u32; - thread->m_last_memory_space = local_space; - } - - else - { - printf("Destination stores to unknown location."); - assert(0); - } - - -} - -void ptx_thread_info::set_vector_operand_values( const operand_info &dst, - const ptx_reg_t &data1, - const ptx_reg_t &data2, - const ptx_reg_t &data3, - const ptx_reg_t &data4 ) -{ - unsigned num_elements = dst.get_vect_nelem(); - if (num_elements > 0) { - set_reg(dst.vec_symbol(0), data1); - if (num_elements > 1) { - set_reg(dst.vec_symbol(1), data2); - if (num_elements > 2) { - set_reg(dst.vec_symbol(2), data3); - if (num_elements > 3) { - set_reg(dst.vec_symbol(3), data4); - } - } - } - } - - m_last_set_operand_value = data1; -} - -#define my_abs(a) (((a)<0)?(-a):(a)) - -#define MY_MAX_I(a,b) (a > b) ? a : b -#define MY_MAX_F(a,b) isNaN(a) ? b : isNaN(b) ? a : (a > b) ? a : b - -#define MY_MIN_I(a,b) (a < b) ? a : b -#define MY_MIN_F(a,b) isNaN(a) ? b : isNaN(b) ? a : (a < b) ? a : b - -#define MY_INC_I(a,b) (a >= b) ? 0 : a+1 -#define MY_DEC_I(a,b) ((a == 0) || (a > b)) ? b : a-1 - -#define MY_CAS_I(a,b,c) (a == b) ? c : a - -#define MY_EXCH(a,b) b - -void abs_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case S16_TYPE: d.s16 = my_abs(a.s16); break; - case S32_TYPE: d.s32 = my_abs(a.s32); break; - case S64_TYPE: d.s64 = my_abs(a.s64); break; - case U16_TYPE: d.s16 = my_abs(a.u16); break; - case U32_TYPE: d.s32 = my_abs(a.u32); break; - case U64_TYPE: d.s64 = my_abs(a.u64); break; - case F32_TYPE: d.f32 = my_abs(a.f32); break; - case F64_TYPE: case FF64_TYPE: d.f64 = my_abs(a.f64); break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void addp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - //PTXPlus add instruction with carry (carry is kept in a predicate) register - ptx_reg_t src1_data, src2_data, src3_data, data; - int overflow = 0; - int carry = 0; - - const operand_info &dst = pI->dst(); //get operand info of sources and destination - const operand_info &src1 = pI->src1(); //use them to determine that they are of type 'register' - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - src3_data = thread->get_operand_value(src3, dst, i_type, thread, 1); - - unsigned rounding_mode = pI->rounding_mode(); - int orig_rm = fegetround(); - switch ( rounding_mode ) { - case RN_OPTION: break; - case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; - default: assert(0); break; - } - - //performs addition. Sets carry and overflow if needed. - //src3_data.pred&0x4 is the carry flag - switch ( i_type ) { - case S8_TYPE: - data.s64 = (src1_data.s64 & 0x0000000FF) + (src2_data.s64 & 0x0000000FF) + (src3_data.pred & 0x4); - if(((src1_data.s64 & 0x80)-(src2_data.s64 & 0x80)) == 0) {overflow=((src1_data.s64 & 0x80)-(data.s64 & 0x80))==0?0:1; } - carry = (data.u64 & 0x000000100)>>8; - break; - case S16_TYPE: - data.s64 = (src1_data.s64 & 0x00000FFFF) + (src2_data.s64 & 0x00000FFFF) + (src3_data.pred & 0x4); - if(((src1_data.s64 & 0x8000)-(src2_data.s64 & 0x8000)) == 0) {overflow=((src1_data.s64 & 0x8000)-(data.s64 & 0x8000))==0?0:1; } - carry = (data.u64 & 0x000010000)>>16; - break; - case S32_TYPE: - data.s64 = (src1_data.s64 & 0x0FFFFFFFF) + (src2_data.s64 & 0x0FFFFFFFF) + (src3_data.pred & 0x4); - if(((src1_data.s64 & 0x80000000)-(src2_data.s64 & 0x80000000)) == 0) {overflow=((src1_data.s64 & 0x80000000)-(data.s64 & 0x80000000))==0?0:1; } - carry = (data.u64 & 0x100000000)>>32; - break; - case S64_TYPE: - data.s64 = src1_data.s64 + src2_data.s64 + (src3_data.pred & 0x4); - break; - case U8_TYPE: - data.u64 = (src1_data.u64 & 0xFF) + (src2_data.u64 & 0xFF) + (src3_data.pred & 0x4); - carry = (data.u64 & 0x100)>>8; - break; - case U16_TYPE: - data.u64 = (src1_data.u64 & 0xFFFF) + (src2_data.u64 & 0xFFFF) + (src3_data.pred & 0x4); - carry = (data.u64 & 0x10000)>>16; - break; - case U32_TYPE: - data.u64 = (src1_data.u64 & 0xFFFFFFFF) + (src2_data.u64 & 0xFFFFFFFF) + (src3_data.pred & 0x4); - carry = (data.u64 & 0x100000000)>>32; - break; - case U64_TYPE: - data.s64 = src1_data.s64 + src2_data.s64 + (src3_data.pred & 0x4); - break; - case F16_TYPE: assert(0); break; - case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break; - case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break; - default: assert(0); break; - } - fesetround( orig_rm ); - - thread->set_operand_value(dst, data, i_type, thread, pI, overflow, carry ); -} - -void add_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - int overflow = 0; - int carry = 0; - - const operand_info &dst = pI->dst(); //get operand info of sources and destination - const operand_info &src1 = pI->src1(); //use them to determine that they are of type 'register' - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - unsigned rounding_mode = pI->rounding_mode(); - int orig_rm = fegetround(); - switch ( rounding_mode ) { - case RN_OPTION: break; - case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; - default: assert(0); break; - } - - //performs addition. Sets carry and overflow if needed. - switch ( i_type ) { - case S8_TYPE: - data.s64 = (src1_data.s64 & 0x0000000FF) + (src2_data.s64 & 0x0000000FF); - if(((src1_data.s64 & 0x80)-(src2_data.s64 & 0x80)) == 0) {overflow=((src1_data.s64 & 0x80)-(data.s64 & 0x80))==0?0:1; } - carry = (data.u64 & 0x000000100)>>8; - break; - case S16_TYPE: - data.s64 = (src1_data.s64 & 0x00000FFFF) + (src2_data.s64 & 0x00000FFFF); - if(((src1_data.s64 & 0x8000)-(src2_data.s64 & 0x8000)) == 0) {overflow=((src1_data.s64 & 0x8000)-(data.s64 & 0x8000))==0?0:1; } - carry = (data.u64 & 0x000010000)>>16; - break; - case S32_TYPE: - data.s64 = (src1_data.s64 & 0x0FFFFFFFF) + (src2_data.s64 & 0x0FFFFFFFF); - if(((src1_data.s64 & 0x80000000)-(src2_data.s64 & 0x80000000)) == 0) {overflow=((src1_data.s64 & 0x80000000)-(data.s64 & 0x80000000))==0?0:1; } - carry = (data.u64 & 0x100000000)>>32; - break; - case S64_TYPE: - data.s64 = src1_data.s64 + src2_data.s64; - break; - case U8_TYPE: - data.u64 = (src1_data.u64 & 0xFF) + (src2_data.u64 & 0xFF); - carry = (data.u64 & 0x100)>>8; - break; - case U16_TYPE: - data.u64 = (src1_data.u64 & 0xFFFF) + (src2_data.u64 & 0xFFFF); - carry = (data.u64 & 0x10000)>>16; - break; - case U32_TYPE: - data.u64 = (src1_data.u64 & 0xFFFFFFFF) + (src2_data.u64 & 0xFFFFFFFF); - carry = (data.u64 & 0x100000000)>>32; - break; - case U64_TYPE: - data.u64 = src1_data.u64 + src2_data.u64; - break; - case F16_TYPE: assert(0); break; - case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break; - case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break; - default: assert(0); break; - } - fesetround( orig_rm ); - - thread->set_operand_value(dst, data, i_type, thread, pI, overflow, carry ); -} - -void addc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } - -void and_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - //the way ptxplus handles predicates: 1 = false and 0 = true - if(i_type == PRED_TYPE) - data.pred = ~(~(src1_data.pred) & ~(src2_data.pred)); - else - data.u64 = src1_data.u64 & src2_data.u64; - - thread->set_operand_value(dst,data, i_type, thread, pI); -} - -void andn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - switch ( i_type ) { - case B16_TYPE: src2_data.u16 = ~src2_data.u16; break; - case B32_TYPE: src2_data.u32 = ~src2_data.u32; break; - case B64_TYPE: src2_data.u64 = ~src2_data.u64; break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - data.u64 = src1_data.u64 & src2_data.u64; - - thread->set_operand_value(dst,data, i_type, thread, pI); -} - -void bar_callback( const inst_t* inst, ptx_thread_info* thread) -{ - unsigned ctaid = thread->get_cta_uid(); - unsigned barid = inst->bar_id; - unsigned value = thread->get_reduction_value(ctaid,barid); - const ptx_instruction *pI = dynamic_cast(inst); - const operand_info &dst = pI->dst(); - ptx_reg_t data; - data.u32 = value; - thread->set_operand_value(dst,value, U32_TYPE, thread, pI); -} - -void atom_callback( const inst_t* inst, ptx_thread_info* thread) -{ - const ptx_instruction *pI = dynamic_cast(inst); - - // "Decode" the output type - unsigned to_type = pI->get_type(); - size_t size; - int t; - type_info_key::type_decode(to_type, size, t); - - // Set up operand variables - ptx_reg_t data; // d - ptx_reg_t src1_data; // a - ptx_reg_t src2_data; // b - ptx_reg_t op_result; // temp variable to hold operation result - - bool data_ready = false; - - // Get operand info of sources and destination - const operand_info &dst = pI->dst(); // d - const operand_info &src1 = pI->src1(); // a - const operand_info &src2 = pI->src2(); // b - - // Get operand values - src1_data = thread->get_operand_value(src1, src1, to_type, thread, 1); // a - if (dst.get_symbol()->type()){ - src2_data = thread->get_operand_value(src2, dst, to_type, thread, 1); // b - } else { - //This is the case whent he first argument (dest) is '_' - src2_data = thread->get_operand_value(src2, src1, to_type, thread, 1); // b - } - - // Check state space - addr_t effective_address = src1_data.u64; - memory_space_t space = pI->get_space(); - if (space == undefined_space) { - // generic space - determine space via address - if( whichspace(effective_address) == global_space ) { - effective_address = generic_to_global(effective_address); - space = global_space; - } else if( whichspace(effective_address) == shared_space ) { - unsigned smid = thread->get_hw_sid(); - effective_address = generic_to_shared(smid,effective_address); - space = shared_space; - } else { - abort(); - } - } - assert( space == global_space || space == shared_space ); - - memory_space *mem = NULL; - if(space == global_space) - mem = thread->get_global_memory(); - else if(space == shared_space) - mem = thread->m_shared_mem; - else - abort(); - - // Copy value pointed to in operand 'a' into register 'd' - // (i.e. copy src1_data to dst) - mem->read(effective_address,size/8,&data.s64); - if (dst.get_symbol()->type()){ - thread->set_operand_value(dst, data, to_type, thread, pI); // Write value into register 'd' - } - - // Get the atomic operation to be performed - unsigned m_atomic_spec = pI->get_atomic(); - - switch ( m_atomic_spec ) { - // AND - case ATOMIC_AND: - { - - switch ( to_type ) { - case B32_TYPE: - case U32_TYPE: - op_result.u32 = data.u32 & src2_data.u32; - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = data.s32 & src2_data.s32; - data_ready = true; - break; - default: - printf("Execution error: type mismatch (%x) with instruction\natom.AND only accepts b32\n", to_type); - assert(0); - break; - } - - break; - } - // OR - case ATOMIC_OR: - { - - switch ( to_type ) { - case B32_TYPE: - case U32_TYPE: - op_result.u32 = data.u32 | src2_data.u32; - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = data.s32 | src2_data.s32; - data_ready = true; - break; - default: - printf("Execution error: type mismatch (%x) with instruction\natom.OR only accepts b32\n", to_type); - assert(0); - break; - } - - break; - } - // XOR - case ATOMIC_XOR: - { - - switch ( to_type ) { - case B32_TYPE: - case U32_TYPE: - op_result.u32 = data.u32 ^ src2_data.u32; - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = data.s32 ^ src2_data.s32; - data_ready = true; - break; - default: - printf("Execution error: type mismatch (%x) with instruction\natom.XOR only accepts b32\n", to_type); - assert(0); - break; - } - - break; - } - // CAS - case ATOMIC_CAS: - { - - ptx_reg_t src3_data; - const operand_info &src3 = pI->src3(); - src3_data = thread->get_operand_value(src3, dst, to_type, thread, 1); - - switch ( to_type ) { - case B32_TYPE: - case U32_TYPE: - op_result.u32 = MY_CAS_I(data.u32, src2_data.u32, src3_data.u32); - data_ready = true; - break; - case B64_TYPE: - case U64_TYPE: - op_result.u64 = MY_CAS_I(data.u64, src2_data.u64, src3_data.u64); - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = MY_CAS_I(data.s32, src2_data.s32, src3_data.s32); - data_ready = true; - break; - default: - printf("Execution error: type mismatch (%x) with instruction\natom.CAS only accepts b32 and b64\n", to_type); - assert(0); - break; - } - - break; - } - // EXCH - case ATOMIC_EXCH: - { - switch ( to_type ) { - case B32_TYPE: - case U32_TYPE: - op_result.u32 = MY_EXCH(data.u32, src2_data.u32); - data_ready = true; - break; - case B64_TYPE: - case U64_TYPE: - op_result.u64 = MY_EXCH(data.u64, src2_data.u64); - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = MY_EXCH(data.s32, src2_data.s32); - data_ready = true; - break; - default: - printf("Execution error: type mismatch (%x) with instruction\natom.EXCH only accepts b32\n", to_type); - assert(0); - break; - } - - break; - } - // ADD - case ATOMIC_ADD: - { - - switch ( to_type ) { - case U32_TYPE: - op_result.u32 = data.u32 + src2_data.u32; - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = data.s32 + src2_data.s32; - data_ready = true; - break; - case U64_TYPE: - op_result.u64 = data.u64 + src2_data.u64; - data_ready = true; - break; - case F32_TYPE: - op_result.f32 = data.f32 + src2_data.f32; - data_ready = true; - break; - default: - printf("Execution error: type mismatch with instruction\natom.ADD only accepts u32, s32, u64, and f32\n"); - assert(0); - break; - } - - break; - } - // INC - case ATOMIC_INC: - { - switch ( to_type ) { - case U32_TYPE: - op_result.u32 = MY_INC_I(data.u32, src2_data.u32); - data_ready = true; - break; - default: - printf("Execution error: type mismatch with instruction\natom.INC only accepts u32 and s32\n"); - assert(0); - break; - } - - break; - } - // DEC - case ATOMIC_DEC: - { - switch ( to_type ) { - case U32_TYPE: - op_result.u32 = MY_DEC_I(data.u32, src2_data.u32); - data_ready = true; - break; - default: - printf("Execution error: type mismatch with instruction\natom.DEC only accepts u32 and s32\n"); - assert(0); - break; - } - - break; - } - // MIN - case ATOMIC_MIN: - { - switch ( to_type ) { - case U32_TYPE: - op_result.u32 = MY_MIN_I(data.u32, src2_data.u32); - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = MY_MIN_I(data.s32, src2_data.s32); - data_ready = true; - break; - default: - printf("Execution error: type mismatch with instruction\natom.MIN only accepts u32 and s32\n"); - assert(0); - break; - } - - break; - } - // MAX - case ATOMIC_MAX: - { - switch ( to_type ) { - case U32_TYPE: - op_result.u32 = MY_MAX_I(data.u32, src2_data.u32); - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = MY_MAX_I(data.s32, src2_data.s32); - data_ready = true; - break; - default: - printf("Execution error: type mismatch with instruction\natom.MAX only accepts u32 and s32\n"); - assert(0); - break; - } - - break; - } - // DEFAULT - default: - { - assert(0); - break; - } - } - - // Write operation result into memory - // (i.e. copy src1_data to dst) - if ( data_ready ) { - mem->write(effective_address,size/8,&op_result.s64,thread,pI); - } else { - printf("Execution error: data_ready not set\n"); - assert(0); - } -} - -// atom_impl will now result in a callback being called in mem_ctrl_pop (gpu-sim.c) -void atom_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - // SYNTAX - // atom.space.operation.type d, a, b[, c]; (now read in callback) - - // obtain memory space of the operation - memory_space_t space = pI->get_space(); - - // get the memory address - const operand_info &src1 = pI->src1(); - // const operand_info &dst = pI->dst(); // not needed for effective address calculation - unsigned i_type = pI->get_type(); - ptx_reg_t src1_data; - src1_data = thread->get_operand_value(src1, src1, i_type, thread, 1); - addr_t effective_address = src1_data.u64; - - addr_t effective_address_final; - - // handle generic memory space by converting it to global - if ( space == undefined_space ) { - if( whichspace(effective_address) == global_space ) { - effective_address_final = generic_to_global(effective_address); - space = global_space; - } else if( whichspace(effective_address) == shared_space ) { - unsigned smid = thread->get_hw_sid(); - effective_address_final = generic_to_shared(smid,effective_address); - space = shared_space; - } else { - abort(); - } - } else { - assert( space == global_space || space == shared_space ); - effective_address_final = effective_address; - } - - // Check state space - assert( space == global_space || space == shared_space ); - - thread->m_last_effective_address = effective_address_final; - thread->m_last_memory_space = space; - thread->m_last_dram_callback.function = atom_callback; - thread->m_last_dram_callback.instruction = pI; -} - -void bar_impl( const ptx_instruction *pIin, ptx_thread_info *thread ) -{ - ptx_instruction * pI = const_cast(pIin); - unsigned bar_op = pI->barrier_op(); - unsigned red_op = pI->get_atomic(); - unsigned ctaid = thread->get_cta_uid(); - - switch(bar_op){ - case SYNC_OPTION: - { - if(pI->get_num_operands()>1){ - const operand_info &op0 = pI->dst(); - const operand_info &op1 = pI->src1(); - ptx_reg_t op0_data; - ptx_reg_t op1_data; - op0_data = thread->get_operand_value(op0, op0, U32_TYPE, thread, 1); - op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); - pI->set_bar_id(op0_data.u32); - pI->set_bar_count(op1_data.u32); - }else{ - const operand_info &op0 = pI->dst(); - ptx_reg_t op0_data; - op0_data = thread->get_operand_value(op0, op0, U32_TYPE, thread, 1); - pI->set_bar_id(op0_data.u32); - } - break; - } - case ARRIVE_OPTION: - { - const operand_info &op0 = pI->dst(); - const operand_info &op1 = pI->src1(); - ptx_reg_t op0_data; - ptx_reg_t op1_data; - op0_data = thread->get_operand_value(op0, op0, U32_TYPE, thread, 1); - op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); - pI->set_bar_id(op0_data.u32); - pI->set_bar_count(op1_data.u32); - break; - } - case RED_OPTION: - { - if(pI->get_num_operands()>3){ - const operand_info &op1 = pI->src1(); - const operand_info &op2 = pI->src2(); - const operand_info &op3 = pI->src3(); - ptx_reg_t op1_data; - ptx_reg_t op2_data; - ptx_reg_t op3_data; - op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); - op2_data = thread->get_operand_value(op2, op2, U32_TYPE, thread, 1); - op3_data = thread->get_operand_value(op3, op3, PRED_TYPE, thread, 1); - op3_data.u32=!(op3_data.pred & 0x0001); - pI->set_bar_id(op1_data.u32); - pI->set_bar_count(op2_data.u32); - switch(red_op){ - case ATOMIC_POPC: - thread->popc_reduction(ctaid,op1_data.u32,op3_data.u32); - break; - case ATOMIC_AND: - thread->and_reduction(ctaid,op1_data.u32,op3_data.u32); - break; - case ATOMIC_OR: - thread->or_reduction(ctaid,op1_data.u32,op3_data.u32); - break; - default: - abort(); - break; - } - }else{ - const operand_info &op1 = pI->src1(); - const operand_info &op2 = pI->src2(); - ptx_reg_t op1_data; - ptx_reg_t op2_data; - op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); - op2_data = thread->get_operand_value(op2, op2, PRED_TYPE, thread, 1); - op2_data.u32=!(op2_data.pred & 0x0001); - pI->set_bar_id(op1_data.u32); - switch(red_op){ - case ATOMIC_POPC: - thread->popc_reduction(ctaid,op1_data.u32,op2_data.u32); - break; - case ATOMIC_AND: - thread->and_reduction(ctaid,op1_data.u32,op2_data.u32); - break; - case ATOMIC_OR: - thread->or_reduction(ctaid,op1_data.u32,op2_data.u32); - break; - default: - abort(); - break; - } - } - break; - } - default: - abort(); - break; - } - - thread->m_last_dram_callback.function = bar_callback; - thread->m_last_dram_callback.instruction = pIin; -} - -void bfe_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - unsigned i_type = pI->get_type(); - unsigned msb = (i_type == U32_TYPE || i_type == S32_TYPE) ? 31 : 63; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); - ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); - ptx_reg_t c = thread->get_operand_value(src3, dst, i_type, thread, 1); - unsigned pos = b.u32 & 0xFF; - unsigned len = c.u32 & 0xFF; - unsigned d = 0; - switch (i_type) - { - case U32_TYPE: - { - unsigned mask; - d = a.u32 >> pos; - mask = 0xFFFFFFFF >> (32 - len); - d &= mask; - break; - } - case U64_TYPE: - { - unsigned long mask; - d = a.u64 >> pos; - mask = 0xFFFFFFFFFFFFFFFF >> (64 - len); - d &= mask; - break; - } - case S32_TYPE: - { - unsigned mask; - unsigned min = MY_MIN_I(pos + len - 1, msb); - unsigned sbit = len == 0 ? 0 : (a.s32 >> min) & 0x1; - d = a.s32 >> pos; - if (sbit > 0) - { - mask = 0xFFFFFFFF << len; - d |= mask; - } - else - { - mask = 0xFFFFFFFF >> (32 - len); - d &= mask; - } - break; - } - case S64_TYPE: - { - unsigned long mask; - unsigned min = MY_MIN_I(pos + len - 1, msb); - unsigned sbit = len == 0 ? 0 : (a.s64 >> min) & 0x1; - d = a.s64 >> pos; - if (sbit > 0) - { - mask = 0xFFFFFFFFFFFFFFFF << len; - d |= mask; - } - else - { - mask = 0xFFFFFFFFFFFFFFFF >> (64 - len); - d &= mask; - } - break; - } - default: - printf("Operand type not supported for BFE instruction.\n"); - abort(); - return; - } - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void bfi_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void bfind_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } - -void bra_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &target = pI->dst(); - ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); - - thread->m_branch_taken = true; - thread->set_npc(target_pc); -} - -void brx_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &target = pI->dst(); - ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); - - thread->m_branch_taken = true; - thread->set_npc(target_pc); -} - -void break_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &target = thread->pop_breakaddr(); - ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); - - thread->m_branch_taken = true; - thread->set_npc(target_pc); -} - -void breakaddr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &target = pI->dst(); - thread->push_breakaddr(target); - assert(pI->has_pred() == false); // pdom analysis cannot handle if this instruction is predicated -} - -void brev_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } - -void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - static unsigned call_uid_next = 1; - - const operand_info &target = pI->func_addr(); - assert( target.is_function_address() ); - const symbol *func_addr = target.get_symbol(); - function_info *target_func = func_addr->get_pc(); - if (target_func->is_pdom_set()) { - printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", target_func->get_name().c_str() ); - } else { - printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", target_func->get_name().c_str() ); - if (target_func->get_function_size() >0) - target_func->do_pdom(); - target_func->set_pdom(); - } - - // check that number of args and return match function requirements - if( pI->has_return() ^ target_func->has_return() ) { - printf("GPGPU-Sim PTX: Execution error - mismatch in number of return values between\n" - " call instruction and function declaration\n"); - abort(); - } - unsigned n_return = target_func->has_return(); - unsigned n_args = target_func->num_args(); - unsigned n_operands = pI->get_num_operands(); - - if( n_operands != (n_return+1+n_args) ) { - printf("GPGPU-Sim PTX: Execution error - mismatch in number of arguements between\n" - " call instruction and function declaration\n"); - abort(); - } - - // handle intrinsic functions - std::string fname = target_func->get_name(); - if( fname == "vprintf" ) { - gpgpusim_cuda_vprintf(pI, thread, target_func); - return; - } - -#if (CUDART_VERSION >= 5000) - //Jin: handle device runtime apis for CDP - else if(fname == "cudaGetParameterBufferV2") { - gpgpusim_cuda_getParameterBufferV2(pI, thread, target_func); - return; - } - else if(fname == "cudaLaunchDeviceV2") { - gpgpusim_cuda_launchDeviceV2(pI, thread, target_func); - return; - } - else if(fname == "cudaStreamCreateWithFlags") { - gpgpusim_cuda_streamCreateWithFlags(pI, thread, target_func); - return; - } -#endif - - // read source arguements into register specified in declaration of function - arg_buffer_list_t arg_values; - copy_args_into_buffer_list(pI, thread, target_func, arg_values); - - // record local for return value (we only support a single return value) - const symbol *return_var_src = NULL; - const symbol *return_var_dst = NULL; - if( target_func->has_return() ) { - return_var_dst = pI->dst().get_symbol(); - return_var_src = target_func->get_return_var(); - } - - gpgpu_sim *gpu = thread->get_gpu(); - unsigned callee_pc=0, callee_rpc=0; - if( gpu->simd_model() == POST_DOMINATOR ) { - thread->get_core()->get_pdom_stack_top_info(thread->get_hw_wid(),&callee_pc,&callee_rpc); - assert( callee_pc == thread->get_pc() ); - } - - thread->callstack_push(callee_pc + pI->inst_size(), callee_rpc, return_var_src, return_var_dst, call_uid_next++); - - copy_buffer_list_into_frame(thread, arg_values); - - thread->set_npc(target_func); -} - -//Ptxplus version of call instruction. Jumps to a label not a different Kernel. -void callp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - - static unsigned call_uid_next = 1; - - const operand_info &target = pI->dst(); - ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); - - const symbol *return_var_src = NULL; - const symbol *return_var_dst = NULL; - - gpgpu_sim *gpu = thread->get_gpu(); - unsigned callee_pc=0, callee_rpc=0; - if( gpu->simd_model() == POST_DOMINATOR ) { - thread->get_core()->get_pdom_stack_top_info(thread->get_hw_wid(),&callee_pc,&callee_rpc); - assert( callee_pc == thread->get_pc() ); - } - - thread->callstack_push_plus(callee_pc + pI->inst_size(), callee_rpc, return_var_src, return_var_dst, call_uid_next++); - thread->set_npc(target_pc); -} - -void clz_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - int max; - unsigned long long mask; - d.u64 = 0; - - switch ( i_type ) { - case B32_TYPE: - max = 32; - mask = 0x80000000; - break; - case B64_TYPE: - max = 64; - mask = 0x8000000000000000; - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - while ((d.u32 < max) && ((a.u64&mask) == 0) ) { - d.u32++; - a.u64 = a.u64 << 1; - } - - thread->set_operand_value(dst,d, B32_TYPE, thread, pI); -} - -void cnot_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - switch ( i_type ) { - case PRED_TYPE: d.pred = ((a.pred & 0x0001) == 0)?1:0; break; - case B16_TYPE: d.u16 = (a.u16 == 0)?1:0; break; - case B32_TYPE: d.u32 = (a.u32 == 0)?1:0; break; - case B64_TYPE: d.u64 = (a.u64 == 0)?1:0; break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void cos_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case F32_TYPE: - d.f32 = cos(a.f32); - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -ptx_reg_t chop( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - switch ( to_width ) { - case 8: x.mask_and(0,0xFF); break; - case 16: x.mask_and(0,0xFFFF); break; - case 32: x.mask_and(0,0xFFFFFFFF); break; - case 64: break; - default: assert(0); - } - return x; -} - -ptx_reg_t sext( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - x=chop(x,0,from_width,0,rounding_mode,saturation_mode); - switch ( from_width ) { - case 8: if ( x.get_bit(7) ) x.mask_or(0xFFFFFFFF,0xFFFFFF00);break; - case 16:if ( x.get_bit(15) ) x.mask_or(0xFFFFFFFF,0xFFFF0000);break; - case 32: if ( x.get_bit(31) ) x.mask_or(0xFFFFFFFF,0x00000000);break; - case 64: break; - default: assert(0); - } - return x; -} - -// sign extend depending on the destination register size - hack to get SobelFilter working in CUDA 4.2 -ptx_reg_t sexd( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - x=chop(x,0,from_width,0,rounding_mode,saturation_mode); - switch ( to_width ) { - case 8: if ( x.get_bit(7) ) x.mask_or(0xFFFFFFFF,0xFFFFFF00);break; - case 16:if ( x.get_bit(15) ) x.mask_or(0xFFFFFFFF,0xFFFF0000);break; - case 32: if ( x.get_bit(31) ) x.mask_or(0xFFFFFFFF,0x00000000);break; - case 64: break; - default: assert(0); - } - return x; -} - -ptx_reg_t zext( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - return chop(x,0,from_width,0,rounding_mode,saturation_mode); -} - -int saturatei(int a, int max, int min) -{ - if (a > max) a = max; - else if (a < min) a = min; - return a; -} - -unsigned int saturatei(unsigned int a, unsigned int max) -{ - if (a > max) a = max; - return a; -} - -ptx_reg_t f2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - assert( from_width == 32); - - enum cuda_math::cudaRoundMode mode = cuda_math::cudaRoundZero; - switch (rounding_mode) { - case RZI_OPTION: mode = cuda_math::cudaRoundZero; break; - case RNI_OPTION: mode = cuda_math::cudaRoundNearest; break; - case RMI_OPTION: mode = cuda_math::cudaRoundMinInf; break; - case RPI_OPTION: mode = cuda_math::cudaRoundPosInf; break; - default: break; - } - - ptx_reg_t y; - if ( to_sign == 1 ) { // convert to 64-bit number first? - int tmp = cuda_math::float2int(x.f32, mode); - if ((x.u32 & 0x7f800000) == 0) - tmp = 0; // round denorm. FP to 0 - if (saturation_mode && to_width < 32) { - tmp = saturatei(tmp, (1< max) a = max; - else if (a < min) a = min; - return a; -} - -ptx_reg_t d2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - assert( from_width == 64); - - double tmp; - switch (rounding_mode) { - case RZI_OPTION: tmp = trunc(x.f64); break; - case RNI_OPTION: tmp = nearbyint(x.f64); break; - case RMI_OPTION: tmp = floor(x.f64); break; - case RPI_OPTION: tmp = ceil(x.f64); break; - default: tmp = x.f64; break; - } - - ptx_reg_t y; - if ( to_sign == 1 ) { - tmp = saturated2i(tmp, ((1<<(to_width - 1)) - 1), (1<<(to_width - 1)) ); - switch ( to_width ) { - case 8: y.s8 = (char)tmp; break; - case 16: y.s16 = (short)tmp; break; - case 32: y.s32 = (int)tmp; break; - case 64: y.s64 = (long long)tmp; break; - default: assert(0); break; - } - } else if ( to_sign == 0 ) { - tmp = saturated2i(tmp, ((1<<(to_width - 1)) - 1), 0); - switch ( to_width ) { - case 8: y.u8 = (unsigned char)tmp; break; - case 16: y.u16 = (unsigned short)tmp; break; - case 32: y.u32 = (unsigned int)tmp; break; - case 64: y.u64 = (unsigned long long)tmp; break; - default: assert(0); break; - } - } else { - switch ( to_width ) { - case 16: assert(0); break; - case 32: - y.f32 = x.f64; - break; - case 64: - y.f64 = x.f64; // should be handled by d2d - break; - default: assert(0); break; - } - } - return y; -} - -ptx_reg_t s2f( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - ptx_reg_t y; - - if (from_width < 64) { // 32-bit conversion - y = sext(x,from_width,32,0,rounding_mode,saturation_mode); - - switch ( to_width ) { - case 16: assert(0); break; - case 32: - switch (rounding_mode) { - case RZ_OPTION: y.f32 = cuda_math::__int2float_rz(y.s32); break; - case RN_OPTION: y.f32 = cuda_math::__int2float_rn(y.s32); break; - case RM_OPTION: y.f32 = cuda_math::__int2float_rd(y.s32); break; - case RP_OPTION: y.f32 = cuda_math::__int2float_ru(y.s32); break; - default: break; - } - break; - case 64: y.f64 = y.s32; break; // no rounding needed - default: assert(0); break; - } - } else { - switch ( to_width ) { - case 16: assert(0); break; - case 32: - switch (rounding_mode) { - case RZ_OPTION: y.f32 = cuda_math::__ll2float_rz(y.s64); break; - case RN_OPTION: y.f32 = cuda_math::__ll2float_rn(y.s64); break; - case RM_OPTION: y.f32 = cuda_math::__ll2float_rd(y.s64); break; - case RP_OPTION: y.f32 = cuda_math::__ll2float_ru(y.s64); break; - default: break; - } - break; - case 64: y.f64 = y.s64; break; // no internal implementation found - default: assert(0); break; - } - } - - // saturating an integer to 1 or 0? - return y; -} - -ptx_reg_t u2f( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - ptx_reg_t y; - - if (from_width < 64) { // 32-bit conversion - y = zext(x,from_width,32,0,rounding_mode,saturation_mode); - - switch ( to_width ) { - case 16: assert(0); break; - case 32: - switch (rounding_mode) { - case RZ_OPTION: y.f32 = cuda_math::__uint2float_rz(y.u32); break; - case RN_OPTION: y.f32 = cuda_math::__uint2float_rn(y.u32); break; - case RM_OPTION: y.f32 = cuda_math::__uint2float_rd(y.u32); break; - case RP_OPTION: y.f32 = cuda_math::__uint2float_ru(y.u32); break; - default: break; - } - break; - case 64: y.f64 = y.u32; break; // no rounding needed - default: assert(0); break; - } - } else { - switch ( to_width ) { - case 16: assert(0); break; - case 32: - switch (rounding_mode) { - case RZ_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; - case RN_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; - case RM_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; - case RP_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; - default: break; - } - break; - case 64: y.f64 = y.u64; break; // no internal implementation found - default: assert(0); break; - } - } - - // saturating an integer to 1 or 0? - return y; -} - -ptx_reg_t f2f( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - ptx_reg_t y; - switch ( rounding_mode ) { - case RZI_OPTION: - y.f32 = truncf(x.f32); - break; - case RNI_OPTION: -#if CUDART_VERSION >= 3000 - y.f32 = nearbyintf(x.f32); -#else - y.f32 = cuda_math::__internal_nearbyintf(x.f32); -#endif - break; - case RMI_OPTION: - if ((x.u32 & 0x7f800000) == 0) { - y.u32 = x.u32 & 0x80000000; // round denorm. FP to 0, keeping sign - } else { - y.f32 = floorf(x.f32); - } - break; - case RPI_OPTION: - if ((x.u32 & 0x7f800000) == 0) { - y.u32 = x.u32 & 0x80000000; // round denorm. FP to 0, keeping sign - } else { - y.f32 = ceilf(x.f32); - } - break; - default: - if ((x.u32 & 0x7f800000) == 0) { - y.u32 = x.u32 & 0x80000000; // round denorm. FP to 0, keeping sign - } else { - y.f32 = x.f32; - } - break; - } -#if CUDART_VERSION >= 3000 - if (isnanf(y.f32)) -#else - if (cuda_math::__cuda___isnanf(y.f32)) -#endif - { - y.u32 = 0x7fffffff; - } else if (saturation_mode) { - y.f32 = cuda_math::__saturatef(y.f32); - } - - return y; -} - -ptx_reg_t d2d( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - ptx_reg_t y; - switch ( rounding_mode ) { - case RZI_OPTION: - y.f64 = trunc(x.f64); - break; - case RNI_OPTION: -#if CUDART_VERSION >= 3000 - y.f64 = nearbyint(x.f64); -#else - y.f64 = cuda_math::__internal_nearbyintf(x.f64); -#endif - break; - case RMI_OPTION: - y.f64 = floor(x.f64); - break; - case RPI_OPTION: - y.f64 = ceil(x.f64); - break; - default: - y.f64 = x.f64; - break; - } - if (std::isnan(y.f64)) { - y.u64 = 0xfff8000000000000ull; - } else if (saturation_mode) { - y.f64 = cuda_math::__saturatef(y.f64); - } - return y; -} - -ptx_reg_t (*g_cvt_fn[11][11])( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, - int rounding_mode, int saturation_mode ) = { - { NULL, sext, sext, sext, NULL, sext, sext, sext, s2f, s2f, s2f}, - { chop, NULL, sext, sext, chop, NULL, sext, sext, s2f, s2f, s2f}, - { chop, sexd, NULL, sext, chop, chop, NULL, sext, s2f, s2f, s2f}, - { chop, chop, chop, NULL, chop, chop, chop, NULL, s2f, s2f, s2f}, - { NULL, zext, zext, zext, NULL, zext, zext, zext, u2f, u2f, u2f}, - { chop, NULL, zext, zext, chop, NULL, zext, zext, u2f, u2f, u2f}, - { chop, chop, NULL, zext, chop, chop, NULL, zext, u2f, u2f, u2f}, - { chop, chop, chop, NULL, chop, chop, chop, NULL, u2f, u2f, u2f}, - { f2x , f2x , f2x , f2x , f2x , f2x , f2x , f2x , NULL,f2x, f2x}, - { f2x , f2x , f2x , f2x , f2x , f2x , f2x , f2x , f2x, f2f, f2x}, - { d2x , d2x , d2x , d2x , d2x , d2x , d2x , d2x , d2x, d2x, d2d} -}; - -void ptx_round(ptx_reg_t& data, int rounding_mode, int type) -{ - if (rounding_mode == RN_OPTION) { - return; - } - switch ( rounding_mode ) { - case RZI_OPTION: - switch ( type ) { - case S8_TYPE: - case S16_TYPE: - case S32_TYPE: - case S64_TYPE: - case U8_TYPE: - case U16_TYPE: - case U32_TYPE: - case U64_TYPE: - printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; - case F32_TYPE: - data.f32 = truncf(data.f32); - break; - case F64_TYPE: - case FF64_TYPE: - if (data.f64 < 0) data.f64 = ceil(data.f64); //negative - else data.f64 = floor(data.f64); //positive - break; - default: assert(0); break; - } - break; - case RNI_OPTION: - switch ( type ) { - case S8_TYPE: - case S16_TYPE: - case S32_TYPE: - case S64_TYPE: - case U8_TYPE: - case U16_TYPE: - case U32_TYPE: - case U64_TYPE: - printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; - case F32_TYPE: -#if CUDART_VERSION >= 3000 - data.f32 = nearbyintf(data.f32); -#else - data.f32 = cuda_math::__cuda_nearbyintf(data.f32); -#endif - break; - case F64_TYPE: case FF64_TYPE: data.f64 = round(data.f64); break; - default: assert(0); break; - } - break; - case RMI_OPTION: - switch ( type ) { - case S8_TYPE: - case S16_TYPE: - case S32_TYPE: - case S64_TYPE: - case U8_TYPE: - case U16_TYPE: - case U32_TYPE: - case U64_TYPE: - printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; - case F32_TYPE: - data.f32 = floorf(data.f32); - break; - case F64_TYPE: case FF64_TYPE: data.f64 = floor(data.f64); break; - default: assert(0); break; - } - break; - case RPI_OPTION: - switch ( type ) { - case S8_TYPE: - case S16_TYPE: - case S32_TYPE: - case S64_TYPE: - case U8_TYPE: - case U16_TYPE: - case U32_TYPE: - case U64_TYPE: - printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; - case F32_TYPE: data.f32 = ceilf(data.f32); break; - case F64_TYPE: case FF64_TYPE: data.f64 = ceil(data.f64); break; - default: assert(0); break; - } - break; - default: break; - } - - if (type == F32_TYPE) { -#if CUDART_VERSION >= 3000 - if (isnanf(data.f32)) -#else - if (cuda_math::__cuda___isnanf(data.f32)) -#endif - { - data.u32 = 0x7fffffff; - } - } - if ((type == F64_TYPE)||(type == FF64_TYPE)) { - if (std::isnan(data.f64)) { - data.u64 = 0xfff8000000000000ull; - } - } -} - -void ptx_saturate(ptx_reg_t& data, int saturation_mode, int type) -{ - if (!saturation_mode) { - return; - } - switch ( type ) { - case S8_TYPE: - case S16_TYPE: - case S32_TYPE: - case S64_TYPE: - case U8_TYPE: - case U16_TYPE: - case U32_TYPE: - case U64_TYPE: - printf("Trying to clamp an integer to 1??\n"); assert(0); break; - case F16_TYPE: assert(0); break; - case F32_TYPE: - if (data.f32 > 1.0f) data.f32 = 1.0f; //negative - if (data.f32 < 0.0f) data.f32 = 0.0f; //positive - break; - case F64_TYPE: - case FF64_TYPE: - if (data.f64 > 1.0f) data.f64 = 1.0f; //negative - if (data.f64 < 0.0f) data.f64 = 0.0f; //positive - break; - default: assert(0); break; - } - -} - -void cvt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - unsigned to_type = pI->get_type(); - unsigned from_type = pI->get_type2(); - unsigned rounding_mode = pI->rounding_mode(); - unsigned saturation_mode = pI->saturation_mode(); - - if ( to_type == F16_TYPE || from_type == F16_TYPE ) - abort(); - - int to_sign, from_sign; - size_t from_width, to_width; - unsigned src_fmt = type_info_key::type_decode(from_type, from_width, from_sign); - unsigned dst_fmt = type_info_key::type_decode(to_type, to_width, to_sign); - - ptx_reg_t data = thread->get_operand_value(src1, dst, from_type, thread, 1); - - if(pI->is_neg()){ - - switch( from_type ) { - // Default to f32 for now, need to add support for others - case S8_TYPE: - case U8_TYPE: - case B8_TYPE: - data.s8 = -data.s8; - break; - case S16_TYPE: - case U16_TYPE: - case B16_TYPE: - data.s16 = -data.s16; - break; - case S32_TYPE: - case U32_TYPE: - case B32_TYPE: - data.s32 = -data.s32; - break; - case S64_TYPE: - case U64_TYPE: - case B64_TYPE: - data.s64 = -data.s64; - break; - case F16_TYPE: - data.f16 = -data.f16; - break; - case F32_TYPE: - data.f32 = -data.f32; - break; - case F64_TYPE: - case FF64_TYPE: - data.f64 = -data.f64; - break; - default: - assert(0); - } - - } - - - if ( g_cvt_fn[src_fmt][dst_fmt] != NULL ) { - ptx_reg_t result = g_cvt_fn[src_fmt][dst_fmt](data,from_width,to_width,to_sign, rounding_mode, saturation_mode); - data = result; - } - - thread->set_operand_value(dst, data, to_type, thread, pI ); -} - -void cvta_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - memory_space_t space = pI->get_space(); - bool to_non_generic = pI->is_to(); - - unsigned i_type = pI->get_type(); - ptx_reg_t from_addr = thread->get_operand_value(src1,dst,i_type,thread,1); - addr_t from_addr_hw = (addr_t)from_addr.u64; - addr_t to_addr_hw = 0; - unsigned smid = thread->get_hw_sid(); - unsigned hwtid = thread->get_hw_tid(); - - if( to_non_generic ) { - switch( space.get_type() ) { - case shared_space: to_addr_hw = generic_to_shared( smid, from_addr_hw ); break; - case local_space: to_addr_hw = generic_to_local( smid, hwtid, from_addr_hw ); break; - case global_space: to_addr_hw = generic_to_global(from_addr_hw ); break; - default: abort(); - } - } else { - switch( space.get_type() ) { - case shared_space: to_addr_hw = shared_to_generic( smid, from_addr_hw ); break; - case local_space: to_addr_hw = local_to_generic( smid, hwtid, from_addr_hw ) - + thread->get_local_mem_stack_pointer(); break; // add stack ptr here so that it can be passed as a pointer at function call - case global_space: to_addr_hw = global_to_generic( from_addr_hw ); break; - default: abort(); - } - } - - ptx_reg_t to_addr; - to_addr.u64 = to_addr_hw; - thread->set_reg(dst.get_symbol(),to_addr); -} - -void div_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - - ptx_reg_t src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - ptx_reg_t src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - switch ( i_type ) { - case S8_TYPE: - data.s8 = src1_data.s8 / src2_data.s8 ; break; - case S16_TYPE: - data.s16 = src1_data.s16 / src2_data.s16; break; - case S32_TYPE: - data.s32 = src1_data.s32 / src2_data.s32; break; - case S64_TYPE: - data.s64 = src1_data.s64 / src2_data.s64; break; - case U8_TYPE: - data.u8 = src1_data.u8 / src2_data.u8 ; break; - case U16_TYPE: - data.u16 = src1_data.u16 / src2_data.u16; break; - case U32_TYPE: - data.u32 = src1_data.u32 / src2_data.u32; break; - case U64_TYPE: - data.u64 = src1_data.u64 / src2_data.u64; break; - case B8_TYPE: - data.u8 = src1_data.u8 / src2_data.u8 ; break; - case B16_TYPE: - data.u16 = src1_data.u16 / src2_data.u16; break; - case B32_TYPE: - data.u32 = src1_data.u32 / src2_data.u32; break; - case B64_TYPE: - data.u64 = src1_data.u64 / src2_data.u64; break; - case F16_TYPE: assert(0); break; - case F32_TYPE: data.f32 = src1_data.f32 / src2_data.f32; break; - case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 / src2_data.f64; break; - default: assert(0); break; - } - thread->set_operand_value(dst,data, i_type, thread,pI); -} - -void ex2_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case F32_TYPE: - data.f32 = cuda_math::__powf(2.0, src1_data.f32); - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,data, i_type, thread,pI); -} - -void exit_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - thread->set_done(); - thread->exitCore(); - thread->registerExit(); -} - -void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry = false ); - -void fma_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - mad_def(pI,thread); -} - -void isspacep_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a; - bool t=false; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - memory_space_t space = pI->get_space(); - - a = thread->get_reg(src1.get_symbol()); - addr_t addr = (addr_t)a.u64; - unsigned smid = thread->get_hw_sid(); - unsigned hwtid = thread->get_hw_tid(); - - switch( space.get_type() ) { - case shared_space: t = isspace_shared( smid, addr ); - case local_space: t = isspace_local( smid, hwtid, addr ); - case global_space: t = isspace_global( addr ); - default: abort(); - } - - ptx_reg_t p; - p.pred = t?1:0; - - thread->set_reg(dst.get_symbol(),p); -} - -void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand_info &op, memory_space *&mem, addr_t &addr) -{ - unsigned smid = thread->get_hw_sid(); - unsigned hwtid = thread->get_hw_tid(); - - if( space == param_space_unclassified ) { - // need to op to determine whether it refers to a kernel param or local param - const symbol *s = op.get_symbol(); - const type_info *t = s->type(); - type_info_key ti = t->get_key(); - if( ti.is_param_kernel() ) - space = param_space_kernel; - else if( ti.is_param_local() ) { - space = param_space_local; - } else { - printf("GPGPU-Sim PTX: ERROR ** cannot resolve .param space for '%s'\n", s->name().c_str() ); - abort(); - } - } - switch ( space.get_type() ) { - case global_space: mem = thread->get_global_memory(); break; - case param_space_local: - case local_space: - mem = thread->m_local_mem; - addr += thread->get_local_mem_stack_pointer(); - break; - case tex_space: mem = thread->get_tex_memory(); break; - case surf_space: mem = thread->get_surf_memory(); break; - case param_space_kernel: mem = thread->get_param_memory(); break; - case shared_space: mem = thread->m_shared_mem; break; - case const_space: mem = thread->get_global_memory(); break; - case generic_space: - if( thread->get_ptx_version().ver() >= 2.0 ) { - // convert generic address to memory space address - space = whichspace(addr); - switch ( space.get_type() ) { - case global_space: mem = thread->get_global_memory(); addr = generic_to_global(addr); break; - case local_space: mem = thread->m_local_mem; addr = generic_to_local(smid,hwtid,addr); break; - case shared_space: mem = thread->m_shared_mem; addr = generic_to_shared(smid,addr); break; - default: abort(); - } - } else { - abort(); - } - break; - case param_space_unclassified: - case undefined_space: - default: - abort(); - } -} - -void ld_exec( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned type = pI->get_type(); - - ptx_reg_t src1_data = thread->get_operand_value(src1, dst, type, thread, 1); - ptx_reg_t data; - memory_space_t space = pI->get_space(); - unsigned vector_spec = pI->get_vector(); - - memory_space *mem = NULL; - addr_t addr = src1_data.u32; - - decode_space(space,thread,src1,mem,addr); - - size_t size; - int t; - data.u64=0; - type_info_key::type_decode(type,size,t); - if (!vector_spec) { - mem->read(addr,size/8,&data.s64); - if( type == S16_TYPE || type == S32_TYPE ) - sign_extend(data,size,dst); - thread->set_operand_value(dst,data, type, thread, pI); - } else { - ptx_reg_t data1, data2, data3, data4; - mem->read(addr,size/8,&data1.s64); - mem->read(addr+size/8,size/8,&data2.s64); - if (vector_spec != V2_TYPE) { //either V3 or V4 - mem->read(addr+2*size/8,size/8,&data3.s64); - if (vector_spec != V3_TYPE) { //v4 - mem->read(addr+3*size/8,size/8,&data4.s64); - thread->set_vector_operand_values(dst,data1,data2,data3,data4); - } else //v3 - thread->set_vector_operand_values(dst,data1,data2,data3,data3); - } else //v2 - thread->set_vector_operand_values(dst,data1,data2,data2,data2); - } - thread->m_last_effective_address = addr; - thread->m_last_memory_space = space; -} - -void ld_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ld_exec(pI,thread); -} -void ldu_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ld_exec(pI,thread); -} - -void lg2_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case F32_TYPE: - d.f32 = log(a.f32)/log(2); - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void mad24_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - ptx_reg_t d, t; - - unsigned i_type = pI->get_type(); - ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); - ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); - ptx_reg_t c = thread->get_operand_value(src3, dst, i_type, thread, 1); - - unsigned sat_mode = pI->saturation_mode(); - - assert( !pI->is_wide() ); - - switch ( i_type ) { - case S32_TYPE: - t.s64 = a.s32 * b.s32; - if ( pI->is_hi() ) { - d.s64 = (t.s64>>16) + c.s32; - if ( sat_mode ) { - if ( d.s64 > (int)0x7FFFFFFF ) - d.s64 = (int)0x7FFFFFFF; - else if ( d.s64 < (int)0x80000000 ) - d.s64 = (int)0x80000000; - } - } else if ( pI->is_lo() ) d.s64 = t.s32 + c.s32; - else assert(0); - break; - case U32_TYPE: - t.u64 = a.u32 * b.u32; - if ( pI->is_hi() ) d.u64 = (t.u64>>16) + c.u32; - else if ( pI->is_lo() ) d.u64 = t.u32 + c.u32; - else assert(0); - break; - default: - assert(0); - break; - } - - thread->set_operand_value(dst, d, i_type, thread, pI); -} - -void mad_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - mad_def(pI, thread, false); -} - -void madp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - mad_def(pI, thread, true); -} - -void madc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - mad_def(pI, thread, true); -} - -void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry ) -{ - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - ptx_reg_t d, t; - - int carry=0; - int overflow=0; - - unsigned i_type = pI->get_type(); - ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); - ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); - ptx_reg_t c = thread->get_operand_value(src3, dst, i_type, thread, 1); - - // take the carry bit, it should be the 4th operand - ptx_reg_t carry_bit; - carry_bit.u64 = 0; - if (use_carry) { - const operand_info &carry = pI->operand_lookup(4); - carry_bit = thread->get_operand_value(carry, dst, PRED_TYPE, thread, 0); - carry_bit.pred &= 0x4; - carry_bit.pred >>=2; - } - - unsigned rounding_mode = pI->rounding_mode(); - - switch ( i_type ) { - case S16_TYPE: - t.s32 = a.s16 * b.s16; - if ( pI->is_wide() ) d.s32 = t.s32 + c.s32 + carry_bit.pred; - else if ( pI->is_hi() ) d.s16 = (t.s32>>16) + c.s16 + carry_bit.pred; - else if ( pI->is_lo() ) d.s16 = t.s16 + c.s16 + carry_bit.pred; - else assert(0); - carry = ((long long int)(t.s32 + c.s32 + carry_bit.pred)&0x100000000)>>32; - break; - case S32_TYPE: - t.s64 = a.s32 * b.s32; - if ( pI->is_wide() ) d.s64 = t.s64 + c.s64 + carry_bit.pred; - else if ( pI->is_hi() ) d.s32 = (t.s64>>32) + c.s32 + carry_bit.pred; - else if ( pI->is_lo() ) d.s32 = t.s32 + c.s32 + carry_bit.pred; - else assert(0); - break; - case S64_TYPE: - t.s64 = a.s64 * b.s64; - assert( !pI->is_wide() ); - assert( !pI->is_hi() ); - assert( use_carry == false); - if ( pI->is_lo() ) d.s64 = t.s64 + c.s64 + carry_bit.pred; - else assert(0); - break; - case U16_TYPE: - t.u32 = a.u16 * b.u16; - if ( pI->is_wide() ) d.u32 = t.u32 + c.u32 + carry_bit.pred; - else if ( pI->is_hi() ) d.u16 = (t.u32 + c.u16 + carry_bit.pred)>>16; - else if ( pI->is_lo() ) d.u16 = t.u16 + c.u16 + carry_bit.pred; - else assert(0); - carry = ((long long int)((long long int)t.u32 + c.u32 + carry_bit.pred)&0x100000000)>>32; - break; - case U32_TYPE: - t.u64 = a.u32 * b.u32; - if ( pI->is_wide() ) d.u64 = t.u64 + c.u64 + carry_bit.pred; - else if ( pI->is_hi() ) d.u32 = (t.u64 + c.u32 + carry_bit.pred)>>32; - else if ( pI->is_lo() ) d.u32 = t.u32 + c.u32 + carry_bit.pred; - else assert(0); - break; - case U64_TYPE: - t.u64 = a.u64 * b.u64; - assert( !pI->is_wide() ); - assert( !pI->is_hi() ); - assert( use_carry == false); - if ( pI->is_lo() ) d.u64 = t.u64 + c.u64 + carry_bit.pred; - else assert(0); - break; - case F16_TYPE: - assert(0); - break; - case F32_TYPE: { - assert( use_carry == false); - int orig_rm = fegetround(); - switch ( rounding_mode ) { - case RN_OPTION: break; - case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; - default: assert(0); break; - } - d.f32 = a.f32 * b.f32 + c.f32; - if ( pI->saturation_mode() ) { - if ( d.f32 < 0 ) d.f32 = 0; - else if ( d.f32 > 1.0f ) d.f32 = 1.0f; - } - fesetround( orig_rm ); - break; - } - case F64_TYPE: case FF64_TYPE: { - assert( use_carry == false); - int orig_rm = fegetround(); - switch ( rounding_mode ) { - case RN_OPTION: break; - case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; - default: assert(0); break; - } - d.f64 = a.f64 * b.f64 + c.f64; - if ( pI->saturation_mode() ) { - if ( d.f64 < 0 ) d.f64 = 0; - else if ( d.f64 > 1.0f ) d.f64 = 1.0; - } - fesetround( orig_rm ); - break; - } - default: - assert(0); - break; - } - thread->set_operand_value(dst, d, i_type, thread, pI, overflow, carry); -} - -bool isNaN(float x) -{ - return std::isnan(x); -} - -bool isNaN(double x) -{ - return std::isnan(x); -} - -void max_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - b = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - switch ( i_type ) { - case U16_TYPE: d.u16 = MY_MAX_I(a.u16,b.u16); break; - case U32_TYPE: d.u32 = MY_MAX_I(a.u32,b.u32); break; - case U64_TYPE: d.u64 = MY_MAX_I(a.u64,b.u64); break; - case S16_TYPE: d.s16 = MY_MAX_I(a.s16,b.s16); break; - case S32_TYPE: d.s32 = MY_MAX_I(a.s32,b.s32); break; - case S64_TYPE: d.s64 = MY_MAX_I(a.s64,b.s64); break; - case F32_TYPE: d.f32 = MY_MAX_F(a.f32,b.f32); break; - case F64_TYPE: case FF64_TYPE: d.f64 = MY_MAX_F(a.f64,b.f64); break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void membar_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - // handled by timing simulator -} - -void min_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - b = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - switch ( i_type ) { - case U16_TYPE: d.u16 = MY_MIN_I(a.u16,b.u16); break; - case U32_TYPE: d.u32 = MY_MIN_I(a.u32,b.u32); break; - case U64_TYPE: d.u64 = MY_MIN_I(a.u64,b.u64); break; - case S16_TYPE: d.s16 = MY_MIN_I(a.s16,b.s16); break; - case S32_TYPE: d.s32 = MY_MIN_I(a.s32,b.s32); break; - case S64_TYPE: d.s64 = MY_MIN_I(a.s64,b.s64); break; - case F32_TYPE: d.f32 = MY_MIN_F(a.f32,b.f32); break; - case F64_TYPE: case FF64_TYPE: d.f64 = MY_MIN_F(a.f64,b.f64); break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void mov_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - unsigned i_type = pI->get_type(); - - if( (src1.is_vector() || dst.is_vector()) && (i_type != BB64_TYPE) && (i_type != BB128_TYPE) && (i_type != FF64_TYPE) ) { - // pack or unpack operation - unsigned nbits_to_move; - ptx_reg_t tmp_bits; - - switch( pI->get_type() ) { - case B16_TYPE: nbits_to_move = 16; break; - case B32_TYPE: nbits_to_move = 32; break; - case B64_TYPE: nbits_to_move = 64; break; - default: printf("Execution error: mov pack/unpack with unsupported type qualifier\n"); assert(0); break; - } - - if( src1.is_vector() ) { - unsigned nelem = src1.get_vect_nelem(); - ptx_reg_t v[4]; - thread->get_vector_operand_values(src1, v, nelem ); - - unsigned bits_per_src_elem = nbits_to_move / nelem; - for( unsigned i=0; i < nelem; i++ ) { - switch(bits_per_src_elem) { - case 8: tmp_bits.u64 |= ((unsigned long long)(v[i].u8) << (8*i)); break; - case 16: tmp_bits.u64 |= ((unsigned long long)(v[i].u16) << (16*i)); break; - case 32: tmp_bits.u64 |= ((unsigned long long)(v[i].u32) << (32*i)); break; - default: printf("Execution error: mov pack/unpack with unsupported source/dst size ratio (src)\n"); assert(0); break; - } - } - } else { - data = thread->get_operand_value(src1, dst, i_type, thread, 1); - - switch( pI->get_type() ) { - case B16_TYPE: tmp_bits.u16 = data.u16; break; - case B32_TYPE: tmp_bits.u32 = data.u32; break; - case B64_TYPE: tmp_bits.u64 = data.u64; break; - default: assert(0); break; - } - } - - if( dst.is_vector() ) { - unsigned nelem = dst.get_vect_nelem(); - ptx_reg_t v[4]; - unsigned bits_per_dst_elem = nbits_to_move / nelem; - for( unsigned i=0; i < nelem; i++ ) { - switch(bits_per_dst_elem) { - case 8: v[i].u8 = (tmp_bits.u64 >> (8*i)) & ((unsigned long long) 0xFF); break; - case 16: v[i].u16 = (tmp_bits.u64 >> (16*i)) & ((unsigned long long) 0xFFFF); break; - case 32: v[i].u32 = (tmp_bits.u64 >> (32*i)) & ((unsigned long long) 0xFFFFFFFF); break; - default: - printf("Execution error: mov pack/unpack with unsupported source/dst size ratio (dst)\n"); - assert(0); - break; - } - } - thread->set_vector_operand_values(dst,v[0],v[1],v[2],v[3]); - } else { - thread->set_operand_value(dst,tmp_bits, i_type, thread, pI); - } - } else if (i_type == PRED_TYPE and src1.is_literal() == true) { - // in ptx, literal input translate to predicate as 0 = false and 1 = true - // we have adopted the opposite to simplify implementation of zero flags in ptxplus - data = thread->get_operand_value(src1, dst, i_type, thread, 1); - - ptx_reg_t finaldata; - finaldata.pred = (data.u32 == 0)? 1 : 0; // setting zero-flag in predicate - thread->set_operand_value(dst, finaldata, i_type, thread, pI); - } else { - - data = thread->get_operand_value(src1, dst, i_type, thread, 1); - - thread->set_operand_value(dst, data, i_type, thread, pI); - - } -} - -void mul24_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - //src1_data = srcOperandModifiers(src1_data, src1, dst, i_type, thread); - //src2_data = srcOperandModifiers(src2_data, src2, dst, i_type, thread); - - src1_data.mask_and(0,0x00FFFFFF); - src2_data.mask_and(0,0x00FFFFFF); - - switch ( i_type ) { - case S32_TYPE: - if( src1_data.get_bit(23) ) - src1_data.mask_or(0xFFFFFFFF,0xFF000000); - if( src2_data.get_bit(23) ) - src2_data.mask_or(0xFFFFFFFF,0xFF000000); - data.s64 = src1_data.s64 * src2_data.s64; - break; - case U32_TYPE: - data.u64 = src1_data.u64 * src2_data.u64; - break; - default: - printf("GPGPU-Sim PTX: Execution error - type mismatch with instruction\n"); - assert(0); - break; - } - - if ( pI->is_hi() ) { - data.u64 = data.u64 >> 16; - data.mask_and(0,0xFFFFFFFF); - } else if (pI->is_lo()) { - data.mask_and(0,0xFFFFFFFF); - } - - thread->set_operand_value(dst, data, i_type, thread, pI); -} - -void mul_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - ptx_reg_t d, t; - - unsigned i_type = pI->get_type(); - ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); - ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); - - unsigned rounding_mode = pI->rounding_mode(); - - switch ( i_type ) { - case S16_TYPE: - t.s32 = ((int)a.s16) * ((int)b.s16); - if ( pI->is_wide() ) d.s32 = t.s32; - else if ( pI->is_hi() ) d.s16 = (t.s32>>16); - else if ( pI->is_lo() ) d.s16 = t.s16; - else assert(0); - break; - case S32_TYPE: - t.s64 = ((long long)a.s32) * ((long long)b.s32); - if ( pI->is_wide() ) d.s64 = t.s64; - else if ( pI->is_hi() ) d.s32 = (t.s64>>32); - else if ( pI->is_lo() ) d.s32 = t.s32; - else assert(0); - break; - case S64_TYPE: - t.s64 = a.s64 * b.s64; - assert( !pI->is_wide() ); - assert( !pI->is_hi() ); - if ( pI->is_lo() ) d.s64 = t.s64; - else assert(0); - break; - case U16_TYPE: - t.u32 = ((unsigned)a.u16) * ((unsigned)b.u16); - if ( pI->is_wide() ) d.u32 = t.u32; - else if ( pI->is_lo() ) d.u16 = t.u16; - else if ( pI->is_hi() ) d.u16 = (t.u32>>16); - else assert(0); - break; - case U32_TYPE: - t.u64 = ((unsigned long long)a.u32) * ((unsigned long long)b.u32); - if ( pI->is_wide() ) d.u64 = t.u64; - else if ( pI->is_lo() ) d.u32 = t.u32; - else if ( pI->is_hi() ) d.u32 = (t.u64>>32); - else assert(0); - break; - case U64_TYPE: - t.u64 = a.u64 * b.u64; - assert( !pI->is_wide() ); - assert( !pI->is_hi() ); - if ( pI->is_lo() ) d.u64 = t.u64; - else assert(0); - break; - case F16_TYPE: - assert(0); - break; - case F32_TYPE: { - int orig_rm = fegetround(); - switch ( rounding_mode ) { - case RN_OPTION: break; - case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; - default: assert(0); break; - } - - d.f32 = a.f32 * b.f32; - - if ( pI->saturation_mode() ) { - if ( d.f32 < 0 ) d.f32 = 0; - else if ( d.f32 > 1.0f ) d.f32 = 1.0f; - } - fesetround( orig_rm ); - break; - } - case F64_TYPE: case FF64_TYPE:{ - int orig_rm = fegetround(); - switch ( rounding_mode ) { - case RN_OPTION: break; - case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; - default: assert(0); break; - } - d.f64 = a.f64 * b.f64; - if ( pI->saturation_mode() ) { - if ( d.f64 < 0 ) d.f64 = 0; - else if ( d.f64 > 1.0f ) d.f64 = 1.0; - } - fesetround( orig_rm ); - break; - } - default: - assert(0); - break; - } - - thread->set_operand_value(dst, d, i_type, thread, pI); -} - -void neg_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned to_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, to_type, thread, 1); - - - switch ( to_type ) { - case S8_TYPE: - case S16_TYPE: - case S32_TYPE: - case S64_TYPE: - data.s64 = 0 - src1_data.s64; break; // seems buggy, but not (just ignore higher bits) - case U8_TYPE: - case U16_TYPE: - case U32_TYPE: - case U64_TYPE: - assert(0); break; - case F16_TYPE: assert(0); break; - case F32_TYPE: data.f32 = 0.0f - src1_data.f32; break; - case F64_TYPE: case FF64_TYPE: data.f64 = 0.0f - src1_data.f64; break; - default: assert(0); break; - } - - thread->set_operand_value(dst,data, to_type, thread, pI); -} - -//nandn bitwise negates second operand then bitwise nands with the first operand -void nandn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - //the way ptxplus handles predicates: 1 = false and 0 = true - if(i_type == PRED_TYPE) - data.pred = (~src1_data.pred & src2_data.pred); - else - data.u64 = ~(src1_data.u64 & ~src2_data.u64); - - thread->set_operand_value(dst,data, i_type, thread, pI); - -} - -//norn bitwise negates first operand then bitwise ands with the second operand -void norn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - //the way ptxplus handles predicates: 1 = false and 0 = true - if(i_type == PRED_TYPE) - data.pred = ~(src1_data.pred & ~(src2_data.pred)); - else - data.u64 = ~(src1_data.u64) & src2_data.u64; - - thread->set_operand_value(dst,data, i_type, thread, pI); - -} - -void not_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case PRED_TYPE: d.pred = (~(a.pred) & 0x000F); break; - case B16_TYPE: d.u16 = ~a.u16; break; - case B32_TYPE: d.u32 = ~a.u32; break; - case B64_TYPE: d.u64 = ~a.u64; break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void or_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - //the way ptxplus handles predicates: 1 = false and 0 = true - if(i_type == PRED_TYPE) - data.pred = ~(~(src1_data.pred) | ~(src2_data.pred)); - else - data.u64 = src1_data.u64 | src2_data.u64; - - thread->set_operand_value(dst,data, i_type, thread, pI); -} - -void orn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - //the way ptxplus handles predicates: 1 = false and 0 = true - if(i_type == PRED_TYPE) - data.pred = ~(~(src1_data.pred) | (src2_data.pred)); - else - data.u64 = src1_data.u64 | ~src2_data.u64; - - thread->set_operand_value(dst,data, i_type, thread, pI); -} - -void pmevent_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void popc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src_data, data; - const operand_info &dst = pI->dst(); - const operand_info &src = pI->src1(); - - unsigned i_type = pI->get_type(); - src_data = thread->get_operand_value(src, dst, i_type, thread, 1); - - switch ( i_type ) { - case B32_TYPE: { - std::bitset<32> mask(src_data.u32); - data.u32 = mask.count(); - } break; - case B64_TYPE: { - std::bitset<64> mask(src_data.u64); - data.u32 = mask.count(); - } break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,data, i_type, thread, pI); -} -void prefetch_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void prefetchu_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void prmt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } - -void rcp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case F32_TYPE: - data.f32 = 1.0f / src1_data.f32; - break; - case F64_TYPE: - case FF64_TYPE: - data.f64 = 1.0f / src1_data.f64; - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,data, i_type, thread, pI); -} - -void red_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } - -void rem_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - data.u64 = src1_data.u64 % src2_data.u64; - - thread->set_operand_value(dst,data, i_type, thread, pI); -} - -void ret_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - bool empty = thread->callstack_pop(); - if( empty ) { - thread->set_done(); - thread->exitCore(); - thread->registerExit(); - } -} - -//Ptxplus version of ret instruction. -void retp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - bool empty = thread->callstack_pop_plus(); - if( empty ) { - thread->set_done(); - thread->exitCore(); - thread->registerExit(); - } -} - -void rsqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case F32_TYPE: - if ( a.f32 < 0 ) { - d.u64 = 0; - d.u64 = 0x7fc00000; // NaN - } else if ( a.f32 == 0 ) { - d.u64 = 0; - d.u32 = 0x7f800000; // Inf - } else - d.f32 = cuda_math::__internal_accurate_fdividef(1.0f, sqrtf(a.f32)); - break; - case F64_TYPE: - case FF64_TYPE: - if ( a.f32 < 0 ) { - d.u64 = 0; - d.u32 = 0x7fc00000; // NaN - float x = d.f32; - d.f64 = (double)x; - } else if ( a.f32 == 0 ) { - d.u64 = 0; - d.u32 = 0x7f800000; // Inf - float x = d.f32; - d.f64 = (double)x; - } else - d.f64 = 1.0 / sqrt(a.f64); - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -#define SAD(d,a,b,c) d = c + ((adst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - b = thread->get_operand_value(src2, dst, i_type, thread, 1); - c = thread->get_operand_value(src3, dst, i_type, thread, 1); - - - switch ( i_type ) { - case U16_TYPE: SAD(d.u16,a.u16,b.u16,c.u16); break; - case U32_TYPE: SAD(d.u32,a.u32,b.u32,c.u32); break; - case U64_TYPE: SAD(d.u64,a.u64,b.u64,c.u64); break; - case S16_TYPE: SAD(d.s16,a.s16,b.s16,c.s16); break; - case S32_TYPE: SAD(d.s32,a.s32,b.s32,c.s32); break; - case S64_TYPE: SAD(d.s64,a.s64,b.s64,c.s64); break; - case F32_TYPE: SAD(d.f32,a.f32,b.f32,c.f32); break; - case F64_TYPE: case FF64_TYPE: SAD(d.f64,a.f64,b.f64,c.f64); break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void selp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - - ptx_reg_t a, b, c, d; - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - b = thread->get_operand_value(src2, dst, i_type, thread, 1); - c = thread->get_operand_value(src3, dst, i_type, thread, 1); - - //predicate value was changed so the lowest bit being set means the zero flag is set. - //As a result, the value of c.pred must be inverted to get proper behavior - d = (!(c.pred & 0x0001))?a:b; - - thread->set_operand_value(dst,d, PRED_TYPE, thread, pI); -} - -bool isFloat(int type) -{ - switch ( type ) { - case F16_TYPE: - case F32_TYPE: - case F64_TYPE: - case FF64_TYPE: - return true; - default: - return false; - } -} - -bool CmpOp( int type, ptx_reg_t a, ptx_reg_t b, unsigned cmpop ) -{ - bool t = false; - - switch ( type ) { - case B16_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.u16 == b.u16); break; - case NE_OPTION: t = (a.u16 != b.u16); break; - default: - assert(0); - } - - case B32_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.u32 == b.u32); break; - case NE_OPTION: t = (a.u32 != b.u32); break; - default: - assert(0); - } - case B64_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.u64 == b.u64); break; - case NE_OPTION: t = (a.u64 != b.u64); break; - default: - assert(0); - } - break; - case S8_TYPE: - case S16_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.s16 == b.s16); break; - case NE_OPTION: t = (a.s16 != b.s16); break; - case LT_OPTION: t = (a.s16 < b.s16); break; - case LE_OPTION: t = (a.s16 <= b.s16); break; - case GT_OPTION: t = (a.s16 > b.s16); break; - case GE_OPTION: t = (a.s16 >= b.s16); break; - default: - assert(0); - } - break; - case S32_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.s32 == b.s32); break; - case NE_OPTION: t = (a.s32 != b.s32); break; - case LT_OPTION: t = (a.s32 < b.s32); break; - case LE_OPTION: t = (a.s32 <= b.s32); break; - case GT_OPTION: t = (a.s32 > b.s32); break; - case GE_OPTION: t = (a.s32 >= b.s32); break; - default: - assert(0); - } - break; - case S64_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.s64 == b.s64); break; - case NE_OPTION: t = (a.s64 != b.s64); break; - case LT_OPTION: t = (a.s64 < b.s64); break; - case LE_OPTION: t = (a.s64 <= b.s64); break; - case GT_OPTION: t = (a.s64 > b.s64); break; - case GE_OPTION: t = (a.s64 >= b.s64); break; - default: - assert(0); - } - break; - case U8_TYPE: - case U16_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.u16 == b.u16); break; - case NE_OPTION: t = (a.u16 != b.u16); break; - case LT_OPTION: t = (a.u16 < b.u16); break; - case LE_OPTION: t = (a.u16 <= b.u16); break; - case GT_OPTION: t = (a.u16 > b.u16); break; - case GE_OPTION: t = (a.u16 >= b.u16); break; - case LO_OPTION: t = (a.u16 < b.u16); break; - case LS_OPTION: t = (a.u16 <= b.u16); break; - case HI_OPTION: t = (a.u16 > b.u16); break; - case HS_OPTION: t = (a.u16 >= b.u16); break; - default: - assert(0); - } - break; - case U32_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.u32 == b.u32); break; - case NE_OPTION: t = (a.u32 != b.u32); break; - case LT_OPTION: t = (a.u32 < b.u32); break; - case LE_OPTION: t = (a.u32 <= b.u32); break; - case GT_OPTION: t = (a.u32 > b.u32); break; - case GE_OPTION: t = (a.u32 >= b.u32); break; - case LO_OPTION: t = (a.u32 < b.u32); break; - case LS_OPTION: t = (a.u32 <= b.u32); break; - case HI_OPTION: t = (a.u32 > b.u32); break; - case HS_OPTION: t = (a.u32 >= b.u32); break; - default: - assert(0); - } - break; - case U64_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.u64 == b.u64); break; - case NE_OPTION: t = (a.u64 != b.u64); break; - case LT_OPTION: t = (a.u64 < b.u64); break; - case LE_OPTION: t = (a.u64 <= b.u64); break; - case GT_OPTION: t = (a.u64 > b.u64); break; - case GE_OPTION: t = (a.u64 >= b.u64); break; - case LO_OPTION: t = (a.u64 < b.u64); break; - case LS_OPTION: t = (a.u64 <= b.u64); break; - case HI_OPTION: t = (a.u64 > b.u64); break; - case HS_OPTION: t = (a.u64 >= b.u64); break; - default: - assert(0); - } - break; - case F16_TYPE: assert(0); break; - case F32_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.f32 == b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; - case NE_OPTION: t = (a.f32 != b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; - case LT_OPTION: t = (a.f32 < b.f32 ) && !isNaN(a.f32) && !isNaN(b.f32); break; - case LE_OPTION: t = (a.f32 <= b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; - case GT_OPTION: t = (a.f32 > b.f32 ) && !isNaN(a.f32) && !isNaN(b.f32); break; - case GE_OPTION: t = (a.f32 >= b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; - case EQU_OPTION: t = (a.f32 == b.f32) || isNaN(a.f32) || isNaN(b.f32); break; - case NEU_OPTION: t = (a.f32 != b.f32) || isNaN(a.f32) || isNaN(b.f32); break; - case LTU_OPTION: t = (a.f32 < b.f32 ) || isNaN(a.f32) || isNaN(b.f32); break; - case LEU_OPTION: t = (a.f32 <= b.f32) || isNaN(a.f32) || isNaN(b.f32); break; - case GTU_OPTION: t = (a.f32 > b.f32 ) || isNaN(a.f32) || isNaN(b.f32); break; - case GEU_OPTION: t = (a.f32 >= b.f32) || isNaN(a.f32) || isNaN(b.f32); break; - case NUM_OPTION: t = !isNaN(a.f32) && !isNaN(b.f32); break; - case NAN_OPTION: t = isNaN(a.f32) || isNaN(b.f32); break; - default: - assert(0); - } - break; - case F64_TYPE: - case FF64_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.f64 == b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; - case NE_OPTION: t = (a.f64 != b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; - case LT_OPTION: t = (a.f64 < b.f64 ) && !isNaN(a.f64) && !isNaN(b.f64); break; - case LE_OPTION: t = (a.f64 <= b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; - case GT_OPTION: t = (a.f64 > b.f64 ) && !isNaN(a.f64) && !isNaN(b.f64); break; - case GE_OPTION: t = (a.f64 >= b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; - case EQU_OPTION: t = (a.f64 == b.f64) || isNaN(a.f64) || isNaN(b.f64); break; - case NEU_OPTION: t = (a.f64 != b.f64) || isNaN(a.f64) || isNaN(b.f64); break; - case LTU_OPTION: t = (a.f64 < b.f64 ) || isNaN(a.f64) || isNaN(b.f64); break; - case LEU_OPTION: t = (a.f64 <= b.f64) || isNaN(a.f64) || isNaN(b.f64); break; - case GTU_OPTION: t = (a.f64 > b.f64 ) || isNaN(a.f64) || isNaN(b.f64); break; - case GEU_OPTION: t = (a.f64 >= b.f64) || isNaN(a.f64) || isNaN(b.f64); break; - case NUM_OPTION: t = !isNaN(a.f64) && !isNaN(b.f64); break; - case NAN_OPTION: t = isNaN(a.f64) || isNaN(b.f64); break; - default: - assert(0); - } - break; - default: assert(0); break; - } - - return t; -} - -void setp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b; - - int t=0; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - assert( pI->get_num_operands() < 4 ); // or need to deal with "c" operand / boolOp - - unsigned type = pI->get_type(); - unsigned cmpop = pI->get_cmpop(); - a = thread->get_operand_value(src1, dst, type, thread, 1); - b = thread->get_operand_value(src2, dst, type, thread, 1); - - t = CmpOp(type,a,b,cmpop); - - ptx_reg_t data; - - //the way ptxplus handles the zero flag, 1 = false and 0 = true - data.pred = (t==0); //inverting predicate since ptxplus uses "1" for a set zero flag - - thread->set_operand_value(dst,data, PRED_TYPE, thread, pI); -} - -void set_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b; - - int t=0; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - assert( pI->get_num_operands() < 4 ); // or need to deal with "c" operand / boolOp - - unsigned src_type = pI->get_type2(); - unsigned cmpop = pI->get_cmpop(); - - a = thread->get_operand_value(src1, dst, src_type, thread, 1); - b = thread->get_operand_value(src2, dst, src_type, thread, 1); - - // Take abs of first operand if needed - if(pI->is_abs()) { - switch ( src_type ) { - case S16_TYPE: a.s16 = my_abs(a.s16); break; - case S32_TYPE: a.s32 = my_abs(a.s32); break; - case S64_TYPE: a.s64 = my_abs(a.s64); break; - case U16_TYPE: a.u16 = a.u16; break; - case U32_TYPE: a.u32 = my_abs(a.u32); break; - case U64_TYPE: a.u64 = my_abs(a.u64); break; - case F32_TYPE: a.f32 = my_abs(a.f32); break; - case F64_TYPE: case FF64_TYPE: a.f64 = my_abs(a.f64); break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - } - - t = CmpOp(src_type,a,b,cmpop); - - ptx_reg_t data; - if ( isFloat(pI->get_type()) ) { - data.f32 = (t!=0)?1.0f:0.0f; - } else { - data.u32 = (t!=0)?0xFFFFFFFF:0; - } - - thread->set_operand_value(dst, data, pI->get_type(), thread, pI); - -} - -void shfl_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) -{ - unsigned i_type = pI->get_type(); - int tid = inst.warp_id() * core->get_warp_size(); - ptx_thread_info *thread = core->get_thread_info()[tid]; - ptx_warp_info *warp_info = thread->m_warp_info; - int lane = warp_info->get_done_threads(); - thread = core->get_thread_info()[tid + lane]; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - int bval = (thread->get_operand_value(src2, dst, i_type, thread, 1)).u32; - int cval = (thread->get_operand_value(src3, dst, i_type, thread, 1)).u32; - int mask = cval >> 8; - bval &= 0x1F; - cval &= 0x1F; - - int maxLane = (lane & mask) | (cval & ~mask); - int minLane = lane & mask; - - int src_idx; - unsigned p; - switch(pI->shfl_op()) { - case UP_OPTION: - src_idx = lane - bval; - p = (src_idx >= maxLane); - break; - case DOWN_OPTION: - src_idx = lane + bval; - p = (src_idx <= maxLane); - break; - case BFLY_OPTION: - src_idx = lane ^ bval; - p = (src_idx <= maxLane); - break; - case IDX_OPTION: - src_idx = minLane | (bval & ~mask); - p = (src_idx <= maxLane); - break; - default: - printf("GPGPU-Sim PTX: ERROR: Invalid shfl option\n"); - assert(0); - break; - } - // copy from own lane - if (!p) src_idx = lane; - - // copy input from lane src_idx - ptx_reg_t data; - if (inst.active(src_idx)) { - ptx_thread_info *source = core->get_thread_info()[tid + src_idx]; - data = source->get_operand_value(src1, dst, i_type, source, 1); - } else { - printf("GPGPU-Sim PTX: WARNING: shfl input value unpredictable for inactive threads in a warp\n"); - data.u32 = 0; - } - thread->set_operand_value(dst, data, i_type, thread, pI); - - /* - TODO: deal with predicates appropriately using the following pseudocode: - if (!isGuardPredicateTrue(src_idx)) { - printf("GPGPU-Sim PTX: WARNING: shfl input value unpredictable for predicated-off threads in a warp\n"); - } - if (dest predicate selected) data.pred = p; - */ - - // keep track of the number of threads that have executed in the warp - warp_info->inc_done_threads(); - if (warp_info->get_done_threads() == inst.active_count()) { - warp_info->reset_done_threads(); - } -} - -void shl_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - b = thread->get_operand_value(src2, dst, i_type, thread, 1); - - switch ( i_type ) { - case B16_TYPE: - case U16_TYPE: - if ( b.u16 >= 16 ) - d.u16 = 0; - else - d.u16 = (unsigned short) ((a.u16 << b.u16) & 0xFFFF); - break; - case B32_TYPE: - case U32_TYPE: - if ( b.u32 >= 32 ) - d.u32 = 0; - else - d.u32 = (unsigned) ((a.u32 << b.u32) & 0xFFFFFFFF); - break; - case B64_TYPE: - case U64_TYPE: - if ( b.u32 >= 64 ) - d.u64 = 0; - else - d.u64 = (a.u64 << b.u64); - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst, d, i_type, thread, pI); -} - -void shr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - b = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - switch ( i_type ) { - case U16_TYPE: - case B16_TYPE: - if ( b.u16 < 16 ) - d.u16 = (unsigned short) ((a.u16 >> b.u16) & 0xFFFF); - else - d.u16 = 0; - break; - case U32_TYPE: - case B32_TYPE: - if ( b.u32 < 32 ) - d.u32 = (unsigned) ((a.u32 >> b.u32) & 0xFFFFFFFF); - else - d.u32 = 0; - break; - case U64_TYPE: - case B64_TYPE: - if ( b.u32 < 64 ) - d.u64 = (a.u64 >> b.u64); - else - d.u64 = 0; - break; - case S16_TYPE: - if ( b.u16 < 16 ) - d.s64 = (a.s16 >> b.s16); - else { - if ( a.s16 < 0 ) { - d.s64 = -1; - } else { - d.s64 = 0; - } - } - break; - case S32_TYPE: - if ( b.u32 < 32 ) - d.s64 = (a.s32 >> b.s32); - else { - if ( a.s32 < 0 ) { - d.s64 = -1; - } else { - d.s64 = 0; - } - } - break; - case S64_TYPE: - if ( b.u64 < 64 ) - d.s64 = (a.s64 >> b.u64); - else { - if ( a.s64 < 0 ) { - if ( b.s32 < 0 ) { - d.u64 = -1; - d.s32 = 0; - } else { - d.s64 = -1; - } - } else { - d.s64 = 0; - } - } - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void sin_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case F32_TYPE: - d.f32 = sin(a.f32); - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void slct_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - - ptx_reg_t a, b, c, d; - - unsigned i_type = pI->get_type(); - unsigned c_type = pI->get_type2(); - bool t = false; - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - b = thread->get_operand_value(src2, dst, i_type, thread, 1); - c = thread->get_operand_value(src3, dst, c_type, thread, 1); - - switch ( c_type ) { - case S32_TYPE: t = c.s32 >= 0; break; - case F32_TYPE: t = c.f32 >= 0; break; - default: assert(0); - } - - switch ( i_type ) { - case B16_TYPE: - case S16_TYPE: - case U16_TYPE: d.u16 = t?a.u16:b.u16; break; - case F32_TYPE: - case B32_TYPE: - case S32_TYPE: - case U32_TYPE: d.u32 = t?a.u32:b.u32; break; - case F64_TYPE: - case FF64_TYPE: - case B64_TYPE: - case S64_TYPE: - case U64_TYPE: d.u64 = t?a.u64:b.u64; break; - default: assert(0); - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case F32_TYPE: - if ( a.f32 < 0 ) - d.f32 = nanf(""); - else - d.f32 = sqrt(a.f32); break; - case F64_TYPE: - case FF64_TYPE: - if ( a.f64 < 0 ) - d.f64 = nan(""); - else - d.f64 = sqrt(a.f64); break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void ssy_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - //printf("Execution Warning: unimplemented ssy instruction is treated as a nop\n"); - // TODO: add implementation -} - -void st_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); //may be scalar or vector of regs - unsigned type = pI->get_type(); - ptx_reg_t addr_reg = thread->get_operand_value(dst, dst, type, thread, 1); - ptx_reg_t data; - memory_space_t space = pI->get_space(); - unsigned vector_spec = pI->get_vector(); - - memory_space *mem = NULL; - addr_t addr = addr_reg.u32; - - decode_space(space,thread,dst,mem,addr); - - size_t size; - int t; - type_info_key::type_decode(type,size,t); - - if (!vector_spec) { - data = thread->get_operand_value(src1, dst, type, thread, 1); - mem->write(addr,size/8,&data.s64,thread,pI); - } else { - if (vector_spec == V2_TYPE) { - ptx_reg_t* ptx_regs = new ptx_reg_t[2]; - thread->get_vector_operand_values(src1, ptx_regs, 2); - mem->write(addr,size/8,&ptx_regs[0].s64,thread,pI); - mem->write(addr+size/8,size/8,&ptx_regs[1].s64,thread,pI); - delete [] ptx_regs; - } - if (vector_spec == V3_TYPE) { - ptx_reg_t* ptx_regs = new ptx_reg_t[3]; - thread->get_vector_operand_values(src1, ptx_regs, 3); - mem->write(addr,size/8,&ptx_regs[0].s64,thread,pI); - mem->write(addr+size/8,size/8,&ptx_regs[1].s64,thread,pI); - mem->write(addr+2*size/8,size/8,&ptx_regs[2].s64,thread,pI); - delete [] ptx_regs; - } - if (vector_spec == V4_TYPE) { - ptx_reg_t* ptx_regs = new ptx_reg_t[4]; - thread->get_vector_operand_values(src1, ptx_regs, 4); - mem->write(addr,size/8,&ptx_regs[0].s64,thread,pI); - mem->write(addr+size/8,size/8,&ptx_regs[1].s64,thread,pI); - mem->write(addr+2*size/8,size/8,&ptx_regs[2].s64,thread,pI); - mem->write(addr+3*size/8,size/8,&ptx_regs[3].s64,thread,pI); - delete [] ptx_regs; - } - } - thread->m_last_effective_address = addr; - thread->m_last_memory_space = space; -} - -void sub_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t data; - int overflow = 0; - int carry = 0; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - ptx_reg_t src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - ptx_reg_t src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - //performs addition. Sets carry and overflow if needed. - //the constant is added in during subtraction so the carry bit is set properly. - switch ( i_type ) { - case S8_TYPE: - data.s64 = (src1_data.s64 & 0xFF) - (src2_data.s64 & 0xFF) + 0x100; - if(((src1_data.s64 & 0x80)-(src2_data.s64 & 0x80)) != 0) {overflow=((src1_data.s64 & 0x80)-(data.s64 & 0x80))==0?0:1; } - carry = (data.s32 & 0x100)>>8; - break; - case S16_TYPE: - data.s64 = (src1_data.s64 & 0xFFFF) - (src2_data.s64 & 0xFFFF) + 0x10000; - if(((src1_data.s64 & 0x8000)-(src2_data.s64 & 0x8000)) != 0) {overflow=((src1_data.s64 & 0x8000)-(data.s64 & 0x8000))==0?0:1; } - carry = (data.s32 & 0x10000)>>16; - break; - case S32_TYPE: - data.s64 = (src1_data.s64 & 0xFFFFFFFF) - (src2_data.s64 & 0xFFFFFFFF) + 0x100000000; - if(((src1_data.s64 & 0x80000000)-(src2_data.s64 & 0x80000000)) != 0) {overflow=((src1_data.s64 & 0x80000000)-(data.s64 & 0x80000000))==0?0:1; } - carry = ((data.u64)>>32) & 0x0001; - break; - case S64_TYPE: - data.s64 = src1_data.s64 - src2_data.s64; break; - case B8_TYPE: - case U8_TYPE: - data.u64 = (src1_data.u64 & 0xFF) - (src2_data.u64 & 0xFF) + 0x100; - carry = (data.u64 & 0x100)>>8; - break; - case B16_TYPE: - case U16_TYPE: - data.u64 = (src1_data.u64 & 0xFFFF) - (src2_data.u64 & 0xFFFF) + 0x10000; - carry = (data.u64 & 0x10000)>>16; - break; - case B32_TYPE: - case U32_TYPE: - data.u64 = (src1_data.u64 & 0xFFFFFFFF) - (src2_data.u64 & 0xFFFFFFFF) + 0x100000000; - carry = (data.u64 & 0x100000000)>>32; - break; - case B64_TYPE: - case U64_TYPE: - data.u64 = src1_data.u64 - src2_data.u64; break; - case F16_TYPE: assert(0); break; - case F32_TYPE: data.f32 = src1_data.f32 - src2_data.f32; break; - case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 - src2_data.f64; break; - default: assert(0); break; - } - - thread->set_operand_value(dst,data, i_type, thread, pI, overflow, carry); -} - -void nop_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - // Do nothing -} - -void subc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void suld_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void sured_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void sust_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void suq_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } - -ptx_reg_t* ptx_tex_regs = NULL; - -union intfloat { - int a; - float b; -}; - -float reduce_precision( float x, unsigned bits ) -{ - intfloat tmp; - tmp.b = x; - int v = tmp.a; - int man = v & ((1<<23)-1); - int mask = ((1<= mx) nx -= elem_size; - unsigned ny = (y >= my)? my - 1 : y; - return nx + mx*ny; -} - -typedef unsigned (*texAddr_t) (unsigned x, unsigned y, unsigned mx, unsigned my, size_t elem_size); -float tex_linf_sampling(memory_space* mem, unsigned tex_array_base, - int x, int y, unsigned int width, unsigned int height, size_t elem_size, - float alpha, float beta, texAddr_t b_lim) -{ - float Tij; - float Ti1j; - float Tij1; - float Ti1j1; - - mem->read(tex_array_base + b_lim(x,y,width,height,elem_size), 4, &Tij); - mem->read(tex_array_base + b_lim(x+elem_size,y,width,height,elem_size), 4, &Ti1j); - mem->read(tex_array_base + b_lim(x,y+1,width,height,elem_size), 4, &Tij1); - mem->read(tex_array_base + b_lim(x+elem_size,y+1,width,height,elem_size), 4, &Ti1j1); - - float sample = (1-alpha)*(1-beta)*Tij + - alpha*(1-beta)*Ti1j + - (1-alpha)*beta*Tij1 + - alpha*beta*Ti1j1; - - return sample; -} - -float textureNormalizeElementSigned(int element, int bits) -{ - if (bits) { - int maxN = (1 << bits) - 1; - // removing upper bits - element &= maxN; - // normalizing the number to [-1.0,1.0] - maxN >>= 1; - float output = (float) element / maxN; - if (output < -1.0f) output = -1.0f; - return output; - } else { - return 0.0f; - } -} - -float textureNormalizeElementUnsigned(unsigned int element, int bits) -{ - if (bits) { - unsigned int maxN = (1 << bits) - 1; - // removing upper bits and normalizing the number to [0.0,1.0] - return (float)(element & maxN) / maxN; - } else { - return 0.0f; - } -} - -void textureNormalizeOutput( const struct cudaChannelFormatDesc& desc, ptx_reg_t& datax, ptx_reg_t& datay, ptx_reg_t& dataz, ptx_reg_t& dataw ) -{ - if (desc.f == cudaChannelFormatKindSigned) { - datax.f32 = textureNormalizeElementSigned( datax.s32, desc.x ); - datay.f32 = textureNormalizeElementSigned( datay.s32, desc.y ); - dataz.f32 = textureNormalizeElementSigned( dataz.s32, desc.z ); - dataw.f32 = textureNormalizeElementSigned( dataw.s32, desc.w ); - } else if (desc.f == cudaChannelFormatKindUnsigned) { - datax.f32 = textureNormalizeElementUnsigned( datax.u32, desc.x ); - datay.f32 = textureNormalizeElementUnsigned( datay.u32, desc.y ); - dataz.f32 = textureNormalizeElementUnsigned( dataz.u32, desc.z ); - dataw.f32 = textureNormalizeElementUnsigned( dataw.u32, desc.w ); - } else { - assert(0 && "Undefined texture read mode: cudaReadModeNormalizedFloat expect integer elements"); - } -} - -void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - unsigned dimension = pI->dimension(); - const operand_info &dst = pI->dst(); //the registers to which fetched texel will be placed - const operand_info &src1 = pI->src1(); //the name of the texture - const operand_info &src2 = pI->src2(); //the vector registers containing coordinates of the texel to be fetched - - std::string texname = src1.name(); - unsigned to_type = pI->get_type(); - unsigned c_type = pI->get_type2(); - fflush(stdout); - ptx_reg_t data1, data2, data3, data4; - if (!ptx_tex_regs) ptx_tex_regs = new ptx_reg_t[4]; - unsigned nelem = src2.get_vect_nelem(); - thread->get_vector_operand_values(src2, ptx_tex_regs, nelem); //ptx_reg should be 4 entry vector type...coordinates into texture - - gpgpu_t *gpu = thread->get_gpu(); - const struct textureReference* texref = gpu->get_texref(texname); - const struct cudaArray* cuArray = gpu->get_texarray(texref); - const struct textureInfo* texInfo = gpu->get_texinfo(texref); - const struct textureReferenceAttr* texAttr = gpu->get_texattr(texref); - - //assume always 2D f32 input - //access array with src2 coordinates - memory_space *mem = thread->get_global_memory(); - float x_f32, y_f32; - size_t size; - int t; - unsigned tex_array_base; - unsigned int width = 0, height = 0; - int x = 0; - int y = 0; - unsigned tex_array_index; - float alpha=0, beta=0; - - type_info_key::type_decode(to_type,size,t); - tex_array_base = cuArray->devPtr32; - - switch (dimension) { - case GEOM_MODIFIER_1D: - width = cuArray->width; - height = cuArray->height; - if (texref->normalized) { - assert(c_type == F32_TYPE); - x_f32 = ptx_tex_regs[0].f32; - if (texref->addressMode[0] == cudaAddressModeClamp) { - x_f32 = (x_f32 > 1.0)? 1.0 : x_f32; - x_f32 = (x_f32 < 0.0)? 0.0 : x_f32; - } else if (texref->addressMode[0] == cudaAddressModeWrap) { - x_f32 = x_f32 - floor(x_f32); - } - - if( texref->filterMode == cudaFilterModeLinear ) { - float xb = x_f32 * width - 0.5; - alpha = xb - floor(xb); - alpha = reduce_precision(alpha,9); - beta = 0.0; - - x = (int)floor(xb); - y = 0; - } else { - x = (int) floor(x_f32 * width); - y = 0; - } - } else { - switch ( c_type ) { - case S32_TYPE: - x = ptx_tex_regs[0].s32; - assert(texref->filterMode == cudaFilterModePoint); - break; - case F32_TYPE: - x_f32 = ptx_tex_regs[0].f32; - alpha = x_f32 - floor(x_f32); // offset into subtexel (for linear sampling) - x = (int) x_f32; - break; - default: assert(0 && "Unsupported texture coordinate type."); - } - // handle texture fetch that exceeded boundaries - if (texref->addressMode[0] == cudaAddressModeClamp) { - x = (x > width - 1)? (width - 1) : x; - x = (x < 0)? 0 : x; - } else if (texref->addressMode[0] == cudaAddressModeWrap) { - x = x % width; - } - } - width *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; - x *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; - tex_array_index = tex_array_base + x; - - break; - case GEOM_MODIFIER_2D: - width = cuArray->width; - height = cuArray->height; - if (texref->normalized) { - x_f32 = reduce_precision(ptx_tex_regs[0].f32,16); - y_f32 = reduce_precision(ptx_tex_regs[1].f32,15); - - if (texref->addressMode[0]) {//clamp - if (x_f32<0) x_f32 = 0; - if (x_f32>=1) x_f32 = 1 - 1/x_f32; - } else {//wrap - x_f32 = x_f32 - floor(x_f32); - } - if (texref->addressMode[1]) {//clamp - if (y_f32<0) y_f32 = 0; - if (y_f32>=1) y_f32 = 1 - 1/y_f32; - } else {//wrap - y_f32 = y_f32 - floor(y_f32); - } - - if( texref->filterMode == cudaFilterModeLinear ) { - float xb = x_f32 * width - 0.5; - float yb = y_f32 * height - 0.5; - alpha = xb - floor(xb); - beta = yb - floor(yb); - alpha = reduce_precision(alpha,9); - beta = reduce_precision(beta,9); - - x = (int)floor(xb); - y = (int)floor(yb); - } else { - x = (int) floor(x_f32 * width); - y = (int) floor(y_f32 * height); - } - } else { - x_f32 = ptx_tex_regs[0].f32; - y_f32 = ptx_tex_regs[1].f32; - - alpha = x_f32 - floor(x_f32); - beta = y_f32 - floor(y_f32); - - x = (int) x_f32; - y = (int) y_f32; - if (texref->addressMode[0]) {//clamp - if (x<0) x = 0; - if (x>= (int)width) x = width-1; - } else {//wrap - x = x % width; - if (x < 0) x*= -1; - } - if (texref->addressMode[1]) {//clamp - if (y<0) y = 0; - if (y>= (int)height) y = height -1; - } else {//wrap - y = y % height; - if (y < 0) y *= -1; - } - } - - width *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; - x *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; - tex_array_index = tex_array_base + (x + width*y); - break; - default: - assert(0); break; - } - switch ( to_type ) { - case U8_TYPE: - case U16_TYPE: - case U32_TYPE: - case B8_TYPE: - case B16_TYPE: - case B32_TYPE: - case S8_TYPE: - case S16_TYPE: - case S32_TYPE: { - unsigned long long elementOffset = 0; // offset into the next element - mem->read( tex_array_index, cuArray->desc.x/8, &data1.u32); - elementOffset += cuArray->desc.x/8; - if (cuArray->desc.y) { - mem->read( tex_array_index + elementOffset, cuArray->desc.y/8, &data2.u32); - elementOffset += cuArray->desc.y/8; - if (cuArray->desc.z) { - mem->read( tex_array_index + elementOffset, cuArray->desc.z/8, &data3.u32); - elementOffset += cuArray->desc.z/8; - if (cuArray->desc.w) - mem->read( tex_array_index + elementOffset, cuArray->desc.w/8, &data4.u32); - } - } - break; - } - case B64_TYPE: - case U64_TYPE: - case S64_TYPE: - mem->read( tex_array_index, 8, &data1.u64); - if (cuArray->desc.y) { - mem->read( tex_array_index+8, 8, &data2.u64); - if (cuArray->desc.z) { - mem->read( tex_array_index+16, 8, &data3.u64); - if (cuArray->desc.w) - mem->read( tex_array_index+24, 8, &data4.u64); - } - } - break; - case F16_TYPE: assert(0); break; - case F32_TYPE: { - if( texref->filterMode == cudaFilterModeLinear ) { - texAddr_t b_lim = wrap; - if ( texref->addressMode[0] == cudaAddressModeClamp ) { - b_lim = clamp; - } - size_t elem_size = (cuArray->desc.x + cuArray->desc.y + cuArray->desc.z + cuArray->desc.w) / 8; - size_t elem_ofst = 0; - - data1.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); - elem_ofst += cuArray->desc.x / 8; - if (cuArray->desc.y) { - data2.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); - elem_ofst += cuArray->desc.y / 8; - if (cuArray->desc.z) { - data3.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); - elem_ofst += cuArray->desc.z / 8; - if (cuArray->desc.w) - data4.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); - } - } - } else { - mem->read( tex_array_index, cuArray->desc.x/8, &data1.f32); - if (cuArray->desc.y) { - mem->read( tex_array_index+4, cuArray->desc.y/8, &data2.f32); - if (cuArray->desc.z) { - mem->read( tex_array_index+8, cuArray->desc.z/8, &data3.f32); - if (cuArray->desc.w) - mem->read( tex_array_index+12, cuArray->desc.w/8, &data4.f32); - } - } - } - } break; - case F64_TYPE: - case FF64_TYPE: - mem->read( tex_array_index, 8, &data1.f64); - if (cuArray->desc.y) { - mem->read( tex_array_index+8, 8, &data2.f64); - if (cuArray->desc.z) { - mem->read( tex_array_index+16, 8, &data3.f64); - if (cuArray->desc.w) - mem->read( tex_array_index+24, 8, &data4.f64); - } - } - break; - default: assert(0); break; - } - int x_block_coord, y_block_coord, memreqindex, blockoffset; - - switch (dimension) { - case GEOM_MODIFIER_1D: - thread->m_last_effective_address = tex_array_index; - break; - case GEOM_MODIFIER_2D: - x_block_coord = x >> (texInfo->Tx_numbits + texInfo->texel_size_numbits); - y_block_coord = y >> texInfo->Ty_numbits; - - memreqindex = ((y_block_coord*cuArray->width/texInfo->Tx)+x_block_coord)<<6; - - blockoffset = (x%(texInfo->Tx*texInfo->texel_size) + (y%(texInfo->Ty)<<(texInfo->Tx_numbits + texInfo->texel_size_numbits))); - memreqindex += blockoffset; - thread->m_last_effective_address = tex_array_base + memreqindex;//tex_array_index; - break; - default: - assert(0); - } - thread->m_last_memory_space = tex_space; - - // normalize output into floating point numbers according to the texture read mode - if (texAttr->m_readmode == cudaReadModeNormalizedFloat) { - textureNormalizeOutput(cuArray->desc, data1, data2, data3, data4); - } else { - assert(texAttr->m_readmode == cudaReadModeElementType); - } - - thread->set_vector_operand_values(dst,data1,data2,data3,data4); -} - -void txq_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void trap_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vabsdiff_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vadd_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vmad_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vmax_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vmin_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vset_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vshl_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vshr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vsub_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } - -void vote_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - static bool first_in_warp = true; - static bool and_all; - static bool or_all; - static unsigned int ballot_result; - static std::list threads_in_warp; - static unsigned last_tid; - - if( first_in_warp ) { - first_in_warp = false; - threads_in_warp.clear(); - and_all = true; - or_all = false; - ballot_result = 0; - int offset=31; - while( (offset>=0) && !pI->active(offset) ) - offset--; - assert( offset >= 0 ); - last_tid = (thread->get_hw_tid() - (thread->get_hw_tid()%pI->warp_size())) + offset; - } - - ptx_reg_t src1_data; - const operand_info &src1 = pI->src1(); - src1_data = thread->get_operand_value(src1, pI->dst(), PRED_TYPE, thread, 1); - - //predicate value was changed so the lowest bit being set means the zero flag is set. - //As a result, the value of src1_data.pred must be inverted to get proper behavior - bool pred_value = !(src1_data.pred & 0x0001); - bool invert = src1.is_neg_pred(); - - threads_in_warp.push_back(thread); - and_all &= (invert ^ pred_value); - or_all |= (invert ^ pred_value); - - // vote.ballot - if (invert ^ pred_value) { - int lane_id = thread->get_hw_tid() % pI->warp_size(); - ballot_result |= (1 << lane_id); - } - - if( thread->get_hw_tid() == last_tid ) { - if (pI->vote_mode() == ptx_instruction::vote_ballot) { - ptx_reg_t data = ballot_result; - for( std::list::iterator t=threads_in_warp.begin(); t!=threads_in_warp.end(); ++t ) { - const operand_info &dst = pI->dst(); - (*t)->set_operand_value(dst,data, pI->get_type(), (*t), pI); - } - } else { - bool pred_value = false; - - switch( pI->vote_mode() ) { - case ptx_instruction::vote_any: pred_value = or_all; break; - case ptx_instruction::vote_all: pred_value = and_all; break; - case ptx_instruction::vote_uni: pred_value = (or_all ^ and_all); break; - default: - abort(); - } - ptx_reg_t data; - data.pred = pred_value?0:1; //the way ptxplus handles the zero flag, 1 = false and 0 = true - - for( std::list::iterator t=threads_in_warp.begin(); t!=threads_in_warp.end(); ++t ) { - const operand_info &dst = pI->dst(); - (*t)->set_operand_value(dst,data, PRED_TYPE, (*t), pI); - } - } - first_in_warp = true; - } -} - -void xor_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - //the way ptxplus handles predicates: 1 = false and 0 = true - if(i_type == PRED_TYPE) - data.pred = ~(~(src1_data.pred) ^ ~(src2_data.pred)); - else - data.u64 = src1_data.u64 ^ src2_data.u64; - - thread->set_operand_value(dst,data, i_type, thread, pI); -} - -void inst_not_implemented( const ptx_instruction * pI ) -{ - printf("GPGPU-Sim PTX: ERROR (%s:%u) instruction \"%s\" not (yet) implemented\n", - pI->source_file(), - pI->source_line(), - pI->get_opcode_cstr() ); - abort(); -} - -ptx_reg_t srcOperandModifiers(ptx_reg_t opData, operand_info opInfo, operand_info dstInfo, unsigned type, ptx_thread_info *thread) -{ - ptx_reg_t result; - memory_space *mem = NULL; - size_t size; - int t; - result.u64=0; - - //complete other cases for reading from memory, such as reading from other const memory - if(opInfo.get_addr_space() == global_space) - { - mem = thread->get_global_memory(); - type_info_key::type_decode(type,size,t); - mem->read(opData.u32,size/8,&result.u64); - if( type == S16_TYPE || type == S32_TYPE ) - sign_extend(result,size,dstInfo); - } - else if(opInfo.get_addr_space() == shared_space) - { - mem = thread->m_shared_mem; - type_info_key::type_decode(type,size,t); - mem->read(opData.u32,size/8,&result.u64); - - if( type == S16_TYPE || type == S32_TYPE ) - sign_extend(result,size,dstInfo); - - } - else if(opInfo.get_addr_space() == const_space) - { - mem = thread->get_global_memory(); - type_info_key::type_decode(type,size,t); - - mem->read((opData.u32 + opInfo.get_const_mem_offset()),size/8,&result.u64); - - if( type == S16_TYPE || type == S32_TYPE ) - sign_extend(result,size,dstInfo); - } - else - { - result = opData; - } - - if(opInfo.get_operand_lohi() == 1) - { - result.u64 = result.u64 & 0xFFFF; - } - else if(opInfo.get_operand_lohi() == 2) - { - result.u64 = (result.u64>>16) & 0xFFFF; - } - - if(opInfo.get_operand_neg() == true) { - result.f32 = -result.f32; - } - - return result; -} - diff --git a/src/cuda-sim/ptx_loader.cc~ b/src/cuda-sim/ptx_loader.cc~ deleted file mode 100644 index c922b18..0000000 --- a/src/cuda-sim/ptx_loader.cc~ +++ /dev/null @@ -1,462 +0,0 @@ -// Copyright (c) 2009-2011, Tor M. Aamodt -// The University of British Columbia -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// Redistributions in binary form must reproduce the above copyright notice, this -// list of conditions and the following disclaimer in the documentation and/or -// other materials provided with the distribution. -// Neither the name of The University of British Columbia nor the names of its -// contributors may be used to endorse or promote products derived from this -// software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -#include "ptx_loader.h" -#include "ptx_ir.h" -#include "cuda-sim.h" -#include "ptx_parser.h" -#include -#include -#include -#include - -/// globals - -memory_space *g_global_mem; -memory_space *g_tex_mem; -memory_space *g_surf_mem; -memory_space *g_param_mem; -bool g_override_embedded_ptx = false; - -/// extern prototypes - -extern int ptx_parse(); -extern int ptx__scan_string(const char*); - -extern std::map get_duplicate(); - -const char *g_ptxinfo_filename; -extern int ptxinfo_parse(); -extern int ptxinfo_debug; -extern FILE *ptxinfo_in; - -static bool g_save_embedded_ptx; -bool g_keep_intermediate_files; -bool m_ptx_save_converted_ptxplus; - -bool keep_intermediate_files() {return g_keep_intermediate_files;} - -void ptx_reg_options(option_parser_t opp) -{ - option_parser_register(opp, "-save_embedded_ptx", OPT_BOOL, &g_save_embedded_ptx, - "saves ptx files embedded in binary as .ptx", - "0"); - option_parser_register(opp, "-keep", OPT_BOOL, &g_keep_intermediate_files, - "keep intermediate files created by GPGPU-Sim when interfacing with external programs", - "0"); - option_parser_register(opp, "-gpgpu_ptx_save_converted_ptxplus", OPT_BOOL, - &m_ptx_save_converted_ptxplus, - "Saved converted ptxplus to a file", - "0"); -} - -void print_ptx_file( const char *p, unsigned source_num, const char *filename ) -{ - printf("\nGPGPU-Sim PTX: file _%u.ptx contents:\n\n", source_num ); - char *s = strdup(p); - char *t = s; - unsigned n=1; - while ( *t != '\0' ) { - char *u = t; - while ( (*u != '\n') && (*u != '\0') ) u++; - unsigned last = (*u == '\0'); - *u = '\0'; - const ptx_instruction *pI = ptx_instruction_lookup(filename,n); - char pc[64]; - if( pI && pI->get_PC() ) - snprintf(pc,64,"%4u", pI->get_PC() ); - else - snprintf(pc,64," "); - printf(" _%u.ptx %4u (pc=%s): %s\n", source_num, n, pc, t ); - if ( last ) break; - t = u+1; - n++; - } - free(s); - fflush(stdout); -} - -char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptxfilename, const std::string elffilename, const std::string sassfilename) -{ - - printf("GPGPU-Sim PTX: converting EMBEDDED .ptx file to ptxplus \n"); - - char fname_ptxplus[1024]; - snprintf(fname_ptxplus,1024,"_ptxplus_XXXXXX"); - int fd4=mkstemp(fname_ptxplus); - close(fd4); - - // Run cuobjdump_to_ptxplus - char commandline[1024]; - int result; - snprintf(commandline, 1024, "$GPGPUSIM_ROOT/build/$GPGPUSIM_CONFIG/cuobjdump_to_ptxplus/cuobjdump_to_ptxplus %s %s %s %s", - ptxfilename.c_str(), - sassfilename.c_str(), - elffilename.c_str(), - fname_ptxplus); - fflush(stdout); - printf("GPGPU-Sim PTX: calling cuobjdump_to_ptxplus\ncommandline: %s\n", commandline); - result = system(commandline); - if(result){printf("GPGPU-Sim PTX: ERROR ** could not execute %s\n", commandline); exit(1);} - - - // Get ptxplus from file - std::ifstream fileStream(fname_ptxplus, std::ios::in); - std::string text, line; - while(getline(fileStream,line)) { - text += (line + "\n"); - } - fileStream.close(); - - char* ptxplus_str = new char [strlen(text.c_str())+1]; - strcpy(ptxplus_str, text.c_str()); - - if (!m_ptx_save_converted_ptxplus){ - char rm_commandline[1024]; - - snprintf(rm_commandline,1024,"rm -f %s", fname_ptxplus); - - printf("GPGPU-Sim PTX: removing temporary files using \"%s\"\n", rm_commandline); - int rm_result = system(rm_commandline); - if( rm_result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while removing temporary files %d\n", rm_result); - exit(1); - } - } - printf("GPGPU-Sim PTX: DONE converting EMBEDDED .ptx file to ptxplus \n"); - - return ptxplus_str; -} - - -symbol_table *gpgpu_ptx_sim_load_ptx_from_string( const char *p, unsigned source_num ) -{ - char buf[1024]; - snprintf(buf,1024,"_%u.ptx", source_num ); - if( g_save_embedded_ptx ) { - FILE *fp = fopen(buf,"w"); - fprintf(fp,"%s",p); - fclose(fp); - } - symbol_table *symtab=init_parser(buf); - ptx__scan_string(p); - int errors = ptx_parse (); - if ( errors ) { - char fname[1024]; - snprintf(fname,1024,"_ptx_errors_XXXXXX"); - int fd=mkstemp(fname); - close(fd); - printf("GPGPU-Sim PTX: parser error detected, exiting... but first extracting .ptx to \"%s\"\n", fname); - FILE *ptxfile = fopen(fname,"w"); - fprintf(ptxfile,"%s", p ); - fclose(ptxfile); - abort(); - exit(40); - } - - //if ( g_debug_execution >= 100 ) - print_ptx_file(p,source_num,buf); - - printf("GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file %s\n",buf); - return symtab; -} - -void fix_duplicate_errors(char fname2[1024]) { - char tempfile[1024] = "_temp_ptx"; - char commandline[1024]; - - // change the name of the ptx file to _temp_ptx - snprintf(commandline,1024,"mv %s %s",fname2,tempfile); - printf("Running: %s\n", commandline); - int result = system(commandline); - if (result != 0) { - printf("GPGPU-Sim PTX: ERROR ** while changing filename from %s to %s", fname2, tempfile); - exit(1); - } - - // store all of the ptx into a char array - FILE *ptxsource = fopen(tempfile,"r"); - fseek(ptxsource, 0, SEEK_END); - long filesize = ftell(ptxsource); - rewind(ptxsource); - char *ptxdata = (char*)malloc((filesize+1)*sizeof(char)); - fread(ptxdata, filesize, 1, ptxsource); - fclose(ptxsource); - - FILE *ptxdest = fopen(fname2,"w"); - std::map duplicate = get_duplicate(); - unsigned offset; - unsigned oldlinenum = 1; - unsigned linenum; - char *startptr = ptxdata; - char *funcptr; - char *tempptr = ptxdata - 1; - char *lineptr = ptxdata - 1; - - // recreate the ptx file without duplications - for ( std::map::iterator iter = duplicate.begin(); - iter != duplicate.end(); - iter++){ - // find the line of the next error - linenum = iter->first; - for (int i = oldlinenum; i < linenum; i++) { - lineptr = strchr(lineptr + 1, '\n'); - } - - // find the end of the current section to be copied over - // then find the start of the next section that will be copied - if (strcmp("function", iter->second) == 0) { - // get location of most recent .func - while (tempptr < lineptr && tempptr != NULL) { - funcptr = tempptr; - tempptr = strstr(funcptr + 1, ".func"); - } - - // get the start of the previous line - offset = 0; - while (*(funcptr - offset) != '\n') offset++; - - fwrite(startptr, sizeof(char), funcptr - offset + 1 - startptr, ptxdest); - - //find next location of startptr - if (*(lineptr + 3) == ';') { - // for function definitions - startptr = lineptr + 5; - } else if (*(lineptr + 3) == '{') { - // for functions enclosed with curly brackets - offset = 5; - unsigned bracket = 1; - while (bracket != 0) { - if (*(lineptr + offset) == '{') bracket++; - else if (*(lineptr + offset) == '}') bracket--; - offset++; - } - startptr = lineptr + offset + 1; - } else { - printf("GPGPU-Sim PTX: ERROR ** Unrecognized function format\n"); - abort(); - } - } else if (strcmp("variable", iter->second) == 0) { - fwrite(startptr, sizeof(char), (int)(lineptr + 1 - startptr), ptxdest); - - //find next location of startptr - offset = 1; - while (*(lineptr + offset) != '\n') offset++; - startptr = lineptr + offset + 1; - } else { - printf("GPGPU-Sim PTX: ERROR ** Unsupported duplicate type: %s\n", iter->second); - } - - oldlinenum = linenum; - } - // copy over the rest of the file - fwrite(startptr, sizeof(char), ptxdata + filesize - startptr, ptxdest); - - // cleanup - free(ptxdata); - fclose(ptxdest); - snprintf(commandline,1024,"rm -f %s",tempfile); - printf("Running: %s\n", commandline); - result = system(commandline); - if (result != 0) { - printf("GPGPU-Sim PTX: ERROR ** while deleting %s", tempfile); - exit(1); - } -} - -//we need the application name here too. -char* get_app_binary_name(){ - char exe_path[1025]; - char *self_exe_path; -#ifdef __APPLE__ - //AMRUTH: get apple device and check the result. - printf("WARNING: not tested for Apple-mac devices \n"); - abort(); -#else - std::stringstream exec_link; - exec_link << "/proc/self/exe"; - ssize_t path_length = readlink(exec_link.str().c_str(), exe_path, 1024); - assert(path_length != -1); - exe_path[path_length] = '\0'; - - char *token = strtok(exe_path, "/"); - while(token !=NULL){ - self_exe_path = token; - token = strtok(NULL,"/"); - } -#endif - self_exe_path = strtok(self_exe_path, "."); - printf("self exe links to: %s\n", self_exe_path); - return self_exe_path; -} - -void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version ) -{ - //do ptxas for individual files instead of one big embedded ptx. This prevents the duplicate defs and declarations. - char ptx_file[1000]; - char *name=get_app_binary_name(); - char commandline[4096], fname[1024], fname2[1024], final_tempfile_ptxinfo[1024], tempfile_ptxinfo[1024]; - for (int index=1; index <= no_of_ptx; index++){ - snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", name, index, sm_version); - snprintf(fname,1024,"_ptx_XXXXXX"); - int fd=mkstemp(fname); - close(fd); - - printf("GPGPU-Sim PTX: extracting embedded .ptx to temporary file \"%s\"\n", fname); - snprintf(commandline,4096,"cat %s > %s",ptx_file, fname); - if (system(commandline) !=0) { - printf("ERROR: %s command failed\n", commandline); - exit(0); - } - - snprintf(fname2,1024,"_ptx2_XXXXXX"); - fd=mkstemp(fname2); - close(fd); - char commandline2[4096]; - snprintf(commandline2,4096,"cat %s | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\\(\\.extern \\.const\\[1\\] .b8 \\w\\+\\)\\[\\]/\\1\\[1\\]/' | sed 's/const\\[.\\]/const\\[0\\]/g' > %s", fname, fname2); - printf("Running: %s\n", commandline2); - int result = system(commandline2); - if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); - printf(" Ensure you have write access to simulation directory\n"); - printf(" and have \'cat\' and \'sed\' in your path.\n"); - exit(1); - } - - snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); - char extra_flags[1024]; - extra_flags[0]=0; - - #if CUDART_VERSION >= 3000 - if (sm_version == 0) sm_version = 20; - extern bool g_cdp_enabled; - if(!g_cdp_enabled) - snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); - else - snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version); - #endif - - snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", - extra_flags, fname2, tempfile_ptxinfo); - printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); - result = system(commandline); - if( result != 0 ) { - // 65280 = duplicate errors - if (result == 65280) { - ptxinfo_in = fopen(tempfile_ptxinfo,"r"); - g_ptxinfo_filename = tempfile_ptxinfo; - ptxinfo_parse(); - - fix_duplicate_errors(fname2); - snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", - extra_flags, fname2, tempfile_ptxinfo); - printf("GPGPU-Sim PTX: regenerating ptxinfo using \"%s\"\n", commandline); - result = system(commandline); - } - if (result != 0) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); - printf(" Ensure ptxas is in your path.\n"); - exit(1); - } - } - } - - //TODO: duplicate code! move it into a function so that it can be reused! - if(no_of_ptx==0) { - //For CDP, we dump everything. So no_of_ptx will be 0. - snprintf(fname,1024,"_ptx_XXXXXX"); - int fd=mkstemp(fname); - close(fd); - - printf("GPGPU-Sim PTX: extracting embedded .ptx to temporary file \"%s\"\n", fname); - FILE *ptxfile = fopen(fname,"w"); - fprintf(ptxfile,"%s", p_for_info); - fclose(ptxfile); - - snprintf(fname2,1024,"_ptx2_XXXXXX"); - fd=mkstemp(fname2); - close(fd); - char commandline2[4096]; - snprintf(commandline2,4096,"cat %s | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\\(\\.extern \\.const\\[1\\] .b8 \\w\\+\\)\\[\\]/\\1\\[1\\]/' | sed 's/const\\[.\\]/const\\[0\\]/g' > %s", fname, fname2); - printf("Running: %s\n", commandline2); - int result = system(commandline2); - if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); - printf(" Ensure you have write access to simulation directory\n"); - printf(" and have \'cat\' and \'sed\' in your path.\n"); - exit(1); - } - //char tempfile_ptxinfo[1024]; - snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); - char extra_flags[1024]; - extra_flags[0]=0; -#if CUDART_VERSION >= 3000 - snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); -#endif - - snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", - extra_flags, fname2, tempfile_ptxinfo); - printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); - result = system(commandline); - if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); - printf(" Ensure ptxas is in your path.\n"); - exit(1); - } - } - - //Now that we got resource usage per kernel in a ptx file, we dump all into one file and pass it to rest of the code as usual. - if(no_of_ptx>0){ - char commandline3[4096]; - snprintf(final_tempfile_ptxinfo,1024,"f_tempfile_ptx"); - snprintf(commandline3,4096, "cat *info > %s", final_tempfile_ptxinfo); - if (system(commandline3)!=0) { - printf("ERROR: Either we dont have info files or cat is not working \n"); - printf("ERROR: %s command failed\n",commandline3); - exit(1); - } - } - - ptxinfo_in = fopen(final_tempfile_ptxinfo,"r"); - if(no_of_ptx>0) - g_ptxinfo_filename = final_tempfile_ptxinfo; - else - g_ptxinfo_filename = tempfile_ptxinfo; - ptxinfo_parse(); - - if( ! g_save_embedded_ptx ) { - if(no_of_ptx>0) - snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, final_tempfile_ptxinfo); - else - snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, tempfile_ptxinfo); - printf("GPGPU-Sim PTX: removing ptxinfo using \"%s\"\n", commandline); - if( system(commandline) != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while removing temporary files\n"); - exit(1); - } - } -} -- cgit v1.3 From 31ad7674de6dc4b25ba862bcd00b660fdb1a5cff Mon Sep 17 00:00:00 2001 From: Amruth Date: Wed, 4 Apr 2018 13:44:10 -0700 Subject: adding missing ptxas flags for cdp support --- README | 66 +++++++++++++++++++++++++++++++++++++++++++++ libcuda/cuda_runtime_api.cc | 4 +-- src/cuda-sim/ptx_loader.cc | 27 ++++++++++++------- 3 files changed, 85 insertions(+), 12 deletions(-) diff --git a/README b/README index 6e2d734..4426cdd 100644 --- a/README +++ b/README @@ -346,3 +346,69 @@ the applications you care about (implying these applications worked for you before you did the merge). You want to do this before making further changes to identify any compile time or runtime errors that occur due to the code merging process. + + +** Debugging failing GPGPU-Sim Regressions ** + +To debug failing GPGPU-Sim regression tests you need to run them locally. The fastest way to do this, assuming you are working with GPGPU-Sim versions more recent than the GPGPU-Sim dev branch circa March 28, 2018 (commit hash 2221d208a745a098a60b0d24c05007e92aaba092), is to install Docker. The instructions below were tested with Docker CE version 18.03 on Ubuntu and Mac OS. Docker will enable you to run the same set of regressions used by GPGPU-Sim when submitting a pull request to https://github.com/gpgpu-sim/gpgpu-sim_distribution and also allow you to log in and launch GPGPU-Sim in gdb so you can inspect failures. + +1. Install Docker. On Ubuntu 14.04 and 16.04 the following instructions work: https://docs.docker.com/install/linux/docker-ce/ubuntu/#uninstall-old-versions + +2. Clone GPGPU-Sim from your fork of GPGPU-Sim. For example: + + git clone https://github.com//gpgpu-sim_distribution.git + + +3. Run the following command (this is all one line) to run the regressions in docker: + + docker run --privileged -v `pwd`:/home/runner/gpgpu-sim_distribution:rw aamodt/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.gtx1080ti.yml -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress’; tail -f /dev/null" + +Explanation: The last part of this command, "tail -f /dev/null" will keep the docker container running after the regressions finish. This enables you to log into the container to run the same tests inside gdb so you can debug. The "--privileged" part enables you to use breakpoints inside gdb in a container. The "-v" part maps the current directory (with the GPGPU-Sim source code you want to test) into the container. The string "aamodt/gpgpu-sim_regress:latest" is a tag for a container setup to run regressions which will be downloaded from docker hub. The portion starting with /bin/bash is a set of commands run inside a bash shell inside the container. E.g., the command start_torque.sh starts up a queue manager inside the container. + +If the above command stops with the message "fatal: unable to access 'https://github.com/tgrogers/gpgpu-sim_simulations.git/': Could not resolve host: github.com" this likely means your computer sits behind a firewall which is blocking access to Google's name servers (e.g., 8.8.8.8). To get around this you will need to modify th above command to point to your local DNS server. Lookup your DNS server IP address which we will call below. On Ubuntu run "ifconfig" to lookup the network interface connecting your computer to the network. Then run "nmcli device show " to find the IP address of your DNS server. Modify the above command to include "--dns " after "run", E.g., + + docker run --dns --privileged -v `pwd`:/home/runner/gpgpu-sim_distribution:rw aamodt/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.gtx1080ti.yml -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress’; tail -f /dev/null" + +4. Find the CONTAINER ID associated with your docker container by running "docker ps". + +5. Log into the container by running the command: + + docker exec -it /bin/bash -c "su -l runner" + +The container is running Ubuntu 16.04 and has screen, cscope and vim installed (if you find a favorite Linux tool missing, it is fairly easy to create derived containers that have additional tools). + +6. Lookup the directory of the regression test you want to debug by going to the regression log file directory: + + cd /home/runner/gpgpu-sim_simulations/util/job_launching/logfiles + +7. The file "failed_job_log_sim_log.regress..txt" includes information about the failed test including its simulation directory. For the following example, I'll assume the first failing test was "hotspot-rodinia-2.0-ft-30_6_40___data_result_30_6_40_txt--GTX1080Ti" for which the simulation directory is /home/runner/gpgpu-sim_simulations/util/job_launching/../../sim_run_4.2/hotspot-rodinia-2.0-ft/30_6_40___data_result_30_6_40_txt/GTX1080Ti/ + +8. Change to the simulation directory using: + + cd + +E.g., "cd /home/runner/gpgpu-sim_simulations/util/job_launching/../../sim_run_4.2/hotspot-rodinia-2.0-ft/30_6_40___data_result_30_6_40_txt/GTX1080Ti/" + +This directory should contain a file called "torque.sim" that contains commands used to launch the simulation during regression tests. We will modify this file to enable us to re-run the regression test in gdb. This directory should also contain a file containing the standard output during the regression test. This file will end in .o where is the torque queue manager job number. For the running example for me this file is called "hotspot-rodinia-2.0-ft-30_6_40___data_result_30_6_40_txt.o2". Open this file to determine the LD_LIBRARY_PATH settings used when launching the simulation. Look for a line that starts "doing: export LD_LIBRARY_PATH" and copy the entire line starting with "export LD_LIBRARY_PATH ..." + +9. Paste the "export LD_LIBRARY_PATH ..." line into the bash shell to set LD_LIBRARY_PATH. E.g., + + export LD_LIBRARY_PATH=/home/runner/gpgpu-sim_simulations/util/job_launching/../../sim_run_4.2/gpgpu-sim-builds/libcudart_gpgpu-sim_git-commit-177d02254ae38b6331b17dd6cd139b570a03c589_modified_0.so:/gpgpu-sim/usr/local/gcc-4.5.4/lib64:/gpgpu-sim/usr/local/gcc-4.5.4/lib:/gpgpu-sim/usr/local/gcc-4.5.4/lib/gcc/x86_64-unknown-linux-gnu/lib64/:/gpgpu-sim/usr/local/gcc-4.5.4/lib/gcc/x86_64-unknown-linux-gnu/4.5.4/:/usr/lib/x86_64-linux-gnu:/home/runner/gpgpu-sim_distribution/lib/gcc-4.5.4/cuda-4020/release:/gpgpu-sim/usr/local/gcc-4.5.4/lib64:/gpgpu-sim/usr/local/gcc-4.5.4/lib:/gpgpu-sim/usr/local/gcc-4.5.4/lib/gcc/x86_64-unknown-linux-gnu/lib64/:/gpgpu-sim/usr/local/gcc-4.5.4/lib/gcc/x86_64-unknown-linux-gnu/4.5.4/:/usr/lib/x86_64-linux-gnu: + +10. In the same shell, build the debug version of GPGPU-Sim then return to the directory above: + + pushd ~/gpgpu-sim_distribution/ + source setup_environment debug + make + popd + +11. Open and edit torque.sim and preface the very last line with "gdb --args ". After editing the last line in torque.sim should look something like: + + gdb --args /home/runner/gpgpu-sim_simulations/util/job_launching/../../benchmarks/bin/4.2/release/hotspot-rodinia-2.0-ft 30 6 40 ./data/result_30_6_40.txt + +12. Re-run the regression test in gdb by sourcing the torque.sim file: + + . torque.sim + +This will put you in at the (gdb) prompt. Setup any breakpoints needed and run. + diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index ded1aee..c103244 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1085,8 +1085,8 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetStreamPriorityRange(int* leastPriori return cudaSuccess; } -__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *pStream, unsigned int flags) { - return cudaStreamCreate(pStream); +__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *stream, unsigned int flags) { + return cudaStreamCreate(stream); } __host__ cudaError_t CUDARTAPI cudaStreamDestroy(cudaStream_t stream) diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 34870c4..7863be4 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -353,11 +353,7 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num #if CUDART_VERSION >= 3000 if (sm_version == 0) sm_version = 20; - extern bool g_cdp_enabled; - if(!g_cdp_enabled) - snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); - else - snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version); + snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); #endif snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", @@ -414,9 +410,15 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); char extra_flags[1024]; extra_flags[0]=0; -#if CUDART_VERSION >= 3000 - snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); -#endif + + #if CUDART_VERSION >= 3000 + if (sm_version == 0) sm_version = 20; + extern bool g_cdp_enabled; + if(!g_cdp_enabled) + snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); + else + snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version); + #endif snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", extra_flags, fname2, tempfile_ptxinfo); @@ -448,11 +450,16 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num g_ptxinfo_filename = tempfile_ptxinfo; ptxinfo_parse(); + snprintf(commandline,1024,"rm -f *info"); + if( system(commandline) != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while removing temporary info files\n"); + exit(1); + } if( ! g_save_embedded_ptx ) { if(no_of_ptx>0) - snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, final_tempfile_ptxinfo); + snprintf(commandline,1024,"rm -f %s %s %s", fname, fname2, final_tempfile_ptxinfo); else - snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, tempfile_ptxinfo); + snprintf(commandline,1024,"rm -f %s %s %s", fname, fname2, tempfile_ptxinfo); printf("GPGPU-Sim PTX: removing ptxinfo using \"%s\"\n", commandline); if( system(commandline) != 0 ) { printf("GPGPU-Sim PTX: ERROR ** while removing temporary files\n"); -- cgit v1.3 From 335bb4b38974b1843e1786c5d86b0fcf2a7943c8 Mon Sep 17 00:00:00 2001 From: Amruth Date: Wed, 4 Apr 2018 16:01:32 -0700 Subject: Prog gets stuck because it doesnt recieve EOF --- src/cuda-sim/ptx_loader.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 7863be4..03ea31a 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -448,6 +448,9 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num g_ptxinfo_filename = final_tempfile_ptxinfo; else g_ptxinfo_filename = tempfile_ptxinfo; + + //The program might get stuck because the parser didnt receive a EOF. + printf("NOTE: If the program is stuck, please press ctrl+d for ubuntu and ctrl+z for windows users \n"); ptxinfo_parse(); snprintf(commandline,1024,"rm -f *info"); -- cgit v1.3 From 69c57b077d6799f46ad43b99cc0e0049b7c43775 Mon Sep 17 00:00:00 2001 From: Amruth Date: Wed, 4 Apr 2018 16:06:42 -0700 Subject: updating EOF condition for Mac users --- src/cuda-sim/ptx_loader.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 03ea31a..4ddc6bf 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -450,7 +450,7 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num g_ptxinfo_filename = tempfile_ptxinfo; //The program might get stuck because the parser didnt receive a EOF. - printf("NOTE: If the program is stuck, please press ctrl+d for ubuntu and ctrl+z for windows users \n"); + printf("NOTE: If the program is stuck, please press ctrl+d for Ubuntu/Mac and ctrl+z for Windows users \n"); ptxinfo_parse(); snprintf(commandline,1024,"rm -f *info"); -- cgit v1.3 From 49429d3b01dcb5bac49b71df2156bceb70b64ce9 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Thu, 5 Apr 2018 10:10:15 -0400 Subject: GPGPU-Sim should always print when the sim thread exits - if this doesn't happen, something bad has happened --- src/gpgpusim_entrypoint.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index dac9fd8..64962ab 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -165,10 +165,10 @@ void *gpgpu_sim_thread_concurrent(void*) g_sim_active = false; pthread_mutex_unlock(&g_sim_lock); } while( !g_sim_done ); - if(g_debug_execution >= 3) { - printf("GPGPU-Sim: *** simulation thread exiting ***\n"); - fflush(stdout); - } + + printf("GPGPU-Sim: *** simulation thread exiting ***\n"); + fflush(stdout); + if(break_limit) { printf("GPGPU-Sim: ** break due to reaching the maximum cycles (or instructions) **\n"); exit(1); -- cgit v1.3 From 60a32420caa0e79c7d5133ff67a55c02333b1dc2 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 28 Mar 2018 14:00:16 -0400 Subject: adding new counters for parition level para and L2 BW --- src/gpgpu-sim/gpu-sim.cc | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 0ef267d..95951a8 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -88,6 +88,12 @@ unsigned long long gpu_tot_sim_cycle = 0; // performance counter for stalls due to congestion. unsigned int gpu_stall_dramfull = 0; unsigned int gpu_stall_icnt2sh = 0; +unsigned long long partiton_reqs_in_parallel = 0; +unsigned long long partiton_reqs_in_parallel_total = 0; +unsigned long long partiton_reqs_in_parallel_util = 0; +unsigned long long partiton_reqs_in_parallel_util_total = 0; +unsigned long long partiton_replys_in_parallel = 0; +unsigned long long partiton_replys_in_parallel_total = 0; /* Clock Domains */ @@ -745,6 +751,9 @@ void gpgpu_sim::init() gpu_sim_insn = 0; last_gpu_sim_insn = 0; m_total_cta_launched=0; + partiton_reqs_in_parallel = 0; + partiton_replys_in_parallel = 0; + partiton_reqs_in_parallel_util = 0; reinit_clock_domains(); set_param_gpgpu_num_shaders(m_config.num_shader()); @@ -781,8 +790,14 @@ void gpgpu_sim::update_stats() { gpu_tot_sim_cycle += gpu_sim_cycle; gpu_tot_sim_insn += gpu_sim_insn; gpu_tot_issued_cta += m_total_cta_launched; + partiton_reqs_in_parallel_total += partiton_reqs_in_parallel; + partiton_replys_in_parallel_total += partiton_replys_in_parallel; + partiton_reqs_in_parallel_util_total += partiton_reqs_in_parallel_util; gpu_sim_cycle = 0; + partiton_reqs_in_parallel = 0; + partiton_replys_in_parallel = 0; + partiton_reqs_in_parallel_util = 0; gpu_sim_insn = 0; m_total_cta_launched = 0; } @@ -966,6 +981,19 @@ void gpgpu_sim::gpu_print_stat() printf("gpu_stall_dramfull = %d\n", gpu_stall_dramfull); printf("gpu_stall_icnt2sh = %d\n", gpu_stall_icnt2sh ); + printf("partiton_reqs_in_parallel = %lld\n", partiton_reqs_in_parallel); + printf("partiton_reqs_in_parallel_total = %lld\n", partiton_reqs_in_parallel_total ); + printf("partiton_level_parallism = %12.4f\n", (float)partiton_reqs_in_parallel / gpu_sim_cycle); + printf("partiton_level_parallism_total = %12.4f\n", (float)(partiton_reqs_in_parallel+partiton_reqs_in_parallel_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); + printf("partiton_reqs_in_parallel_util = %lld\n", partiton_reqs_in_parallel_util); + printf("partiton_reqs_in_parallel_util_total = %lld\n", partiton_reqs_in_parallel_util_total ); + printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle); + printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); + printf("partiton_replys_in_parallel = %lld\n", partiton_replys_in_parallel); + printf("partiton_replys_in_parallel_total = %lld\n", partiton_replys_in_parallel_total ); + printf("L2_BW = %12.4f GB/Sec\n", ((float)(partiton_replys_in_parallel * 32) / (gpu_sim_cycle * m_config.icnt_period)) / 1000000000); + printf("L2_BW_total = %12.4f GB/Sec\n", ((float)((partiton_replys_in_parallel+partiton_replys_in_parallel_total) * 32) / ((gpu_tot_sim_cycle+gpu_sim_cycle) * m_config.icnt_period)) / 1000000000 ); + time_t curr_time; time(&curr_time); unsigned long long elapsed_time = MAX( curr_time - g_simulation_starttime, 1 ); @@ -1367,6 +1395,7 @@ void gpgpu_sim::cycle() for (unsigned i=0;in_simt_clusters;i++) m_cluster[i]->icnt_cycle(); } + unsigned partiton_replys_in_parallel_per_cycle = 0; if (clock_mask & ICNT) { // pop from memory controller to interconnect for (unsigned i=0;im_n_mem_sub_partition;i++) { @@ -1379,6 +1408,7 @@ void gpgpu_sim::cycle() mf->set_status(IN_ICNT_TO_SHADER,gpu_sim_cycle+gpu_tot_sim_cycle); ::icnt_push( m_shader_config->mem2device(i), mf->get_tpc(), mf, response_size ); m_memory_sub_partition[i]->pop(); + partiton_replys_in_parallel_per_cycle++; } else { gpu_stall_icnt2sh++; } @@ -1387,6 +1417,7 @@ void gpgpu_sim::cycle() } } } + partiton_replys_in_parallel += partiton_replys_in_parallel_per_cycle; if (clock_mask & DRAM) { for (unsigned i=0;im_n_mem;i++){ @@ -1399,6 +1430,7 @@ void gpgpu_sim::cycle() } // L2 operations follow L2 clock domain + unsigned partiton_reqs_in_parallel_per_cycle = 0; if (clock_mask & L2) { m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].clear(); for (unsigned i=0;im_n_mem_sub_partition;i++) { @@ -1409,11 +1441,15 @@ void gpgpu_sim::cycle() } else { mem_fetch* mf = (mem_fetch*) icnt_pop( m_shader_config->mem2device(i) ); m_memory_sub_partition[i]->push( mf, gpu_sim_cycle + gpu_tot_sim_cycle ); + partiton_reqs_in_parallel_per_cycle++; } m_memory_sub_partition[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle); m_memory_sub_partition[i]->accumulate_L2cache_stats(m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX]); } } + partiton_reqs_in_parallel += partiton_reqs_in_parallel_per_cycle; + if(partiton_reqs_in_parallel_per_cycle > 0) + partiton_reqs_in_parallel_util += partiton_reqs_in_parallel_per_cycle; if (clock_mask & ICNT) { icnt_transfer(); -- cgit v1.3 From 038df10118351d44f8950065ddeb698ae3e390a1 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 28 Mar 2018 15:22:33 -0400 Subject: adding new stats counter --- src/gpgpu-sim/gpu-sim.cc | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 95951a8..da35dc3 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -92,6 +92,8 @@ unsigned long long partiton_reqs_in_parallel = 0; unsigned long long partiton_reqs_in_parallel_total = 0; unsigned long long partiton_reqs_in_parallel_util = 0; unsigned long long partiton_reqs_in_parallel_util_total = 0; +unsigned long long gpu_sim_cycle_parition_util = 0; +unsigned long long gpu_tot_sim_cycle_parition_util = 0; unsigned long long partiton_replys_in_parallel = 0; unsigned long long partiton_replys_in_parallel_total = 0; @@ -754,6 +756,7 @@ void gpgpu_sim::init() partiton_reqs_in_parallel = 0; partiton_replys_in_parallel = 0; partiton_reqs_in_parallel_util = 0; + gpu_sim_cycle_parition_util = 0; reinit_clock_domains(); set_param_gpgpu_num_shaders(m_config.num_shader()); @@ -793,11 +796,14 @@ void gpgpu_sim::update_stats() { partiton_reqs_in_parallel_total += partiton_reqs_in_parallel; partiton_replys_in_parallel_total += partiton_replys_in_parallel; partiton_reqs_in_parallel_util_total += partiton_reqs_in_parallel_util; + gpu_tot_sim_cycle_parition_util += gpu_sim_cycle_parition_util ; gpu_sim_cycle = 0; partiton_reqs_in_parallel = 0; partiton_replys_in_parallel = 0; partiton_reqs_in_parallel_util = 0; + gpu_sim_cycle_parition_util = 0; + gpu_tot_sim_cycle = 0; gpu_sim_insn = 0; m_total_cta_launched = 0; } @@ -987,8 +993,10 @@ void gpgpu_sim::gpu_print_stat() printf("partiton_level_parallism_total = %12.4f\n", (float)(partiton_reqs_in_parallel+partiton_reqs_in_parallel_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); printf("partiton_reqs_in_parallel_util = %lld\n", partiton_reqs_in_parallel_util); printf("partiton_reqs_in_parallel_util_total = %lld\n", partiton_reqs_in_parallel_util_total ); - printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle); - printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); + printf("gpu_sim_cycle_parition_util = %lld\n", gpu_sim_cycle_parition_util); + printf("gpu_tot_sim_cycle_parition_util = %lld\n", gpu_tot_sim_cycle_parition_util ); + printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle_parition_util); + printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_sim_cycle_parition_util+gpu_tot_sim_cycle_parition_util) ); printf("partiton_replys_in_parallel = %lld\n", partiton_replys_in_parallel); printf("partiton_replys_in_parallel_total = %lld\n", partiton_replys_in_parallel_total ); printf("L2_BW = %12.4f GB/Sec\n", ((float)(partiton_replys_in_parallel * 32) / (gpu_sim_cycle * m_config.icnt_period)) / 1000000000); @@ -1448,8 +1456,10 @@ void gpgpu_sim::cycle() } } partiton_reqs_in_parallel += partiton_reqs_in_parallel_per_cycle; - if(partiton_reqs_in_parallel_per_cycle > 0) + if(partiton_reqs_in_parallel_per_cycle > 0){ partiton_reqs_in_parallel_util += partiton_reqs_in_parallel_per_cycle; + gpu_sim_cycle_parition_util++; + } if (clock_mask & ICNT) { icnt_transfer(); -- cgit v1.3 From cfab001e7c65541eaf8f7573bbf4a2e5d69f296e Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Fri, 30 Mar 2018 11:27:57 -0400 Subject: fixing gpu-tot-cycle bug --- src/gpgpu-sim/gpu-sim.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index da35dc3..550c550 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -803,7 +803,6 @@ void gpgpu_sim::update_stats() { partiton_replys_in_parallel = 0; partiton_reqs_in_parallel_util = 0; gpu_sim_cycle_parition_util = 0; - gpu_tot_sim_cycle = 0; gpu_sim_insn = 0; m_total_cta_launched = 0; } -- cgit v1.3 From 913c8934d89068ea96729b238a42879d2e02e7f4 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Thu, 5 Apr 2018 11:27:17 -0400 Subject: Nice to know when the simulaton thread actually gets the exit call under normal operation. This helps immensely in a clustered environmrnt where jobs randomly fail --- src/gpgpusim_entrypoint.cc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index 64962ab..ede9f20 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -93,8 +93,15 @@ bool g_sim_active = false; bool g_sim_done = true; bool break_limit = false; +static void termination_callback() +{ + printf("GPGPU-Sim: *** exit detected ***\n"); + fflush(stdout); +} + void *gpgpu_sim_thread_concurrent(void*) { + atexit(termination_callback); // concurrent kernel execution simulation thread do { if(g_debug_execution >= 3) { @@ -165,7 +172,6 @@ void *gpgpu_sim_thread_concurrent(void*) g_sim_active = false; pthread_mutex_unlock(&g_sim_lock); } while( !g_sim_done ); - printf("GPGPU-Sim: *** simulation thread exiting ***\n"); fflush(stdout); -- cgit v1.3 From e1dc8113aa2a51885541f96943bd8d90eaccd968 Mon Sep 17 00:00:00 2001 From: Amruth Date: Thu, 5 Apr 2018 16:31:44 -0700 Subject: fixing file pointer and attributes issues --- README | 1 + libcuda/cuda_runtime_api.cc | 34 ++++++++++++++++++++++++++++++++-- src/cuda-sim/cuda-sim.cc | 1 + src/cuda-sim/ptx_loader.cc | 5 ++--- 4 files changed, 36 insertions(+), 5 deletions(-) diff --git a/README b/README index 4426cdd..543177c 100644 --- a/README +++ b/README @@ -349,6 +349,7 @@ process. ** Debugging failing GPGPU-Sim Regressions ** +Credits: Tor M Aamodt To debug failing GPGPU-Sim regression tests you need to run them locally. The fastest way to do this, assuming you are working with GPGPU-Sim versions more recent than the GPGPU-Sim dev branch circa March 28, 2018 (commit hash 2221d208a745a098a60b0d24c05007e92aaba092), is to install Docker. The instructions below were tested with Docker CE version 18.03 on Ubuntu and Mac OS. Docker will enable you to run the same set of regressions used by GPGPU-Sim when submitting a pull request to https://github.com/gpgpu-sim/gpgpu-sim_distribution and also allow you to log in and launch GPGPU-Sim in gdb so you can inspect failures. diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index c103244..3fd88dc 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -349,7 +349,15 @@ class _cuda_device_id *GPGPUSim_Init() prop->maxGridSize[2] = 0x40000000; prop->totalConstMem = 0x40000000; prop->textureAlignment = 0; - prop->sharedMemPerBlock = the_gpu->shared_mem_size(); + /* + * TODO: Update the .config and xml files of all GPU config files with new value of sharedMemPerBlock. + * Previously, this was thought as sharedMemPerMultiprocessor and is being used in many places. + * Check whether all the instances of shared_mem_size(), gpgpu_shmem_size or sharedMemPerBlock are meant to use sharedMemPerBlock or sharedMemPerMultiprocessor. + */ + prop->sharedMemPerBlock = 49152; +#if (CUDART_VERSION > 5000) + prop->sharedMemPerMultiprocessor = the_gpu->shared_mem_size(); +#endif prop->regsPerBlock = the_gpu->num_registers_per_core(); prop->warpSize = the_gpu->wrp_size(); prop->clockRate = the_gpu->shader_clock(); @@ -840,6 +848,15 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic if (device <= dev->num_devices() ) { prop = dev->get_prop(); switch (attr) { + case 2: + *value= prop->maxThreadsDim[0]; + break; + case 3: + *value= prop->maxThreadsDim[1]; + break; + case 4: + *value= prop->maxThreadsDim[2]; + break; case 5: *value= prop->maxGridSize[0]; break; @@ -849,6 +866,12 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 7: *value= prop->maxGridSize[2]; break; + case 8: + *value= prop->sharedMemPerBlock; + break; + case 9: + *value= prop->totalConstMem; + break; case 10: *value= prop->warpSize; break; @@ -861,11 +884,14 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 16: *value= prop->multiProcessorCount ; break; + case 34: + *value= 0; + break; case 39: *value= dev->get_gpgpu()->threads_per_core(); break; case 75: - *value= 8 ; + *value= 9 ; break; case 76: *value= 3 ; @@ -873,6 +899,9 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 78: *value= 0 ; //TODO: as of now, we dont support stream priorities. break; + case 81: + *value= prop->sharedMemPerMultiprocessor; + break; default: printf("ERROR: implement the attribute numbered %d \n",attr); abort(); @@ -1882,6 +1911,7 @@ void cuobjdumpParseBinary(unsigned int handle){ if (capability > max_capability) max_capability = capability; } if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); + max_capability=context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index dce35ca..b1eaf01 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -2155,3 +2155,4 @@ void functionalCoreSim::warp_exit( unsigned warp_id ) } } } + diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 4ddc6bf..33a4260 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -423,6 +423,7 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", extra_flags, fname2, tempfile_ptxinfo); printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); + fflush(stdout); result = system(commandline); if( result != 0 ) { printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); @@ -443,14 +444,12 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num } } - ptxinfo_in = fopen(final_tempfile_ptxinfo,"r"); if(no_of_ptx>0) g_ptxinfo_filename = final_tempfile_ptxinfo; else g_ptxinfo_filename = tempfile_ptxinfo; + ptxinfo_in = fopen(g_ptxinfo_filename,"r"); - //The program might get stuck because the parser didnt receive a EOF. - printf("NOTE: If the program is stuck, please press ctrl+d for Ubuntu/Mac and ctrl+z for Windows users \n"); ptxinfo_parse(); snprintf(commandline,1024,"rm -f *info"); -- cgit v1.3 From 2f9cdd0ac0954bae8822d0cfdb68fa4173087c1b Mon Sep 17 00:00:00 2001 From: Amruth Date: Fri, 6 Apr 2018 11:22:48 -0700 Subject: fixing arch flags --- libcuda/cuda_runtime_api.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 3fd88dc..184325c 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1911,7 +1911,7 @@ void cuobjdumpParseBinary(unsigned int handle){ if (capability > max_capability) max_capability = capability; } if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); - max_capability=context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); + //max_capability=context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); -- cgit v1.3 From 6c9555d42f3ab7f11dd003a9271d0c7e0ad21031 Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Mon, 9 Apr 2018 12:42:20 -0500 Subject: adding additional device attributes in cudaDeviceGetAttributes function for mnist --- libcuda/cuda_runtime_api.cc | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index c103244..bcc3e14 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -840,7 +840,16 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic if (device <= dev->num_devices() ) { prop = dev->get_prop(); switch (attr) { - case 5: + case 2: + *value= prop->maxThreadsDim[0]; + break; + case 3: + *value= prop->maxThreadsDim[1]; + break; + case 4: + *value= prop->maxThreadsDim[2]; + break; + case 5: *value= prop->maxGridSize[0]; break; case 6: @@ -849,6 +858,9 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 7: *value= prop->maxGridSize[2]; break; + case 8: + *value= prop->sharedMemPerBlock; + break; case 10: *value= prop->warpSize; break; @@ -873,6 +885,12 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 78: *value= 0 ; //TODO: as of now, we dont support stream priorities. break; + case 81: + *value= prop->sharedMemPerBlock; + break; + case 82: + *value= prop->regsPerBlock; + break; default: printf("ERROR: implement the attribute numbered %d \n",attr); abort(); -- cgit v1.3 From 960a1492fbbf2a4d098c8d060bc22782211ca60b Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Tue, 10 Apr 2018 14:52:49 -0500 Subject: added config -gpgpu_shmem_per_block and fixed cudaGetDeviceAttributes function --- libcuda/cuda_runtime_api.cc | 31 +++++++++++++++++++++++++++---- src/gpgpu-sim/gpu-sim.cc | 8 ++++++++ src/gpgpu-sim/gpu-sim.h | 1 + src/gpgpu-sim/shader.h | 2 +- 4 files changed, 37 insertions(+), 5 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index bcc3e14..d6ce4e0 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -349,7 +349,24 @@ class _cuda_device_id *GPGPUSim_Init() prop->maxGridSize[2] = 0x40000000; prop->totalConstMem = 0x40000000; prop->textureAlignment = 0; - prop->sharedMemPerBlock = the_gpu->shared_mem_size(); + /* + + * TODO: Update the .config and xml files of all GPU config files with new value of sharedMemPerBlock. + + * Previously, this was thought as sharedMemPerMultiprocessor and is being used in many places. + + * Check whether all the instances of shared_mem_size(), gpgpu_shmem_size or sharedMemPerBlock are meant to use sharedMemPerBlock or sharedMemPerMultiprocessor. + + */ + + prop->sharedMemPerBlock = the_gpu->shared_mem_per_block(); + + #if (CUDART_VERSION > 5000) + + prop->sharedMemPerMultiprocessor = the_gpu->shared_mem_size(); + + #endif + prop->regsPerBlock = the_gpu->num_registers_per_core(); prop->warpSize = the_gpu->wrp_size(); prop->clockRate = the_gpu->shader_clock(); @@ -861,6 +878,9 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 8: *value= prop->sharedMemPerBlock; break; + case 9: + *value= prop->totalConstMem; + break; case 10: *value= prop->warpSize; break; @@ -873,11 +893,14 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 16: *value= prop->multiProcessorCount ; break; + case 34: + *value= 0; + break; case 39: *value= dev->get_gpgpu()->threads_per_core(); break; case 75: - *value= 8 ; + *value= 9 ; break; case 76: *value= 3 ; @@ -886,13 +909,13 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic *value= 0 ; //TODO: as of now, we dont support stream priorities. break; case 81: - *value= prop->sharedMemPerBlock; + *value= prop->sharedMemPerMultiprocessor; break; case 82: *value= prop->regsPerBlock; break; default: - printf("ERROR: implement the attribute numbered %d \n",attr); + printf("ERROR: Attribute number %d unimplemented \n",attr); abort(); } return g_last_cudaError = cudaSuccess; diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 3829861..5d63ab7 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -265,6 +265,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_n_ldst_response_buffer_size", OPT_UINT32, &ldst_unit_response_queue_size, "number of response packets in ld/st unit ejection buffer", "2"); + option_parser_register(opp, "-gpgpu_shmem_per_block", OPT_UINT32, &gpgpu_shmem_per_block, + "Size of shared memory per thread block or CTA (default 48kB)", + "49152"); option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size, "Size of shared memory per shader core (default 16kB)", "16384"); @@ -661,6 +664,11 @@ int gpgpu_sim::shared_mem_size() const return m_shader_config->gpgpu_shmem_size; } +int gpgpu_sim::shared_mem_per_block() const +{ + return m_shader_config->gpgpu_shmem_per_block; +} + int gpgpu_sim::num_registers_per_core() const { return m_shader_config->gpgpu_shader_registers; diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 7d92c66..8d1c4fc 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -389,6 +389,7 @@ public: void get_pdom_stack_top_info( unsigned sid, unsigned tid, unsigned *pc, unsigned *rpc ); int shared_mem_size() const; + int shared_mem_per_block() const; int num_registers_per_core() const; int wrp_size() const; int shader_clock() const; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index bdd8dbe..fbddd18 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1285,7 +1285,7 @@ struct shader_core_config : public core_config unsigned max_cta_per_core; //Limit on number of concurrent CTAs in shader core unsigned max_barriers_per_cta; char * gpgpu_scheduler_string; - + unsigned gpgpu_shmem_per_block; char* pipeline_widths_string; int pipe_widths[N_PIPELINE_STAGES]; -- cgit v1.3 From c99a4ff88ecf7f69715939d96c1fa8152eee524c Mon Sep 17 00:00:00 2001 From: Amruth Date: Wed, 11 Apr 2018 11:05:12 -0700 Subject: PDOM analysis for child kernel in CDP --- src/cuda-sim/cuda_device_runtime.cc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc index 4a8ffe5..b399133 100644 --- a/src/cuda-sim/cuda_device_runtime.cc +++ b/src/cuda-sim/cuda_device_runtime.cc @@ -177,6 +177,20 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * //device_grid = op.grid; device_kernel_entry = config.entry; DEV_RUNTIME_REPORT("find device kernel " << device_kernel_entry->get_name()); + + //PDOM analysis is done for Parent kernel but not for child kernel. + if (device_kernel_entry->is_pdom_set()) { + printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", device_kernel_entry->get_name().c_str() ); + } else { + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", device_kernel_entry->get_name().c_str() ); + /* + * Some of the instructions like printf() gives the gpgpusim the wrong impression that it is a function call. + * As printf() doesnt have a body like functions do, doing pdom analysis for printf() causes a crash. + */ + if (device_kernel_entry->get_function_size() >0) + device_kernel_entry->do_pdom(); + device_kernel_entry->set_pdom(); + } //copy data in parameter_buffer to device kernel param memory unsigned device_kernel_arg_size = device_kernel_entry->get_args_aligned_size(); -- cgit v1.3 From f118b10cc49bf771755f2afdee04cde0359d745e Mon Sep 17 00:00:00 2001 From: Amruth Date: Wed, 11 Apr 2018 12:07:34 -0700 Subject: clean up --- libcuda/cuda_runtime_api.cc | 36 +++--------------------------------- src/cuda-sim/cuda-sim.cc | 1 - 2 files changed, 3 insertions(+), 34 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 184325c..abdc345 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -349,15 +349,7 @@ class _cuda_device_id *GPGPUSim_Init() prop->maxGridSize[2] = 0x40000000; prop->totalConstMem = 0x40000000; prop->textureAlignment = 0; - /* - * TODO: Update the .config and xml files of all GPU config files with new value of sharedMemPerBlock. - * Previously, this was thought as sharedMemPerMultiprocessor and is being used in many places. - * Check whether all the instances of shared_mem_size(), gpgpu_shmem_size or sharedMemPerBlock are meant to use sharedMemPerBlock or sharedMemPerMultiprocessor. - */ - prop->sharedMemPerBlock = 49152; -#if (CUDART_VERSION > 5000) - prop->sharedMemPerMultiprocessor = the_gpu->shared_mem_size(); -#endif + prop->sharedMemPerBlock = the_gpu->shared_mem_size(); prop->regsPerBlock = the_gpu->num_registers_per_core(); prop->warpSize = the_gpu->wrp_size(); prop->clockRate = the_gpu->shader_clock(); @@ -848,17 +840,8 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic if (device <= dev->num_devices() ) { prop = dev->get_prop(); switch (attr) { - case 2: - *value= prop->maxThreadsDim[0]; - break; - case 3: - *value= prop->maxThreadsDim[1]; - break; - case 4: - *value= prop->maxThreadsDim[2]; - break; case 5: - *value= prop->maxGridSize[0]; + *value= prop->maxGridSize[1]; break; case 6: *value= prop->maxGridSize[1]; @@ -866,12 +849,6 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 7: *value= prop->maxGridSize[2]; break; - case 8: - *value= prop->sharedMemPerBlock; - break; - case 9: - *value= prop->totalConstMem; - break; case 10: *value= prop->warpSize; break; @@ -884,14 +861,11 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 16: *value= prop->multiProcessorCount ; break; - case 34: - *value= 0; - break; case 39: *value= dev->get_gpgpu()->threads_per_core(); break; case 75: - *value= 9 ; + *value= 8 ; break; case 76: *value= 3 ; @@ -899,9 +873,6 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 78: *value= 0 ; //TODO: as of now, we dont support stream priorities. break; - case 81: - *value= prop->sharedMemPerMultiprocessor; - break; default: printf("ERROR: implement the attribute numbered %d \n",attr); abort(); @@ -1911,7 +1882,6 @@ void cuobjdumpParseBinary(unsigned int handle){ if (capability > max_capability) max_capability = capability; } if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); - //max_capability=context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index b1eaf01..dce35ca 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -2155,4 +2155,3 @@ void functionalCoreSim::warp_exit( unsigned warp_id ) } } } - -- cgit v1.3 From f052807cd6acfaf3221fbfe40ab905fd3aeaf2ef Mon Sep 17 00:00:00 2001 From: Amruth Date: Wed, 11 Apr 2018 19:11:47 +0000 Subject: cuda_runtime_api.cc edited online with Bitbucket --- libcuda/cuda_runtime_api.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index abdc345..dd32654 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -5,7 +5,7 @@ /* * cuda_runtime_api.cc * - * Copyright © 2009 by Tor M. Aamodt, Wilson W. L. Fung, Ali Bakhoda, + * Copyright 2009 by Tor M. Aamodt, Wilson W. L. Fung, Ali Bakhoda, * George L. Yuan and the University of British Columbia, Vancouver, * BC V6T 1Z4, All Rights Reserved. * @@ -841,7 +841,7 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic prop = dev->get_prop(); switch (attr) { case 5: - *value= prop->maxGridSize[1]; + *value= prop->maxGridSize[0]; break; case 6: *value= prop->maxGridSize[1]; -- cgit v1.3 From 89094df5b4e861b104393ea0f41886494a7f26a4 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 11 Apr 2018 15:46:01 -0400 Subject: This build status line was broken when there were cached files --- setup_environment | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/setup_environment b/setup_environment index 96cc362..3f2476e 100644 --- a/setup_environment +++ b/setup_environment @@ -8,7 +8,8 @@ export GPGPUSIM_ROOT="$( cd "$( dirname "$BASH_SOURCE" )" && pwd )" GPGPUSIM_VERSION_STRING=`cat $GPGPUSIM_ROOT/version | awk '/Version/ {print $8}'` #Detect Git branch and commit # GIT_COMMIT=`git log -n 1 | head -1 | sed -re 's/commit (.*)/\1/'` -GIT_FILES_CHANGED=`git diff --numstat --cached && git diff --numstat | wc | sed -re 's/^\s+([0-9]+).*/\1/'` +GIT_FILES_CHANGED=`git diff --numstat | wc | sed -re 's/^\s+([0-9]+).*/\1./'` +GIT_FILES_CHANGED+=`git diff --numstat --cached | wc | sed -re 's/^\s+([0-9]+).*/\1/'` GPGPUSIM_BUILD_STRING="gpgpu-sim_git-commit-$GIT_COMMIT-modified_$GIT_FILES_CHANGED" echo -n "GPGPU-Sim version $GPGPUSIM_VERSION_STRING (build $GPGPUSIM_BUILD_STRING) "; -- cgit v1.3 From 90a0a1e4093df69505d0ffc0b08eedc9d0355ac3 Mon Sep 17 00:00:00 2001 From: Amruth Date: Wed, 11 Apr 2018 19:55:24 +0000 Subject: Copyright symbol error --- libcuda/cuda_runtime_api.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index dd32654..c103244 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -5,7 +5,7 @@ /* * cuda_runtime_api.cc * - * Copyright 2009 by Tor M. Aamodt, Wilson W. L. Fung, Ali Bakhoda, + * Copyright © 2009 by Tor M. Aamodt, Wilson W. L. Fung, Ali Bakhoda, * George L. Yuan and the University of British Columbia, Vancouver, * BC V6T 1Z4, All Rights Reserved. * -- cgit v1.3 From 8ea33c977b26cfe96beb98cdda289b81b8fda899 Mon Sep 17 00:00:00 2001 From: Amruth Date: Sat, 14 Apr 2018 17:17:11 -0700 Subject: solving alignment issue --- libcuda/cuda_runtime_api.cc | 1 + src/cuda-sim/cuda-sim.cc | 7 ++++++- src/cuda-sim/ptx.l | 5 +++-- src/cuda-sim/ptx_ir.h | 1 + 4 files changed, 11 insertions(+), 3 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index d6ce4e0..ef46f00 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1923,6 +1923,7 @@ void cuobjdumpParseBinary(unsigned int handle){ if (capability > max_capability) max_capability = capability; } if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); + if (max_capability == 0) max_capability=context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index dce35ca..2c87031 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1139,8 +1139,13 @@ void function_info::finalize( memory_space *param_mem ) } // copy the parameter over word-by-word so that parameter that crosses a memory page can be copied over //Jin: copy parameter using aligned rules + const type_info *paramtype = param->type(); + int align_amount = paramtype->get_key().get_alignment_spec(); + align_amount = (align_amount == -1) ? size : align_amount; + param_address = (param_address + align_amount - 1) / align_amount * align_amount; //aligned + const size_t word_size = 4; - param_address = (param_address + size - 1) / size * size; //aligned with size + //param_address = (param_address + size - 1) / size * size; //aligned with size for (size_t idx = 0; idx < size; idx += word_size) { const char *pdata = reinterpret_cast(param_value.pdata) + idx; // cast to char * for ptr arithmetic param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 1b5d7f6..908c5be 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -36,7 +36,8 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "ptx.tab.h" #include -char linebuf[1024]; +#define LINEBUF_SIZE (64*1024) +char linebuf[LINEBUF_SIZE]; unsigned col = 0; #define TC col+=strlen(ptx_text); #define CHECK_UNSIGNED \ @@ -384,7 +385,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; "//"[^\n]* TC; // eat single -\n.* col=0; strncpy(linebuf, yytext + 1, 1024); yyless( 1 ); +\n.* col=0; strncpy(linebuf, yytext + 1, LINEBUF_SIZE); yyless( 1 ); " " TC; "\t" TC; diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 85b2a3b..6731763 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -91,6 +91,7 @@ public: bool is_tex() const { return m_space_spec == tex_space;} bool is_func_addr() const { return m_is_function?true:false; } int scalar_type() const { return m_scalar_type_spec;} + int get_alignment_spec() const { return m_alignment_spec;} unsigned type_decode( size_t &size, int &t ) const; static unsigned type_decode( int type, size_t &size, int &t ); memory_space_t get_memory_space() const { return m_space_spec; } -- cgit v1.3 -- cgit v1.3 From 60017ca1ddbe844a93f631fe2b86bc4101850037 Mon Sep 17 00:00:00 2001 From: Amruth Date: Thu, 19 Apr 2018 18:13:44 -0700 Subject: Crash when array pointers are passed --- README | 27 ++++++++++++++++++++++++++- src/cuda-sim/instructions.cc | 4 +++- src/cuda-sim/ptx_ir.h | 13 +++++++++++++ 3 files changed, 42 insertions(+), 2 deletions(-) diff --git a/README b/README index 543177c..bf5aa62 100644 --- a/README +++ b/README @@ -235,6 +235,14 @@ The documentation resides at doc/doxygen/html. Step 3: Run ============ +Before we run, we need to make sure the application's executable file is dynamically linked to CUDA runtime library. This can be done during compilation of your program by introducing the nvcc flag "--cudart shared" in makefile (quotes should be excluded). + +To confirm the same, type the follwoing command: + +ldd + +You should see that your application is using libcudart.so file in GPGPUSim directory. + Copy the contents of configs/QuadroFX5800/ or configs/GTX480/ to your application's working directory. These files configure the microarchitecture models to resemble the respective GPGPU architectures. @@ -348,7 +356,24 @@ identify any compile time or runtime errors that occur due to the code merging process. -** Debugging failing GPGPU-Sim Regressions ** +4. MISCELLANEOUS + +4.1 Speeding up the execution + +Some applications take several hours to execute on GPGPUSim. This is because the simulator has to dump the PTX, analyze them and get resource usage statistics. This can be avoided everytime we execute the program in the following way: + +Step 1: Execute the program by enabling “-save_embedded_ptx 1” in config file, execute the code and let cuobjdump command dump all necessary files. After this process, you will get 2 new files namely: _cuobjdump_complete_output_ and _1.ptx + +Step 2: Create new environment variables or include the below in your .bashrc file: + a. export PTX_SIM_USE_PTX_FILE=_1.ptx + b. export PTX_SIM_KERNELFILE=_1.ptx + c. export CUOBJDUMP_SIM_FILE=_cuobjdump_complete_output_ + +Step 3: Disable -save_embedded_ptx flag, execute the code again. This will skip the dumping by cuobjdump and directly goes to executing the program thus saving time. + + +4.2 Debugging failing GPGPU-Sim Regressions + Credits: Tor M Aamodt To debug failing GPGPU-Sim regression tests you need to run them locally. The fastest way to do this, assuming you are working with GPGPU-Sim versions more recent than the GPGPU-Sim dev branch circa March 28, 2018 (commit hash 2221d208a745a098a60b0d24c05007e92aaba092), is to install Docker. The instructions below were tested with Docker CE version 18.03 on Ubuntu and Mac OS. Docker will enable you to run the same set of regressions used by GPGPU-Sim when submitting a pull request to https://github.com/gpgpu-sim/gpgpu-sim_distribution and also allow you to log in and launch GPGPU-Sim in gdb so you can inspect failures. diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 0025c52..e53aaab 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -154,7 +154,9 @@ ptx_reg_t ptx_thread_info::get_operand_value( const operand_info &op, operand_in } else if ( op.is_local() ) { result.u64 = op.get_symbol()->get_address(); } else if ( op.is_function_address() ) { - result.u64 = (size_t)op.get_symbol()->get_pc(); + result.u64 = (size_t)op.get_symbol()->get_pc(); + } else if ( op.is_param_kernel()) { + result.u64 = op.get_symbol()->get_address(); } else { const char *name = op.name().c_str(); printf("GPGPU-Sim PTX: ERROR ** get_operand_value : unknown operand type for %s\n", name ); diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 6731763..58d5f49 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -164,6 +164,7 @@ public: m_is_global = false; m_is_local = false; m_is_param_local = false; + m_is_param_kernel = false; m_is_tex = false; m_is_func_addr = false; m_reg_num_valid = false; @@ -177,6 +178,7 @@ public: if ( type ) m_is_global = type->get_key().is_global(); if ( type ) m_is_local = type->get_key().is_local(); if ( type ) m_is_param_local = type->get_key().is_param_local(); + if ( type ) m_is_param_kernel = type->get_key().is_param_kernel(); if ( type ) m_is_tex = type->get_key().is_tex(); if ( type ) m_is_func_addr = type->get_key().is_func_addr(); } @@ -227,6 +229,7 @@ public: bool is_global() const { return m_is_global;} bool is_local() const { return m_is_local;} bool is_param_local() const { return m_is_param_local; } + bool is_param_kernel() const { return m_is_param_kernel; } bool is_tex() const { return m_is_tex;} bool is_func_addr() const { return m_is_func_addr; } bool is_reg() const @@ -284,6 +287,7 @@ private: bool m_is_global; bool m_is_local; bool m_is_param_local; + bool m_is_param_kernel; bool m_is_tex; bool m_is_func_addr; unsigned m_reg_num; @@ -400,6 +404,8 @@ public: m_type = symbolic_t; } else if ( addr->is_param_local() ) { m_type = symbolic_t; + } else if ( addr->is_param_kernel() ) { + m_type = symbolic_t; } else if ( addr->is_tex() ) { m_type = symbolic_t; } else if ( addr->is_func_addr() ) { @@ -676,6 +682,13 @@ public: return m_value.m_symbolic->type()->get_key().is_param_local(); } + bool is_param_kernel() const + { + if ( m_type != symbolic_t ) + return false; + return m_value.m_symbolic->type()->get_key().is_param_kernel(); + } + bool is_vector() const { if ( m_vector) return true; -- cgit v1.3 From f97a699ea5bee0a9df79afec40c0142d7ff8c5be Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Sun, 22 Apr 2018 23:29:09 -0400 Subject: Add cmath include to cuda-math.h, to allow std::isnan to be used --- src/cuda-sim/cuda-math.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cuda-sim/cuda-math.h b/src/cuda-sim/cuda-math.h index a3db0df..f88c526 100644 --- a/src/cuda-sim/cuda-math.h +++ b/src/cuda-sim/cuda-math.h @@ -67,6 +67,8 @@ #ifndef CUDA_MATH #define CUDA_MATH +#include + // cuda math implementations #undef max #undef min -- cgit v1.3 From 373d64290239f3ed74d98b20494383f03fe189b6 Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Sun, 22 Apr 2018 23:31:42 -0400 Subject: Some classes were referred to as a class and a struct (reported as clang warnings). This makes these consistent. --- libcuda/cuda_runtime_api.cc | 2 +- src/cuda-sim/cuda-sim.cc | 2 +- src/cuda-sim/ptx_ir.h | 2 +- src/debug.cc | 2 +- src/debug.h | 2 +- src/gpgpu-sim/dram.h | 4 ++-- src/gpgpu-sim/mem_fetch.cc | 2 +- src/gpgpu-sim/mem_fetch.h | 4 ++-- src/gpgpu-sim/shader.h | 4 ++-- src/stream_manager.h | 6 +++--- 10 files changed, 15 insertions(+), 15 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 9bdb993..5ef6115 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -324,7 +324,7 @@ private: gpgpu_ptx_sim_arg_list_t m_args; }; -class _cuda_device_id *GPGPUSim_Init() +struct _cuda_device_id *GPGPUSim_Init() { static _cuda_device_id *the_device = NULL; if( !the_device ) { diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index a34b99b..9f24c69 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -2067,7 +2067,7 @@ struct rec_pts { int s_num_recon; }; -struct std::map g_rpts; +class std::map g_rpts; struct rec_pts find_reconvergence_points( function_info *finfo ) { diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 9ad1571..8750187 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -105,7 +105,7 @@ private: int m_is_function; bool m_is_non_arch_reg; - friend class type_info_key_compare; + friend struct type_info_key_compare; }; class symbol_table; diff --git a/src/debug.cc b/src/debug.cc index cfd7bb0..ae15760 100644 --- a/src/debug.cc +++ b/src/debug.cc @@ -222,7 +222,7 @@ void gpgpu_sim::gpgpu_debug() } } -bool thread_at_brkpt( ptx_thread_info *thread, const struct brk_pt &b ) +bool thread_at_brkpt( ptx_thread_info *thread, const class brk_pt &b ) { return b.is_equal(thread->get_location(),thread->get_uid()); } diff --git a/src/debug.h b/src/debug.h index 7c79f1e..1277494 100644 --- a/src/debug.h +++ b/src/debug.h @@ -87,7 +87,7 @@ extern int gpgpu_ptx_instruction_classification ; class ptx_thread_info; class ptx_instruction; -bool thread_at_brkpt( ptx_thread_info *thd_info, const struct brk_pt &b ); +bool thread_at_brkpt( ptx_thread_info *thd_info, const class brk_pt &b ); void hit_watchpoint( unsigned watchpoint_num, ptx_thread_info *thd, const ptx_instruction *pI ); #endif diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index a8bff14..15c63e7 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -87,7 +87,7 @@ struct bank_t unsigned int bkgrpindex; }; -struct mem_fetch; +class mem_fetch; class dram_t { @@ -178,7 +178,7 @@ private: unsigned int ave_mrqs_partial; unsigned int bwutil_partial; - struct memory_stats_t *m_stats; + class memory_stats_t *m_stats; class Stats* mrqq_Dist; //memory request queue inside DRAM friend class frfcfs_scheduler; diff --git a/src/gpgpu-sim/mem_fetch.cc b/src/gpgpu-sim/mem_fetch.cc index 580c051..729636d 100644 --- a/src/gpgpu-sim/mem_fetch.cc +++ b/src/gpgpu-sim/mem_fetch.cc @@ -39,7 +39,7 @@ mem_fetch::mem_fetch( const mem_access_t &access, unsigned wid, unsigned sid, unsigned tpc, - const class memory_config *config ) + const struct memory_config *config ) { m_request_uid = sm_next_mf_request_uid++; m_access = access; diff --git a/src/gpgpu-sim/mem_fetch.h b/src/gpgpu-sim/mem_fetch.h index c89edbb..de98748 100644 --- a/src/gpgpu-sim/mem_fetch.h +++ b/src/gpgpu-sim/mem_fetch.h @@ -55,7 +55,7 @@ public: unsigned wid, unsigned sid, unsigned tpc, - const class memory_config *config ); + const struct memory_config *config ); ~mem_fetch(); void set_status( enum mem_fetch_status status, unsigned long long cycle ); @@ -141,7 +141,7 @@ private: static unsigned sm_next_mf_request_uid; - const class memory_config *m_mem_config; + const struct memory_config *m_mem_config; unsigned icnt_flit_size; }; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index bdd8dbe..ea8c019 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -286,7 +286,7 @@ typedef std::bitset warp_set_t; int register_bank(int regnum, int wid, unsigned num_banks, unsigned bank_warp_shift); class shader_core_ctx; -class shader_core_config; +struct shader_core_config; class shader_core_stats; enum scheduler_prioritization_type @@ -967,7 +967,7 @@ struct ifetch_buffer_t { unsigned m_warp_id; }; -class shader_core_config; +struct shader_core_config; class simd_function_unit { public: diff --git a/src/stream_manager.h b/src/stream_manager.h index 222a1b2..d3a804f 100644 --- a/src/stream_manager.h +++ b/src/stream_manager.h @@ -93,7 +93,7 @@ public: m_stream=stream; m_done=false; } - stream_operation( class CUevent_st *e, struct CUstream_st *stream ) + stream_operation( struct CUevent_st *e, struct CUstream_st *stream ) { m_kernel=NULL; m_type=stream_event; @@ -172,10 +172,10 @@ private: bool m_sim_mode; kernel_info_t *m_kernel; - class CUevent_st *m_event; + struct CUevent_st *m_event; }; -class CUevent_st { +struct CUevent_st { public: CUevent_st( bool blocking ) { -- cgit v1.3 From 968a0510e7d1826fefa7b6688eb662d71d048809 Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Sun, 22 Apr 2018 23:35:05 -0400 Subject: One more instance of where a string should be escaped with %s before being passed to printf. --- cuobjdump_to_ptxplus/cuobjdumpInst.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cuobjdump_to_ptxplus/cuobjdumpInst.cc b/cuobjdump_to_ptxplus/cuobjdumpInst.cc index c74d2d8..392f829 100644 --- a/cuobjdump_to_ptxplus/cuobjdumpInst.cc +++ b/cuobjdump_to_ptxplus/cuobjdumpInst.cc @@ -2083,7 +2083,7 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list labelList, std: else { printf("Unknown Instruction: "); - printf(m_base.c_str()); + printf("%s",m_base.c_str()); printf("\n"); output("Unknown Instruction: "); output(m_base); -- cgit v1.3 From c246c12dffa6683a1fe61ad3a311cce8b1c1cbbf Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Sun, 22 Apr 2018 23:35:57 -0400 Subject: Clang disallows empty bracks to show array indices. I believe that inserting a zero is the intent. --- src/gpgpu-sim/shader.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index ea8c019..53a10e0 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1347,7 +1347,7 @@ struct shader_core_config : public core_config struct shader_core_stats_pod { - void* shader_core_stats_pod_start[]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure + void* shader_core_stats_pod_start[0]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure unsigned long long *shader_cycles; unsigned *m_num_sim_insn; // number of scalar thread instructions committed by this shader core unsigned *m_num_sim_winsn; // number of warp instructions committed by this shader core -- cgit v1.3 From 70e036c6007135c43d213139e1a6963090721f59 Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Tue, 1 May 2018 14:58:35 -0500 Subject: Added support for -gpgpu_registers_per_block config --- libcuda/cuda_runtime_api.cc | 27 ++++++++------------------- src/gpgpu-sim/gpu-sim.cc | 8 ++++++++ src/gpgpu-sim/gpu-sim.h | 1 + src/gpgpu-sim/shader.h | 1 + 4 files changed, 18 insertions(+), 19 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index ef46f00..e3c2542 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -349,24 +349,13 @@ class _cuda_device_id *GPGPUSim_Init() prop->maxGridSize[2] = 0x40000000; prop->totalConstMem = 0x40000000; prop->textureAlignment = 0; - /* - - * TODO: Update the .config and xml files of all GPU config files with new value of sharedMemPerBlock. - - * Previously, this was thought as sharedMemPerMultiprocessor and is being used in many places. - - * Check whether all the instances of shared_mem_size(), gpgpu_shmem_size or sharedMemPerBlock are meant to use sharedMemPerBlock or sharedMemPerMultiprocessor. - - */ - - prop->sharedMemPerBlock = the_gpu->shared_mem_per_block(); - - #if (CUDART_VERSION > 5000) - - prop->sharedMemPerMultiprocessor = the_gpu->shared_mem_size(); - - #endif - +// * TODO: Update the .config and xml files of all GPU config files with new value of sharedMemPerBlock and regsPerBlock + prop->sharedMemPerBlock = the_gpu->shared_mem_per_block(); +#if (CUDART_VERSION > 5000) + prop->regsPerMultiprocessor = the_gpu->num_registers_per_core(); + prop->sharedMemPerMultiprocessor = the_gpu->shared_mem_size(); +#endif + prop->sharedMemPerBlock = the_gpu->shared_mem_per_block(); prop->regsPerBlock = the_gpu->num_registers_per_core(); prop->warpSize = the_gpu->wrp_size(); prop->clockRate = the_gpu->shader_clock(); @@ -912,7 +901,7 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic *value= prop->sharedMemPerMultiprocessor; break; case 82: - *value= prop->regsPerBlock; + *value= prop->regsPerMultiprocessor; break; default: printf("ERROR: Attribute number %d unimplemented \n",attr); diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 5d63ab7..b283964 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -247,6 +247,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shader_registers", OPT_UINT32, &gpgpu_shader_registers, "Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)", "8192"); + option_parser_register(opp, "-gpgpu_registers_per_block", OPT_UINT32, &gpgpu_registers_per_block, + "Maximum number of registers per thread block. (default 8192)", + "8192"); option_parser_register(opp, "-gpgpu_shader_cta", OPT_UINT32, &max_cta_per_core, "Maximum number of concurrent CTAs in shader (default 8)", "8"); @@ -674,6 +677,11 @@ int gpgpu_sim::num_registers_per_core() const return m_shader_config->gpgpu_shader_registers; } +int gpgpu_sim::num_registers_per_block() const +{ + return m_shader_config->gpgpu_registers_per_block; +} + int gpgpu_sim::wrp_size() const { return m_shader_config->warp_size; diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 8d1c4fc..5908fd5 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -391,6 +391,7 @@ public: int shared_mem_size() const; int shared_mem_per_block() const; int num_registers_per_core() const; + int num_registers_per_block() const; int wrp_size() const; int shader_clock() const; const struct cudaDeviceProp *get_prop() const; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index fbddd18..6201840 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1286,6 +1286,7 @@ struct shader_core_config : public core_config unsigned max_barriers_per_cta; char * gpgpu_scheduler_string; unsigned gpgpu_shmem_per_block; + unsigned gpgpu_registers_per_block; char* pipeline_widths_string; int pipe_widths[N_PIPELINE_STAGES]; -- cgit v1.3 -- cgit v1.3 From e096e97dc6d38e26d21a83347bd0367cb6d78aeb Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Tue, 1 May 2018 15:18:11 -0500 Subject: Added -save_embedded_ptx 1 to config files --- configs/GTX480/gpgpusim.config | 3 +++ configs/GeForceGTX1080Ti/gpgpusim.config | 3 +++ configs/GeForceGTX750Ti/gpgpusim.config | 3 +++ configs/QuadroFX5600/gpgpusim.config | 3 +++ configs/QuadroFX5800/gpgpusim.config | 3 +++ configs/TeslaC2050/gpgpusim.config | 3 +++ 6 files changed, 18 insertions(+) diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config index 436cb41..580929f 100644 --- a/configs/GTX480/gpgpusim.config +++ b/configs/GTX480/gpgpusim.config @@ -1,3 +1,6 @@ +#Save the cuobjdump dump +#-save_embedded_ptx 1 + # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 diff --git a/configs/GeForceGTX1080Ti/gpgpusim.config b/configs/GeForceGTX1080Ti/gpgpusim.config index a5ada34..6d8b43a 100644 --- a/configs/GeForceGTX1080Ti/gpgpusim.config +++ b/configs/GeForceGTX1080Ti/gpgpusim.config @@ -1,5 +1,8 @@ # This config models the Pascal GP102 (GeForceGTX 1080Ti) +#Save the cuobjdump dump +#-save_embedded_ptx 1 + # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index 8b030b6..b6870b0 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -1,3 +1,6 @@ +#Save the cuobjdump dump +#-save_embedded_ptx 1 + # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 diff --git a/configs/QuadroFX5600/gpgpusim.config b/configs/QuadroFX5600/gpgpusim.config index cb87b65..6f6e032 100644 --- a/configs/QuadroFX5600/gpgpusim.config +++ b/configs/QuadroFX5600/gpgpusim.config @@ -1,3 +1,6 @@ +#Save the cuobjdump dump +#-save_embedded_ptx 1 + # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index 82243c2..77d9c6d 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -1,3 +1,6 @@ +#Save the cuobjdump dump +#-save_embedded_ptx 1 + # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config index 442ab8b..480aaa4 100644 --- a/configs/TeslaC2050/gpgpusim.config +++ b/configs/TeslaC2050/gpgpusim.config @@ -1,3 +1,6 @@ +#Save the cuobjdump dump +#-save_embedded_ptx 1 + # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 -- cgit v1.3 From f405cb9484a8b0f961bd7c143bebf1fcb17546da Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Wed, 2 May 2018 12:23:59 -0500 Subject: Minor change in config description --- src/gpgpu-sim/gpu-sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index b283964..07a0c57 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -248,7 +248,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)", "8192"); option_parser_register(opp, "-gpgpu_registers_per_block", OPT_UINT32, &gpgpu_registers_per_block, - "Maximum number of registers per thread block. (default 8192)", + "Maximum number of registers per CTA. (default 8192)", "8192"); option_parser_register(opp, "-gpgpu_shader_cta", OPT_UINT32, &max_cta_per_core, "Maximum number of concurrent CTAs in shader (default 8)", -- cgit v1.3 From 2be06dee25a11f9c37e94ed8d92cdeac71cf504e Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 4 May 2018 12:04:19 -0400 Subject: Getting the simulator to compile with older versions of g++ --- src/cuda-sim/cuda-math.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cuda-sim/cuda-math.h b/src/cuda-sim/cuda-math.h index a3db0df..afac330 100644 --- a/src/cuda-sim/cuda-math.h +++ b/src/cuda-sim/cuda-math.h @@ -67,6 +67,8 @@ #ifndef CUDA_MATH #define CUDA_MATH +#include + // cuda math implementations #undef max #undef min @@ -148,6 +150,7 @@ float __ll2float_rd(long long int a) { #include #include + // 32-bit integer to float float __int2float_rn(int a) { int orig_rnd_mode = fegetround(); -- cgit v1.3 From 6ff157a4ec13e33dc69856de33a7690afa408f6d Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 4 May 2018 12:04:19 -0400 Subject: Getting the simulator to compile with older versions of g++ --- src/cuda-sim/cuda-math.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cuda-sim/cuda-math.h b/src/cuda-sim/cuda-math.h index a3db0df..afac330 100644 --- a/src/cuda-sim/cuda-math.h +++ b/src/cuda-sim/cuda-math.h @@ -67,6 +67,8 @@ #ifndef CUDA_MATH #define CUDA_MATH +#include + // cuda math implementations #undef max #undef min @@ -148,6 +150,7 @@ float __ll2float_rd(long long int a) { #include #include + // 32-bit integer to float float __int2float_rn(int a) { int orig_rnd_mode = fegetround(); -- cgit v1.3 From 7d2b1a546cfc4a03eac998fa37b7720ce9e68109 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 9 May 2018 11:24:50 -0400 Subject: if data_dirs is not there - forget about it --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 806231e..57fc6c3 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -28,7 +28,7 @@ pipeline { cd gpgpu-sim_simulations && \ git checkout purdue-cluster && \ git pull && \ - rm -r ./benchmarks/data_dirs && ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' + rm -fr ./benchmarks/data_dirs && ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ -- cgit v1.3 From 0f8c407eea99e1622486127912a83ef3e0dcf397 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 9 May 2018 16:04:09 -0400 Subject: When doing the HW correlation, do not count the first 4 cycle runs (all our data now has 10 run cycle runs). The first 4 are unreliable cause of DVFS --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 57fc6c3..db0c18f 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -84,7 +84,7 @@ pipeline { ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS > stats-4.2.csv && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ - ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-4.2.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ + ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-4.2.csv -H ./gpgpu-sim_simulations/run_hw/ -B 4 &&\ scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' } } @@ -95,7 +95,7 @@ pipeline { ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C GTX1080Ti > stats-9.1.csv && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ - ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ + ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ -B 4 &&\ scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' } } -- cgit v1.3 From 68674d4ba230df0d3bf9f4e5b035f4cf9cfc185b Mon Sep 17 00:00:00 2001 From: negargoli93 Date: Sat, 12 May 2018 16:09:04 -0700 Subject: commit for eece527project --- src/abstract_hardware_model.h | 6 +- src/cuda-sim/cuda-sim.cc | 11 ++- src/cuda-sim/instructions.cc | 213 +++++++++++++++++++----------------------- src/cuda-sim/opcodes.def | 2 +- src/cuda-sim/ptx.l | 2 +- src/cuda-sim/ptx_ir.h | 25 +++++ src/gpgpu-sim/scoreboard.cc | 4 + src/gpgpusim_entrypoint.cc | 1 - 8 files changed, 136 insertions(+), 128 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index cdd9cf3..9dc58d4 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -750,7 +750,7 @@ public: }; // the maximum number of destination, source, or address uarch operands in a instruction -#define MAX_REG_OPERANDS 8 +#define MAX_REG_OPERANDS 32 struct dram_callback_t { dram_callback_t() { function=NULL; instruction=NULL; thread=NULL; } @@ -825,8 +825,8 @@ public: address_type reconvergence_pc; // -1 => not a branch, -2 => use function return address - unsigned out[4]; - unsigned in[4]; + unsigned out[8]; + unsigned in[8]; unsigned char is_vectorin; unsigned char is_vectorout; int pred; // predicate register number diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 54d8796..006738a 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -792,9 +792,9 @@ void ptx_instruction::set_opcode_and_latency() initiation_interval = dp_init[2]; op = SFU_OP; break; - case BSMAD_OP: - latency = int_precision/int_lane_width; - initiation_interval = int_init_precision/int_init_lane_width; + case MMA_OP: + latency = 64; + initiation_interval = 64; break; case SHFL_OP: latency = 32; @@ -1301,6 +1301,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) *((warp_inst_t*)pJ) = inst; // copy active mask information pI = pJ; } + if((pI->get_opcode()!=MMA_OP)||((pI->get_opcode()==MMA_OP)&&(lane_id==0))){ switch ( pI->get_opcode() ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; #define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; @@ -1308,7 +1309,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) #undef OP_DEF #undef OP_W_DEF default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break; - } + }} delete pJ; pI = pI_saved; @@ -1930,7 +1931,7 @@ void functionalCoreSim::executeWarp(unsigned i, bool &allAtBarrier, bool & someO { if(!m_warpAtBarrier[i] && m_liveThreadCount[i]!=0){ warp_inst_t inst =getExecuteWarp(i); - execute_warp_inst_t(inst,i); + execute_warp_inst_t(inst,i); if(inst.isatomic()) inst.do_atomic(true); if(inst.op==BARRIER_OP || inst.op==MEMORY_BARRIER_OP ) m_warpAtBarrier[i]=true; updateSIMTStack( i, &inst ); diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 493e307..7903343 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -771,6 +771,17 @@ void add_impl( const ptx_instruction *pI, ptx_thread_info *thread ) unsigned i_type = pI->get_type(); src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + //unsigned warpId_aa,warp_size_aa; + //warpId_aa = pI->warp_id(); + //warp_size_aa=32; + //dim3 t=thread->get_tid(); + //unsigned tid_aa=warp_size_aa*warpId_aa; + + ptx_thread_info *thread2; + thread2=thread; + src1_data = thread2->get_operand_value(src1, dst, i_type, thread2, 1); + src2_data = thread2->get_operand_value(src2, dst, i_type, thread2, 1); + unsigned rounding_mode = pI->rounding_mode(); int orig_rm = fegetround(); @@ -1483,135 +1494,102 @@ unsigned trunc(unsigned num, unsigned precision) { return num; } -void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) +void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { - // operands: - // 0 = output - // 1 = input precision - // 2 = output precision - // 3 = buffer0 - // 4 = buffer1 - // 5 = buffer2 - // 6 = buffer3 - // 7 = synapse value - // 8 = output value + int i,j,k,thrd; + int row,offset; + printf("mmaWorld\n"); + ptx_reg_t matrix_a[16][16]; + ptx_reg_t matrix_b[16][16]; + ptx_reg_t matrix_c[16][16]; + ptx_reg_t matrix_d[16][16]; + ptx_reg_t src_data; + ptx_thread_info *thread; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); unsigned type = pI->get_type(); int tid = inst.warp_id_func() * core->get_warp_size(); - ptx_thread_info *thread = core->get_thread_info()[tid]; - const int ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; - const int op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; - const int THREADS = inst.active_count(); - const int INBUFFERS = 4; - const int OUTBUFFERS = (((32/ip)*INBUFFERS) / (32/op)) + ((((32/ip)*INBUFFERS) % (32/op)) != 0); - if (OUTBUFFERS > THREADS) { - printf("GPGPU-Sim PTX: BSMAD ERROR - Number of output registers required (%d) is greater than the number available (%d)\n", OUTBUFFERS, THREADS); - abort(); - } - ptx_warp_info *warp_info = thread->m_warp_info; - warp_info->inc_done_threads(); + const operand_info &dst = pI->operand_lookup(0); + +//NOT WOR thread = core->get_thread_info()[tid]; +//NOT WOR const operand_info &src_a= pI->operand_lookup(1); +//NOT WOR src_data= (thread->get_operand_value(src_a, dst, type, thread, 1)); +//NOT WOR thread->set_operand_value(dst, src_data, type, thread, pI); + for (thrd=0; thrd < core->get_warp_size(); thrd++){ + row=thrd/2; + offset=8*(thrd%2); + thread = core->get_thread_info()[tid+thrd]; + printf("thread=%d:",thrd); + for(i=8;i<=31;i++){ + const operand_info &src_a= pI->operand_lookup(i); + src_data= (thread->get_operand_value(src_a, dst, type, thread, 1)); + printf("%f ",src_data.f32); + if(i<=15) + matrix_a[row][offset+(i)%8]=src_data; + else if((i>15)&&(i<=23)) + matrix_b[row][offset+(i)%8]=src_data; + else if(i>23) + matrix_c[row][offset+(i)%8]=src_data; + - // threads within the warp are executed sequentially by the simulator, store output in first four registers - if (warp_info->get_done_threads() <= OUTBUFFERS) { - unsigned buffer[THREADS][INBUFFERS]; - unsigned synapse[THREADS]; - unsigned output; - - // loop through all threads in the warp and get all data - for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { - if (inst.active(i)) { - const operand_info &src3 = pI->operand_lookup(3); - const operand_info &src4 = pI->operand_lookup(4); - const operand_info &src5 = pI->operand_lookup(5); - const operand_info &src6 = pI->operand_lookup(6); - const operand_info &src7 = pI->operand_lookup(7); - const operand_info &src8 = pI->operand_lookup(8); - - thread = core->get_thread_info()[tid+i]; - // get buffer data and synapse data from each thread - buffer[j][0] = (thread->get_operand_value(src3, dst, type, thread, 1)).u32; - buffer[j][1] = (thread->get_operand_value(src4, dst, type, thread, 1)).u32; - buffer[j][2] = (thread->get_operand_value(src5, dst, type, thread, 1)).u32; - buffer[j][3] = (thread->get_operand_value(src6, dst, type, thread, 1)).u32; - synapse[j] = (thread->get_operand_value(src7, dst, type, thread, 1)).u32; - j++; - // get output data from the first 4 threads - if (j == warp_info->get_done_threads()) { - output = (thread->get_operand_value(src8, dst, type, thread, 1)).u32; - } - } } + printf("\n"); + } - // unpack registers, compute enough outputs to fill an output register - unsigned *unpacked_output = (unsigned*)calloc(32/op,sizeof(unsigned)); - unsigned buffer_data_start = (32/op)*(warp_info->get_done_threads()-1); - for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*INBUFFERS; i++) { - unsigned buf = i/(32/ip); - unsigned pos = i%(32/ip); - // sum values from the buffers - int sum = 0; - unsigned mask = (unsigned)(pow(2,ip)-1) << (pos*ip); - for (int j = 0; j < THREADS; j++) { - //sum += ((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j]; - sum += trunc(((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j], op); - } - // get the previous output - mask = (unsigned)(pow(2,op)-1) << (op*(i-buffer_data_start)); - int past_output = (mask & output) >> (op*(i-buffer_data_start)); - unpacked_output[i-buffer_data_start] = trunc(trunc(sum,op) + past_output,op); - // truncate sum, truncate (truncated sum + past_output) + printf("MATRIX_A\n"); + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + printf("%f ",matrix_a[i][j].f32); } - - // truncate output - /*for (unsigned i = 0; i < 32/op; i++) { - int mask = 1, latest_one = -1; - unsigned data = unpacked_output[i]; - for (unsigned j = 0; j < sizeof(unsigned)*8; j++) { - int bit = data & mask; - if (bit == 1) latest_one = j; - data >>= 1; - } - if (latest_one >= op) { - // round_up is 1 if the most significant truncated digit is a 1, otherwise it is 0 - int round_up = (unpacked_output[i] & (1 << (latest_one-op))) >> (latest_one-op); - unsigned shifted_output = unpacked_output[i] >> (latest_one-op+1); - // if shifted_output is a number like 1111, don't round up - if (shifted_output == (pow(2,op)-1)) round_up = 0; - unpacked_output[i] = shifted_output + round_up; - } - }*/ - - // pack the outputs into one register - unsigned mask = pow(2,op)-1; - unsigned output_data = 0; - for (int i = 0; i < 32/op; i++) { - output_data |= (unpacked_output[i] & mask) << (op*i); + printf("\n"); + } + printf("MATRIX_B\n"); + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + printf("%f ",matrix_b[i][j].f32); } - - // store the result in the correct thread's output register - for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { - if (inst.active(i)) j++; - if (j == warp_info->get_done_threads()) { - thread = core->get_thread_info()[tid+i]; - ptx_reg_t data; - data.u32 = output_data; - thread->set_operand_value(dst, data, type, thread, pI); - break; + printf("\n"); + } + printf("MATRIX_C\n"); + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + printf("%f ",matrix_c[i][j].f32); + } + printf("\n"); + } + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + matrix_d[i][j].f32=0; + } + } + + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + for(k=0;k<16;k++){ + matrix_d[i][j].f32=matrix_d[i][j].f32+matrix_a[i][k].f32*matrix_b[j][k].f32; } + matrix_d[i][j].f32+=matrix_c[i][j].f32; } } - - // once the warp has finished, set the number of completed threads back to 0 for the next warp - if (warp_info->get_done_threads() == THREADS) { - warp_info->reset_done_threads(); + printf("MATRIX_D\n"); + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + printf("%f ",matrix_d[i][j].f32); + } + printf("\n"); + } + for (thrd=0; thrd < core->get_warp_size(); thrd++){ + thread = core->get_thread_info()[tid+thrd]; + row=thrd/2; + offset=8*(thrd%2); + for(i=0;i<8;i++){ + const operand_info &dst = pI->operand_lookup(i); + const symbol *r2; + r2=dst.get_symbol(); + printf("thrd=%d,i=%d,register%s, data=%f\n",thrd,i,(r2->name()).c_str(),matrix_d[row][offset+i].f32); + thread->set_operand_value(dst, matrix_d[row][offset+i], type, thread, pI); + } } - - // set the latency assuming 4 bits of each input get processed every cycle - // mutable latency variable??? - //pI->latency = (ip+3)/4; + } void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) @@ -4098,7 +4076,8 @@ void st_impl( const ptx_instruction *pI, ptx_thread_info *thread ) if (!vector_spec) { data = thread->get_operand_value(src1, dst, type, thread, 1); mem->write(addr,size/8,&data.s64,thread,pI); - } else { + printf("addr=%d data=%d\n",addr,data.s64); + } else { if (vector_spec == V2_TYPE) { ptx_reg_t* ptx_regs = new ptx_reg_t[2]; thread->get_vector_operand_values(src1, ptx_regs, 2); diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 41f2f22..a3cc83f 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -52,7 +52,7 @@ OP_DEF(BRA_OP,bra_impl,"bra",0,3) OP_DEF(BRX_OP,brx_impl,"brx",0,3) OP_DEF(BREV_OP,brev_impl,"brev",1,1) OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9) -OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",1,1) +OP_W_DEF(MMA_OP,mma_impl,"mma",1,1) OP_DEF(CALL_OP,call_impl,"call",1,3) OP_DEF(CALLP_OP,callp_impl,"callp",1,3) OP_DEF(CLZ_OP,clz_impl,"clz",1,1) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 7620134..e07e339 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -68,7 +68,7 @@ bra TC; ptx_lval.int_value = BRA_OP; return OPCODE; brx TC; ptx_lval.int_value = BRX_OP; return OPCODE; brev TC; ptx_lval.int_value = BREV_OP; return OPCODE; brkpt TC; ptx_lval.int_value = BRKPT_OP; return OPCODE; -bsmad TC; ptx_lval.int_value = BSMAD_OP; return OPCODE; +mma TC; ptx_lval.int_value = MMA_OP; return OPCODE; call TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode callp TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE; clz TC; ptx_lval.int_value = CLZ_OP; return OPCODE; diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 4c10373..0601b97 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -948,6 +948,31 @@ public: assert( m_operands.size() > 3 ); return m_operands[3]; } + const operand_info &src4() const + { + assert( m_operands.size() > 4 ); + return m_operands[4]; + } + const operand_info &src5() const + { + assert( m_operands.size() > 5 ); + return m_operands[5]; + } + const operand_info &src6() const + { + assert( m_operands.size() > 6 ); + return m_operands[6]; + } + const operand_info &src7() const + { + assert( m_operands.size() > 7 ); + return m_operands[7]; + } + const operand_info &src8() const + { + assert( m_operands.size() > 8 ); + return m_operands[8]; + } const operand_info &operand_lookup( unsigned n ) const { diff --git a/src/gpgpu-sim/scoreboard.cc b/src/gpgpu-sim/scoreboard.cc index f412054..b538fdf 100644 --- a/src/gpgpu-sim/scoreboard.cc +++ b/src/gpgpu-sim/scoreboard.cc @@ -146,6 +146,10 @@ bool Scoreboard::checkCollision( unsigned wid, const class inst_t *inst ) const if(inst->in[1] > 0) inst_regs.insert(inst->in[1]); if(inst->in[2] > 0) inst_regs.insert(inst->in[2]); if(inst->in[3] > 0) inst_regs.insert(inst->in[3]); + if(inst->in[3] > 0) inst_regs.insert(inst->in[4]); + if(inst->in[3] > 0) inst_regs.insert(inst->in[5]); + if(inst->in[3] > 0) inst_regs.insert(inst->in[6]); + if(inst->in[3] > 0) inst_regs.insert(inst->in[7]); if(inst->pred > 0) inst_regs.insert(inst->pred); if(inst->ar1 > 0) inst_regs.insert(inst->ar1); if(inst->ar2 > 0) inst_regs.insert(inst->ar2); diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index 04845e7..a6d7eb4 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -134,7 +134,6 @@ void *gpgpu_sim_thread_concurrent(void*) gpgpu_cuda_ptx_sim_main_func(*kernel); g_the_gpu->finish_functional_sim(kernel); } - //performance simulation if( g_the_gpu->active() ) { g_the_gpu->cycle(); -- cgit v1.3 From bae67e6a355047e360c30391588c2076913f86fa Mon Sep 17 00:00:00 2001 From: negargoli93 Date: Sat, 12 May 2018 17:11:34 -0700 Subject: mma added --- src/cuda-sim/instructions.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 7903343..bddaf8c 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1565,7 +1565,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) for (i=0;i<16;i++){ for(j=0;j<16;j++){ for(k=0;k<16;k++){ - matrix_d[i][j].f32=matrix_d[i][j].f32+matrix_a[i][k].f32*matrix_b[j][k].f32; + matrix_d[i][j].f32=matrix_d[i][j].f32+matrix_a[i][k].f32*matrix_b[k][j].f32; } matrix_d[i][j].f32+=matrix_c[i][j].f32; } -- cgit v1.3 From 8b34db6513e20335e06c8b40ead6d181e3ebba44 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Wed, 16 May 2018 13:36:15 -0700 Subject: is_reg change --- .gitignore | 4 ++++ src/cuda-sim/instructions.cc | 6 ++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/.gitignore b/.gitignore index 887b605..428abce 100644 --- a/.gitignore +++ b/.gitignore @@ -29,3 +29,7 @@ cuobjdump_to_ptxplus/sass_parser.output build/* *.swp +*~ +cscope* +tags + diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index e53aaab..8a3539b 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2366,9 +2366,11 @@ void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand type_info_key ti = t->get_key(); if( ti.is_param_kernel() ) space = param_space_kernel; - else if( ti.is_param_local() ) { + else if( ti.is_param_local() ) space = param_space_local; - } else { + else if( ti.is_reg() ) + space = param_space_kernel; + else { printf("GPGPU-Sim PTX: ERROR ** cannot resolve .param space for '%s'\n", s->name().c_str() ); abort(); } -- cgit v1.3 From a851f6d6217396ebd8cd8a895ecad697336387b4 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 09:27:07 -0700 Subject: allows gpgpusim to select a set of texture array,attr,info but maybe not the right one --- src/abstract_hardware_model.h | 73 +++++++++++++++++++++++++++++++++++++------ src/cuda-sim/cuda-sim.cc | 30 ++++++++++++++++++ 2 files changed, 94 insertions(+), 9 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index f5708bc..ca41e68 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -522,22 +522,77 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); - assert(t != m_TextureRefToCudaArray.end()); - return t->second; + + for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); kv!= m_TextureRefToCudaArray.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f){ + + return kv->second; + } + } + + assert(false); +// std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); +// assert(t != m_TextureRefToCudaArray.end()); +// return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); - assert(t != m_TextureRefToTexureInfo.end()); - return t->second; + for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); kv!= m_TextureRefToTexureInfo.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f){ + + return kv->second; + } + } + + assert(false); +// std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); +// assert(t != m_TextureRefToTexureInfo.end()); +// return t->second; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToAttribute.find(texref); - assert(t != m_TextureRefToAttribute.end()); - return t->second; + for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f){ + + return kv->second; + } + } + + assert(false); +// std::map::const_iterator t=m_TextureRefToAttribute.find(texref); +// assert(t != m_TextureRefToAttribute.end()); +// return t->second; } const gpgpu_functional_sim_config &get_config() const { return m_function_model_config; } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 946043a..6e04ca8 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -140,6 +140,36 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { + // counts number of matches +// int normalized; +// enum cudaTextureFilterMode filterMode; +// enum cudaTextureAddressMode addressMode[3]; +// struct cudaChannelFormatDesc channelDesc; +// int x; +// int y; +// int z; +// int w; +// enum cudaChannelFormatKind f; +// int trMatches = 0; +// for (auto& kv : m_NameToTextureRef){ +// const struct textureReference* tr = kv.second; +// if (tr->normalized==texref->normalized&& +// tr->filterMode==texref->filterMode&& +// tr->addressMode[0]==texref->addressMode[0]&& +// tr->addressMode[1]==texref->addressMode[1]&& +// tr->addressMode[2]==texref->addressMode[2]&& +// tr->channelDesc.x==texref->channelDesc.x&& +// tr->channelDesc.y==texref->channelDesc.y&& +// tr->channelDesc.z==texref->channelDesc.z&& +// tr->channelDesc.w==texref->channelDesc.w&& +// tr->channelDesc.f==texref->channelDesc.f){ +// +// m_TextureRefToCudaArray[tr] = array; +// trMatches++; +// } +// } +// printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); +// assert(trMatches==1); m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; -- cgit v1.3 From 7546c12af13aca0fdcba6a339913120c0ffed50d Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 16:24:41 -0700 Subject: counting matches with same texref contents, added cuda8 fields to texref struct --- src/abstract_hardware_model.h | 143 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 130 insertions(+), 13 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index ca41e68..c21ff6d 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -25,6 +25,11 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#ifndef VERSION_EIGHT +#define VERSION_EIGHT +#endif + #ifndef ABSTRACT_HARDWARE_MODEL_INCLUDED #define ABSTRACT_HARDWARE_MODEL_INCLUDED @@ -445,6 +450,35 @@ struct textureReference { enum cudaTextureFilterMode filterMode; enum cudaTextureAddressMode addressMode[3]; struct cudaChannelFormatDesc channelDesc; + +#ifdef VERSION_EIGHT + /** + * Perform sRGB->linear conversion during texture read + */ + int sRGB; + /** + * Limit to the anisotropy ratio + */ + unsigned int maxAnisotropy; + /** + * Mipmap filter mode + */ + enum cudaTextureFilterMode mipmapFilterMode; + /** + * Offset applied to the supplied mipmap level + */ + float mipmapLevelBias; + /** + * Lower end of the mipmap level range to clamp access to + */ + float minMipmapLevelClamp; + /** + * Upper end of the mipmap level range to clamp access to + */ + float maxMipmapLevelClamp; + int __cudaReserved[15]; +#endif + }; #endif @@ -522,7 +556,8 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - + int matches = 0; + const struct cudaArray* t = NULL; for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); kv!= m_TextureRefToCudaArray.end(); kv ++){ const struct textureReference* tr = kv->first; if (tr->normalized==texref->normalized&& @@ -534,19 +569,49 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f){ - - return kv->second; + tr->channelDesc.f==texref->channelDesc.f && + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14] + ){ + matches++; + t = kv->second; + //return kv->second; } } - assert(false); + printf("matches (texarray) = %d\n", matches); + //assert(matches==1); + return t; + + //assert(false); + // std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); // assert(t != m_TextureRefToCudaArray.end()); // return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { + int matches = 0; + const struct textureInfo* t = NULL; for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); kv!= m_TextureRefToTexureInfo.end(); kv ++){ const struct textureReference* tr = kv->first; if (tr->normalized==texref->normalized&& @@ -558,13 +623,38 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f){ - - return kv->second; + tr->channelDesc.f==texref->channelDesc.f&& + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14]){ + matches++; + t = kv->second; + //return kv->second; } } - assert(false); + printf("matches (texinfo) = %d\n", matches); + //assert(matches==1); + return t; + // std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); // assert(t != m_TextureRefToTexureInfo.end()); // return t->second; @@ -572,6 +662,8 @@ public: const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { + int matches = 0; + const struct textureReferenceAttr* t = NULL; for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ const struct textureReference* tr = kv->first; if (tr->normalized==texref->normalized&& @@ -583,13 +675,38 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f){ - - return kv->second; + tr->channelDesc.f==texref->channelDesc.f&& + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14]){ + matches++; + t = kv->second; + //return kv->second; } } - assert(false); + printf("matches (texattr) = %d\n", matches); + //assert(matches==1); + return t; + // std::map::const_iterator t=m_TextureRefToAttribute.find(texref); // assert(t != m_TextureRefToAttribute.end()); // return t->second; -- cgit v1.3 From 9476c4ccf17949a67a430155dfc93e66ca73d4a8 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 16:26:55 -0700 Subject: abstract_hardware_model.h:texrefAttr is different and can be searched via pointer cuda-sim.cc: counts matches between cudaBinTextureToArray texref param (pointer) to texref pointers in m_NameToTextureRef --- src/abstract_hardware_model.h | 94 +++++++++++++++++++++---------------------- src/cuda-sim/cuda-sim.cc | 47 +++++++++++++++++----- 2 files changed, 84 insertions(+), 57 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index c21ff6d..608a7e2 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -662,54 +662,54 @@ public: const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { - int matches = 0; - const struct textureReferenceAttr* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f&& - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14]){ - matches++; - t = kv->second; - //return kv->second; - } - } - - printf("matches (texattr) = %d\n", matches); - //assert(matches==1); - return t; +// int matches = 0; +// const struct textureReferenceAttr* t = NULL; +// for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ +// const struct textureReference* tr = kv->first; +// if (tr->normalized==texref->normalized&& +// tr->filterMode==texref->filterMode&& +// tr->addressMode[0]==texref->addressMode[0]&& +// tr->addressMode[1]==texref->addressMode[1]&& +// tr->addressMode[2]==texref->addressMode[2]&& +// tr->channelDesc.x==texref->channelDesc.x&& +// tr->channelDesc.y==texref->channelDesc.y&& +// tr->channelDesc.z==texref->channelDesc.z&& +// tr->channelDesc.w==texref->channelDesc.w&& +// tr->channelDesc.f==texref->channelDesc.f&& +// tr->sRGB==texref->sRGB&& +// tr->maxAnisotropy==texref->maxAnisotropy&& +// tr->mipmapFilterMode==texref->mipmapFilterMode&& +// tr->mipmapLevelBias==texref->mipmapLevelBias&& +// tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& +// tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& +// tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& +// tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& +// tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& +// tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& +// tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& +// tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& +// tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& +// tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& +// tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& +// tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& +// tr->__cudaReserved[10]==texref->__cudaReserved[10]&& +// tr->__cudaReserved[11]==texref->__cudaReserved[11]&& +// tr->__cudaReserved[12]==texref->__cudaReserved[12]&& +// tr->__cudaReserved[13]==texref->__cudaReserved[13]&& +// tr->__cudaReserved[14]==texref->__cudaReserved[14]){ +// matches++; +// t = kv->second; +// //return kv->second; +// } +// } +// +// printf("matches (texattr) = %d\n", matches); +// //assert(matches==1); +// return t; -// std::map::const_iterator t=m_TextureRefToAttribute.find(texref); -// assert(t != m_TextureRefToAttribute.end()); -// return t->second; + std::map::const_iterator t=m_TextureRefToAttribute.find(texref); + assert(t != m_TextureRefToAttribute.end()); + return t->second; } const gpgpu_functional_sim_config &get_config() const { return m_function_model_config; } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 6e04ca8..39ffa63 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -26,6 +26,10 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +#ifndef VERSION_EIGHT +#define VERSION_EIGHT +#endif + #include "cuda-sim.h" #include "instructions.h" @@ -104,6 +108,16 @@ static address_type get_converge_point(address_type pc); void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) { + +//#ifdef VERSION_EIGHT +// int i; +// printf("%s ", name); +// printf("__cudaReserved:"); +// for (i = 0; i<15; i++){ +// printf(" %i", texref->__cudaReserved[i]); +// } +// printf("\n"); +//#endif std::string texname(name); m_NameToTextureRef[texname] = texref; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); @@ -140,16 +154,15 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { +//#ifdef VERSION_EIGHT +// int i; +// printf("__cudaReserved:"); +// for (i = 0; i<15; i++){ +// printf(" %i", texref->__cudaReserved[i]); +// } +// printf("\n"); +//#endif // counts number of matches -// int normalized; -// enum cudaTextureFilterMode filterMode; -// enum cudaTextureAddressMode addressMode[3]; -// struct cudaChannelFormatDesc channelDesc; -// int x; -// int y; -// int z; -// int w; -// enum cudaChannelFormatKind f; // int trMatches = 0; // for (auto& kv : m_NameToTextureRef){ // const struct textureReference* tr = kv.second; @@ -170,7 +183,21 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te // } // printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); // assert(trMatches==1); - m_TextureRefToCudaArray[texref] = array; + + //tests if texref pointer matches any pointer in m_NameToTextureRef map + int trMatches = 0; + for (auto& kv : m_NameToTextureRef){ + const struct textureReference* tr = kv.second; + if (tr==texref){ + m_TextureRefToCudaArray[tr] = array; + //printf("%s\n", kv.first); + trMatches++; + } + } + printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); + //assert(trMatches==1); + + //m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; unsigned int Tx, Ty; -- cgit v1.3 From ab1f21e94756b4276e97124a7f2af6bec645c81e Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 16:49:55 -0700 Subject: changed for loop, pass pipeline? --- 0517_13-24cudaReserved.log | 0 517-1418cudaReserved.log | 0 src/cuda-sim/cuda-sim.cc | 6 +++--- 3 files changed, 3 insertions(+), 3 deletions(-) create mode 100644 0517_13-24cudaReserved.log create mode 100644 517-1418cudaReserved.log diff --git a/0517_13-24cudaReserved.log b/0517_13-24cudaReserved.log new file mode 100644 index 0000000..e69de29 diff --git a/517-1418cudaReserved.log b/517-1418cudaReserved.log new file mode 100644 index 0000000..e69de29 diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 39ffa63..656091c 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -186,11 +186,11 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te //tests if texref pointer matches any pointer in m_NameToTextureRef map int trMatches = 0; - for (auto& kv : m_NameToTextureRef){ - const struct textureReference* tr = kv.second; + for (std::map::const_iterator kv = m_NameToTextureRef.begin(); kv!= m_NameToTextureRef.end(); kv ++){ + const struct textureReference* tr = kv->second; if (tr==texref){ m_TextureRefToCudaArray[tr] = array; - //printf("%s\n", kv.first); + printf("%s\n", kv->first.c_str()); trMatches++; } } -- cgit v1.3 From c8a6dfa9bb8bcec0458a58f0b702cd7b739ac1f1 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 18 May 2018 10:50:19 -0700 Subject: reverted cuda8 changes (extra fields) and assert texture bug fix's assumption --- src/abstract_hardware_model.h | 134 ++++++++++++++---------------------------- src/cuda-sim/cuda-sim.cc | 59 +------------------ 2 files changed, 45 insertions(+), 148 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 608a7e2..412c0a8 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -451,33 +451,32 @@ struct textureReference { enum cudaTextureAddressMode addressMode[3]; struct cudaChannelFormatDesc channelDesc; -#ifdef VERSION_EIGHT - /** - * Perform sRGB->linear conversion during texture read - */ - int sRGB; - /** - * Limit to the anisotropy ratio - */ - unsigned int maxAnisotropy; - /** - * Mipmap filter mode - */ - enum cudaTextureFilterMode mipmapFilterMode; - /** - * Offset applied to the supplied mipmap level - */ - float mipmapLevelBias; - /** - * Lower end of the mipmap level range to clamp access to - */ - float minMipmapLevelClamp; - /** - * Upper end of the mipmap level range to clamp access to - */ - float maxMipmapLevelClamp; - int __cudaReserved[15]; -#endif +//following commented section applies only to CUDA_VERSION 8+ +// /** +// * Perform sRGB->linear conversion during texture read +// */ +// int sRGB; +// /** +// * Limit to the anisotropy ratio +// */ +// unsigned int maxAnisotropy; +// /** +// * Mipmap filter mode +// */ +// enum cudaTextureFilterMode mipmapFilterMode; +// /** +// * Offset applied to the supplied mipmap level +// */ +// float mipmapLevelBias; +// /** +// * Lower end of the mipmap level range to clamp access to +// */ +// float minMipmapLevelClamp; +// /** +// * Upper end of the mipmap level range to clamp access to +// */ +// float maxMipmapLevelClamp; +// int __cudaReserved[15]; }; @@ -569,7 +568,10 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f && + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && tr->sRGB==texref->sRGB&& tr->maxAnisotropy==texref->maxAnisotropy&& tr->mipmapFilterMode==texref->mipmapFilterMode&& @@ -591,6 +593,7 @@ public: tr->__cudaReserved[12]==texref->__cudaReserved[12]&& tr->__cudaReserved[13]==texref->__cudaReserved[13]&& tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ ){ matches++; t = kv->second; @@ -598,15 +601,9 @@ public: } } - printf("matches (texarray) = %d\n", matches); - //assert(matches==1); + //printf("matches (texarray) = %d\n", matches); + assert(matches==1); return t; - - //assert(false); - -// std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); -// assert(t != m_TextureRefToCudaArray.end()); -// return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { @@ -623,7 +620,10 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f&& + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && tr->sRGB==texref->sRGB&& tr->maxAnisotropy==texref->maxAnisotropy&& tr->mipmapFilterMode==texref->mipmapFilterMode&& @@ -644,69 +644,23 @@ public: tr->__cudaReserved[11]==texref->__cudaReserved[11]&& tr->__cudaReserved[12]==texref->__cudaReserved[12]&& tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14]){ + tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ + ){ matches++; t = kv->second; - //return kv->second; } } - printf("matches (texinfo) = %d\n", matches); - //assert(matches==1); + //printf("matches (texinfo) = %d\n", matches); + assert(matches==1); return t; - -// std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); -// assert(t != m_TextureRefToTexureInfo.end()); -// return t->second; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { -// int matches = 0; -// const struct textureReferenceAttr* t = NULL; -// for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ -// const struct textureReference* tr = kv->first; -// if (tr->normalized==texref->normalized&& -// tr->filterMode==texref->filterMode&& -// tr->addressMode[0]==texref->addressMode[0]&& -// tr->addressMode[1]==texref->addressMode[1]&& -// tr->addressMode[2]==texref->addressMode[2]&& -// tr->channelDesc.x==texref->channelDesc.x&& -// tr->channelDesc.y==texref->channelDesc.y&& -// tr->channelDesc.z==texref->channelDesc.z&& -// tr->channelDesc.w==texref->channelDesc.w&& -// tr->channelDesc.f==texref->channelDesc.f&& -// tr->sRGB==texref->sRGB&& -// tr->maxAnisotropy==texref->maxAnisotropy&& -// tr->mipmapFilterMode==texref->mipmapFilterMode&& -// tr->mipmapLevelBias==texref->mipmapLevelBias&& -// tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& -// tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& -// tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& -// tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& -// tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& -// tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& -// tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& -// tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& -// tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& -// tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& -// tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& -// tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& -// tr->__cudaReserved[10]==texref->__cudaReserved[10]&& -// tr->__cudaReserved[11]==texref->__cudaReserved[11]&& -// tr->__cudaReserved[12]==texref->__cudaReserved[12]&& -// tr->__cudaReserved[13]==texref->__cudaReserved[13]&& -// tr->__cudaReserved[14]==texref->__cudaReserved[14]){ -// matches++; -// t = kv->second; -// //return kv->second; -// } -// } -// -// printf("matches (texattr) = %d\n", matches); -// //assert(matches==1); -// return t; - + //note textureReferenceAttr map behaves differently from cudaArray and + //textureInfo maps std::map::const_iterator t=m_TextureRefToAttribute.find(texref); assert(t != m_TextureRefToAttribute.end()); return t->second; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 656091c..946043a 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -26,10 +26,6 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -#ifndef VERSION_EIGHT -#define VERSION_EIGHT -#endif - #include "cuda-sim.h" #include "instructions.h" @@ -108,16 +104,6 @@ static address_type get_converge_point(address_type pc); void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) { - -//#ifdef VERSION_EIGHT -// int i; -// printf("%s ", name); -// printf("__cudaReserved:"); -// for (i = 0; i<15; i++){ -// printf(" %i", texref->__cudaReserved[i]); -// } -// printf("\n"); -//#endif std::string texname(name); m_NameToTextureRef[texname] = texref; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); @@ -154,50 +140,7 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { -//#ifdef VERSION_EIGHT -// int i; -// printf("__cudaReserved:"); -// for (i = 0; i<15; i++){ -// printf(" %i", texref->__cudaReserved[i]); -// } -// printf("\n"); -//#endif - // counts number of matches -// int trMatches = 0; -// for (auto& kv : m_NameToTextureRef){ -// const struct textureReference* tr = kv.second; -// if (tr->normalized==texref->normalized&& -// tr->filterMode==texref->filterMode&& -// tr->addressMode[0]==texref->addressMode[0]&& -// tr->addressMode[1]==texref->addressMode[1]&& -// tr->addressMode[2]==texref->addressMode[2]&& -// tr->channelDesc.x==texref->channelDesc.x&& -// tr->channelDesc.y==texref->channelDesc.y&& -// tr->channelDesc.z==texref->channelDesc.z&& -// tr->channelDesc.w==texref->channelDesc.w&& -// tr->channelDesc.f==texref->channelDesc.f){ -// -// m_TextureRefToCudaArray[tr] = array; -// trMatches++; -// } -// } -// printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); -// assert(trMatches==1); - - //tests if texref pointer matches any pointer in m_NameToTextureRef map - int trMatches = 0; - for (std::map::const_iterator kv = m_NameToTextureRef.begin(); kv!= m_NameToTextureRef.end(); kv ++){ - const struct textureReference* tr = kv->second; - if (tr==texref){ - m_TextureRefToCudaArray[tr] = array; - printf("%s\n", kv->first.c_str()); - trMatches++; - } - } - printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); - //assert(trMatches==1); - - //m_TextureRefToCudaArray[texref] = array; + m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; unsigned int Tx, Ty; -- cgit v1.3 From 9f6bfadf5c0b07d66b002e966940f9620f8b5623 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 18 May 2018 11:52:31 -0700 Subject: implemented unbind, currently only affects cudaArray map --- 0517_13-24cudaReserved.log | 0 517-1418cudaReserved.log | 0 libcuda/cuda_runtime_api.cc | 11 +++++++++++ src/abstract_hardware_model.h | 1 + src/cuda-sim/cuda-sim.cc | 5 +++++ 5 files changed, 17 insertions(+) delete mode 100644 0517_13-24cudaReserved.log delete mode 100644 517-1418cudaReserved.log diff --git a/0517_13-24cudaReserved.log b/0517_13-24cudaReserved.log deleted file mode 100644 index e69de29..0000000 diff --git a/517-1418cudaReserved.log b/517-1418cudaReserved.log deleted file mode 100644 index e69de29..0000000 diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index ef46f00..292d43d 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1002,6 +1002,14 @@ __host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureRefere __host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) { + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + printf("GPGPU-Sim PTX: in cudaUnbindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); + printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); + const struct cudaArray* array = gpu->get_texarray(texref); + printf("GPGPU-Sim PTX: texref = %p, array = %p\n", texref, array); + + gpu->gpgpu_ptx_sim_unbindTexture(texref); return g_last_cudaError = cudaSuccess; } @@ -2084,10 +2092,12 @@ void __cudaUnregisterFatBinary(void **fatCubinHandle) cudaError_t cudaDeviceReset ( void ) { // Should reset the simulated GPU + // TODO: Implement return g_last_cudaError = cudaSuccess; } cudaError_t CUDARTAPI cudaDeviceSynchronize(void){ // I don't know what this should do + // TODO: Implement return g_last_cudaError = cudaSuccess; } @@ -2189,6 +2199,7 @@ typedef unsigned long GLuint; cudaError_t cudaGLRegisterBufferObject(GLuint bufferObj) { printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); + // TODO: Implement return g_last_cudaError = cudaSuccess; } diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 412c0a8..3ef450e 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -544,6 +544,7 @@ public: class memory_space *get_surf_memory() { return m_surf_mem; } void gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array); + void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); void gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 946043a..ef16f43 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -183,6 +183,11 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te m_TextureRefToTexureInfo[texref] = texInfo; } +void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) +{ + m_TextureRefToCudaArray.erase(texref); +} + unsigned g_assemble_code_next_pc=0; std::map g_pc_to_finfo; std::vector function_info::s_g_pc_to_insn; -- cgit v1.3 From f754ad8e135befe98998193121fff6cb4c22fe25 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 18 May 2018 14:41:23 -0700 Subject: erase texinfo in unbind and disable assert --- src/abstract_hardware_model.h | 195 ++++++++++++++++++++++-------------------- src/cuda-sim/cuda-sim.cc | 2 + 2 files changed, 104 insertions(+), 93 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 3ef450e..6dd5436 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -556,106 +556,115 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - int matches = 0; - const struct cudaArray* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); kv!= m_TextureRefToCudaArray.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; - //return kv->second; + + std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); + if(t != m_TextureRefToCudaArray.end()){ + return t->second; + } else{ + int matches = 0; + const struct cudaArray* t = NULL; + for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); + kv!= m_TextureRefToCudaArray.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ + ){ + matches++; + t = kv->second; + } } + + //assert(matches==1); + return t; } - - //printf("matches (texarray) = %d\n", matches); - assert(matches==1); - return t; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { - int matches = 0; - const struct textureInfo* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); kv!= m_TextureRefToTexureInfo.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; + std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); + if(t != m_TextureRefToTexureInfo.end()){ + return t->second; + }else{ + int matches = 0; + const struct textureInfo* t = NULL; + for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); + kv!= m_TextureRefToTexureInfo.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ + ){ + matches++; + t = kv->second; + } } + //assert(matches==1); + return t; } - - //printf("matches (texinfo) = %d\n", matches); - assert(matches==1); - return t; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index ef16f43..6bdf75f 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -140,6 +140,7 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { + printf("GPGPU-Simm PTX: name from texture = %s\n", gpgpu_ptx_sim_findNamefromTexture(texref)); m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; @@ -186,6 +187,7 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) { m_TextureRefToCudaArray.erase(texref); + m_TextureRefToTexureInfo.erase(texref); } unsigned g_assemble_code_next_pc=0; -- cgit v1.3 From 5fd987fc8e551b823b0299e0cd3ce0d161fb84b6 Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Fri, 18 May 2018 20:28:02 -0500 Subject: ld operand in register space --- src/cuda-sim/instructions.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index e53aaab..583a49a 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2368,7 +2368,11 @@ void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand space = param_space_kernel; else if( ti.is_param_local() ) { space = param_space_local; - } else { + } + else if( ti.is_reg() ) { + space = param_space_kernel; + } + else { printf("GPGPU-Sim PTX: ERROR ** cannot resolve .param space for '%s'\n", s->name().c_str() ); abort(); } -- cgit v1.3 -- cgit v1.3 From 7c57ad4c1186d28ccc7fb7ea45f66007f2903bf2 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 09:49:26 -0700 Subject: revert to before texture bug --- libcuda/cuda_runtime_api.cc | 11 ---- src/abstract_hardware_model.h | 144 ++---------------------------------------- src/cuda-sim/cuda-sim.cc | 7 -- 3 files changed, 4 insertions(+), 158 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 292d43d..ef46f00 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1002,14 +1002,6 @@ __host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureRefere __host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) { - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - printf("GPGPU-Sim PTX: in cudaUnbindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); - printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); - const struct cudaArray* array = gpu->get_texarray(texref); - printf("GPGPU-Sim PTX: texref = %p, array = %p\n", texref, array); - - gpu->gpgpu_ptx_sim_unbindTexture(texref); return g_last_cudaError = cudaSuccess; } @@ -2092,12 +2084,10 @@ void __cudaUnregisterFatBinary(void **fatCubinHandle) cudaError_t cudaDeviceReset ( void ) { // Should reset the simulated GPU - // TODO: Implement return g_last_cudaError = cudaSuccess; } cudaError_t CUDARTAPI cudaDeviceSynchronize(void){ // I don't know what this should do - // TODO: Implement return g_last_cudaError = cudaSuccess; } @@ -2199,7 +2189,6 @@ typedef unsigned long GLuint; cudaError_t cudaGLRegisterBufferObject(GLuint bufferObj) { printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); - // TODO: Implement return g_last_cudaError = cudaSuccess; } diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 6dd5436..f5708bc 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -25,11 +25,6 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -#ifndef VERSION_EIGHT -#define VERSION_EIGHT -#endif - #ifndef ABSTRACT_HARDWARE_MODEL_INCLUDED #define ABSTRACT_HARDWARE_MODEL_INCLUDED @@ -450,34 +445,6 @@ struct textureReference { enum cudaTextureFilterMode filterMode; enum cudaTextureAddressMode addressMode[3]; struct cudaChannelFormatDesc channelDesc; - -//following commented section applies only to CUDA_VERSION 8+ -// /** -// * Perform sRGB->linear conversion during texture read -// */ -// int sRGB; -// /** -// * Limit to the anisotropy ratio -// */ -// unsigned int maxAnisotropy; -// /** -// * Mipmap filter mode -// */ -// enum cudaTextureFilterMode mipmapFilterMode; -// /** -// * Offset applied to the supplied mipmap level -// */ -// float mipmapLevelBias; -// /** -// * Lower end of the mipmap level range to clamp access to -// */ -// float minMipmapLevelClamp; -// /** -// * Upper end of the mipmap level range to clamp access to -// */ -// float maxMipmapLevelClamp; -// int __cudaReserved[15]; - }; #endif @@ -544,7 +511,6 @@ public: class memory_space *get_surf_memory() { return m_surf_mem; } void gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array); - void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); void gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); @@ -556,121 +522,19 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); - if(t != m_TextureRefToCudaArray.end()){ - return t->second; - } else{ - int matches = 0; - const struct cudaArray* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); - kv!= m_TextureRefToCudaArray.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; - } - } - - //assert(matches==1); - return t; - } + assert(t != m_TextureRefToCudaArray.end()); + return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); - if(t != m_TextureRefToTexureInfo.end()){ - return t->second; - }else{ - int matches = 0; - const struct textureInfo* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); - kv!= m_TextureRefToTexureInfo.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; - } - } - //assert(matches==1); - return t; - } + assert(t != m_TextureRefToTexureInfo.end()); + return t->second; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { - //note textureReferenceAttr map behaves differently from cudaArray and - //textureInfo maps std::map::const_iterator t=m_TextureRefToAttribute.find(texref); assert(t != m_TextureRefToAttribute.end()); return t->second; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 6bdf75f..946043a 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -140,7 +140,6 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { - printf("GPGPU-Simm PTX: name from texture = %s\n", gpgpu_ptx_sim_findNamefromTexture(texref)); m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; @@ -184,12 +183,6 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te m_TextureRefToTexureInfo[texref] = texInfo; } -void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) -{ - m_TextureRefToCudaArray.erase(texref); - m_TextureRefToTexureInfo.erase(texref); -} - unsigned g_assemble_code_next_pc=0; std::map g_pc_to_finfo; std::vector function_info::s_g_pc_to_insn; -- cgit v1.3 From 26ab318c443339e14940772c2199e486411d12ed Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 09:56:07 -0700 Subject: unbind implementation --- libcuda/cuda_runtime_api.cc | 11 ++++++++--- src/abstract_hardware_model.h | 1 + src/cuda-sim/cuda-sim.cc | 6 ++++++ src/cuda-sim/instructions.cc | 2 +- 4 files changed, 16 insertions(+), 4 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index ef46f00..fa5a523 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1000,9 +1000,14 @@ __host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureRefere return g_last_cudaError = cudaSuccess; } -__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) -{ - return g_last_cudaError = cudaSuccess; +__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) { + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + printf("GPGPU-Sim PTX: in cudaUnbindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); + printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); + + gpu->gpgpu_ptx_sim_unbindTexture(texref); + return g_last_cudaError = cudaSuccess; } __host__ cudaError_t CUDARTAPI cudaGetTextureAlignmentOffset(size_t *offset, const struct textureReference *texref) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index f5708bc..ab94ded 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -512,6 +512,7 @@ public: void gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array); void gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext); + void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); const struct textureReference* get_texref(const std::string &texname) const diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 946043a..6125422 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -183,6 +183,12 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te m_TextureRefToTexureInfo[texref] = texInfo; } +void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) +{ + m_TextureRefToCudaArray.erase(texref); + m_TextureRefToTexureInfo.erase(texref); +} + unsigned g_assemble_code_next_pc=0; std::map g_pc_to_finfo; std::vector function_info::s_g_pc_to_insn; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 8a3539b..31162b4 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2368,7 +2368,7 @@ void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand space = param_space_kernel; else if( ti.is_param_local() ) space = param_space_local; - else if( ti.is_reg() ) + else if( ti.is_reg() ) space = param_space_kernel; else { printf("GPGPU-Sim PTX: ERROR ** cannot resolve .param space for '%s'\n", s->name().c_str() ); -- cgit v1.3 From 91db4fc3b6a3ef4c4a330736896e498694fc3455 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 14:00:59 -0700 Subject: restructured texref maps to fix texture bug --- src/abstract_hardware_model.h | 36 +++++++++++++++++-------------- src/cuda-sim/cuda-sim.cc | 49 ++++++++++++++++++++++++++++--------------- src/cuda-sim/instructions.cc | 6 +++--- 3 files changed, 55 insertions(+), 36 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index ab94ded..d0af1ea 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -65,6 +65,7 @@ enum FuncCache #include #include +#include typedef unsigned long long new_addr_type; typedef unsigned address_type; @@ -515,29 +516,31 @@ public: void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); - const struct textureReference* get_texref(const std::string &texname) const + const struct textureReference* get_texref( const std::string &texname ) const { - std::map::const_iterator t=m_NameToTextureRef.find(texname); + std::map >::const_iterator t=m_NameToTextureRef.find(texname); assert( t != m_NameToTextureRef.end() ); - return t->second; + return *(t->second.begin()); } - const struct cudaArray* get_texarray( const struct textureReference *texref ) const + + const struct cudaArray* get_texarray( const std::string &texname ) const { - std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); - assert(t != m_TextureRefToCudaArray.end()); + std::map::const_iterator t=m_NameToCudaArray.find(texname); + assert(t != m_NameToCudaArray.end()); return t->second; } - const struct textureInfo* get_texinfo( const struct textureReference *texref ) const + + const struct textureInfo* get_texinfo( const std::string &texname ) const { - std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); - assert(t != m_TextureRefToTexureInfo.end()); + std::map::const_iterator t=m_NameToTexureInfo.find(texname); + assert(t != m_NameToTexureInfo.end()); return t->second; } - const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const + const struct textureReferenceAttr* get_texattr( const std::string &texname ) const { - std::map::const_iterator t=m_TextureRefToAttribute.find(texref); - assert(t != m_TextureRefToAttribute.end()); + std::map::const_iterator t=m_NameToAttribute.find(texname); + assert(t != m_NameToAttribute.end()); return t->second; } @@ -554,10 +557,11 @@ protected: unsigned long long m_dev_malloc; - std::map m_NameToTextureRef; - std::map m_TextureRefToCudaArray; - std::map m_TextureRefToTexureInfo; - std::map m_TextureRefToAttribute; + std::map > m_NameToTextureRef; + std::map m_TextureRefToName; + std::map m_NameToCudaArray; + std::map m_NameToTexureInfo; + std::map m_NameToAttribute; }; struct gpgpu_ptx_sim_info diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 6125422..05b6201 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -105,22 +105,36 @@ static address_type get_converge_point(address_type pc); void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) { std::string texname(name); - m_NameToTextureRef[texname] = texref; + if (m_NameToTextureRef.find(texname)==m_NameToTextureRef.end()){ + m_NameToTextureRef[texname] = std::set(); + m_NameToTextureRef[texname].insert(texref); + }else{ + const struct textureReference* tr = *m_NameToTextureRef[texname].begin(); + assert(tr!=NULL); + //asserts that all texrefs in set have same fields + assert(tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f + ); + m_NameToTextureRef[texname].insert(texref); + } + m_TextureRefToName[texref] = texname; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); - m_TextureRefToAttribute[texref] = texAttr; + m_NameToAttribute[texname] = texAttr; } const char* gpgpu_t::gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref) { - std::map::iterator itr = m_NameToTextureRef.begin(); - while (itr != m_NameToTextureRef.end()) { - if ((*itr).second == texref) { - const char *p = ((*itr).first).c_str(); - return p; - } - itr++; - } - return NULL; + std::map::const_iterator t=m_TextureRefToName.find(texref); + assert( t != m_TextureRefToName.end() ); + return t->second.c_str(); } unsigned int intLOGB2( unsigned int v ) { @@ -140,7 +154,8 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { - m_TextureRefToCudaArray[texref] = array; + std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); + m_NameToCudaArray[texname] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; unsigned int Tx, Ty; @@ -180,13 +195,14 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te texInfo->Ty_numbits = intLOGB2(Ty); texInfo->texel_size = texel_size; texInfo->texel_size_numbits = intLOGB2(texel_size); - m_TextureRefToTexureInfo[texref] = texInfo; + m_NameToTexureInfo[texname] = texInfo; } void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) { - m_TextureRefToCudaArray.erase(texref); - m_TextureRefToTexureInfo.erase(texref); + std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); + m_NameToCudaArray.erase(texname); + m_NameToTexureInfo.erase(texname); } unsigned g_assemble_code_next_pc=0; @@ -1246,8 +1262,7 @@ static unsigned get_tex_datasize( const ptx_instruction *pI, ptx_thread_info *th std::string texname = src1.name(); gpgpu_t *gpu = thread->get_gpu(); - const struct textureReference* texref = gpu->get_texref(texname); - const struct textureInfo* texInfo = gpu->get_texinfo(texref); + const struct textureInfo* texInfo = gpu->get_texinfo(texname); unsigned data_size = texInfo->texel_size; return data_size; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 31162b4..ac9b387 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -4098,9 +4098,9 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread ) gpgpu_t *gpu = thread->get_gpu(); const struct textureReference* texref = gpu->get_texref(texname); - const struct cudaArray* cuArray = gpu->get_texarray(texref); - const struct textureInfo* texInfo = gpu->get_texinfo(texref); - const struct textureReferenceAttr* texAttr = gpu->get_texattr(texref); + const struct cudaArray* cuArray = gpu->get_texarray(texname); + const struct textureInfo* texInfo = gpu->get_texinfo(texname); + const struct textureReferenceAttr* texAttr = gpu->get_texattr(texname); //assume always 2D f32 input //access array with src2 coordinates -- cgit v1.3 From 1d37aee592b621c3113dc878403dfd1ccf547746 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 17:27:28 -0700 Subject: cudaStreamWaitEvent tentative implementation --- libcuda/cuda_runtime_api.cc | 20 ++++++++++++++++++++ src/cuda-sim/cuda-sim.cc | 3 +-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index fa5a523..f597a15 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1168,6 +1168,26 @@ __host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) #endif } +__host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) +{ + +#if (CUDART_VERSION >= 3000) + if( stream == NULL ) + return g_last_cudaError = cudaErrorInvalidResourceHandle; + return g_last_cudaError = stream->empty()?cudaSuccess:cudaErrorNotReady; +#else + printf("GPGPU-Sim API: cudaStreamWaitEvent ** waiting for event\n"); + fflush(stdout); + CUevent_st *e = (CUevent_st*) event; + while( !e->done() ) + ; + printf("GPGPU-Sim API: cudaStreamWaitEvent ** event detected\n"); + fflush(stdout); + printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); + return g_last_cudaError = cudaSuccess; // it is always success because all cuda calls are synchronous +#endif +} + /******************************************************************************* * * * * diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 05b6201..0e14dd0 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -107,7 +107,6 @@ void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct tex std::string texname(name); if (m_NameToTextureRef.find(texname)==m_NameToTextureRef.end()){ m_NameToTextureRef[texname] = std::set(); - m_NameToTextureRef[texname].insert(texref); }else{ const struct textureReference* tr = *m_NameToTextureRef[texname].begin(); assert(tr!=NULL); @@ -123,8 +122,8 @@ void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct tex tr->channelDesc.w==texref->channelDesc.w&& tr->channelDesc.f==texref->channelDesc.f ); - m_NameToTextureRef[texname].insert(texref); } + m_NameToTextureRef[texname].insert(texref); m_TextureRefToName[texref] = texname; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); m_NameToAttribute[texname] = texAttr; -- cgit v1.3 From 7dc5e8fba40a30d7e5d7299646332482136a477b Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 22:31:13 -0700 Subject: gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 428abce..0e2a898 100644 --- a/.gitignore +++ b/.gitignore @@ -32,4 +32,5 @@ build/* *~ cscope* tags +regression.sh -- cgit v1.3 From 835b78988ce1797e394cb1b169db83e7d0fc1038 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Wed, 23 May 2018 10:04:11 -0700 Subject: assertions and comments that allow the current unbind implementation to behave correctly --- src/cuda-sim/cuda-sim.cc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 0e14dd0..2a197c3 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -154,6 +154,10 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); + + std::map::const_iterator t=m_NameToCudaArray.find(texname); + //check that there's nothing there first + assert(t == m_NameToCudaArray.end()); m_NameToCudaArray[texname] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; @@ -199,6 +203,7 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) { + //assumes bind-use-unbind-bind-use-unbind pattern std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); m_NameToCudaArray.erase(texname); m_NameToTexureInfo.erase(texname); -- cgit v1.3 From 9636bbfef261c732c990b7159c9ad699888f5553 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Wed, 23 May 2018 11:14:42 -0700 Subject: unimplement cudaStreaWaitEvent because I don't know what I'm doing --- libcuda/cuda_runtime_api.cc | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index f597a15..e61ed0b 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1170,22 +1170,8 @@ __host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) __host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) { - -#if (CUDART_VERSION >= 3000) - if( stream == NULL ) - return g_last_cudaError = cudaErrorInvalidResourceHandle; - return g_last_cudaError = stream->empty()?cudaSuccess:cudaErrorNotReady; -#else - printf("GPGPU-Sim API: cudaStreamWaitEvent ** waiting for event\n"); - fflush(stdout); - CUevent_st *e = (CUevent_st*) event; - while( !e->done() ) - ; - printf("GPGPU-Sim API: cudaStreamWaitEvent ** event detected\n"); - fflush(stdout); - printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); - return g_last_cudaError = cudaSuccess; // it is always success because all cuda calls are synchronous -#endif + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; } /******************************************************************************* -- cgit v1.3 From 64e80dd0c771dce517973ec0a27eb01238f4d8e6 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 24 May 2018 15:35:05 -0700 Subject: changed assertion to warning when binding to previously bound name. --- src/cuda-sim/cuda-sim.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 2a197c3..34368ce 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -157,7 +157,9 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te std::map::const_iterator t=m_NameToCudaArray.find(texname); //check that there's nothing there first - assert(t == m_NameToCudaArray.end()); + if(t != m_NameToCudaArray.end()){ + printf("GPGPU-Sim PTX: Warning: binding to texref associated with %s, which was previously bound.\nImplicitly unbinding texref associated to %s first\n", texname.c_str(), texname.c_str()); + } m_NameToCudaArray[texname] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; -- cgit v1.3 From a9f90b837af13e205886c19696f779e15e2499b0 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Wed, 16 May 2018 13:36:15 -0700 Subject: is_reg change --- .gitignore | 4 ++++ src/cuda-sim/instructions.cc | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 887b605..428abce 100644 --- a/.gitignore +++ b/.gitignore @@ -29,3 +29,7 @@ cuobjdump_to_ptxplus/sass_parser.output build/* *.swp +*~ +cscope* +tags + diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 583a49a..86951ed 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2366,7 +2366,7 @@ void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand type_info_key ti = t->get_key(); if( ti.is_param_kernel() ) space = param_space_kernel; - else if( ti.is_param_local() ) { + else if( ti.is_param_local() ) space = param_space_local; } else if( ti.is_reg() ) { -- cgit v1.3 From 4fb2d23f350bd8921417f5c09bde73594e5c8a0b Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 09:27:07 -0700 Subject: allows gpgpusim to select a set of texture array,attr,info but maybe not the right one --- src/abstract_hardware_model.h | 73 +++++++++++++++++++++++++++++++++++++------ src/cuda-sim/cuda-sim.cc | 30 ++++++++++++++++++ 2 files changed, 94 insertions(+), 9 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index f5708bc..ca41e68 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -522,22 +522,77 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); - assert(t != m_TextureRefToCudaArray.end()); - return t->second; + + for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); kv!= m_TextureRefToCudaArray.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f){ + + return kv->second; + } + } + + assert(false); +// std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); +// assert(t != m_TextureRefToCudaArray.end()); +// return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); - assert(t != m_TextureRefToTexureInfo.end()); - return t->second; + for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); kv!= m_TextureRefToTexureInfo.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f){ + + return kv->second; + } + } + + assert(false); +// std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); +// assert(t != m_TextureRefToTexureInfo.end()); +// return t->second; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToAttribute.find(texref); - assert(t != m_TextureRefToAttribute.end()); - return t->second; + for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f){ + + return kv->second; + } + } + + assert(false); +// std::map::const_iterator t=m_TextureRefToAttribute.find(texref); +// assert(t != m_TextureRefToAttribute.end()); +// return t->second; } const gpgpu_functional_sim_config &get_config() const { return m_function_model_config; } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 946043a..6e04ca8 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -140,6 +140,36 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { + // counts number of matches +// int normalized; +// enum cudaTextureFilterMode filterMode; +// enum cudaTextureAddressMode addressMode[3]; +// struct cudaChannelFormatDesc channelDesc; +// int x; +// int y; +// int z; +// int w; +// enum cudaChannelFormatKind f; +// int trMatches = 0; +// for (auto& kv : m_NameToTextureRef){ +// const struct textureReference* tr = kv.second; +// if (tr->normalized==texref->normalized&& +// tr->filterMode==texref->filterMode&& +// tr->addressMode[0]==texref->addressMode[0]&& +// tr->addressMode[1]==texref->addressMode[1]&& +// tr->addressMode[2]==texref->addressMode[2]&& +// tr->channelDesc.x==texref->channelDesc.x&& +// tr->channelDesc.y==texref->channelDesc.y&& +// tr->channelDesc.z==texref->channelDesc.z&& +// tr->channelDesc.w==texref->channelDesc.w&& +// tr->channelDesc.f==texref->channelDesc.f){ +// +// m_TextureRefToCudaArray[tr] = array; +// trMatches++; +// } +// } +// printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); +// assert(trMatches==1); m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; -- cgit v1.3 From d36216db7a9d1d2360acf00afb5303b1f76fb7c7 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 16:24:41 -0700 Subject: counting matches with same texref contents, added cuda8 fields to texref struct --- src/abstract_hardware_model.h | 143 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 130 insertions(+), 13 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index ca41e68..c21ff6d 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -25,6 +25,11 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#ifndef VERSION_EIGHT +#define VERSION_EIGHT +#endif + #ifndef ABSTRACT_HARDWARE_MODEL_INCLUDED #define ABSTRACT_HARDWARE_MODEL_INCLUDED @@ -445,6 +450,35 @@ struct textureReference { enum cudaTextureFilterMode filterMode; enum cudaTextureAddressMode addressMode[3]; struct cudaChannelFormatDesc channelDesc; + +#ifdef VERSION_EIGHT + /** + * Perform sRGB->linear conversion during texture read + */ + int sRGB; + /** + * Limit to the anisotropy ratio + */ + unsigned int maxAnisotropy; + /** + * Mipmap filter mode + */ + enum cudaTextureFilterMode mipmapFilterMode; + /** + * Offset applied to the supplied mipmap level + */ + float mipmapLevelBias; + /** + * Lower end of the mipmap level range to clamp access to + */ + float minMipmapLevelClamp; + /** + * Upper end of the mipmap level range to clamp access to + */ + float maxMipmapLevelClamp; + int __cudaReserved[15]; +#endif + }; #endif @@ -522,7 +556,8 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - + int matches = 0; + const struct cudaArray* t = NULL; for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); kv!= m_TextureRefToCudaArray.end(); kv ++){ const struct textureReference* tr = kv->first; if (tr->normalized==texref->normalized&& @@ -534,19 +569,49 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f){ - - return kv->second; + tr->channelDesc.f==texref->channelDesc.f && + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14] + ){ + matches++; + t = kv->second; + //return kv->second; } } - assert(false); + printf("matches (texarray) = %d\n", matches); + //assert(matches==1); + return t; + + //assert(false); + // std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); // assert(t != m_TextureRefToCudaArray.end()); // return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { + int matches = 0; + const struct textureInfo* t = NULL; for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); kv!= m_TextureRefToTexureInfo.end(); kv ++){ const struct textureReference* tr = kv->first; if (tr->normalized==texref->normalized&& @@ -558,13 +623,38 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f){ - - return kv->second; + tr->channelDesc.f==texref->channelDesc.f&& + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14]){ + matches++; + t = kv->second; + //return kv->second; } } - assert(false); + printf("matches (texinfo) = %d\n", matches); + //assert(matches==1); + return t; + // std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); // assert(t != m_TextureRefToTexureInfo.end()); // return t->second; @@ -572,6 +662,8 @@ public: const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { + int matches = 0; + const struct textureReferenceAttr* t = NULL; for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ const struct textureReference* tr = kv->first; if (tr->normalized==texref->normalized&& @@ -583,13 +675,38 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f){ - - return kv->second; + tr->channelDesc.f==texref->channelDesc.f&& + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14]){ + matches++; + t = kv->second; + //return kv->second; } } - assert(false); + printf("matches (texattr) = %d\n", matches); + //assert(matches==1); + return t; + // std::map::const_iterator t=m_TextureRefToAttribute.find(texref); // assert(t != m_TextureRefToAttribute.end()); // return t->second; -- cgit v1.3 From d75898c2bf867ac6ea45594f3da9f18525f2ad6f Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 16:26:55 -0700 Subject: abstract_hardware_model.h:texrefAttr is different and can be searched via pointer cuda-sim.cc: counts matches between cudaBinTextureToArray texref param (pointer) to texref pointers in m_NameToTextureRef --- src/abstract_hardware_model.h | 94 +++++++++++++++++++++---------------------- src/cuda-sim/cuda-sim.cc | 47 +++++++++++++++++----- 2 files changed, 84 insertions(+), 57 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index c21ff6d..608a7e2 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -662,54 +662,54 @@ public: const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { - int matches = 0; - const struct textureReferenceAttr* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f&& - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14]){ - matches++; - t = kv->second; - //return kv->second; - } - } - - printf("matches (texattr) = %d\n", matches); - //assert(matches==1); - return t; +// int matches = 0; +// const struct textureReferenceAttr* t = NULL; +// for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ +// const struct textureReference* tr = kv->first; +// if (tr->normalized==texref->normalized&& +// tr->filterMode==texref->filterMode&& +// tr->addressMode[0]==texref->addressMode[0]&& +// tr->addressMode[1]==texref->addressMode[1]&& +// tr->addressMode[2]==texref->addressMode[2]&& +// tr->channelDesc.x==texref->channelDesc.x&& +// tr->channelDesc.y==texref->channelDesc.y&& +// tr->channelDesc.z==texref->channelDesc.z&& +// tr->channelDesc.w==texref->channelDesc.w&& +// tr->channelDesc.f==texref->channelDesc.f&& +// tr->sRGB==texref->sRGB&& +// tr->maxAnisotropy==texref->maxAnisotropy&& +// tr->mipmapFilterMode==texref->mipmapFilterMode&& +// tr->mipmapLevelBias==texref->mipmapLevelBias&& +// tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& +// tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& +// tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& +// tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& +// tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& +// tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& +// tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& +// tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& +// tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& +// tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& +// tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& +// tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& +// tr->__cudaReserved[10]==texref->__cudaReserved[10]&& +// tr->__cudaReserved[11]==texref->__cudaReserved[11]&& +// tr->__cudaReserved[12]==texref->__cudaReserved[12]&& +// tr->__cudaReserved[13]==texref->__cudaReserved[13]&& +// tr->__cudaReserved[14]==texref->__cudaReserved[14]){ +// matches++; +// t = kv->second; +// //return kv->second; +// } +// } +// +// printf("matches (texattr) = %d\n", matches); +// //assert(matches==1); +// return t; -// std::map::const_iterator t=m_TextureRefToAttribute.find(texref); -// assert(t != m_TextureRefToAttribute.end()); -// return t->second; + std::map::const_iterator t=m_TextureRefToAttribute.find(texref); + assert(t != m_TextureRefToAttribute.end()); + return t->second; } const gpgpu_functional_sim_config &get_config() const { return m_function_model_config; } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 6e04ca8..39ffa63 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -26,6 +26,10 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +#ifndef VERSION_EIGHT +#define VERSION_EIGHT +#endif + #include "cuda-sim.h" #include "instructions.h" @@ -104,6 +108,16 @@ static address_type get_converge_point(address_type pc); void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) { + +//#ifdef VERSION_EIGHT +// int i; +// printf("%s ", name); +// printf("__cudaReserved:"); +// for (i = 0; i<15; i++){ +// printf(" %i", texref->__cudaReserved[i]); +// } +// printf("\n"); +//#endif std::string texname(name); m_NameToTextureRef[texname] = texref; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); @@ -140,16 +154,15 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { +//#ifdef VERSION_EIGHT +// int i; +// printf("__cudaReserved:"); +// for (i = 0; i<15; i++){ +// printf(" %i", texref->__cudaReserved[i]); +// } +// printf("\n"); +//#endif // counts number of matches -// int normalized; -// enum cudaTextureFilterMode filterMode; -// enum cudaTextureAddressMode addressMode[3]; -// struct cudaChannelFormatDesc channelDesc; -// int x; -// int y; -// int z; -// int w; -// enum cudaChannelFormatKind f; // int trMatches = 0; // for (auto& kv : m_NameToTextureRef){ // const struct textureReference* tr = kv.second; @@ -170,7 +183,21 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te // } // printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); // assert(trMatches==1); - m_TextureRefToCudaArray[texref] = array; + + //tests if texref pointer matches any pointer in m_NameToTextureRef map + int trMatches = 0; + for (auto& kv : m_NameToTextureRef){ + const struct textureReference* tr = kv.second; + if (tr==texref){ + m_TextureRefToCudaArray[tr] = array; + //printf("%s\n", kv.first); + trMatches++; + } + } + printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); + //assert(trMatches==1); + + //m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; unsigned int Tx, Ty; -- cgit v1.3 From c875860b1a79d3dc828275b6129c92f154b516e1 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 16:49:55 -0700 Subject: changed for loop, pass pipeline? --- 0517_13-24cudaReserved.log | 0 517-1418cudaReserved.log | 0 src/cuda-sim/cuda-sim.cc | 6 +++--- 3 files changed, 3 insertions(+), 3 deletions(-) create mode 100644 0517_13-24cudaReserved.log create mode 100644 517-1418cudaReserved.log diff --git a/0517_13-24cudaReserved.log b/0517_13-24cudaReserved.log new file mode 100644 index 0000000..e69de29 diff --git a/517-1418cudaReserved.log b/517-1418cudaReserved.log new file mode 100644 index 0000000..e69de29 diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 39ffa63..656091c 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -186,11 +186,11 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te //tests if texref pointer matches any pointer in m_NameToTextureRef map int trMatches = 0; - for (auto& kv : m_NameToTextureRef){ - const struct textureReference* tr = kv.second; + for (std::map::const_iterator kv = m_NameToTextureRef.begin(); kv!= m_NameToTextureRef.end(); kv ++){ + const struct textureReference* tr = kv->second; if (tr==texref){ m_TextureRefToCudaArray[tr] = array; - //printf("%s\n", kv.first); + printf("%s\n", kv->first.c_str()); trMatches++; } } -- cgit v1.3 From 3b4c3898771ac5e774bca9445a5a4a81670b7b17 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 18 May 2018 10:50:19 -0700 Subject: reverted cuda8 changes (extra fields) and assert texture bug fix's assumption --- src/abstract_hardware_model.h | 134 ++++++++++++++---------------------------- src/cuda-sim/cuda-sim.cc | 59 +------------------ 2 files changed, 45 insertions(+), 148 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 608a7e2..412c0a8 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -451,33 +451,32 @@ struct textureReference { enum cudaTextureAddressMode addressMode[3]; struct cudaChannelFormatDesc channelDesc; -#ifdef VERSION_EIGHT - /** - * Perform sRGB->linear conversion during texture read - */ - int sRGB; - /** - * Limit to the anisotropy ratio - */ - unsigned int maxAnisotropy; - /** - * Mipmap filter mode - */ - enum cudaTextureFilterMode mipmapFilterMode; - /** - * Offset applied to the supplied mipmap level - */ - float mipmapLevelBias; - /** - * Lower end of the mipmap level range to clamp access to - */ - float minMipmapLevelClamp; - /** - * Upper end of the mipmap level range to clamp access to - */ - float maxMipmapLevelClamp; - int __cudaReserved[15]; -#endif +//following commented section applies only to CUDA_VERSION 8+ +// /** +// * Perform sRGB->linear conversion during texture read +// */ +// int sRGB; +// /** +// * Limit to the anisotropy ratio +// */ +// unsigned int maxAnisotropy; +// /** +// * Mipmap filter mode +// */ +// enum cudaTextureFilterMode mipmapFilterMode; +// /** +// * Offset applied to the supplied mipmap level +// */ +// float mipmapLevelBias; +// /** +// * Lower end of the mipmap level range to clamp access to +// */ +// float minMipmapLevelClamp; +// /** +// * Upper end of the mipmap level range to clamp access to +// */ +// float maxMipmapLevelClamp; +// int __cudaReserved[15]; }; @@ -569,7 +568,10 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f && + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && tr->sRGB==texref->sRGB&& tr->maxAnisotropy==texref->maxAnisotropy&& tr->mipmapFilterMode==texref->mipmapFilterMode&& @@ -591,6 +593,7 @@ public: tr->__cudaReserved[12]==texref->__cudaReserved[12]&& tr->__cudaReserved[13]==texref->__cudaReserved[13]&& tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ ){ matches++; t = kv->second; @@ -598,15 +601,9 @@ public: } } - printf("matches (texarray) = %d\n", matches); - //assert(matches==1); + //printf("matches (texarray) = %d\n", matches); + assert(matches==1); return t; - - //assert(false); - -// std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); -// assert(t != m_TextureRefToCudaArray.end()); -// return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { @@ -623,7 +620,10 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f&& + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && tr->sRGB==texref->sRGB&& tr->maxAnisotropy==texref->maxAnisotropy&& tr->mipmapFilterMode==texref->mipmapFilterMode&& @@ -644,69 +644,23 @@ public: tr->__cudaReserved[11]==texref->__cudaReserved[11]&& tr->__cudaReserved[12]==texref->__cudaReserved[12]&& tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14]){ + tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ + ){ matches++; t = kv->second; - //return kv->second; } } - printf("matches (texinfo) = %d\n", matches); - //assert(matches==1); + //printf("matches (texinfo) = %d\n", matches); + assert(matches==1); return t; - -// std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); -// assert(t != m_TextureRefToTexureInfo.end()); -// return t->second; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { -// int matches = 0; -// const struct textureReferenceAttr* t = NULL; -// for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ -// const struct textureReference* tr = kv->first; -// if (tr->normalized==texref->normalized&& -// tr->filterMode==texref->filterMode&& -// tr->addressMode[0]==texref->addressMode[0]&& -// tr->addressMode[1]==texref->addressMode[1]&& -// tr->addressMode[2]==texref->addressMode[2]&& -// tr->channelDesc.x==texref->channelDesc.x&& -// tr->channelDesc.y==texref->channelDesc.y&& -// tr->channelDesc.z==texref->channelDesc.z&& -// tr->channelDesc.w==texref->channelDesc.w&& -// tr->channelDesc.f==texref->channelDesc.f&& -// tr->sRGB==texref->sRGB&& -// tr->maxAnisotropy==texref->maxAnisotropy&& -// tr->mipmapFilterMode==texref->mipmapFilterMode&& -// tr->mipmapLevelBias==texref->mipmapLevelBias&& -// tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& -// tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& -// tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& -// tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& -// tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& -// tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& -// tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& -// tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& -// tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& -// tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& -// tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& -// tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& -// tr->__cudaReserved[10]==texref->__cudaReserved[10]&& -// tr->__cudaReserved[11]==texref->__cudaReserved[11]&& -// tr->__cudaReserved[12]==texref->__cudaReserved[12]&& -// tr->__cudaReserved[13]==texref->__cudaReserved[13]&& -// tr->__cudaReserved[14]==texref->__cudaReserved[14]){ -// matches++; -// t = kv->second; -// //return kv->second; -// } -// } -// -// printf("matches (texattr) = %d\n", matches); -// //assert(matches==1); -// return t; - + //note textureReferenceAttr map behaves differently from cudaArray and + //textureInfo maps std::map::const_iterator t=m_TextureRefToAttribute.find(texref); assert(t != m_TextureRefToAttribute.end()); return t->second; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 656091c..946043a 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -26,10 +26,6 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -#ifndef VERSION_EIGHT -#define VERSION_EIGHT -#endif - #include "cuda-sim.h" #include "instructions.h" @@ -108,16 +104,6 @@ static address_type get_converge_point(address_type pc); void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) { - -//#ifdef VERSION_EIGHT -// int i; -// printf("%s ", name); -// printf("__cudaReserved:"); -// for (i = 0; i<15; i++){ -// printf(" %i", texref->__cudaReserved[i]); -// } -// printf("\n"); -//#endif std::string texname(name); m_NameToTextureRef[texname] = texref; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); @@ -154,50 +140,7 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { -//#ifdef VERSION_EIGHT -// int i; -// printf("__cudaReserved:"); -// for (i = 0; i<15; i++){ -// printf(" %i", texref->__cudaReserved[i]); -// } -// printf("\n"); -//#endif - // counts number of matches -// int trMatches = 0; -// for (auto& kv : m_NameToTextureRef){ -// const struct textureReference* tr = kv.second; -// if (tr->normalized==texref->normalized&& -// tr->filterMode==texref->filterMode&& -// tr->addressMode[0]==texref->addressMode[0]&& -// tr->addressMode[1]==texref->addressMode[1]&& -// tr->addressMode[2]==texref->addressMode[2]&& -// tr->channelDesc.x==texref->channelDesc.x&& -// tr->channelDesc.y==texref->channelDesc.y&& -// tr->channelDesc.z==texref->channelDesc.z&& -// tr->channelDesc.w==texref->channelDesc.w&& -// tr->channelDesc.f==texref->channelDesc.f){ -// -// m_TextureRefToCudaArray[tr] = array; -// trMatches++; -// } -// } -// printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); -// assert(trMatches==1); - - //tests if texref pointer matches any pointer in m_NameToTextureRef map - int trMatches = 0; - for (std::map::const_iterator kv = m_NameToTextureRef.begin(); kv!= m_NameToTextureRef.end(); kv ++){ - const struct textureReference* tr = kv->second; - if (tr==texref){ - m_TextureRefToCudaArray[tr] = array; - printf("%s\n", kv->first.c_str()); - trMatches++; - } - } - printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); - //assert(trMatches==1); - - //m_TextureRefToCudaArray[texref] = array; + m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; unsigned int Tx, Ty; -- cgit v1.3 From 6a39e5c5964f23a97dafaa6a66f2a9d9c37bbfdd Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 18 May 2018 11:52:31 -0700 Subject: implemented unbind, currently only affects cudaArray map --- 0517_13-24cudaReserved.log | 0 517-1418cudaReserved.log | 0 libcuda/cuda_runtime_api.cc | 11 +++++++++++ src/abstract_hardware_model.h | 1 + src/cuda-sim/cuda-sim.cc | 5 +++++ 5 files changed, 17 insertions(+) delete mode 100644 0517_13-24cudaReserved.log delete mode 100644 517-1418cudaReserved.log diff --git a/0517_13-24cudaReserved.log b/0517_13-24cudaReserved.log deleted file mode 100644 index e69de29..0000000 diff --git a/517-1418cudaReserved.log b/517-1418cudaReserved.log deleted file mode 100644 index e69de29..0000000 diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index e3c2542..71926f8 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -991,6 +991,14 @@ __host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureRefere __host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) { + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + printf("GPGPU-Sim PTX: in cudaUnbindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); + printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); + const struct cudaArray* array = gpu->get_texarray(texref); + printf("GPGPU-Sim PTX: texref = %p, array = %p\n", texref, array); + + gpu->gpgpu_ptx_sim_unbindTexture(texref); return g_last_cudaError = cudaSuccess; } @@ -2073,10 +2081,12 @@ void __cudaUnregisterFatBinary(void **fatCubinHandle) cudaError_t cudaDeviceReset ( void ) { // Should reset the simulated GPU + // TODO: Implement return g_last_cudaError = cudaSuccess; } cudaError_t CUDARTAPI cudaDeviceSynchronize(void){ // I don't know what this should do + // TODO: Implement return g_last_cudaError = cudaSuccess; } @@ -2178,6 +2188,7 @@ typedef unsigned long GLuint; cudaError_t cudaGLRegisterBufferObject(GLuint bufferObj) { printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); + // TODO: Implement return g_last_cudaError = cudaSuccess; } diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 412c0a8..3ef450e 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -544,6 +544,7 @@ public: class memory_space *get_surf_memory() { return m_surf_mem; } void gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array); + void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); void gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 946043a..ef16f43 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -183,6 +183,11 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te m_TextureRefToTexureInfo[texref] = texInfo; } +void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) +{ + m_TextureRefToCudaArray.erase(texref); +} + unsigned g_assemble_code_next_pc=0; std::map g_pc_to_finfo; std::vector function_info::s_g_pc_to_insn; -- cgit v1.3 From a93aa28a94140ee912c0cba0d9414d9da1588d54 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 18 May 2018 14:41:23 -0700 Subject: erase texinfo in unbind and disable assert --- src/abstract_hardware_model.h | 195 ++++++++++++++++++++++-------------------- src/cuda-sim/cuda-sim.cc | 2 + 2 files changed, 104 insertions(+), 93 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 3ef450e..6dd5436 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -556,106 +556,115 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - int matches = 0; - const struct cudaArray* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); kv!= m_TextureRefToCudaArray.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; - //return kv->second; + + std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); + if(t != m_TextureRefToCudaArray.end()){ + return t->second; + } else{ + int matches = 0; + const struct cudaArray* t = NULL; + for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); + kv!= m_TextureRefToCudaArray.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ + ){ + matches++; + t = kv->second; + } } + + //assert(matches==1); + return t; } - - //printf("matches (texarray) = %d\n", matches); - assert(matches==1); - return t; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { - int matches = 0; - const struct textureInfo* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); kv!= m_TextureRefToTexureInfo.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; + std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); + if(t != m_TextureRefToTexureInfo.end()){ + return t->second; + }else{ + int matches = 0; + const struct textureInfo* t = NULL; + for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); + kv!= m_TextureRefToTexureInfo.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ + ){ + matches++; + t = kv->second; + } } + //assert(matches==1); + return t; } - - //printf("matches (texinfo) = %d\n", matches); - assert(matches==1); - return t; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index ef16f43..6bdf75f 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -140,6 +140,7 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { + printf("GPGPU-Simm PTX: name from texture = %s\n", gpgpu_ptx_sim_findNamefromTexture(texref)); m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; @@ -186,6 +187,7 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) { m_TextureRefToCudaArray.erase(texref); + m_TextureRefToTexureInfo.erase(texref); } unsigned g_assemble_code_next_pc=0; -- cgit v1.3 From 958e430266cb3de73033a7e0aab6e7c697fdc6bc Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 09:49:26 -0700 Subject: revert to before texture bug --- libcuda/cuda_runtime_api.cc | 11 ---- src/abstract_hardware_model.h | 144 ++---------------------------------------- src/cuda-sim/cuda-sim.cc | 7 -- 3 files changed, 4 insertions(+), 158 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 71926f8..e3c2542 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -991,14 +991,6 @@ __host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureRefere __host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) { - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - printf("GPGPU-Sim PTX: in cudaUnbindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); - printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); - const struct cudaArray* array = gpu->get_texarray(texref); - printf("GPGPU-Sim PTX: texref = %p, array = %p\n", texref, array); - - gpu->gpgpu_ptx_sim_unbindTexture(texref); return g_last_cudaError = cudaSuccess; } @@ -2081,12 +2073,10 @@ void __cudaUnregisterFatBinary(void **fatCubinHandle) cudaError_t cudaDeviceReset ( void ) { // Should reset the simulated GPU - // TODO: Implement return g_last_cudaError = cudaSuccess; } cudaError_t CUDARTAPI cudaDeviceSynchronize(void){ // I don't know what this should do - // TODO: Implement return g_last_cudaError = cudaSuccess; } @@ -2188,7 +2178,6 @@ typedef unsigned long GLuint; cudaError_t cudaGLRegisterBufferObject(GLuint bufferObj) { printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); - // TODO: Implement return g_last_cudaError = cudaSuccess; } diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 6dd5436..f5708bc 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -25,11 +25,6 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -#ifndef VERSION_EIGHT -#define VERSION_EIGHT -#endif - #ifndef ABSTRACT_HARDWARE_MODEL_INCLUDED #define ABSTRACT_HARDWARE_MODEL_INCLUDED @@ -450,34 +445,6 @@ struct textureReference { enum cudaTextureFilterMode filterMode; enum cudaTextureAddressMode addressMode[3]; struct cudaChannelFormatDesc channelDesc; - -//following commented section applies only to CUDA_VERSION 8+ -// /** -// * Perform sRGB->linear conversion during texture read -// */ -// int sRGB; -// /** -// * Limit to the anisotropy ratio -// */ -// unsigned int maxAnisotropy; -// /** -// * Mipmap filter mode -// */ -// enum cudaTextureFilterMode mipmapFilterMode; -// /** -// * Offset applied to the supplied mipmap level -// */ -// float mipmapLevelBias; -// /** -// * Lower end of the mipmap level range to clamp access to -// */ -// float minMipmapLevelClamp; -// /** -// * Upper end of the mipmap level range to clamp access to -// */ -// float maxMipmapLevelClamp; -// int __cudaReserved[15]; - }; #endif @@ -544,7 +511,6 @@ public: class memory_space *get_surf_memory() { return m_surf_mem; } void gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array); - void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); void gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); @@ -556,121 +522,19 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); - if(t != m_TextureRefToCudaArray.end()){ - return t->second; - } else{ - int matches = 0; - const struct cudaArray* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); - kv!= m_TextureRefToCudaArray.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; - } - } - - //assert(matches==1); - return t; - } + assert(t != m_TextureRefToCudaArray.end()); + return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); - if(t != m_TextureRefToTexureInfo.end()){ - return t->second; - }else{ - int matches = 0; - const struct textureInfo* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); - kv!= m_TextureRefToTexureInfo.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; - } - } - //assert(matches==1); - return t; - } + assert(t != m_TextureRefToTexureInfo.end()); + return t->second; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { - //note textureReferenceAttr map behaves differently from cudaArray and - //textureInfo maps std::map::const_iterator t=m_TextureRefToAttribute.find(texref); assert(t != m_TextureRefToAttribute.end()); return t->second; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 6bdf75f..946043a 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -140,7 +140,6 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { - printf("GPGPU-Simm PTX: name from texture = %s\n", gpgpu_ptx_sim_findNamefromTexture(texref)); m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; @@ -184,12 +183,6 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te m_TextureRefToTexureInfo[texref] = texInfo; } -void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) -{ - m_TextureRefToCudaArray.erase(texref); - m_TextureRefToTexureInfo.erase(texref); -} - unsigned g_assemble_code_next_pc=0; std::map g_pc_to_finfo; std::vector function_info::s_g_pc_to_insn; -- cgit v1.3 From 4a567a94aca58fdd2298b50ae9e9da3a889e2173 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 09:56:07 -0700 Subject: unbind implementation --- libcuda/cuda_runtime_api.cc | 11 ++++++++--- src/abstract_hardware_model.h | 1 + src/cuda-sim/cuda-sim.cc | 6 ++++++ 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index e3c2542..d971222 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -989,9 +989,14 @@ __host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureRefere return g_last_cudaError = cudaSuccess; } -__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) -{ - return g_last_cudaError = cudaSuccess; +__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) { + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + printf("GPGPU-Sim PTX: in cudaUnbindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); + printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); + + gpu->gpgpu_ptx_sim_unbindTexture(texref); + return g_last_cudaError = cudaSuccess; } __host__ cudaError_t CUDARTAPI cudaGetTextureAlignmentOffset(size_t *offset, const struct textureReference *texref) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index f5708bc..ab94ded 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -512,6 +512,7 @@ public: void gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array); void gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext); + void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); const struct textureReference* get_texref(const std::string &texname) const diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 946043a..6125422 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -183,6 +183,12 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te m_TextureRefToTexureInfo[texref] = texInfo; } +void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) +{ + m_TextureRefToCudaArray.erase(texref); + m_TextureRefToTexureInfo.erase(texref); +} + unsigned g_assemble_code_next_pc=0; std::map g_pc_to_finfo; std::vector function_info::s_g_pc_to_insn; -- cgit v1.3 From ff958f36689c9c217eb099326ceb8f70ed3ac447 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 14:00:59 -0700 Subject: restructured texref maps to fix texture bug --- src/abstract_hardware_model.h | 36 +++++++++++++++++-------------- src/cuda-sim/cuda-sim.cc | 49 ++++++++++++++++++++++++++++--------------- src/cuda-sim/instructions.cc | 6 +++--- 3 files changed, 55 insertions(+), 36 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index ab94ded..d0af1ea 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -65,6 +65,7 @@ enum FuncCache #include #include +#include typedef unsigned long long new_addr_type; typedef unsigned address_type; @@ -515,29 +516,31 @@ public: void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); - const struct textureReference* get_texref(const std::string &texname) const + const struct textureReference* get_texref( const std::string &texname ) const { - std::map::const_iterator t=m_NameToTextureRef.find(texname); + std::map >::const_iterator t=m_NameToTextureRef.find(texname); assert( t != m_NameToTextureRef.end() ); - return t->second; + return *(t->second.begin()); } - const struct cudaArray* get_texarray( const struct textureReference *texref ) const + + const struct cudaArray* get_texarray( const std::string &texname ) const { - std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); - assert(t != m_TextureRefToCudaArray.end()); + std::map::const_iterator t=m_NameToCudaArray.find(texname); + assert(t != m_NameToCudaArray.end()); return t->second; } - const struct textureInfo* get_texinfo( const struct textureReference *texref ) const + + const struct textureInfo* get_texinfo( const std::string &texname ) const { - std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); - assert(t != m_TextureRefToTexureInfo.end()); + std::map::const_iterator t=m_NameToTexureInfo.find(texname); + assert(t != m_NameToTexureInfo.end()); return t->second; } - const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const + const struct textureReferenceAttr* get_texattr( const std::string &texname ) const { - std::map::const_iterator t=m_TextureRefToAttribute.find(texref); - assert(t != m_TextureRefToAttribute.end()); + std::map::const_iterator t=m_NameToAttribute.find(texname); + assert(t != m_NameToAttribute.end()); return t->second; } @@ -554,10 +557,11 @@ protected: unsigned long long m_dev_malloc; - std::map m_NameToTextureRef; - std::map m_TextureRefToCudaArray; - std::map m_TextureRefToTexureInfo; - std::map m_TextureRefToAttribute; + std::map > m_NameToTextureRef; + std::map m_TextureRefToName; + std::map m_NameToCudaArray; + std::map m_NameToTexureInfo; + std::map m_NameToAttribute; }; struct gpgpu_ptx_sim_info diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 6125422..05b6201 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -105,22 +105,36 @@ static address_type get_converge_point(address_type pc); void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) { std::string texname(name); - m_NameToTextureRef[texname] = texref; + if (m_NameToTextureRef.find(texname)==m_NameToTextureRef.end()){ + m_NameToTextureRef[texname] = std::set(); + m_NameToTextureRef[texname].insert(texref); + }else{ + const struct textureReference* tr = *m_NameToTextureRef[texname].begin(); + assert(tr!=NULL); + //asserts that all texrefs in set have same fields + assert(tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f + ); + m_NameToTextureRef[texname].insert(texref); + } + m_TextureRefToName[texref] = texname; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); - m_TextureRefToAttribute[texref] = texAttr; + m_NameToAttribute[texname] = texAttr; } const char* gpgpu_t::gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref) { - std::map::iterator itr = m_NameToTextureRef.begin(); - while (itr != m_NameToTextureRef.end()) { - if ((*itr).second == texref) { - const char *p = ((*itr).first).c_str(); - return p; - } - itr++; - } - return NULL; + std::map::const_iterator t=m_TextureRefToName.find(texref); + assert( t != m_TextureRefToName.end() ); + return t->second.c_str(); } unsigned int intLOGB2( unsigned int v ) { @@ -140,7 +154,8 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { - m_TextureRefToCudaArray[texref] = array; + std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); + m_NameToCudaArray[texname] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; unsigned int Tx, Ty; @@ -180,13 +195,14 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te texInfo->Ty_numbits = intLOGB2(Ty); texInfo->texel_size = texel_size; texInfo->texel_size_numbits = intLOGB2(texel_size); - m_TextureRefToTexureInfo[texref] = texInfo; + m_NameToTexureInfo[texname] = texInfo; } void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) { - m_TextureRefToCudaArray.erase(texref); - m_TextureRefToTexureInfo.erase(texref); + std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); + m_NameToCudaArray.erase(texname); + m_NameToTexureInfo.erase(texname); } unsigned g_assemble_code_next_pc=0; @@ -1246,8 +1262,7 @@ static unsigned get_tex_datasize( const ptx_instruction *pI, ptx_thread_info *th std::string texname = src1.name(); gpgpu_t *gpu = thread->get_gpu(); - const struct textureReference* texref = gpu->get_texref(texname); - const struct textureInfo* texInfo = gpu->get_texinfo(texref); + const struct textureInfo* texInfo = gpu->get_texinfo(texname); unsigned data_size = texInfo->texel_size; return data_size; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 86951ed..d362231 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -4100,9 +4100,9 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread ) gpgpu_t *gpu = thread->get_gpu(); const struct textureReference* texref = gpu->get_texref(texname); - const struct cudaArray* cuArray = gpu->get_texarray(texref); - const struct textureInfo* texInfo = gpu->get_texinfo(texref); - const struct textureReferenceAttr* texAttr = gpu->get_texattr(texref); + const struct cudaArray* cuArray = gpu->get_texarray(texname); + const struct textureInfo* texInfo = gpu->get_texinfo(texname); + const struct textureReferenceAttr* texAttr = gpu->get_texattr(texname); //assume always 2D f32 input //access array with src2 coordinates -- cgit v1.3 From 3fcc3f8fd99b4183be4f5511800049198a9a0116 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 17:27:28 -0700 Subject: cudaStreamWaitEvent tentative implementation --- libcuda/cuda_runtime_api.cc | 20 ++++++++++++++++++++ src/cuda-sim/cuda-sim.cc | 3 +-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index d971222..a45ed61 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1157,6 +1157,26 @@ __host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) #endif } +__host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) +{ + +#if (CUDART_VERSION >= 3000) + if( stream == NULL ) + return g_last_cudaError = cudaErrorInvalidResourceHandle; + return g_last_cudaError = stream->empty()?cudaSuccess:cudaErrorNotReady; +#else + printf("GPGPU-Sim API: cudaStreamWaitEvent ** waiting for event\n"); + fflush(stdout); + CUevent_st *e = (CUevent_st*) event; + while( !e->done() ) + ; + printf("GPGPU-Sim API: cudaStreamWaitEvent ** event detected\n"); + fflush(stdout); + printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); + return g_last_cudaError = cudaSuccess; // it is always success because all cuda calls are synchronous +#endif +} + /******************************************************************************* * * * * diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 05b6201..0e14dd0 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -107,7 +107,6 @@ void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct tex std::string texname(name); if (m_NameToTextureRef.find(texname)==m_NameToTextureRef.end()){ m_NameToTextureRef[texname] = std::set(); - m_NameToTextureRef[texname].insert(texref); }else{ const struct textureReference* tr = *m_NameToTextureRef[texname].begin(); assert(tr!=NULL); @@ -123,8 +122,8 @@ void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct tex tr->channelDesc.w==texref->channelDesc.w&& tr->channelDesc.f==texref->channelDesc.f ); - m_NameToTextureRef[texname].insert(texref); } + m_NameToTextureRef[texname].insert(texref); m_TextureRefToName[texref] = texname; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); m_NameToAttribute[texname] = texAttr; -- cgit v1.3 From d659ac82a83dc985a441001a7a7b46004d3ad11d Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 22:31:13 -0700 Subject: gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 428abce..0e2a898 100644 --- a/.gitignore +++ b/.gitignore @@ -32,4 +32,5 @@ build/* *~ cscope* tags +regression.sh -- cgit v1.3 From 11aa36f93b49b384d5620df69ab3ce2a50a84d24 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Wed, 23 May 2018 10:04:11 -0700 Subject: assertions and comments that allow the current unbind implementation to behave correctly --- src/cuda-sim/cuda-sim.cc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 0e14dd0..2a197c3 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -154,6 +154,10 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); + + std::map::const_iterator t=m_NameToCudaArray.find(texname); + //check that there's nothing there first + assert(t == m_NameToCudaArray.end()); m_NameToCudaArray[texname] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; @@ -199,6 +203,7 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) { + //assumes bind-use-unbind-bind-use-unbind pattern std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); m_NameToCudaArray.erase(texname); m_NameToTexureInfo.erase(texname); -- cgit v1.3 From 14db8e9d45ff253ae79376c7e8e4dc4cb06042b6 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Wed, 23 May 2018 11:14:42 -0700 Subject: unimplement cudaStreaWaitEvent because I don't know what I'm doing --- libcuda/cuda_runtime_api.cc | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index a45ed61..30e3989 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1159,22 +1159,8 @@ __host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) __host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) { - -#if (CUDART_VERSION >= 3000) - if( stream == NULL ) - return g_last_cudaError = cudaErrorInvalidResourceHandle; - return g_last_cudaError = stream->empty()?cudaSuccess:cudaErrorNotReady; -#else - printf("GPGPU-Sim API: cudaStreamWaitEvent ** waiting for event\n"); - fflush(stdout); - CUevent_st *e = (CUevent_st*) event; - while( !e->done() ) - ; - printf("GPGPU-Sim API: cudaStreamWaitEvent ** event detected\n"); - fflush(stdout); - printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); - return g_last_cudaError = cudaSuccess; // it is always success because all cuda calls are synchronous -#endif + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; } /******************************************************************************* -- cgit v1.3 From 006006efb4290f007ec96f0c2e6023d53e7601ff Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 24 May 2018 15:35:05 -0700 Subject: changed assertion to warning when binding to previously bound name. --- src/cuda-sim/cuda-sim.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 2a197c3..34368ce 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -157,7 +157,9 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te std::map::const_iterator t=m_NameToCudaArray.find(texname); //check that there's nothing there first - assert(t == m_NameToCudaArray.end()); + if(t != m_NameToCudaArray.end()){ + printf("GPGPU-Sim PTX: Warning: binding to texref associated with %s, which was previously bound.\nImplicitly unbinding texref associated to %s first\n", texname.c_str(), texname.c_str()); + } m_NameToCudaArray[texname] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; -- cgit v1.3 From 7e08538246f386a8e4ce0686d3f6eafff99f23cc Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 25 May 2018 09:32:49 -0700 Subject: fixed merge issue --- src/cuda-sim/instructions.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index d362231..35d1782 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2366,12 +2366,12 @@ void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand type_info_key ti = t->get_key(); if( ti.is_param_kernel() ) space = param_space_kernel; - else if( ti.is_param_local() ) + else if( ti.is_param_local() ) { space = param_space_local; } else if( ti.is_reg() ) { space = param_space_kernel; - } + } else { printf("GPGPU-Sim PTX: ERROR ** cannot resolve .param space for '%s'\n", s->name().c_str() ); abort(); -- cgit v1.3 From 7aa77ad0cb1265b3858a0daa08b5afe026c129f7 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 25 May 2018 09:41:51 -0700 Subject: fixed weird spacing issue --- libcuda/cuda_runtime_api.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 30e3989..cfa9cec 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -989,7 +989,7 @@ __host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureRefere return g_last_cudaError = cudaSuccess; } -__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) { +__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref){ CUctx_st *context = GPGPUSim_Context(); gpgpu_t *gpu = context->get_device()->get_gpgpu(); printf("GPGPU-Sim PTX: in cudaUnbindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); -- cgit v1.3 From fbf8e1180008db2fec31ba1f1e916ea4cb4af97a Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 25 May 2018 17:05:28 -0700 Subject: tentative impl of cudaStreamWaitEvent --- libcuda/cuda_runtime_api.cc | 4 ++-- src/stream_manager.cc | 7 +++++++ src/stream_manager.h | 11 ++++++++++- 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index cfa9cec..de6d5a5 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1159,8 +1159,8 @@ __host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) __host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) { - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; + stream->push(stream_operation(stream, event, flags)); + return g_last_cudaError = cudaSuccess; } /******************************************************************************* diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 3b6cbd5..5b886ab 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -195,6 +195,13 @@ bool stream_operation::do_operation( gpgpu_sim *gpu ) m_stream->record_next_done(); } break; + case stream_wait_event: { + if(g_debug_execution >= 3) + printf("stream wait event\n"); + if(m_event->done()) + m_stream->record_next_done(); + } + break; default: abort(); } diff --git a/src/stream_manager.h b/src/stream_manager.h index 222a1b2..edf2b24 100644 --- a/src/stream_manager.h +++ b/src/stream_manager.h @@ -51,7 +51,8 @@ enum stream_operation_type { stream_memcpy_to_symbol, stream_memcpy_from_symbol, stream_kernel_launch, - stream_event + stream_event, + stream_wait_event }; class stream_operation { @@ -101,6 +102,14 @@ public: m_stream=stream; m_done=false; } + stream_operation( struct CUstream_st *stream, class CUevent_st *e, unsigned int flags ) + { + m_kernel=NULL; + m_type=stream_wait_event; + m_event=e; + m_stream=stream; + m_done=false; + } stream_operation( const void *host_address_src, size_t device_address_dst, size_t cnt, struct CUstream_st *stream ) { m_kernel=NULL; -- cgit v1.3 From 2778712a298a58be4a5abaa28f45805eb3c027c6 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 25 May 2018 17:41:40 -0700 Subject: seg fault fix --- libcuda/cuda_runtime_api.cc | 16 ++++++++++------ src/stream_manager.cc | 1 + 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index de6d5a5..f130a37 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1157,12 +1157,6 @@ __host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) #endif } -__host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) -{ - stream->push(stream_operation(stream, event, flags)); - return g_last_cudaError = cudaSuccess; -} - /******************************************************************************* * * * * @@ -1205,6 +1199,16 @@ __host__ cudaError_t CUDARTAPI cudaEventRecord(cudaEvent_t event, cudaStream_t s return g_last_cudaError = cudaSuccess; } +__host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) +{ + CUevent_st *e = get_event(event); + if( !e ) return g_last_cudaError = cudaErrorUnknown; + struct CUstream_st *s = (struct CUstream_st *)stream; + stream_operation op(s,e,flags); + g_stream_manager->push(op); + return g_last_cudaError = cudaSuccess; +} + __host__ cudaError_t CUDARTAPI cudaEventQuery(cudaEvent_t event) { CUevent_st *e = get_event(event); diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 5b886ab..1b8ebb1 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -199,6 +199,7 @@ bool stream_operation::do_operation( gpgpu_sim *gpu ) if(g_debug_execution >= 3) printf("stream wait event\n"); if(m_event->done()) + printf("stream wait event done\n"); m_stream->record_next_done(); } break; -- cgit v1.3 From 7dfa2ae2e6f8ccaaf133318265a7ab00de546e82 Mon Sep 17 00:00:00 2001 From: aamir Date: Sun, 27 May 2018 14:18:53 -0700 Subject: added wmma parsing but execution getting aborted --- cuda-kernels/Makefile | 7 + cuda-kernels/_cuobjdump_1.elf | 15 + cuda-kernels/_cuobjdump_1.ptx | 170 ++++ cuda-kernels/_cuobjdump_1.sass | 2 + cuda-kernels/_cuobjdump_2.elf | 494 +++++++++ cuda-kernels/_cuobjdump_2.sass | 348 +++++++ cuda-kernels/_cuobjdump_complete_output_EIGzTK | 1055 ++++++++++++++++++++ cuda-kernels/_cuobjdump_complete_output_rndQyq | 1055 ++++++++++++++++++++ cuda-kernels/config_fermi_islip.icnt | 70 ++ cuda-kernels/gpgpu_inst_stats.txt | 1 + cuda-kernels/gpgpusim.config | 149 +++ ...usim_power_report__Sun-May-27-14-17-34-2018.log | 324 ++++++ ...usim_power_report__Sun-May-27-14-17-47-2018.log | 324 ++++++ cuda-kernels/gpuwattch_gtx1080Ti.xml | 538 ++++++++++ cuda-kernels/tensor_core | Bin 0 -> 48541 bytes cuda-kernels/tensor_core.cu | 250 +++++ cuobjdump_to_ptxplus/ptx_parser.h | 2 + src/cuda-sim/instructions.cc | 8 +- src/cuda-sim/opcodes.def | 2 + src/cuda-sim/opcodes.h | 11 +- src/cuda-sim/ptx.l | 18 +- src/cuda-sim/ptx.y | 10 + src/cuda-sim/ptx_ir.cc | 6 +- src/cuda-sim/ptx_ir.h | 33 + src/cuda-sim/ptx_parser.cc | 33 +- src/cuda-sim/ptx_parser.h | 2 + 26 files changed, 4918 insertions(+), 9 deletions(-) create mode 100755 cuda-kernels/Makefile create mode 100644 cuda-kernels/_cuobjdump_1.elf create mode 100644 cuda-kernels/_cuobjdump_1.ptx create mode 100644 cuda-kernels/_cuobjdump_1.sass create mode 100644 cuda-kernels/_cuobjdump_2.elf create mode 100644 cuda-kernels/_cuobjdump_2.sass create mode 100644 cuda-kernels/_cuobjdump_complete_output_EIGzTK create mode 100644 cuda-kernels/_cuobjdump_complete_output_rndQyq create mode 100755 cuda-kernels/config_fermi_islip.icnt create mode 100755 cuda-kernels/gpgpu_inst_stats.txt create mode 100755 cuda-kernels/gpgpusim.config create mode 100644 cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log create mode 100644 cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log create mode 100755 cuda-kernels/gpuwattch_gtx1080Ti.xml create mode 100755 cuda-kernels/tensor_core create mode 100644 cuda-kernels/tensor_core.cu diff --git a/cuda-kernels/Makefile b/cuda-kernels/Makefile new file mode 100755 index 0000000..51a7760 --- /dev/null +++ b/cuda-kernels/Makefile @@ -0,0 +1,7 @@ +all: tensor_core.cu + nvcc -arch=sm_70 -lcudart -g -o tensor_core tensor_core.cu + +.PHONY: +clean: + rm tensorcore +# nvcc -arch=sm_70 --gpu-architecture=compute_50 --gpu-code=compute_50 -lcudart -g -o tensor_core tensor_core.cu diff --git a/cuda-kernels/_cuobjdump_1.elf b/cuda-kernels/_cuobjdump_1.elf new file mode 100644 index 0000000..672b0f0 --- /dev/null +++ b/cuda-kernels/_cuobjdump_1.elf @@ -0,0 +1,15 @@ +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 32 0 1 STRTAB 0 0 0 .shstrtab + 2 72 32 0 1 STRTAB 0 0 0 .strtab + 3 a8 18 18 8 SYMTAB 0 2 0 .symtab + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + diff --git a/cuda-kernels/_cuobjdump_1.ptx b/cuda-kernels/_cuobjdump_1.ptx new file mode 100644 index 0000000..3453f4a --- /dev/null +++ b/cuda-kernels/_cuobjdump_1.ptx @@ -0,0 +1,170 @@ + + + + + + + +.version 6.0 +.target sm_70 +.address_size 64 + + +.extern .func (.param .b32 func_retval0) vprintf +( +.param .b64 vprintf_param_0, +.param .b64 vprintf_param_1 +) +; +.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0}; + +.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff( +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7 +) +{ +.local .align 8 .b8 __local_depot0[8]; +.reg .b64 %SP; +.reg .b64 %SPL; +.reg .pred %p<6>; +.reg .f32 %f<34>; +.reg .b32 %r<38>; +.reg .b64 %rd<18>; + + +mov.u64 %rd17, __local_depot0; +cvta.local.u64 %SP, %rd17; +ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0]; +ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1]; +ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2]; +ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3]; +ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4]; +ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5]; + + mov.u32 %r6, %clock; + + mov.u32 %r8, %ntid.x; +mov.u32 %r9, %ctaid.x; +mov.u32 %r10, %tid.x; +mad.lo.s32 %r11, %r8, %r9, %r10; +mov.u32 %r12, WARP_SZ; +div.u32 %r13, %r11, %r12; +mov.u32 %r14, %ntid.y; +mov.u32 %r15, %ctaid.y; +mov.u32 %r16, %tid.y; +mad.lo.s32 %r17, %r14, %r15, %r16; +shl.b32 %r2, %r13, 4; +shl.b32 %r3, %r17, 4; +setp.lt.s32 %p1, %r2, %r4; +setp.gt.s32 %p2, %r5, 0; +and.pred %p3, %p1, %p2; +setp.lt.s32 %p4, %r3, %r7; +and.pred %p5, %p3, %p4; +mov.f32 %f26, 0f00000000; +mov.f32 %f27, %f26; +mov.f32 %f28, %f26; +mov.f32 %f29, %f26; +mov.f32 %f30, %f26; +mov.f32 %f31, %f26; +mov.f32 %f32, %f26; +mov.f32 %f33, %f26; +@!%p5 bra BB0_2; +bra.uni BB0_1; + +BB0_1: +mul.wide.s32 %rd4, %r2, 2; +add.s64 %rd5, %rd1, %rd4; +wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4; +mul.wide.s32 %rd6, %r3, 2; +add.s64 %rd7, %rd2, %rd6; +wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5; +mov.f32 %f25, 0f00000000; +wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25}; + +BB0_2: +add.u64 %rd8, %SP, 0; +cvta.to.local.u64 %rd9, %rd8; +mul.lo.s32 %r35, %r3, %r4; +cvt.s64.s32 %rd10, %r35; +cvt.s64.s32 %rd11, %r2; +add.s64 %rd12, %rd10, %rd11; +shl.b64 %rd13, %rd12, 2; +add.s64 %rd14, %rd3, %rd13; +wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4; + + mov.u32 %r34, %clock; + + sub.s32 %r36, %r34, %r6; +st.local.u32 [%rd9], %r36; +mov.u64 %rd15, $str; +cvta.global.u64 %rd16, %rd15; + + { +.reg .b32 temp_param_reg; + + .param .b64 param0; +st.param.b64 [param0+0], %rd16; +.param .b64 param1; +st.param.b64 [param1+0], %rd8; +.param .b32 retval0; +call.uni (retval0), +vprintf, +( +param0, +param1 +); +ld.param.b32 %r37, [retval0+0]; + + + } + ret; +} + + +.visible .entry _Z17convertFp32ToFp16P6__halfPfi( +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0, +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1, +.param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2 +) +{ +.reg .pred %p<2>; +.reg .b16 %rs<2>; +.reg .f32 %f<2>; +.reg .b32 %r<6>; +.reg .b64 %rd<9>; + + +ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0]; +ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1]; +ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2]; +mov.u32 %r3, %ntid.x; +mov.u32 %r4, %ctaid.x; +mov.u32 %r5, %tid.x; +mad.lo.s32 %r1, %r4, %r3, %r5; +setp.ge.s32 %p1, %r1, %r2; +@%p1 bra BB1_2; + +cvta.to.global.u64 %rd3, %rd2; +mul.wide.s32 %rd4, %r1, 4; +add.s64 %rd5, %rd3, %rd4; +ld.global.f32 %f1, [%rd5]; + + { cvt.rn.f16.f32 %rs1, %f1;} + + + cvta.to.global.u64 %rd6, %rd1; +mul.wide.s32 %rd7, %r1, 2; +add.s64 %rd8, %rd6, %rd7; +st.global.u16 [%rd8], %rs1; + +BB1_2: +ret; +} + + diff --git a/cuda-kernels/_cuobjdump_1.sass b/cuda-kernels/_cuobjdump_1.sass new file mode 100644 index 0000000..2aac29a --- /dev/null +++ b/cuda-kernels/_cuobjdump_1.sass @@ -0,0 +1,2 @@ + code for sm_70 + diff --git a/cuda-kernels/_cuobjdump_2.elf b/cuda-kernels/_cuobjdump_2.elf new file mode 100644 index 0000000..c03b06d --- /dev/null +++ b/cuda-kernels/_cuobjdump_2.elf @@ -0,0 +1,494 @@ +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 21b 0 1 STRTAB 0 0 0 .shstrtab + 2 25b 273 0 1 STRTAB 0 0 0 .strtab + 3 4d0 108 18 8 SYMTAB 0 2 7 .symtab + 4 5d8 e0 0 1 PROGBITS 0 0 0 .debug_frame + 5 6b8 48 0 4 CUDA_INFO 0 3 0 .nv.info + 6 700 50 0 4 CUDA_INFO 0 3 d .nv.info._Z17convertFp32ToFp16P6__halfPfi + 7 750 ac 0 4 CUDA_INFO 0 3 e .nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + 8 800 30 10 8 REL 0 3 e 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_Z17convertFp32ToFp16P6__halfPfi + 9 0 2432 12 10 e _Z12wmma_exampleP6__halfS0_Pfiiiff + 10 0 0 12 0 0 vprintf + + +.nv.constant0._Z17convertFp32ToFp16P6__halfPfi +0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 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_Z17convertFp32ToFp16P6__halfPfi(0x8) min stack size: 0x0 + <0x6> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) frame size: 0x0 + + +.nv.info._Z17convertFp32ToFp16P6__halfPfi + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x4 0x140160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x14 + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x7> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x60 0xe0 + + +.nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x6 0x2c0160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x2c + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x7 Offset : 0x28 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x6 Offset : 0x24 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x5 Offset : 0x20 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x4 Offset : 0x1c Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x7> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x3 Offset : 0x18 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x8> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x9> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x10> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x11> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x12> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x940 + <0x13> + Attribute: EIATTR_EXTERNS + Format: EIFMT_SVAL + Value: externs: vprintf(0xa) + <0x14> + Attribute: EIATTR_CRS_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x0 + + +.text._Z17convertFp32ToFp16P6__halfPfi +bar = 0 reg = 9 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0x00017a02 0x00000a00 0x00000f00 0x000fd000 +0x00047919 0x00000000 0x00002500 0x000e2200 +0x00027919 0x00000000 0x00002100 0x000e2400 +0x04047a24 0x00000000 0x078e0202 0x001fca00 +0x04007a0c 0x00005c00 0x03f062f0 0x000fd800 +0x0000094d 0x00000000 0x03800000 0x000fea00 +0x00027802 0x00000004 0x00000f00 0x000fca00 +0x04027625 0x00005a00 0x078e0202 0x000fd400 +0x02027381 0x00000000 0x001ee900 0x000e2200 +0x00057802 0x00000002 0x00000f00 0x000fca00 +0x04047625 0x00005800 0x078e0205 0x000fe200 +0x00067304 0x00000002 0x00200800 0x001e3200 +0x04007386 0x00000006 0x0010e500 0x0011e200 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 + + + +.text._Z12wmma_exampleP6__halfS0_Pfiiiff +bar = 0 reg = 32 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0xff017624 0x00000a00 0x078e00ff 0x000fd000 +0x01017810 0xfffffff8 0x07ffe0ff 0x000fc800 +0x01027a10 0x00000800 0x07f1e0ff 0x000fca00 +0xff007624 0x00000900 0x000e06ff 0x000fd000 +0x00037805 0x00000000 0x00005000 0x000fd000 +0x00077906 0x00000020 0x00209000 0x000e2400 +0x00077308 0x00000007 0x00001000 0x001e2200 +0x00067919 0x00000000 0x00002500 0x000e6200 +0x00097919 0x00000000 0x00002100 0x000e6200 +0x07087810 0x0ffffffe 0x07ffe0ff 0x001fcc00 +0x00057305 0x00000008 0x0021f000 0x0000a200 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0x06067a24 0x00000000 0x078e0209 0x002fe400 +0x050a7824 0xffffffe0 0x078e00ff 0x004fc800 +0x05047225 0x0000000a 0x078e0004 0x000fd000 +0x05047225 0x00000006 0x078e00ff 0x000fcc00 +0xff047224 0x000000ff 0x078e0a05 0x000fc800 +0x04067824 0x00000020 0x078e0206 0x000fca00 +0x0600780c 0x00000020 0x03f060f0 0x040fe200 +0x001c7919 0x00000000 0x00002600 0x000e2200 +0x00077919 0x00000000 0x00002200 0x000e3400 +0x06060810 0xffffffe0 0x07ffe0ff 0x000fc800 +0x0600780c 0x00000020 0x03f260f0 0x000fe400 +0x05050810 0x00000001 0x07ffe0ff 0x000fe400 +0xff007a0c 0x00006000 0x03f012f0 0x000fd000 +0x05051810 0x00000001 0x07ffe0ff 0x000fe200 +0x1c1c7a24 0x00000100 0x078e0207 0x001fc600 +0x051d7819 0x00000004 0x000006ff 0x000fe200 +0x1c1c7824 0x00000010 0x078e00ff 0x000fc600 +0x1d007a0c 0x00005e00 0x007012f0 0x000fc800 +0x1c007a0c 0x00005f00 0x007012f0 0x000fe200 +0x00007945 0x000003a0 0x03800000 0x000fe200 +0xff077224 0x000000ff 0x078e00ff 0x000fe200 +0x000b7202 0x000000ff 0x00000f00 0x000fe200 +0xff067224 0x000000ff 0x078e00ff 0x000fe400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0xff0a7224 0x000000ff 0x078e00ff 0x000fc400 +0xff097224 0x000000ff 0x078e00ff 0x000fe400 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00008947 0x00000300 0x03800000 0x000fee00 +0x00067919 0x00000000 0x00000000 0x000e2200 +0xff0a7424 0x00000002 0x078e00ff 0x000fc800 +0x1d107625 0x00005800 0x078e020a 0x000fe200 +0xff047819 0x00000002 0x00011606 0x001fc800 +0x04057812 0x00000003 0x078ec0ff 0x000fe400 +0x06047812 0x00000003 0x078ec0ff 0x000fe400 +0x05077812 0x00000001 0x078ec0ff 0x000fe400 +0xff067819 0x00000004 0x00011606 0x000fe400 +0xff057819 0x00000001 0x00011605 0x000fe200 +0x07077824 0x00000008 0x078e0204 0x000fe200 +0x06067812 0x00000001 0x078ec0ff 0x000fc400 +0x05047211 0x00000004 0x078e18ff 0x000fe200 +0x1c0c7625 0x00005a00 0x078e020a 0x000fe400 +0x06077824 0x00000004 0x078e0207 0x040fe400 +0x06047824 0x00000004 0x078e0204 0x000fe400 +0x07077824 0x00000002 0x078e00ff 0x000fe400 +0x04057824 0x00000002 0x078e00ff 0x000fe400 +0x07107a25 0x00005e00 0x078e0010 0x000fc400 +0x050c7a25 0x00006000 0x078e000c 0x000fd000 +0x10187980 0x00000000 0x0010ed00 0x00006400 +0x0c147980 0x00000000 0x0010ed00 0x00046200 +0x10107980 0x00000010 0x0010ed00 0x001e2200 +0x0c0c7980 0x00000010 0x0010ed00 0x004e2200 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00097202 0x000000ff 0x00000f00 0x000fe200 +0xff0a7224 0x000000ff 0x078e00ff 0x000fe400 +0xff0b7224 0x000000ff 0x078e00ff 0x000fe200 +0x00077202 0x000000ff 0x00000f00 0x000fe200 +0xff047224 0x000000ff 0x078e00ff 0x000fc400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff067224 0x000000ff 0x078e00ff 0x000fe200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x18087236 0x00000014 0x00005408 0x0c226400 +0x180a7236 0x00000014 0x0000d40a 0x0c04a400 +0x18047236 0x00000014 0x00015404 0x0c06e400 +0x18067236 0x00000014 0x0001d406 0x00092800 +0x1a087236 0x00000016 0x00005408 0x0c202400 +0x1a0a7236 0x00000016 0x0000d40a 0x0c426400 +0x1a047236 0x00000016 0x00015404 0x0c84a400 +0x1a067236 0x00000016 0x0001d406 0x0106e800 +0x10087236 0x0000000c 0x00005408 0x0c102400 +0x100a7236 0x0000000c 0x0000d40a 0x0c226400 +0x10047236 0x0000000c 0x00015404 0x0c44a400 +0x10067236 0x0000000c 0x0001d406 0x0086e800 +0x12087236 0x0000000e 0x00005408 0x0c102400 +0x120a7236 0x0000000e 0x0000d40a 0x0c202400 +0x12047236 0x0000000e 0x00015404 0x0c402400 +0x12067236 0x0000000e 0x0001d406 0x00803400 +0x00007941 0x00000000 0x03800000 0x001fea00 +0x000c7919 0x00000000 0x00000000 0x000e2200 +0x1c1c7a24 0x00005e00 0x078e02ff 0x000fe200 +0xff0e7819 0x00000004 0x0001160c 0x001fc400 +0xff0d7819 0x00000002 0x0001160c 0x000fe400 +0x0c0c7812 0x00000003 0x078ec0ff 0x000fe400 +0x0e0e7812 0x00000001 0x078ec0ff 0x000fe400 +0x0d0d7812 0x00000003 0x078ec0ff 0x000fc600 +0x0e0c7824 0x00000004 0x078e020c 0x000fe200 +0x0d0f7812 0x00000001 0x078ec0ff 0x000fe400 +0xff107819 0x00000001 0x0001160d 0x000fe400 +0x0c0d7812 0x00000005 0x078ec0ff 0x040fe400 +0x0c0e7812 0x00000002 0x078ec0ff 0x000fc600 +0x0f0c7824 0x00000008 0x078e020d 0x000fe200 +0xff0f7819 0x0000001f 0x0001141d 0x000fe200 +0x100e7824 0x00000008 0x078e020e 0x000fe200 +0x1d117210 0x0000001c 0x07f1e0ff 0x000fe200 +0xff0d7224 0x000000ff 0x078e00ff 0x000fc600 +0x1c0f7211 0x0000000f 0x000f0eff 0x000fe200 +0x0e0c7a25 0x00005e00 0x078e000c 0x000fe200 +0x110e7a11 0x00005c00 0x078010ff 0x000fe200 +0xff127624 0x00005e00 0x078e00ff 0x000fc600 +0x11117a11 0x00005d00 0x000f140f 0x000fe400 +0x0c107211 0x0000000e 0x078010ff 0x000fe400 +0x120e7819 0x00000002 0x000006ff 0x000fe400 +0xff0f7819 0x0000001e 0x00011612 0x000fe400 +0x0c0d7211 0x00000011 0x000f140d 0x000fe400 +0x0e127211 0x00000010 0x078210ff 0x000fc400 +0x0e117210 0x00000010 0x07f1e0ff 0x040fe400 +0x0e137211 0x0000000d 0x008f140f 0x040fe400 +0x0e157210 0x00000012 0x07f3e0ff 0x000fe200 +0x0f147824 0x00000001 0x000e060d 0x040fe400 +0xff0c7224 0x000000ff 0x078e0010 0x000fe400 +0x0f167824 0x00000001 0x008e0613 0x000fe400 +0xff0e7224 0x000000ff 0x078e0011 0x000fc400 +0xff0f7224 0x000000ff 0x078e0014 0x000fe200 +0x00107202 0x00000015 0x00000f00 0x000fe200 +0xff117224 0x000000ff 0x078e0016 0x000fe200 +0x0c007385 0x00000000 0x0010e908 0x0001e200 +0x0c007385 0x00000008 0x0010e90a 0x0003e800 +0x0e007385 0x00000000 0x0010e909 0x0003e200 +0x0e007385 0x00000008 0x0010e90b 0x0003e200 +0x12007385 0x00000000 0x0010e904 0x0003e200 +0x12007385 0x00000008 0x0010e906 0x0003e200 +0x10007385 0x00000000 0x0010e905 0x0003e200 +0x10007385 0x00000008 0x0010e907 0x0003e200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x02087a10 0x80000800 0x07ffe0ff 0x001fd000 +0x00047805 0x00000000 0x00005000 0x002fd000 +0x04037824 0x00000001 0x078e0a03 0x000fd000 +0x08007387 0x00000003 0x00100800 0x0001e200 +0xff067224 0x000000ff 0x078e0002 0x000fe200 +0x00047802 0x00000000 0x00000f00 0x000fe200 +0xff077224 0x000000ff 0x078e0000 0x000fe200 +0x00057802 0x00000000 0x00000f00 0x000fe400 +0x00147802 0x00000000 0x00000f00 0x000fe400 +0x00157802 0x00000000 0x00000f00 0x000fd000 +0x00007943 0x00000000 0x03c00000 0x001fea00 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 + + +.section .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff REL +2272 $str R_CUDA_ABS32_LO_32 +2304 $str R_CUDA_ABS32_HI_32 +2352 vprintf R_CUDA_ABS47_34 + +.section .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff RELA +2320 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_LO_32 2368 +2336 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_HI_32 2368 + +.section .debug_frame +decodeDebugFrame, frameBuf 0xffffffff, total_length 224 +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x100 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 0 + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_advance_loc4 delta 52 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x970 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 2 + DW_CFA_def_cfa register R1, offset 8 + DW_CFA_advance_loc4 delta 586 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +.section .rel.debug_frame REL +72 _Z17convertFp32ToFp16P6__halfPfi R_NV_64 +184 _Z12wmma_exampleP6__halfS0_Pfiiiff R_NV_64 + diff --git a/cuda-kernels/_cuobjdump_2.sass b/cuda-kernels/_cuobjdump_2.sass new file mode 100644 index 0000000..1b50ed2 --- /dev/null +++ b/cuda-kernels/_cuobjdump_2.sass @@ -0,0 +1,348 @@ + code for sm_70 + Function : _Z17convertFp32ToFp16P6__halfPfi + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ MOV R1, c[0x0][0x28]; /* 0x00000a0000017a02 */ + /* 0x000fd00000000f00 */ + /*0020*/ S2R R4, SR_CTAID.X; /* 0x0000000000047919 */ + /* 0x000e220000002500 */ + /*0030*/ S2R R2, SR_TID.X; /* 0x0000000000027919 */ + /* 0x000e240000002100 */ + /*0040*/ IMAD R4, R4, c[0x0][0x0], R2; /* 0x0000000004047a24 */ + /* 0x001fca00078e0202 */ + /*0050*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT, !PT; /* 0x00005c0004007a0c */ + /* 0x000fd80003f062f0 */ + /*0060*/ @P0 EXIT; /* 0x000000000000094d */ + /* 0x000fea0003800000 */ + /*0070*/ MOV R2, 0x4; /* 0x0000000400027802 */ + /* 0x000fca0000000f00 */ + /*0080*/ IMAD.WIDE R2, R4, R2, c[0x0][0x168]; /* 0x00005a0004027625 */ + /* 0x000fd400078e0202 */ + /*0090*/ LDG.E.SYS R2, [R2]; /* 0x0000000002027381 */ + /* 0x000e2200001ee900 */ + /*00a0*/ MOV R5, 0x2; /* 0x0000000200057802 */ + /* 0x000fca0000000f00 */ + /*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160]; /* 0x0000580004047625 */ + /* 0x000fe200078e0205 */ + /*00c0*/ F2F.F16.F32 R6, R2; /* 0x0000000200067304 */ + /* 0x001e320000200800 */ + /*00d0*/ STG.E.U16.SYS [R4], R6; /* 0x0000000604007386 */ + /* 0x0011e2000010e500 */ + /*00e0*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + ........................................... + + + Function : _Z12wmma_exampleP6__halfS0_Pfiiiff + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ IMAD.U32 R1, RZ, RZ, c[0x0][0x28]; /* 0x00000a00ff017624 */ + /* 0x000fd000078e00ff */ + /*0020*/ IADD3 R1, R1, -0x8, RZ; /* 0xfffffff801017810 */ + /* 0x000fc80007ffe0ff */ + /*0030*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ; /* 0x0000080001027a10 */ + /* 0x000fca0007f1e0ff */ + /*0040*/ IMAD.X R0, RZ, RZ, c[0x0][0x24], P0; /* 0x00000900ff007624 */ + /* 0x000fd000000e06ff */ + /*0050*/ CS2R.32 R3, SR_CLOCKLO; /* 0x0000000000037805 */ + /* 0x000fd00000005000 */ + /*0060*/ I2F.U32.RP R7, 0x20; /* 0x0000002000077906 */ + /* 0x000e240000209000 */ + /*0070*/ MUFU.RCP R7, R7; /* 0x0000000700077308 */ + /* 0x001e220000001000 */ + /*0080*/ S2R R6, SR_CTAID.X; /* 0x0000000000067919 */ + /* 0x000e620000002500 */ + /*0090*/ S2R R9, SR_TID.X; /* 0x0000000000097919 */ + /* 0x000e620000002100 */ + /*00a0*/ IADD3 R8, R7, 0xffffffe, RZ; /* 0x0ffffffe07087810 */ + /* 0x001fcc0007ffe0ff */ + /*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R8; /* 0x0000000800057305 */ + /* 0x0000a2000021f000 */ + /*00c0*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*00d0*/ IMAD R6, R6, c[0x0][0x0], R9; /* 0x0000000006067a24 */ + /* 0x002fe400078e0209 */ + /*00e0*/ IMAD.U32 R10, R5, -0x20, RZ; /* 0xffffffe0050a7824 */ + /* 0x004fc800078e00ff */ + /*00f0*/ IMAD.WIDE.U32 R4, R5, R10, R4; /* 0x0000000a05047225 */ + /* 0x000fd000078e0004 */ + /*0100*/ IMAD.WIDE.U32 R4, R5, R6, RZ; /* 0x0000000605047225 */ + /* 0x000fcc00078e00ff */ + /*0110*/ IMAD R4, RZ, RZ, -R5; /* 0x000000ffff047224 */ + /* 0x000fc800078e0a05 */ + /*0120*/ IMAD R6, R4, 0x20, R6; /* 0x0000002004067824 */ + /* 0x000fca00078e0206 */ + /*0130*/ ISETP.GE.U32.AND P0, PT, R6.reuse, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x040fe20003f060f0 */ + /*0140*/ S2R R28, SR_CTAID.Y; /* 0x00000000001c7919 */ + /* 0x000e220000002600 */ + /*0150*/ S2R R7, SR_TID.Y; /* 0x0000000000077919 */ + /* 0x000e340000002200 */ + /*0160*/ @P0 IADD3 R6, R6, -0x20, RZ; /* 0xffffffe006060810 */ + /* 0x000fc80007ffe0ff */ + /*0170*/ ISETP.GE.U32.AND P1, PT, R6, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x000fe40003f260f0 */ + /*0180*/ @P0 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105050810 */ + /* 0x000fe40007ffe0ff */ + /*0190*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT, !PT; /* 0x00006000ff007a0c */ + /* 0x000fd00003f012f0 */ + /*01a0*/ @P1 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105051810 */ + /* 0x000fe20007ffe0ff */ + /*01b0*/ IMAD R28, R28, c[0x0][0x4], R7; /* 0x000001001c1c7a24 */ + /* 0x001fc600078e0207 */ + /*01c0*/ SHF.L.U32 R29, R5, 0x4, RZ; /* 0x00000004051d7819 */ + /* 0x000fe200000006ff */ + /*01d0*/ IMAD.U32 R28, R28, 0x10, RZ; /* 0x000000101c1c7824 */ + /* 0x000fc600078e00ff */ + /*01e0*/ ISETP.LT.AND P0, PT, R29, c[0x0][0x178], P0, !PT; /* 0x00005e001d007a0c */ + /* 0x000fc800007012f0 */ + /*01f0*/ ISETP.LT.AND P0, PT, R28, c[0x0][0x17c], P0, !PT; /* 0x00005f001c007a0c */ + /* 0x000fe200007012f0 */ + /*0200*/ BSSY B0, 0x5b0; /* 0x000003a000007945 */ + /* 0x000fe20003800000 */ + /*0210*/ IMAD.U32 R7, RZ, RZ, RZ; /* 0x000000ffff077224 */ + /* 0x000fe200078e00ff */ + /*0220*/ MOV R11, RZ; /* 0x000000ff000b7202 */ + /* 0x000fe20000000f00 */ + /*0230*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe400078e00ff */ + /*0240*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0250*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*0260*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fc400078e00ff */ + /*0270*/ IMAD.U32 R9, RZ, RZ, RZ; /* 0x000000ffff097224 */ + /* 0x000fe400078e00ff */ + /*0280*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0290*/ @!P0 BRA 0x5a0; /* 0x0000030000008947 */ + /* 0x000fee0003800000 */ + /*02a0*/ S2R R6, SR_LANEID; /* 0x0000000000067919 */ + /* 0x000e220000000000 */ + /*02b0*/ IMAD.U32 R10, RZ, RZ, 0x2; /* 0x00000002ff0a7424 */ + /* 0x000fc800078e00ff */ + /*02c0*/ IMAD.WIDE R16, R29, R10, c[0x0][0x160]; /* 0x000058001d107625 */ + /* 0x000fe200078e020a */ + /*02d0*/ SHF.R.U32.HI R4, RZ, 0x2, R6; /* 0x00000002ff047819 */ + /* 0x001fc80000011606 */ + /*02e0*/ LOP3.LUT R5, R4, 0x3, RZ, 0xc0, !PT; /* 0x0000000304057812 */ + /* 0x000fe400078ec0ff */ + /*02f0*/ LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT; /* 0x0000000306047812 */ + /* 0x000fe400078ec0ff */ + /*0300*/ LOP3.LUT R7, R5, 0x1, RZ, 0xc0, !PT; /* 0x0000000105077812 */ + /* 0x000fe400078ec0ff */ + /*0310*/ SHF.R.U32.HI R6, RZ, 0x4, R6; /* 0x00000004ff067819 */ + /* 0x000fe40000011606 */ + /*0320*/ SHF.R.U32.HI R5, RZ, 0x1, R5; /* 0x00000001ff057819 */ + /* 0x000fe20000011605 */ + /*0330*/ IMAD R7, R7, 0x8, R4; /* 0x0000000807077824 */ + /* 0x000fe200078e0204 */ + /*0340*/ LOP3.LUT R6, R6, 0x1, RZ, 0xc0, !PT; /* 0x0000000106067812 */ + /* 0x000fc400078ec0ff */ + /*0350*/ LEA R4, R5, R4, 0x3; /* 0x0000000405047211 */ + /* 0x000fe200078e18ff */ + /*0360*/ IMAD.WIDE R12, R28, R10, c[0x0][0x168]; /* 0x00005a001c0c7625 */ + /* 0x000fe400078e020a */ + /*0370*/ IMAD R7, R6.reuse, 0x4, R7; /* 0x0000000406077824 */ + /* 0x040fe400078e0207 */ + /*0380*/ IMAD R4, R6, 0x4, R4; /* 0x0000000406047824 */ + /* 0x000fe400078e0204 */ + /*0390*/ IMAD.U32 R7, R7, 0x2, RZ; /* 0x0000000207077824 */ + /* 0x000fe400078e00ff */ + /*03a0*/ IMAD.U32 R5, R4, 0x2, RZ; /* 0x0000000204057824 */ + /* 0x000fe400078e00ff */ + /*03b0*/ IMAD.WIDE.U32 R16, R7, c[0x0][0x178], R16; /* 0x00005e0007107a25 */ + /* 0x000fc400078e0010 */ + /*03c0*/ IMAD.WIDE.U32 R12, R5, c[0x0][0x180], R12; /* 0x00006000050c7a25 */ + /* 0x000fd000078e000c */ + /*03d0*/ LD.E.128.SYS R24, [R16]; /* 0x0000000010187980 */ + /* 0x000064000010ed00 */ + /*03e0*/ LD.E.128.SYS R20, [R12]; /* 0x000000000c147980 */ + /* 0x000462000010ed00 */ + /*03f0*/ LD.E.128.SYS R16, [R16+0x10]; /* 0x0000001010107980 */ + /* 0x001e22000010ed00 */ + /*0400*/ LD.E.128.SYS R12, [R12+0x10]; /* 0x000000100c0c7980 */ + /* 0x004e22000010ed00 */ + /*0410*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0420*/ MOV R9, RZ; /* 0x000000ff00097202 */ + /* 0x000fe20000000f00 */ + /*0430*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fe400078e00ff */ + /*0440*/ IMAD.U32 R11, RZ, RZ, RZ; /* 0x000000ffff0b7224 */ + /* 0x000fe200078e00ff */ + /*0450*/ MOV R7, RZ; /* 0x000000ff00077202 */ + /* 0x000fe20000000f00 */ + /*0460*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fc400078e00ff */ + /*0470*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0480*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe200078e00ff */ + /*0490*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*04a0*/ HMMA.884.F32.F32.STEP0 R8, R24.reuse, R20.reuse.T, R8; /* 0x0000001418087236 */ + /* 0x0c22640000005408 */ + /*04b0*/ HMMA.884.F32.F32.STEP1 R10, R24.reuse, R20.reuse.T, R10; /* 0x00000014180a7236 */ + /* 0x0c04a4000000d40a */ + /*04c0*/ HMMA.884.F32.F32.STEP2 R4, R24.reuse, R20.reuse.T, R4; /* 0x0000001418047236 */ + /* 0x0c06e40000015404 */ + /*04d0*/ HMMA.884.F32.F32.STEP3 R6, R24, R20.T, R6; /* 0x0000001418067236 */ + /* 0x000928000001d406 */ + /*04e0*/ HMMA.884.F32.F32.STEP0 R8, R26.reuse, R22.reuse.T, R8; /* 0x000000161a087236 */ + /* 0x0c20240000005408 */ + /*04f0*/ HMMA.884.F32.F32.STEP1 R10, R26.reuse, R22.reuse.T, R10; /* 0x000000161a0a7236 */ + /* 0x0c4264000000d40a */ + /*0500*/ HMMA.884.F32.F32.STEP2 R4, R26.reuse, R22.reuse.T, R4; /* 0x000000161a047236 */ + /* 0x0c84a40000015404 */ + /*0510*/ HMMA.884.F32.F32.STEP3 R6, R26, R22.T, R6; /* 0x000000161a067236 */ + /* 0x0106e8000001d406 */ + /*0520*/ HMMA.884.F32.F32.STEP0 R8, R16.reuse, R12.reuse.T, R8; /* 0x0000000c10087236 */ + /* 0x0c10240000005408 */ + /*0530*/ HMMA.884.F32.F32.STEP1 R10, R16.reuse, R12.reuse.T, R10; /* 0x0000000c100a7236 */ + /* 0x0c2264000000d40a */ + /*0540*/ HMMA.884.F32.F32.STEP2 R4, R16.reuse, R12.reuse.T, R4; /* 0x0000000c10047236 */ + /* 0x0c44a40000015404 */ + /*0550*/ HMMA.884.F32.F32.STEP3 R6, R16, R12.T, R6; /* 0x0000000c10067236 */ + /* 0x0086e8000001d406 */ + /*0560*/ HMMA.884.F32.F32.STEP0 R8, R18.reuse, R14.reuse.T, R8; /* 0x0000000e12087236 */ + /* 0x0c10240000005408 */ + /*0570*/ HMMA.884.F32.F32.STEP1 R10, R18.reuse, R14.reuse.T, R10; /* 0x0000000e120a7236 */ + /* 0x0c2024000000d40a */ + /*0580*/ HMMA.884.F32.F32.STEP2 R4, R18.reuse, R14.reuse.T, R4; /* 0x0000000e12047236 */ + /* 0x0c40240000015404 */ + /*0590*/ HMMA.884.F32.F32.STEP3 R6, R18, R14.T, R6; /* 0x0000000e12067236 */ + /* 0x008034000001d406 */ + /*05a0*/ BSYNC B0; /* 0x0000000000007941 */ + /* 0x001fea0003800000 */ + /*05b0*/ S2R R12, SR_LANEID; /* 0x00000000000c7919 */ + /* 0x000e220000000000 */ + /*05c0*/ IMAD R28, R28, c[0x0][0x178], RZ; /* 0x00005e001c1c7a24 */ + /* 0x000fe200078e02ff */ + /*05d0*/ SHF.R.U32.HI R14, RZ, 0x4, R12; /* 0x00000004ff0e7819 */ + /* 0x001fc4000001160c */ + /*05e0*/ SHF.R.U32.HI R13, RZ, 0x2, R12; /* 0x00000002ff0d7819 */ + /* 0x000fe4000001160c */ + /*05f0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT; /* 0x000000030c0c7812 */ + /* 0x000fe400078ec0ff */ + /*0600*/ LOP3.LUT R14, R14, 0x1, RZ, 0xc0, !PT; /* 0x000000010e0e7812 */ + /* 0x000fe400078ec0ff */ + /*0610*/ LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT; /* 0x000000030d0d7812 */ + /* 0x000fc600078ec0ff */ + /*0620*/ IMAD R12, R14, 0x4, R12; /* 0x000000040e0c7824 */ + /* 0x000fe200078e020c */ + /*0630*/ LOP3.LUT R15, R13, 0x1, RZ, 0xc0, !PT; /* 0x000000010d0f7812 */ + /* 0x000fe400078ec0ff */ + /*0640*/ SHF.R.U32.HI R16, RZ, 0x1, R13; /* 0x00000001ff107819 */ + /* 0x000fe4000001160d */ + /*0650*/ LOP3.LUT R13, R12.reuse, 0x5, RZ, 0xc0, !PT; /* 0x000000050c0d7812 */ + /* 0x040fe400078ec0ff */ + /*0660*/ LOP3.LUT R14, R12, 0x2, RZ, 0xc0, !PT; /* 0x000000020c0e7812 */ + /* 0x000fc600078ec0ff */ + /*0670*/ IMAD R12, R15, 0x8, R13; /* 0x000000080f0c7824 */ + /* 0x000fe200078e020d */ + /*0680*/ SHF.R.S32.HI R15, RZ, 0x1f, R29; /* 0x0000001fff0f7819 */ + /* 0x000fe2000001141d */ + /*0690*/ IMAD R14, R16, 0x8, R14; /* 0x00000008100e7824 */ + /* 0x000fe200078e020e */ + /*06a0*/ IADD3 R17, P0, R29, R28, RZ; /* 0x0000001c1d117210 */ + /* 0x000fe20007f1e0ff */ + /*06b0*/ IMAD.U32 R13, RZ, RZ, RZ; /* 0x000000ffff0d7224 */ + /* 0x000fc600078e00ff */ + /*06c0*/ LEA.HI.X.SX32 R15, R28, R15, 0x1, P0; /* 0x0000000f1c0f7211 */ + /* 0x000fe200000f0eff */ + /*06d0*/ IMAD.WIDE.U32 R12, R14, c[0x0][0x178], R12; /* 0x00005e000e0c7a25 */ + /* 0x000fe200078e000c */ + /*06e0*/ LEA R14, P0, R17, c[0x0][0x170], 0x2; /* 0x00005c00110e7a11 */ + /* 0x000fe200078010ff */ + /*06f0*/ IMAD.U32 R18, RZ, RZ, c[0x0][0x178]; /* 0x00005e00ff127624 */ + /* 0x000fc600078e00ff */ + /*0700*/ LEA.HI.X R17, R17, c[0x0][0x174], R15, 0x2, P0; /* 0x00005d0011117a11 */ + /* 0x000fe400000f140f */ + /*0710*/ LEA R16, P0, R12, R14, 0x2; /* 0x0000000e0c107211 */ + /* 0x000fe400078010ff */ + /*0720*/ SHF.L.U32 R14, R18, 0x2, RZ; /* 0x00000002120e7819 */ + /* 0x000fe400000006ff */ + /*0730*/ SHF.R.U32.HI R15, RZ, 0x1e, R18; /* 0x0000001eff0f7819 */ + /* 0x000fe40000011612 */ + /*0740*/ LEA.HI.X R13, R12, R17, R13, 0x2, P0; /* 0x000000110c0d7211 */ + /* 0x000fe400000f140d */ + /*0750*/ LEA R18, P1, R14, R16, 0x2; /* 0x000000100e127211 */ + /* 0x000fc400078210ff */ + /*0760*/ IADD3 R17, P0, R14.reuse, R16, RZ; /* 0x000000100e117210 */ + /* 0x040fe40007f1e0ff */ + /*0770*/ LEA.HI.X R19, R14.reuse, R13, R15, 0x2, P1; /* 0x0000000d0e137211 */ + /* 0x040fe400008f140f */ + /*0780*/ IADD3 R21, P1, R14, R18, RZ; /* 0x000000120e157210 */ + /* 0x000fe20007f3e0ff */ + /*0790*/ IMAD.X R20, R15.reuse, 0x1, R13, P0; /* 0x000000010f147824 */ + /* 0x040fe400000e060d */ + /*07a0*/ IMAD.U32 R12, RZ, RZ, R16; /* 0x000000ffff0c7224 */ + /* 0x000fe400078e0010 */ + /*07b0*/ IMAD.X R22, R15, 0x1, R19, P1; /* 0x000000010f167824 */ + /* 0x000fe400008e0613 */ + /*07c0*/ IMAD.U32 R14, RZ, RZ, R17; /* 0x000000ffff0e7224 */ + /* 0x000fc400078e0011 */ + /*07d0*/ IMAD.U32 R15, RZ, RZ, R20; /* 0x000000ffff0f7224 */ + /* 0x000fe200078e0014 */ + /*07e0*/ MOV R16, R21; /* 0x0000001500107202 */ + /* 0x000fe20000000f00 */ + /*07f0*/ IMAD.U32 R17, RZ, RZ, R22; /* 0x000000ffff117224 */ + /* 0x000fe200078e0016 */ + /*0800*/ ST.E.SYS [R12], R8; /* 0x000000000c007385 */ + /* 0x0001e2000010e908 */ + /*0810*/ ST.E.SYS [R12+0x8], R10; /* 0x000000080c007385 */ + /* 0x0003e8000010e90a */ + /*0820*/ ST.E.SYS [R14], R9; /* 0x000000000e007385 */ + /* 0x0003e2000010e909 */ + /*0830*/ ST.E.SYS [R14+0x8], R11; /* 0x000000080e007385 */ + /* 0x0003e2000010e90b */ + /*0840*/ ST.E.SYS [R18], R4; /* 0x0000000012007385 */ + /* 0x0003e2000010e904 */ + /*0850*/ ST.E.SYS [R18+0x8], R6; /* 0x0000000812007385 */ + /* 0x0003e2000010e906 */ + /*0860*/ ST.E.SYS [R16], R5; /* 0x0000000010007385 */ + /* 0x0003e2000010e905 */ + /*0870*/ ST.E.SYS [R16+0x8], R7; /* 0x0000000810007385 */ + /* 0x0003e2000010e907 */ + /*0880*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*0890*/ IADD3 R8, R2, -c[0x0][0x20], RZ; /* 0x8000080002087a10 */ + /* 0x001fd00007ffe0ff */ + /*08a0*/ CS2R.32 R4, SR_CLOCKLO; /* 0x0000000000047805 */ + /* 0x002fd00000005000 */ + /*08b0*/ IMAD R3, R4, 0x1, -R3; /* 0x0000000104037824 */ + /* 0x000fd000078e0a03 */ + /*08c0*/ STL [R8], R3; /* 0x0000000308007387 */ + /* 0x0001e20000100800 */ + /*08d0*/ IMAD.U32 R6, RZ, RZ, R2; /* 0x000000ffff067224 */ + /* 0x000fe200078e0002 */ + /*08e0*/ MOV R4, 0x0; /* 0x0000000000047802 */ + /* 0x000fe20000000f00 */ + /*08f0*/ IMAD.U32 R7, RZ, RZ, R0; /* 0x000000ffff077224 */ + /* 0x000fe200078e0000 */ + /*0900*/ MOV R5, 0x0; /* 0x0000000000057802 */ + /* 0x000fe40000000f00 */ + /*0910*/ MOV R20, 0x0; /* 0x0000000000147802 */ + /* 0x000fe40000000f00 */ + /*0920*/ MOV R21, 0x0; /* 0x0000000000157802 */ + /* 0x000fd00000000f00 */ + /*0930*/ CALL.ABS.NOINC 0x0; /* 0x0000000000007943 */ + /* 0x001fea0003c00000 */ + /*0940*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*0950*/ BRA 0x950; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + /*0960*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + /*0970*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + ............................................. + + + diff --git a/cuda-kernels/_cuobjdump_complete_output_EIGzTK b/cuda-kernels/_cuobjdump_complete_output_EIGzTK new file mode 100644 index 0000000..36999c0 --- /dev/null +++ b/cuda-kernels/_cuobjdump_complete_output_EIGzTK @@ -0,0 +1,1055 @@ + +Fatbin elf code: +================ +arch = sm_70 +code version = [1,7] +producer = +host = linux +compile_size = 64bit + +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 32 0 1 STRTAB 0 0 0 .shstrtab + 2 72 32 0 1 STRTAB 0 0 0 .strtab + 3 a8 18 18 8 SYMTAB 0 2 0 .symtab + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + + code for sm_70 + +Fatbin elf code: +================ +arch = sm_70 +code version = [1,7] +producer = cuda +host = linux +compile_size = 64bit + +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 21b 0 1 STRTAB 0 0 0 .shstrtab + 2 25b 273 0 1 STRTAB 0 0 0 .strtab + 3 4d0 108 18 8 SYMTAB 0 2 7 .symtab + 4 5d8 e0 0 1 PROGBITS 0 0 0 .debug_frame + 5 6b8 48 0 4 CUDA_INFO 0 3 0 .nv.info + 6 700 50 0 4 CUDA_INFO 0 3 d .nv.info._Z17convertFp32ToFp16P6__halfPfi + 7 750 ac 0 4 CUDA_INFO 0 3 e .nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + 8 800 30 10 8 REL 0 3 e .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff + 9 830 30 18 8 RELA 0 3 e .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff + a 860 20 10 8 REL 0 3 4 .rel.debug_frame + b 880 174 0 4 PROGBITS 2 0 d .nv.constant0._Z17convertFp32ToFp16P6__halfPfi + c 9f4 18c 0 4 PROGBITS 2 0 e .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff + d b80 100 0 80 PROGBITS 6 3 9000008 .text._Z17convertFp32ToFp16P6__halfPfi + e c80 980 0 80 PROGBITS 6 3 20000009 .text._Z12wmma_exampleP6__halfS0_Pfiiiff + f 1600 9 0 10 PROGBITS 3 0 0 .nv.global.init + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + 1 0 0 3 0 d .text._Z17convertFp32ToFp16P6__halfPfi + 2 0 0 3 0 f .nv.global.init + 3 0 9 1 0 f $str + 4 0 0 3 0 b .nv.constant0._Z17convertFp32ToFp16P6__halfPfi + 5 0 0 3 0 e .text._Z12wmma_exampleP6__halfS0_Pfiiiff + 6 0 0 3 0 c .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff + 7 0 0 3 0 4 .debug_frame + 8 0 256 12 10 d _Z17convertFp32ToFp16P6__halfPfi + 9 0 2432 12 10 e _Z12wmma_exampleP6__halfS0_Pfiiiff + 10 0 0 12 0 0 vprintf + + +.nv.constant0._Z17convertFp32ToFp16P6__halfPfi +0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 + + + +.nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff +0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 + + +.nv.global.init +0x636f6c63 0x64253d6b 0 + + +.nv.info + <0x1> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x9 0x0 + <0x2> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) min stack size: 0x8 + <0x3> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) frame size: 0x8 + <0x4> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x8 0x0 + <0x5> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) min stack size: 0x0 + <0x6> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) frame size: 0x0 + + +.nv.info._Z17convertFp32ToFp16P6__halfPfi + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x4 0x140160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x14 + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x7> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x60 0xe0 + + +.nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x6 0x2c0160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x2c + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x7 Offset : 0x28 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x6 Offset : 0x24 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x5 Offset : 0x20 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x4 Offset : 0x1c Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x7> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x3 Offset : 0x18 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x8> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x9> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x10> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x11> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x12> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x940 + <0x13> + Attribute: EIATTR_EXTERNS + Format: EIFMT_SVAL + Value: externs: vprintf(0xa) + <0x14> + Attribute: EIATTR_CRS_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x0 + + +.text._Z17convertFp32ToFp16P6__halfPfi +bar = 0 reg = 9 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0x00017a02 0x00000a00 0x00000f00 0x000fd000 +0x00047919 0x00000000 0x00002500 0x000e2200 +0x00027919 0x00000000 0x00002100 0x000e2400 +0x04047a24 0x00000000 0x078e0202 0x001fca00 +0x04007a0c 0x00005c00 0x03f062f0 0x000fd800 +0x0000094d 0x00000000 0x03800000 0x000fea00 +0x00027802 0x00000004 0x00000f00 0x000fca00 +0x04027625 0x00005a00 0x078e0202 0x000fd400 +0x02027381 0x00000000 0x001ee900 0x000e2200 +0x00057802 0x00000002 0x00000f00 0x000fca00 +0x04047625 0x00005800 0x078e0205 0x000fe200 +0x00067304 0x00000002 0x00200800 0x001e3200 +0x04007386 0x00000006 0x0010e500 0x0011e200 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 + + + +.text._Z12wmma_exampleP6__halfS0_Pfiiiff +bar = 0 reg = 32 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0xff017624 0x00000a00 0x078e00ff 0x000fd000 +0x01017810 0xfffffff8 0x07ffe0ff 0x000fc800 +0x01027a10 0x00000800 0x07f1e0ff 0x000fca00 +0xff007624 0x00000900 0x000e06ff 0x000fd000 +0x00037805 0x00000000 0x00005000 0x000fd000 +0x00077906 0x00000020 0x00209000 0x000e2400 +0x00077308 0x00000007 0x00001000 0x001e2200 +0x00067919 0x00000000 0x00002500 0x000e6200 +0x00097919 0x00000000 0x00002100 0x000e6200 +0x07087810 0x0ffffffe 0x07ffe0ff 0x001fcc00 +0x00057305 0x00000008 0x0021f000 0x0000a200 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0x06067a24 0x00000000 0x078e0209 0x002fe400 +0x050a7824 0xffffffe0 0x078e00ff 0x004fc800 +0x05047225 0x0000000a 0x078e0004 0x000fd000 +0x05047225 0x00000006 0x078e00ff 0x000fcc00 +0xff047224 0x000000ff 0x078e0a05 0x000fc800 +0x04067824 0x00000020 0x078e0206 0x000fca00 +0x0600780c 0x00000020 0x03f060f0 0x040fe200 +0x001c7919 0x00000000 0x00002600 0x000e2200 +0x00077919 0x00000000 0x00002200 0x000e3400 +0x06060810 0xffffffe0 0x07ffe0ff 0x000fc800 +0x0600780c 0x00000020 0x03f260f0 0x000fe400 +0x05050810 0x00000001 0x07ffe0ff 0x000fe400 +0xff007a0c 0x00006000 0x03f012f0 0x000fd000 +0x05051810 0x00000001 0x07ffe0ff 0x000fe200 +0x1c1c7a24 0x00000100 0x078e0207 0x001fc600 +0x051d7819 0x00000004 0x000006ff 0x000fe200 +0x1c1c7824 0x00000010 0x078e00ff 0x000fc600 +0x1d007a0c 0x00005e00 0x007012f0 0x000fc800 +0x1c007a0c 0x00005f00 0x007012f0 0x000fe200 +0x00007945 0x000003a0 0x03800000 0x000fe200 +0xff077224 0x000000ff 0x078e00ff 0x000fe200 +0x000b7202 0x000000ff 0x00000f00 0x000fe200 +0xff067224 0x000000ff 0x078e00ff 0x000fe400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0xff0a7224 0x000000ff 0x078e00ff 0x000fc400 +0xff097224 0x000000ff 0x078e00ff 0x000fe400 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00008947 0x00000300 0x03800000 0x000fee00 +0x00067919 0x00000000 0x00000000 0x000e2200 +0xff0a7424 0x00000002 0x078e00ff 0x000fc800 +0x1d107625 0x00005800 0x078e020a 0x000fe200 +0xff047819 0x00000002 0x00011606 0x001fc800 +0x04057812 0x00000003 0x078ec0ff 0x000fe400 +0x06047812 0x00000003 0x078ec0ff 0x000fe400 +0x05077812 0x00000001 0x078ec0ff 0x000fe400 +0xff067819 0x00000004 0x00011606 0x000fe400 +0xff057819 0x00000001 0x00011605 0x000fe200 +0x07077824 0x00000008 0x078e0204 0x000fe200 +0x06067812 0x00000001 0x078ec0ff 0x000fc400 +0x05047211 0x00000004 0x078e18ff 0x000fe200 +0x1c0c7625 0x00005a00 0x078e020a 0x000fe400 +0x06077824 0x00000004 0x078e0207 0x040fe400 +0x06047824 0x00000004 0x078e0204 0x000fe400 +0x07077824 0x00000002 0x078e00ff 0x000fe400 +0x04057824 0x00000002 0x078e00ff 0x000fe400 +0x07107a25 0x00005e00 0x078e0010 0x000fc400 +0x050c7a25 0x00006000 0x078e000c 0x000fd000 +0x10187980 0x00000000 0x0010ed00 0x00006400 +0x0c147980 0x00000000 0x0010ed00 0x00046200 +0x10107980 0x00000010 0x0010ed00 0x001e2200 +0x0c0c7980 0x00000010 0x0010ed00 0x004e2200 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00097202 0x000000ff 0x00000f00 0x000fe200 +0xff0a7224 0x000000ff 0x078e00ff 0x000fe400 +0xff0b7224 0x000000ff 0x078e00ff 0x000fe200 +0x00077202 0x000000ff 0x00000f00 0x000fe200 +0xff047224 0x000000ff 0x078e00ff 0x000fc400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff067224 0x000000ff 0x078e00ff 0x000fe200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x18087236 0x00000014 0x00005408 0x0c226400 +0x180a7236 0x00000014 0x0000d40a 0x0c04a400 +0x18047236 0x00000014 0x00015404 0x0c06e400 +0x18067236 0x00000014 0x0001d406 0x00092800 +0x1a087236 0x00000016 0x00005408 0x0c202400 +0x1a0a7236 0x00000016 0x0000d40a 0x0c426400 +0x1a047236 0x00000016 0x00015404 0x0c84a400 +0x1a067236 0x00000016 0x0001d406 0x0106e800 +0x10087236 0x0000000c 0x00005408 0x0c102400 +0x100a7236 0x0000000c 0x0000d40a 0x0c226400 +0x10047236 0x0000000c 0x00015404 0x0c44a400 +0x10067236 0x0000000c 0x0001d406 0x0086e800 +0x12087236 0x0000000e 0x00005408 0x0c102400 +0x120a7236 0x0000000e 0x0000d40a 0x0c202400 +0x12047236 0x0000000e 0x00015404 0x0c402400 +0x12067236 0x0000000e 0x0001d406 0x00803400 +0x00007941 0x00000000 0x03800000 0x001fea00 +0x000c7919 0x00000000 0x00000000 0x000e2200 +0x1c1c7a24 0x00005e00 0x078e02ff 0x000fe200 +0xff0e7819 0x00000004 0x0001160c 0x001fc400 +0xff0d7819 0x00000002 0x0001160c 0x000fe400 +0x0c0c7812 0x00000003 0x078ec0ff 0x000fe400 +0x0e0e7812 0x00000001 0x078ec0ff 0x000fe400 +0x0d0d7812 0x00000003 0x078ec0ff 0x000fc600 +0x0e0c7824 0x00000004 0x078e020c 0x000fe200 +0x0d0f7812 0x00000001 0x078ec0ff 0x000fe400 +0xff107819 0x00000001 0x0001160d 0x000fe400 +0x0c0d7812 0x00000005 0x078ec0ff 0x040fe400 +0x0c0e7812 0x00000002 0x078ec0ff 0x000fc600 +0x0f0c7824 0x00000008 0x078e020d 0x000fe200 +0xff0f7819 0x0000001f 0x0001141d 0x000fe200 +0x100e7824 0x00000008 0x078e020e 0x000fe200 +0x1d117210 0x0000001c 0x07f1e0ff 0x000fe200 +0xff0d7224 0x000000ff 0x078e00ff 0x000fc600 +0x1c0f7211 0x0000000f 0x000f0eff 0x000fe200 +0x0e0c7a25 0x00005e00 0x078e000c 0x000fe200 +0x110e7a11 0x00005c00 0x078010ff 0x000fe200 +0xff127624 0x00005e00 0x078e00ff 0x000fc600 +0x11117a11 0x00005d00 0x000f140f 0x000fe400 +0x0c107211 0x0000000e 0x078010ff 0x000fe400 +0x120e7819 0x00000002 0x000006ff 0x000fe400 +0xff0f7819 0x0000001e 0x00011612 0x000fe400 +0x0c0d7211 0x00000011 0x000f140d 0x000fe400 +0x0e127211 0x00000010 0x078210ff 0x000fc400 +0x0e117210 0x00000010 0x07f1e0ff 0x040fe400 +0x0e137211 0x0000000d 0x008f140f 0x040fe400 +0x0e157210 0x00000012 0x07f3e0ff 0x000fe200 +0x0f147824 0x00000001 0x000e060d 0x040fe400 +0xff0c7224 0x000000ff 0x078e0010 0x000fe400 +0x0f167824 0x00000001 0x008e0613 0x000fe400 +0xff0e7224 0x000000ff 0x078e0011 0x000fc400 +0xff0f7224 0x000000ff 0x078e0014 0x000fe200 +0x00107202 0x00000015 0x00000f00 0x000fe200 +0xff117224 0x000000ff 0x078e0016 0x000fe200 +0x0c007385 0x00000000 0x0010e908 0x0001e200 +0x0c007385 0x00000008 0x0010e90a 0x0003e800 +0x0e007385 0x00000000 0x0010e909 0x0003e200 +0x0e007385 0x00000008 0x0010e90b 0x0003e200 +0x12007385 0x00000000 0x0010e904 0x0003e200 +0x12007385 0x00000008 0x0010e906 0x0003e200 +0x10007385 0x00000000 0x0010e905 0x0003e200 +0x10007385 0x00000008 0x0010e907 0x0003e200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x02087a10 0x80000800 0x07ffe0ff 0x001fd000 +0x00047805 0x00000000 0x00005000 0x002fd000 +0x04037824 0x00000001 0x078e0a03 0x000fd000 +0x08007387 0x00000003 0x00100800 0x0001e200 +0xff067224 0x000000ff 0x078e0002 0x000fe200 +0x00047802 0x00000000 0x00000f00 0x000fe200 +0xff077224 0x000000ff 0x078e0000 0x000fe200 +0x00057802 0x00000000 0x00000f00 0x000fe400 +0x00147802 0x00000000 0x00000f00 0x000fe400 +0x00157802 0x00000000 0x00000f00 0x000fd000 +0x00007943 0x00000000 0x03c00000 0x001fea00 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 + + +.section .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff REL +2272 $str R_CUDA_ABS32_LO_32 +2304 $str R_CUDA_ABS32_HI_32 +2352 vprintf R_CUDA_ABS47_34 + +.section .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff RELA +2320 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_LO_32 2368 +2336 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_HI_32 2368 + +.section .debug_frame +decodeDebugFrame, frameBuf 0xffffffff, total_length 224 +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x100 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 0 + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_advance_loc4 delta 52 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x970 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 2 + DW_CFA_def_cfa register R1, offset 8 + DW_CFA_advance_loc4 delta 586 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +.section .rel.debug_frame REL +72 _Z17convertFp32ToFp16P6__halfPfi R_NV_64 +184 _Z12wmma_exampleP6__halfS0_Pfiiiff R_NV_64 + + code for sm_70 + Function : _Z17convertFp32ToFp16P6__halfPfi + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ MOV R1, c[0x0][0x28]; /* 0x00000a0000017a02 */ + /* 0x000fd00000000f00 */ + /*0020*/ S2R R4, SR_CTAID.X; /* 0x0000000000047919 */ + /* 0x000e220000002500 */ + /*0030*/ S2R R2, SR_TID.X; /* 0x0000000000027919 */ + /* 0x000e240000002100 */ + /*0040*/ IMAD R4, R4, c[0x0][0x0], R2; /* 0x0000000004047a24 */ + /* 0x001fca00078e0202 */ + /*0050*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT, !PT; /* 0x00005c0004007a0c */ + /* 0x000fd80003f062f0 */ + /*0060*/ @P0 EXIT; /* 0x000000000000094d */ + /* 0x000fea0003800000 */ + /*0070*/ MOV R2, 0x4; /* 0x0000000400027802 */ + /* 0x000fca0000000f00 */ + /*0080*/ IMAD.WIDE R2, R4, R2, c[0x0][0x168]; /* 0x00005a0004027625 */ + /* 0x000fd400078e0202 */ + /*0090*/ LDG.E.SYS R2, [R2]; /* 0x0000000002027381 */ + /* 0x000e2200001ee900 */ + /*00a0*/ MOV R5, 0x2; /* 0x0000000200057802 */ + /* 0x000fca0000000f00 */ + /*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160]; /* 0x0000580004047625 */ + /* 0x000fe200078e0205 */ + /*00c0*/ F2F.F16.F32 R6, R2; /* 0x0000000200067304 */ + /* 0x001e320000200800 */ + /*00d0*/ STG.E.U16.SYS [R4], R6; /* 0x0000000604007386 */ + /* 0x0011e2000010e500 */ + /*00e0*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + ........................................... + + + Function : _Z12wmma_exampleP6__halfS0_Pfiiiff + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ IMAD.U32 R1, RZ, RZ, c[0x0][0x28]; /* 0x00000a00ff017624 */ + /* 0x000fd000078e00ff */ + /*0020*/ IADD3 R1, R1, -0x8, RZ; /* 0xfffffff801017810 */ + /* 0x000fc80007ffe0ff */ + /*0030*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ; /* 0x0000080001027a10 */ + /* 0x000fca0007f1e0ff */ + /*0040*/ IMAD.X R0, RZ, RZ, c[0x0][0x24], P0; /* 0x00000900ff007624 */ + /* 0x000fd000000e06ff */ + /*0050*/ CS2R.32 R3, SR_CLOCKLO; /* 0x0000000000037805 */ + /* 0x000fd00000005000 */ + /*0060*/ I2F.U32.RP R7, 0x20; /* 0x0000002000077906 */ + /* 0x000e240000209000 */ + /*0070*/ MUFU.RCP R7, R7; /* 0x0000000700077308 */ + /* 0x001e220000001000 */ + /*0080*/ S2R R6, SR_CTAID.X; /* 0x0000000000067919 */ + /* 0x000e620000002500 */ + /*0090*/ S2R R9, SR_TID.X; /* 0x0000000000097919 */ + /* 0x000e620000002100 */ + /*00a0*/ IADD3 R8, R7, 0xffffffe, RZ; /* 0x0ffffffe07087810 */ + /* 0x001fcc0007ffe0ff */ + /*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R8; /* 0x0000000800057305 */ + /* 0x0000a2000021f000 */ + /*00c0*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*00d0*/ IMAD R6, R6, c[0x0][0x0], R9; /* 0x0000000006067a24 */ + /* 0x002fe400078e0209 */ + /*00e0*/ IMAD.U32 R10, R5, -0x20, RZ; /* 0xffffffe0050a7824 */ + /* 0x004fc800078e00ff */ + /*00f0*/ IMAD.WIDE.U32 R4, R5, R10, R4; /* 0x0000000a05047225 */ + /* 0x000fd000078e0004 */ + /*0100*/ IMAD.WIDE.U32 R4, R5, R6, RZ; /* 0x0000000605047225 */ + /* 0x000fcc00078e00ff */ + /*0110*/ IMAD R4, RZ, RZ, -R5; /* 0x000000ffff047224 */ + /* 0x000fc800078e0a05 */ + /*0120*/ IMAD R6, R4, 0x20, R6; /* 0x0000002004067824 */ + /* 0x000fca00078e0206 */ + /*0130*/ ISETP.GE.U32.AND P0, PT, R6.reuse, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x040fe20003f060f0 */ + /*0140*/ S2R R28, SR_CTAID.Y; /* 0x00000000001c7919 */ + /* 0x000e220000002600 */ + /*0150*/ S2R R7, SR_TID.Y; /* 0x0000000000077919 */ + /* 0x000e340000002200 */ + /*0160*/ @P0 IADD3 R6, R6, -0x20, RZ; /* 0xffffffe006060810 */ + /* 0x000fc80007ffe0ff */ + /*0170*/ ISETP.GE.U32.AND P1, PT, R6, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x000fe40003f260f0 */ + /*0180*/ @P0 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105050810 */ + /* 0x000fe40007ffe0ff */ + /*0190*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT, !PT; /* 0x00006000ff007a0c */ + /* 0x000fd00003f012f0 */ + /*01a0*/ @P1 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105051810 */ + /* 0x000fe20007ffe0ff */ + /*01b0*/ IMAD R28, R28, c[0x0][0x4], R7; /* 0x000001001c1c7a24 */ + /* 0x001fc600078e0207 */ + /*01c0*/ SHF.L.U32 R29, R5, 0x4, RZ; /* 0x00000004051d7819 */ + /* 0x000fe200000006ff */ + /*01d0*/ IMAD.U32 R28, R28, 0x10, RZ; /* 0x000000101c1c7824 */ + /* 0x000fc600078e00ff */ + /*01e0*/ ISETP.LT.AND P0, PT, R29, c[0x0][0x178], P0, !PT; /* 0x00005e001d007a0c */ + /* 0x000fc800007012f0 */ + /*01f0*/ ISETP.LT.AND P0, PT, R28, c[0x0][0x17c], P0, !PT; /* 0x00005f001c007a0c */ + /* 0x000fe200007012f0 */ + /*0200*/ BSSY B0, 0x5b0; /* 0x000003a000007945 */ + /* 0x000fe20003800000 */ + /*0210*/ IMAD.U32 R7, RZ, RZ, RZ; /* 0x000000ffff077224 */ + /* 0x000fe200078e00ff */ + /*0220*/ MOV R11, RZ; /* 0x000000ff000b7202 */ + /* 0x000fe20000000f00 */ + /*0230*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe400078e00ff */ + /*0240*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0250*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*0260*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fc400078e00ff */ + /*0270*/ IMAD.U32 R9, RZ, RZ, RZ; /* 0x000000ffff097224 */ + /* 0x000fe400078e00ff */ + /*0280*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0290*/ @!P0 BRA 0x5a0; /* 0x0000030000008947 */ + /* 0x000fee0003800000 */ + /*02a0*/ S2R R6, SR_LANEID; /* 0x0000000000067919 */ + /* 0x000e220000000000 */ + /*02b0*/ IMAD.U32 R10, RZ, RZ, 0x2; /* 0x00000002ff0a7424 */ + /* 0x000fc800078e00ff */ + /*02c0*/ IMAD.WIDE R16, R29, R10, c[0x0][0x160]; /* 0x000058001d107625 */ + /* 0x000fe200078e020a */ + /*02d0*/ SHF.R.U32.HI R4, RZ, 0x2, R6; /* 0x00000002ff047819 */ + /* 0x001fc80000011606 */ + /*02e0*/ LOP3.LUT R5, R4, 0x3, RZ, 0xc0, !PT; /* 0x0000000304057812 */ + /* 0x000fe400078ec0ff */ + /*02f0*/ LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT; /* 0x0000000306047812 */ + /* 0x000fe400078ec0ff */ + /*0300*/ LOP3.LUT R7, R5, 0x1, RZ, 0xc0, !PT; /* 0x0000000105077812 */ + /* 0x000fe400078ec0ff */ + /*0310*/ SHF.R.U32.HI R6, RZ, 0x4, R6; /* 0x00000004ff067819 */ + /* 0x000fe40000011606 */ + /*0320*/ SHF.R.U32.HI R5, RZ, 0x1, R5; /* 0x00000001ff057819 */ + /* 0x000fe20000011605 */ + /*0330*/ IMAD R7, R7, 0x8, R4; /* 0x0000000807077824 */ + /* 0x000fe200078e0204 */ + /*0340*/ LOP3.LUT R6, R6, 0x1, RZ, 0xc0, !PT; /* 0x0000000106067812 */ + /* 0x000fc400078ec0ff */ + /*0350*/ LEA R4, R5, R4, 0x3; /* 0x0000000405047211 */ + /* 0x000fe200078e18ff */ + /*0360*/ IMAD.WIDE R12, R28, R10, c[0x0][0x168]; /* 0x00005a001c0c7625 */ + /* 0x000fe400078e020a */ + /*0370*/ IMAD R7, R6.reuse, 0x4, R7; /* 0x0000000406077824 */ + /* 0x040fe400078e0207 */ + /*0380*/ IMAD R4, R6, 0x4, R4; /* 0x0000000406047824 */ + /* 0x000fe400078e0204 */ + /*0390*/ IMAD.U32 R7, R7, 0x2, RZ; /* 0x0000000207077824 */ + /* 0x000fe400078e00ff */ + /*03a0*/ IMAD.U32 R5, R4, 0x2, RZ; /* 0x0000000204057824 */ + /* 0x000fe400078e00ff */ + /*03b0*/ IMAD.WIDE.U32 R16, R7, c[0x0][0x178], R16; /* 0x00005e0007107a25 */ + /* 0x000fc400078e0010 */ + /*03c0*/ IMAD.WIDE.U32 R12, R5, c[0x0][0x180], R12; /* 0x00006000050c7a25 */ + /* 0x000fd000078e000c */ + /*03d0*/ LD.E.128.SYS R24, [R16]; /* 0x0000000010187980 */ + /* 0x000064000010ed00 */ + /*03e0*/ LD.E.128.SYS R20, [R12]; /* 0x000000000c147980 */ + /* 0x000462000010ed00 */ + /*03f0*/ LD.E.128.SYS R16, [R16+0x10]; /* 0x0000001010107980 */ + /* 0x001e22000010ed00 */ + /*0400*/ LD.E.128.SYS R12, [R12+0x10]; /* 0x000000100c0c7980 */ + /* 0x004e22000010ed00 */ + /*0410*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0420*/ MOV R9, RZ; /* 0x000000ff00097202 */ + /* 0x000fe20000000f00 */ + /*0430*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fe400078e00ff */ + /*0440*/ IMAD.U32 R11, RZ, RZ, RZ; /* 0x000000ffff0b7224 */ + /* 0x000fe200078e00ff */ + /*0450*/ MOV R7, RZ; /* 0x000000ff00077202 */ + /* 0x000fe20000000f00 */ + /*0460*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fc400078e00ff */ + /*0470*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0480*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe200078e00ff */ + /*0490*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*04a0*/ HMMA.884.F32.F32.STEP0 R8, R24.reuse, R20.reuse.T, R8; /* 0x0000001418087236 */ + /* 0x0c22640000005408 */ + /*04b0*/ HMMA.884.F32.F32.STEP1 R10, R24.reuse, R20.reuse.T, R10; /* 0x00000014180a7236 */ + /* 0x0c04a4000000d40a */ + /*04c0*/ HMMA.884.F32.F32.STEP2 R4, R24.reuse, R20.reuse.T, R4; /* 0x0000001418047236 */ + /* 0x0c06e40000015404 */ + /*04d0*/ HMMA.884.F32.F32.STEP3 R6, R24, R20.T, R6; /* 0x0000001418067236 */ + /* 0x000928000001d406 */ + /*04e0*/ HMMA.884.F32.F32.STEP0 R8, R26.reuse, R22.reuse.T, R8; /* 0x000000161a087236 */ + /* 0x0c20240000005408 */ + /*04f0*/ HMMA.884.F32.F32.STEP1 R10, R26.reuse, R22.reuse.T, R10; /* 0x000000161a0a7236 */ + /* 0x0c4264000000d40a */ + /*0500*/ HMMA.884.F32.F32.STEP2 R4, R26.reuse, R22.reuse.T, R4; /* 0x000000161a047236 */ + /* 0x0c84a40000015404 */ + /*0510*/ HMMA.884.F32.F32.STEP3 R6, R26, R22.T, R6; /* 0x000000161a067236 */ + /* 0x0106e8000001d406 */ + /*0520*/ HMMA.884.F32.F32.STEP0 R8, R16.reuse, R12.reuse.T, R8; /* 0x0000000c10087236 */ + /* 0x0c10240000005408 */ + /*0530*/ HMMA.884.F32.F32.STEP1 R10, R16.reuse, R12.reuse.T, R10; /* 0x0000000c100a7236 */ + /* 0x0c2264000000d40a */ + /*0540*/ HMMA.884.F32.F32.STEP2 R4, R16.reuse, R12.reuse.T, R4; /* 0x0000000c10047236 */ + /* 0x0c44a40000015404 */ + /*0550*/ HMMA.884.F32.F32.STEP3 R6, R16, R12.T, R6; /* 0x0000000c10067236 */ + /* 0x0086e8000001d406 */ + /*0560*/ HMMA.884.F32.F32.STEP0 R8, R18.reuse, R14.reuse.T, R8; /* 0x0000000e12087236 */ + /* 0x0c10240000005408 */ + /*0570*/ HMMA.884.F32.F32.STEP1 R10, R18.reuse, R14.reuse.T, R10; /* 0x0000000e120a7236 */ + /* 0x0c2024000000d40a */ + /*0580*/ HMMA.884.F32.F32.STEP2 R4, R18.reuse, R14.reuse.T, R4; /* 0x0000000e12047236 */ + /* 0x0c40240000015404 */ + /*0590*/ HMMA.884.F32.F32.STEP3 R6, R18, R14.T, R6; /* 0x0000000e12067236 */ + /* 0x008034000001d406 */ + /*05a0*/ BSYNC B0; /* 0x0000000000007941 */ + /* 0x001fea0003800000 */ + /*05b0*/ S2R R12, SR_LANEID; /* 0x00000000000c7919 */ + /* 0x000e220000000000 */ + /*05c0*/ IMAD R28, R28, c[0x0][0x178], RZ; /* 0x00005e001c1c7a24 */ + /* 0x000fe200078e02ff */ + /*05d0*/ SHF.R.U32.HI R14, RZ, 0x4, R12; /* 0x00000004ff0e7819 */ + /* 0x001fc4000001160c */ + /*05e0*/ SHF.R.U32.HI R13, RZ, 0x2, R12; /* 0x00000002ff0d7819 */ + /* 0x000fe4000001160c */ + /*05f0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT; /* 0x000000030c0c7812 */ + /* 0x000fe400078ec0ff */ + /*0600*/ LOP3.LUT R14, R14, 0x1, RZ, 0xc0, !PT; /* 0x000000010e0e7812 */ + /* 0x000fe400078ec0ff */ + /*0610*/ LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT; /* 0x000000030d0d7812 */ + /* 0x000fc600078ec0ff */ + /*0620*/ IMAD R12, R14, 0x4, R12; /* 0x000000040e0c7824 */ + /* 0x000fe200078e020c */ + /*0630*/ LOP3.LUT R15, R13, 0x1, RZ, 0xc0, !PT; /* 0x000000010d0f7812 */ + /* 0x000fe400078ec0ff */ + /*0640*/ SHF.R.U32.HI R16, RZ, 0x1, R13; /* 0x00000001ff107819 */ + /* 0x000fe4000001160d */ + /*0650*/ LOP3.LUT R13, R12.reuse, 0x5, RZ, 0xc0, !PT; /* 0x000000050c0d7812 */ + /* 0x040fe400078ec0ff */ + /*0660*/ LOP3.LUT R14, R12, 0x2, RZ, 0xc0, !PT; /* 0x000000020c0e7812 */ + /* 0x000fc600078ec0ff */ + /*0670*/ IMAD R12, R15, 0x8, R13; /* 0x000000080f0c7824 */ + /* 0x000fe200078e020d */ + /*0680*/ SHF.R.S32.HI R15, RZ, 0x1f, R29; /* 0x0000001fff0f7819 */ + /* 0x000fe2000001141d */ + /*0690*/ IMAD R14, R16, 0x8, R14; /* 0x00000008100e7824 */ + /* 0x000fe200078e020e */ + /*06a0*/ IADD3 R17, P0, R29, R28, RZ; /* 0x0000001c1d117210 */ + /* 0x000fe20007f1e0ff */ + /*06b0*/ IMAD.U32 R13, RZ, RZ, RZ; /* 0x000000ffff0d7224 */ + /* 0x000fc600078e00ff */ + /*06c0*/ LEA.HI.X.SX32 R15, R28, R15, 0x1, P0; /* 0x0000000f1c0f7211 */ + /* 0x000fe200000f0eff */ + /*06d0*/ IMAD.WIDE.U32 R12, R14, c[0x0][0x178], R12; /* 0x00005e000e0c7a25 */ + /* 0x000fe200078e000c */ + /*06e0*/ LEA R14, P0, R17, c[0x0][0x170], 0x2; /* 0x00005c00110e7a11 */ + /* 0x000fe200078010ff */ + /*06f0*/ IMAD.U32 R18, RZ, RZ, c[0x0][0x178]; /* 0x00005e00ff127624 */ + /* 0x000fc600078e00ff */ + /*0700*/ LEA.HI.X R17, R17, c[0x0][0x174], R15, 0x2, P0; /* 0x00005d0011117a11 */ + /* 0x000fe400000f140f */ + /*0710*/ LEA R16, P0, R12, R14, 0x2; /* 0x0000000e0c107211 */ + /* 0x000fe400078010ff */ + /*0720*/ SHF.L.U32 R14, R18, 0x2, RZ; /* 0x00000002120e7819 */ + /* 0x000fe400000006ff */ + /*0730*/ SHF.R.U32.HI R15, RZ, 0x1e, R18; /* 0x0000001eff0f7819 */ + /* 0x000fe40000011612 */ + /*0740*/ LEA.HI.X R13, R12, R17, R13, 0x2, P0; /* 0x000000110c0d7211 */ + /* 0x000fe400000f140d */ + /*0750*/ LEA R18, P1, R14, R16, 0x2; /* 0x000000100e127211 */ + /* 0x000fc400078210ff */ + /*0760*/ IADD3 R17, P0, R14.reuse, R16, RZ; /* 0x000000100e117210 */ + /* 0x040fe40007f1e0ff */ + /*0770*/ LEA.HI.X R19, R14.reuse, R13, R15, 0x2, P1; /* 0x0000000d0e137211 */ + /* 0x040fe400008f140f */ + /*0780*/ IADD3 R21, P1, R14, R18, RZ; /* 0x000000120e157210 */ + /* 0x000fe20007f3e0ff */ + /*0790*/ IMAD.X R20, R15.reuse, 0x1, R13, P0; /* 0x000000010f147824 */ + /* 0x040fe400000e060d */ + /*07a0*/ IMAD.U32 R12, RZ, RZ, R16; /* 0x000000ffff0c7224 */ + /* 0x000fe400078e0010 */ + /*07b0*/ IMAD.X R22, R15, 0x1, R19, P1; /* 0x000000010f167824 */ + /* 0x000fe400008e0613 */ + /*07c0*/ IMAD.U32 R14, RZ, RZ, R17; /* 0x000000ffff0e7224 */ + /* 0x000fc400078e0011 */ + /*07d0*/ IMAD.U32 R15, RZ, RZ, R20; /* 0x000000ffff0f7224 */ + /* 0x000fe200078e0014 */ + /*07e0*/ MOV R16, R21; /* 0x0000001500107202 */ + /* 0x000fe20000000f00 */ + /*07f0*/ IMAD.U32 R17, RZ, RZ, R22; /* 0x000000ffff117224 */ + /* 0x000fe200078e0016 */ + /*0800*/ ST.E.SYS [R12], R8; /* 0x000000000c007385 */ + /* 0x0001e2000010e908 */ + /*0810*/ ST.E.SYS [R12+0x8], R10; /* 0x000000080c007385 */ + /* 0x0003e8000010e90a */ + /*0820*/ ST.E.SYS [R14], R9; /* 0x000000000e007385 */ + /* 0x0003e2000010e909 */ + /*0830*/ ST.E.SYS [R14+0x8], R11; /* 0x000000080e007385 */ + /* 0x0003e2000010e90b */ + /*0840*/ ST.E.SYS [R18], R4; /* 0x0000000012007385 */ + /* 0x0003e2000010e904 */ + /*0850*/ ST.E.SYS [R18+0x8], R6; /* 0x0000000812007385 */ + /* 0x0003e2000010e906 */ + /*0860*/ ST.E.SYS [R16], R5; /* 0x0000000010007385 */ + /* 0x0003e2000010e905 */ + /*0870*/ ST.E.SYS [R16+0x8], R7; /* 0x0000000810007385 */ + /* 0x0003e2000010e907 */ + /*0880*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*0890*/ IADD3 R8, R2, -c[0x0][0x20], RZ; /* 0x8000080002087a10 */ + /* 0x001fd00007ffe0ff */ + /*08a0*/ CS2R.32 R4, SR_CLOCKLO; /* 0x0000000000047805 */ + /* 0x002fd00000005000 */ + /*08b0*/ IMAD R3, R4, 0x1, -R3; /* 0x0000000104037824 */ + /* 0x000fd000078e0a03 */ + /*08c0*/ STL [R8], R3; /* 0x0000000308007387 */ + /* 0x0001e20000100800 */ + /*08d0*/ IMAD.U32 R6, RZ, RZ, R2; /* 0x000000ffff067224 */ + /* 0x000fe200078e0002 */ + /*08e0*/ MOV R4, 0x0; /* 0x0000000000047802 */ + /* 0x000fe20000000f00 */ + /*08f0*/ IMAD.U32 R7, RZ, RZ, R0; /* 0x000000ffff077224 */ + /* 0x000fe200078e0000 */ + /*0900*/ MOV R5, 0x0; /* 0x0000000000057802 */ + /* 0x000fe40000000f00 */ + /*0910*/ MOV R20, 0x0; /* 0x0000000000147802 */ + /* 0x000fe40000000f00 */ + /*0920*/ MOV R21, 0x0; /* 0x0000000000157802 */ + /* 0x000fd00000000f00 */ + /*0930*/ CALL.ABS.NOINC 0x0; /* 0x0000000000007943 */ + /* 0x001fea0003c00000 */ + /*0940*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*0950*/ BRA 0x950; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + /*0960*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + /*0970*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + ............................................. + + + +Fatbin ptx code: +================ +arch = sm_70 +code version = [6,0] +producer = cuda +host = linux +compile_size = 64bit +compressed + + + + + + + + +.version 6.0 +.target sm_70 +.address_size 64 + + +.extern .func (.param .b32 func_retval0) vprintf +( +.param .b64 vprintf_param_0, +.param .b64 vprintf_param_1 +) +; +.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0}; + +.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff( +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7 +) +{ +.local .align 8 .b8 __local_depot0[8]; +.reg .b64 %SP; +.reg .b64 %SPL; +.reg .pred %p<6>; +.reg .f32 %f<34>; +.reg .b32 %r<38>; +.reg .b64 %rd<18>; + + +mov.u64 %rd17, __local_depot0; +cvta.local.u64 %SP, %rd17; +ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0]; +ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1]; +ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2]; +ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3]; +ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4]; +ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5]; + + mov.u32 %r6, %clock; + + mov.u32 %r8, %ntid.x; +mov.u32 %r9, %ctaid.x; +mov.u32 %r10, %tid.x; +mad.lo.s32 %r11, %r8, %r9, %r10; +mov.u32 %r12, WARP_SZ; +div.u32 %r13, %r11, %r12; +mov.u32 %r14, %ntid.y; +mov.u32 %r15, %ctaid.y; +mov.u32 %r16, %tid.y; +mad.lo.s32 %r17, %r14, %r15, %r16; +shl.b32 %r2, %r13, 4; +shl.b32 %r3, %r17, 4; +setp.lt.s32 %p1, %r2, %r4; +setp.gt.s32 %p2, %r5, 0; +and.pred %p3, %p1, %p2; +setp.lt.s32 %p4, %r3, %r7; +and.pred %p5, %p3, %p4; +mov.f32 %f26, 0f00000000; +mov.f32 %f27, %f26; +mov.f32 %f28, %f26; +mov.f32 %f29, %f26; +mov.f32 %f30, %f26; +mov.f32 %f31, %f26; +mov.f32 %f32, %f26; +mov.f32 %f33, %f26; +@!%p5 bra BB0_2; +bra.uni BB0_1; + +BB0_1: +mul.wide.s32 %rd4, %r2, 2; +add.s64 %rd5, %rd1, %rd4; +wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4; +mul.wide.s32 %rd6, %r3, 2; +add.s64 %rd7, %rd2, %rd6; +wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5; +mov.f32 %f25, 0f00000000; +wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25}; + +BB0_2: +add.u64 %rd8, %SP, 0; +cvta.to.local.u64 %rd9, %rd8; +mul.lo.s32 %r35, %r3, %r4; +cvt.s64.s32 %rd10, %r35; +cvt.s64.s32 %rd11, %r2; +add.s64 %rd12, %rd10, %rd11; +shl.b64 %rd13, %rd12, 2; +add.s64 %rd14, %rd3, %rd13; +wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4; + + mov.u32 %r34, %clock; + + sub.s32 %r36, %r34, %r6; +st.local.u32 [%rd9], %r36; +mov.u64 %rd15, $str; +cvta.global.u64 %rd16, %rd15; + + { +.reg .b32 temp_param_reg; + + .param .b64 param0; +st.param.b64 [param0+0], %rd16; +.param .b64 param1; +st.param.b64 [param1+0], %rd8; +.param .b32 retval0; +call.uni (retval0), +vprintf, +( +param0, +param1 +); +ld.param.b32 %r37, [retval0+0]; + + + } + ret; +} + + +.visible .entry _Z17convertFp32ToFp16P6__halfPfi( +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0, +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1, +.param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2 +) +{ +.reg .pred %p<2>; +.reg .b16 %rs<2>; +.reg .f32 %f<2>; +.reg .b32 %r<6>; +.reg .b64 %rd<9>; + + +ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0]; +ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1]; +ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2]; +mov.u32 %r3, %ntid.x; +mov.u32 %r4, %ctaid.x; +mov.u32 %r5, %tid.x; +mad.lo.s32 %r1, %r4, %r3, %r5; +setp.ge.s32 %p1, %r1, %r2; +@%p1 bra BB1_2; + +cvta.to.global.u64 %rd3, %rd2; +mul.wide.s32 %rd4, %r1, 4; +add.s64 %rd5, %rd3, %rd4; +ld.global.f32 %f1, [%rd5]; + + { cvt.rn.f16.f32 %rs1, %f1;} + + + cvta.to.global.u64 %rd6, %rd1; +mul.wide.s32 %rd7, %r1, 2; +add.s64 %rd8, %rd6, %rd7; +st.global.u16 [%rd8], %rs1; + +BB1_2: +ret; +} + + diff --git a/cuda-kernels/_cuobjdump_complete_output_rndQyq b/cuda-kernels/_cuobjdump_complete_output_rndQyq new file mode 100644 index 0000000..36999c0 --- /dev/null +++ b/cuda-kernels/_cuobjdump_complete_output_rndQyq @@ -0,0 +1,1055 @@ + +Fatbin elf code: +================ +arch = sm_70 +code version = [1,7] +producer = +host = linux +compile_size = 64bit + +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 32 0 1 STRTAB 0 0 0 .shstrtab + 2 72 32 0 1 STRTAB 0 0 0 .strtab + 3 a8 18 18 8 SYMTAB 0 2 0 .symtab + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + + code for sm_70 + +Fatbin elf code: +================ +arch = sm_70 +code version = [1,7] +producer = cuda +host = linux +compile_size = 64bit + +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 21b 0 1 STRTAB 0 0 0 .shstrtab + 2 25b 273 0 1 STRTAB 0 0 0 .strtab + 3 4d0 108 18 8 SYMTAB 0 2 7 .symtab + 4 5d8 e0 0 1 PROGBITS 0 0 0 .debug_frame + 5 6b8 48 0 4 CUDA_INFO 0 3 0 .nv.info + 6 700 50 0 4 CUDA_INFO 0 3 d .nv.info._Z17convertFp32ToFp16P6__halfPfi + 7 750 ac 0 4 CUDA_INFO 0 3 e .nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + 8 800 30 10 8 REL 0 3 e .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff + 9 830 30 18 8 RELA 0 3 e .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff + a 860 20 10 8 REL 0 3 4 .rel.debug_frame + b 880 174 0 4 PROGBITS 2 0 d .nv.constant0._Z17convertFp32ToFp16P6__halfPfi + c 9f4 18c 0 4 PROGBITS 2 0 e .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff + d b80 100 0 80 PROGBITS 6 3 9000008 .text._Z17convertFp32ToFp16P6__halfPfi + e c80 980 0 80 PROGBITS 6 3 20000009 .text._Z12wmma_exampleP6__halfS0_Pfiiiff + f 1600 9 0 10 PROGBITS 3 0 0 .nv.global.init + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + 1 0 0 3 0 d .text._Z17convertFp32ToFp16P6__halfPfi + 2 0 0 3 0 f .nv.global.init + 3 0 9 1 0 f $str + 4 0 0 3 0 b .nv.constant0._Z17convertFp32ToFp16P6__halfPfi + 5 0 0 3 0 e .text._Z12wmma_exampleP6__halfS0_Pfiiiff + 6 0 0 3 0 c .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff + 7 0 0 3 0 4 .debug_frame + 8 0 256 12 10 d _Z17convertFp32ToFp16P6__halfPfi + 9 0 2432 12 10 e _Z12wmma_exampleP6__halfS0_Pfiiiff + 10 0 0 12 0 0 vprintf + + +.nv.constant0._Z17convertFp32ToFp16P6__halfPfi +0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 + + + +.nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff +0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 + + +.nv.global.init +0x636f6c63 0x64253d6b 0 + + +.nv.info + <0x1> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x9 0x0 + <0x2> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) min stack size: 0x8 + <0x3> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) frame size: 0x8 + <0x4> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x8 0x0 + <0x5> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) min stack size: 0x0 + <0x6> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) frame size: 0x0 + + +.nv.info._Z17convertFp32ToFp16P6__halfPfi + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x4 0x140160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x14 + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x7> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x60 0xe0 + + +.nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x6 0x2c0160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x2c + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x7 Offset : 0x28 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x6 Offset : 0x24 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x5 Offset : 0x20 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x4 Offset : 0x1c Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x7> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x3 Offset : 0x18 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x8> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x9> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x10> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x11> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x12> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x940 + <0x13> + Attribute: EIATTR_EXTERNS + Format: EIFMT_SVAL + Value: externs: vprintf(0xa) + <0x14> + Attribute: EIATTR_CRS_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x0 + + +.text._Z17convertFp32ToFp16P6__halfPfi +bar = 0 reg = 9 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0x00017a02 0x00000a00 0x00000f00 0x000fd000 +0x00047919 0x00000000 0x00002500 0x000e2200 +0x00027919 0x00000000 0x00002100 0x000e2400 +0x04047a24 0x00000000 0x078e0202 0x001fca00 +0x04007a0c 0x00005c00 0x03f062f0 0x000fd800 +0x0000094d 0x00000000 0x03800000 0x000fea00 +0x00027802 0x00000004 0x00000f00 0x000fca00 +0x04027625 0x00005a00 0x078e0202 0x000fd400 +0x02027381 0x00000000 0x001ee900 0x000e2200 +0x00057802 0x00000002 0x00000f00 0x000fca00 +0x04047625 0x00005800 0x078e0205 0x000fe200 +0x00067304 0x00000002 0x00200800 0x001e3200 +0x04007386 0x00000006 0x0010e500 0x0011e200 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 + + + +.text._Z12wmma_exampleP6__halfS0_Pfiiiff +bar = 0 reg = 32 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0xff017624 0x00000a00 0x078e00ff 0x000fd000 +0x01017810 0xfffffff8 0x07ffe0ff 0x000fc800 +0x01027a10 0x00000800 0x07f1e0ff 0x000fca00 +0xff007624 0x00000900 0x000e06ff 0x000fd000 +0x00037805 0x00000000 0x00005000 0x000fd000 +0x00077906 0x00000020 0x00209000 0x000e2400 +0x00077308 0x00000007 0x00001000 0x001e2200 +0x00067919 0x00000000 0x00002500 0x000e6200 +0x00097919 0x00000000 0x00002100 0x000e6200 +0x07087810 0x0ffffffe 0x07ffe0ff 0x001fcc00 +0x00057305 0x00000008 0x0021f000 0x0000a200 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0x06067a24 0x00000000 0x078e0209 0x002fe400 +0x050a7824 0xffffffe0 0x078e00ff 0x004fc800 +0x05047225 0x0000000a 0x078e0004 0x000fd000 +0x05047225 0x00000006 0x078e00ff 0x000fcc00 +0xff047224 0x000000ff 0x078e0a05 0x000fc800 +0x04067824 0x00000020 0x078e0206 0x000fca00 +0x0600780c 0x00000020 0x03f060f0 0x040fe200 +0x001c7919 0x00000000 0x00002600 0x000e2200 +0x00077919 0x00000000 0x00002200 0x000e3400 +0x06060810 0xffffffe0 0x07ffe0ff 0x000fc800 +0x0600780c 0x00000020 0x03f260f0 0x000fe400 +0x05050810 0x00000001 0x07ffe0ff 0x000fe400 +0xff007a0c 0x00006000 0x03f012f0 0x000fd000 +0x05051810 0x00000001 0x07ffe0ff 0x000fe200 +0x1c1c7a24 0x00000100 0x078e0207 0x001fc600 +0x051d7819 0x00000004 0x000006ff 0x000fe200 +0x1c1c7824 0x00000010 0x078e00ff 0x000fc600 +0x1d007a0c 0x00005e00 0x007012f0 0x000fc800 +0x1c007a0c 0x00005f00 0x007012f0 0x000fe200 +0x00007945 0x000003a0 0x03800000 0x000fe200 +0xff077224 0x000000ff 0x078e00ff 0x000fe200 +0x000b7202 0x000000ff 0x00000f00 0x000fe200 +0xff067224 0x000000ff 0x078e00ff 0x000fe400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0xff0a7224 0x000000ff 0x078e00ff 0x000fc400 +0xff097224 0x000000ff 0x078e00ff 0x000fe400 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00008947 0x00000300 0x03800000 0x000fee00 +0x00067919 0x00000000 0x00000000 0x000e2200 +0xff0a7424 0x00000002 0x078e00ff 0x000fc800 +0x1d107625 0x00005800 0x078e020a 0x000fe200 +0xff047819 0x00000002 0x00011606 0x001fc800 +0x04057812 0x00000003 0x078ec0ff 0x000fe400 +0x06047812 0x00000003 0x078ec0ff 0x000fe400 +0x05077812 0x00000001 0x078ec0ff 0x000fe400 +0xff067819 0x00000004 0x00011606 0x000fe400 +0xff057819 0x00000001 0x00011605 0x000fe200 +0x07077824 0x00000008 0x078e0204 0x000fe200 +0x06067812 0x00000001 0x078ec0ff 0x000fc400 +0x05047211 0x00000004 0x078e18ff 0x000fe200 +0x1c0c7625 0x00005a00 0x078e020a 0x000fe400 +0x06077824 0x00000004 0x078e0207 0x040fe400 +0x06047824 0x00000004 0x078e0204 0x000fe400 +0x07077824 0x00000002 0x078e00ff 0x000fe400 +0x04057824 0x00000002 0x078e00ff 0x000fe400 +0x07107a25 0x00005e00 0x078e0010 0x000fc400 +0x050c7a25 0x00006000 0x078e000c 0x000fd000 +0x10187980 0x00000000 0x0010ed00 0x00006400 +0x0c147980 0x00000000 0x0010ed00 0x00046200 +0x10107980 0x00000010 0x0010ed00 0x001e2200 +0x0c0c7980 0x00000010 0x0010ed00 0x004e2200 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00097202 0x000000ff 0x00000f00 0x000fe200 +0xff0a7224 0x000000ff 0x078e00ff 0x000fe400 +0xff0b7224 0x000000ff 0x078e00ff 0x000fe200 +0x00077202 0x000000ff 0x00000f00 0x000fe200 +0xff047224 0x000000ff 0x078e00ff 0x000fc400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff067224 0x000000ff 0x078e00ff 0x000fe200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x18087236 0x00000014 0x00005408 0x0c226400 +0x180a7236 0x00000014 0x0000d40a 0x0c04a400 +0x18047236 0x00000014 0x00015404 0x0c06e400 +0x18067236 0x00000014 0x0001d406 0x00092800 +0x1a087236 0x00000016 0x00005408 0x0c202400 +0x1a0a7236 0x00000016 0x0000d40a 0x0c426400 +0x1a047236 0x00000016 0x00015404 0x0c84a400 +0x1a067236 0x00000016 0x0001d406 0x0106e800 +0x10087236 0x0000000c 0x00005408 0x0c102400 +0x100a7236 0x0000000c 0x0000d40a 0x0c226400 +0x10047236 0x0000000c 0x00015404 0x0c44a400 +0x10067236 0x0000000c 0x0001d406 0x0086e800 +0x12087236 0x0000000e 0x00005408 0x0c102400 +0x120a7236 0x0000000e 0x0000d40a 0x0c202400 +0x12047236 0x0000000e 0x00015404 0x0c402400 +0x12067236 0x0000000e 0x0001d406 0x00803400 +0x00007941 0x00000000 0x03800000 0x001fea00 +0x000c7919 0x00000000 0x00000000 0x000e2200 +0x1c1c7a24 0x00005e00 0x078e02ff 0x000fe200 +0xff0e7819 0x00000004 0x0001160c 0x001fc400 +0xff0d7819 0x00000002 0x0001160c 0x000fe400 +0x0c0c7812 0x00000003 0x078ec0ff 0x000fe400 +0x0e0e7812 0x00000001 0x078ec0ff 0x000fe400 +0x0d0d7812 0x00000003 0x078ec0ff 0x000fc600 +0x0e0c7824 0x00000004 0x078e020c 0x000fe200 +0x0d0f7812 0x00000001 0x078ec0ff 0x000fe400 +0xff107819 0x00000001 0x0001160d 0x000fe400 +0x0c0d7812 0x00000005 0x078ec0ff 0x040fe400 +0x0c0e7812 0x00000002 0x078ec0ff 0x000fc600 +0x0f0c7824 0x00000008 0x078e020d 0x000fe200 +0xff0f7819 0x0000001f 0x0001141d 0x000fe200 +0x100e7824 0x00000008 0x078e020e 0x000fe200 +0x1d117210 0x0000001c 0x07f1e0ff 0x000fe200 +0xff0d7224 0x000000ff 0x078e00ff 0x000fc600 +0x1c0f7211 0x0000000f 0x000f0eff 0x000fe200 +0x0e0c7a25 0x00005e00 0x078e000c 0x000fe200 +0x110e7a11 0x00005c00 0x078010ff 0x000fe200 +0xff127624 0x00005e00 0x078e00ff 0x000fc600 +0x11117a11 0x00005d00 0x000f140f 0x000fe400 +0x0c107211 0x0000000e 0x078010ff 0x000fe400 +0x120e7819 0x00000002 0x000006ff 0x000fe400 +0xff0f7819 0x0000001e 0x00011612 0x000fe400 +0x0c0d7211 0x00000011 0x000f140d 0x000fe400 +0x0e127211 0x00000010 0x078210ff 0x000fc400 +0x0e117210 0x00000010 0x07f1e0ff 0x040fe400 +0x0e137211 0x0000000d 0x008f140f 0x040fe400 +0x0e157210 0x00000012 0x07f3e0ff 0x000fe200 +0x0f147824 0x00000001 0x000e060d 0x040fe400 +0xff0c7224 0x000000ff 0x078e0010 0x000fe400 +0x0f167824 0x00000001 0x008e0613 0x000fe400 +0xff0e7224 0x000000ff 0x078e0011 0x000fc400 +0xff0f7224 0x000000ff 0x078e0014 0x000fe200 +0x00107202 0x00000015 0x00000f00 0x000fe200 +0xff117224 0x000000ff 0x078e0016 0x000fe200 +0x0c007385 0x00000000 0x0010e908 0x0001e200 +0x0c007385 0x00000008 0x0010e90a 0x0003e800 +0x0e007385 0x00000000 0x0010e909 0x0003e200 +0x0e007385 0x00000008 0x0010e90b 0x0003e200 +0x12007385 0x00000000 0x0010e904 0x0003e200 +0x12007385 0x00000008 0x0010e906 0x0003e200 +0x10007385 0x00000000 0x0010e905 0x0003e200 +0x10007385 0x00000008 0x0010e907 0x0003e200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x02087a10 0x80000800 0x07ffe0ff 0x001fd000 +0x00047805 0x00000000 0x00005000 0x002fd000 +0x04037824 0x00000001 0x078e0a03 0x000fd000 +0x08007387 0x00000003 0x00100800 0x0001e200 +0xff067224 0x000000ff 0x078e0002 0x000fe200 +0x00047802 0x00000000 0x00000f00 0x000fe200 +0xff077224 0x000000ff 0x078e0000 0x000fe200 +0x00057802 0x00000000 0x00000f00 0x000fe400 +0x00147802 0x00000000 0x00000f00 0x000fe400 +0x00157802 0x00000000 0x00000f00 0x000fd000 +0x00007943 0x00000000 0x03c00000 0x001fea00 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 + + +.section .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff REL +2272 $str R_CUDA_ABS32_LO_32 +2304 $str R_CUDA_ABS32_HI_32 +2352 vprintf R_CUDA_ABS47_34 + +.section .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff RELA +2320 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_LO_32 2368 +2336 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_HI_32 2368 + +.section .debug_frame +decodeDebugFrame, frameBuf 0xffffffff, total_length 224 +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x100 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 0 + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_advance_loc4 delta 52 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x970 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 2 + DW_CFA_def_cfa register R1, offset 8 + DW_CFA_advance_loc4 delta 586 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +.section .rel.debug_frame REL +72 _Z17convertFp32ToFp16P6__halfPfi R_NV_64 +184 _Z12wmma_exampleP6__halfS0_Pfiiiff R_NV_64 + + code for sm_70 + Function : _Z17convertFp32ToFp16P6__halfPfi + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ MOV R1, c[0x0][0x28]; /* 0x00000a0000017a02 */ + /* 0x000fd00000000f00 */ + /*0020*/ S2R R4, SR_CTAID.X; /* 0x0000000000047919 */ + /* 0x000e220000002500 */ + /*0030*/ S2R R2, SR_TID.X; /* 0x0000000000027919 */ + /* 0x000e240000002100 */ + /*0040*/ IMAD R4, R4, c[0x0][0x0], R2; /* 0x0000000004047a24 */ + /* 0x001fca00078e0202 */ + /*0050*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT, !PT; /* 0x00005c0004007a0c */ + /* 0x000fd80003f062f0 */ + /*0060*/ @P0 EXIT; /* 0x000000000000094d */ + /* 0x000fea0003800000 */ + /*0070*/ MOV R2, 0x4; /* 0x0000000400027802 */ + /* 0x000fca0000000f00 */ + /*0080*/ IMAD.WIDE R2, R4, R2, c[0x0][0x168]; /* 0x00005a0004027625 */ + /* 0x000fd400078e0202 */ + /*0090*/ LDG.E.SYS R2, [R2]; /* 0x0000000002027381 */ + /* 0x000e2200001ee900 */ + /*00a0*/ MOV R5, 0x2; /* 0x0000000200057802 */ + /* 0x000fca0000000f00 */ + /*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160]; /* 0x0000580004047625 */ + /* 0x000fe200078e0205 */ + /*00c0*/ F2F.F16.F32 R6, R2; /* 0x0000000200067304 */ + /* 0x001e320000200800 */ + /*00d0*/ STG.E.U16.SYS [R4], R6; /* 0x0000000604007386 */ + /* 0x0011e2000010e500 */ + /*00e0*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + ........................................... + + + Function : _Z12wmma_exampleP6__halfS0_Pfiiiff + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ IMAD.U32 R1, RZ, RZ, c[0x0][0x28]; /* 0x00000a00ff017624 */ + /* 0x000fd000078e00ff */ + /*0020*/ IADD3 R1, R1, -0x8, RZ; /* 0xfffffff801017810 */ + /* 0x000fc80007ffe0ff */ + /*0030*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ; /* 0x0000080001027a10 */ + /* 0x000fca0007f1e0ff */ + /*0040*/ IMAD.X R0, RZ, RZ, c[0x0][0x24], P0; /* 0x00000900ff007624 */ + /* 0x000fd000000e06ff */ + /*0050*/ CS2R.32 R3, SR_CLOCKLO; /* 0x0000000000037805 */ + /* 0x000fd00000005000 */ + /*0060*/ I2F.U32.RP R7, 0x20; /* 0x0000002000077906 */ + /* 0x000e240000209000 */ + /*0070*/ MUFU.RCP R7, R7; /* 0x0000000700077308 */ + /* 0x001e220000001000 */ + /*0080*/ S2R R6, SR_CTAID.X; /* 0x0000000000067919 */ + /* 0x000e620000002500 */ + /*0090*/ S2R R9, SR_TID.X; /* 0x0000000000097919 */ + /* 0x000e620000002100 */ + /*00a0*/ IADD3 R8, R7, 0xffffffe, RZ; /* 0x0ffffffe07087810 */ + /* 0x001fcc0007ffe0ff */ + /*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R8; /* 0x0000000800057305 */ + /* 0x0000a2000021f000 */ + /*00c0*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*00d0*/ IMAD R6, R6, c[0x0][0x0], R9; /* 0x0000000006067a24 */ + /* 0x002fe400078e0209 */ + /*00e0*/ IMAD.U32 R10, R5, -0x20, RZ; /* 0xffffffe0050a7824 */ + /* 0x004fc800078e00ff */ + /*00f0*/ IMAD.WIDE.U32 R4, R5, R10, R4; /* 0x0000000a05047225 */ + /* 0x000fd000078e0004 */ + /*0100*/ IMAD.WIDE.U32 R4, R5, R6, RZ; /* 0x0000000605047225 */ + /* 0x000fcc00078e00ff */ + /*0110*/ IMAD R4, RZ, RZ, -R5; /* 0x000000ffff047224 */ + /* 0x000fc800078e0a05 */ + /*0120*/ IMAD R6, R4, 0x20, R6; /* 0x0000002004067824 */ + /* 0x000fca00078e0206 */ + /*0130*/ ISETP.GE.U32.AND P0, PT, R6.reuse, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x040fe20003f060f0 */ + /*0140*/ S2R R28, SR_CTAID.Y; /* 0x00000000001c7919 */ + /* 0x000e220000002600 */ + /*0150*/ S2R R7, SR_TID.Y; /* 0x0000000000077919 */ + /* 0x000e340000002200 */ + /*0160*/ @P0 IADD3 R6, R6, -0x20, RZ; /* 0xffffffe006060810 */ + /* 0x000fc80007ffe0ff */ + /*0170*/ ISETP.GE.U32.AND P1, PT, R6, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x000fe40003f260f0 */ + /*0180*/ @P0 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105050810 */ + /* 0x000fe40007ffe0ff */ + /*0190*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT, !PT; /* 0x00006000ff007a0c */ + /* 0x000fd00003f012f0 */ + /*01a0*/ @P1 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105051810 */ + /* 0x000fe20007ffe0ff */ + /*01b0*/ IMAD R28, R28, c[0x0][0x4], R7; /* 0x000001001c1c7a24 */ + /* 0x001fc600078e0207 */ + /*01c0*/ SHF.L.U32 R29, R5, 0x4, RZ; /* 0x00000004051d7819 */ + /* 0x000fe200000006ff */ + /*01d0*/ IMAD.U32 R28, R28, 0x10, RZ; /* 0x000000101c1c7824 */ + /* 0x000fc600078e00ff */ + /*01e0*/ ISETP.LT.AND P0, PT, R29, c[0x0][0x178], P0, !PT; /* 0x00005e001d007a0c */ + /* 0x000fc800007012f0 */ + /*01f0*/ ISETP.LT.AND P0, PT, R28, c[0x0][0x17c], P0, !PT; /* 0x00005f001c007a0c */ + /* 0x000fe200007012f0 */ + /*0200*/ BSSY B0, 0x5b0; /* 0x000003a000007945 */ + /* 0x000fe20003800000 */ + /*0210*/ IMAD.U32 R7, RZ, RZ, RZ; /* 0x000000ffff077224 */ + /* 0x000fe200078e00ff */ + /*0220*/ MOV R11, RZ; /* 0x000000ff000b7202 */ + /* 0x000fe20000000f00 */ + /*0230*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe400078e00ff */ + /*0240*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0250*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*0260*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fc400078e00ff */ + /*0270*/ IMAD.U32 R9, RZ, RZ, RZ; /* 0x000000ffff097224 */ + /* 0x000fe400078e00ff */ + /*0280*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0290*/ @!P0 BRA 0x5a0; /* 0x0000030000008947 */ + /* 0x000fee0003800000 */ + /*02a0*/ S2R R6, SR_LANEID; /* 0x0000000000067919 */ + /* 0x000e220000000000 */ + /*02b0*/ IMAD.U32 R10, RZ, RZ, 0x2; /* 0x00000002ff0a7424 */ + /* 0x000fc800078e00ff */ + /*02c0*/ IMAD.WIDE R16, R29, R10, c[0x0][0x160]; /* 0x000058001d107625 */ + /* 0x000fe200078e020a */ + /*02d0*/ SHF.R.U32.HI R4, RZ, 0x2, R6; /* 0x00000002ff047819 */ + /* 0x001fc80000011606 */ + /*02e0*/ LOP3.LUT R5, R4, 0x3, RZ, 0xc0, !PT; /* 0x0000000304057812 */ + /* 0x000fe400078ec0ff */ + /*02f0*/ LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT; /* 0x0000000306047812 */ + /* 0x000fe400078ec0ff */ + /*0300*/ LOP3.LUT R7, R5, 0x1, RZ, 0xc0, !PT; /* 0x0000000105077812 */ + /* 0x000fe400078ec0ff */ + /*0310*/ SHF.R.U32.HI R6, RZ, 0x4, R6; /* 0x00000004ff067819 */ + /* 0x000fe40000011606 */ + /*0320*/ SHF.R.U32.HI R5, RZ, 0x1, R5; /* 0x00000001ff057819 */ + /* 0x000fe20000011605 */ + /*0330*/ IMAD R7, R7, 0x8, R4; /* 0x0000000807077824 */ + /* 0x000fe200078e0204 */ + /*0340*/ LOP3.LUT R6, R6, 0x1, RZ, 0xc0, !PT; /* 0x0000000106067812 */ + /* 0x000fc400078ec0ff */ + /*0350*/ LEA R4, R5, R4, 0x3; /* 0x0000000405047211 */ + /* 0x000fe200078e18ff */ + /*0360*/ IMAD.WIDE R12, R28, R10, c[0x0][0x168]; /* 0x00005a001c0c7625 */ + /* 0x000fe400078e020a */ + /*0370*/ IMAD R7, R6.reuse, 0x4, R7; /* 0x0000000406077824 */ + /* 0x040fe400078e0207 */ + /*0380*/ IMAD R4, R6, 0x4, R4; /* 0x0000000406047824 */ + /* 0x000fe400078e0204 */ + /*0390*/ IMAD.U32 R7, R7, 0x2, RZ; /* 0x0000000207077824 */ + /* 0x000fe400078e00ff */ + /*03a0*/ IMAD.U32 R5, R4, 0x2, RZ; /* 0x0000000204057824 */ + /* 0x000fe400078e00ff */ + /*03b0*/ IMAD.WIDE.U32 R16, R7, c[0x0][0x178], R16; /* 0x00005e0007107a25 */ + /* 0x000fc400078e0010 */ + /*03c0*/ IMAD.WIDE.U32 R12, R5, c[0x0][0x180], R12; /* 0x00006000050c7a25 */ + /* 0x000fd000078e000c */ + /*03d0*/ LD.E.128.SYS R24, [R16]; /* 0x0000000010187980 */ + /* 0x000064000010ed00 */ + /*03e0*/ LD.E.128.SYS R20, [R12]; /* 0x000000000c147980 */ + /* 0x000462000010ed00 */ + /*03f0*/ LD.E.128.SYS R16, [R16+0x10]; /* 0x0000001010107980 */ + /* 0x001e22000010ed00 */ + /*0400*/ LD.E.128.SYS R12, [R12+0x10]; /* 0x000000100c0c7980 */ + /* 0x004e22000010ed00 */ + /*0410*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0420*/ MOV R9, RZ; /* 0x000000ff00097202 */ + /* 0x000fe20000000f00 */ + /*0430*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fe400078e00ff */ + /*0440*/ IMAD.U32 R11, RZ, RZ, RZ; /* 0x000000ffff0b7224 */ + /* 0x000fe200078e00ff */ + /*0450*/ MOV R7, RZ; /* 0x000000ff00077202 */ + /* 0x000fe20000000f00 */ + /*0460*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fc400078e00ff */ + /*0470*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0480*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe200078e00ff */ + /*0490*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*04a0*/ HMMA.884.F32.F32.STEP0 R8, R24.reuse, R20.reuse.T, R8; /* 0x0000001418087236 */ + /* 0x0c22640000005408 */ + /*04b0*/ HMMA.884.F32.F32.STEP1 R10, R24.reuse, R20.reuse.T, R10; /* 0x00000014180a7236 */ + /* 0x0c04a4000000d40a */ + /*04c0*/ HMMA.884.F32.F32.STEP2 R4, R24.reuse, R20.reuse.T, R4; /* 0x0000001418047236 */ + /* 0x0c06e40000015404 */ + /*04d0*/ HMMA.884.F32.F32.STEP3 R6, R24, R20.T, R6; /* 0x0000001418067236 */ + /* 0x000928000001d406 */ + /*04e0*/ HMMA.884.F32.F32.STEP0 R8, R26.reuse, R22.reuse.T, R8; /* 0x000000161a087236 */ + /* 0x0c20240000005408 */ + /*04f0*/ HMMA.884.F32.F32.STEP1 R10, R26.reuse, R22.reuse.T, R10; /* 0x000000161a0a7236 */ + /* 0x0c4264000000d40a */ + /*0500*/ HMMA.884.F32.F32.STEP2 R4, R26.reuse, R22.reuse.T, R4; /* 0x000000161a047236 */ + /* 0x0c84a40000015404 */ + /*0510*/ HMMA.884.F32.F32.STEP3 R6, R26, R22.T, R6; /* 0x000000161a067236 */ + /* 0x0106e8000001d406 */ + /*0520*/ HMMA.884.F32.F32.STEP0 R8, R16.reuse, R12.reuse.T, R8; /* 0x0000000c10087236 */ + /* 0x0c10240000005408 */ + /*0530*/ HMMA.884.F32.F32.STEP1 R10, R16.reuse, R12.reuse.T, R10; /* 0x0000000c100a7236 */ + /* 0x0c2264000000d40a */ + /*0540*/ HMMA.884.F32.F32.STEP2 R4, R16.reuse, R12.reuse.T, R4; /* 0x0000000c10047236 */ + /* 0x0c44a40000015404 */ + /*0550*/ HMMA.884.F32.F32.STEP3 R6, R16, R12.T, R6; /* 0x0000000c10067236 */ + /* 0x0086e8000001d406 */ + /*0560*/ HMMA.884.F32.F32.STEP0 R8, R18.reuse, R14.reuse.T, R8; /* 0x0000000e12087236 */ + /* 0x0c10240000005408 */ + /*0570*/ HMMA.884.F32.F32.STEP1 R10, R18.reuse, R14.reuse.T, R10; /* 0x0000000e120a7236 */ + /* 0x0c2024000000d40a */ + /*0580*/ HMMA.884.F32.F32.STEP2 R4, R18.reuse, R14.reuse.T, R4; /* 0x0000000e12047236 */ + /* 0x0c40240000015404 */ + /*0590*/ HMMA.884.F32.F32.STEP3 R6, R18, R14.T, R6; /* 0x0000000e12067236 */ + /* 0x008034000001d406 */ + /*05a0*/ BSYNC B0; /* 0x0000000000007941 */ + /* 0x001fea0003800000 */ + /*05b0*/ S2R R12, SR_LANEID; /* 0x00000000000c7919 */ + /* 0x000e220000000000 */ + /*05c0*/ IMAD R28, R28, c[0x0][0x178], RZ; /* 0x00005e001c1c7a24 */ + /* 0x000fe200078e02ff */ + /*05d0*/ SHF.R.U32.HI R14, RZ, 0x4, R12; /* 0x00000004ff0e7819 */ + /* 0x001fc4000001160c */ + /*05e0*/ SHF.R.U32.HI R13, RZ, 0x2, R12; /* 0x00000002ff0d7819 */ + /* 0x000fe4000001160c */ + /*05f0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT; /* 0x000000030c0c7812 */ + /* 0x000fe400078ec0ff */ + /*0600*/ LOP3.LUT R14, R14, 0x1, RZ, 0xc0, !PT; /* 0x000000010e0e7812 */ + /* 0x000fe400078ec0ff */ + /*0610*/ LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT; /* 0x000000030d0d7812 */ + /* 0x000fc600078ec0ff */ + /*0620*/ IMAD R12, R14, 0x4, R12; /* 0x000000040e0c7824 */ + /* 0x000fe200078e020c */ + /*0630*/ LOP3.LUT R15, R13, 0x1, RZ, 0xc0, !PT; /* 0x000000010d0f7812 */ + /* 0x000fe400078ec0ff */ + /*0640*/ SHF.R.U32.HI R16, RZ, 0x1, R13; /* 0x00000001ff107819 */ + /* 0x000fe4000001160d */ + /*0650*/ LOP3.LUT R13, R12.reuse, 0x5, RZ, 0xc0, !PT; /* 0x000000050c0d7812 */ + /* 0x040fe400078ec0ff */ + /*0660*/ LOP3.LUT R14, R12, 0x2, RZ, 0xc0, !PT; /* 0x000000020c0e7812 */ + /* 0x000fc600078ec0ff */ + /*0670*/ IMAD R12, R15, 0x8, R13; /* 0x000000080f0c7824 */ + /* 0x000fe200078e020d */ + /*0680*/ SHF.R.S32.HI R15, RZ, 0x1f, R29; /* 0x0000001fff0f7819 */ + /* 0x000fe2000001141d */ + /*0690*/ IMAD R14, R16, 0x8, R14; /* 0x00000008100e7824 */ + /* 0x000fe200078e020e */ + /*06a0*/ IADD3 R17, P0, R29, R28, RZ; /* 0x0000001c1d117210 */ + /* 0x000fe20007f1e0ff */ + /*06b0*/ IMAD.U32 R13, RZ, RZ, RZ; /* 0x000000ffff0d7224 */ + /* 0x000fc600078e00ff */ + /*06c0*/ LEA.HI.X.SX32 R15, R28, R15, 0x1, P0; /* 0x0000000f1c0f7211 */ + /* 0x000fe200000f0eff */ + /*06d0*/ IMAD.WIDE.U32 R12, R14, c[0x0][0x178], R12; /* 0x00005e000e0c7a25 */ + /* 0x000fe200078e000c */ + /*06e0*/ LEA R14, P0, R17, c[0x0][0x170], 0x2; /* 0x00005c00110e7a11 */ + /* 0x000fe200078010ff */ + /*06f0*/ IMAD.U32 R18, RZ, RZ, c[0x0][0x178]; /* 0x00005e00ff127624 */ + /* 0x000fc600078e00ff */ + /*0700*/ LEA.HI.X R17, R17, c[0x0][0x174], R15, 0x2, P0; /* 0x00005d0011117a11 */ + /* 0x000fe400000f140f */ + /*0710*/ LEA R16, P0, R12, R14, 0x2; /* 0x0000000e0c107211 */ + /* 0x000fe400078010ff */ + /*0720*/ SHF.L.U32 R14, R18, 0x2, RZ; /* 0x00000002120e7819 */ + /* 0x000fe400000006ff */ + /*0730*/ SHF.R.U32.HI R15, RZ, 0x1e, R18; /* 0x0000001eff0f7819 */ + /* 0x000fe40000011612 */ + /*0740*/ LEA.HI.X R13, R12, R17, R13, 0x2, P0; /* 0x000000110c0d7211 */ + /* 0x000fe400000f140d */ + /*0750*/ LEA R18, P1, R14, R16, 0x2; /* 0x000000100e127211 */ + /* 0x000fc400078210ff */ + /*0760*/ IADD3 R17, P0, R14.reuse, R16, RZ; /* 0x000000100e117210 */ + /* 0x040fe40007f1e0ff */ + /*0770*/ LEA.HI.X R19, R14.reuse, R13, R15, 0x2, P1; /* 0x0000000d0e137211 */ + /* 0x040fe400008f140f */ + /*0780*/ IADD3 R21, P1, R14, R18, RZ; /* 0x000000120e157210 */ + /* 0x000fe20007f3e0ff */ + /*0790*/ IMAD.X R20, R15.reuse, 0x1, R13, P0; /* 0x000000010f147824 */ + /* 0x040fe400000e060d */ + /*07a0*/ IMAD.U32 R12, RZ, RZ, R16; /* 0x000000ffff0c7224 */ + /* 0x000fe400078e0010 */ + /*07b0*/ IMAD.X R22, R15, 0x1, R19, P1; /* 0x000000010f167824 */ + /* 0x000fe400008e0613 */ + /*07c0*/ IMAD.U32 R14, RZ, RZ, R17; /* 0x000000ffff0e7224 */ + /* 0x000fc400078e0011 */ + /*07d0*/ IMAD.U32 R15, RZ, RZ, R20; /* 0x000000ffff0f7224 */ + /* 0x000fe200078e0014 */ + /*07e0*/ MOV R16, R21; /* 0x0000001500107202 */ + /* 0x000fe20000000f00 */ + /*07f0*/ IMAD.U32 R17, RZ, RZ, R22; /* 0x000000ffff117224 */ + /* 0x000fe200078e0016 */ + /*0800*/ ST.E.SYS [R12], R8; /* 0x000000000c007385 */ + /* 0x0001e2000010e908 */ + /*0810*/ ST.E.SYS [R12+0x8], R10; /* 0x000000080c007385 */ + /* 0x0003e8000010e90a */ + /*0820*/ ST.E.SYS [R14], R9; /* 0x000000000e007385 */ + /* 0x0003e2000010e909 */ + /*0830*/ ST.E.SYS [R14+0x8], R11; /* 0x000000080e007385 */ + /* 0x0003e2000010e90b */ + /*0840*/ ST.E.SYS [R18], R4; /* 0x0000000012007385 */ + /* 0x0003e2000010e904 */ + /*0850*/ ST.E.SYS [R18+0x8], R6; /* 0x0000000812007385 */ + /* 0x0003e2000010e906 */ + /*0860*/ ST.E.SYS [R16], R5; /* 0x0000000010007385 */ + /* 0x0003e2000010e905 */ + /*0870*/ ST.E.SYS [R16+0x8], R7; /* 0x0000000810007385 */ + /* 0x0003e2000010e907 */ + /*0880*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*0890*/ IADD3 R8, R2, -c[0x0][0x20], RZ; /* 0x8000080002087a10 */ + /* 0x001fd00007ffe0ff */ + /*08a0*/ CS2R.32 R4, SR_CLOCKLO; /* 0x0000000000047805 */ + /* 0x002fd00000005000 */ + /*08b0*/ IMAD R3, R4, 0x1, -R3; /* 0x0000000104037824 */ + /* 0x000fd000078e0a03 */ + /*08c0*/ STL [R8], R3; /* 0x0000000308007387 */ + /* 0x0001e20000100800 */ + /*08d0*/ IMAD.U32 R6, RZ, RZ, R2; /* 0x000000ffff067224 */ + /* 0x000fe200078e0002 */ + /*08e0*/ MOV R4, 0x0; /* 0x0000000000047802 */ + /* 0x000fe20000000f00 */ + /*08f0*/ IMAD.U32 R7, RZ, RZ, R0; /* 0x000000ffff077224 */ + /* 0x000fe200078e0000 */ + /*0900*/ MOV R5, 0x0; /* 0x0000000000057802 */ + /* 0x000fe40000000f00 */ + /*0910*/ MOV R20, 0x0; /* 0x0000000000147802 */ + /* 0x000fe40000000f00 */ + /*0920*/ MOV R21, 0x0; /* 0x0000000000157802 */ + /* 0x000fd00000000f00 */ + /*0930*/ CALL.ABS.NOINC 0x0; /* 0x0000000000007943 */ + /* 0x001fea0003c00000 */ + /*0940*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*0950*/ BRA 0x950; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + /*0960*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + /*0970*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + ............................................. + + + +Fatbin ptx code: +================ +arch = sm_70 +code version = [6,0] +producer = cuda +host = linux +compile_size = 64bit +compressed + + + + + + + + +.version 6.0 +.target sm_70 +.address_size 64 + + +.extern .func (.param .b32 func_retval0) vprintf +( +.param .b64 vprintf_param_0, +.param .b64 vprintf_param_1 +) +; +.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0}; + +.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff( +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7 +) +{ +.local .align 8 .b8 __local_depot0[8]; +.reg .b64 %SP; +.reg .b64 %SPL; +.reg .pred %p<6>; +.reg .f32 %f<34>; +.reg .b32 %r<38>; +.reg .b64 %rd<18>; + + +mov.u64 %rd17, __local_depot0; +cvta.local.u64 %SP, %rd17; +ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0]; +ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1]; +ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2]; +ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3]; +ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4]; +ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5]; + + mov.u32 %r6, %clock; + + mov.u32 %r8, %ntid.x; +mov.u32 %r9, %ctaid.x; +mov.u32 %r10, %tid.x; +mad.lo.s32 %r11, %r8, %r9, %r10; +mov.u32 %r12, WARP_SZ; +div.u32 %r13, %r11, %r12; +mov.u32 %r14, %ntid.y; +mov.u32 %r15, %ctaid.y; +mov.u32 %r16, %tid.y; +mad.lo.s32 %r17, %r14, %r15, %r16; +shl.b32 %r2, %r13, 4; +shl.b32 %r3, %r17, 4; +setp.lt.s32 %p1, %r2, %r4; +setp.gt.s32 %p2, %r5, 0; +and.pred %p3, %p1, %p2; +setp.lt.s32 %p4, %r3, %r7; +and.pred %p5, %p3, %p4; +mov.f32 %f26, 0f00000000; +mov.f32 %f27, %f26; +mov.f32 %f28, %f26; +mov.f32 %f29, %f26; +mov.f32 %f30, %f26; +mov.f32 %f31, %f26; +mov.f32 %f32, %f26; +mov.f32 %f33, %f26; +@!%p5 bra BB0_2; +bra.uni BB0_1; + +BB0_1: +mul.wide.s32 %rd4, %r2, 2; +add.s64 %rd5, %rd1, %rd4; +wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4; +mul.wide.s32 %rd6, %r3, 2; +add.s64 %rd7, %rd2, %rd6; +wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5; +mov.f32 %f25, 0f00000000; +wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25}; + +BB0_2: +add.u64 %rd8, %SP, 0; +cvta.to.local.u64 %rd9, %rd8; +mul.lo.s32 %r35, %r3, %r4; +cvt.s64.s32 %rd10, %r35; +cvt.s64.s32 %rd11, %r2; +add.s64 %rd12, %rd10, %rd11; +shl.b64 %rd13, %rd12, 2; +add.s64 %rd14, %rd3, %rd13; +wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4; + + mov.u32 %r34, %clock; + + sub.s32 %r36, %r34, %r6; +st.local.u32 [%rd9], %r36; +mov.u64 %rd15, $str; +cvta.global.u64 %rd16, %rd15; + + { +.reg .b32 temp_param_reg; + + .param .b64 param0; +st.param.b64 [param0+0], %rd16; +.param .b64 param1; +st.param.b64 [param1+0], %rd8; +.param .b32 retval0; +call.uni (retval0), +vprintf, +( +param0, +param1 +); +ld.param.b32 %r37, [retval0+0]; + + + } + ret; +} + + +.visible .entry _Z17convertFp32ToFp16P6__halfPfi( +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0, +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1, +.param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2 +) +{ +.reg .pred %p<2>; +.reg .b16 %rs<2>; +.reg .f32 %f<2>; +.reg .b32 %r<6>; +.reg .b64 %rd<9>; + + +ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0]; +ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1]; +ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2]; +mov.u32 %r3, %ntid.x; +mov.u32 %r4, %ctaid.x; +mov.u32 %r5, %tid.x; +mad.lo.s32 %r1, %r4, %r3, %r5; +setp.ge.s32 %p1, %r1, %r2; +@%p1 bra BB1_2; + +cvta.to.global.u64 %rd3, %rd2; +mul.wide.s32 %rd4, %r1, 4; +add.s64 %rd5, %rd3, %rd4; +ld.global.f32 %f1, [%rd5]; + + { cvt.rn.f16.f32 %rs1, %f1;} + + + cvta.to.global.u64 %rd6, %rd1; +mul.wide.s32 %rd7, %r1, 2; +add.s64 %rd8, %rd6, %rd7; +st.global.u16 [%rd8], %rs1; + +BB1_2: +ret; +} + + diff --git a/cuda-kernels/config_fermi_islip.icnt b/cuda-kernels/config_fermi_islip.icnt new file mode 100755 index 0000000..a788090 --- /dev/null +++ b/cuda-kernels/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 62; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/cuda-kernels/gpgpu_inst_stats.txt b/cuda-kernels/gpgpu_inst_stats.txt new file mode 100755 index 0000000..acb1839 --- /dev/null +++ b/cuda-kernels/gpgpu_inst_stats.txt @@ -0,0 +1 @@ +kernel line : count latency dram_traffic smem_bk_conflicts smem_warp gmem_access_generated gmem_warp exposed_latency warp_divergence diff --git a/cuda-kernels/gpgpusim.config b/cuda-kernels/gpgpusim.config new file mode 100755 index 0000000..306d7f9 --- /dev/null +++ b/cuda-kernels/gpgpusim.config @@ -0,0 +1,149 @@ +# This config models the Pascal GP102 (GeForceGTX 1080Ti) + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 70 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 40 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 11 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145,16,4 +-ptx_opcode_initiation_int 1,2,2,2,8,16,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 1,2,1,1,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The default is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_shmem_size 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 +-gpgpu_cache:dl2_texture_only 0 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +# gpgpu_num_reg_banks should be increased to 32, but it gives an error! +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) +# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" + +# Pascal has four schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log new file mode 100644 index 0000000..f754f0c --- /dev/null +++ b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log @@ -0,0 +1,324 @@ +kernel_name = +kernel_launch_uid = + +Kernel Average Power Data: +kernel_avg_power = 0 +gpu_avg_IBP, = -nan +gpu_avg_ICP, = -nan +gpu_avg_DCP, = -nan +gpu_avg_TCP, = -nan +gpu_avg_CCP, = -nan +gpu_avg_SHRDP, = -nan +gpu_avg_RFP, = -nan +gpu_avg_SPP, = -nan +gpu_avg_SFUP, = -nan +gpu_avg_FPUP, = -nan +gpu_avg_SCHEDP, = -nan +gpu_avg_L2CP, = -nan +gpu_avg_MCP, = -nan +gpu_avg_NOCP, = -nan +gpu_avg_DRAMP, = -nan +gpu_avg_PIPEP, = -nan +gpu_avg_IDLE_COREP, = -nan +gpu_avg_CONST_DYNAMICP = -nan +gpu_avg_TOT_INST, = -nan +gpu_avg_FP_INT, = -nan +gpu_avg_IC_H, = -nan +gpu_avg_IC_M, = -nan +gpu_avg_DC_RH, = -nan +gpu_avg_DC_RM, = -nan +gpu_avg_DC_WH, = -nan +gpu_avg_DC_WM, = -nan +gpu_avg_TC_H, = -nan +gpu_avg_TC_M, = -nan +gpu_avg_CC_H, = -nan +gpu_avg_CC_M, = -nan +gpu_avg_SHRD_ACC, = -nan +gpu_avg_REG_RD, = -nan +gpu_avg_REG_WR, = -nan +gpu_avg_NON_REG_OPs, = -nan +gpu_avg_SP_ACC, = -nan +gpu_avg_SFU_ACC, = -nan +gpu_avg_FPU_ACC, = -nan +gpu_avg_MEM_RD, = -nan +gpu_avg_MEM_WR, = -nan +gpu_avg_MEM_PRE, = -nan +gpu_avg_L2_RH, = -nan +gpu_avg_L2_RM, = -nan +gpu_avg_L2_WH, = -nan +gpu_avg_L2_WM, = -nan +gpu_avg_NOC_A, = -nan +gpu_avg_PIPE_A, = -nan +gpu_avg_IDLE_CORE_N, = -nan +gpu_avg_CONST_DYNAMICN = -nan + +Kernel Maximum Power Data: +kernel_max_power = 0 +gpu_max_IBP, = 0 +gpu_max_ICP, = 0 +gpu_max_DCP, = 0 +gpu_max_TCP, = 0 +gpu_max_CCP, = 0 +gpu_max_SHRDP, = 0 +gpu_max_RFP, = 0 +gpu_max_SPP, = 0 +gpu_max_SFUP, = 0 +gpu_max_FPUP, = 0 +gpu_max_SCHEDP, = 0 +gpu_max_L2CP, = 0 +gpu_max_MCP, = 0 +gpu_max_NOCP, = 0 +gpu_max_DRAMP, = 0 +gpu_max_PIPEP, = 0 +gpu_max_IDLE_COREP, = 0 +gpu_max_CONST_DYNAMICP = 0 +gpu_max_TOT_INST, = 0 +gpu_max_FP_INT, = 0 +gpu_max_IC_H, = 0 +gpu_max_IC_M, = 0 +gpu_max_DC_RH, = 0 +gpu_max_DC_RM, = 0 +gpu_max_DC_WH, = 0 +gpu_max_DC_WM, = 0 +gpu_max_TC_H, = 0 +gpu_max_TC_M, = 0 +gpu_max_CC_H, = 0 +gpu_max_CC_M, = 0 +gpu_max_SHRD_ACC, = 0 +gpu_max_REG_RD, = 0 +gpu_max_REG_WR, = 0 +gpu_max_NON_REG_OPs, = 0 +gpu_max_SP_ACC, = 0 +gpu_max_SFU_ACC, = 0 +gpu_max_FPU_ACC, = 0 +gpu_max_MEM_RD, = 0 +gpu_max_MEM_WR, = 0 +gpu_max_MEM_PRE, = 0 +gpu_max_L2_RH, = 0 +gpu_max_L2_RM, = 0 +gpu_max_L2_WH, = 0 +gpu_max_L2_WM, = 0 +gpu_max_NOC_A, = 0 +gpu_max_PIPE_A, = 0 +gpu_max_IDLE_CORE_N, = 0 +gpu_max_CONST_DYNAMICN = 0 + +Kernel Minimum Power Data: +kernel_min_power = 0 +gpu_min_IBP, = 0 +gpu_min_ICP, = 0 +gpu_min_DCP, = 0 +gpu_min_TCP, = 0 +gpu_min_CCP, = 0 +gpu_min_SHRDP, = 0 +gpu_min_RFP, = 0 +gpu_min_SPP, = 0 +gpu_min_SFUP, = 0 +gpu_min_FPUP, = 0 +gpu_min_SCHEDP, = 0 +gpu_min_L2CP, = 0 +gpu_min_MCP, = 0 +gpu_min_NOCP, = 0 +gpu_min_DRAMP, = 0 +gpu_min_PIPEP, = 0 +gpu_min_IDLE_COREP, = 0 +gpu_min_CONST_DYNAMICP = 0 +gpu_min_TOT_INST, = 0 +gpu_min_FP_INT, = 0 +gpu_min_IC_H, = 0 +gpu_min_IC_M, = 0 +gpu_min_DC_RH, = 0 +gpu_min_DC_RM, = 0 +gpu_min_DC_WH, = 0 +gpu_min_DC_WM, = 0 +gpu_min_TC_H, = 0 +gpu_min_TC_M, = 0 +gpu_min_CC_H, = 0 +gpu_min_CC_M, = 0 +gpu_min_SHRD_ACC, = 0 +gpu_min_REG_RD, = 0 +gpu_min_REG_WR, = 0 +gpu_min_NON_REG_OPs, = 0 +gpu_min_SP_ACC, = 0 +gpu_min_SFU_ACC, = 0 +gpu_min_FPU_ACC, = 0 +gpu_min_MEM_RD, = 0 +gpu_min_MEM_WR, = 0 +gpu_min_MEM_PRE, = 0 +gpu_min_L2_RH, = 0 +gpu_min_L2_RM, = 0 +gpu_min_L2_WH, = 0 +gpu_min_L2_WM, = 0 +gpu_min_NOC_A, = 0 +gpu_min_PIPE_A, = 0 +gpu_min_IDLE_CORE_N, = 0 +gpu_min_CONST_DYNAMICN = 0 + +Accumulative Power Statistics Over Previous Kernels: +gpu_tot_avg_power = -nan +gpu_tot_max_power = 0 +gpu_tot_min_power = 0 + + +kernel_name = +kernel_launch_uid = + +Kernel Average Power Data: +kernel_avg_power = 0 +gpu_avg_IBP, = -nan +gpu_avg_ICP, = -nan +gpu_avg_DCP, = -nan +gpu_avg_TCP, = -nan +gpu_avg_CCP, = -nan +gpu_avg_SHRDP, = -nan +gpu_avg_RFP, = -nan +gpu_avg_SPP, = -nan +gpu_avg_SFUP, = -nan +gpu_avg_FPUP, = -nan +gpu_avg_SCHEDP, = -nan +gpu_avg_L2CP, = -nan +gpu_avg_MCP, = -nan +gpu_avg_NOCP, = -nan +gpu_avg_DRAMP, = -nan +gpu_avg_PIPEP, = -nan +gpu_avg_IDLE_COREP, = -nan +gpu_avg_CONST_DYNAMICP = -nan +gpu_avg_TOT_INST, = -nan +gpu_avg_FP_INT, = -nan +gpu_avg_IC_H, = -nan +gpu_avg_IC_M, = -nan +gpu_avg_DC_RH, = -nan +gpu_avg_DC_RM, = -nan +gpu_avg_DC_WH, = -nan +gpu_avg_DC_WM, = -nan +gpu_avg_TC_H, = -nan +gpu_avg_TC_M, = -nan +gpu_avg_CC_H, = -nan +gpu_avg_CC_M, = -nan +gpu_avg_SHRD_ACC, = -nan +gpu_avg_REG_RD, = -nan +gpu_avg_REG_WR, = -nan +gpu_avg_NON_REG_OPs, = -nan +gpu_avg_SP_ACC, = -nan +gpu_avg_SFU_ACC, = -nan +gpu_avg_FPU_ACC, = -nan +gpu_avg_MEM_RD, = -nan +gpu_avg_MEM_WR, = -nan +gpu_avg_MEM_PRE, = -nan +gpu_avg_L2_RH, = -nan +gpu_avg_L2_RM, = -nan +gpu_avg_L2_WH, = -nan +gpu_avg_L2_WM, = -nan +gpu_avg_NOC_A, = -nan +gpu_avg_PIPE_A, = -nan +gpu_avg_IDLE_CORE_N, = -nan +gpu_avg_CONST_DYNAMICN = -nan + +Kernel Maximum Power Data: +kernel_max_power = 0 +gpu_max_IBP, = 0 +gpu_max_ICP, = 0 +gpu_max_DCP, = 0 +gpu_max_TCP, = 0 +gpu_max_CCP, = 0 +gpu_max_SHRDP, = 0 +gpu_max_RFP, = 0 +gpu_max_SPP, = 0 +gpu_max_SFUP, = 0 +gpu_max_FPUP, = 0 +gpu_max_SCHEDP, = 0 +gpu_max_L2CP, = 0 +gpu_max_MCP, = 0 +gpu_max_NOCP, = 0 +gpu_max_DRAMP, = 0 +gpu_max_PIPEP, = 0 +gpu_max_IDLE_COREP, = 0 +gpu_max_CONST_DYNAMICP = 0 +gpu_max_TOT_INST, = 0 +gpu_max_FP_INT, = 0 +gpu_max_IC_H, = 0 +gpu_max_IC_M, = 0 +gpu_max_DC_RH, = 0 +gpu_max_DC_RM, = 0 +gpu_max_DC_WH, = 0 +gpu_max_DC_WM, = 0 +gpu_max_TC_H, = 0 +gpu_max_TC_M, = 0 +gpu_max_CC_H, = 0 +gpu_max_CC_M, = 0 +gpu_max_SHRD_ACC, = 0 +gpu_max_REG_RD, = 0 +gpu_max_REG_WR, = 0 +gpu_max_NON_REG_OPs, = 0 +gpu_max_SP_ACC, = 0 +gpu_max_SFU_ACC, = 0 +gpu_max_FPU_ACC, = 0 +gpu_max_MEM_RD, = 0 +gpu_max_MEM_WR, = 0 +gpu_max_MEM_PRE, = 0 +gpu_max_L2_RH, = 0 +gpu_max_L2_RM, = 0 +gpu_max_L2_WH, = 0 +gpu_max_L2_WM, = 0 +gpu_max_NOC_A, = 0 +gpu_max_PIPE_A, = 0 +gpu_max_IDLE_CORE_N, = 0 +gpu_max_CONST_DYNAMICN = 0 + +Kernel Minimum Power Data: +kernel_min_power = 0 +gpu_min_IBP, = 0 +gpu_min_ICP, = 0 +gpu_min_DCP, = 0 +gpu_min_TCP, = 0 +gpu_min_CCP, = 0 +gpu_min_SHRDP, = 0 +gpu_min_RFP, = 0 +gpu_min_SPP, = 0 +gpu_min_SFUP, = 0 +gpu_min_FPUP, = 0 +gpu_min_SCHEDP, = 0 +gpu_min_L2CP, = 0 +gpu_min_MCP, = 0 +gpu_min_NOCP, = 0 +gpu_min_DRAMP, = 0 +gpu_min_PIPEP, = 0 +gpu_min_IDLE_COREP, = 0 +gpu_min_CONST_DYNAMICP = 0 +gpu_min_TOT_INST, = 0 +gpu_min_FP_INT, = 0 +gpu_min_IC_H, = 0 +gpu_min_IC_M, = 0 +gpu_min_DC_RH, = 0 +gpu_min_DC_RM, = 0 +gpu_min_DC_WH, = 0 +gpu_min_DC_WM, = 0 +gpu_min_TC_H, = 0 +gpu_min_TC_M, = 0 +gpu_min_CC_H, = 0 +gpu_min_CC_M, = 0 +gpu_min_SHRD_ACC, = 0 +gpu_min_REG_RD, = 0 +gpu_min_REG_WR, = 0 +gpu_min_NON_REG_OPs, = 0 +gpu_min_SP_ACC, = 0 +gpu_min_SFU_ACC, = 0 +gpu_min_FPU_ACC, = 0 +gpu_min_MEM_RD, = 0 +gpu_min_MEM_WR, = 0 +gpu_min_MEM_PRE, = 0 +gpu_min_L2_RH, = 0 +gpu_min_L2_RM, = 0 +gpu_min_L2_WH, = 0 +gpu_min_L2_WM, = 0 +gpu_min_NOC_A, = 0 +gpu_min_PIPE_A, = 0 +gpu_min_IDLE_CORE_N, = 0 +gpu_min_CONST_DYNAMICN = 0 + +Accumulative Power Statistics Over Previous Kernels: +gpu_tot_avg_power = -nan +gpu_tot_max_power = 0 +gpu_tot_min_power = 0 + + diff --git a/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log new file mode 100644 index 0000000..f754f0c --- /dev/null +++ b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log @@ -0,0 +1,324 @@ +kernel_name = +kernel_launch_uid = + +Kernel Average Power Data: +kernel_avg_power = 0 +gpu_avg_IBP, = -nan +gpu_avg_ICP, = -nan +gpu_avg_DCP, = -nan +gpu_avg_TCP, = -nan +gpu_avg_CCP, = -nan +gpu_avg_SHRDP, = -nan +gpu_avg_RFP, = -nan +gpu_avg_SPP, = -nan +gpu_avg_SFUP, = -nan +gpu_avg_FPUP, = -nan +gpu_avg_SCHEDP, = -nan +gpu_avg_L2CP, = -nan +gpu_avg_MCP, = -nan +gpu_avg_NOCP, = -nan +gpu_avg_DRAMP, = -nan +gpu_avg_PIPEP, = -nan +gpu_avg_IDLE_COREP, = -nan +gpu_avg_CONST_DYNAMICP = -nan +gpu_avg_TOT_INST, = -nan +gpu_avg_FP_INT, = -nan +gpu_avg_IC_H, = -nan +gpu_avg_IC_M, = -nan +gpu_avg_DC_RH, = -nan +gpu_avg_DC_RM, = -nan +gpu_avg_DC_WH, = -nan +gpu_avg_DC_WM, = -nan +gpu_avg_TC_H, = -nan +gpu_avg_TC_M, = -nan +gpu_avg_CC_H, = -nan +gpu_avg_CC_M, = -nan +gpu_avg_SHRD_ACC, = -nan +gpu_avg_REG_RD, = -nan +gpu_avg_REG_WR, = -nan +gpu_avg_NON_REG_OPs, = -nan +gpu_avg_SP_ACC, = -nan +gpu_avg_SFU_ACC, = -nan +gpu_avg_FPU_ACC, = -nan +gpu_avg_MEM_RD, = -nan +gpu_avg_MEM_WR, = -nan +gpu_avg_MEM_PRE, = -nan +gpu_avg_L2_RH, = -nan +gpu_avg_L2_RM, = -nan +gpu_avg_L2_WH, = -nan +gpu_avg_L2_WM, = -nan +gpu_avg_NOC_A, = -nan +gpu_avg_PIPE_A, = -nan +gpu_avg_IDLE_CORE_N, = -nan +gpu_avg_CONST_DYNAMICN = -nan + +Kernel Maximum Power Data: +kernel_max_power = 0 +gpu_max_IBP, = 0 +gpu_max_ICP, = 0 +gpu_max_DCP, = 0 +gpu_max_TCP, = 0 +gpu_max_CCP, = 0 +gpu_max_SHRDP, = 0 +gpu_max_RFP, = 0 +gpu_max_SPP, = 0 +gpu_max_SFUP, = 0 +gpu_max_FPUP, = 0 +gpu_max_SCHEDP, = 0 +gpu_max_L2CP, = 0 +gpu_max_MCP, = 0 +gpu_max_NOCP, = 0 +gpu_max_DRAMP, = 0 +gpu_max_PIPEP, = 0 +gpu_max_IDLE_COREP, = 0 +gpu_max_CONST_DYNAMICP = 0 +gpu_max_TOT_INST, = 0 +gpu_max_FP_INT, = 0 +gpu_max_IC_H, = 0 +gpu_max_IC_M, = 0 +gpu_max_DC_RH, = 0 +gpu_max_DC_RM, = 0 +gpu_max_DC_WH, = 0 +gpu_max_DC_WM, = 0 +gpu_max_TC_H, = 0 +gpu_max_TC_M, = 0 +gpu_max_CC_H, = 0 +gpu_max_CC_M, = 0 +gpu_max_SHRD_ACC, = 0 +gpu_max_REG_RD, = 0 +gpu_max_REG_WR, = 0 +gpu_max_NON_REG_OPs, = 0 +gpu_max_SP_ACC, = 0 +gpu_max_SFU_ACC, = 0 +gpu_max_FPU_ACC, = 0 +gpu_max_MEM_RD, = 0 +gpu_max_MEM_WR, = 0 +gpu_max_MEM_PRE, = 0 +gpu_max_L2_RH, = 0 +gpu_max_L2_RM, = 0 +gpu_max_L2_WH, = 0 +gpu_max_L2_WM, = 0 +gpu_max_NOC_A, = 0 +gpu_max_PIPE_A, = 0 +gpu_max_IDLE_CORE_N, = 0 +gpu_max_CONST_DYNAMICN = 0 + +Kernel Minimum Power Data: +kernel_min_power = 0 +gpu_min_IBP, = 0 +gpu_min_ICP, = 0 +gpu_min_DCP, = 0 +gpu_min_TCP, = 0 +gpu_min_CCP, = 0 +gpu_min_SHRDP, = 0 +gpu_min_RFP, = 0 +gpu_min_SPP, = 0 +gpu_min_SFUP, = 0 +gpu_min_FPUP, = 0 +gpu_min_SCHEDP, = 0 +gpu_min_L2CP, = 0 +gpu_min_MCP, = 0 +gpu_min_NOCP, = 0 +gpu_min_DRAMP, = 0 +gpu_min_PIPEP, = 0 +gpu_min_IDLE_COREP, = 0 +gpu_min_CONST_DYNAMICP = 0 +gpu_min_TOT_INST, = 0 +gpu_min_FP_INT, = 0 +gpu_min_IC_H, = 0 +gpu_min_IC_M, = 0 +gpu_min_DC_RH, = 0 +gpu_min_DC_RM, = 0 +gpu_min_DC_WH, = 0 +gpu_min_DC_WM, = 0 +gpu_min_TC_H, = 0 +gpu_min_TC_M, = 0 +gpu_min_CC_H, = 0 +gpu_min_CC_M, = 0 +gpu_min_SHRD_ACC, = 0 +gpu_min_REG_RD, = 0 +gpu_min_REG_WR, = 0 +gpu_min_NON_REG_OPs, = 0 +gpu_min_SP_ACC, = 0 +gpu_min_SFU_ACC, = 0 +gpu_min_FPU_ACC, = 0 +gpu_min_MEM_RD, = 0 +gpu_min_MEM_WR, = 0 +gpu_min_MEM_PRE, = 0 +gpu_min_L2_RH, = 0 +gpu_min_L2_RM, = 0 +gpu_min_L2_WH, = 0 +gpu_min_L2_WM, = 0 +gpu_min_NOC_A, = 0 +gpu_min_PIPE_A, = 0 +gpu_min_IDLE_CORE_N, = 0 +gpu_min_CONST_DYNAMICN = 0 + +Accumulative Power Statistics Over Previous Kernels: +gpu_tot_avg_power = -nan +gpu_tot_max_power = 0 +gpu_tot_min_power = 0 + + +kernel_name = +kernel_launch_uid = + +Kernel Average Power Data: +kernel_avg_power = 0 +gpu_avg_IBP, = -nan +gpu_avg_ICP, = -nan +gpu_avg_DCP, = -nan +gpu_avg_TCP, = -nan +gpu_avg_CCP, = -nan +gpu_avg_SHRDP, = -nan +gpu_avg_RFP, = -nan +gpu_avg_SPP, = -nan +gpu_avg_SFUP, = -nan +gpu_avg_FPUP, = -nan +gpu_avg_SCHEDP, = -nan +gpu_avg_L2CP, = -nan +gpu_avg_MCP, = -nan +gpu_avg_NOCP, = -nan +gpu_avg_DRAMP, = -nan +gpu_avg_PIPEP, = -nan +gpu_avg_IDLE_COREP, = -nan +gpu_avg_CONST_DYNAMICP = -nan +gpu_avg_TOT_INST, = -nan +gpu_avg_FP_INT, = -nan +gpu_avg_IC_H, = -nan +gpu_avg_IC_M, = -nan +gpu_avg_DC_RH, = -nan +gpu_avg_DC_RM, = -nan +gpu_avg_DC_WH, = -nan +gpu_avg_DC_WM, = -nan +gpu_avg_TC_H, = -nan +gpu_avg_TC_M, = -nan +gpu_avg_CC_H, = -nan +gpu_avg_CC_M, = -nan +gpu_avg_SHRD_ACC, = -nan +gpu_avg_REG_RD, = -nan +gpu_avg_REG_WR, = -nan +gpu_avg_NON_REG_OPs, = -nan +gpu_avg_SP_ACC, = -nan +gpu_avg_SFU_ACC, = -nan +gpu_avg_FPU_ACC, = -nan +gpu_avg_MEM_RD, = -nan +gpu_avg_MEM_WR, = -nan +gpu_avg_MEM_PRE, = -nan +gpu_avg_L2_RH, = -nan +gpu_avg_L2_RM, = -nan +gpu_avg_L2_WH, = -nan +gpu_avg_L2_WM, = -nan +gpu_avg_NOC_A, = -nan +gpu_avg_PIPE_A, = -nan +gpu_avg_IDLE_CORE_N, = -nan +gpu_avg_CONST_DYNAMICN = -nan + +Kernel Maximum Power Data: +kernel_max_power = 0 +gpu_max_IBP, = 0 +gpu_max_ICP, = 0 +gpu_max_DCP, = 0 +gpu_max_TCP, = 0 +gpu_max_CCP, = 0 +gpu_max_SHRDP, = 0 +gpu_max_RFP, = 0 +gpu_max_SPP, = 0 +gpu_max_SFUP, = 0 +gpu_max_FPUP, = 0 +gpu_max_SCHEDP, = 0 +gpu_max_L2CP, = 0 +gpu_max_MCP, = 0 +gpu_max_NOCP, = 0 +gpu_max_DRAMP, = 0 +gpu_max_PIPEP, = 0 +gpu_max_IDLE_COREP, = 0 +gpu_max_CONST_DYNAMICP = 0 +gpu_max_TOT_INST, = 0 +gpu_max_FP_INT, = 0 +gpu_max_IC_H, = 0 +gpu_max_IC_M, = 0 +gpu_max_DC_RH, = 0 +gpu_max_DC_RM, = 0 +gpu_max_DC_WH, = 0 +gpu_max_DC_WM, = 0 +gpu_max_TC_H, = 0 +gpu_max_TC_M, = 0 +gpu_max_CC_H, = 0 +gpu_max_CC_M, = 0 +gpu_max_SHRD_ACC, = 0 +gpu_max_REG_RD, = 0 +gpu_max_REG_WR, = 0 +gpu_max_NON_REG_OPs, = 0 +gpu_max_SP_ACC, = 0 +gpu_max_SFU_ACC, = 0 +gpu_max_FPU_ACC, = 0 +gpu_max_MEM_RD, = 0 +gpu_max_MEM_WR, = 0 +gpu_max_MEM_PRE, = 0 +gpu_max_L2_RH, = 0 +gpu_max_L2_RM, = 0 +gpu_max_L2_WH, = 0 +gpu_max_L2_WM, = 0 +gpu_max_NOC_A, = 0 +gpu_max_PIPE_A, = 0 +gpu_max_IDLE_CORE_N, = 0 +gpu_max_CONST_DYNAMICN = 0 + +Kernel Minimum Power Data: +kernel_min_power = 0 +gpu_min_IBP, = 0 +gpu_min_ICP, = 0 +gpu_min_DCP, = 0 +gpu_min_TCP, = 0 +gpu_min_CCP, = 0 +gpu_min_SHRDP, = 0 +gpu_min_RFP, = 0 +gpu_min_SPP, = 0 +gpu_min_SFUP, = 0 +gpu_min_FPUP, = 0 +gpu_min_SCHEDP, = 0 +gpu_min_L2CP, = 0 +gpu_min_MCP, = 0 +gpu_min_NOCP, = 0 +gpu_min_DRAMP, = 0 +gpu_min_PIPEP, = 0 +gpu_min_IDLE_COREP, = 0 +gpu_min_CONST_DYNAMICP = 0 +gpu_min_TOT_INST, = 0 +gpu_min_FP_INT, = 0 +gpu_min_IC_H, = 0 +gpu_min_IC_M, = 0 +gpu_min_DC_RH, = 0 +gpu_min_DC_RM, = 0 +gpu_min_DC_WH, = 0 +gpu_min_DC_WM, = 0 +gpu_min_TC_H, = 0 +gpu_min_TC_M, = 0 +gpu_min_CC_H, = 0 +gpu_min_CC_M, = 0 +gpu_min_SHRD_ACC, = 0 +gpu_min_REG_RD, = 0 +gpu_min_REG_WR, = 0 +gpu_min_NON_REG_OPs, = 0 +gpu_min_SP_ACC, = 0 +gpu_min_SFU_ACC, = 0 +gpu_min_FPU_ACC, = 0 +gpu_min_MEM_RD, = 0 +gpu_min_MEM_WR, = 0 +gpu_min_MEM_PRE, = 0 +gpu_min_L2_RH, = 0 +gpu_min_L2_RM, = 0 +gpu_min_L2_WH, = 0 +gpu_min_L2_WM, = 0 +gpu_min_NOC_A, = 0 +gpu_min_PIPE_A, = 0 +gpu_min_IDLE_CORE_N, = 0 +gpu_min_CONST_DYNAMICN = 0 + +Accumulative Power Statistics Over Previous Kernels: +gpu_tot_avg_power = -nan +gpu_tot_max_power = 0 +gpu_tot_min_power = 0 + + diff --git a/cuda-kernels/gpuwattch_gtx1080Ti.xml b/cuda-kernels/gpuwattch_gtx1080Ti.xml new file mode 100755 index 0000000..02619ff --- /dev/null +++ b/cuda-kernels/gpuwattch_gtx1080Ti.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cuda-kernels/tensor_core b/cuda-kernels/tensor_core new file mode 100755 index 0000000..b25f3d9 Binary files /dev/null and b/cuda-kernels/tensor_core differ diff --git a/cuda-kernels/tensor_core.cu b/cuda-kernels/tensor_core.cu new file mode 100644 index 0000000..483a42b --- /dev/null +++ b/cuda-kernels/tensor_core.cu @@ -0,0 +1,250 @@ +/* Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of NVIDIA CORPORATION nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +// Define some error checking macros. +#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } +void cudaErrCheck_(cudaError_t stat, const char *file, int line) { + if (stat != cudaSuccess) { + fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); + } +} + + + + +#include +using namespace nvcuda; + +// Must be multiples of 16 for wmma code to work +#define MATRIX_M (16) +#define MATRIX_N (16) +#define MATRIX_K (16) + + + +// The only dimensions currently supported by WMMA +const int WMMA_M = 16; +const int WMMA_N = 16; +const int WMMA_K = 16; + + +// Performs an MxNxK GEMM (C=alpha*A*B + beta*C) assuming: +// 1) Matrices are packed in memory. +// 2) M, N and K are multiples of 16. +// 3) Neither A nor B are transposed. +// Note: This is NOT a high performance example but is for demonstration purposes only +// For a high performance code please use the GEMM provided in cuBLAS. +__global__ void wmma_example(half *a, half *b, float *c, int M, int N, int K, float alpha, float beta) { + unsigned int start_time=0,end_time=0; + // Leading dimensions. Packed with no transpositions. + start_time=clock(); + int lda = M; + int ldb = K; + int ldc = M; + + // Tile using a 2D grid/ + int warpM = (blockIdx.x * blockDim.x + threadIdx.x) / warpSize; + int warpN = (blockIdx.y * blockDim.y + threadIdx.y); + + // Declare the fragments + wmma::fragment a_frag; + wmma::fragment b_frag; + wmma::fragment acc_frag; + wmma::fragment c_frag; + + wmma::fill_fragment(c_frag, 0.0f); + + int i=0; + int aRow = warpM * WMMA_M; + int bCol = warpN * WMMA_N; + int aCol = i; + int bRow = i; + + + // Bounds checking + if (aRow < M && aCol < K && bRow < K && bCol < N) { + wmma::load_matrix_sync(a_frag, a+aRow+aCol*lda, lda); + wmma::load_matrix_sync(b_frag, b+bRow*ldb+bCol, ldb); + wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); + //wmma::mma_sync(acc_frag, a_frag, b_frag, acc_frag); + } + int cRow = warpM * WMMA_M; + int cCol = warpN * WMMA_N; + wmma::store_matrix_sync(c + cRow + cCol * ldc, c_frag, ldc, wmma::mem_col_major); + end_time=clock(); + printf("clock=%d",end_time-start_time); +} + +__global__ void convertFp32ToFp16 (half *out, float *in, int n) { + int idx = blockDim.x * blockIdx.x + threadIdx.x; + if (idx < n) { + out[idx] = in[idx]; + } +} + +int main(int argc, char* argv[]) { + float *a_fp32; + float *b_fp32; + half *a_fp16; + half *b_fp16; + + float *c; + float *c_cublas; + float *c_wmma; + + float *c_host_cublas; + float *c_host_wmma; + float *a_host_wmma; + float *b_host_wmma; + float *c_init_host_wmma; + + + cudaEvent_t startWMMA; + cudaEvent_t stopWMMA; + + + cudaErrCheck(cudaEventCreate(&startWMMA)); + cudaErrCheck(cudaEventCreate(&stopWMMA)); + + + + + // Use tensor cores + + + cudaErrCheck(cudaMalloc((void**)&a_fp32, MATRIX_M * MATRIX_K * sizeof(float))); + cudaErrCheck(cudaMalloc((void**)&b_fp32, MATRIX_K * MATRIX_N * sizeof(float))); + cudaErrCheck(cudaMalloc((void**)&a_fp16, MATRIX_M * MATRIX_K * sizeof(half))); + cudaErrCheck(cudaMalloc((void**)&b_fp16, MATRIX_K * MATRIX_N * sizeof(half))); + + cudaErrCheck(cudaMalloc((void**)&c, MATRIX_M * MATRIX_N * sizeof(float))); + cudaErrCheck(cudaMalloc((void**)&c_wmma, MATRIX_M * MATRIX_N * sizeof(float))); + + c_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); + c_init_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); + a_host_wmma = (float*)malloc(MATRIX_M * MATRIX_K * sizeof(float)); + b_host_wmma = (float*)malloc(MATRIX_K * MATRIX_N * sizeof(float)); + + + +// printf("a_fp32\n"); + for(int m=0;m>> (a_fp16, a_fp32, MATRIX_M * MATRIX_K); + convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); + + for(int m=0;m>> (a_fp16, b_fp16, c_wmma, MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta); + // wmma_example <<< gridDim, blockDim >>> (a_fp16, b_fp16, c_wmma, MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta); + cudaErrCheck(cudaEventRecord(stopWMMA)); + + + + + // Error checking + printf("\nChecking results...\n"); + cudaErrCheck(cudaMemcpy(c_host_wmma, c_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); + // printf("c_host\n"); + // for(int m=0;m{ +\.a\.sync TC; ptx_lval.int_value = LOAD_A; return WMMA_DIRECTIVE; +\.b\.sync TC; ptx_lval.int_value = LOAD_B; return WMMA_DIRECTIVE; +\.c\.sync TC; ptx_lval.int_value = LOAD_C; return WMMA_DIRECTIVE; +\.d\.sync TC; ptx_lval.int_value = STORE_D; return WMMA_DIRECTIVE; +\.sync TC;ptx_lval.int_value=MMA; return WMMA_DIRECTIVE; +\.row TC; ptx_lval.int_value = ROW; return LAYOUT; +\.col TC; ptx_lval.int_value = COL; return LAYOUT; +\.m16n16k16 TC; ptx_lval.int_value = M16N16K16; return CONFIGURATION; + \.align TC; return ALIGN_DIRECTIVE; \.branchtargets TC; return BRANCHTARGETS_DIRECTIVE; diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 3360c55..737657c 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -37,6 +37,9 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token STRING %token OPCODE +%token WMMA_DIRECTIVE +%token LAYOUT +%token CONFIGURATION %token ALIGN_DIRECTIVE %token BRANCHTARGETS_DIRECTIVE %token BYTE_DIRECTIVE @@ -428,6 +431,7 @@ option: type_spec | compare_spec | addressable_spec | rounding_mode + | wmma_spec | SYNC_OPTION { add_option(SYNC_OPTION); } | ARRIVE_OPTION { add_option(ARRIVE_OPTION); } | RED_OPTION { add_option(RED_OPTION); } @@ -483,6 +487,7 @@ atomic_operation_spec: ATOMIC_AND { add_option(ATOMIC_AND); } rounding_mode: floating_point_rounding_mode | integer_rounding_mode; + floating_point_rounding_mode: RN_OPTION { add_option(RN_OPTION); } | RZ_OPTION { add_option(RZ_OPTION); } | RM_OPTION { add_option(RM_OPTION); } @@ -515,6 +520,10 @@ compare_spec:EQ_OPTION { add_option(EQ_OPTION); } | NAN_OPTION { add_option(NAN_OPTION); } ; +wmma_spec: WMMA_DIRECTIVE LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2);add_wmma_option($3);} + | WMMA_DIRECTIVE LAYOUT LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2),add_wmma_option($3),add_wmma_option($4)} + ; + operand_list: operand | operand COMMA operand_list; @@ -543,6 +552,7 @@ operand: IDENTIFIER { add_scalar_operand( $1 ); } vector_operand: LEFT_BRACE IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_2vector_operand($2,$4); } | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_3vector_operand($2,$4,$6); } | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_4vector_operand($2,$4,$6,$8); } + | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_8vector_operand($2,$4,$6,$8,$10,$12,$14,$16); } | LEFT_BRACE IDENTIFIER RIGHT_BRACE { add_1vector_operand($2); } ; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 8ebdcf8..9a4d8d3 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -995,7 +995,7 @@ static std::list check_operands( int opcode, const std::list &operands ) { static int g_warn_literal_operands_two_type_inst; - if( (opcode == CVT_OP) || (opcode == SET_OP) || (opcode == SLCT_OP) || (opcode == TEX_OP) ) { + if( (opcode == CVT_OP) || (opcode == SET_OP) || (opcode == SLCT_OP) || (opcode == TEX_OP) || (opcode==MMA_OP)) { // just make sure these do not have have const operands... if( !g_warn_literal_operands_two_type_inst ) { std::list::const_iterator o; @@ -1043,6 +1043,7 @@ ptx_instruction::ptx_instruction( int opcode, const std::list &operands, const operand_info &return_var, const std::list &options, + const std::list &wmma_options, const std::list &scalar_type, memory_space_t space_spec, const char *file, @@ -1061,6 +1062,7 @@ ptx_instruction::ptx_instruction( int opcode, m_operands.insert(m_operands.begin(), checked_operands.begin(), checked_operands.end() ); m_return_var = return_var; m_options = options; + m_wmma_options = wmma_options; m_wide = false; m_hi = false; m_lo = false; @@ -1078,7 +1080,7 @@ ptx_instruction::ptx_instruction( int opcode, m_atomic_spec = 0; m_membar_level = 0; m_inst_size = 8; // bytes - + int rr=0; std::list::const_iterator i; unsigned n=1; for ( i=options.begin(); i!= options.end(); i++, n++ ) { diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 0601b97..ff24a66 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -582,6 +582,34 @@ public: m_is_return_var = false; m_immediate_address=false; } + operand_info( const symbol *s1, const symbol *s2, const symbol *s3, const symbol *s4 ,const symbol *s5,const symbol *s6,const symbol *s7, const symbol *s8) + { + init(); + m_is_non_arch_reg = false; + m_addr_space = undefined_space; + m_operand_lohi = 0; + m_double_operand_type = 0; + m_operand_neg = false; + m_const_mem_offset = 0; + m_uid = get_uid(); + m_valid = true; + m_vector = true; + m_type = vector_t; + m_value.m_vector_symbolic = new const symbol*[8]; + m_value.m_vector_symbolic[0] = s1; + m_value.m_vector_symbolic[1] = s2; + m_value.m_vector_symbolic[2] = s3; + m_value.m_vector_symbolic[3] = s4; + m_value.m_vector_symbolic[4] = s5; + m_value.m_vector_symbolic[5] = s6; + m_value.m_vector_symbolic[6] = s7; + m_value.m_vector_symbolic[7] = s8; + m_addr_offset = 0; + m_neg_pred = false; + m_is_return_var = false; + m_immediate_address=false; + } + void init() { m_uid=(unsigned)-1; @@ -866,6 +894,7 @@ public: const std::list &operands, const operand_info &return_var, const std::list &options, + const std::list &wmma_options, const std::list &scalar_type, memory_space_t space_spec, const char *file, @@ -1087,6 +1116,7 @@ private: operand_info m_return_var; std::list m_options; + std::list m_wmma_options; bool m_wide; bool m_hi; bool m_lo; @@ -1096,6 +1126,9 @@ private: bool m_uni; //if branch instruction, this evaluates to true for uniform branches (ie jumps) bool m_to_option; unsigned m_cache_option; + unsigned m_wmma_type; + unsigned m_wmma_layout[2]; + unsigned m_wmma_configuration; unsigned m_rounding_mode; unsigned m_compare_op; unsigned m_saturation_mode; diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index 7fc54e9..6757091 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -72,6 +72,7 @@ symbol *g_label; int g_opcode = -1; std::list g_operands; std::list g_options; +std::list g_wmma_options; std::list g_scalar_type; #define PTX_PARSE_DPRINTF(...) \ @@ -162,6 +163,7 @@ void init_instruction_state() g_label = NULL; g_opcode = -1; g_options.clear(); + g_wmma_options.clear(); g_return_var = operand_info(); init_directive_state(); } @@ -300,6 +302,7 @@ void add_instruction() g_operands, g_return_var, g_options, + g_wmma_options, g_scalar_type, g_space_spec, g_filename, @@ -629,7 +632,7 @@ void add_scalar_type_spec( int type_spec ) g_scalar_type.push_back( type_spec ); if ( g_scalar_type.size() > 1 ) { parse_assert( (g_opcode == -1) || (g_opcode == CVT_OP) || (g_opcode == SET_OP) || (g_opcode == SLCT_OP) - || (g_opcode == TEX_OP), + || (g_opcode == TEX_OP)|| (g_opcode==MMA_OP), "only cvt, set, slct, and tex can have more than one type specifier."); } g_scalar_type_spec = type_spec; @@ -669,7 +672,11 @@ void add_option( int option ) PTX_PARSE_DPRINTF("add_option"); g_options.push_back( option ); } - +void add_wmma_option( int option ) +{ + PTX_PARSE_DPRINTF("add_option"); + g_wmma_options.push_back( option ); +} void add_double_operand( const char *d1, const char *d2 ) { //operands that access two variables. @@ -725,6 +732,28 @@ void add_4vector_operand( const char *d1, const char *d2, const char *d3, const if ( s4 == null_op ) s4 = NULL; g_operands.push_back( operand_info(s1,s2,s3,s4) ); } +void add_8vector_operand( const char *d1, const char *d2, const char *d3, const char *d4,const char *d5,const char *d6,const char *d7,const char *d8 ) +{ + PTX_PARSE_DPRINTF("add_8vector_operand"); + const symbol *s1 = g_current_symbol_table->lookup(d1); + const symbol *s2 = g_current_symbol_table->lookup(d2); + const symbol *s3 = g_current_symbol_table->lookup(d3); + const symbol *s4 = g_current_symbol_table->lookup(d4); + const symbol *s5 = g_current_symbol_table->lookup(d5); + const symbol *s6 = g_current_symbol_table->lookup(d6); + const symbol *s7 = g_current_symbol_table->lookup(d7); + const symbol *s8 = g_current_symbol_table->lookup(d8); + parse_assert( s1 != NULL && s2 != NULL && s3 != NULL && s4 != NULL && s5 !=NULL && s6 !=NULL && s7 !=NULL && s8 !=NULL, "v4 component(s) missing declarations."); + const symbol *null_op = g_current_symbol_table->lookup("_"); + if ( s2 == null_op ) s2 = NULL; + if ( s3 == null_op ) s3 = NULL; + if ( s4 == null_op ) s4 = NULL; + if ( s5 == null_op ) s5 = NULL; + if ( s6 == null_op ) s6 = NULL; + if ( s7 == null_op ) s7 = NULL; + if ( s8 == null_op ) s8 = NULL; + g_operands.push_back( operand_info(s1,s2,s3,s4,s5,s6,s7,s8) ); +} void add_builtin_operand( int builtin, int dim_modifier ) { diff --git a/src/cuda-sim/ptx_parser.h b/src/cuda-sim/ptx_parser.h index 32f3903..8094b43 100644 --- a/src/cuda-sim/ptx_parser.h +++ b/src/cuda-sim/ptx_parser.h @@ -57,7 +57,9 @@ void add_1vector_operand( const char *d1 ); void add_2vector_operand( const char *d1, const char *d2 ); void add_3vector_operand( const char *d1, const char *d2, const char *d3 ); void add_4vector_operand( const char *d1, const char *d2, const char *d3, const char *d4 ); +void add_8vector_operand( const char *d1, const char *d2, const char *d3, const char *d4 ,const char *d5,const char *d6,const char *d7,const char *d8); void add_option(int option ); +void add_wmma_option(int option ); void add_builtin_operand( int builtin, int dim_modifier ); void add_memory_operand( ); void add_literal_int( int value ); -- cgit v1.3 From 89177651e85312fbc841391121908a5e92280881 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Mon, 28 May 2018 14:40:19 -0700 Subject: better print statements for debugging stream_wait_event op --- src/stream_manager.cc | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 1b8ebb1..547e06b 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -188,16 +188,14 @@ bool stream_operation::do_operation( gpgpu_sim *gpu ) } break; case stream_event: { - if(g_debug_execution >= 3) - printf("event update\n"); + printf("event update\n"); time_t wallclock = time((time_t *)NULL); m_event->update( gpu_tot_sim_cycle, wallclock ); m_stream->record_next_done(); } break; case stream_wait_event: { - if(g_debug_execution >= 3) - printf("stream wait event\n"); + printf("stream wait event processing...\n"); if(m_event->done()) printf("stream wait event done\n"); m_stream->record_next_done(); -- cgit v1.3 From 21cce426d844c64dac5de7985b97857bb3724e88 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 29 May 2018 10:15:19 -0700 Subject: fixes seg fault on concurrentKernels, speeds up concurrent_streams_empty, adds check for null stream case on cudaStreamWaitEvent --- libcuda/cuda_runtime_api.cc | 4 ++++ src/gpgpusim_entrypoint.cc | 2 +- src/stream_manager.cc | 3 +++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index f130a37..33da17f 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1203,6 +1203,10 @@ __host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEven { CUevent_st *e = get_event(event); if( !e ) return g_last_cudaError = cudaErrorUnknown; + if (!stream){ + printf("GPGPU-Sim API: Warning: cudaStreamWaitEvent on NULL stream not currently supported.\n"); + return g_last_cudaError = cudaErrorInvalidValue; + } struct CUstream_st *s = (struct CUstream_st *)stream; stream_operation op(s,e,flags); g_stream_manager->push(op); diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index ede9f20..58d8c04 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -108,7 +108,7 @@ void *gpgpu_sim_thread_concurrent(void*) printf("GPGPU-Sim: *** simulation thread starting and spinning waiting for work ***\n"); fflush(stdout); } - while( g_stream_manager->empty() && !g_sim_done ) + while( g_stream_manager->empty_protected() && !g_sim_done ) ; if(g_debug_execution >= 3) { printf("GPGPU-Sim: ** START simulation thread (detected work) **\n"); diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 547e06b..697d6ec 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -375,6 +375,8 @@ void stream_manager::destroy_stream( CUstream_st *stream ) bool stream_manager::concurrent_streams_empty() { bool result = true; + if (m_streams.empty()) + return true; // called by gpu simulation thread std::list::iterator s; for( s=m_streams.begin(); s!=m_streams.end();++s ) { @@ -382,6 +384,7 @@ bool stream_manager::concurrent_streams_empty() if( !stream->empty() ) { //stream->print(stdout); result = false; + break; } } return result; -- cgit v1.3 From 4b19748d4b3f808d8a45039326673da8caf73186 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 29 May 2018 10:20:39 -0700 Subject: clarifying comments --- src/stream_manager.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 697d6ec..c6c17ac 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -195,6 +195,8 @@ bool stream_operation::do_operation( gpgpu_sim *gpu ) } break; case stream_wait_event: { + //only allows next op to go if event is done + //otherwise stays in the stream queue printf("stream wait event processing...\n"); if(m_event->done()) printf("stream wait event done\n"); -- cgit v1.3 From 80707e17c486f5628b280c3da7e84ba73f317157 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 29 May 2018 10:39:17 -0700 Subject: added must recordevent before waitevent call message --- libcuda/cuda_runtime_api.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 33da17f..b6fc6c8 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1202,9 +1202,12 @@ __host__ cudaError_t CUDARTAPI cudaEventRecord(cudaEvent_t event, cudaStream_t s __host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) { CUevent_st *e = get_event(event); - if( !e ) return g_last_cudaError = cudaErrorUnknown; + if( !e ){ + printf("GPGPU-Sim API: ERROR: Must call cudaEventRecord on event before calling cudaStreamWaitEvent.\n"); + return g_last_cudaError = cudaErrorInvalidValue; + } if (!stream){ - printf("GPGPU-Sim API: Warning: cudaStreamWaitEvent on NULL stream not currently supported.\n"); + printf("GPGPU-Sim API: ERROR: cudaStreamWaitEvent on NULL stream not currently supported.\n"); return g_last_cudaError = cudaErrorInvalidValue; } struct CUstream_st *s = (struct CUstream_st *)stream; -- cgit v1.3 From 99a7e032781ee2772cd86e4c1922851f101ec2c7 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 29 May 2018 11:40:51 -0700 Subject: implements null stream case on cudaStreamWaitEvent and updates warning on null event to reflect api reference --- libcuda/cuda_runtime_api.cc | 15 ++++++++------- src/stream_manager.cc | 7 +++++++ src/stream_manager.h | 1 + 3 files changed, 16 insertions(+), 7 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index b6fc6c8..dc92522 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1201,18 +1201,19 @@ __host__ cudaError_t CUDARTAPI cudaEventRecord(cudaEvent_t event, cudaStream_t s __host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) { + //reference: https://www.cs.cmu.edu/afs/cs/academic/class/15668-s11/www/cuda-doc/html/group__CUDART__STREAM_gfe68d207dc965685d92d3f03d77b0876.html CUevent_st *e = get_event(event); if( !e ){ - printf("GPGPU-Sim API: ERROR: Must call cudaEventRecord on event before calling cudaStreamWaitEvent.\n"); - return g_last_cudaError = cudaErrorInvalidValue; + printf("GPGPU-Sim API: Warning: cudaEventRecord has not been called on event before calling cudaStreamWaitEvent.\nNothing to be done.\n"); + return g_last_cudaError = cudaSuccess; } if (!stream){ - printf("GPGPU-Sim API: ERROR: cudaStreamWaitEvent on NULL stream not currently supported.\n"); - return g_last_cudaError = cudaErrorInvalidValue; + g_stream_manager->pushCudaStreamWaitEventToAllStreams(e, flags); + } else { + struct CUstream_st *s = (struct CUstream_st *)stream; + stream_operation op(s,e,flags); + g_stream_manager->push(op); } - struct CUstream_st *s = (struct CUstream_st *)stream; - stream_operation op(s,e,flags); - g_stream_manager->push(op); return g_last_cudaError = cudaSuccess; } diff --git a/src/stream_manager.cc b/src/stream_manager.cc index c6c17ac..6cd62a2 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -478,3 +478,10 @@ void stream_manager::push( stream_operation op ) } } +void stream_manager::pushCudaStreamWaitEventToAllStreams( CUevent_st *e, unsigned int flags ){ + std::list::iterator s; + for( s=m_streams.begin(); s != m_streams.end(); s++ ) { + stream_operation op(*s,e,flags); + push(op); + } +} diff --git a/src/stream_manager.h b/src/stream_manager.h index edf2b24..1719ebd 100644 --- a/src/stream_manager.h +++ b/src/stream_manager.h @@ -255,6 +255,7 @@ public: bool empty(); void print( FILE *fp); void push( stream_operation op ); + void pushCudaStreamWaitEventToAllStreams( CUevent_st *e, unsigned int flags ); bool operation(bool * sim); void stop_all_running_kernels(); private: -- cgit v1.3 From 5b1ba75a3d5d02fbc12b5218abaaae4fcf2b5c2d Mon Sep 17 00:00:00 2001 From: aamir Date: Wed, 30 May 2018 17:34:14 -0700 Subject: changes for vector operands --- src/abstract_hardware_model.h | 2 +- src/cuda-sim/cuda-sim.cc | 24 +++++++++---- src/cuda-sim/instructions.cc | 80 +++++++++++++++++++++++++++++++++---------- src/cuda-sim/ptx_ir.h | 10 +++++- 4 files changed, 88 insertions(+), 28 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 9dc58d4..e00c941 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -826,7 +826,7 @@ public: address_type reconvergence_pc; // -1 => not a branch, -2 => use function return address unsigned out[8]; - unsigned in[8]; + unsigned in[24]; unsigned char is_vectorin; unsigned char is_vectorout; int pred; // predicate register number diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 006738a..62077e6 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -852,8 +852,10 @@ void ptx_instruction::pre_decode() { pc = m_PC; isize = m_inst_size; - for( unsigned i=0; i<4; i++) { + for(unsigned i=0; i<8; i++) { out[i] = 0; + } + for(unsigned i=0; i<24; i++) { in[i] = 0; } is_vectorin = 0; @@ -922,6 +924,10 @@ void ptx_instruction::pre_decode() if( num_elem >= 2 ) out[1] = o.reg2_num(); if( num_elem >= 3 ) out[2] = o.reg3_num(); if( num_elem >= 4 ) out[3] = o.reg4_num(); + if( num_elem >= 5 ) out[4] = o.reg5_num(); + if( num_elem >= 6 ) out[5] = o.reg6_num(); + if( num_elem >= 7 ) out[6] = o.reg7_num(); + if( num_elem >= 8 ) out[7] = o.reg8_num(); for (int i = 0; i < num_elem; i++) arch_reg.dst[i] = o.arch_reg_num(i); } @@ -940,13 +946,17 @@ void ptx_instruction::pre_decode() //assert(m == 0); //only support 1 vector operand (for textures) right now is_vectorout = 1; unsigned num_elem = o.get_vect_nelem(); - if( num_elem >= 1 ) in[0] = o.reg1_num(); - if( num_elem >= 2 ) in[1] = o.reg2_num(); - if( num_elem >= 3 ) in[2] = o.reg3_num(); - if( num_elem >= 4 ) in[3] = o.reg4_num(); + if( num_elem >= 1 ) in[m+0] = o.reg1_num(); + if( num_elem >= 2 ) in[m+1] = o.reg2_num(); + if( num_elem >= 3 ) in[m+2] = o.reg3_num(); + if( num_elem >= 4 ) in[m+3] = o.reg4_num(); + if( num_elem >= 5 ) in[m+4] = o.reg5_num(); + if( num_elem >= 6 ) in[m+5] = o.reg6_num(); + if( num_elem >= 7 ) in[m+6] = o.reg7_num(); + if( num_elem >= 8 ) in[m+7] = o.reg8_num(); for (int i = 0; i < num_elem; i++) - arch_reg.src[i] = o.arch_reg_num(i); - m+=4; + arch_reg.src[m+i] = o.arch_reg_num(i); + m+=num_elem; } } } diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 7407269..446cdbf 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -748,7 +748,7 @@ void addp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) case U64_TYPE: data.s64 = src1_data.s64 + src2_data.s64 + (src3_data.pred & 0x4); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16=src1_data.f16+src2_data.f16; break;//assert(0); break; case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break; case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break; default: assert(0); break; @@ -826,7 +826,7 @@ void add_impl( const ptx_instruction *pI, ptx_thread_info *thread ) case U64_TYPE: data.u64 = src1_data.u64 + src2_data.u64; break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16=src1_data.f16+src2_data.f16; break;//assert(0); break; case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break; case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break; default: assert(0); break; @@ -1878,7 +1878,9 @@ ptx_reg_t f2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, } } else { switch ( to_width ) { - case 16: assert(0); break; + case 16: //assert(0); break; + y.f16 = x.f32; + break; case 32: assert(0); break; // handled by f2f case 64: y.f64 = x.f32; @@ -2140,7 +2142,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) case U32_TYPE: case U64_TYPE: printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16=truncf(data.f16);break;//assert(0); break; case F32_TYPE: data.f32 = truncf(data.f32); break; @@ -2163,7 +2165,13 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) case U32_TYPE: case U64_TYPE: printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE:// assert(0); break; +#if CUDART_VERSION >= 3000 + data.f16 = nearbyintf(data.f16); +#else + data.f16 = cuda_math::__cuda_nearbyintf(data.f16); +#endif + break; case F32_TYPE: #if CUDART_VERSION >= 3000 data.f32 = nearbyintf(data.f32); @@ -2186,7 +2194,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) case U32_TYPE: case U64_TYPE: printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16=floorf(data.f16);break;//assert(0); break; case F32_TYPE: data.f32 = floorf(data.f32); break; @@ -2205,7 +2213,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) case U32_TYPE: case U64_TYPE: printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16 = ceilf(data.f16); break; //assert(0); break; case F32_TYPE: data.f32 = ceilf(data.f32); break; case F64_TYPE: case FF64_TYPE: data.f64 = ceil(data.f64); break; default: assert(0); break; @@ -2246,7 +2254,10 @@ void ptx_saturate(ptx_reg_t& data, int saturation_mode, int type) case U32_TYPE: case U64_TYPE: printf("Trying to clamp an integer to 1??\n"); assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: //assert(0); break; + if (data.f16 > 1.0f) data.f16 = 1.0f; //negative + if (data.f16 < 0.0f) data.f16 = 0.0f; //positive + break; case F32_TYPE: if (data.f32 > 1.0f) data.f32 = 1.0f; //negative if (data.f32 < 0.0f) data.f32 = 0.0f; //positive @@ -2270,8 +2281,8 @@ void cvt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) unsigned rounding_mode = pI->rounding_mode(); unsigned saturation_mode = pI->saturation_mode(); - if ( to_type == F16_TYPE || from_type == F16_TYPE ) - abort(); +// if ( to_type == F16_TYPE || from_type == F16_TYPE ) +// abort(); int to_sign, from_sign; size_t from_width, to_width; @@ -2406,7 +2417,7 @@ void div_impl( const ptx_instruction *pI, ptx_thread_info *thread ) data.u32 = src1_data.u32 / src2_data.u32; break; case B64_TYPE: data.u64 = src1_data.u64 / src2_data.u64; break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16 = src1_data.f16 / src2_data.f16; break;//assert(0); break; case F32_TYPE: data.f32 = src1_data.f32 / src2_data.f32; break; case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 / src2_data.f64; break; default: assert(0); break; @@ -2744,9 +2755,24 @@ void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry if ( pI->is_lo() ) d.u64 = t.u64 + c.u64 + carry_bit.pred; else assert(0); break; - case F16_TYPE: - assert(0); - break; + case F16_TYPE:{ + // assert(0); + // break; + assert( use_carry == false); + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + d.f16 = a.f16 * b.f16 + c.f16; + if ( pI->saturation_mode() ) { + if ( d.f16 < 0 ) d.f16 = 0; + else if ( d.f16 > 1.0f ) d.f16 = 1.0f; + } + fesetround( orig_rm ); + break; + } case F32_TYPE: { assert( use_carry == false); int orig_rm = fegetround(); @@ -3046,9 +3072,25 @@ void mul_impl( const ptx_instruction *pI, ptx_thread_info *thread ) if ( pI->is_lo() ) d.u64 = t.u64; else assert(0); break; - case F16_TYPE: - assert(0); - break; + case F16_TYPE:{ + //assert(0); + //break; + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + + d.f16 = a.f16 * b.f16; + + if ( pI->saturation_mode() ) { + if ( d.f16 < 0 ) d.f16 = 0; + else if ( d.f16 > 1.0f ) d.f16 = 1.0f; + } + fesetround( orig_rm ); + break; + } case F32_TYPE: { int orig_rm = fegetround(); switch ( rounding_mode ) { @@ -3111,7 +3153,7 @@ void neg_impl( const ptx_instruction *pI, ptx_thread_info *thread ) case U32_TYPE: case U64_TYPE: assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16 =0.0f - src1_data.f16; break;//assert(0); break; case F32_TYPE: data.f32 = 0.0f - src1_data.f32; break; case F64_TYPE: case FF64_TYPE: data.f64 = 0.0f - src1_data.f64; break; default: assert(0); break; @@ -4165,7 +4207,7 @@ void sub_impl( const ptx_instruction *pI, ptx_thread_info *thread ) case B64_TYPE: case U64_TYPE: data.u64 = src1_data.u64 - src2_data.u64; break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16 = src1_data.f16 - src2_data.f16; break;//assert(0); break; case F32_TYPE: data.f32 = src1_data.f32 - src2_data.f32; break; case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 - src2_data.f64; break; default: assert(0); break; diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index ff24a66..833f175 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -656,7 +656,11 @@ public: if( !m_value.m_vector_symbolic[1] ) return 1; if( !m_value.m_vector_symbolic[2] ) return 2; if( !m_value.m_vector_symbolic[3] ) return 3; - return 4; + if( !m_value.m_vector_symbolic[4] ) return 4; + if( !m_value.m_vector_symbolic[5] ) return 5; + if( !m_value.m_vector_symbolic[6] ) return 6; + if( !m_value.m_vector_symbolic[7] ) return 7; + return 8; } const symbol* vec_symbol(int idx) const @@ -718,6 +722,10 @@ public: int reg2_num() const { return m_value.m_vector_symbolic[1]->reg_num();} int reg3_num() const { return m_value.m_vector_symbolic[2]?m_value.m_vector_symbolic[2]->reg_num():0; } int reg4_num() const { return m_value.m_vector_symbolic[3]?m_value.m_vector_symbolic[3]->reg_num():0; } + int reg5_num() const { return m_value.m_vector_symbolic[4]?m_value.m_vector_symbolic[4]->reg_num():0; } + int reg6_num() const { return m_value.m_vector_symbolic[5]?m_value.m_vector_symbolic[5]->reg_num():0; } + int reg7_num() const { return m_value.m_vector_symbolic[6]?m_value.m_vector_symbolic[6]->reg_num():0; } + int reg8_num() const { return m_value.m_vector_symbolic[7]?m_value.m_vector_symbolic[7]->reg_num():0; } int arch_reg_num() const { return m_value.m_symbolic->arch_reg_num(); } int arch_reg_num(unsigned n) const { return (m_value.m_vector_symbolic[n])? m_value.m_vector_symbolic[n]->arch_reg_num() : -1; } bool is_label() const { return m_type == label_t;} -- cgit v1.3 From fa0089a5d3a86ef348fae9a83a862f5219892bab Mon Sep 17 00:00:00 2001 From: aamir Date: Wed, 30 May 2018 23:07:44 -0700 Subject: adding code for wmma_ld_impl, error at decode space --- cuda-kernels/.tensor_core_ptx.swp | Bin 0 -> 16384 bytes cuda-kernels/Makefile | 3 +- cuda-kernels/tensor_core | Bin 48541 -> 2750968 bytes cuda-kernels/tensor_core_ptx | 171 +++++++++++ src/Makefile | 2 +- src/cuda-sim/.ptx.y.swp | Bin 0 -> 36864 bytes src/cuda-sim/Makefile | 2 +- src/cuda-sim/instructions.cc | 72 ++++- src/cuda-sim/ptx.y~ | 608 ++++++++++++++++++++++++++++++++++++++ src/cuda-sim/ptx_ir.h | 4 +- src/cuda-sim/ptx_sim.h | 9 + src/gpgpu-sim/Makefile | 2 +- src/intersim2/Makefile | 2 +- 13 files changed, 865 insertions(+), 10 deletions(-) create mode 100644 cuda-kernels/.tensor_core_ptx.swp create mode 100644 cuda-kernels/tensor_core_ptx create mode 100644 src/cuda-sim/.ptx.y.swp create mode 100644 src/cuda-sim/ptx.y~ diff --git a/cuda-kernels/.tensor_core_ptx.swp b/cuda-kernels/.tensor_core_ptx.swp new file mode 100644 index 0000000..6d7bad4 Binary files /dev/null and b/cuda-kernels/.tensor_core_ptx.swp differ diff --git a/cuda-kernels/Makefile b/cuda-kernels/Makefile index 51a7760..673460f 100755 --- a/cuda-kernels/Makefile +++ b/cuda-kernels/Makefile @@ -1,5 +1,6 @@ all: tensor_core.cu - nvcc -arch=sm_70 -lcudart -g -o tensor_core tensor_core.cu + nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o tensor_core tensor_core.cu +# nvcc -arch=sm_70 -lcudart -g -o tensor_core tensor_core.cu .PHONY: clean: diff --git a/cuda-kernels/tensor_core b/cuda-kernels/tensor_core index b25f3d9..cb53851 100755 Binary files a/cuda-kernels/tensor_core and b/cuda-kernels/tensor_core differ diff --git a/cuda-kernels/tensor_core_ptx b/cuda-kernels/tensor_core_ptx new file mode 100644 index 0000000..36074cb --- /dev/null +++ b/cuda-kernels/tensor_core_ptx @@ -0,0 +1,171 @@ +// +// Generated by NVIDIA NVVM Compiler +// +// Compiler Build ID: CL-22781540 +// Cuda compilation tools, release 9.0, V9.0.176 +// Based on LLVM 3.4svn +// + +.version 6.0 +.target sm_70 +.address_size 64 + + // .globl _Z12wmma_exampleP6__halfS0_Pfiiiff +.extern .func (.param .b32 func_retval0) vprintf +( + .param .b64 vprintf_param_0, + .param .b64 vprintf_param_1 +) +; +.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0}; + +.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff( + .param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0, + .param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1, + .param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2, + .param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3, + .param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4, + .param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5, + .param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6, + .param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7 +) +{ + .local .align 8 .b8 __local_depot0[8]; + .reg .b64 %SP; + .reg .b64 %SPL; + .reg .pred %p<6>; + .reg .f32 %f<34>; + .reg .b32 %r<38>; + .reg .b64 %rd<18>; + + + mov.u64 %rd17, __local_depot0; + cvta.local.u64 %SP, %rd17; + ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0]; + ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1]; + ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2]; + ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3]; + ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4]; + ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5]; + // inline asm + mov.u32 %r6, %clock; + // inline asm + mov.u32 %r8, %ntid.x; + mov.u32 %r9, %ctaid.x; + mov.u32 %r10, %tid.x; + mad.lo.s32 %r11, %r8, %r9, %r10; + mov.u32 %r12, WARP_SZ; + div.u32 %r13, %r11, %r12; + mov.u32 %r14, %ntid.y; + mov.u32 %r15, %ctaid.y; + mov.u32 %r16, %tid.y; + mad.lo.s32 %r17, %r14, %r15, %r16; + shl.b32 %r2, %r13, 4; + shl.b32 %r3, %r17, 4; + setp.lt.s32 %p1, %r2, %r4; + setp.gt.s32 %p2, %r5, 0; + and.pred %p3, %p1, %p2; + setp.lt.s32 %p4, %r3, %r7; + and.pred %p5, %p3, %p4; + mov.f32 %f26, 0f00000000; + mov.f32 %f27, %f26; + mov.f32 %f28, %f26; + mov.f32 %f29, %f26; + mov.f32 %f30, %f26; + mov.f32 %f31, %f26; + mov.f32 %f32, %f26; + mov.f32 %f33, %f26; + @!%p5 bra BB0_2; + bra.uni BB0_1; + +BB0_1: + mul.wide.s32 %rd4, %r2, 2; + add.s64 %rd5, %rd1, %rd4; + wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4; + mul.wide.s32 %rd6, %r3, 2; + add.s64 %rd7, %rd2, %rd6; + wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5; + mov.f32 %f25, 0f00000000; + wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25}; + +BB0_2: + add.u64 %rd8, %SP, 0; + cvta.to.local.u64 %rd9, %rd8; + mul.lo.s32 %r35, %r3, %r4; + cvt.s64.s32 %rd10, %r35; + cvt.s64.s32 %rd11, %r2; + add.s64 %rd12, %rd10, %rd11; + shl.b64 %rd13, %rd12, 2; + add.s64 %rd14, %rd3, %rd13; + wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4; + // inline asm + mov.u32 %r34, %clock; + // inline asm + sub.s32 %r36, %r34, %r6; + st.local.u32 [%rd9], %r36; + mov.u64 %rd15, $str; + cvta.global.u64 %rd16, %rd15; + // Callseq Start 0 + { + .reg .b32 temp_param_reg; + // } + .param .b64 param0; + st.param.b64 [param0+0], %rd16; + .param .b64 param1; + st.param.b64 [param1+0], %rd8; + .param .b32 retval0; + call.uni (retval0), + vprintf, + ( + param0, + param1 + ); + ld.param.b32 %r37, [retval0+0]; + + //{ + }// Callseq End 0 + ret; +} + + // .globl _Z17convertFp32ToFp16P6__halfPfi +.visible .entry _Z17convertFp32ToFp16P6__halfPfi( + .param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0, + .param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1, + .param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2 +) +{ + .reg .pred %p<2>; + .reg .b16 %rs<2>; + .reg .f32 %f<2>; + .reg .b32 %r<6>; + .reg .b64 %rd<9>; + + + ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0]; + ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1]; + ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2]; + mov.u32 %r3, %ntid.x; + mov.u32 %r4, %ctaid.x; + mov.u32 %r5, %tid.x; + mad.lo.s32 %r1, %r4, %r3, %r5; + setp.ge.s32 %p1, %r1, %r2; + @%p1 bra BB1_2; + + cvta.to.global.u64 %rd3, %rd2; + mul.wide.s32 %rd4, %r1, 4; + add.s64 %rd5, %rd3, %rd4; + ld.global.f32 %f1, [%rd5]; + // inline asm + { cvt.rn.f16.f32 %rs1, %f1;} + + // inline asm + cvta.to.global.u64 %rd6, %rd1; + mul.wide.s32 %rd7, %r1, 2; + add.s64 %rd8, %rd6, %rd7; + st.global.u16 [%rd8], %rs1; + +BB1_2: + ret; +} + + diff --git a/src/Makefile b/src/Makefile index 6001669..09194f3 100644 --- a/src/Makefile +++ b/src/Makefile @@ -46,7 +46,7 @@ ifeq ($(TRACE),1) endif ifneq ($(DEBUG),1) - OPTFLAGS += -O3 + OPTFLAGS += -O0 else CXXFLAGS += endif diff --git a/src/cuda-sim/.ptx.y.swp b/src/cuda-sim/.ptx.y.swp new file mode 100644 index 0000000..c8a83b5 Binary files /dev/null and b/src/cuda-sim/.ptx.y.swp differ diff --git a/src/cuda-sim/Makefile b/src/cuda-sim/Makefile index 999dad7..a65e8e1 100644 --- a/src/cuda-sim/Makefile +++ b/src/cuda-sim/Makefile @@ -42,7 +42,7 @@ include ../../version_detection.mk OUTPUT_DIR=$(SIM_OBJ_FILES_DIR)/cuda-sim -OPT := -O3 -g3 -Wall -Wno-unused-function -Wno-sign-compare +OPT := -O0 -g3 -Wall -Wno-unused-function -Wno-sign-compare ifeq ($(DEBUG),1) OPT := -g3 -Wall -Wno-unused-function -Wno-sign-compare endif diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 446cdbf..16f33c6 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -643,6 +643,33 @@ void ptx_thread_info::set_vector_operand_values( const operand_info &dst, m_last_set_operand_value = data1; } +void ptx_thread_info::set_wmma_vector_operand_values( const operand_info &dst, + const ptx_reg_t &data1, + const ptx_reg_t &data2, + const ptx_reg_t &data3, + const ptx_reg_t &data4, + const ptx_reg_t &data5, + const ptx_reg_t &data6, + const ptx_reg_t &data7, + const ptx_reg_t &data8 ) +{ + unsigned num_elements = dst.get_vect_nelem(); + if (num_elements > 7) { + set_reg(dst.vec_symbol(0), data1); + set_reg(dst.vec_symbol(1), data2); + set_reg(dst.vec_symbol(2), data3); + set_reg(dst.vec_symbol(3), data4); + set_reg(dst.vec_symbol(4), data5); + set_reg(dst.vec_symbol(5), data6); + set_reg(dst.vec_symbol(6), data7); + set_reg(dst.vec_symbol(7), data8); + } + else{ + printf("error:set_wmma_vector_operands"); + } + + m_last_set_operand_value = data1; +} #define my_abs(a) (((a)<0)?(-a):(a)) @@ -1493,9 +1520,6 @@ unsigned trunc(unsigned num, unsigned precision) { } return num; } -void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) -{ -} void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { } @@ -2595,6 +2619,48 @@ void ldu_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { ld_exec(pI,thread); } +void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned type = pI->get_type(); + + int tid = inst.warp_id_func() * core->get_warp_size(); + int thrd; + ptx_thread_info *thread; + thread = core->get_thread_info()[tid]; + + ptx_reg_t src1_data = thread->get_operand_value(src1, dst, type, thread, 1); + + ptx_reg_t data; + memory_space_t space = pI->get_space(); + + memory_space *mem = NULL; + addr_t addr = src1_data.u32; + + decode_space(space,thread,src1,mem,addr); + + size_t size; + int t; + data.u64=0; + type_info_key::type_decode(type,size,t); + ptx_reg_t data1, data2, data3, data4; + ptx_reg_t data5, data6, data7, data8; + mem->read(addr,size/8,&data1.s64); + mem->read(addr+size/8,size/8,&data2.s64); + mem->read(addr+2*size/8,size/8,&data3.s64); + mem->read(addr+3*size/8,size/8,&data4.s64); + mem->read(addr+4*size/8,size/8,&data5.s64); + mem->read(addr+5*size/8,size/8,&data6.s64); + mem->read(addr+6*size/8,size/8,&data7.s64); + mem->read(addr+7*size/8,size/8,&data8.s64); + thread->set_wmma_vector_operand_values(dst,data1,data2,data3,data4,data5,data6,data7,data8); + + thread->m_last_effective_address = addr; + thread->m_last_memory_space = space; +} void lg2_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { diff --git a/src/cuda-sim/ptx.y~ b/src/cuda-sim/ptx.y~ new file mode 100644 index 0000000..0710ecd --- /dev/null +++ b/src/cuda-sim/ptx.y~ @@ -0,0 +1,608 @@ +/* +Copyright (c) 2009-2011, Tor M. Aamodt +The University of British Columbia +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. +Redistributions in binary form must reproduce the above copyright notice, this +list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. +Neither the name of The University of British Columbia nor the names of its +contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +%union { + double double_value; + float float_value; + int int_value; + char * string_value; + void * ptr_value; +} + +%token STRING +%token OPCODE +%token WMMA_DIRECTIVE +%token LAYOUT +%token CONFIGURATION +%token ALIGN_DIRECTIVE +%token BRANCHTARGETS_DIRECTIVE +%token BYTE_DIRECTIVE +%token CALLPROTOTYPE_DIRECTIVE +%token CALLTARGETS_DIRECTIVE +%token CONST_DIRECTIVE +%token CONSTPTR_DIRECTIVE +%token PTR_DIRECTIVE +%token ENTRY_DIRECTIVE +%token EXTERN_DIRECTIVE +%token WEAK_DIRECTIVE +%token FILE_DIRECTIVE +%token FUNC_DIRECTIVE +%token GLOBAL_DIRECTIVE +%token LOCAL_DIRECTIVE +%token LOC_DIRECTIVE +%token MAXNCTAPERSM_DIRECTIVE +%token MAXNNREG_DIRECTIVE +%token MAXNTID_DIRECTIVE +%token MINNCTAPERSM_DIRECTIVE +%token PARAM_DIRECTIVE +%token PRAGMA_DIRECTIVE +%token REG_DIRECTIVE +%token REQNTID_DIRECTIVE +%token SECTION_DIRECTIVE +%token SHARED_DIRECTIVE +%token SREG_DIRECTIVE +%token SSTARR_DIRECTIVE +%token STRUCT_DIRECTIVE +%token SURF_DIRECTIVE +%token TARGET_DIRECTIVE +%token TEX_DIRECTIVE +%token UNION_DIRECTIVE +%token VERSION_DIRECTIVE +%token ADDRESS_SIZE_DIRECTIVE +%token VISIBLE_DIRECTIVE +%token WEAK_DIRECTIVE +%token IDENTIFIER +%token INT_OPERAND +%token FLOAT_OPERAND +%token DOUBLE_OPERAND +%token S8_TYPE +%token S16_TYPE +%token S32_TYPE +%token S64_TYPE +%token U8_TYPE +%token U16_TYPE +%token U32_TYPE +%token U64_TYPE +%token F16_TYPE +%token F32_TYPE +%token F64_TYPE +%token FF64_TYPE +%token B8_TYPE +%token B16_TYPE +%token B32_TYPE +%token B64_TYPE +%token BB64_TYPE +%token BB128_TYPE +%token PRED_TYPE +%token TEXREF_TYPE +%token SAMPLERREF_TYPE +%token SURFREF_TYPE +%token V2_TYPE +%token V3_TYPE +%token V4_TYPE +%token COMMA +%token PRED +%token HALF_OPTION +%token EXTP_OPTION +%token EQ_OPTION +%token NE_OPTION +%token LT_OPTION +%token LE_OPTION +%token GT_OPTION +%token GE_OPTION +%token LO_OPTION +%token LS_OPTION +%token HI_OPTION +%token HS_OPTION +%token EQU_OPTION +%token NEU_OPTION +%token LTU_OPTION +%token LEU_OPTION +%token GTU_OPTION +%token GEU_OPTION +%token NUM_OPTION +%token NAN_OPTION +%token CF_OPTION +%token SF_OPTION +%token NSF_OPTION +%token LEFT_SQUARE_BRACKET +%token RIGHT_SQUARE_BRACKET +%token WIDE_OPTION +%token SPECIAL_REGISTER +%token MINUS +%token PLUS +%token COLON +%token SEMI_COLON +%token EXCLAMATION +%token PIPE +%token RIGHT_BRACE +%token LEFT_BRACE +%token EQUALS +%token PERIOD +%token BACKSLASH +%token DIMENSION_MODIFIER +%token RN_OPTION +%token RZ_OPTION +%token RM_OPTION +%token RP_OPTION +%token RNI_OPTION +%token RZI_OPTION +%token RMI_OPTION +%token RPI_OPTION +%token UNI_OPTION +%token GEOM_MODIFIER_1D +%token GEOM_MODIFIER_2D +%token GEOM_MODIFIER_3D +%token SAT_OPTION +%token FTZ_OPTION +%token NEG_OPTION +%token SYNC_OPTION +%token RED_OPTION +%token ARRIVE_OPTION +%token ATOMIC_POPC +%token ATOMIC_AND +%token ATOMIC_OR +%token ATOMIC_XOR +%token ATOMIC_CAS +%token ATOMIC_EXCH +%token ATOMIC_ADD +%token ATOMIC_INC +%token ATOMIC_DEC +%token ATOMIC_MIN +%token ATOMIC_MAX +%token LEFT_ANGLE_BRACKET +%token RIGHT_ANGLE_BRACKET +%token LEFT_PAREN +%token RIGHT_PAREN +%token APPROX_OPTION +%token FULL_OPTION +%token ANY_OPTION +%token ALL_OPTION +%token BALLOT_OPTION +%token GLOBAL_OPTION +%token CTA_OPTION +%token SYS_OPTION +%token EXIT_OPTION +%token ABS_OPTION +%token TO_OPTION +%token CA_OPTION; +%token CG_OPTION; +%token CS_OPTION; +%token LU_OPTION; +%token CV_OPTION; +%token WB_OPTION; +%token WT_OPTION; +%token NC_OPTION; +%token UP_OPTION; +%token DOWN_OPTION; +%token BFLY_OPTION; +%token IDX_OPTION; + +%type function_decl_header +%type function_decl + +%{ + #include "ptx_parser.h" + #include + #include + #include + void syntax_not_implemented(); + extern int g_func_decl; + int ptx_lex(void); + int ptx_error(const char *); +%} + +%% + +input: /* empty */ + | input directive_statement + | input function_defn + | input function_decl + ; + +function_defn: function_decl { set_symtab($1); func_header(".skip"); } statement_block { end_function(); } + | function_decl { set_symtab($1); } block_spec_list { func_header(".skip"); } statement_block { end_function(); } + ; + +block_spec: MAXNTID_DIRECTIVE INT_OPERAND COMMA INT_OPERAND COMMA INT_OPERAND {func_header_info_int(".maxntid", $2); + func_header_info_int(",", $4); + func_header_info_int(",", $6); } + | MINNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".minnctapersm", $2); printf("GPGPU-Sim: Warning: .minnctapersm ignored. \n"); } + | MAXNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".maxnctapersm", $2); printf("GPGPU-Sim: Warning: .maxnctapersm ignored. \n"); } + ; + +block_spec_list: block_spec + | block_spec_list block_spec + ; + +function_decl: function_decl_header LEFT_PAREN { start_function($1); func_header_info("(");} param_entry RIGHT_PAREN {func_header_info(")");} function_ident_param { $$ = reset_symtab(); } + | function_decl_header { start_function($1); } function_ident_param { $$ = reset_symtab(); } + | function_decl_header { start_function($1); add_function_name(""); g_func_decl=0; $$ = reset_symtab(); } + ; + +function_ident_param: IDENTIFIER { add_function_name($1); } LEFT_PAREN {func_header_info("(");} param_list RIGHT_PAREN { g_func_decl=0; func_header_info(")"); } + | IDENTIFIER { add_function_name($1); g_func_decl=0; } + ; + +function_decl_header: ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } + | VISIBLE_DIRECTIVE ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } + | WEAK_DIRECTIVE ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } + | FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } + | VISIBLE_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } + | WEAK_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } + | EXTERN_DIRECTIVE FUNC_DIRECTIVE { $$ = 2; g_func_decl=1; func_header(".func"); } + | WEAK_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } + ; + +param_list: /*empty*/ + | param_entry { add_directive(); } + | param_list COMMA {func_header_info(",");} param_entry { add_directive(); } + +param_entry: PARAM_DIRECTIVE { add_space_spec(param_space_unclassified,0); } variable_spec ptr_spec identifier_spec { add_function_arg(); } + | REG_DIRECTIVE { add_space_spec(reg_space,0); } variable_spec identifier_spec { add_function_arg(); } + +ptr_spec: /*empty*/ + | PTR_DIRECTIVE ptr_space_spec ptr_align_spec + | PTR_DIRECTIVE ptr_align_spec + +ptr_space_spec: GLOBAL_DIRECTIVE { add_ptr_spec(global_space); } + | LOCAL_DIRECTIVE { add_ptr_spec(local_space); } + | SHARED_DIRECTIVE { add_ptr_spec(shared_space); } + +ptr_align_spec: ALIGN_DIRECTIVE INT_OPERAND + +statement_block: LEFT_BRACE statement_list RIGHT_BRACE + +statement_list: directive_statement { add_directive(); } + | instruction_statement { add_instruction(); } + | statement_list directive_statement { add_directive(); } + | statement_list instruction_statement { add_instruction(); } + | statement_list {start_inst_group();} statement_block {end_inst_group();} + | {start_inst_group();} statement_block {end_inst_group();} + ; + +directive_statement: variable_declaration SEMI_COLON + | VERSION_DIRECTIVE DOUBLE_OPERAND { add_version_info($2, 0); } + | VERSION_DIRECTIVE DOUBLE_OPERAND PLUS { add_version_info($2,1); } + | ADDRESS_SIZE_DIRECTIVE INT_OPERAND {/*Do nothing*/} + | TARGET_DIRECTIVE IDENTIFIER COMMA IDENTIFIER { target_header2($2,$4); } + | TARGET_DIRECTIVE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER { target_header3($2,$4,$6); } + | TARGET_DIRECTIVE IDENTIFIER { target_header($2); } + | FILE_DIRECTIVE INT_OPERAND STRING { add_file($2,$3); } + | FILE_DIRECTIVE INT_OPERAND STRING COMMA INT_OPERAND COMMA INT_OPERAND { add_file($2,$3); } + | LOC_DIRECTIVE INT_OPERAND INT_OPERAND INT_OPERAND + | PRAGMA_DIRECTIVE STRING SEMI_COLON { add_pragma($2); } + | function_decl SEMI_COLON {/*Do nothing*/} + ; + +variable_declaration: variable_spec identifier_list { add_variables(); } + | variable_spec identifier_spec EQUALS initializer_list { add_variables(); } + | variable_spec identifier_spec EQUALS literal_operand { add_variables(); } + | CONSTPTR_DIRECTIVE IDENTIFIER COMMA IDENTIFIER COMMA INT_OPERAND { add_constptr($2, $4, $6); } + ; + +variable_spec: var_spec_list { set_variable_type(); } + +identifier_list: identifier_spec + | identifier_list COMMA identifier_spec; + +identifier_spec: IDENTIFIER { add_identifier($1,0,NON_ARRAY_IDENTIFIER); func_header_info($1);} + | IDENTIFIER LEFT_ANGLE_BRACKET INT_OPERAND RIGHT_ANGLE_BRACKET { func_header_info($1); func_header_info_int("<", $3); func_header_info(">"); + int i,lbase,l; + char *id = NULL; + lbase = strlen($1); + for( i=0; i < $3; i++ ) { + l = lbase + (int)log10(i+1)+10; + id = (char*) malloc(l); + snprintf(id,l,"%s%u",$1,i); + add_identifier(id,0,NON_ARRAY_IDENTIFIER); + } + free($1); + } + | IDENTIFIER LEFT_SQUARE_BRACKET RIGHT_SQUARE_BRACKET { add_identifier($1,0,ARRAY_IDENTIFIER_NO_DIM); func_header_info($1); func_header_info("["); func_header_info("]");} + | IDENTIFIER LEFT_SQUARE_BRACKET INT_OPERAND RIGHT_SQUARE_BRACKET { add_identifier($1,$3,ARRAY_IDENTIFIER); func_header_info($1); func_header_info_int("[",$3); func_header_info("]");} + ; + +var_spec_list: var_spec + | var_spec_list var_spec; + +var_spec: space_spec + | type_spec + | align_spec + | EXTERN_DIRECTIVE { add_extern_spec(); } + | WEAK_DIRECTIVE + ; + +align_spec: ALIGN_DIRECTIVE INT_OPERAND { add_alignment_spec($2); } + +space_spec: REG_DIRECTIVE { add_space_spec(reg_space,0); } + | SREG_DIRECTIVE { add_space_spec(reg_space,0); } + | addressable_spec + ; + +addressable_spec: CONST_DIRECTIVE { add_space_spec(const_space,$1); } + | GLOBAL_DIRECTIVE { add_space_spec(global_space,0); } + | LOCAL_DIRECTIVE { add_space_spec(local_space,0); } + | PARAM_DIRECTIVE { add_space_spec(param_space_unclassified,0); } + | SHARED_DIRECTIVE { add_space_spec(shared_space,0); } + | SSTARR_DIRECTIVE { add_space_spec(sstarr_space,0); } + | SURF_DIRECTIVE { add_space_spec(surf_space,0); } + | TEX_DIRECTIVE { add_space_spec(tex_space,0); } + ; + +type_spec: scalar_type + | vector_spec scalar_type + ; + +vector_spec: V2_TYPE { add_option(V2_TYPE); func_header_info(".v2");} + | V3_TYPE { add_option(V3_TYPE); func_header_info(".v3");} + | V4_TYPE { add_option(V4_TYPE); func_header_info(".v4");} + ; + +scalar_type: S8_TYPE { add_scalar_type_spec( S8_TYPE ); } + | S16_TYPE { add_scalar_type_spec( S16_TYPE ); } + | S32_TYPE { add_scalar_type_spec( S32_TYPE ); } + | S64_TYPE { add_scalar_type_spec( S64_TYPE ); } + | U8_TYPE { add_scalar_type_spec( U8_TYPE ); } + | U16_TYPE { add_scalar_type_spec( U16_TYPE ); } + | U32_TYPE { add_scalar_type_spec( U32_TYPE ); } + | U64_TYPE { add_scalar_type_spec( U64_TYPE ); } + | F16_TYPE { add_scalar_type_spec( F16_TYPE ); } + | F32_TYPE { add_scalar_type_spec( F32_TYPE ); } + | F64_TYPE { add_scalar_type_spec( F64_TYPE ); } + | FF64_TYPE { add_scalar_type_spec( FF64_TYPE ); } + | B8_TYPE { add_scalar_type_spec( B8_TYPE ); } + | B16_TYPE { add_scalar_type_spec( B16_TYPE ); } + | B32_TYPE { add_scalar_type_spec( B32_TYPE ); } + | B64_TYPE { add_scalar_type_spec( B64_TYPE ); } + | BB64_TYPE { add_scalar_type_spec( BB64_TYPE ); } + | BB128_TYPE { add_scalar_type_spec( BB128_TYPE ); } + | PRED_TYPE { add_scalar_type_spec( PRED_TYPE ); } + | TEXREF_TYPE { add_scalar_type_spec( TEXREF_TYPE ); } + | SAMPLERREF_TYPE { add_scalar_type_spec( SAMPLERREF_TYPE ); } + | SURFREF_TYPE { add_scalar_type_spec( SURFREF_TYPE ); } + ; + +initializer_list: LEFT_BRACE literal_list RIGHT_BRACE { add_array_initializer(); } + | LEFT_BRACE initializer_list RIGHT_BRACE { syntax_not_implemented(); } + +literal_list: literal_operand + | literal_list COMMA literal_operand; + +instruction_statement: instruction SEMI_COLON + | IDENTIFIER COLON { add_label($1); } + | pred_spec instruction SEMI_COLON; + +instruction: opcode_spec LEFT_PAREN operand RIGHT_PAREN { set_return(); } COMMA operand COMMA LEFT_PAREN operand_list RIGHT_PAREN + | opcode_spec operand COMMA LEFT_PAREN operand_list RIGHT_PAREN + | opcode_spec operand COMMA LEFT_PAREN RIGHT_PAREN + | opcode_spec operand_list + | opcode_spec + ; + +opcode_spec: OPCODE { add_opcode($1); } option_list + | OPCODE { add_opcode($1); } + +pred_spec: PRED IDENTIFIER { add_pred($2,0, -1); } + | PRED EXCLAMATION IDENTIFIER { add_pred($3,1, -1); } + | PRED IDENTIFIER LT_OPTION { add_pred($2,0,1); } + | PRED IDENTIFIER EQ_OPTION { add_pred($2,0,2); } + | PRED IDENTIFIER LE_OPTION { add_pred($2,0,3); } + | PRED IDENTIFIER NE_OPTION { add_pred($2,0,5); } + | PRED IDENTIFIER GE_OPTION { add_pred($2,0,6); } + | PRED IDENTIFIER EQU_OPTION { add_pred($2,0,10); } + | PRED IDENTIFIER GTU_OPTION { add_pred($2,0,12); } + | PRED IDENTIFIER NEU_OPTION { add_pred($2,0,13); } + | PRED IDENTIFIER CF_OPTION { add_pred($2,0,17); } + | PRED IDENTIFIER SF_OPTION { add_pred($2,0,19); } + | PRED IDENTIFIER NSF_OPTION { add_pred($2,0,28); } + ; + +option_list: option + | option option_list ; + +option: type_spec + | compare_spec + | addressable_spec + | rounding_mode + | wmma_spec + | SYNC_OPTION { add_option(SYNC_OPTION); } + | ARRIVE_OPTION { add_option(ARRIVE_OPTION); } + | RED_OPTION { add_option(RED_OPTION); } + | UNI_OPTION { add_option(UNI_OPTION); } + | WIDE_OPTION { add_option(WIDE_OPTION); } + | ANY_OPTION { add_option(ANY_OPTION); } + | ALL_OPTION { add_option(ALL_OPTION); } + | BALLOT_OPTION { add_option(BALLOT_OPTION); } + | GLOBAL_OPTION { add_option(GLOBAL_OPTION); } + | CTA_OPTION { add_option(CTA_OPTION); } + | SYS_OPTION { add_option(SYS_OPTION); } + | GEOM_MODIFIER_1D { add_option(GEOM_MODIFIER_1D); } + | GEOM_MODIFIER_2D { add_option(GEOM_MODIFIER_2D); } + | GEOM_MODIFIER_3D { add_option(GEOM_MODIFIER_3D); } + | SAT_OPTION { add_option(SAT_OPTION); } + | FTZ_OPTION { add_option(FTZ_OPTION); } + | NEG_OPTION { add_option(NEG_OPTION); } + | APPROX_OPTION { add_option(APPROX_OPTION); } + | FULL_OPTION { add_option(FULL_OPTION); } + | EXIT_OPTION { add_option(EXIT_OPTION); } + | ABS_OPTION { add_option(ABS_OPTION); } + | atomic_operation_spec ; + | TO_OPTION { add_option(TO_OPTION); } + | HALF_OPTION { add_option(HALF_OPTION); } + | EXTP_OPTION { add_option(EXTP_OPTION); } + | CA_OPTION { add_option(CA_OPTION); } + | CG_OPTION { add_option(CG_OPTION); } + | CS_OPTION { add_option(CS_OPTION); } + | LU_OPTION { add_option(LU_OPTION); } + | CV_OPTION { add_option(CV_OPTION); } + | WB_OPTION { add_option(WB_OPTION); } + | WT_OPTION { add_option(WT_OPTION); } + | NC_OPTION { add_option(NC_OPTION); } + | UP_OPTION { add_option(UP_OPTION); } + | DOWN_OPTION { add_option(DOWN_OPTION); } + | BFLY_OPTION { add_option(BFLY_OPTION); } + | IDX_OPTION { add_option(IDX_OPTION); } + ; + +atomic_operation_spec: ATOMIC_AND { add_option(ATOMIC_AND); } + | ATOMIC_POPC { add_option(ATOMIC_POPC); } + | ATOMIC_OR { add_option(ATOMIC_OR); } + | ATOMIC_XOR { add_option(ATOMIC_XOR); } + | ATOMIC_CAS { add_option(ATOMIC_CAS); } + | ATOMIC_EXCH { add_option(ATOMIC_EXCH); } + | ATOMIC_ADD { add_option(ATOMIC_ADD); } + | ATOMIC_INC { add_option(ATOMIC_INC); } + | ATOMIC_DEC { add_option(ATOMIC_DEC); } + | ATOMIC_MIN { add_option(ATOMIC_MIN); } + | ATOMIC_MAX { add_option(ATOMIC_MAX); } + ; + +rounding_mode: floating_point_rounding_mode + | integer_rounding_mode; + + +floating_point_rounding_mode: RN_OPTION { add_option(RN_OPTION); } + | RZ_OPTION { add_option(RZ_OPTION); } + | RM_OPTION { add_option(RM_OPTION); } + | RP_OPTION { add_option(RP_OPTION); } + ; + +integer_rounding_mode: RNI_OPTION { add_option(RNI_OPTION); } + | RZI_OPTION { add_option(RZI_OPTION); } + | RMI_OPTION { add_option(RMI_OPTION); } + | RPI_OPTION { add_option(RPI_OPTION); } + ; + +compare_spec:EQ_OPTION { add_option(EQ_OPTION); } + | NE_OPTION { add_option(NE_OPTION); } + | LT_OPTION { add_option(LT_OPTION); } + | LE_OPTION { add_option(LE_OPTION); } + | GT_OPTION { add_option(GT_OPTION); } + | GE_OPTION { add_option(GE_OPTION); } + | LO_OPTION { add_option(LO_OPTION); } + | LS_OPTION { add_option(LS_OPTION); } + | HI_OPTION { add_option(HI_OPTION); } + | HS_OPTION { add_option(HS_OPTION); } + | EQU_OPTION { add_option(EQU_OPTION); } + | NEU_OPTION { add_option(NEU_OPTION); } + | LTU_OPTION { add_option(LTU_OPTION); } + | LEU_OPTION { add_option(LEU_OPTION); } + | GTU_OPTION { add_option(GTU_OPTION); } + | GEU_OPTION { add_option(GEU_OPTION); } + | NUM_OPTION { add_option(NUM_OPTION); } + | NAN_OPTION { add_option(NAN_OPTION); } + ; + +wmma_spec: WMMA_DIRECTIVE LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2);add_wmma_option($3);} + | WMMA_DIRECTIVE LAYOUT LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2),add_wmma_option($3),add_wmma_option($4)} + | WMMA_DIRECTIVE LAYOUT CONFIGURATION ptr_space_spec{add_wmma_option($1);add_wmma_option($2),add_wmma_option($3),add_wmma_option($4)} + | WMMA_DIRECTIVE LAYOUT LAYOUT CONFIGURATION ptr_space_spec{add_wmma_option($1);add_wmma_option($2),add_wmma_option($3),add_wmma_option($4)} + ; + +operand_list: operand + | operand COMMA operand_list; + +operand: IDENTIFIER { add_scalar_operand( $1 ); } + | EXCLAMATION IDENTIFIER { add_neg_pred_operand( $2 ); } + | MINUS IDENTIFIER { add_scalar_operand( $2 ); change_operand_neg(); } + | memory_operand + | literal_operand + | builtin_operand + | vector_operand + | MINUS vector_operand { change_operand_neg(); } + | tex_operand + | IDENTIFIER PLUS INT_OPERAND { add_address_operand($1,$3); } + | IDENTIFIER LO_OPTION { add_scalar_operand( $1 ); change_operand_lohi(1);} + | MINUS IDENTIFIER LO_OPTION { add_scalar_operand( $2 ); change_operand_lohi(1); change_operand_neg();} + | IDENTIFIER HI_OPTION { add_scalar_operand( $1 ); change_operand_lohi(2);} + | MINUS IDENTIFIER HI_OPTION { add_scalar_operand( $2 ); change_operand_lohi(2); change_operand_neg();} + | IDENTIFIER PIPE IDENTIFIER { add_2vector_operand($1,$3); change_double_operand_type(-1);} + | IDENTIFIER PIPE IDENTIFIER LO_OPTION { add_2vector_operand($1,$3); change_double_operand_type(-1); change_operand_lohi(1);} + | IDENTIFIER PIPE IDENTIFIER HI_OPTION { add_2vector_operand($1,$3); change_double_operand_type(-1); change_operand_lohi(2);} + | IDENTIFIER BACKSLASH IDENTIFIER { add_2vector_operand($1,$3); change_double_operand_type(-3);} + | IDENTIFIER BACKSLASH IDENTIFIER LO_OPTION { add_2vector_operand($1,$3); change_double_operand_type(-3); change_operand_lohi(1);} + | IDENTIFIER BACKSLASH IDENTIFIER HI_OPTION { add_2vector_operand($1,$3); change_double_operand_type(-3); change_operand_lohi(2);} + ; + +vector_operand: LEFT_BRACE IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_2vector_operand($2,$4); } + | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_3vector_operand($2,$4,$6); } + | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_4vector_operand($2,$4,$6,$8); } + | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_8vector_operand($2,$4,$6,$8,$10,$12,$14,$16); } + | LEFT_BRACE IDENTIFIER RIGHT_BRACE { add_1vector_operand($2); } + ; + +tex_operand: LEFT_SQUARE_BRACKET IDENTIFIER COMMA { add_scalar_operand($2); } + vector_operand + RIGHT_SQUARE_BRACKET + ; + +builtin_operand: SPECIAL_REGISTER DIMENSION_MODIFIER { add_builtin_operand($1,$2); } + | SPECIAL_REGISTER { add_builtin_operand($1,-1); } + ; + +memory_operand : LEFT_SQUARE_BRACKET address_expression RIGHT_SQUARE_BRACKET { add_memory_operand(); } + | IDENTIFIER LEFT_SQUARE_BRACKET address_expression RIGHT_SQUARE_BRACKET { add_memory_operand(); change_memory_addr_space($1); } + | IDENTIFIER LEFT_SQUARE_BRACKET literal_operand RIGHT_SQUARE_BRACKET { change_memory_addr_space($1); } + | IDENTIFIER LEFT_SQUARE_BRACKET twin_operand RIGHT_SQUARE_BRACKET { change_memory_addr_space($1); add_memory_operand();} + | MINUS memory_operand { change_operand_neg(); } + ; + +twin_operand : IDENTIFIER PLUS IDENTIFIER { add_double_operand($1,$3); change_double_operand_type(1); } + | IDENTIFIER PLUS IDENTIFIER LO_OPTION { add_double_operand($1,$3); change_double_operand_type(1); change_operand_lohi(1); } + | IDENTIFIER PLUS IDENTIFIER HI_OPTION { add_double_operand($1,$3); change_double_operand_type(1); change_operand_lohi(2); } + | IDENTIFIER PLUS EQUALS IDENTIFIER { add_double_operand($1,$4); change_double_operand_type(2); } + | IDENTIFIER PLUS EQUALS IDENTIFIER LO_OPTION { add_double_operand($1,$4); change_double_operand_type(2); change_operand_lohi(1); } + | IDENTIFIER PLUS EQUALS IDENTIFIER HI_OPTION { add_double_operand($1,$4); change_double_operand_type(2); change_operand_lohi(2); } + | IDENTIFIER PLUS EQUALS INT_OPERAND { add_address_operand($1,$4); change_double_operand_type(3); } + ; + +literal_operand : INT_OPERAND { add_literal_int($1); } + | FLOAT_OPERAND { add_literal_float($1); } + | DOUBLE_OPERAND { add_literal_double($1); } + ; + +address_expression: IDENTIFIER { add_address_operand($1,0); } + | IDENTIFIER LO_OPTION { add_address_operand($1,0); change_operand_lohi(1);} + | IDENTIFIER HI_OPTION { add_address_operand($1,0); change_operand_lohi(2); } + | IDENTIFIER PLUS INT_OPERAND { add_address_operand($1,$3); } + | INT_OPERAND { add_address_operand2($1); } + ; + +%% + +extern int ptx_lineno; +extern const char *g_filename; + +void syntax_not_implemented() +{ + printf("Parse error (%s:%u): this syntax is not (yet) implemented:\n",g_filename,ptx_lineno); + ptx_error(NULL); + abort(); +} diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 833f175..16cc975 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1078,7 +1078,7 @@ public: int membar_level() const { return m_membar_level; } bool has_memory_read() const { - if( m_opcode == LD_OP || m_opcode == LDU_OP || m_opcode == TEX_OP ) + if( m_opcode == LD_OP || m_opcode == LDU_OP || m_opcode == TEX_OP|| m_opcode==MMA_LD_OP) return true; // Check PTXPlus operand type below // Source operands are memory operands @@ -1090,7 +1090,7 @@ public: return false; } bool has_memory_write() const { - if( m_opcode == ST_OP ) return true; + if( m_opcode == ST_OP || m_opcode==MMA_ST_OP ) return true; // Check PTXPlus operand type below // Destination operand is a memory operand ptx_instruction::const_iterator op=op_iter_begin(); diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index 05acf20..403ce5b 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -303,6 +303,15 @@ public: const ptx_reg_t &data2, const ptx_reg_t &data3, const ptx_reg_t &data4 ); + void set_wmma_vector_operand_values( const operand_info &dst, + const ptx_reg_t &data1, + const ptx_reg_t &data2, + const ptx_reg_t &data3, + const ptx_reg_t &data4, + const ptx_reg_t &data5, + const ptx_reg_t &data6, + const ptx_reg_t &data7, + const ptx_reg_t &data8 ); function_info *func_info() { diff --git a/src/gpgpu-sim/Makefile b/src/gpgpu-sim/Makefile index f10a8a4..4f77699 100644 --- a/src/gpgpu-sim/Makefile +++ b/src/gpgpu-sim/Makefile @@ -48,7 +48,7 @@ ifeq ($(GNUC_CPP0X), 1) endif ifneq ($(DEBUG),1) - OPTFLAGS += -O3 + OPTFLAGS += -O0 else CXXFLAGS += endif diff --git a/src/intersim2/Makefile b/src/intersim2/Makefile index bd42000..4ef21ac 100644 --- a/src/intersim2/Makefile +++ b/src/intersim2/Makefile @@ -44,7 +44,7 @@ endif CPPFLAGS += -Wall $(INCPATH) $(DEFINE) ifneq ($(DEBUG),1) -CPPFLAGS += -O3 +CPPFLAGS += -O0 endif CPPFLAGS += -g CPPFLAGS += -fPIC -- cgit v1.3 From 29b566108f2304e42e12ba5ab1d9e7f45117bd83 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Wed, 30 May 2018 23:11:25 -0700 Subject: allows _1.ptx generation without cuobjdump_complete_output generation --- libcuda/cuda_runtime_api.cc | 130 ++++++++++++++++++++++++-------------------- 1 file changed, 70 insertions(+), 60 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index dc92522..fcb0808 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1611,61 +1611,70 @@ void extract_code_using_cuobjdump(){ printf("Parsing skipped for %s\n", fname); } - if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ - //Experimental library support - //Currently only for cufft - - std::stringstream cmd; - cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; - int result = system(cmd.str().c_str()); - if(result){ - std::cout << "Failed to execute: " << cmd.str() << std::endl; - exit(1); - } - std::ifstream libsf; - libsf.open("_tempfile_.txt"); - if(!libsf.is_open()) { - std::cout << "Failed to open: _tempfile_.txt" << std::endl; - exit(1); - } - - //Save the original section list - std::list tmpsl = cuobjdumpSectionList; - cuobjdumpSectionList.clear(); - - std::string line; - std::getline(libsf, line); - std::cout << "DOING: " << line << std::endl; - int cnt=1; - while(libsf.good()){ - std::stringstream libcodfn; - libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; - cmd.str(""); //resetting - cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; - cmd << line; - cmd << " > "; - cmd << libcodfn.str(); - std::cout << "Running cuobjdump on " << line << std::endl; - std::cout << "Using command: " << cmd.str() << std::endl; - result = system(cmd.str().c_str()); - if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} - std::cout << "Done" << std::endl; - - std::cout << "Trying to parse " << libcodfn.str() << std::endl; - cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); - cuobjdump_parse(); - fclose(cuobjdump_in); - std::getline(libsf, line); - } - libSectionList = cuobjdumpSectionList; - - //Restore the original section list - cuobjdumpSectionList = tmpsl; - } } else { printf("GPGPU-Sim PTX: overriding cuobjdump with '%s' (CUOBJDUMP_SIM_FILE is set)\n", override_cuobjdump); snprintf(fname,1024, "%s",override_cuobjdump); + + printf("Parsing file %s\n", override_cuobjdump); + cuobjdump_in = fopen(override_cuobjdump, "r"); + + cuobjdump_parse(); + fclose(cuobjdump_in); + printf("Done parsing!!!\n"); } + + if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ + //Experimental library support + //Currently only for cufft + + std::stringstream cmd; + cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; + int result = system(cmd.str().c_str()); + if(result){ + std::cout << "Failed to execute: " << cmd.str() << std::endl; + exit(1); + } + std::ifstream libsf; + libsf.open("_tempfile_.txt"); + if(!libsf.is_open()) { + std::cout << "Failed to open: _tempfile_.txt" << std::endl; + exit(1); + } + + //Save the original section list + std::list tmpsl = cuobjdumpSectionList; + cuobjdumpSectionList.clear(); + + std::string line; + std::getline(libsf, line); + std::cout << "DOING: " << line << std::endl; + int cnt=1; + while(libsf.good()){ + std::stringstream libcodfn; + libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; + cmd.str(""); //resetting + cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; + cmd << line; + cmd << " > "; + cmd << libcodfn.str(); + std::cout << "Running cuobjdump on " << line << std::endl; + std::cout << "Using command: " << cmd.str() << std::endl; + result = system(cmd.str().c_str()); + if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} + std::cout << "Done" << std::endl; + + std::cout << "Trying to parse " << libcodfn.str() << std::endl; + cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); + cuobjdump_parse(); + fclose(cuobjdump_in); + std::getline(libsf, line); + } + libSectionList = cuobjdumpSectionList; + + //Restore the original section list + cuobjdumpSectionList = tmpsl; + } + } //! Read file into char* @@ -1898,10 +1907,10 @@ void cuobjdumpInit(){ CUctx_st *context = GPGPUSim_Context(); extract_code_using_cuobjdump(); //extract all the output of cuobjdump to _cuobjdump_*.* const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); - if (pre_load ==NULL || strlen(pre_load)==0){ + //if (pre_load ==NULL || strlen(pre_load)==0){ cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); cuobjdumpSectionList = mergeSections(cuobjdumpSectionList); - } + //} } std::map fatbinmap; @@ -1939,17 +1948,18 @@ void cuobjdumpParseBinary(unsigned int handle){ cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); - if(pre_load==NULL || strlen(pre_load)==0) + //if(pre_load==NULL || strlen(pre_load)==0) ptx = findPTXSection(fname); symbol_table *symtab; char *ptxcode; - const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); - if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL or strlen(getenv("PTX_SIM_USE_PTX_FILE"))==0) { + //const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); + //if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL or strlen(getenv("PTX_SIM_USE_PTX_FILE"))==0) { ptxcode = readfile(ptx->getPTXfilename()); - } else { - printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); - ptxcode = readfile(override_ptx_name); - } +// } +// else { +// printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); +// ptxcode = readfile(override_ptx_name); +// } if(context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() ) { cuobjdumpELFSection* elfsection = findELFSection(ptx->getIdentifier()); assert (elfsection!= NULL); -- cgit v1.3 From 03de5ae03420ba5666d669c6f76faccf2704fa58 Mon Sep 17 00:00:00 2001 From: aamir Date: Thu, 31 May 2018 00:48:37 -0700 Subject: mma_ld_impl --- src/cuda-sim/ptx.y | 2 +- src/cuda-sim/ptx_ir.h | 2 +- src/cuda-sim/ptx_parser.cc | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 737657c..012451c 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -520,7 +520,7 @@ compare_spec:EQ_OPTION { add_option(EQ_OPTION); } | NAN_OPTION { add_option(NAN_OPTION); } ; -wmma_spec: WMMA_DIRECTIVE LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2);add_wmma_option($3);} +wmma_spec: WMMA_DIRECTIVE LAYOUT CONFIGURATION{add_space_spec(global_space,0);add_ptr_spec(global_space); add_wmma_option($1);add_wmma_option($2);add_wmma_option($3);} | WMMA_DIRECTIVE LAYOUT LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2),add_wmma_option($3),add_wmma_option($4)} ; diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 16cc975..6bba717 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -665,7 +665,7 @@ public: const symbol* vec_symbol(int idx) const { - assert(idx < 4); + assert(idx < 8); const symbol *result = m_value.m_vector_symbolic[idx]; assert( result != NULL ); return result; diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index 6757091..eb81961 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -39,7 +39,7 @@ void set_ptx_warp_size(const struct core_config * warp_size) g_shader_core_config=warp_size; } -static bool g_debug_ir_generation=false; +static bool g_debug_ir_generation=true; const char *g_filename; unsigned g_max_regs_per_thread = 0; -- cgit v1.3 From c175eeab56567165f4be72b87746439ad0837c6e Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 31 May 2018 11:23:02 -0700 Subject: Revert "allows _1.ptx generation without cuobjdump_complete_output generation" This reverts commit 29b566108f2304e42e12ba5ab1d9e7f45117bd83. --- libcuda/cuda_runtime_api.cc | 130 ++++++++++++++++++++------------------------ 1 file changed, 60 insertions(+), 70 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index fcb0808..dc92522 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1611,70 +1611,61 @@ void extract_code_using_cuobjdump(){ printf("Parsing skipped for %s\n", fname); } + if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ + //Experimental library support + //Currently only for cufft + + std::stringstream cmd; + cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; + int result = system(cmd.str().c_str()); + if(result){ + std::cout << "Failed to execute: " << cmd.str() << std::endl; + exit(1); + } + std::ifstream libsf; + libsf.open("_tempfile_.txt"); + if(!libsf.is_open()) { + std::cout << "Failed to open: _tempfile_.txt" << std::endl; + exit(1); + } + + //Save the original section list + std::list tmpsl = cuobjdumpSectionList; + cuobjdumpSectionList.clear(); + + std::string line; + std::getline(libsf, line); + std::cout << "DOING: " << line << std::endl; + int cnt=1; + while(libsf.good()){ + std::stringstream libcodfn; + libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; + cmd.str(""); //resetting + cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; + cmd << line; + cmd << " > "; + cmd << libcodfn.str(); + std::cout << "Running cuobjdump on " << line << std::endl; + std::cout << "Using command: " << cmd.str() << std::endl; + result = system(cmd.str().c_str()); + if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} + std::cout << "Done" << std::endl; + + std::cout << "Trying to parse " << libcodfn.str() << std::endl; + cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); + cuobjdump_parse(); + fclose(cuobjdump_in); + std::getline(libsf, line); + } + libSectionList = cuobjdumpSectionList; + + //Restore the original section list + cuobjdumpSectionList = tmpsl; + } } else { printf("GPGPU-Sim PTX: overriding cuobjdump with '%s' (CUOBJDUMP_SIM_FILE is set)\n", override_cuobjdump); snprintf(fname,1024, "%s",override_cuobjdump); - - printf("Parsing file %s\n", override_cuobjdump); - cuobjdump_in = fopen(override_cuobjdump, "r"); - - cuobjdump_parse(); - fclose(cuobjdump_in); - printf("Done parsing!!!\n"); } - - if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ - //Experimental library support - //Currently only for cufft - - std::stringstream cmd; - cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; - int result = system(cmd.str().c_str()); - if(result){ - std::cout << "Failed to execute: " << cmd.str() << std::endl; - exit(1); - } - std::ifstream libsf; - libsf.open("_tempfile_.txt"); - if(!libsf.is_open()) { - std::cout << "Failed to open: _tempfile_.txt" << std::endl; - exit(1); - } - - //Save the original section list - std::list tmpsl = cuobjdumpSectionList; - cuobjdumpSectionList.clear(); - - std::string line; - std::getline(libsf, line); - std::cout << "DOING: " << line << std::endl; - int cnt=1; - while(libsf.good()){ - std::stringstream libcodfn; - libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; - cmd.str(""); //resetting - cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; - cmd << line; - cmd << " > "; - cmd << libcodfn.str(); - std::cout << "Running cuobjdump on " << line << std::endl; - std::cout << "Using command: " << cmd.str() << std::endl; - result = system(cmd.str().c_str()); - if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} - std::cout << "Done" << std::endl; - - std::cout << "Trying to parse " << libcodfn.str() << std::endl; - cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); - cuobjdump_parse(); - fclose(cuobjdump_in); - std::getline(libsf, line); - } - libSectionList = cuobjdumpSectionList; - - //Restore the original section list - cuobjdumpSectionList = tmpsl; - } - } //! Read file into char* @@ -1907,10 +1898,10 @@ void cuobjdumpInit(){ CUctx_st *context = GPGPUSim_Context(); extract_code_using_cuobjdump(); //extract all the output of cuobjdump to _cuobjdump_*.* const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); - //if (pre_load ==NULL || strlen(pre_load)==0){ + if (pre_load ==NULL || strlen(pre_load)==0){ cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); cuobjdumpSectionList = mergeSections(cuobjdumpSectionList); - //} + } } std::map fatbinmap; @@ -1948,18 +1939,17 @@ void cuobjdumpParseBinary(unsigned int handle){ cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); - //if(pre_load==NULL || strlen(pre_load)==0) + if(pre_load==NULL || strlen(pre_load)==0) ptx = findPTXSection(fname); symbol_table *symtab; char *ptxcode; - //const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); - //if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL or strlen(getenv("PTX_SIM_USE_PTX_FILE"))==0) { + const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); + if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL or strlen(getenv("PTX_SIM_USE_PTX_FILE"))==0) { ptxcode = readfile(ptx->getPTXfilename()); -// } -// else { -// printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); -// ptxcode = readfile(override_ptx_name); -// } + } else { + printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); + ptxcode = readfile(override_ptx_name); + } if(context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() ) { cuobjdumpELFSection* elfsection = findELFSection(ptx->getIdentifier()); assert (elfsection!= NULL); -- cgit v1.3 From e5f532a3b65e17f49991ed08a275f87ac2d68d0a Mon Sep 17 00:00:00 2001 From: aamir Date: Fri, 1 Jun 2018 09:52:12 -0700 Subject: wmma load working --- cuda-kernels/gpgpu_inst_stats.txt | 19 + cuda-kernels/log | 6328 +++++++++++++++++++++++++++++++++++++ cuda-kernels/log1 | 512 +++ cuda-kernels/tensor_core | Bin 2750968 -> 2750968 bytes src/cuda-sim/Makefile | 2 +- src/cuda-sim/cuda-math.h | 1 + src/cuda-sim/cuda-sim.cc | 2 +- src/cuda-sim/half.hpp | 3067 ++++++++++++++++++ src/cuda-sim/instructions.cc | 96 +- src/cuda-sim/ptx_sim.h | 6 +- 10 files changed, 9988 insertions(+), 45 deletions(-) create mode 100644 cuda-kernels/log create mode 100644 cuda-kernels/log1 create mode 100644 src/cuda-sim/half.hpp diff --git a/cuda-kernels/gpgpu_inst_stats.txt b/cuda-kernels/gpgpu_inst_stats.txt index acb1839..41f06a4 100755 --- a/cuda-kernels/gpgpu_inst_stats.txt +++ b/cuda-kernels/gpgpu_inst_stats.txt @@ -1 +1,20 @@ kernel line : count latency dram_traffic smem_bk_conflicts smem_warp gmem_access_generated gmem_warp exposed_latency warp_divergence +_1.ptx 164 : 512 2560 1024 0 0 16 16 0 0 +_1.ptx 163 : 512 5696 0 0 0 0 0 0 0 +_1.ptx 162 : 512 5664 0 0 0 0 0 0 0 +_1.ptx 161 : 512 3616 0 0 0 0 0 0 0 +_1.ptx 158 : 512 3616 0 0 0 0 0 0 0 +_1.ptx 156 : 512 134048 2048 0 0 16 16 0 0 +_1.ptx 155 : 512 5632 0 0 0 0 0 0 0 +_1.ptx 154 : 512 5376 0 0 0 0 0 0 0 +_1.ptx 143 : 512 100864 128 0 0 0 0 0 0 +_1.ptx 167 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 144 : 512 100864 0 0 0 0 0 0 0 +_1.ptx 145 : 512 1536 0 0 0 0 0 0 0 +_1.ptx 146 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 147 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 148 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 149 : 512 8384 0 0 0 0 0 0 0 +_1.ptx 150 : 512 4096 0 0 0 0 0 0 0 +_1.ptx 151 : 512 0 0 0 0 0 0 0 0 +_1.ptx 153 : 512 3968 0 0 0 0 0 0 0 diff --git a/cuda-kernels/log b/cuda-kernels/log new file mode 100644 index 0000000..98df26a --- /dev/null +++ b/cuda-kernels/log @@ -0,0 +1,6328 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-03de5ae03420ba5666d669c6f76faccf2704fa58_modified_17] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 70 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 40 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,16,4 # Opcode latencies for integers Default 1,1,19,25,145,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,16,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 40 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 50 51 52 53 54 55 +GPGPU-Sim uArch: 56 57 58 59 60 61 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 40 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 50 51 52 53 54 55 +GPGPU-Sim uArch: 56 57 58 59 60 61 +a9478053306cbb4803bedf0d6ea12100 /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core +Running md5sum using "md5sum /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core " +Parsing file _cuobjdump_complete_output_c7ZC8M +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_70 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z17convertFp32ToFp16P6__halfPfi : hostFun 0x0x401dd7, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 70 + _1.ptx:13 => (ptx_parser.cc:175) start_function + _1.ptx:13 => (ptx_parser.cc:144) init_directive_state + _1.ptx:13 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:13 => (ptx_parser.cc:144) init_directive_state + _1.ptx:13 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:13 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:13 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B32_TYPE + _1.ptx:14 => (ptx_parser.cc:189) add_function_name vprintf (extern) + _1.ptx:14 => (ptx_parser.cc:381) add_identifier "func_retval0" (0) +GPGPU-Sim PTX: allocating stack frame region for .param "func_retval0" from 0x0 to 0x4 + _1.ptx:14 => (ptx_parser.cc:144) init_directive_state + _1.ptx:15 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:15 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:15 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B64_TYPE + _1.ptx:15 => (ptx_parser.cc:381) add_identifier "vprintf_param_0" (1) +GPGPU-Sim PTX: allocating stack frame region for .param "vprintf_param_0" from 0x4 to 0xc + _1.ptx:15 => (ptx_parser.cc:577) add_function_arg "vprintf_param_0" + _1.ptx:15 => (ptx_parser.cc:219) add_directive + _1.ptx:15 => (ptx_parser.cc:144) init_directive_state + _1.ptx:16 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:16 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:16 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B64_TYPE + _1.ptx:17 => (ptx_parser.cc:381) add_identifier "vprintf_param_1" (2) +GPGPU-Sim PTX: allocating stack frame region for .param "vprintf_param_1" from 0xc to 0x14 + _1.ptx:17 => (ptx_parser.cc:577) add_function_arg "vprintf_param_1" + _1.ptx:17 => (ptx_parser.cc:219) add_directive + _1.ptx:17 => (ptx_parser.cc:144) init_directive_state + _1.ptx:19 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:19 => (ptx_parser.cc:590) add_alignment_spec + _1.ptx:19 => (ptx_parser.cc:631) add_scalar_type_spec "B8_TYPE" + _1.ptx:19 => (ptx_parser.cc:331) set_variable_type space_spec=global_space scalar_type_spec=B8_TYPE + _1.ptx:19 => (ptx_parser.cc:381) add_identifier "$str" (3) +GPGPU-Sim PTX: allocating global region for "$str" from 0x100 to 0x109 (global memory space) + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:319) add_variables + _1.ptx:19 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:175) start_function + _1.ptx:21 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:21 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:189) add_function_name _Z12wmma_exampleP6__halfS0_Pfiiiff (entrypoint) + _1.ptx:22 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:22 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:22 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:22 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0" (4) + _1.ptx:22 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0" + _1.ptx:22 => (ptx_parser.cc:219) add_directive + _1.ptx:22 => (ptx_parser.cc:144) init_directive_state + _1.ptx:23 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:23 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:23 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:23 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1" (5) + _1.ptx:23 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1" + _1.ptx:23 => (ptx_parser.cc:219) add_directive + _1.ptx:23 => (ptx_parser.cc:144) init_directive_state + _1.ptx:24 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:24 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:24 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:24 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2" (6) + _1.ptx:24 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2" + _1.ptx:24 => (ptx_parser.cc:219) add_directive + _1.ptx:24 => (ptx_parser.cc:144) init_directive_state + _1.ptx:25 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:25 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:25 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:25 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3" (7) + _1.ptx:25 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3" + _1.ptx:25 => (ptx_parser.cc:219) add_directive + _1.ptx:25 => (ptx_parser.cc:144) init_directive_state + _1.ptx:26 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:26 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:26 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:26 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4" (8) + _1.ptx:26 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4" + _1.ptx:26 => (ptx_parser.cc:219) add_directive + _1.ptx:26 => (ptx_parser.cc:144) init_directive_state + _1.ptx:27 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:27 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:27 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:27 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5" (9) + _1.ptx:27 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5" + _1.ptx:27 => (ptx_parser.cc:219) add_directive + _1.ptx:27 => (ptx_parser.cc:144) init_directive_state + _1.ptx:28 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:28 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:28 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=F32_TYPE + _1.ptx:28 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_6" (10) + _1.ptx:28 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_6" + _1.ptx:28 => (ptx_parser.cc:219) add_directive + _1.ptx:28 => (ptx_parser.cc:144) init_directive_state + _1.ptx:29 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:29 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:29 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=F32_TYPE + _1.ptx:30 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_7" (11) + _1.ptx:30 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_7" + _1.ptx:30 => (ptx_parser.cc:219) add_directive + _1.ptx:30 => (ptx_parser.cc:144) init_directive_state + _1.ptx:32 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:32 => (ptx_parser.cc:590) add_alignment_spec + _1.ptx:32 => (ptx_parser.cc:631) add_scalar_type_spec "B8_TYPE" + _1.ptx:32 => (ptx_parser.cc:331) set_variable_type space_spec=local_space scalar_type_spec=B8_TYPE + _1.ptx:32 => (ptx_parser.cc:381) add_identifier "__local_depot0" (12) +GPGPU-Sim PTX: allocating stack frame region for .local "__local_depot0" from 0x0 to 0x8 + _1.ptx:32 => (ptx_parser.cc:319) add_variables + _1.ptx:32 => (ptx_parser.cc:144) init_directive_state + _1.ptx:32 => (ptx_parser.cc:219) add_directive + _1.ptx:32 => (ptx_parser.cc:144) init_directive_state + _1.ptx:33 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:33 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:33 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:33 => (ptx_parser.cc:381) add_identifier "%SP" (13) + _1.ptx:33 => (ptx_parser.cc:319) add_variables + _1.ptx:33 => (ptx_parser.cc:144) init_directive_state + _1.ptx:33 => (ptx_parser.cc:219) add_directive + _1.ptx:33 => (ptx_parser.cc:144) init_directive_state + _1.ptx:34 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:34 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:34 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:34 => (ptx_parser.cc:381) add_identifier "%SPL" (14) + _1.ptx:34 => (ptx_parser.cc:319) add_variables + _1.ptx:34 => (ptx_parser.cc:144) init_directive_state + _1.ptx:34 => (ptx_parser.cc:219) add_directive + _1.ptx:34 => (ptx_parser.cc:144) init_directive_state + _1.ptx:35 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:35 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:35 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=PRED_TYPE + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p0" (15) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p1" (16) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p2" (17) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p3" (18) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p4" (19) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p5" (20) + _1.ptx:35 => (ptx_parser.cc:319) add_variables + _1.ptx:35 => (ptx_parser.cc:144) init_directive_state + _1.ptx:35 => (ptx_parser.cc:219) add_directive + _1.ptx:35 => (ptx_parser.cc:144) init_directive_state + _1.ptx:36 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:36 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:36 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=F32_TYPE + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f0" (21) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f1" (22) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f2" (23) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f3" (24) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f4" (25) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f5" (26) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f6" (27) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f7" (28) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f8" (29) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f9" (30) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f10" (31) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f11" (32) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f12" (33) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f13" (34) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f14" (35) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f15" (36) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f16" (37) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f17" (38) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f18" (39) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f19" (40) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f20" (41) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f21" (42) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f22" (43) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f23" (44) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f24" (45) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f25" (46) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f26" (47) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f27" (48) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f28" (49) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f29" (50) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f30" (51) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f31" (52) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f32" (53) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f33" (54) + _1.ptx:36 => (ptx_parser.cc:319) add_variables + _1.ptx:36 => (ptx_parser.cc:144) init_directive_state + _1.ptx:36 => (ptx_parser.cc:219) add_directive + _1.ptx:36 => (ptx_parser.cc:144) init_directive_state + _1.ptx:37 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:37 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:37 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B32_TYPE + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r0" (55) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r1" (56) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r2" (57) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r3" (58) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r4" (59) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r5" (60) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r6" (61) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r7" (62) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r8" (63) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r9" (64) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r10" (65) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r11" (66) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r12" (67) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r13" (68) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r14" (69) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r15" (70) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r16" (71) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r17" (72) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r18" (73) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r19" (74) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r20" (75) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r21" (76) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r22" (77) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r23" (78) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r24" (79) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r25" (80) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r26" (81) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r27" (82) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r28" (83) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r29" (84) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r30" (85) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r31" (86) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r32" (87) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r33" (88) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r34" (89) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r35" (90) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r36" (91) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r37" (92) + _1.ptx:37 => (ptx_parser.cc:319) add_variables + _1.ptx:37 => (ptx_parser.cc:144) init_directive_state + _1.ptx:37 => (ptx_parser.cc:219) add_directive + _1.ptx:37 => (ptx_parser.cc:144) init_directive_state + _1.ptx:38 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:38 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:38 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd0" (93) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd1" (94) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd2" (95) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd3" (96) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd4" (97) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd5" (98) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd6" (99) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd7" (100) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd8" (101) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd9" (102) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd10" (103) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd11" (104) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd12" (105) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd13" (106) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd14" (107) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd15" (108) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd16" (109) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd17" (110) + _1.ptx:38 => (ptx_parser.cc:319) add_variables + _1.ptx:38 => (ptx_parser.cc:144) init_directive_state + _1.ptx:38 => (ptx_parser.cc:219) add_directive + _1.ptx:38 => (ptx_parser.cc:144) init_directive_state + _1.ptx:41 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:41 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:41 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:41 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:41 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:41 => (ptx_parser.cc:144) init_directive_state + _1.ptx:42 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:42 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:42 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:42 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:42 => (ptx_parser.cc:295) add_instruction: cvta + _1.ptx:42 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:42 => (ptx_parser.cc:144) init_directive_state + _1.ptx:43 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:43 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:43 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:43 => (ptx_parser.cc:929) add_address_operand + _1.ptx:43 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:43 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:43 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:43 => (ptx_parser.cc:144) init_directive_state + _1.ptx:44 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:44 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:44 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:44 => (ptx_parser.cc:929) add_address_operand + _1.ptx:44 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:44 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:44 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:44 => (ptx_parser.cc:144) init_directive_state + _1.ptx:45 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:45 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:45 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:45 => (ptx_parser.cc:929) add_address_operand + _1.ptx:45 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:45 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:45 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:45 => (ptx_parser.cc:144) init_directive_state + _1.ptx:46 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:46 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:46 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:46 => (ptx_parser.cc:929) add_address_operand + _1.ptx:46 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:46 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:46 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:46 => (ptx_parser.cc:144) init_directive_state + _1.ptx:47 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:47 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:47 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:47 => (ptx_parser.cc:929) add_address_operand + _1.ptx:47 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:47 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:47 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:47 => (ptx_parser.cc:144) init_directive_state + _1.ptx:48 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:48 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:48 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:48 => (ptx_parser.cc:929) add_address_operand + _1.ptx:48 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:48 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:48 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:48 => (ptx_parser.cc:144) init_directive_state + _1.ptx:50 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:50 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:50 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:50 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:50 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:50 => (ptx_parser.cc:144) init_directive_state + _1.ptx:52 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:52 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:52 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:52 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:52 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:52 => (ptx_parser.cc:144) init_directive_state + _1.ptx:53 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:53 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:53 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:53 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:53 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:53 => (ptx_parser.cc:144) init_directive_state + _1.ptx:54 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:54 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:54 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:54 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:54 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:54 => (ptx_parser.cc:144) init_directive_state + _1.ptx:55 => (ptx_parser.cc:672) add_option + _1.ptx:55 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:295) add_instruction: mad + _1.ptx:55 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:55 => (ptx_parser.cc:144) init_directive_state + _1.ptx:56 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:56 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:56 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:56 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:56 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:56 => (ptx_parser.cc:144) init_directive_state + _1.ptx:57 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:295) add_instruction: div + _1.ptx:57 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:57 => (ptx_parser.cc:144) init_directive_state + _1.ptx:58 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:58 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:58 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:58 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:58 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:58 => (ptx_parser.cc:144) init_directive_state + _1.ptx:59 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:59 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:59 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:59 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:59 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:59 => (ptx_parser.cc:144) init_directive_state + _1.ptx:60 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:60 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:60 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:60 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:60 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:60 => (ptx_parser.cc:144) init_directive_state + _1.ptx:61 => (ptx_parser.cc:672) add_option + _1.ptx:61 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:295) add_instruction: mad + _1.ptx:61 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:61 => (ptx_parser.cc:144) init_directive_state + _1.ptx:62 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:62 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:62 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:62 => (ptx_parser.cc:883) add_literal_int + _1.ptx:62 => (ptx_parser.cc:295) add_instruction: shl + _1.ptx:62 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:62 => (ptx_parser.cc:144) init_directive_state + _1.ptx:63 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:63 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:63 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:63 => (ptx_parser.cc:883) add_literal_int + _1.ptx:63 => (ptx_parser.cc:295) add_instruction: shl + _1.ptx:63 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:63 => (ptx_parser.cc:144) init_directive_state + _1.ptx:64 => (ptx_parser.cc:672) add_option + _1.ptx:64 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:64 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:64 => (ptx_parser.cc:144) init_directive_state + _1.ptx:65 => (ptx_parser.cc:672) add_option + _1.ptx:65 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:65 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:65 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:65 => (ptx_parser.cc:883) add_literal_int + _1.ptx:65 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:65 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:65 => (ptx_parser.cc:144) init_directive_state + _1.ptx:66 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:295) add_instruction: and + _1.ptx:66 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:66 => (ptx_parser.cc:144) init_directive_state + _1.ptx:67 => (ptx_parser.cc:672) add_option + _1.ptx:67 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:67 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:67 => (ptx_parser.cc:144) init_directive_state + _1.ptx:68 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:295) add_instruction: and + _1.ptx:68 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:68 => (ptx_parser.cc:144) init_directive_state + _1.ptx:69 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:69 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:69 => (ptx_parser.cc:889) add_literal_float + _1.ptx:69 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:69 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:69 => (ptx_parser.cc:144) init_directive_state + _1.ptx:70 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:70 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:70 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:70 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:70 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:70 => (ptx_parser.cc:144) init_directive_state + _1.ptx:71 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:71 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:71 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:71 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:71 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:71 => (ptx_parser.cc:144) init_directive_state + _1.ptx:72 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:72 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:72 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:72 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:72 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:72 => (ptx_parser.cc:144) init_directive_state + _1.ptx:73 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:73 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:73 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:73 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:73 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:73 => (ptx_parser.cc:144) init_directive_state + _1.ptx:74 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:74 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:74 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:74 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:74 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:74 => (ptx_parser.cc:144) init_directive_state + _1.ptx:75 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:75 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:75 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:75 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:75 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:75 => (ptx_parser.cc:144) init_directive_state + _1.ptx:76 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:76 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:76 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:76 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:76 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:76 => (ptx_parser.cc:144) init_directive_state + _1.ptx:77 => (ptx_parser.cc:659) add_pred + _1.ptx:77 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:77 => (ptx_parser.cc:295) add_instruction: bra + _1.ptx:77 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:77 => (ptx_parser.cc:144) init_directive_state + _1.ptx:78 => (ptx_parser.cc:672) add_option + _1.ptx:78 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:78 => (ptx_parser.cc:295) add_instruction: bra + _1.ptx:78 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:78 => (ptx_parser.cc:144) init_directive_state + _1.ptx:80 => (ptx_parser.cc:643) add_label + _1.ptx:80 => (ptx_parser.cc:295) add_instruction: