From 53e4c1bc257deba2341467d0438a55e4074f3059 Mon Sep 17 00:00:00 2001 From: Andrew Boktor Date: Wed, 18 Feb 2015 13:43:19 -0800 Subject: Fixing icache bug where for each miss we also count a hit. --- CHANGES | 1 + src/gpgpu-sim/mem_fetch.h | 1 + src/gpgpu-sim/shader.cc | 33 ++++++++++++++++++--------------- 3 files changed, 20 insertions(+), 15 deletions(-) diff --git a/CHANGES b/CHANGES index 7352d28..830ca85 100644 --- a/CHANGES +++ b/CHANGES @@ -8,6 +8,7 @@ Version 3.2.3+edits (development branch) versus 3.2.3 - Bug fixes: - Fixed bug #81, fix ordering of pushing branch entries to the stack + - Fixed a bug where for each icache miss we also count a hit Version 3.2.3 versus 3.2.2 - Bug fixes: diff --git a/src/gpgpu-sim/mem_fetch.h b/src/gpgpu-sim/mem_fetch.h index f788c2b..c89edbb 100644 --- a/src/gpgpu-sim/mem_fetch.h +++ b/src/gpgpu-sim/mem_fetch.h @@ -82,6 +82,7 @@ public: bool is_write() {return m_access.is_write();} void set_addr(new_addr_type addr) { m_access.set_addr(addr); } new_addr_type get_addr() const { return m_access.get_addr(); } + unsigned get_access_size() const { return m_access.get_size(); } new_addr_type get_partition_addr() const { return m_partition_addr; } unsigned get_sub_partition_id() const { return m_raw_addr.sub_partition; } bool get_is_write() const { return m_access.is_write(); } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index b761dac..1c4465b 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -633,12 +633,12 @@ void shader_core_ctx::fetch() // mem_fetch *mf = m_mem_fetch_allocator->alloc() mem_access_t acc(INST_ACC_R,ppc,nbytes,false); mem_fetch *mf = new mem_fetch(acc, - NULL/*we don't have an instruction yet*/, - READ_PACKET_SIZE, - warp_id, - m_sid, - m_tpc, - m_memory_config ); + NULL/*we don't have an instruction yet*/, + READ_PACKET_SIZE, + warp_id, + m_sid, + m_tpc, + m_memory_config ); std::list events; enum cache_request_status status = m_L1I->access( (new_addr_type)ppc, mf, gpu_sim_cycle+gpu_tot_sim_cycle,events); if( status == MISS ) { @@ -665,6 +665,9 @@ void shader_core_ctx::fetch() if( m_L1I->access_ready() ) { mem_fetch *mf = m_L1I->next_access(); m_warp[mf->get_wid()].clear_imiss_pending(); + m_inst_fetch_buffer = ifetch_buffer_t(m_warp[mf->get_wid()].get_pc(), mf->get_access_size(), mf->get_wid()); + m_inst_fetch_buffer.m_valid = true; + m_warp[mf->get_wid()].set_last_fetch(gpu_sim_cycle); delete mf; } } @@ -680,7 +683,7 @@ void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* { warp_inst_t** pipe_reg = pipe_reg_set.get_free(); assert(pipe_reg); - + m_warp[warp_id].ibuffer_free(); assert(next_inst->valid()); **pipe_reg = *next_inst; // static instruction information @@ -688,7 +691,7 @@ void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* m_stats->shader_cycle_distro[2+(*pipe_reg)->active_count()]++; func_exec_inst( **pipe_reg ); if( next_inst->op == BARRIER_OP ){ - m_warp[warp_id].store_info_of_last_inst_at_barrier(*pipe_reg); + m_warp[warp_id].store_info_of_last_inst_at_barrier(*pipe_reg); m_barriers.warp_reaches_barrier(m_warp[warp_id].get_cta_id(),warp_id,const_cast (next_inst)); }else if( next_inst->op == MEMORY_BARRIER_OP ){ @@ -731,21 +734,21 @@ shd_warp_t& scheduler_unit::warp(int i){ * limit this number. If the number if < m_supervised_warps.size(), then only * the warps with highest RR priority will be placed in the result_list. */ -template < class T > + template < class T > void scheduler_unit::order_lrr( std::vector< T >& result_list, - const typename std::vector< T >& input_list, - const typename std::vector< T >::const_iterator& last_issued_from_input, - unsigned num_warps_to_add ) + const typename std::vector< T >& input_list, + const typename std::vector< T >::const_iterator& last_issued_from_input, + unsigned num_warps_to_add ) { assert( num_warps_to_add <= input_list.size() ); result_list.clear(); typename std::vector< T >::const_iterator iter = ( last_issued_from_input == input_list.end() ) ? input_list.begin() - : last_issued_from_input + 1; + : last_issued_from_input + 1; for ( unsigned count = 0; - count < num_warps_to_add; - ++iter, ++count) { + count < num_warps_to_add; + ++iter, ++count) { if ( iter == input_list.end() ) { iter = input_list.begin(); } -- cgit v1.3 From 7b32e6b04e0cfbf34a18d87bde5f9b26789177e8 Mon Sep 17 00:00:00 2001 From: Andrew Boktor Date: Wed, 18 Feb 2015 14:35:56 -0800 Subject: Making sure that we only service returning cache misses when we have a place to fetch into. --- src/gpgpu-sim/shader.cc | 144 ++++++++++++++++++++++++------------------------ 1 file changed, 73 insertions(+), 71 deletions(-) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 1c4465b..2c8d5d1 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -595,81 +595,83 @@ void shader_core_ctx::decode() void shader_core_ctx::fetch() { + if( !m_inst_fetch_buffer.m_valid ) { - // find an active warp with space in instruction buffer that is not already waiting on a cache miss - // and get next 1-2 instructions from i-cache... - for( unsigned i=0; i < m_config->max_warps_per_shader; i++ ) { - unsigned warp_id = (m_last_warp_fetched+1+i) % m_config->max_warps_per_shader; - - // this code checks if this warp has finished executing and can be reclaimed - if( m_warp[warp_id].hardware_done() && !m_scoreboard->pendingWrites(warp_id) && !m_warp[warp_id].done_exit() ) { - bool did_exit=false; - for( unsigned t=0; twarp_size;t++) { - unsigned tid=warp_id*m_config->warp_size+t; - if( m_threadState[tid].m_active == true ) { - m_threadState[tid].m_active = false; - unsigned cta_id = m_warp[warp_id].get_cta_id(); - register_cta_thread_exit(cta_id); - m_not_completed -= 1; - m_active_threads.reset(tid); - assert( m_thread[tid]!= NULL ); - did_exit=true; + if( m_L1I->access_ready() ) { + mem_fetch *mf = m_L1I->next_access(); + m_warp[mf->get_wid()].clear_imiss_pending(); + m_inst_fetch_buffer = ifetch_buffer_t(m_warp[mf->get_wid()].get_pc(), mf->get_access_size(), mf->get_wid()); + m_inst_fetch_buffer.m_valid = true; + m_warp[mf->get_wid()].set_last_fetch(gpu_sim_cycle); + delete mf; + } + else { + // find an active warp with space in instruction buffer that is not already waiting on a cache miss + // and get next 1-2 instructions from i-cache... + for( unsigned i=0; i < m_config->max_warps_per_shader; i++ ) { + unsigned warp_id = (m_last_warp_fetched+1+i) % m_config->max_warps_per_shader; + + // this code checks if this warp has finished executing and can be reclaimed + if( m_warp[warp_id].hardware_done() && !m_scoreboard->pendingWrites(warp_id) && !m_warp[warp_id].done_exit() ) { + bool did_exit=false; + for( unsigned t=0; twarp_size;t++) { + unsigned tid=warp_id*m_config->warp_size+t; + if( m_threadState[tid].m_active == true ) { + m_threadState[tid].m_active = false; + unsigned cta_id = m_warp[warp_id].get_cta_id(); + register_cta_thread_exit(cta_id); + m_not_completed -= 1; + m_active_threads.reset(tid); + assert( m_thread[tid]!= NULL ); + did_exit=true; + } } + if( did_exit ) + m_warp[warp_id].set_done_exit(); } - if( did_exit ) - m_warp[warp_id].set_done_exit(); - } - // this code fetches instructions from the i-cache or generates memory requests - if( !m_warp[warp_id].functional_done() && !m_warp[warp_id].imiss_pending() && m_warp[warp_id].ibuffer_empty() ) { - address_type pc = m_warp[warp_id].get_pc(); - address_type ppc = pc + PROGRAM_MEM_START; - unsigned nbytes=16; - unsigned offset_in_block = pc & (m_config->m_L1I_config.get_line_sz()-1); - if( (offset_in_block+nbytes) > m_config->m_L1I_config.get_line_sz() ) - nbytes = (m_config->m_L1I_config.get_line_sz()-offset_in_block); - - // TODO: replace with use of allocator - // mem_fetch *mf = m_mem_fetch_allocator->alloc() - mem_access_t acc(INST_ACC_R,ppc,nbytes,false); - mem_fetch *mf = new mem_fetch(acc, - NULL/*we don't have an instruction yet*/, - READ_PACKET_SIZE, - warp_id, - m_sid, - m_tpc, - m_memory_config ); - std::list events; - enum cache_request_status status = m_L1I->access( (new_addr_type)ppc, mf, gpu_sim_cycle+gpu_tot_sim_cycle,events); - if( status == MISS ) { - m_last_warp_fetched=warp_id; - m_warp[warp_id].set_imiss_pending(); - m_warp[warp_id].set_last_fetch(gpu_sim_cycle); - } else if( status == HIT ) { - m_last_warp_fetched=warp_id; - m_inst_fetch_buffer = ifetch_buffer_t(pc,nbytes,warp_id); - m_warp[warp_id].set_last_fetch(gpu_sim_cycle); - delete mf; - } else { - m_last_warp_fetched=warp_id; - assert( status == RESERVATION_FAIL ); - delete mf; + // this code fetches instructions from the i-cache or generates memory requests + if( !m_warp[warp_id].functional_done() && !m_warp[warp_id].imiss_pending() && m_warp[warp_id].ibuffer_empty() ) { + address_type pc = m_warp[warp_id].get_pc(); + address_type ppc = pc + PROGRAM_MEM_START; + unsigned nbytes=16; + unsigned offset_in_block = pc & (m_config->m_L1I_config.get_line_sz()-1); + if( (offset_in_block+nbytes) > m_config->m_L1I_config.get_line_sz() ) + nbytes = (m_config->m_L1I_config.get_line_sz()-offset_in_block); + + // TODO: replace with use of allocator + // mem_fetch *mf = m_mem_fetch_allocator->alloc() + mem_access_t acc(INST_ACC_R,ppc,nbytes,false); + mem_fetch *mf = new mem_fetch(acc, + NULL/*we don't have an instruction yet*/, + READ_PACKET_SIZE, + warp_id, + m_sid, + m_tpc, + m_memory_config ); + std::list events; + enum cache_request_status status = m_L1I->access( (new_addr_type)ppc, mf, gpu_sim_cycle+gpu_tot_sim_cycle,events); + if( status == MISS ) { + m_last_warp_fetched=warp_id; + m_warp[warp_id].set_imiss_pending(); + m_warp[warp_id].set_last_fetch(gpu_sim_cycle); + } else if( status == HIT ) { + m_last_warp_fetched=warp_id; + m_inst_fetch_buffer = ifetch_buffer_t(pc,nbytes,warp_id); + m_warp[warp_id].set_last_fetch(gpu_sim_cycle); + delete mf; + } else { + m_last_warp_fetched=warp_id; + assert( status == RESERVATION_FAIL ); + delete mf; + } + break; } - break; } } } m_L1I->cycle(); - - if( m_L1I->access_ready() ) { - mem_fetch *mf = m_L1I->next_access(); - m_warp[mf->get_wid()].clear_imiss_pending(); - m_inst_fetch_buffer = ifetch_buffer_t(m_warp[mf->get_wid()].get_pc(), mf->get_access_size(), mf->get_wid()); - m_inst_fetch_buffer.m_valid = true; - m_warp[mf->get_wid()].set_last_fetch(gpu_sim_cycle); - delete mf; - } } void shader_core_ctx::func_exec_inst( warp_inst_t &inst ) @@ -767,13 +769,13 @@ void scheduler_unit::order_lrr( std::vector< T >& result_list, * with the oldest warps having the most priority, then the priority_function * would compare the age of the two warps. */ -template < class T > + template < class T > void scheduler_unit::order_by_priority( std::vector< T >& result_list, - const typename std::vector< T >& input_list, - const typename std::vector< T >::const_iterator& last_issued_from_input, - unsigned num_warps_to_add, - OrderingType ordering, - bool (*priority_func)(T lhs, T rhs) ) + const typename std::vector< T >& input_list, + const typename std::vector< T >::const_iterator& last_issued_from_input, + unsigned num_warps_to_add, + OrderingType ordering, + bool (*priority_func)(T lhs, T rhs) ) { assert( num_warps_to_add <= input_list.size() ); result_list.clear(); -- cgit v1.3 From 1e925effd20bf6fb78b19a4cdb96b17691a29b29 Mon Sep 17 00:00:00 2001 From: Andrew Boktor Date: Thu, 19 Feb 2015 14:40:06 -0800 Subject: Adding an assert to make sure we got the right instruction back --- src/gpgpu-sim/shader.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 2c8d5d1..3c105ab 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -601,6 +601,7 @@ void shader_core_ctx::fetch() mem_fetch *mf = m_L1I->next_access(); m_warp[mf->get_wid()].clear_imiss_pending(); m_inst_fetch_buffer = ifetch_buffer_t(m_warp[mf->get_wid()].get_pc(), mf->get_access_size(), mf->get_wid()); + assert( m_warp[mf->get_wid()].get_pc() == (mf->get_addr()-PROGRAM_MEM_START)); // Verify that we got the instruction we were expecting. m_inst_fetch_buffer.m_valid = true; m_warp[mf->get_wid()].set_last_fetch(gpu_sim_cycle); delete mf; -- cgit v1.3 From 18e0b0614611edcb19ee0a3b315c7b45e50b5595 Mon Sep 17 00:00:00 2001 From: Ahmed ElTantawy Date: Wed, 4 Mar 2015 12:02:52 -0800 Subject: initial support for CUDA 5.0, 5.5, 6.0 to get template from SDK running --- CHANGES | 3 +- Makefile | 3 ++ libcuda/cuda_runtime_api.cc | 31 +++++++++++++++---- libcuda/cuobjdump.l | 1 + setup_environment | 3 +- src/abstract_hardware_model.h | 7 +++-- src/cuda-sim/cuda-sim.cc | 72 ++++++++++++++++++++++++++++--------------- src/cuda-sim/cuda-sim.h | 4 +-- src/cuda-sim/ptx.y | 2 ++ src/cuda-sim/ptx_ir.cc | 4 +-- src/cuda-sim/ptx_ir.h | 6 ++-- src/cuda-sim/ptx_loader.cc | 14 +++++---- src/cuda-sim/ptxinfo.l | 1 + src/cuda-sim/ptxinfo.y | 10 ++++-- src/gpgpu-sim/shader.cc | 4 +-- 15 files changed, 111 insertions(+), 54 deletions(-) diff --git a/CHANGES b/CHANGES index 7352d28..d03b93f 100644 --- a/CHANGES +++ b/CHANGES @@ -5,7 +5,8 @@ Version 3.2.3+edits (development branch) versus 3.2.3 the two default cache sizes, 16KB/48KB with 32/64 sets. - Added support for named barriers. - Added support for bar.arrive and bar.red instructions. - +- Initial support for CUDA 5.0,5.5 and 6.0 to get template running. + - Bug fixes: - Fixed bug #81, fix ordering of pushing branch entries to the stack diff --git a/Makefile b/Makefile index 0334168..080ca2d 100644 --- a/Makefile +++ b/Makefile @@ -152,6 +152,9 @@ $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib if [ ! -f $(SIM_LIB_DIR)/libcudart.so.2 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.2; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.3 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.3; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.4 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.4; fi + if [ ! -f $(SIM_LIB_DIR)/libcudart.so.5.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.5.0; fi + if [ ! -f $(SIM_LIB_DIR)/libcudart.so.5.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.5.5; fi + if [ ! -f $(SIM_LIB_DIR)/libcudart.so.6.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.6.0; fi $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib g++ -dynamiclib -Wl,-headerpad_max_install_names,-undefined,dynamic_lookup,-compatibility_version,1.1,-current_version,1.1\ diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 72ade49..eed4017 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -227,7 +227,12 @@ private: }; struct CUctx_st { - CUctx_st( _cuda_device_id *gpu ) { m_gpu = gpu; } + CUctx_st( _cuda_device_id *gpu ) + { + m_gpu = gpu; + m_binary_info.cmem = 0; + m_binary_info.gmem = 0; + } _cuda_device_id *get_device() { return m_gpu; } @@ -237,7 +242,7 @@ struct CUctx_st { m_last_fat_cubin_handle = fat_cubin_handle; } - void add_ptxinfo( const char *deviceFun, const struct gpgpu_ptx_sim_kernel_info &info ) + void add_ptxinfo( const char *deviceFun, const struct gpgpu_ptx_sim_info &info ) { symbol *s = m_code[m_last_fat_cubin_handle]->lookup(deviceFun); assert( s != NULL ); @@ -246,6 +251,11 @@ struct CUctx_st { f->set_kernel_info(info); } + void add_ptxinfo( const struct gpgpu_ptx_sim_info &info ) + { + m_binary_info = info; + } + void register_function( unsigned fat_cubin_handle, const char *hostFun, const char *deviceFun ) { if( m_code.find(fat_cubin_handle) != m_code.end() ) { @@ -271,6 +281,8 @@ private: std::map m_code; // fat binary handle => global symbol table unsigned m_last_fat_cubin_handle; std::map m_kernel_lookup; // unique id (CUDA app function address) => kernel entry point + struct gpgpu_ptx_sim_info m_binary_info; + }; class kernel_config { @@ -346,14 +358,22 @@ static CUctx_st* GPGPUSim_Context() void ptxinfo_addinfo() { - if( !strcmp("__cuda_dummy_entry__",get_ptxinfo_kname()) ) { + if(!get_ptxinfo_kname()){ + /* This info is not per kernel (since CUDA 5.0 some info (e.g. gmem, and cmem) is added at the beginning for the whole binary ) */ + CUctx_st *context = GPGPUSim_Context(); + print_ptxinfo(); + context->add_ptxinfo(get_ptxinfo()); + clear_ptxinfo(); + return; + } + if( !strcmp("__cuda_dummy_entry__",get_ptxinfo_kname()) ) { // this string produced by ptxas for empty ptx files (e.g., bandwidth test) clear_ptxinfo(); return; } CUctx_st *context = GPGPUSim_Context(); print_ptxinfo(); - context->add_ptxinfo( get_ptxinfo_kname(), get_ptxinfo_kinfo() ); + context->add_ptxinfo( get_ptxinfo_kname(), get_ptxinfo() ); clear_ptxinfo(); } @@ -1307,7 +1327,6 @@ void extract_code_using_cuobjdump(){ system(command); // Running cuobjdump using dynamic link to current process snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass %s > %s", app_binary.c_str(), fname); - printf("Running cuobjdump using \"%s\"\n", command); bool parse_output = true; int result = system(command); if(result) { @@ -1923,7 +1942,7 @@ cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, con CUctx_st *context = GPGPUSim_Context(); function_info *entry = context->get_kernel(hostFun); if( entry ) { - const struct gpgpu_ptx_sim_kernel_info *kinfo = entry->get_kernel_info(); + const struct gpgpu_ptx_sim_info *kinfo = entry->get_kernel_info(); attr->sharedSizeBytes = kinfo->smem; attr->constSizeBytes = kinfo->cmem; attr->localSizeBytes = kinfo->lmem; diff --git a/libcuda/cuobjdump.l b/libcuda/cuobjdump.l index d264338..d7086ad 100644 --- a/libcuda/cuobjdump.l +++ b/libcuda/cuobjdump.l @@ -103,6 +103,7 @@ newlines {newline}+
"producer = " return H_PRODUCER;
"host = " return H_HOST;
"compile_size = " return H_COMPILESIZE; +
"compressed"{newline}
"identifier = " BEGIN(endheader); return H_IDENTIFIER;
"has debug info"{newline} diff --git a/setup_environment b/setup_environment index f1a63f2..839da60 100644 --- a/setup_environment +++ b/setup_environment @@ -44,8 +44,7 @@ CC_VERSION=`gcc --version | head -1 | awk '{for(i=1;i<=NF;i++){ if(match($i,/^[0 CUDA_VERSION_STRING=`$CUDA_INSTALL_PATH/bin/nvcc --version | awk '/release/ {print $5;}' | sed 's/,//'`; CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("%02u%02u", 10*int($1), 10*$2);}'` if [ $CUDA_VERSION_NUMBER -gt 4020 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then - echo "ERROR ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; - return; + echo "WARNING ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; fi if [ $# = '1' ] ; diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 936d208..ba4ea29 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -443,6 +443,7 @@ private: unsigned m_texcache_linesize; }; + class gpgpu_t { public: gpgpu_t( const gpgpu_functional_sim_config &config ); @@ -497,7 +498,7 @@ protected: class memory_space *m_global_mem; class memory_space *m_tex_mem; class memory_space *m_surf_mem; - + unsigned long long m_dev_malloc; std::map m_NameToTextureRef; @@ -506,18 +507,20 @@ protected: std::map m_TextureRefToAttribute; }; -struct gpgpu_ptx_sim_kernel_info +struct gpgpu_ptx_sim_info { // Holds properties of the kernel (Kernel's resource use). // These will be set to zero if a ptxinfo file is not present. int lmem; int smem; int cmem; + int gmem; int regs; unsigned ptx_version; unsigned sm_target; }; + struct gpgpu_ptx_sim_arg { gpgpu_ptx_sim_arg() { m_start=NULL; } gpgpu_ptx_sim_arg(const void *arg, size_t size, size_t offset) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index ab54121..715be98 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1382,7 +1382,7 @@ void set_param_gpgpu_num_shaders(int num_shaders) gpgpu_param_num_shaders = num_shaders; } -const struct gpgpu_ptx_sim_kernel_info* ptx_sim_kernel_info(const function_info *kernel) +const struct gpgpu_ptx_sim_info* ptx_sim_kernel_info(const function_info *kernel) { return kernel->get_kernel_info(); } @@ -1867,7 +1867,7 @@ unsigned translate_pc_to_ptxlineno(unsigned pc) int g_ptxinfo_error_detected; static char *g_ptxinfo_kname = NULL; -static struct gpgpu_ptx_sim_kernel_info g_ptxinfo_kinfo; +static struct gpgpu_ptx_sim_info g_ptxinfo; const char *get_ptxinfo_kname() { @@ -1876,18 +1876,25 @@ const char *get_ptxinfo_kname() void print_ptxinfo() { - printf ("GPGPU-Sim PTX: Kernel \'%s\' : regs=%u, lmem=%u, smem=%u, cmem=%u\n", - get_ptxinfo_kname(), - g_ptxinfo_kinfo.regs, - g_ptxinfo_kinfo.lmem, - g_ptxinfo_kinfo.smem, - g_ptxinfo_kinfo.cmem ); + if(! get_ptxinfo_kname()){ + printf ("GPGPU-Sim PTX: Binary info : gmem=%u, cmem=%u\n", + g_ptxinfo.gmem, + g_ptxinfo.cmem); + } + if(get_ptxinfo_kname()){ + printf ("GPGPU-Sim PTX: Kernel \'%s\' : regs=%u, lmem=%u, smem=%u, cmem=%u\n", + get_ptxinfo_kname(), + g_ptxinfo.regs, + g_ptxinfo.lmem, + g_ptxinfo.smem, + g_ptxinfo.cmem ); + } } -struct gpgpu_ptx_sim_kernel_info get_ptxinfo_kinfo() +struct gpgpu_ptx_sim_info get_ptxinfo() { - return g_ptxinfo_kinfo; + return g_ptxinfo; } void ptxinfo_function(const char *fname ) @@ -1898,39 +1905,54 @@ void ptxinfo_function(const char *fname ) void ptxinfo_regs( unsigned nregs ) { - g_ptxinfo_kinfo.regs=nregs; + g_ptxinfo.regs=nregs; } void ptxinfo_lmem( unsigned declared, unsigned system ) { - g_ptxinfo_kinfo.lmem=declared+system; + g_ptxinfo.lmem=declared+system; +} + +void ptxinfo_gmem( unsigned declared, unsigned system ) +{ + g_ptxinfo.gmem=declared+system; } void ptxinfo_smem( unsigned declared, unsigned system ) { - g_ptxinfo_kinfo.smem=declared+system; + g_ptxinfo.smem=declared+system; } void ptxinfo_cmem( unsigned nbytes, unsigned bank ) { - g_ptxinfo_kinfo.cmem+=nbytes; + g_ptxinfo.cmem+=nbytes; } void clear_ptxinfo() { free(g_ptxinfo_kname); g_ptxinfo_kname=NULL; - g_ptxinfo_kinfo.regs=0; - g_ptxinfo_kinfo.lmem=0; - g_ptxinfo_kinfo.smem=0; - g_ptxinfo_kinfo.cmem=0; - g_ptxinfo_kinfo.ptx_version=0; - g_ptxinfo_kinfo.sm_target=0; + g_ptxinfo.regs=0; + g_ptxinfo.lmem=0; + g_ptxinfo.smem=0; + g_ptxinfo.cmem=0; + g_ptxinfo.gmem=0; + g_ptxinfo.ptx_version=0; + g_ptxinfo.sm_target=0; } void ptxinfo_opencl_addinfo( std::map &kernels ) { + + if(! g_ptxinfo_kname) { + printf ("GPGPU-Sim PTX: Binary info : gmem=%u, cmem=%u\n", + g_ptxinfo.gmem, + g_ptxinfo.cmem); + clear_ptxinfo(); + return; + } + if( !strcmp("__cuda_dummy_entry__",g_ptxinfo_kname) ) { // this string produced by ptxas for empty ptx files (e.g., bandwidth test) clear_ptxinfo(); @@ -1943,13 +1965,13 @@ void ptxinfo_opencl_addinfo( std::map &kernels ) } else { printf ("GPGPU-Sim PTX: Kernel \'%s\' : regs=%u, lmem=%u, smem=%u, cmem=%u\n", g_ptxinfo_kname, - g_ptxinfo_kinfo.regs, - g_ptxinfo_kinfo.lmem, - g_ptxinfo_kinfo.smem, - g_ptxinfo_kinfo.cmem ); + g_ptxinfo.regs, + g_ptxinfo.lmem, + g_ptxinfo.smem, + g_ptxinfo.cmem ); function_info *finfo = k->second; assert(finfo!=NULL); - finfo->set_kernel_info( g_ptxinfo_kinfo ); + finfo->set_kernel_info( g_ptxinfo ); } clear_ptxinfo(); } diff --git a/src/cuda-sim/cuda-sim.h b/src/cuda-sim/cuda-sim.h index 4c26350..958daba 100644 --- a/src/cuda-sim/cuda-sim.h +++ b/src/cuda-sim/cuda-sim.h @@ -73,7 +73,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, gpgpu_t *gpu, bool functionalSimulationMode = false); const warp_inst_t *ptx_fetch_inst( address_type pc ); -const struct gpgpu_ptx_sim_kernel_info* ptx_sim_kernel_info(const class function_info *kernel); +const struct gpgpu_ptx_sim_info* ptx_sim_kernel_info(const class function_info *kernel); void ptx_print_insn( address_type pc, FILE *fp ); std::string ptx_get_insn_str( address_type pc ); void set_param_gpgpu_num_shaders(int num_shaders); @@ -129,6 +129,6 @@ address_type get_return_pc( void *thd ); const char *get_ptxinfo_kname(); void print_ptxinfo(); void clear_ptxinfo(); -struct gpgpu_ptx_sim_kernel_info get_ptxinfo_kinfo(); +struct gpgpu_ptx_sim_info get_ptxinfo(); #endif diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 770ee1d..79faddf 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -239,6 +239,7 @@ function_ident_param: IDENTIFIER { add_function_name($1); } LEFT_PAREN {func_hea ; function_decl_header: ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } + | VISIBLE_DIRECTIVE ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } | FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } | VISIBLE_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } | EXTERN_DIRECTIVE FUNC_DIRECTIVE { $$ = 2; g_func_decl=1; func_header(".func"); } @@ -279,6 +280,7 @@ directive_statement: variable_declaration SEMI_COLON | TARGET_DIRECTIVE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER { target_header3($2,$4,$6); } | TARGET_DIRECTIVE IDENTIFIER { target_header($2); } | FILE_DIRECTIVE INT_OPERAND STRING { add_file($2,$3); } + | FILE_DIRECTIVE INT_OPERAND STRING COMMA INT_OPERAND COMMA INT_OPERAND { add_file($2,$3); } | LOC_DIRECTIVE INT_OPERAND INT_OPERAND INT_OPERAND | PRAGMA_DIRECTIVE STRING SEMI_COLON { add_pragma($2); } | function_decl SEMI_COLON {/*Do nothing*/} diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 490cb10..6943b48 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -843,14 +843,14 @@ void function_info::print_basic_block_dot() unsigned ptx_kernel_shmem_size( void *kernel_impl ) { function_info *f = (function_info*)kernel_impl; - const struct gpgpu_ptx_sim_kernel_info *kernel_info = f->get_kernel_info(); + const struct gpgpu_ptx_sim_info *kernel_info = f->get_kernel_info(); return kernel_info->smem; } unsigned ptx_kernel_nregs( void *kernel_impl ) { function_info *f = (function_info*)kernel_impl; - const struct gpgpu_ptx_sim_kernel_info *kernel_info = f->get_kernel_info(); + const struct gpgpu_ptx_sim_info *kernel_info = f->get_kernel_info(); return kernel_info->regs; } diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index b51406e..601a13d 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1229,12 +1229,12 @@ public: void param_to_shared( memory_space *shared_mem, symbol_table *symtab ); void list_param( FILE *fout ) const; - const struct gpgpu_ptx_sim_kernel_info* get_kernel_info () const + const struct gpgpu_ptx_sim_info* get_kernel_info () const { return &m_kernel_info; } - const void set_kernel_info (const struct gpgpu_ptx_sim_kernel_info &info) { + const void set_kernel_info (const struct gpgpu_ptx_sim_info &info) { m_kernel_info = info; m_kernel_info.ptx_version = 10*get_ptx_version().ver(); m_kernel_info.sm_target = get_ptx_version().target(); @@ -1282,7 +1282,7 @@ private: unsigned num_reconvergence_pairs; //Registers/shmem/etc. used (from ptxas -v), loaded from ___.ptxinfo along with ___.ptx - struct gpgpu_ptx_sim_kernel_info m_kernel_info; + struct gpgpu_ptx_sim_info m_kernel_info; symbol_table *m_symtab; diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 4ed57da..e293065 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -232,12 +232,14 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num ptxinfo_in = fopen(tempfile_ptxinfo,"r"); g_ptxinfo_filename = tempfile_ptxinfo; ptxinfo_parse(); - snprintf(commandline,1024,"rm -f %s %s %s", fname, fname2, tempfile_ptxinfo); - printf("GPGPU-Sim PTX: removing ptxinfo using \"%s\"\n", commandline); - result = system(commandline); - if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (c) %d\n", result); - exit(1); + if( ! g_save_embedded_ptx ) { + snprintf(commandline,1024,"rm -f %s %s %s", fname, fname2, tempfile_ptxinfo); + printf("GPGPU-Sim PTX: removing ptxinfo using \"%s\"\n", commandline); + result = system(commandline); + if( result != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (c) %d\n", result); + exit(1); + } } } diff --git a/src/cuda-sim/ptxinfo.l b/src/cuda-sim/ptxinfo.l index 18bf77d..99ee1fc 100644 --- a/src/cuda-sim/ptxinfo.l +++ b/src/cuda-sim/ptxinfo.l @@ -56,6 +56,7 @@ unsigned ptxinfo_col = 0; "lmem" TC; return LMEM; "smem" TC; return SMEM; "cmem" TC; return CMEM; +"gmem" TC; return GMEM; "line" TC; return LINE; "for" TC; return FOR; diff --git a/src/cuda-sim/ptxinfo.y b/src/cuda-sim/ptxinfo.y index e4ba6b2..294412d 100644 --- a/src/cuda-sim/ptxinfo.y +++ b/src/cuda-sim/ptxinfo.y @@ -42,6 +42,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token LMEM %token SMEM %token CMEM +%token GMEM %token IDENTIFIER %token PLUS %token COMMA @@ -65,6 +66,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. void ptxinfo_function(const char *fname ); void ptxinfo_regs( unsigned nregs ); void ptxinfo_lmem( unsigned declared, unsigned system ); + void ptxinfo_gmem( unsigned declared, unsigned system ); void ptxinfo_smem( unsigned declared, unsigned system ); void ptxinfo_cmem( unsigned nbytes, unsigned bank ); int ptxinfo_error(const char*); @@ -85,9 +87,10 @@ line_info: function_name | function_info { ptxinfo_addinfo(); } ; -function_name: FUNC QUOTE IDENTIFIER QUOTE { ptxinfo_function($3); } - | FUNC QUOTE IDENTIFIER QUOTE FOR QUOTE IDENTIFIER QUOTE { ptxinfo_function($3); } - +function_name: FUNC QUOTE IDENTIFIER QUOTE { ptxinfo_function($3); } + | FUNC QUOTE IDENTIFIER QUOTE FOR QUOTE IDENTIFIER QUOTE {ptxinfo_function($3); } + ; + function_info: info | function_info COMMA info ; @@ -96,6 +99,7 @@ info: USED INT_OPERAND REGS { ptxinfo_regs($2); } | tuple LMEM { ptxinfo_lmem(g_declared,g_system); } | tuple SMEM { ptxinfo_smem(g_declared,g_system); } | INT_OPERAND BYTES CMEM LEFT_SQUARE_BRACKET INT_OPERAND RIGHT_SQUARE_BRACKET { ptxinfo_cmem($1,$5); } + | INT_OPERAND BYTES GMEM { ptxinfo_gmem($1,0); } | INT_OPERAND BYTES LMEM { ptxinfo_lmem($1,0); } | INT_OPERAND BYTES SMEM { ptxinfo_smem($1,0); } | INT_OPERAND BYTES CMEM { ptxinfo_cmem($1,0); } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index b761dac..d11f12c 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -2392,7 +2392,7 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const //Limit by n_threads/shader unsigned int result_thread = n_thread_per_shader / padded_cta_size; - const struct gpgpu_ptx_sim_kernel_info *kernel_info = ptx_sim_kernel_info(kernel); + const struct gpgpu_ptx_sim_info *kernel_info = ptx_sim_kernel_info(kernel); //Limit by shmem/shader unsigned int result_shmem = (unsigned)-1; @@ -2412,7 +2412,7 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const result = gs_min2(result, result_regs); result = gs_min2(result, result_cta); - static const struct gpgpu_ptx_sim_kernel_info* last_kinfo = NULL; + static const struct gpgpu_ptx_sim_info* last_kinfo = NULL; if (last_kinfo != kernel_info) { //Only print out stats if kernel_info struct changes last_kinfo = kernel_info; printf ("GPGPU-Sim uArch: CTA/core = %u, limited by:", result); -- cgit v1.3 From 66d5ba0e9143b1bd6b839643bbffff6fb7db4aa6 Mon Sep 17 00:00:00 2001 From: Ahmed ElTantawy Date: Thu, 5 Mar 2015 12:41:31 -0800 Subject: update setup_environment to reflect the levels of support of CUDA versions --- setup_environment | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/setup_environment b/setup_environment index 839da60..c55d71f 100644 --- a/setup_environment +++ b/setup_environment @@ -43,8 +43,11 @@ CC_VERSION=`gcc --version | head -1 | awk '{for(i=1;i<=NF;i++){ if(match($i,/^[0 CUDA_VERSION_STRING=`$CUDA_INSTALL_PATH/bin/nvcc --version | awk '/release/ {print $5;}' | sed 's/,//'`; CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("%02u%02u", 10*int($1), 10*$2);}'` -if [ $CUDA_VERSION_NUMBER -gt 4020 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then - echo "WARNING ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; +if [ $CUDA_VERSION_NUMBER -gt 6000 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then + echo "ERROR ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; + return +elif [ $CUDA_VERSION_NUMBER -gt 4020 ]; then + echo "WARNING ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not fully tested with CUDA version $CUDA_VERSION_STRING (please see README)"; fi if [ $# = '1' ] ; -- cgit v1.3 From 6b9eb92bd0b03d69a2f2e9c075a8af99d860d4d1 Mon Sep 17 00:00:00 2001 From: Myrice Date: Tue, 7 Apr 2015 14:43:05 -0700 Subject: Booksim2 abandoned svn and moved to github (https://github.com/booksim/booksim2). This .svn folder is useless now and should be deleted. For further integration, a git submodule/git subtree may be used. Since I modified their source code, we cannot use git submodule/git subtree easily. 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src/intersim2/.svn/wc.db diff --git a/README b/README index 7ec45ea..4883e93 100644 --- a/README +++ b/README @@ -339,30 +339,3 @@ the applications you care about (implying these applications worked for you before you did the merge). You want to do this before making further changes to identify any compile time or runtime errors that occur due to the code merging process. - -3.2 (OPTIONAL) Updating Intersim2 (ADVANCED USERS ONLY) - -Booksim 2.0 is maintained by the Concurrent VLSI Architecture group at Stanford -(https://nocs.stanford.edu/cgi-bin/trac.cgi/wiki/Resources/BookSim). Intersim2 -is Booksim 2.0 with extentions. Booksim 2.0 is still under active development, -with updates that usually bring cutting edge features and bug fixes. If you want -these new features or bug fixes, it is possible to pull updates from Booksim 2.0 - server and apply the updates to Intersim2. You can follow the instructions -below to update Intersim2 with the new Booksim 2.0. - -As above, YOU SHOULD BACKUP YOUR CHANGES BEFORE PROCEEDING. - -The Booksim 2.0 uses svn source control. First, go to the Intersim2 root -directory($GPGPUSIM_ROOT/src/intersim2) in the terminal. Then, run the -following command in terminal: - -svn update - -While svn is updating your local copy of Intersim2 with the latest changes from -the Booksim 2.0 svn server, conflicts might arise due to changes that either we -or you made that conflict with the latest updates. In this case, svn will prompt -you to edit conflict files using default text editor or you can postpone it and -then using your favorite merge tool to resolve conflict files. - -After you updated Intersim2, you should test the merged version through the -instructions described in Section 3.1. diff --git a/src/intersim2/.svn/entries b/src/intersim2/.svn/entries deleted file mode 100644 index 48082f7..0000000 --- a/src/intersim2/.svn/entries +++ /dev/null @@ -1 +0,0 @@ -12 diff --git a/src/intersim2/.svn/format b/src/intersim2/.svn/format deleted file mode 100644 index 48082f7..0000000 --- a/src/intersim2/.svn/format +++ /dev/null @@ -1 +0,0 @@ -12 diff --git a/src/intersim2/.svn/pristine/04/043985cd8560fd203de2c2d82735f1e5ecf3783d.svn-base b/src/intersim2/.svn/pristine/04/043985cd8560fd203de2c2d82735f1e5ecf3783d.svn-base deleted file mode 100644 index bccc4db..0000000 --- a/src/intersim2/.svn/pristine/04/043985cd8560fd203de2c2d82735f1e5ecf3783d.svn-base +++ /dev/null @@ -1,79 +0,0 @@ -// $Id$ - -// Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -// Dragonfly -// - - - - -vc_buf_size = 256; - - -wait_for_tail_credit = 0; - -// -// Router architecture -// -vc_allocator = separable_input_first; -sw_allocator = separable_input_first; -alloc_iters = 1; - -credit_delay = 2; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; -st_final_delay = 1; - -input_speedup = 1; -output_speedup = 1; -internal_speedup = 2.0; - - -warmup_periods = 3; -sim_count = 1; - -sample_period = 10000; - - - -routing_function = min; -num_vcs = 2; - -priority = none; -traffic = uniform; - -injection_rate = 0.8; -packet_size = 10; -injection_rate_uses_flits=1; - -topology = dragonflynew; - -k = 4; -n = 1; - -watch_out=-; - diff --git a/src/intersim2/.svn/pristine/05/05a079244c124bc5d781812aac07878c6956ef46.svn-base b/src/intersim2/.svn/pristine/05/05a079244c124bc5d781812aac07878c6956ef46.svn-base deleted file mode 100644 index 168d973..0000000 --- a/src/intersim2/.svn/pristine/05/05a079244c124bc5d781812aac07878c6956ef46.svn-base +++ /dev/null @@ -1,1331 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -//Flattened butterfly simulator -//Created by John Kim -// -//Updated 11/6/2007 by Ted Jiang, now scales -//with any n such that N = K^3, k is a power of 2 -//however, the change restrict it to a 2D FBfly -// -//updated sometimes in december by Ted Jiang, now works for updat to 4 -//dimension. -// -//Updated 2/4/08 by Ted Jiang disabling partial networks -//change concentrations -// -//More update 3/31/08 to correctly assign the nodes to the routers -//UGAL now has added a "mapping" to account for this new assignment -//of the nodes to the routers -// -//Updated by mihelog 27 Aug to add progressive choice of intermediate destination. -//Also, half of the total vcs are used for non-minimal routing, others for minimal (for UGAL and valiant). - - -#include "booksim.hpp" -#include -#include -#include -#include -#include "flatfly_onchip.hpp" -#include "random_utils.hpp" -#include "misc_utils.hpp" -#include "globals.hpp" - - - -//#define DEBUG_FLATFLY - -static int _xcount; -static int _ycount; -static int _xrouter; -static int _yrouter; - -FlatFlyOnChip::FlatFlyOnChip( const Configuration &config, const string & name ) : - Network( config, name ) -{ - - _ComputeSize( config ); - _Alloc( ); - _BuildNet( config ); -} - -void FlatFlyOnChip::_ComputeSize( const Configuration &config ) -{ - _k = config.GetInt( "k" ); // # of routers per dimension - _n = config.GetInt( "n" ); // dimension - _c = config.GetInt( "c" ); //concentration, may be different from k - _r = _c + (_k-1)*_n ; // total radix of the switch ( # of inputs/outputs) - - //how many routers in the x or y direction - _xcount = config.GetInt("x"); - _ycount = config.GetInt("y"); - assert(_xcount == _ycount); - //configuration of hohw many clients in X and Y per router - _xrouter = config.GetInt("xr"); - _yrouter = config.GetInt("yr"); - assert(_xrouter == _yrouter); - gK = _k; - gN = _n; - gC = _c; - - assert(_c == _xrouter*_yrouter); - - _nodes = powi( _k, _n )*_c; //network size - - _num_of_switch = _nodes / _c; - _channels = _num_of_switch * (_r - _c); - _size = _num_of_switch; - -} - -void FlatFlyOnChip::_BuildNet( const Configuration &config ) -{ - int _output; - - ostringstream router_name; - - - if(gTrace){ - - cout<<"Setup Finished Router"<1){ - ileng+=(abs(yleng)-1); - } - //measure distance in the x direction - if(abs(xleng)>1){ - ileng+=(abs(xleng)-1); - } - //increment for the next client, add Y, if full, reset y add x - yleng++; - if(yleng>_yrouter/2){ - yleng= -_yrouter/2; - xleng++; - } - //adopted from the CMESH, the first node has 0,1,8,9 (as an example) - int link = (_xcount * _xrouter) * (_yrouter * y_index + y) + (_xrouter * x_index + x) ; - - if(use_noc_latency){ - _inject[link]->SetLatency(ileng); - _inject_cred[link]->SetLatency(ileng); - _eject[link] ->SetLatency(ileng); - _eject_cred[link]->SetLatency(ileng); - } else { - _inject[link]->SetLatency(1); - _inject_cred[link]->SetLatency(1); - _eject[link] ->SetLatency(1); - _eject_cred[link]->SetLatency(1); - } - _routers[node]->AddInputChannel( _inject[link], _inject_cred[link] ); - -#ifdef DEBUG_FLATFLY - cout << " Adding injection channel " << link << endl; -#endif - - _routers[node]->AddOutputChannel( _eject[link], _eject_cred[link] ); -#ifdef DEBUG_FLATFLY - cout << " Adding ejection channel " << link << endl; -#endif - } - } - } - //****************************************************************** - // add output inter-router channels - //****************************************************************** - - //for every router, in every dimension - for ( int node = 0; node < _num_of_switch; ++node ) { - for ( int dim = 0; dim < _n; ++dim ) { - - //locate itself in every dimension - int xcurr = node%_k; - int ycurr = (int)(node/_k); - int curr3 = node%(_k*_k); - int curr4 = (int)(node/(_k*_k)); - int curr5 = (int)(node/(_k*_k*_k));//mmm didn't mean to be racist - int curr6 = (node%(_k*_k*_k));//mmm didn't mean to be racist - - //for every other router in the dimension - for ( int cnt = 0; cnt < (_k ); ++cnt ) { - int other=0; //the other router that we are trying to connect - int offset = 0; //silly ness when node< other or when node>other - //if xdimension - if(dim == 0){ - other = ycurr * _k +cnt; - } else if (dim ==1){ - other = cnt * _k + xcurr; - if(_n==3){ - other+= curr4*_k*_k; - } - if(_n==4){ - curr4=((int)(node/(_k*_k)))%_k; - other+= curr4*_k*_k+curr5*_k*_k*_k; - } - }else if (dim ==2){ - other = cnt*_k*_k + curr3; - if(_n==4){ - other+= curr5*_k*_k*_k; - } - }else if (dim ==3){ - other = cnt*_k*_k*_k+curr6; - } - assert(dim < 4); - if(other == node){ -#ifdef DEBUG_FLATFLY - cout << "ignore channel : " << _output << " to node " << node <<" and "<SetLatency(length); - _chan_cred[_output]->SetLatency(length); - } else { - _chan[_output]->SetLatency(1); - _chan_cred[_output]->SetLatency(1); - } - _routers[node]->AddOutputChannel( _chan[_output], _chan_cred[_output] ); - - _routers[other]->AddInputChannel( _chan[_output], _chan_cred[_output]); - - if(gTrace){ - cout<<"Link "<<_output<<" "< Virtual Channel Range - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - int dest = flatfly_transformation(f->dest); - int targetr = (int)(dest/gC); - - if(targetr==r->GetID()){ //if we are at the final router, yay, output to client - out_port = dest % gC; - - } else { - - //each class must have at least 2 vcs assigned or else xy_yx will deadlock - int const available_vcs = (vcEnd - vcBegin + 1) / 2; - assert(available_vcs > 0); - - int out_port_xy = flatfly_outport(dest, r->GetID()); - int out_port_yx = flatfly_outport_yx(dest, r->GetID()); - - // Route order (XY or YX) determined when packet is injected - // into the network, adaptively - bool x_then_y; - if(in_channel < gC){ - int credit_xy = r->GetUsedCredit(out_port_xy); - int credit_yx = r->GetUsedCredit(out_port_yx); - if(credit_xy > credit_yx) { - x_then_y = false; - } else if(credit_xy < credit_yx) { - x_then_y = true; - } else { - x_then_y = (RandomInt(1) > 0); - } - } else { - x_then_y = (f->vc < (vcBegin + available_vcs)); - } - - if(x_then_y) { - out_port = out_port_xy; - vcEnd -= available_vcs; - } else { - out_port = out_port_yx; - vcBegin += available_vcs; - } - } - - } - - outputs->Clear( ); - - outputs->AddRange( out_port , vcBegin, vcEnd ); -} - -//The initial XY or YX minimal routing direction is chosen randomly -void xyyx_flatfly( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - // ( Traffic Class , Routing Order ) -> Virtual Channel Range - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - int dest = flatfly_transformation(f->dest); - int targetr = (int)(dest/gC); - - if(targetr==r->GetID()){ //if we are at the final router, yay, output to client - out_port = dest % gC; - - } else { - - //each class must have at least 2 vcs assigned or else xy_yx will deadlock - int const available_vcs = (vcEnd - vcBegin + 1) / 2; - assert(available_vcs > 0); - - // randomly select dimension order at first hop - bool x_then_y = ((in_channel < gC) ? - (RandomInt(1) > 0) : - (f->vc < (vcBegin + available_vcs))); - - if(x_then_y) { - out_port = flatfly_outport(dest, r->GetID()); - vcEnd -= available_vcs; - } else { - out_port = flatfly_outport_yx(dest, r->GetID()); - vcBegin += available_vcs; - } - } - - } - - outputs->Clear( ); - - outputs->AddRange( out_port , vcBegin, vcEnd ); -} - -int flatfly_outport_yx(int dest, int rID) { - int dest_rID = (int) (dest / gC); - int _dim = gN; - int output = -1, dID, sID; - - if(dest_rID==rID){ - return dest % gC; - } - - for (int d=_dim-1;d >= 0; d--) { - int power = powi(gK,d); - dID = int(dest_rID / power); - sID = int(rID / power); - if ( dID != sID ) { - output = gC + ((gK-1)*d) - 1; - if (dID > sID) { - output += dID; - } else { - output += dID + 1; - } - return output; - } - dest_rID = (int) (dest_rID %power); - rID = (int) (rID %power); - } - if (output == -1) { - cout << " ERROR ---- FLATFLY_OUTPORT function : output not found yx" << endl; - exit(-1); - } - return -1; -} - -void valiant_flatfly( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - // ( Traffic Class , Routing Order ) -> Virtual Channel Range - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - if ( in_channel < gC ){ - f->ph = 0; - f->intm = RandomInt( powi( gK, gN )*gC-1); - } - - int intm = flatfly_transformation(f->intm); - int dest = flatfly_transformation(f->dest); - - if((int)(intm/gC) == r->GetID() || (int)(dest/gC)== r->GetID()){ - f->ph = 1; - } - - if(f->ph == 0) { - out_port = flatfly_outport(intm, r->GetID()); - } else { - assert(f->ph == 1); - out_port = flatfly_outport(dest, r->GetID()); - } - - if((int)(dest/gC) != r->GetID()) { - - //each class must have at least 2 vcs assigned or else valiant valiant will deadlock - int const available_vcs = (vcEnd - vcBegin + 1) / 2; - assert(available_vcs > 0); - - if(f->ph == 0) { - vcEnd -= available_vcs; - } else { - // If routing to final destination use the second half of the VCs. - assert(f->ph == 1); - vcBegin += available_vcs; - } - } - - } - - outputs->Clear( ); - - outputs->AddRange( out_port , vcBegin, vcEnd ); -} - -void min_flatfly( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - // ( Traffic Class , Routing Order ) -> Virtual Channel Range - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - int dest = flatfly_transformation(f->dest); - int targetr= (int)(dest/gC); - //int xdest = ((int)(dest/gC)) % gK; - //int xcurr = ((r->GetID())) % gK; - - //int ydest = ((int)(dest/gC)) / gK; - //int ycurr = ((r->GetID())) / gK; - - if(targetr==r->GetID()){ //if we are at the final router, yay, output to client - out_port = dest % gC; - } else{ //else select a dimension at random - out_port = flatfly_outport(dest, r->GetID()); - } - - } - - outputs->Clear( ); - - outputs->AddRange( out_port , vcBegin, vcEnd ); -} - -//=============================================================^M -// route UGAL in the flattened butterfly -//=============================================================^M - - -//same as ugal except uses xyyx routing -void ugal_xyyx_flatfly_onchip( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - // ( Traffic Class , Routing Order ) -> Virtual Channel Range - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - int dest = flatfly_transformation(f->dest); - - int rID = r->GetID(); - int _concentration = gC; - int found; - int debug = 0; - int tmp_out_port, _ran_intm; - int _min_hop, _nonmin_hop, _min_queucnt, _nonmin_queucnt; - int threshold = 2; - - - if ( in_channel < gC ){ - if(gTrace){ - cout<<"New Flit "<src<ph = 0; - } - - if(gTrace){ - int load = 0; - cout<<"Router "<GetBufferOccupancy(in_channel); - cout<<"Rload "<id << " Router: " << rID << " routing from src : " << f->src << " to dest : " << dest << " f->ph: " <ph << " intm: " << f->intm << endl; - } - // f->ph == 0 ==> make initial global adaptive decision - // f->ph == 1 ==> route nonminimaly to random intermediate node - // f->ph == 2 ==> route minimally to destination - - found = 0; - - if (f->ph == 1){ - dest = f->intm; - } - - if (dest >= rID*_concentration && dest < (rID+1)*_concentration) { - if (f->ph == 1) { - f->ph = 2; - dest = flatfly_transformation(f->dest); - if (debug) cout << " done routing to intermediate "; - } - else { - found = 1; - out_port = dest % gC; - if (debug) cout << " final routing to destination "; - } - } - - if (!found) { - - int const xy_available_vcs = (vcEnd - vcBegin + 1) / 2; - assert(xy_available_vcs > 0); - - // randomly select dimension order at first hop - bool x_then_y = ((in_channel < gC) ? - (RandomInt(1) > 0) : - (f->vc < (vcBegin + xy_available_vcs))); - - if (f->ph == 0) { - //find the min port and min distance - _min_hop = find_distance(flatfly_transformation(f->src),dest); - if(x_then_y){ - tmp_out_port = flatfly_outport(dest, rID); - } else { - tmp_out_port = flatfly_outport_yx(dest, rID); - } - if (f->watch){ - cout << " MIN tmp_out_port: " << tmp_out_port; - } - //sum over all vcs of that port - _min_queucnt = r->GetUsedCredit(tmp_out_port); - - //find the nonmin router, nonmin port, nonmin count - _ran_intm = find_ran_intm(flatfly_transformation(f->src), dest); - _nonmin_hop = find_distance(flatfly_transformation(f->src),_ran_intm) + find_distance(_ran_intm, dest); - if(x_then_y){ - tmp_out_port = flatfly_outport(_ran_intm, rID); - } else { - tmp_out_port = flatfly_outport_yx(_ran_intm, rID); - } - - if (f->watch){ - cout << " NONMIN tmp_out_port: " << tmp_out_port << endl; - } - if (_ran_intm >= rID*_concentration && _ran_intm < (rID+1)*_concentration) { - _nonmin_queucnt = numeric_limits::max(); - } else { - _nonmin_queucnt = r->GetUsedCredit(tmp_out_port); - } - - if (debug){ - cout << " _min_hop " << _min_hop << " _min_queucnt: " <<_min_queucnt << " _nonmin_hop: " << _nonmin_hop << " _nonmin_queucnt :" << _nonmin_queucnt << endl; - } - - if (_min_hop * _min_queucnt <= _nonmin_hop * _nonmin_queucnt +threshold) { - - if (debug) cout << " Route MINIMALLY " << endl; - f->ph = 2; - } else { - // route non-minimally - if (debug) { cout << " Route NONMINIMALLY int node: " <<_ran_intm << endl; } - f->ph = 1; - f->intm = _ran_intm; - dest = f->intm; - if (dest >= rID*_concentration && dest < (rID+1)*_concentration) { - f->ph = 2; - dest = flatfly_transformation(f->dest); - } - } - } - - //dest here should be == intm if ph==1, or dest == dest if ph == 2 - if(x_then_y){ - out_port = flatfly_outport(dest, rID); - if(out_port >= gC) { - vcEnd -= xy_available_vcs; - } - } else { - out_port = flatfly_outport_yx(dest, rID); - if(out_port >= gC) { - vcBegin += xy_available_vcs; - } - } - - // if we haven't reached our destination, restrict VCs appropriately to avoid routing deadlock - if(out_port >= gC) { - - int const ph_available_vcs = xy_available_vcs / 2; - assert(ph_available_vcs > 0); - - if(f->ph == 1) { - vcEnd -= ph_available_vcs; - } else { - assert(f->ph == 2); - vcBegin += ph_available_vcs; - } - } - - found = 1; - } - - if (!found) { - cout << " ERROR: output not found in routing. " << endl; - cout << *f; exit (-1); - } - - if (out_port >= gN*(gK-1) + gC) { - cout << " ERROR: output port too big! " << endl; - cout << " OUTPUT select: " << out_port << endl; - cout << " router radix: " << gN*(gK-1) + gK << endl; - exit (-1); - } - - if (debug) cout << " through output port : " << out_port << endl; - if(gTrace){cout<<"Outport "<Clear( ); - - outputs->AddRange( out_port , vcBegin, vcEnd ); -} - - - -//ugal now uses modified comparison, modefied getcredit -void ugal_flatfly_onchip( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - // ( Traffic Class , Routing Order ) -> Virtual Channel Range - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - int dest = flatfly_transformation(f->dest); - - int rID = r->GetID(); - int _concentration = gC; - int found; - int debug = 0; - int tmp_out_port, _ran_intm; - int _min_hop, _nonmin_hop, _min_queucnt, _nonmin_queucnt; - int threshold = 2; - - if ( in_channel < gC ){ - if(gTrace){ - cout<<"New Flit "<src<ph = 0; - } - - if(gTrace){ - int load = 0; - cout<<"Router "<GetBufferOccupancy(in_channel); - cout<<"Rload "<id << " Router: " << rID << " routing from src : " << f->src << " to dest : " << dest << " f->ph: " <ph << " intm: " << f->intm << endl; - } - // f->ph == 0 ==> make initial global adaptive decision - // f->ph == 1 ==> route nonminimaly to random intermediate node - // f->ph == 2 ==> route minimally to destination - - found = 0; - - if (f->ph == 1){ - dest = f->intm; - } - - - if (dest >= rID*_concentration && dest < (rID+1)*_concentration) { - - if (f->ph == 1) { - f->ph = 2; - dest = flatfly_transformation(f->dest); - if (debug) cout << " done routing to intermediate "; - } - else { - found = 1; - out_port = dest % gC; - if (debug) cout << " final routing to destination "; - } - } - - if (!found) { - - if (f->ph == 0) { - _min_hop = find_distance(flatfly_transformation(f->src),dest); - _ran_intm = find_ran_intm(flatfly_transformation(f->src), dest); - tmp_out_port = flatfly_outport(dest, rID); - if (f->watch){ - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << " MIN tmp_out_port: " << tmp_out_port; - } - - _min_queucnt = r->GetUsedCredit(tmp_out_port); - - _nonmin_hop = find_distance(flatfly_transformation(f->src),_ran_intm) + find_distance(_ran_intm, dest); - tmp_out_port = flatfly_outport(_ran_intm, rID); - - if (f->watch){ - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << " NONMIN tmp_out_port: " << tmp_out_port << endl; - } - if (_ran_intm >= rID*_concentration && _ran_intm < (rID+1)*_concentration) { - _nonmin_queucnt = numeric_limits::max(); - } else { - _nonmin_queucnt = r->GetUsedCredit(tmp_out_port); - } - - if (debug){ - cout << " _min_hop " << _min_hop << " _min_queucnt: " <<_min_queucnt << " _nonmin_hop: " << _nonmin_hop << " _nonmin_queucnt :" << _nonmin_queucnt << endl; - } - - if (_min_hop * _min_queucnt <= _nonmin_hop * _nonmin_queucnt +threshold) { - - if (debug) cout << " Route MINIMALLY " << endl; - f->ph = 2; - } else { - // route non-minimally - if (debug) { cout << " Route NONMINIMALLY int node: " <<_ran_intm << endl; } - f->ph = 1; - f->intm = _ran_intm; - dest = f->intm; - if (dest >= rID*_concentration && dest < (rID+1)*_concentration) { - f->ph = 2; - dest = flatfly_transformation(f->dest); - } - } - } - - // find minimal correct dimension to route through - out_port = flatfly_outport(dest, rID); - - // if we haven't reached our destination, restrict VCs appropriately to avoid routing deadlock - if(out_port >= gC) { - int const available_vcs = (vcEnd - vcBegin + 1) / 2; - assert(available_vcs > 0); - if(f->ph == 1) { - vcEnd -= available_vcs; - } else { - assert(f->ph == 2); - vcBegin += available_vcs; - } - } - - found = 1; - } - - if (!found) { - cout << " ERROR: output not found in routing. " << endl; - cout << *f; exit (-1); - } - - if (out_port >= gN*(gK-1) + gC) { - cout << " ERROR: output port too big! " << endl; - cout << " OUTPUT select: " << out_port << endl; - cout << " router radix: " << gN*(gK-1) + gK << endl; - exit (-1); - } - - if (debug) cout << " through output port : " << out_port << endl; - if(gTrace) { - cout<<"Outport "<Clear( ); - - outputs->AddRange( out_port , vcBegin, vcEnd ); -} - - -// partially non-interfering (i.e., packets ordered by hash of destination) UGAL -void ugal_pni_flatfly_onchip( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - // ( Traffic Class , Routing Order ) -> Virtual Channel Range - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - int dest = flatfly_transformation(f->dest); - - int rID = r->GetID(); - int _concentration = gC; - int found; - int debug = 0; - int tmp_out_port, _ran_intm; - int _min_hop, _nonmin_hop, _min_queucnt, _nonmin_queucnt; - int threshold = 2; - - if ( in_channel < gC ){ - if(gTrace){ - cout<<"New Flit "<src<ph = 0; - } - - if(gTrace){ - int load = 0; - cout<<"Router "<GetBufferOccupancy(in_channel); - cout<<"Rload "<id << " Router: " << rID << " routing from src : " << f->src << " to dest : " << dest << " f->ph: " <ph << " intm: " << f->intm << endl; - } - // f->ph == 0 ==> make initial global adaptive decision - // f->ph == 1 ==> route nonminimaly to random intermediate node - // f->ph == 2 ==> route minimally to destination - - found = 0; - - if (f->ph == 1){ - dest = f->intm; - } - - - if (dest >= rID*_concentration && dest < (rID+1)*_concentration) { - - if (f->ph == 1) { - f->ph = 2; - dest = flatfly_transformation(f->dest); - if (debug) cout << " done routing to intermediate "; - } - else { - found = 1; - out_port = dest % gC; - if (debug) cout << " final routing to destination "; - } - } - - if (!found) { - - if (f->ph == 0) { - _min_hop = find_distance(flatfly_transformation(f->src),dest); - _ran_intm = find_ran_intm(flatfly_transformation(f->src), dest); - tmp_out_port = flatfly_outport(dest, rID); - if (f->watch){ - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << " MIN tmp_out_port: " << tmp_out_port; - } - - _min_queucnt = r->GetUsedCredit(tmp_out_port); - - _nonmin_hop = find_distance(flatfly_transformation(f->src),_ran_intm) + find_distance(_ran_intm, dest); - tmp_out_port = flatfly_outport(_ran_intm, rID); - - if (f->watch){ - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << " NONMIN tmp_out_port: " << tmp_out_port << endl; - } - if (_ran_intm >= rID*_concentration && _ran_intm < (rID+1)*_concentration) { - _nonmin_queucnt = numeric_limits::max(); - } else { - _nonmin_queucnt = r->GetUsedCredit(tmp_out_port); - } - - if (debug){ - cout << " _min_hop " << _min_hop << " _min_queucnt: " <<_min_queucnt << " _nonmin_hop: " << _nonmin_hop << " _nonmin_queucnt :" << _nonmin_queucnt << endl; - } - - if (_min_hop * _min_queucnt <= _nonmin_hop * _nonmin_queucnt +threshold) { - - if (debug) cout << " Route MINIMALLY " << endl; - f->ph = 2; - } else { - // route non-minimally - if (debug) { cout << " Route NONMINIMALLY int node: " <<_ran_intm << endl; } - f->ph = 1; - f->intm = _ran_intm; - dest = f->intm; - if (dest >= rID*_concentration && dest < (rID+1)*_concentration) { - f->ph = 2; - dest = flatfly_transformation(f->dest); - } - } - } - - // find minimal correct dimension to route through - out_port = flatfly_outport(dest, rID); - - // if we haven't reached our destination, restrict VCs appropriately to avoid routing deadlock - if(out_port >= gC) { - int const available_vcs = (vcEnd - vcBegin + 1) / 2; - assert(available_vcs > 0); - if(f->ph == 1) { - vcEnd -= available_vcs; - } else { - assert(f->ph == 2); - vcBegin += available_vcs; - } - } - - found = 1; - } - - if (!found) { - cout << " ERROR: output not found in routing. " << endl; - cout << *f; exit (-1); - } - - if (out_port >= gN*(gK-1) + gC) { - cout << " ERROR: output port too big! " << endl; - cout << " OUTPUT select: " << out_port << endl; - cout << " router radix: " << gN*(gK-1) + gK << endl; - exit (-1); - } - - if (debug) cout << " through output port : " << out_port << endl; - if(gTrace) { - cout<<"Outport "<= gC)) { - - // NOTE: for "proper" flattened butterfly configurations (i.e., ones - // derived from flattening an actual butterfly), gK and gC are the same! - assert(gK == gC); - - assert(inject ? (f->ph == -1) : (f->ph == 1 || f->ph == 2)); - - int next_coord = flatfly_transformation(f->dest); - if(inject) { - next_coord /= gC; - next_coord %= gK; - } else { - int next_dim = (out_port - gC) / (gK - 1) + 1; - if(next_dim == gN) { - next_coord %= gC; - } else { - next_coord /= gC; - for(int d = 0; d < next_dim; ++d) { - next_coord /= gK; - } - next_coord %= gK; - } - } - assert(next_coord >= 0 && next_coord < gK); - int vcs_per_dest = (vcEnd - vcBegin + 1) / gK; - assert(vcs_per_dest > 0); - vcBegin += next_coord * vcs_per_dest; - vcEnd = vcBegin + vcs_per_dest - 1; - } - - outputs->Clear( ); - - outputs->AddRange( out_port , vcBegin, vcEnd ); -} - - -//=============================================================^M -// UGAL : calculate distance (hop cnt) between src and destination -//=============================================================^M -int find_distance (int src, int dest) { - int dist = 0; - int _dim = gN; - int _dim_size; - - int src_tmp= (int) src / gC; - int dest_tmp = (int) dest / gC; - int src_id, dest_id; - - // cout << " HOP CNT between src: " << src << " dest: " << dest; - for (int d=0;d < _dim; d++) { - _dim_size = powi(gK, d )*gC; - //if ((int)(src / _dim_size) != (int)(dest / _dim_size)) - // dist++; - src_id = src_tmp % gK; - dest_id = dest_tmp % gK; - if (src_id != dest_id) - dist++; - src_tmp = (int) (src_tmp / gK); - dest_tmp = (int) (dest_tmp / gK); - } - - // cout << " : " << dist << endl; - - return dist; -} - -//=============================================================^M -// UGAL : find random node for load balancing -//=============================================================^M -int find_ran_intm (int src, int dest) { - int _dim = gN; - int _dim_size; - int _ran_dest = 0; - int debug = 0; - - if (debug) - cout << " INTM node for src: " << src << " dest: " < thus generate a random destination within - _ran_dest += RandomInt(gK - 1) * _dim_size; - if (debug) - cout << " different dimension : " << d << " int node : " << _ran_dest << " _dim_size: " << _dim_size << endl; - } - src = (int) (src / gK); - dest = (int) (dest / gK); - } - - if (debug) cout << " intermediate destination NODE: " << _ran_dest << endl; - return _ran_dest; -} - - - -//============================================================= -// UGAL : calculated minimum distance output port for flatfly -// given the dimension and destination -//============================================================= -// starting from DIM 0 (x first) -int flatfly_outport(int dest, int rID) { - int dest_rID = (int) (dest / gC); - int _dim = gN; - int output = -1, dID, sID; - - if(dest_rID==rID){ - return dest % gC; - } - - - for (int d=0;d < _dim; d++) { - dID = (dest_rID % gK); - sID = (rID % gK); - if ( dID != sID ) { - output = gC + ((gK-1)*d) - 1; - if (dID > sID) { - - output += dID; - } else { - output += dID + 1; - } - - return output; - } - dest_rID = (int) (dest_rID / gK); - rID = (int) (rID / gK); - } - if (output == -1) { - cout << " ERROR ---- FLATFLY_OUTPORT function : output not found " << endl; - exit(-1); - } - return -1; -} - -int flatfly_transformation(int dest){ - //the magic of destination transformation - - //destination transformation, translate how the nodes are actually arranged - //to the easier way of routing - //this transformation only support 64 nodes - - //cout<<"ORiginal destination "< -#include -#include - -#include "fattree.hpp" -#include "misc_utils.hpp" - - - //#define FATTREE_DEBUG - -FatTree::FatTree( const Configuration& config,const string & name ) - : Network( config ,name) -{ - - - _ComputeSize( config ); - _Alloc( ); - _BuildNet( config ); - -} - -void FatTree::_ComputeSize( const Configuration& config ) -{ - - _k = config.GetInt( "k" ); - _n = config.GetInt( "n" ); - - gK = _k; gN = _n; - - _nodes = powi( _k, _n ); - - //levels * routers_per_level - _size = _n * powi( _k , _n - 1 ); - - //(channels per level = k*routers_per_level* up/down) * (levels-1) - _channels = (2*_k * powi( _k , _n-1 ))*(_n-1); - - -} - - -void FatTree::RegisterRoutingFunctions() { - -} - -void FatTree::_BuildNet( const Configuration& config ) -{ - cout << "Fat Tree" << endl; - cout << " k = " << _k << " levels = " << _n << endl; - cout << " each switch - total radix = "<< 2*_k << endl; - cout << " # of switches = "<< _size << endl; - cout << " # of channels = "<< _channels << endl; - cout << " # of nodes ( size of network ) = " << _nodes << endl; - - - // Number of router positions at each depth of the network - const int nPos = powi( _k, _n-1); - - // - // Allocate Routers - // - ostringstream name; - int level, pos, id, degree, port; - for ( level = 0 ; level < _n ; ++level ) { - for ( pos = 0 ; pos < nPos ; ++pos ) { - - if ( level == 0 ) //top routers is zero - degree = _k; - else - degree = 2 * _k; - - id = level * nPos + pos; - - name.str(""); - name << "router_level" << level << "_" << pos; - Router * r = Router::NewRouter( config, this, name.str( ), id, - degree, degree ); - _Router( level, pos ) = r; - _timed_modules.push_back(r); - } - } - - // - // Connect Channels to Routers - // - - // - // Router Connection Rule: Output Ports =gK Move UP Network - // Input Ports =gK from up Network - - // Connecting Injection & Ejection Channels - for ( pos = 0 ; pos < nPos ; ++pos ) { - for(int index = 0; index<_k; index++){ - int link = pos*_k + index; - _Router( _n-1, pos)->AddInputChannel( _inject[link], - _inject_cred[link]); - _Router( _n-1, pos)->AddOutputChannel( _eject[link], - _eject_cred[link]); - _inject[link]->SetLatency( 1 ); - _inject_cred[link]->SetLatency( 1 ); - _eject[link]->SetLatency( 1 ); - _eject_cred[link]->SetLatency( 1 ); - } - } - -#ifdef FATTREE_DEBUG - cout<<"\nAssigning output\n"; -#endif - - //channels are numbered sequentially from an output channel perspective - int chan_per_direction = (_k * powi( _k , _n-1 )); //up or down - int chan_per_level = 2*(_k * powi( _k , _n-1 )); //up+down - - //connect all down output channels - //level n-1's down channel are injection channels - for (level = 0; level<_n-1; level++){ - for ( pos = 0; pos < nPos; ++pos ) { - for ( port = 0; port < _k; ++port ) { - int link = (level*chan_per_level) + pos*_k + port; - _Router(level, pos)->AddOutputChannel( _chan[link], - _chan_cred[link] ); - _chan[link]->SetLatency( 1 ); - _chan_cred[link]->SetLatency( 1 ); -#ifdef FATTREE_DEBUG - cout<<_Router(level, pos)->Name()<<" " - <<"down output "<AddOutputChannel( _chan[link], - _chan_cred[link] ); - _chan[link]->SetLatency( 1 ); - _chan_cred[link]->SetLatency( 1 ); -#ifdef FATTREE_DEBUG - cout<<_Router(level, pos)->Name()<<" " - <<"up output "<AddInputChannel( _chan[link], - _chan_cred[link] ); -#ifdef FATTREE_DEBUG - cout<<_Router(level, pos)->Name()<<" " - <<"down input "<AddInputChannel( _chan[link], - _chan_cred[link] ); -#ifdef FATTREE_DEBUG - cout<<_Router(level, pos)->Name()<<" " - <<"up input "< -#include -#include "router.hpp" - -//////////////////Sub router types////////////////////// -#include "iq_router.hpp" -#include "event_router.hpp" -#include "chaos_router.hpp" -/////////////////////////////////////////////////////// - -int const Router::STALL_BUFFER_BUSY = -2; -int const Router::STALL_BUFFER_CONFLICT = -3; -int const Router::STALL_BUFFER_FULL = -4; -int const Router::STALL_BUFFER_RESERVED = -5; -int const Router::STALL_CROSSBAR_CONFLICT = -6; - -Router::Router( const Configuration& config, - Module *parent, const string & name, int id, - int inputs, int outputs ) : -TimedModule( parent, name ), _id( id ), _inputs( inputs ), _outputs( outputs ), - _partial_internal_cycles(0.0) -{ - _crossbar_delay = ( config.GetInt( "st_prepare_delay" ) + - config.GetInt( "st_final_delay" ) ); - _credit_delay = config.GetInt( "credit_delay" ); - _input_speedup = config.GetInt( "input_speedup" ); - _output_speedup = config.GetInt( "output_speedup" ); - _internal_speedup = config.GetFloat( "internal_speedup" ); - _classes = config.GetInt( "classes" ); - -#ifdef TRACK_FLOWS - _received_flits.resize(_classes, vector(_inputs, 0)); - _stored_flits.resize(_classes); - _sent_flits.resize(_classes, vector(_outputs, 0)); - _active_packets.resize(_classes); - _outstanding_credits.resize(_classes, vector(_outputs, 0)); -#endif - -#ifdef TRACK_STALLS - _buffer_busy_stalls.resize(_classes, 0); - _buffer_conflict_stalls.resize(_classes, 0); - _buffer_full_stalls.resize(_classes, 0); - _buffer_reserved_stalls.resize(_classes, 0); - _crossbar_conflict_stalls.resize(_classes, 0); -#endif - -} - -void Router::AddInputChannel( FlitChannel *channel, CreditChannel *backchannel ) -{ - _input_channels.push_back( channel ); - _input_credits.push_back( backchannel ); - channel->SetSink( this, _input_channels.size() - 1 ) ; -} - -void Router::AddOutputChannel( FlitChannel *channel, CreditChannel *backchannel ) -{ - _output_channels.push_back( channel ); - _output_credits.push_back( backchannel ); - _channel_faults.push_back( false ); - channel->SetSource( this, _output_channels.size() - 1 ) ; -} - -void Router::Evaluate( ) -{ - _partial_internal_cycles += _internal_speedup; - while( _partial_internal_cycles >= 1.0 ) { - _InternalStep( ); - _partial_internal_cycles -= 1.0; - } -} - -void Router::OutChannelFault( int c, bool fault ) -{ - assert( ( c >= 0 ) && ( (size_t)c < _channel_faults.size( ) ) ); - - _channel_faults[c] = fault; -} - -bool Router::IsFaultyOutput( int c ) const -{ - assert( ( c >= 0 ) && ( (size_t)c < _channel_faults.size( ) ) ); - - return _channel_faults[c]; -} - -/*Router constructor*/ -Router *Router::NewRouter( const Configuration& config, - Module *parent, const string & name, int id, - int inputs, int outputs ) -{ - const string type = config.GetStr( "router" ); - Router *r = NULL; - if ( type == "iq" ) { - r = new IQRouter( config, parent, name, id, inputs, outputs ); - } else if ( type == "event" ) { - r = new EventRouter( config, parent, name, id, inputs, outputs ); - } else if ( type == "chaos" ) { - r = new ChaosRouter( config, parent, name, id, inputs, outputs ); - } else { - cerr << "Unknown router type: " << type << endl; - } - /*For additional router, add another else if statement*/ - /*Original booksim specifies the router using "flow_control" - *we now simply call these types. - */ - - return r; -} - - - - - diff --git a/src/intersim2/.svn/pristine/0e/0eae5ca5351f1f31915bc0c3da4a3a1ae19e21c4.svn-base b/src/intersim2/.svn/pristine/0e/0eae5ca5351f1f31915bc0c3da4a3a1ae19e21c4.svn-base deleted file mode 100644 index 5c54228..0000000 --- a/src/intersim2/.svn/pristine/0e/0eae5ca5351f1f31915bc0c3da4a3a1ae19e21c4.svn-base +++ /dev/null @@ -1,57 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _PACKET_REPLY_INFO_HPP_ -#define _PACKET_REPLY_INFO_HPP_ - -#include - -#include "flit.hpp" - -//register the requests to a node -class PacketReplyInfo { - -public: - int source; - int time; - bool record; - Flit::FlitType type; - - static PacketReplyInfo* New(); - void Free(); - static void FreeAll(); - -private: - - static stack _all; - static stack _free; - - PacketReplyInfo() {} - ~PacketReplyInfo() {} -}; - -#endif diff --git a/src/intersim2/.svn/pristine/0f/0fa9e6ee8d633c141585cd663a6307195b79db63.svn-base b/src/intersim2/.svn/pristine/0f/0fa9e6ee8d633c141585cd663a6307195b79db63.svn-base deleted file mode 100644 index a7b540b..0000000 --- a/src/intersim2/.svn/pristine/0f/0fa9e6ee8d633c141585cd663a6307195b79db63.svn-base +++ /dev/null @@ -1,532 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "power_module.hpp" -#include "booksim_config.hpp" -#include "buffer_monitor.hpp" -#include "switch_monitor.hpp" -#include "iq_router.hpp" - -Power_Module::Power_Module(Network * n , const Configuration &config) - : Module( 0, "power_module" ){ - - - string pfile = config.GetStr("tech_file"); - PowerConfig pconfig; - pconfig.ParseFile(pfile); - - net = n; - output_file_name = config.GetStr("power_output_file"); - classes = config.GetInt("classes"); - channel_width = (double)config.GetInt("channel_width"); - channel_sweep = (double)config.GetInt("channel_sweep"); - - numVC = (double)config.GetInt("num_vcs"); - depthVC = (double)config.GetInt("vc_buf_size"); - - //////////////////////////////////Constants///////////////////////////// - //wire length in (mm) - wire_length = pconfig.GetFloat("wire_length"); - //////////Metal Parameters//////////// - // Wire left/right coupling capacitance [ F/mm ] - Cw_cpl = pconfig.GetFloat("Cw_cpl"); - // Wire up/down groudn capacitance [ F/mm ] - Cw_gnd = pconfig.GetFloat("Cw_gnd"); - Cw = 2.0 * Cw_cpl + 2.0 * Cw_gnd ; - Rw = pconfig.GetFloat("Rw"); - // metal pitch [mm] - MetalPitch = pconfig.GetFloat("MetalPitch"); - - //////////Device Parameters//////////// - - LAMBDA = pconfig.GetFloat("LAMBDA") ; // [um/LAMBDA] - Cd = pconfig.GetFloat("Cd"); // [F/um] (for Delay) - Cg = pconfig.GetFloat("Cg"); // [F/um] (for Delay) - Cgdl = pconfig.GetFloat("Cgdl"); // [F/um] (for Delay) - - Cd_pwr = pconfig.GetFloat("Cd_pwr") ; // [F/um] (for Power) - Cg_pwr = pconfig.GetFloat("Cg_pwr") ; // [F/um] (for Power) - - IoffN = pconfig.GetFloat("IoffN"); // [A/um] - IoffP = pconfig.GetFloat("IoffP"); // [A/um] - // Leakage from bitlines, two-port cell [A] - IoffSRAM = pconfig.GetFloat("IoffSRAM"); - // [Ohm] ( D1=1um Inverter) - R = pconfig.GetFloat("R"); - // [F] ( D1=1um Inverter - for Power ) - Ci_delay = (1.0 + 2.0) * ( Cg + Cgdl ); - // [F] ( D1=1um Inverter - for Power ) - Co_delay = (1.0 + 2.0) * Cd ; - - - Ci = (1.0 + 2.0) * Cg_pwr ; - Co = (1.0 + 2.0) * Cd_pwr ; - - Vdd = pconfig.GetFloat("Vdd"); - FO4 = R * ( 3.0 * Cd + 12 * Cg + 12 * Cgdl); - tCLK = 20 * FO4; - fCLK = 1.0 / tCLK; - - H_INVD2=(double)pconfig.GetInt("H_INVD2"); - W_INVD2=(double)pconfig.GetInt("W_INVD2") ; - H_DFQD1=(double)pconfig.GetInt("H_DFQD1"); - W_DFQD1= (double)pconfig.GetInt("W_DFQD1"); - H_ND2D1= (double)pconfig.GetInt("H_ND2D1"); - W_ND2D1=(double)pconfig.GetInt("W_ND2D1"); - H_SRAM=(double)pconfig.GetInt("H_SRAM"); - W_SRAM=(double)pconfig.GetInt("W_SRAM"); - - ChannelPitch = 2.0 * MetalPitch ; - CrossbarPitch = 2.0 * MetalPitch ; -} - -Power_Module::~Power_Module(){ - - -} - - -////////////////////////////////////////////// -//Channels -////////////////////////////////////////////// - -void Power_Module::calcChannel(const FlitChannel* f){ - double channelLength = f->GetLatency()* wire_length; - wire const this_wire = wireOptimize(channelLength); - double const & K = this_wire.K; - double const & N = this_wire.N; - double const & M = this_wire.M; - //area - channelArea += areaChannel(K,N,M); - - //activity factor; - const vector temp = f->GetActivity(); - vector a(classes); - for(int i = 0; i< classes; i++){ - - a[i] = ((double)temp[i])/totalTime; - } - - //power calculation - double const bitPower = powerRepeatedWire(channelLength, K,M,N); - - channelClkPower += powerWireClk(M,channel_width); - for(int i = 0; i< classes; i++){ - channelWirePower += bitPower * a[i]*channel_width; - channelDFFPower += powerWireDFF(M, channel_width, a[i]); - } - channelLeakPower+= powerRepeatedWireLeak(K,M,N)*channel_width; -} - -wire const & Power_Module::wireOptimize(double L){ - map::iterator iter = wire_map.find(L); - if(iter == wire_map.end()){ - - double W = 64; - double bestMetric = 100000000 ; - double bestK = -1; - double bestM = -1; - double bestN = -1; - for (double K = 1.0 ; K < 10 ; K+=0.1 ) { - for (double N = 1.0 ; N < 40 ; N += 1.0 ) { - for (double M = 1.0 ; M < 40.0 ; M +=1.0 ) { - double l = 1.0 * L/( N * M) ; - - double k0 = R * (Co_delay + Ci_delay) ; - double k1 = R/K * Cw + K * Rw * Ci_delay ; - double k2 = 0.5 * Rw * Cw ; - double Tw = k0 + (k1 * l) + k2 * (l * l) ; - double alpha = 0.2 ; - double power = alpha * W * powerRepeatedWire( L, K, M, N) + powerWireDFF( M, W, alpha ) ; - double metric = M * M * M * M * power ; - if ( (N*Tw) < (0.8 * tCLK) ) { - if ( metric < bestMetric ) { - bestMetric = metric ; - bestK = K ; - bestM = M ; - bestN = N ; - } - } - } - } - } - cout<<"L = "<NumInputs(), sm->NumOutputs()); - outputArea += areaOutputModule(sm->NumOutputs()); - switchPowerLeak += powerCrossbarLeak(channel_width, sm->NumInputs(), sm->NumOutputs()); - - const vector activity = sm->GetActivity(); - vector type_activity(classes); - - for(int i = 0; iNumOutputs(); i++){ - for(int k = 0; kNumInputs(); j++){ - for(int k = 0; kNumOutputs()*j)]; - a = a/totalTime; - if(a>1){ - cout<<"Switcht activity factor is greater than 1!!!\n";exit(-1); - } - double Px = powerCrossbar(channel_width, sm->NumInputs(),sm->NumOutputs(),j,i); - switchPower += a*channel_width*Px; - switchPowerCtrl += a *powerCrossbarCtrl(channel_width, sm->NumInputs(),sm->NumOutputs()); - type_activity[k]+=a; - } - } - outputPowerClk += powerWireClk( 1, channel_width ) ; - for(int k = 0; k inject = net->GetInject(); - vector eject = net->GetEject(); - vector chan = net->GetChannels(); - - for(int i = 0; iNumNodes(); i++){ - calcChannel(inject[i]); - } - - for(int i = 0; iNumNodes(); i++){ - calcChannel(eject[i]); - } - - for(int i = 0; iNumChannels();i++){ - calcChannel(chan[i]); - } - - vector routers = net->GetRouters(); - for(size_t i = 0; i < routers.size(); i++){ - IQRouter* temp = dynamic_cast(routers[i]); - const BufferMonitor * bm = temp->GetBufferMonitor(); - calcBuffer(bm); - const SwitchMonitor * sm = temp->GetSwitchMonitor(); - calcSwitch(sm); - } - - double totalpower = channelWirePower+channelClkPower+channelDFFPower+channelLeakPower+ inputReadPower+inputWritePower+inputLeakagePower+ switchPower+switchPowerCtrl+switchPowerLeak+outputPower+outputPowerClk+outputCtrlPower; - double totalarea = channelArea+switchArea+inputArea+outputArea; - cout<< "-----------------------------------------\n" ; - cout<< "- OCN Power Summary\n" ; - cout<< "- Completion Time: "< - -#include "allocator.hpp" - -class Arbiter; - -class SeparableAllocator : public SparseAllocator { - -protected: - - vector _input_arb ; - vector _output_arb ; - -public: - - SeparableAllocator( Module* parent, const string& name, int inputs, - int outputs, const string& arb_type ) ; - - virtual ~SeparableAllocator() ; - - virtual void Clear() ; - -} ; - -#endif diff --git a/src/intersim2/.svn/pristine/12/125686d82b0fb03524a1bd1dc36fd9172006e780.svn-base b/src/intersim2/.svn/pristine/12/125686d82b0fb03524a1bd1dc36fd9172006e780.svn-base deleted file mode 100644 index f7e44a8..0000000 --- a/src/intersim2/.svn/pristine/12/125686d82b0fb03524a1bd1dc36fd9172006e780.svn-base +++ /dev/null @@ -1,673 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "booksim.hpp" -#include -#include -#include -#include - -#include "chaos_router.hpp" -#include "random_utils.hpp" -#include "globals.hpp" - -ChaosRouter::ChaosRouter( const Configuration& config, - Module *parent, const string & name, int id, - int inputs, int outputs ) - : Router( config, - parent, name, - id, - inputs, outputs ) -{ - int i; - - if ( inputs != outputs ) { - Error( "Chaos router must have equal number of input and output ports" ); - } - - _buffer_size = config.GetInt( "vc_buf_size" ); - assert(_buffer_size >= config.GetInt( "const_flits_per_packet" )); - - _multi_queue_size = config.GetInt( "multi_queue_size" ); - - _cur_channel = 0; - _read_stall = 0; - - // Routing - - string rf = config.GetStr("routing_function") + "_" + config.GetStr("topology"); - map::iterator rf_iter = gRoutingFunctionMap.find(rf); - if(rf_iter == gRoutingFunctionMap.end()) { - Error("Invalid routing function: " + rf); - } - _rf = rf_iter->second; - - _input_route.resize(_inputs); - - for ( i = 0; i < _inputs; ++i ) { - _input_route[i] = new OutputSet( ); - } - - _mq_route.resize(_multi_queue_size); - - for ( i = 0; i < _multi_queue_size; ++i ) { - _mq_route[i] = new OutputSet( ); - } - - // Alloc pipelines (to simulate processing/transmission delays) - - _crossbar_pipe = - new PipelineFIFO( this, "crossbar_pipeline", _outputs, - _crossbar_delay ); - - // Input and output queues - - _input_frame.resize(_inputs); - _output_frame.resize(_outputs); - _multi_queue.resize(_multi_queue_size); - - _credit_queue.resize(_inputs); - - _input_state.resize(_inputs, empty); - _input_output_match.resize(_inputs, -1); - _input_mq_match.resize(_inputs, -1); - - _output_matched.resize(_outputs, false); - _next_queue_cnt.resize(_outputs, 0); - - _multi_match.resize(_multi_queue_size, -1); - _mq_age.resize(_multi_queue_size); - _mq_matched.resize(_multi_queue_size, false); - _multi_state.resize(_multi_queue_size, empty); - - for ( i = 0; i < _multi_queue_size; ++i ) { - _multi_state[i] = empty; - _multi_match[i] = -1; - _mq_matched[i] = false; - } -} - -ChaosRouter::~ChaosRouter( ) -{ - int i; - - delete _crossbar_pipe; - - for ( i = 0; i < _inputs; ++i ) { - delete _input_route[i]; - } - - for ( i = 0; i < _multi_queue_size; ++i ) { - delete _mq_route[i]; - } -} - -void ChaosRouter::ReadInputs( ) -{ - Flit *f; - Credit *c; - - for ( int input = 0; input < _inputs; ++input ) { - f = _input_channels[input]->Receive(); - - if ( f ) { - _input_frame[input].push( f ); - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Flit arriving at " << FullName() - << " on channel " << input << endl - << *f; - } - - switch( _input_state[input] ) { - case empty: - if ( f->head ) { - if ( f->tail ) { - _input_state[input] = full; - } else { - _input_state[input] = filling; - } - _rf( this, f, input, _input_route[input], false ); - } else { - cout << *f; - Error( "Empty buffer received non-head flit!" ); - } - break; - - case filling: - if ( f->tail ) { - _input_state[input] = full; - } else if ( f->head ) { - Error( "Input buffer received another head before previous tail!" ); - } - break; - - case full: - Error( "Received flit while full!" ); - break; - - case leaving: - if ( f->head ) { - _input_state[input] = shared; - - if ( f->tail ) { - Error( "Received single-flit packet in leaving state!" ); - } - } else { - cout << *f; - Error( "Received non-head flit while packet leaving!" ); - } - break; - - case cut_through: - if ( f->tail ) { - _input_state[input] = leaving; - } - if ( f->head ) { - cout << *f; - Error( "Received head flit in cut through buffer!" ); - } - break; - - case shared: - if ( f->head ) { - Error( "Shared buffer received another head!" ); - } else if ( f->tail ) { - cout << "Input " << input << endl; - cout << *f; - Error( "Shared buffer received another tail!" ); - } - break; - } - } - } - - // Process incoming credits - - for ( int output = 0; output < _outputs; ++output ) { - c = _output_credits[output]->Receive(); - - if ( c ) { - _next_queue_cnt[output]--; - - if ( _next_queue_cnt[output] < 0 ) { - Error( "Next queue count fell below zero!" ); - } - - c->Free(); - } - } -} - -void ChaosRouter::_InternalStep( ) -{ - _NextInterestingChannel( ); - _OutputAdvance( ); - - _crossbar_pipe->Advance( ); -} - -void ChaosRouter::WriteOutputs( ) -{ - _SendFlits( ); - _SendCredits( ); -} - -bool ChaosRouter::_IsInjectionChan( int chan ) const -{ - return ( chan == _inputs - 1 ); -} - -bool ChaosRouter::_IsEjectionChan( int chan ) const -{ - return ( chan == _outputs - 1 ); -} - -bool ChaosRouter::_InputReady( int input ) const -{ - bool ready = false; - - if ( ( _input_state[input] == filling ) || - ( _input_state[input] == full ) ) { - ready = true; - } - - return ready; -} - -bool ChaosRouter::_OutputFull( int out ) const -{ - return ( _output_frame[out].size( ) >= (size_t)_buffer_size ); -} - -bool ChaosRouter::_OutputAvail( int out ) const -{ - return ( ( !_output_matched[out] ) && ( _output_frame[out].empty( ) ) ); - //&& ( _next_queue_cnt[out] == 0 ) ); - //return ( ( !_output_matched[out] ) && !_OutputFull( out ) ); -} - -bool ChaosRouter::_MultiQueueFull( int mq ) const -{ - return ( _multi_queue[mq].size( ) >= (size_t)_buffer_size ); -} - -int ChaosRouter::_InputForOutput( int output ) const -{ - // return an input that prefers this output - - int input; - int offset = RandomInt( _inputs - 1 ); - bool match = false; - - for ( int i = 0; ( i < _inputs ) && ( !match ); ++i ) { - input = ( i + offset ) % _inputs; - - if ( _InputReady( input ) && - ( ! _input_route[input]->OutputEmpty( output ) ) ) { - match = true; - } - } - - return match ? input : -1; -} - -int ChaosRouter::_MultiQueueForOutput( int output ) const -{ - // return oldest multi queue that prefers the output, - // or if none prefer and the multi queue is full, - // return a random entry - - int mq_oldest = -1; - int mq_age; - - int m, r; - - bool isfull = true; - - for ( int i = 0; i < _multi_queue_size; ++i ) { - if ( ( _multi_match[i] == -1 ) && - ( ( _multi_state[i] == full ) || - ( _multi_state[i] == filling ) ) ) { - - if ( ( !_mq_route[i]->OutputEmpty( output ) ) && - ( ( mq_oldest == -1 ) || ( _mq_age[i] > mq_age ) ) ) { - mq_oldest = i; - mq_age = _mq_age[i]; - } - } - - // deroute only if all queues contain head flits ... - - if ( ( _multi_state[i] != full ) && - ( _multi_state[i] != filling ) && - ( _multi_state[i] != shared ) ) { - isfull = false; - } - } - - // Don't deroute MQs to the ejection channel - if ( ( mq_oldest == -1 ) && isfull && - ( !_IsEjectionChan( output ) ) ) { - r = RandomInt( _multi_queue_size - 1 ); - - // Find first routable multi-queue - for ( int i = 0; i < _multi_queue_size; ++i ) { - m = ( i + r ) % _multi_queue_size; - if ( ( _multi_state[m] == filling ) || - ( _multi_state[m] == full ) ) { - mq_oldest = m; - //cout << "DEROUTING at " << FullName() << endl; - break; - } - } - - if ( mq_oldest == -1 ) { - cout << "write stall" << endl; - } - } - - return mq_oldest; -} - -int ChaosRouter::_FindAvailMultiQueue( ) const -{ - // return any empty multi queue slot - - int avail = -1; - - for ( int i = 0; i < _multi_queue_size; ++i ) { - if ( ( !_MultiQueueFull( i ) ) && - ( !_mq_matched[i] ) ) { - avail = i; - break; - } - } - - return avail; -} - -void ChaosRouter::_NextInterestingChannel( ) -{ - bool interesting; - - int mq_index; - int in_index; - int mq_avail; - - int c; - - interesting = false; - mq_index = -1; - in_index = -1; - - // A channel is interesting if - // - // ( output frame available and - // ( ( a multiqueue packet wants output channel ) or - // ( an input packet wants output channel ) or - // ( the multiqueue is full ) ) ) - // or - // ( the packet at the input channel is stalled ) - - for ( c = 0; ( c < _inputs ) && ( !interesting ); ++c ) { - if ( _OutputAvail( _cur_channel ) ) { - mq_index = _MultiQueueForOutput( _cur_channel ); - in_index = _InputForOutput( _cur_channel ); - - if ( ( mq_index != -1 ) || ( in_index != -1 ) ) { - interesting = true; - } - } - - if ( _input_state[_cur_channel] == full ) { - interesting = true; - } - - if ( !interesting ) { - _cur_channel = ( _cur_channel + 1 ) % _inputs; - } - } - - if ( interesting ) { - //cout << _cur_channel << " is interesting at " << FullName() << endl; - - if ( mq_index != -1 ) { - //cout << "Match for multi-queue " << mq_index << " at " << FullName() - // << ", output matched = " << _output_matched[_cur_channel] << endl; - - _output_matched[_cur_channel] = true; - _multi_match[mq_index] = _cur_channel; - } else if ( in_index != -1 ) { - _output_matched[_cur_channel] = true; - _input_output_match[in_index] = _cur_channel; - - //cout << "Match for input " << in_index << " at " << FullName() << endl; - - if ( _input_state[in_index] == full ) { - _input_state[in_index] = leaving; - } else if ( _input_state[in_index] == filling ) { - _input_state[in_index] = cut_through; - } else { - Error( "Tried to route input through crossbar that was not full or filling!" ); - } - } - - // Any non-injection channel that is routable is - // directed to the multi-queue - if ( ( ( _input_state[_cur_channel] == filling ) || - ( _input_state[_cur_channel] == full ) ) && - ( !_IsInjectionChan( _cur_channel ) ) ) { - ++_read_stall; - } else { - // go to next channel for the next cycle - _cur_channel = ( _cur_channel + 1 ) % _inputs; - _read_stall = 0; - } - } - - if ( _read_stall > 0 ) { - mq_avail = _FindAvailMultiQueue( ); - - if ( mq_avail != -1 ) { - if ( _input_state[_cur_channel] == full ) { - _input_state[_cur_channel] = leaving; - } else if ( _input_state[_cur_channel] == filling ) { - _input_state[_cur_channel] = cut_through; - } else { - cout << "Input " << _cur_channel << " state = " - << _input_state[_cur_channel] << endl; - Error( "Tried to route input throught multi-queue that was not full or filling!" ); - } - - _input_mq_match[_cur_channel] = mq_avail; - _mq_matched[mq_avail] = true; - - // go to next channel for the next cycle - _cur_channel = ( _cur_channel + 1 ) % _inputs; - _read_stall = 0; - } else { - ++_read_stall; - //cout << "stalling at input " << _cur_channel << " (count = " << _read_stall << ")" << endl; - } - } -} - -void ChaosRouter::_OutputAdvance( ) -{ - Flit *f, *f2; - Credit *c; - bool advanced; - int mq; - - _crossbar_pipe->WriteAll( 0 ); - - for ( int i = 0; i < _inputs; ++i ) { - if ( ( ( _input_output_match[i] != -1 ) || - ( _input_mq_match[i] != -1 ) ) && - ( !_input_frame[i].empty( ) ) ) { - - advanced = false; - f = _input_frame[i].front( ); - - /*if ( ! ) { - - } else { - cout << "Input = " << i - << ", input_output_match = " << _input_output_match[i] - << ", input_mq_match = " << _input_mq_match[i] << endl; - Error( "Input queue empty, but matched!" ); - }*/ - - if ( _input_output_match[i] != -1 ) { - if ( f->tail ) { - _output_matched[_input_output_match[i]] = false; - } - - _crossbar_pipe->Write( f, _input_output_match[i] ); - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Flit traversing crossbar from input queue " - << i << " at " - << FullName() << endl - << *f; - } - - advanced = true; - - } else if ( !_MultiQueueFull( _input_mq_match[i] ) ) { - - mq = _input_mq_match[i]; - - if ( f->head ) { - _rf( this, f, i, _mq_route[mq], false ); - _mq_age[mq] = 0; - - if ( _multi_state[mq] == empty ) { - _multi_state[mq] = filling; - } else if ( _multi_state[mq] == leaving ) { - _multi_state[mq] = shared; - } else { - Error( "Multi-queue received head while not empty or leaving!" ); - } - } - - if ( f->tail ) { - _mq_matched[mq] = false; - - if ( _multi_state[mq] == filling ) { - _multi_state[mq] = full; - } else if ( _multi_state[mq] == cut_through ) { - _multi_state[mq] = leaving; - } else { - Error( "Multi-queue received tail while not filling or cutting-through!" ); - } - } - - _multi_queue[mq].push( f ); - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Flit stored in multiqueue at " - << FullName() << endl - << "State = " << _multi_state[mq] << endl - << *f; - } - - advanced = true; - } - - if ( advanced ) { - _input_frame[i].pop( ); - - if ( f->tail ) { // last in packet, update state - if ( _input_state[i] == leaving ) { - _input_state[i] = empty; - } else if ( _input_state[i] == shared ) { - _input_state[i] = filling; - f2 = _input_frame[i].front( ); - // update routes - _rf( this, f2, i, _input_route[i], false ); - } - - _input_output_match[i] = -1; - _input_mq_match[i] = -1; - } - - c = Credit::New( ); - c->vc.insert(0); - _credit_queue[i].push( c ); - } - } - } - - for ( int m = 0; m < _multi_queue_size; ++m ) { - if ( _multi_match[m] != -1 ) { - if ( _multi_queue[m].empty( ) ) { - cout << "State = " << _multi_state[m] << endl; - Error( "Multi queue empty, but matched!" ); - } - assert( !_multi_queue[m].empty( ) ); - f = _multi_queue[m].front( ); - _multi_queue[m].pop( ); - - _crossbar_pipe->Write( f, _multi_match[m] ); - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Flit traversing crossbar from multiqueue slot " - << m << " at " - << FullName() << endl - << *f; - } - - if ( f->head ) { - if ( _multi_state[m] == filling ) { - _multi_state[m] = cut_through; - } else if ( _multi_state[m] == full ) { - _multi_state[m] = leaving; - } else { - Error( "Multi-queue sent head while not filling or full!" ); - } - } - - if ( f->tail ) { - _output_matched[_multi_match[m]] = false; - _multi_match[m] = -1; - - if ( _multi_state[m] == shared ) { - _multi_state[m] = filling; - } else if ( _multi_state[m] == leaving ) { - _multi_state[m] = empty; - } else { - cout << "State = " << _multi_state[m] << endl; - cout << *f; - Error( "Multi-queue sent tail while not leaving or shared!" ); - } - } - } - - _mq_age[m]++; - } -} - - -void ChaosRouter::_SendFlits( ) -{ - for ( int output = 0; output < _outputs; ++output ) { - Flit *f = _crossbar_pipe->Read( output ); - - if ( f ) { - _output_frame[output].push( f ); - f->hops++; - } - - if ( ( _next_queue_cnt[output] < _buffer_size ) && - ( !_output_frame[output].empty( ) ) ) { - _output_channels[output]->Send( _output_frame[output].front( ) ); - _output_frame[output].pop( ); - ++_next_queue_cnt[output]; - } - } -} - -void ChaosRouter::_SendCredits( ) -{ - for ( int input = 0; input < _inputs; ++input ) { - if ( !_credit_queue[input].empty( ) ) { - Credit *c = _credit_queue[input].front( ); - _credit_queue[input].pop( ); - _input_credits[input]->Send( c ); - } - } -} - -void ChaosRouter::Display( ostream & os ) const -{ -} diff --git a/src/intersim2/.svn/pristine/12/1260dd25f0b77d1694bc40d60681090fdb77e795.svn-base b/src/intersim2/.svn/pristine/12/1260dd25f0b77d1694bc40d60681090fdb77e795.svn-base deleted file mode 100644 index 6488ea4..0000000 --- a/src/intersim2/.svn/pristine/12/1260dd25f0b77d1694bc40d60681090fdb77e795.svn-base +++ /dev/null @@ -1,186 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _POWER_MODULE_HPP_ -#define _POWER_MODULE_HPP_ - -#include - -#include "module.hpp" -#include "network.hpp" -#include "config_utils.hpp" -#include "flitchannel.hpp" -#include "switch_monitor.hpp" -#include "buffer_monitor.hpp" - -struct wire{ - double L; - double K; - double M; - double N; -}; - -class Power_Module : public Module { - -protected: - //network undersimulation - Network * net; - int classes; - //all channels are this width - double channel_width; - //resimulate all with channel_width decremented by channel_sweep until 0 - double channel_sweep; - //write result to a tabbed format to file - string output_file_name; - - //buffer depth - double depthVC; - //vcs - double numVC; - - //store the property of wires based on length - map wire_map; - - //////////////////////////////////Constants///////////////////////////// - //wire length in (mm) - double wire_length; - //////////Metal Parameters//////////// - // Wire left/right coupling capacitance [ F/mm ] - double Cw_cpl ; - // Wire up/down groudn capacitance [ F/mm ] - double Cw_gnd ; - double Cw ; - double Rw ; - // metal pitch [mm] - double MetalPitch ; - - - //////////Device Parameters//////////// - - double LAMBDA ; // [um/LAMBDA] - double Cd ; // [F/um] (for Delay) - double Cg ; // [F/um] (for Delay) - double Cgdl ; // [F/um] (for Delay) - - double Cd_pwr; // [F/um] (for Power) - double Cg_pwr ; // [F/um] (for Power) - - double IoffN ; // [A/um] - double IoffP ; // [A/um] - // Leakage from bitlines, two-port cell [A] - double IoffSRAM; - // [Ohm] ( D1=1um Inverter) - double R ; - // [F] ( D1=1um Inverter - for Power ) - double Ci_delay; - // [F] ( D1=1um Inverter - for Power ) - double Co_delay ; - - double Ci ; - double Co ; - double Vdd ; - double FO4 ; - double tCLK ; - double fCLK ; - - double H_INVD2; - double W_INVD2; - double H_DFQD1; - double W_DFQD1; - double H_ND2D1; - double W_ND2D1; - double H_SRAM; - double W_SRAM; - double ChannelPitch ; - double CrossbarPitch; - ////////////////////////////////End of Constants///////////////////////////// - - /////////////results/////////////////// - double totalTime; - double channelWirePower; - double channelClkPower; - double channelDFFPower; - double channelLeakPower; - double inputReadPower; - double inputWritePower; - double inputLeakagePower; - double switchPower; - double switchPowerCtrl; - double switchPowerLeak; - double outputPower; - double outputPowerClk; - double outputCtrlPower; - double channelArea; - double switchArea; - double inputArea; - double outputArea; - double maxInputPort; - double maxOutputPort; - - - //////////////////////// - - //channels - void calcChannel(const FlitChannel * f); - wire const & wireOptimize(double l); - double powerRepeatedWire(double L, double K, double M, double N); - double powerRepeatedWireLeak (double K, double M, double N); - double powerWireClk (double M, double W); - double powerWireDFF(double M, double W, double alpha); - - //memory - void calcBuffer(const BufferMonitor *bm); - double powerWordLine(double memoryWidth, double memoryDepth); - double powerMemoryBitRead(double memoryDepth); - double powerMemoryBitWrite(double memoryDepth); - double powerMemoryBitLeak(double memoryDepth ); - - //switch - void calcSwitch(const SwitchMonitor *sm); - double powerCrossbar(double width, double inputs, double outputs, double from, double to); - double powerCrossbarCtrl(double width, double inputs, double outputs); - double powerCrossbarLeak (double width, double inputs, double outputs); - - //output - double powerOutputCtrl(double width); - - //area - - double areaChannel (double K, double N, double M); - double areaCrossbar(double Inputs, double Outputs) ; - double areaInputModule(double Words) ; - double areaOutputModule(double Outputs); - -public: - Power_Module(Network * net, const Configuration &config); - ~Power_Module(); - - void run(); - - -}; -#endif diff --git a/src/intersim2/.svn/pristine/12/129d383ada436691b3879ee38f72c6420d1b3b86.svn-base b/src/intersim2/.svn/pristine/12/129d383ada436691b3879ee38f72c6420d1b3b86.svn-base deleted file mode 100644 index 6aa2d53..0000000 --- a/src/intersim2/.svn/pristine/12/129d383ada436691b3879ee38f72c6420d1b3b86.svn-base +++ /dev/null @@ -1,481 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "booksim.hpp" -#include -#include -#include -#include "allocator.hpp" - -///////////////////////////////////////////////////////////////////////// -//Allocator types -#include "maxsize.hpp" -#include "pim.hpp" -#include "islip.hpp" -#include "loa.hpp" -#include "wavefront.hpp" -#include "selalloc.hpp" -#include "separable_input_first.hpp" -#include "separable_output_first.hpp" -// -///////////////////////////////////////////////////////////////////////// - -//================================================== -// Allocator base class -//================================================== - -Allocator::Allocator( Module *parent, const string& name, - int inputs, int outputs ) : -Module( parent, name ), _inputs( inputs ), _outputs( outputs ), _dirty( false ) -{ - _inmatch.resize(_inputs, -1); - _outmatch.resize(_outputs, -1); -} - -void Allocator::Clear( ) -{ - if(_dirty) { - _inmatch.assign(_inputs, -1); - _outmatch.assign(_outputs, -1); - _dirty = false; - } -} - -void Allocator::AddRequest( int in, int out, int label, int in_pri, - int out_pri ) { - - assert( ( in >= 0 ) && ( in < _inputs ) ); - assert( ( out >= 0 ) && ( out < _outputs ) ); - assert( label >= 0 ); - _dirty = true; -} - -int Allocator::OutputAssigned( int in ) const -{ - assert( ( in >= 0 ) && ( in < _inputs ) ); - - return _inmatch[in]; -} - -int Allocator::InputAssigned( int out ) const -{ - assert( ( out >= 0 ) && ( out < _outputs ) ); - - return _outmatch[out]; -} - -void Allocator::PrintGrants( ostream * os ) const -{ - if(!os) os = &cout; - - *os << "Input grants = [ "; - for ( int input = 0; input < _inputs; ++input ) { - if(_inmatch[input] >= 0) { - *os << input << " -> " << _inmatch[input] << " "; - } - } - *os << "], output grants = [ "; - for ( int output = 0; output < _outputs; ++output ) { - if(_outmatch[output] >= 0) { - *os << output << " -> " << _outmatch[output] << " "; - } - } - *os << "]." << endl; -} - -//================================================== -// DenseAllocator -//================================================== - -DenseAllocator::DenseAllocator( Module *parent, const string& name, - int inputs, int outputs ) : - Allocator( parent, name, inputs, outputs ) -{ - _request.resize(_inputs); - - for ( int i = 0; i < _inputs; ++i ) { - _request[i].resize(_outputs); - for ( int j = 0; j < _outputs; ++j ) { - _request[i][j].label = -1; - } - } -} - -void DenseAllocator::Clear( ) -{ - for ( int i = 0; i < _inputs; ++i ) { - for ( int j = 0; j < _outputs; ++j ) { - _request[i][j].label = -1; - } - } - Allocator::Clear(); -} - -int DenseAllocator::ReadRequest( int in, int out ) const -{ - assert( ( in >= 0 ) && ( in < _inputs ) ); - assert( ( out >= 0 ) && ( out < _outputs ) ); - - return _request[in][out].label; -} - -bool DenseAllocator::ReadRequest( sRequest &req, int in, int out ) const -{ - assert( ( in >= 0 ) && ( in < _inputs ) ); - assert( ( out >= 0 ) && ( out < _outputs ) ); - - req = _request[in][out]; - - return ( req.label >= 0 ); -} - -void DenseAllocator::AddRequest( int in, int out, int label, - int in_pri, int out_pri ) -{ - Allocator::AddRequest(in, out, label, in_pri, out_pri); - assert( _request[in][out].label == -1 ); - - _request[in][out].label = label; - _request[in][out].in_pri = in_pri; - _request[in][out].out_pri = out_pri; -} - -void DenseAllocator::RemoveRequest( int in, int out, int label ) -{ - assert( ( in >= 0 ) && ( in < _inputs ) ); - assert( ( out >= 0 ) && ( out < _outputs ) ); - - _request[in][out].label = -1; -} - -bool DenseAllocator::InputHasRequests( int in ) const -{ - for(int out = 0; out < _outputs; ++out) { - if(_request[in][out].label >= 0) { - return true; - } - } - return false; -} - -bool DenseAllocator::OutputHasRequests( int out ) const -{ - for(int in = 0; in < _inputs; ++in) { - if(_request[in][out].label >= 0) { - return true; - } - } - return false; -} - -int DenseAllocator::NumInputRequests( int in ) const -{ - int result = 0; - for(int out = 0; out < _outputs; ++out) { - if(_request[in][out].label >= 0) { - ++result; - } - } - return result; -} - -int DenseAllocator::NumOutputRequests( int out ) const -{ - int result = 0; - for(int in = 0; in < _inputs; ++in) { - if(_request[in][out].label >= 0) { - ++result; - } - } - return result; -} - -void DenseAllocator::PrintRequests( ostream * os ) const -{ - if(!os) os = &cout; - - *os << "Input requests = [ "; - for ( int input = 0; input < _inputs; ++input ) { - bool print = false; - ostringstream ss; - for ( int output = 0; output < _outputs; ++output ) { - const sRequest & req = _request[input][output]; - if ( req.label >= 0 ) { - print = true; - ss << output << "@" << req.in_pri << " "; - } - } - if(print) { - *os << input << " -> [ " << ss.str() << "] "; - } - } - *os << "], output requests = [ "; - for ( int output = 0; output < _outputs; ++output ) { - bool print = false; - ostringstream ss; - for ( int input = 0; input < _inputs; ++input ) { - const sRequest & req = _request[input][output]; - if ( req.label >= 0 ) { - print = true; - ss << input << "@" << req.out_pri << " "; - } - } - if(print) { - *os << output << " -> [ " << ss.str() << "] "; - } - } - *os << "]." << endl; -} - -//================================================== -// SparseAllocator -//================================================== - -SparseAllocator::SparseAllocator( Module *parent, const string& name, - int inputs, int outputs ) : - Allocator( parent, name, inputs, outputs ) -{ - _in_req.resize(_inputs); - _out_req.resize(_outputs); -} - - -void SparseAllocator::Clear( ) -{ - for ( int i = 0; i < _inputs; ++i ) { - if(!_in_req[i].empty()) - _in_req[i].clear( ); - } - - for ( int j = 0; j < _outputs; ++j ) { - if(!_out_req[j].empty()) - _out_req[j].clear( ); - } - - _in_occ.clear( ); - _out_occ.clear( ); - - Allocator::Clear(); -} - -int SparseAllocator::ReadRequest( int in, int out ) const -{ - sRequest r; - - if ( ! ReadRequest( r, in, out ) ) { - r.label = -1; - } - - return r.label; -} - -bool SparseAllocator::ReadRequest( sRequest &req, int in, int out ) const -{ - bool found; - - assert( ( in >= 0 ) && ( in < _inputs ) ); - assert( ( out >= 0 ) && ( out < _outputs ) ); - - map::const_iterator match = _in_req[in].find(out); - if ( match != _in_req[in].end( ) ) { - req = match->second; - found = true; - } else { - found = false; - } - - return found; -} - -void SparseAllocator::AddRequest( int in, int out, int label, - int in_pri, int out_pri ) -{ - Allocator::AddRequest(in, out, label, in_pri, out_pri); - assert( _in_req[in].count(out) == 0 ); - assert( _out_req[out].count(in) == 0 ); - - // insert into occupied inputs set if - // input is currently empty - if ( _in_req[in].empty( ) ) { - _in_occ.insert(in); - } - - // similarly for the output - if ( _out_req[out].empty( ) ) { - _out_occ.insert(out); - } - - sRequest req; - req.port = out; - req.label = label; - req.in_pri = in_pri; - req.out_pri = out_pri; - - _in_req[in][out] = req; - - req.port = in; - - _out_req[out][in] = req; -} - -void SparseAllocator::RemoveRequest( int in, int out, int label ) -{ - assert( ( in >= 0 ) && ( in < _inputs ) ); - assert( ( out >= 0 ) && ( out < _outputs ) ); - - assert( _in_req[in].count( out ) > 0 ); - assert( _in_req[in][out].label == label ); - _in_req[in].erase( out ); - - // remove from occupied inputs list if - // input is now empty - if ( _in_req[in].empty( ) ) { - _in_occ.erase(in); - } - - // similarly for the output - assert( _out_req[out].count( in ) > 0 ); - assert( _out_req[out][in].label == label ); - _out_req[out].erase( in ); - - if ( _out_req[out].empty( ) ) { - _out_occ.erase(out); - } -} - -bool SparseAllocator::InputHasRequests( int in ) const -{ - return _in_occ.count(in) > 0; -} - -bool SparseAllocator::OutputHasRequests( int out ) const -{ - return _out_occ.count(out) > 0; -} - -int SparseAllocator::NumInputRequests( int in ) const -{ - return _in_occ.count(in); -} - -int SparseAllocator::NumOutputRequests( int out ) const -{ - return _out_occ.count(out); -} - -void SparseAllocator::PrintRequests( ostream * os ) const -{ - map::const_iterator iter; - - if(!os) os = &cout; - - *os << "Input requests = [ "; - for ( int input = 0; input < _inputs; ++input ) { - if(!_in_req[input].empty()) { - *os << input << " -> [ "; - for ( iter = _in_req[input].begin( ); - iter != _in_req[input].end( ); iter++ ) { - *os << iter->second.port << "@" << iter->second.in_pri << " "; - } - *os << "] "; - } - } - *os << "], output requests = [ "; - for ( int output = 0; output < _outputs; ++output ) { - if(!_out_req[output].empty()) { - *os << output << " -> "; - *os << "[ "; - for ( iter = _out_req[output].begin( ); - iter != _out_req[output].end( ); iter++ ) { - *os << iter->second.port << "@" << iter->second.out_pri << " "; - } - *os << "] "; - } - } - *os << "]." << endl; -} - -//================================================== -// Global allocator allocation function -//================================================== - -Allocator *Allocator::NewAllocator( Module *parent, const string& name, - const string &alloc_type, - int inputs, int outputs, - Configuration const * const config ) -{ - Allocator *a = 0; - - string alloc_name; - string param_str; - size_t left = alloc_type.find_first_of('('); - if(left == string::npos) { - alloc_name = alloc_type; - } else { - alloc_name = alloc_type.substr(0, left); - size_t right = alloc_type.find_last_of(')'); - if(right == string::npos) { - param_str = alloc_type.substr(left+1); - } else { - param_str = alloc_type.substr(left+1, right-left-1); - } - } - if ( alloc_name == "max_size" ) { - a = new MaxSizeMatch( parent, name, inputs, outputs ); - } else if ( alloc_name == "pim" ) { - int iters = param_str.empty() ? (config ? config->GetInt("alloc_iters") : 1) : atoi(param_str.c_str()); - a = new PIM( parent, name, inputs, outputs, iters ); - } else if ( alloc_name == "islip" ) { - int iters = param_str.empty() ? (config ? config->GetInt("alloc_iters") : 1) : atoi(param_str.c_str()); - a = new iSLIP_Sparse( parent, name, inputs, outputs, iters ); - } else if ( alloc_name == "loa" ) { - a = new LOA( parent, name, inputs, outputs ); - } else if ( alloc_name == "wavefront" ) { - a = new Wavefront( parent, name, inputs, outputs ); - } else if ( alloc_name == "rr_wavefront" ) { - a = new Wavefront( parent, name, inputs, outputs, true ); - } else if ( alloc_name == "select" ) { - int iters = param_str.empty() ? (config ? config->GetInt("alloc_iters") : 1) : atoi(param_str.c_str()); - a = new SelAlloc( parent, name, inputs, outputs, iters ); - } else if (alloc_name == "separable_input_first") { - string arb_type = param_str.empty() ? (config ? config->GetStr("arb_type") : "round_robin") : param_str; - a = new SeparableInputFirstAllocator( parent, name, inputs, outputs, - arb_type ); - } else if (alloc_name == "separable_output_first") { - string arb_type = param_str.empty() ? (config ? config->GetStr("arb_type") : "round_robin") : param_str; - a = new SeparableOutputFirstAllocator( parent, name, inputs, outputs, - arb_type ); - } - -//================================================== -// Insert new allocators here, add another else if -//================================================== - - - return a; -} - diff --git a/src/intersim2/.svn/pristine/13/135d8312fc0bb109518f6bfc62cbbf814c7d587c.svn-base b/src/intersim2/.svn/pristine/13/135d8312fc0bb109518f6bfc62cbbf814c7d587c.svn-base deleted file mode 100644 index 27428d9..0000000 --- a/src/intersim2/.svn/pristine/13/135d8312fc0bb109518f6bfc62cbbf814c7d587c.svn-base +++ /dev/null @@ -1,112 +0,0 @@ -/* This program by D E Knuth is in the public domain and freely copyable. - * It is explained in Seminumerical Algorithms, 3rd edition, Section 3.6 - * (or in the errata to the 2nd edition --- see - * http://www-cs-faculty.stanford.edu/~knuth/taocp.html - * in the changes to Volume 2 on pages 171 and following). */ - -/* N.B. The MODIFICATIONS introduced in the 9th printing (2002) are - included here; there's no backwards compatibility with the original. */ - -/* This version also adopts Brendan McKay's suggestion to - accommodate naive users who forget to call ranf_start(seed). */ - -/* If you find any bugs, please report them immediately to - * taocp@cs.stanford.edu - * (and you will be rewarded if the bug is genuine). Thanks! */ - -/************ see the book for explanations and caveats! *******************/ -/************ in particular, you need two's complement arithmetic **********/ - -#define KK 100 /* the long lag */ -#define LL 37 /* the short lag */ -#define mod_sum(x,y) (((x)+(y))-(int)((x)+(y))) /* (x+y) mod 1.0 */ - -double ran_u[KK]; /* the generator state */ - -#ifdef __STDC__ -void ranf_array(double aa[], int n) -#else -void ranf_array(aa,n) /* put n new random fractions in aa */ - double *aa; /* destination */ - int n; /* array length (must be at least KK) */ -#endif -{ - register int i,j; - for (j=0;j=1.0) ss-=1.0-2*ulp; /* cyclic shift of 51 bits */ - } - u[1]+=ulp; /* make u[1] (and only u[1]) "odd" */ - for (s=seed&0x3fffffff,t=TT-1; t; ) { - for (j=KK-1;j>0;j--) - u[j+j]=u[j],u[j+j-1]=0.0; /* "square" */ - for (j=KK+KK-2;j>=KK;j--) { - u[j-(KK-LL)]=mod_sum(u[j-(KK-LL)],u[j]); - u[j-KK]=mod_sum(u[j-KK],u[j]); - } - if (is_odd(s)) { /* "multiply by z" */ - for (j=KK;j>0;j--) u[j]=u[j-1]; - u[0]=u[KK]; /* shift the buffer cyclically */ - u[LL]=mod_sum(u[LL],u[KK]); - } - if (s) s>>=1; else t--; - } - for (j=0;j=0? *ranf_arr_ptr++: ranf_arr_cycle()) -double ranf_arr_cycle() -{ - if (ranf_arr_ptr==&ranf_arr_dummy) - ranf_start(314159L); /* the user forgot to initialize */ - ranf_array(ranf_arr_buf,QUALITY); - ranf_arr_buf[KK]=-1; - ranf_arr_ptr=ranf_arr_buf+1; - return ranf_arr_buf[0]; -} - -#include -int main() -{ - register int m; double a[2009]; /* a rudimentary test */ - ranf_start(310952); - for (m=0;m<2009;m++) ranf_array(a,1009); - printf("%.20f\n", ran_u[0]); /* 0.36410514377569680455 */ - /* beware of buggy printf routines that do not give full accuracy here! */ - ranf_start(310952); - for (m=0;m<1009;m++) ranf_array(a,2009); - printf("%.20f\n", ran_u[0]); /* 0.36410514377569680455 */ - return 0; -} diff --git a/src/intersim2/.svn/pristine/13/13e96ce60fa5bdc9726f48b5186ae562fcd4bbeb.svn-base b/src/intersim2/.svn/pristine/13/13e96ce60fa5bdc9726f48b5186ae562fcd4bbeb.svn-base deleted file mode 100644 index 42bee23..0000000 --- a/src/intersim2/.svn/pristine/13/13e96ce60fa5bdc9726f48b5186ae562fcd4bbeb.svn-base +++ /dev/null @@ -1,53 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _BOOKSIM_CONFIG_HPP_ -#define _BOOKSIM_CONFIG_HPP_ - -#include "config_utils.hpp" - -class BookSimConfig : public Configuration { -protected: - -public: - BookSimConfig( ); -}; - -#endif - -#ifndef _POWER_CONFIG_HPP_ -#define _POWER_CONFIG_HPP_ - -#include "config_utils.hpp" - -class PowerConfig : public Configuration { -public: - PowerConfig( ); - -}; - -#endif diff --git a/src/intersim2/.svn/pristine/14/14292d017cd222997f376c20ca99e10a17cb7e0c.svn-base b/src/intersim2/.svn/pristine/14/14292d017cd222997f376c20ca99e10a17cb7e0c.svn-base deleted file mode 100644 index 07259a3..0000000 --- a/src/intersim2/.svn/pristine/14/14292d017cd222997f376c20ca99e10a17cb7e0c.svn-base +++ /dev/null @@ -1,319 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/*kn.cpp - * - *Meshs, cube, torus - * - */ - -#include "booksim.hpp" -#include -#include -#include "kncube.hpp" -#include "random_utils.hpp" -#include "misc_utils.hpp" - //#include "iq_router.hpp" - - -KNCube::KNCube( const Configuration &config, const string & name, bool mesh ) : -Network( config, name ) -{ - _mesh = mesh; - - _ComputeSize( config ); - _Alloc( ); - _BuildNet( config ); -} - -void KNCube::_ComputeSize( const Configuration &config ) -{ - _k = config.GetInt( "k" ); - _n = config.GetInt( "n" ); - - gK = _k; gN = _n; - _size = powi( _k, _n ); - _channels = 2*_n*_size; - - _nodes = _size; -} - -void KNCube::RegisterRoutingFunctions() { - -} -void KNCube::_BuildNet( const Configuration &config ) -{ - int left_node; - int right_node; - - int right_input; - int left_input; - - int right_output; - int left_output; - - ostringstream router_name; - - //latency type, noc or conventional network - bool use_noc_latency; - use_noc_latency = (config.GetInt("use_noc_latency")==1); - - for ( int node = 0; node < _size; ++node ) { - - router_name << "router"; - - if ( _k > 1 ) { - for ( int dim_offset = _size / _k; dim_offset >= 1; dim_offset /= _k ) { - router_name << "_" << ( node / dim_offset ) % _k; - } - } - - _routers[node] = Router::NewRouter( config, this, router_name.str( ), - node, 2*_n + 1, 2*_n + 1 ); - _timed_modules.push_back(_routers[node]); - - router_name.str(""); - - for ( int dim = 0; dim < _n; ++dim ) { - - //find the neighbor - left_node = _LeftNode( node, dim ); - right_node = _RightNode( node, dim ); - - // - // Current (N)ode - // (L)eft node - // (R)ight node - // - // L--->N<---R - // L<---N--->R - // - - // torus channel is longer due to wrap around - int latency = _mesh ? 1 : 2 ; - - //get the input channel number - right_input = _LeftChannel( right_node, dim ); - left_input = _RightChannel( left_node, dim ); - - //add the input channel - _routers[node]->AddInputChannel( _chan[right_input], _chan_cred[right_input] ); - _routers[node]->AddInputChannel( _chan[left_input], _chan_cred[left_input] ); - - //set input channel latency - if(use_noc_latency){ - _chan[right_input]->SetLatency( latency ); - _chan[left_input]->SetLatency( latency ); - _chan_cred[right_input]->SetLatency( latency ); - _chan_cred[left_input]->SetLatency( latency ); - } else { - _chan[left_input]->SetLatency( 1 ); - _chan_cred[right_input]->SetLatency( 1 ); - _chan_cred[left_input]->SetLatency( 1 ); - _chan[right_input]->SetLatency( 1 ); - } - //get the output channel number - right_output = _RightChannel( node, dim ); - left_output = _LeftChannel( node, dim ); - - //add the output channel - _routers[node]->AddOutputChannel( _chan[right_output], _chan_cred[right_output] ); - _routers[node]->AddOutputChannel( _chan[left_output], _chan_cred[left_output] ); - - //set output channel latency - if(use_noc_latency){ - _chan[right_output]->SetLatency( latency ); - _chan[left_output]->SetLatency( latency ); - _chan_cred[right_output]->SetLatency( latency ); - _chan_cred[left_output]->SetLatency( latency ); - } else { - _chan[right_output]->SetLatency( 1 ); - _chan[left_output]->SetLatency( 1 ); - _chan_cred[right_output]->SetLatency( 1 ); - _chan_cred[left_output]->SetLatency( 1 ); - - } - } - //injection and ejection channel, always 1 latency - _routers[node]->AddInputChannel( _inject[node], _inject_cred[node] ); - _routers[node]->AddOutputChannel( _eject[node], _eject_cred[node] ); - _inject[node]->SetLatency( 1 ); - _eject[node]->SetLatency( 1 ); - } -} - -int KNCube::_LeftChannel( int node, int dim ) -{ - // The base channel for a node is 2*_n*node - int base = 2*_n*node; - // The offset for a left channel is 2*dim + 1 - int off = 2*dim + 1; - - return ( base + off ); -} - -int KNCube::_RightChannel( int node, int dim ) -{ - // The base channel for a node is 2*_n*node - int base = 2*_n*node; - // The offset for a right channel is 2*dim - int off = 2*dim; - return ( base + off ); -} - -int KNCube::_LeftNode( int node, int dim ) -{ - int k_to_dim = powi( _k, dim ); - int loc_in_dim = ( node / k_to_dim ) % _k; - int left_node; - // if at the left edge of the dimension, wraparound - if ( loc_in_dim == 0 ) { - left_node = node + (_k-1)*k_to_dim; - } else { - left_node = node - k_to_dim; - } - - return left_node; -} - -int KNCube::_RightNode( int node, int dim ) -{ - int k_to_dim = powi( _k, dim ); - int loc_in_dim = ( node / k_to_dim ) % _k; - int right_node; - // if at the right edge of the dimension, wraparound - if ( loc_in_dim == ( _k-1 ) ) { - right_node = node - (_k-1)*k_to_dim; - } else { - right_node = node + k_to_dim; - } - - return right_node; -} - -int KNCube::GetN( ) const -{ - return _n; -} - -int KNCube::GetK( ) const -{ - return _k; -} - -/*legacy, not sure how this fits into the own scheme of things*/ -void KNCube::InsertRandomFaults( const Configuration &config ) -{ - int num_fails; - unsigned long prev_seed; - - int node, chan; - int i, j, t, n, c; - bool available; - - bool edge; - - num_fails = config.GetInt( "link_failures" ); - - if ( _size && num_fails ) { - prev_seed = RandomIntLong( ); - RandomSeed( config.GetInt( "fail_seed" ) ); - - vector fail_nodes(_size); - - for ( i = 0; i < _size; ++i ) { - node = i; - - // edge test - edge = false; - for ( n = 0; n < _n; ++n ) { - if ( ( ( node % _k ) == 0 ) || - ( ( node % _k ) == _k - 1 ) ) { - edge = true; - } - node /= _k; - } - - if ( edge ) { - fail_nodes[i] = true; - } else { - fail_nodes[i] = false; - } - } - - for ( i = 0; i < num_fails; ++i ) { - j = RandomInt( _size - 1 ); - available = false; - - for ( t = 0; ( t < _size ) && (!available); ++t ) { - node = ( j + t ) % _size; - - if ( !fail_nodes[node] ) { - // check neighbors - c = RandomInt( 2*_n - 1 ); - - for ( n = 0; ( n < 2*_n ) && (!available); ++n ) { - chan = ( n + c ) % 2*_n; - - if ( chan % 1 ) { - available = fail_nodes[_LeftNode( node, chan/2 )]; - } else { - available = fail_nodes[_RightNode( node, chan/2 )]; - } - } - } - - if ( !available ) { - cout << "skipping " << node << endl; - } - } - - if ( t == _size ) { - Error( "Could not find another possible fault channel" ); - } - - - OutChannelFault( node, chan ); - fail_nodes[node] = true; - - for ( n = 0; ( n < _n ) && available ; ++n ) { - fail_nodes[_LeftNode( node, n )] = true; - fail_nodes[_RightNode( node, n )] = true; - } - - cout << "failure at node " << node << ", channel " - << chan << endl; - } - - RandomSeed( prev_seed ); - } -} - -double KNCube::Capacity( ) const -{ - return (double)_k / ( _mesh ? 8.0 : 4.0 ); -} diff --git a/src/intersim2/.svn/pristine/14/14cfb5d4ea815b6697d047697a25ef8cfb9e17de.svn-base b/src/intersim2/.svn/pristine/14/14cfb5d4ea815b6697d047697a25ef8cfb9e17de.svn-base deleted file mode 100644 index ba64824..0000000 --- a/src/intersim2/.svn/pristine/14/14cfb5d4ea815b6697d047697a25ef8cfb9e17de.svn-base +++ /dev/null @@ -1,57 +0,0 @@ -// $Id$ - -// Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -//A single cross 10X10 cross bar under injection mode - -topology = fly; - -k = 10; -n = 1; - -num_vcs = 8; - -vc_buf_size = 8; - -vc_allocator = separable_input_first; -sw_allocator = separable_input_first; - -routing_function = dest_tag; - -traffic = uniform; - -use_read_write = 0; - -injection_rate = 1.0; - - - - -sample_period = 100000; - -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; -st_final_delay = 1; diff --git a/src/intersim2/.svn/pristine/15/1567f00df3a29e4f360b35e014b1f69cf281f55a.svn-base b/src/intersim2/.svn/pristine/15/1567f00df3a29e4f360b35e014b1f69cf281f55a.svn-base deleted file mode 100644 index 5a20263..0000000 --- a/src/intersim2/.svn/pristine/15/1567f00df3a29e4f360b35e014b1f69cf281f55a.svn-base +++ /dev/null @@ -1,68 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _PRIO_ARB_HPP_ -#define _PRIO_ARB_HPP_ - -#include - -#include "module.hpp" -#include "config_utils.hpp" - -class PriorityArbiter : public Module { - int _rr_ptr; - -protected: - const int _inputs; - - struct sRequest { - int in; - int label; - int pri; - }; - - list _requests; - - int _match; - -public: - PriorityArbiter( const Configuration &config, - Module *parent, const string& name, - int inputs ); - - void Clear( ); - - void AddRequest( int in, int label = 0, int pri = 0 ); - void RemoveRequest( int in, int label = 0 ); - - int Match( ) const; - - void Arbitrate( ); - void Update( ); -}; - -#endif diff --git a/src/intersim2/.svn/pristine/1a/1abf005acda7eb93dad10f55694f27a84ba74f91.svn-base b/src/intersim2/.svn/pristine/1a/1abf005acda7eb93dad10f55694f27a84ba74f91.svn-base deleted file mode 100644 index cae1e45..0000000 --- a/src/intersim2/.svn/pristine/1a/1abf005acda7eb93dad10f55694f27a84ba74f91.svn-base +++ /dev/null @@ -1,111 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/*wavefront.cpp - * - *The wave front allocator - * - */ -#include "booksim.hpp" - -#include "wavefront.hpp" - -Wavefront::Wavefront( Module *parent, const string& name, - int inputs, int outputs, bool skip_diags ) : - DenseAllocator( parent, name, inputs, outputs ), - _last_in(-1), _last_out(-1), _skip_diags(skip_diags), - _square(max(inputs, outputs)), _pri(0), _num_requests(0) -{ -} - -void Wavefront::AddRequest( int in, int out, int label, - int in_pri, int out_pri ) -{ - DenseAllocator::AddRequest(in, out, label, in_pri, out_pri); - _num_requests++; - _last_in = in; - _last_out = out; - _priorities.insert(make_pair(out_pri, in_pri)); -} - -void Wavefront::Allocate( ) -{ - - int first_diag = -1; - - if(_num_requests == 0) - - // bypass allocator completely if there were no requests - return; - - if(_num_requests == 1) { - - // if we only had a single request, we can immediately grant it - _inmatch[_last_in] = _last_out; - _outmatch[_last_out] = _last_in; - first_diag = _last_in + _last_out; - - } else { - - // otherwise we have to loop through the diagonals of request matrix - - for(set >::const_reverse_iterator iter = - _priorities.rbegin(); - iter != _priorities.rend(); ++iter) { - - for ( int p = 0; p < _square; ++p ) { - for ( int output = 0; output < _square; ++output ) { - int input = ( ( _pri + p ) + ( _square - output ) ) % _square; - if ( ( input < _inputs ) && ( output < _outputs ) && - ( _inmatch[input] == -1 ) && ( _outmatch[output] == -1 ) && - ( _request[input][output].label != -1 ) && - ( _request[input][output].in_pri == iter->second ) && - ( _request[input][output].out_pri == iter->first ) ) { - // Grant! - _inmatch[input] = output; - _outmatch[output] = input; - if(first_diag < 0) { - first_diag = input + output; - } - } - } - } - } - } - - _num_requests = 0; - _last_in = -1; - _last_out = -1; - _priorities.clear(); - - assert(first_diag >= 0); - - // Round-robin the priority diagonal - _pri = ( ( _skip_diags ? first_diag : _pri ) + 1 ) % _square; -} - - diff --git a/src/intersim2/.svn/pristine/1a/1afc46cd26811b568cd238a5bb6cf4a3e9687edf.svn-base b/src/intersim2/.svn/pristine/1a/1afc46cd26811b568cd238a5bb6cf4a3e9687edf.svn-base deleted file mode 100644 index 4df14c7..0000000 --- a/src/intersim2/.svn/pristine/1a/1afc46cd26811b568cd238a5bb6cf4a3e9687edf.svn-base +++ /dev/null @@ -1,54 +0,0 @@ -%{ - -#include "y.tab.h" - -static unsigned int lineno = 1; - -void config_error(char * msg, int lineno); -void yyerror(char * msg); - -extern int config_input(char *, int); -#undef YY_INPUT -#define YY_INPUT(b, r, ms) (r = config_input(b, ms)) - -%} - -Digit [0-9] -Exponent [eE][+-]?{Digit}+ -DblConst ({Digit}*\.)?{Digit}+{Exponent}? -StrConst [A-Za-z_\-/\.][A-Za-z0-9_\-/\.\+(\{\,)\}]* - -%% - - /* Ignore comments and all spaces */ - -\/\/[^\n]* ; -[ \t\r]* ; - -\n { lineno++; } - - /* Commands */ - -\{[A-Za-z0-9_\-\.(\{\,)\}]+(\,[A-Za-z0-9_\-\.(\{\,)\}]+)*\} { yylval.name = strdup( yytext ); return STR; } - --?[0-9]+ { yylval.num = atoi( yytext ); return NUM; } - --?[0-9]*\.[0-9]+ { yylval.fnum = atof( yytext ); return FNUM; } - --?{DblConst} { yylval.fnum = atof( yytext ); return FNUM;} - -{StrConst} { yylval.name = strdup( yytext ); return STR; } - -. { return yytext[0]; } - -%% - -void yyerror( char * msg ) -{ - config_error( msg, lineno ); -} - -int yywrap() -{ - return 1; -} diff --git a/src/intersim2/.svn/pristine/1e/1e4194e8f6ff3aacdde8d0caf868ab69490d6a6c.svn-base b/src/intersim2/.svn/pristine/1e/1e4194e8f6ff3aacdde8d0caf868ab69490d6a6c.svn-base deleted file mode 100644 index f1ad2fd..0000000 --- a/src/intersim2/.svn/pristine/1e/1e4194e8f6ff3aacdde8d0caf868ab69490d6a6c.svn-base +++ /dev/null @@ -1,447 +0,0 @@ -// $Id$ -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/*config_utils.cpp - * - *The configuration object which contained the parsed data from the - *configuration file - */ - -#include "booksim.hpp" -#include -#include -#include -#include -#include - -#include "config_utils.hpp" - -Configuration *Configuration::theConfig = 0; - -Configuration::Configuration() -{ - theConfig = this; - _config_file = 0; -} - -void Configuration::AddStrField(string const & field, string const & value) -{ - _str_map[field] = value; -} - -void Configuration::Assign(string const & field, string const & value) -{ - map::const_iterator match; - - match = _str_map.find(field); - if(match != _str_map.end()) { - _str_map[field] = value; - } else { - ParseError("Unknown string field: " + field); - } -} - -void Configuration::Assign(string const & field, int value) -{ - map::const_iterator match; - - match = _int_map.find(field); - if(match != _int_map.end()) { - _int_map[field] = value; - } else { - ParseError("Unknown integer field: " + field); - } -} - -void Configuration::Assign(string const & field, double value) -{ - map::const_iterator match; - - match = _float_map.find(field); - if(match != _float_map.end()) { - _float_map[field] = value; - } else { - ParseError("Unknown double field: " + field); - } -} - -string Configuration::GetStr(string const & field) const -{ - map::const_iterator match; - - match = _str_map.find(field); - if(match != _str_map.end()) { - return match->second; - } else { - ParseError("Unknown string field: " + field); - exit(-1); - } -} - -int Configuration::GetInt(string const & field) const -{ - map::const_iterator match; - - match = _int_map.find(field); - if(match != _int_map.end()) { - return match->second; - } else { - ParseError("Unknown integer field: " + field); - exit(-1); - } -} - -double Configuration::GetFloat(string const & field) const -{ - map::const_iterator match; - - match = _float_map.find(field); - if(match != _float_map.end()) { - return match->second; - } else { - ParseError("Unknown double field: " + field); - exit(-1); - } -} - -vector Configuration::GetStrArray(string const & field) const -{ - string const param_str = GetStr(field); - return tokenize_str(param_str); -} - -vector Configuration::GetIntArray(string const & field) const -{ - string const param_str = GetStr(field); - return tokenize_int(param_str); -} - -vector Configuration::GetFloatArray(string const & field) const -{ - string const param_str = GetStr(field); - return tokenize_float(param_str); -} - -void Configuration::ParseFile(string const & filename) -{ - if((_config_file = fopen(filename.c_str(), "r")) == 0) { - cerr << "Could not open configuration file " << filename << endl; - exit(-1); - } - - yyparse(); - - fclose(_config_file); - _config_file = 0; -} - -void Configuration::ParseString(string const & str) -{ - _config_string = str + ';'; - yyparse(); - _config_string = ""; -} - -int Configuration::Input(char * line, int max_size) -{ - int length = 0; - - if(_config_file) { - length = fread(line, 1, max_size, _config_file); - } else { - length = _config_string.length(); - _config_string.copy(line, max_size); - _config_string.clear(); - } - - return length; -} - -void Configuration::ParseError(string const & msg, unsigned int lineno) const -{ - if(lineno) { - cerr << "Parse error on line " << lineno << " : " << msg << endl; - } else { - cerr << "Parse error : " << msg << endl; - } - - - exit( -1 ); -} - -Configuration * Configuration::GetTheConfig() -{ - return theConfig; -} - -//============================================================ - -extern "C" void config_error( char const * msg, int lineno ) -{ - Configuration::GetTheConfig( )->ParseError( msg, lineno ); -} - -extern "C" void config_assign_string( char const * field, char const * value ) -{ - Configuration::GetTheConfig()->Assign(field, value); -} - -extern "C" void config_assign_int( char const * field, int value ) -{ - Configuration::GetTheConfig()->Assign(field, value); -} - -extern "C" void config_assign_float( char const * field, double value ) -{ - Configuration::GetTheConfig()->Assign(field, value); -} - -extern "C" int config_input(char * line, int max_size) -{ - return Configuration::GetTheConfig()->Input(line, max_size); -} - -bool ParseArgs(Configuration * cf, int argc, char * * argv) -{ - bool rc = false; - - //all dashed variables are ignored by the arg parser - for(int i = 1; i < argc; ++i) { - string arg(argv[i]); - size_t pos = arg.find('='); - bool dash = (argv[i][0] =='-'); - if(pos == string::npos && !dash) { - // parse config file - cf->ParseFile( argv[i] ); - ifstream in(argv[i]); - cout << "BEGIN Configuration File: " << argv[i] << endl; - while (!in.eof()) { - char c; - in.get(c); - cout << c ; - } - cout << "END Configuration File: " << argv[i] << endl; - rc = true; - } else if(pos != string::npos) { - // override individual parameter - cout << "OVERRIDE Parameter: " << arg << endl; - cf->ParseString(argv[i]); - } - } - - return rc; -} - - -//helpful for the GUI, write out nearly all variables contained in a config file. -//However, it can't and won't write out empty strings since the booksim yacc -//parser won't be abled to parse blank strings -void Configuration::WriteFile(string const & filename) { - - ostream *config_out= new ofstream(filename.c_str()); - - - for(map::const_iterator i = _str_map.begin(); - i!=_str_map.end(); - i++){ - //the parser won't read empty strings - if(i->second[0]!='\0'){ - *config_out<first<<" = "<second<<";"<::const_iterator i = _int_map.begin(); - i!=_int_map.end(); - i++){ - *config_out<first<<" = "<second<<";"<::const_iterator i = _float_map.begin(); - i!=_float_map.end(); - i++){ - *config_out<first<<" = "<second<<";"<flush(); - delete config_out; - -} - - - -void Configuration::WriteMatlabFile(ostream * config_out) const { - - - - for(map::const_iterator i = _str_map.begin(); - i!=_str_map.end(); - i++){ - //the parser won't read blanks lolz - if(i->second[0]!='\0'){ - *config_out<<"%"<first<<" = \'"<second<<"\';"<::const_iterator i = _int_map.begin(); - i!=_int_map.end(); - i++){ - *config_out<<"%"<first<<" = "<second<<";"<::const_iterator i = _float_map.begin(); - i!=_float_map.end(); - i++){ - *config_out<<"%"<first<<" = "<second<<";"<flush(); - -} - -vector tokenize_str(string const & data) -{ - vector values; - - // no elements, no braces --> empty list - if(data.empty()) { - return values; - } - - // doesn't start with an opening brace --> treat as single element - // note that this element can potentially contain nested lists - if(data[0] != '{') { - values.push_back(data); - return values; - } - - size_t start = 1; - int nested = 0; - - size_t curr = start; - - while(string::npos != (curr = data.find_first_of("{,}", curr))) { - - if(data[curr] == '{') { - ++nested; - } else if((data[curr] == '}') && nested) { - --nested; - } else if(!nested) { - if(curr > start) { - string token = data.substr(start, curr - start); - values.push_back(token); - } - start = curr + 1; - } - ++curr; - } - assert(!nested); - - return values; -} - -vector tokenize_int(string const & data) -{ - vector values; - - // no elements, no braces --> empty list - if(data.empty()) { - return values; - } - - // doesn't start with an opening brace --> treat as single element - // note that this element can potentially contain nested lists - if(data[0] != '{') { - values.push_back(atoi(data.c_str())); - return values; - } - - size_t start = 1; - int nested = 0; - - size_t curr = start; - - while(string::npos != (curr = data.find_first_of("{,}", curr))) { - - if(data[curr] == '{') { - ++nested; - } else if((data[curr] == '}') && nested) { - --nested; - } else if(!nested) { - if(curr > start) { - string token = data.substr(start, curr - start); - values.push_back(atoi(token.c_str())); - } - start = curr + 1; - } - ++curr; - } - assert(!nested); - - return values; -} - -vector tokenize_float(string const & data) -{ - vector values; - - // no elements, no braces --> empty list - if(data.empty()) { - return values; - } - - // doesn't start with an opening brace --> treat as single element - // note that this element can potentially contain nested lists - if(data[0] != '{') { - values.push_back(atof(data.c_str())); - return values; - } - - size_t start = 1; - int nested = 0; - - size_t curr = start; - - while(string::npos != (curr = data.find_first_of("{,}", curr))) { - - if(data[curr] == '{') { - ++nested; - } else if((data[curr] == '}') && nested) { - --nested; - } else if(!nested) { - if(curr > start) { - string token = data.substr(start, curr - start); - values.push_back(atof(token.c_str())); - } - start = curr + 1; - } - ++curr; - } - assert(!nested); - - return values; -} diff --git a/src/intersim2/.svn/pristine/1f/1f35cbdd9ebe1ee0a41e949e03d51d268ac55bad.svn-base b/src/intersim2/.svn/pristine/1f/1f35cbdd9ebe1ee0a41e949e03d51d268ac55bad.svn-base deleted file mode 100644 index 9ac579a..0000000 --- a/src/intersim2/.svn/pristine/1f/1f35cbdd9ebe1ee0a41e949e03d51d268ac55bad.svn-base +++ /dev/null @@ -1,97 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _PIPEFIFO_HPP_ -#define _PIPEFIFO_HPP_ - -#include - -#include "module.hpp" - -template class PipelineFIFO : public Module { - int _lanes; - int _depth; - - int _pipe_len; - int _pipe_ptr; - - vector > _data; - -public: - PipelineFIFO( Module *parent, const string& name, int lanes, int depth ); - ~PipelineFIFO( ); - - void Write( T* val, int lane = 0 ); - void WriteAll( T* val ); - - T* Read( int lane = 0 ); - - void Advance( ); -}; - -template PipelineFIFO::PipelineFIFO( Module *parent, - const string& name, - int lanes, int depth ) : - Module( parent, name ), - _lanes( lanes ), _depth( depth ) -{ - _pipe_len = depth + 1; - _pipe_ptr = 0; - - _data.resize(_lanes); - for ( int l = 0; l < _lanes; ++l ) { - _data[l].resize(_pipe_len, 0); - } -} - -template PipelineFIFO::~PipelineFIFO( ) -{ -} - -template void PipelineFIFO::Write( T* val, int lane ) -{ - _data[lane][_pipe_ptr] = val; -} - -template void PipelineFIFO::WriteAll( T* val ) -{ - for ( int l = 0; l < _lanes; ++l ) { - _data[l][_pipe_ptr] = val; - } -} - -template T* PipelineFIFO::Read( int lane ) -{ - return _data[lane][_pipe_ptr]; -} - -template void PipelineFIFO::Advance( ) -{ - _pipe_ptr = ( _pipe_ptr + 1 ) % _pipe_len; -} - -#endif diff --git a/src/intersim2/.svn/pristine/1f/1f6b483285599def0e7fea5379c0af7a176d2736.svn-base b/src/intersim2/.svn/pristine/1f/1f6b483285599def0e7fea5379c0af7a176d2736.svn-base deleted file mode 100644 index baded43..0000000 --- a/src/intersim2/.svn/pristine/1f/1f6b483285599def0e7fea5379c0af7a176d2736.svn-base +++ /dev/null @@ -1,223 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/*vc.cpp - * - *this class describes a virtual channel in a router - *it includes buffers and virtual channel state and controls - * - *This class calls the routing functions - */ - -#include -#include - -#include "globals.hpp" -#include "booksim.hpp" -#include "vc.hpp" - -const char * const VC::VCSTATE[] = {"idle", - "routing", - "vc_alloc", - "active"}; - -VC::VC( const Configuration& config, int outputs, - Module *parent, const string& name ) - : Module( parent, name ), - _state(idle), _out_port(-1), _out_vc(-1), _pri(0), _watched(false), - _expected_pid(-1), _last_id(-1), _last_pid(-1) -{ - _lookahead_routing = !config.GetInt("routing_delay"); - _route_set = _lookahead_routing ? NULL : new OutputSet( ); - - string priority = config.GetStr( "priority" ); - if ( priority == "local_age" ) { - _pri_type = local_age_based; - } else if ( priority == "queue_length" ) { - _pri_type = queue_length_based; - } else if ( priority == "hop_count" ) { - _pri_type = hop_count_based; - } else if ( priority == "none" ) { - _pri_type = none; - } else { - _pri_type = other; - } - - _priority_donation = config.GetInt("vc_priority_donation"); -} - -VC::~VC() -{ - if(!_lookahead_routing) { - delete _route_set; - } -} - -void VC::AddFlit( Flit *f ) -{ - assert(f); - - if(_expected_pid >= 0) { - if(f->pid != _expected_pid) { - ostringstream err; - err << "Received flit " << f->id << " with unexpected packet ID: " << f->pid - << " (expected: " << _expected_pid << ")"; - Error(err.str()); - } else if(f->tail) { - _expected_pid = -1; - } - } else if(!f->tail) { - _expected_pid = f->pid; - } - - // update flit priority before adding to VC buffer - if(_pri_type == local_age_based) { - f->pri = numeric_limits::max() - GetSimTime(); - assert(f->pri >= 0); - } else if(_pri_type == hop_count_based) { - f->pri = f->hops; - assert(f->pri >= 0); - } - - _buffer.push_back(f); - UpdatePriority(); -} - -Flit *VC::RemoveFlit( ) -{ - Flit *f = NULL; - if ( !_buffer.empty( ) ) { - f = _buffer.front( ); - _buffer.pop_front( ); - _last_id = f->id; - _last_pid = f->pid; - UpdatePriority(); - } else { - Error("Trying to remove flit from empty buffer."); - } - return f; -} - - - -void VC::SetState( eVCState s ) -{ - Flit * f = FrontFlit(); - - if(f && f->watch) - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Changing state from " << VC::VCSTATE[_state] - << " to " << VC::VCSTATE[s] << "." << endl; - - _state = s; -} - -const OutputSet *VC::GetRouteSet( ) const -{ - return _route_set; -} - -void VC::SetRouteSet( OutputSet * output_set ) -{ - _route_set = output_set; - _out_port = -1; - _out_vc = -1; -} - -void VC::SetOutput( int port, int vc ) -{ - _out_port = port; - _out_vc = vc; -} - -void VC::UpdatePriority() -{ - if(_buffer.empty()) return; - if(_pri_type == queue_length_based) { - _pri = _buffer.size(); - } else if(_pri_type != none) { - Flit * f = _buffer.front(); - if((_pri_type != local_age_based) && _priority_donation) { - Flit * df = f; - for(size_t i = 1; i < _buffer.size(); ++i) { - Flit * bf = _buffer[i]; - if(bf->pri > df->pri) df = bf; - } - if((df != f) && (df->watch || f->watch)) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Flit " << df->id - << " donates priority to flit " << f->id - << "." << endl; - } - f = df; - } - if(f->watch) - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Flit " << f->id - << " sets priority to " << f->pri - << "." << endl; - _pri = f->pri; - } -} - - -void VC::Route( tRoutingFunction rf, const Router* router, const Flit* f, int in_channel ) -{ - rf( router, f, in_channel, _route_set, false ); - _out_port = -1; - _out_vc = -1; -} - -// ==== Debug functions ==== - -void VC::SetWatch( bool watch ) -{ - _watched = watch; -} - -bool VC::IsWatched( ) const -{ - return _watched; -} - -void VC::Display( ostream & os ) const -{ - if ( _state != VC::idle ) { - os << FullName() << ": " - << " state: " << VCSTATE[_state]; - if(_state == VC::active) { - os << " out_port: " << _out_port - << " out_vc: " << _out_vc; - } - os << " fill: " << _buffer.size(); - if(!_buffer.empty()) { - os << " front: " << _buffer.front()->id; - } - os << " pri: " << _pri; - os << endl; - } -} diff --git a/src/intersim2/.svn/pristine/23/235d7e656a8ce9818d81cd7eb47ca78febbe438a.svn-base b/src/intersim2/.svn/pristine/23/235d7e656a8ce9818d81cd7eb47ca78febbe438a.svn-base deleted file mode 100644 index ef62dfd..0000000 --- a/src/intersim2/.svn/pristine/23/235d7e656a8ce9818d81cd7eb47ca78febbe438a.svn-base +++ /dev/null @@ -1,62 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _KNCUBE_HPP_ -#define _KNCUBE_HPP_ - -#include "network.hpp" - -class KNCube : public Network { - - bool _mesh; - - int _k; - int _n; - - void _ComputeSize( const Configuration &config ); - void _BuildNet( const Configuration &config ); - - int _LeftChannel( int node, int dim ); - int _RightChannel( int node, int dim ); - - int _LeftNode( int node, int dim ); - int _RightNode( int node, int dim ); - -public: - KNCube( const Configuration &config, const string & name, bool mesh ); - static void RegisterRoutingFunctions(); - - int GetN( ) const; - int GetK( ) const; - - double Capacity( ) const; - - void InsertRandomFaults( const Configuration &config ); - -}; - -#endif diff --git a/src/intersim2/.svn/pristine/24/244c1dc93f9a90c660c06c653d3809b739d40458.svn-base b/src/intersim2/.svn/pristine/24/244c1dc93f9a90c660c06c653d3809b739d40458.svn-base deleted file mode 100644 index 7c6ade8..0000000 --- a/src/intersim2/.svn/pristine/24/244c1dc93f9a90c660c06c653d3809b739d40458.svn-base +++ /dev/null @@ -1,68 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _BUFFER_MONITOR_HPP_ -#define _BUFFER_MONITOR_HPP_ - -#include -#include - -using namespace std; - -class Flit; - -class BufferMonitor { - int _cycles ; - int _inputs ; - int _classes ; - vector _reads ; - vector _writes ; - int index( int input, int cl ) const ; -public: - BufferMonitor( int inputs, int classes ) ; - void cycle() ; - void write( int input, Flit const * f ) ; - void read( int input, Flit const * f ) ; - inline const vector & GetReads() const { - return _reads; - } - inline const vector & GetWrites() const { - return _writes; - } - inline int NumInputs() const { - return _inputs; - } - inline int NumClasses() const { - return _classes; - } - void display(ostream & os) const; - -} ; - -ostream & operator<<( ostream & os, BufferMonitor const & obj ) ; - -#endif diff --git a/src/intersim2/.svn/pristine/2a/2a04a186dfedaa33f2a0336556c086868dd6ccfc.svn-base b/src/intersim2/.svn/pristine/2a/2a04a186dfedaa33f2a0336556c086868dd6ccfc.svn-base deleted file mode 100644 index 3bdbd7b..0000000 --- a/src/intersim2/.svn/pristine/2a/2a04a186dfedaa33f2a0336556c086868dd6ccfc.svn-base +++ /dev/null @@ -1,174 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _TRAFFIC_HPP_ -#define _TRAFFIC_HPP_ - -#include -#include -#include "config_utils.hpp" - -using namespace std; - -class TrafficPattern { -protected: - int _nodes; - TrafficPattern(int nodes); -public: - virtual ~TrafficPattern() {} - virtual void reset(); - virtual int dest(int source) = 0; - static TrafficPattern * New(string const & pattern, int nodes, - Configuration const * const config = NULL); -}; - -class PermutationTrafficPattern : public TrafficPattern { -protected: - PermutationTrafficPattern(int nodes); -}; - -class BitPermutationTrafficPattern : public PermutationTrafficPattern { -protected: - BitPermutationTrafficPattern(int nodes); -}; - -class BitCompTrafficPattern : public BitPermutationTrafficPattern { -public: - BitCompTrafficPattern(int nodes); - virtual int dest(int source); -}; - -class TransposeTrafficPattern : public BitPermutationTrafficPattern { -protected: - int _shift; -public: - TransposeTrafficPattern(int nodes); - virtual int dest(int source); -}; - -class BitRevTrafficPattern : public BitPermutationTrafficPattern { -public: - BitRevTrafficPattern(int nodes); - virtual int dest(int source); -}; - -class ShuffleTrafficPattern : public BitPermutationTrafficPattern { -public: - ShuffleTrafficPattern(int nodes); - virtual int dest(int source); -}; - -class DigitPermutationTrafficPattern : public PermutationTrafficPattern { -protected: - int _k; - int _n; - int _xr; - DigitPermutationTrafficPattern(int nodes, int k, int n, int xr = 1); -}; - -class TornadoTrafficPattern : public DigitPermutationTrafficPattern { -public: - TornadoTrafficPattern(int nodes, int k, int n, int xr = 1); - virtual int dest(int source); -}; - -class NeighborTrafficPattern : public DigitPermutationTrafficPattern { -public: - NeighborTrafficPattern(int nodes, int k, int n, int xr = 1); - virtual int dest(int source); -}; - -class RandomPermutationTrafficPattern : public TrafficPattern { -private: - vector _dest; - inline void randomize(int seed); -public: - RandomPermutationTrafficPattern(int nodes, int seed); - virtual int dest(int source); -}; - -class RandomTrafficPattern : public TrafficPattern { -protected: - RandomTrafficPattern(int nodes); -}; - -class UniformRandomTrafficPattern : public RandomTrafficPattern { -public: - UniformRandomTrafficPattern(int nodes); - virtual int dest(int source); -}; - -class UniformBackgroundTrafficPattern : public RandomTrafficPattern { -private: - set _excluded; -public: - UniformBackgroundTrafficPattern(int nodes, vector excluded_nodes); - virtual int dest(int source); -}; - -class DiagonalTrafficPattern : public RandomTrafficPattern { -public: - DiagonalTrafficPattern(int nodes); - virtual int dest(int source); -}; - -class AsymmetricTrafficPattern : public RandomTrafficPattern { -public: - AsymmetricTrafficPattern(int nodes); - virtual int dest(int source); -}; - -class Taper64TrafficPattern : public RandomTrafficPattern { -public: - Taper64TrafficPattern(int nodes); - virtual int dest(int source); -}; - -class BadPermDFlyTrafficPattern : public DigitPermutationTrafficPattern { -public: - BadPermDFlyTrafficPattern(int nodes, int k, int n); - virtual int dest(int source); -}; - -class BadPermYarcTrafficPattern : public DigitPermutationTrafficPattern { -public: - BadPermYarcTrafficPattern(int nodes, int k, int n, int xr = 1); - virtual int dest(int source); -}; - -class HotSpotTrafficPattern : public TrafficPattern { -private: - vector _hotspots; - vector _rates; - int _max_val; -public: - HotSpotTrafficPattern(int nodes, vector hotspots, - vector rates = vector()); - virtual int dest(int source); -}; - -#endif diff --git a/src/intersim2/.svn/pristine/2c/2ca444c5a28eb3f8aaffcf0702edd18d4fe31fad.svn-base b/src/intersim2/.svn/pristine/2c/2ca444c5a28eb3f8aaffcf0702edd18d4fe31fad.svn-base deleted file mode 100644 index 9ee46ab..0000000 --- a/src/intersim2/.svn/pristine/2c/2ca444c5a28eb3f8aaffcf0702edd18d4fe31fad.svn-base +++ /dev/null @@ -1,61 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _RANDOM_UTILS_HPP_ -#define _RANDOM_UTILS_HPP_ - - // interface to Knuth's RANARRAY RNG -void ran_start(long seed); -long ran_next( ); -void ranf_start(long seed); -double ranf_next( ); - -inline void RandomSeed( long seed ) { - ran_start( seed ); - ranf_start( seed ); -} - -inline unsigned long RandomIntLong( ) { - return ran_next( ); -} - -// Returns a random integer in the range [0,max] -inline int RandomInt( int max ) { - return ( ran_next( ) % (max+1) ); -} - -// Returns a random floating-point value in the rage [0,1] -inline double RandomFloat( ) { - return ranf_next( ); -} - -// Returns a random floating-point value in the rage [0,max] -inline double RandomFloat( double max ) { - return ( ranf_next( ) * max ); -} - -#endif diff --git a/src/intersim2/.svn/pristine/2e/2e9094d44209e8c6464b2834012a6dc9dd860340.svn-base b/src/intersim2/.svn/pristine/2e/2e9094d44209e8c6464b2834012a6dc9dd860340.svn-base deleted file mode 100644 index 006b06b..0000000 --- a/src/intersim2/.svn/pristine/2e/2e9094d44209e8c6464b2834012a6dc9dd860340.svn-base +++ /dev/null @@ -1,501 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/*anynet - * - *Network setup file format - *example 1: - *router 0 router 1 15 router 2 - * - *Router 0 is connect to router 1 with a 15-cycle channel, and router 0 is connected to - * router 2 with a 1-cycle channel, the channels latency are unidirectional, so channel - * from router 1 back to router 0 is only single-cycle because it was not specified - * - *example 2: - *router 0 node 0 node 1 5 node 2 5 - * - *Router 0 is directly connected to node 0-2. Channel latency is 5cycles for 1 and 2. In - * this case the latency specification is bidirectional, the injeciton and ejection lat - * for node 1 and 2 are 5-cycle - * - *other notes: - * - *Router and node numbers must be sequential starting with 0 - *Credit channel latency follows the channel latency, even though it travels in revse - * direction this might not be desired - * - */ - -#include "anynet.hpp" -#include -#include -#include -#include -//this is a hack, I can't easily get the routing talbe out of the network -map* global_routing_table; - -AnyNet::AnyNet( const Configuration &config, const string & name ) - : Network( config, name ){ - - router_list.resize(2); - _ComputeSize( config ); - _Alloc( ); - _BuildNet( config ); -} - -AnyNet::~AnyNet(){ - for(int i = 0; i < 2; ++i) { - for(map > >::iterator iter = router_list[i].begin(); - iter != router_list[i].end(); - ++iter) { - iter->second.clear(); - } - } -} - -void AnyNet::_ComputeSize( const Configuration &config ){ - file_name = config.GetStr("network_file"); - if(file_name==""){ - cout<<"No network file name provided"<::iterator iter; - for(iter = node_list.begin(); iter!=node_list.end(); iter++){ - cout<<"Node "<first; - cout<<"\tRouter "<second< > >::iterator iter3; - cout<<"\n****************router to node listing*************\n"; - for(iter3 = router_list[0].begin(); iter3!=router_list[0].end(); iter3++){ - cout<<"Router "<first< >::iterator iter2; - for(iter2 = iter3->second.begin(); - iter2!=iter3->second.end(); - iter2++){ - cout<<"\t Node "<first<<" lat "<second.second<first< >::iterator iter2; - if(iter3->second.size() == 0){ - cout<<"Caution Router "<first - <<" is not connected to any other Router\n"<second.begin(); - iter2!=iter3->second.end(); - iter2++){ - cout<<"\t Router "<first<<" lat "<second.second< > >::iterator niter; - for(niter = router_list[0].begin(); niter!=router_list[0].end(); niter++){ - map > >::iterator riter = router_list[1].find(niter->first); - //calculate radix - int radix = niter->second.size()+riter->second.size(); - int node = niter->first; - cout<<"router "< >::iterator nniter; - for(nniter = niter->second.begin();nniter!=niter->second.end(); nniter++){ - int link = nniter->first; - //add the outport port assined to the map - (niter->second)[link].first = outport[node]; - outport[node]++; - cout<<"\t connected to node "<second.first - <<" lat "<second.second<SetLatency(nniter->second.second); - _inject_cred[link]->SetLatency(nniter->second.second); - _eject[link]->SetLatency(nniter->second.second); - _eject_cred[link]->SetLatency(nniter->second.second); - - _routers[node]->AddInputChannel( _inject[link], _inject_cred[link] ); - _routers[node]->AddOutputChannel( _eject[link], _eject_cred[link] ); - } - - } - - cout<<"==========================Router to Router =====================\n"; - //add inter router channels - //since there is no way to systematically number the channels we just start from 0 - //the map, is a mapping of output->input - int channel_count = 0; - for(niter = router_list[0].begin(); niter!=router_list[0].end(); niter++){ - map > >::iterator riter = router_list[1].find(niter->first); - int node = niter->first; - map >::iterator rriter; - cout<<"router "<second.begin();rriter!=riter->second.end(); rriter++){ - int other_node = rriter->first; - int link = channel_count; - //add the outport port assined to the map - (riter->second)[other_node].first = outport[node]; - outport[node]++; - cout<<"\t connected to router "<second.first - <<" lat "<second.second<SetLatency(rriter->second.second); - _chan_cred[link]->SetLatency(rriter->second.second); - - _routers[node]->AddOutputChannel( _chan[link], _chan_cred[link] ); - _routers[other_node]->AddInputChannel( _chan[link], _chan_cred[link]); - channel_count++; - } - } - - buildRoutingTable(); - -} - - -void AnyNet::RegisterRoutingFunctions() { - gRoutingFunctionMap["min_anynet"] = &min_anynet; -} - -void min_anynet( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ){ - int out_port=-1; - if(!inject){ - assert(global_routing_table[r->GetID()].count(f->dest)!=0); - out_port=global_routing_table[r->GetID()][f->dest]; - } - - - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - - outputs->Clear( ); - - outputs->AddRange( out_port , vcBegin, vcEnd ); -} - -void AnyNet::buildRoutingTable(){ - cout<<"========================== Routing table =====================\n"; - routing_table.resize(_size); - for(int i = 0; i<_size; i++){ - route(i); - } - global_routing_table = &routing_table[0]; -} - - -//11/7/2012 -//basically djistra's, tested on a large dragonfly anynet configuration -void AnyNet::route(int r_start){ - int* dist = new int[_size]; - int* prev = new int[_size]; - set rlist; - for(int i = 0; i<_size; i++){ - dist[i] = numeric_limits::max(); - prev[i] = -1; - rlist.insert(i); - } - dist[r_start] = 0; - while(!rlist.empty()){ - //find min - int min_dist = numeric_limits::max(); - int min_cand = -1; - for(set::iterator i = rlist.begin(); - i!=rlist.end(); - i++){ - if(dist[*i] >::iterator i = router_list[1][min_cand].begin(); - i!=router_list[1][min_cand].end(); - i++){ - int new_dist = dist[min_cand] + i->second.second;//distance is hops not cycles - if(new_dist < dist[i->first]){ - dist[i->first] = new_dist; - prev[i->first] = min_cand; - } - } - } - - //post process from the prev list - for(int i = 0; i<_size; i++){ - if(prev[i] ==-1){ //self - assert(i == r_start); - for(map >::iterator iter = router_list[0][i].begin(); - iter!=router_list[0][i].end(); - iter++){ - routing_table[r_start][iter->first]=iter->second.first; - //cout<<"node "<first<<" port "<< iter->second.first<0); - distance+=router_list[1][prev[neighbor]][neighbor].second;//REVERSE lat - neighbor= prev[neighbor]; - } - distance+=router_list[1][prev[neighbor]][neighbor].second;//lat - - assert( router_list[1][r_start].count(neighbor)!=0); - int port = router_list[1][r_start][neighbor].first; - for(map >::iterator iter = router_list[0][i].begin(); - iter!=router_list[0][i].end(); - iter++){ - routing_table[r_start][iter->first]=port; - //cout<<"node "<first<<" port "<< port<<" dist "< >(); - } - if(router_list[ROUTER].count(head_id) == 0){ - router_list[ROUTER][head_id] = map >(); - } - - state=BODY_TYPE; - break; - case LINK_WEIGHT: - if(temp=="router"|| - temp == "node"){ - //ignore - } else { - link_weight= atoi(temp.c_str()); - router_list[head_type][head_id][body_id].second=link_weight; - break; - } - //intentionally letting it flow through - case BODY_TYPE: - if(temp=="router"){ - body_type = ROUTER; - } else if (temp == "node"){ - body_type = NODE; - } else { - cout<<"Anynet:Unknow body type "< >(); - } - if(router_list[ROUTER].count(body_id) == 0){ - router_list[ROUTER][body_id] = map >(); - } - } - - if(head_type==NODE && body_type==NODE){ - - cout<<"Anynet:Cannot connect node to node "<(-1,1); - - } else if(head_type==ROUTER && body_type==NODE){ - //insert and check node - if(node_list.count(body_id) != 0 && - node_list[body_id]!=head_id){ - cout<<"Anynet:Node "<(-1,1); - - } else if(head_type==ROUTER && body_type==ROUTER){ - router_list[ROUTER][head_id][body_id]=pair(-1,1); - if(router_list[ROUTER][body_id].count(head_id)==0){ - router_list[ROUTER][body_id][head_id]=pair(-1,1); - } - } - state=LINK_WEIGHT; - break ; - default: - cout<<"Anynet:Unknow parse state\n"; - assert(false); - break; - } - - } while(pos!=0); - if(state!=LINK_WEIGHT && - state!=BODY_TYPE){ - cout<<"Anynet:Incomplete parse of the line: "< node_check; - for(map::iterator i = node_list.begin(); - i!=node_list.end(); - i++){ - node_check.push_back(i->first); - } - sort(node_check.begin(), node_check.end()); - for(size_t i = 0; i -using namespace std ; - -MatrixArbiter::MatrixArbiter( Module *parent, const string &name, int size ) - : Arbiter( parent, name, size ), _last_req(-1) { - _matrix.resize(size); - for ( int i = 0 ; i < size ; i++ ) { - _matrix[i].resize(size); - for ( int j = 0; j < i; j++ ) { - _matrix[i][j] = 1; - } - } -} - -void MatrixArbiter::PrintState() const { - cout << "Priority Matrix: " << endl ; - for ( int r = 0; r < _size ; r++ ) { - for ( int c = 0 ; c < _size ; c++ ) { - cout << _matrix[r][c] << " " ; - } - cout << endl ; - } - cout << endl ; -} - -void MatrixArbiter::UpdateState() { - // update priority matrix using last grant - if ( _selected > -1 ) { - for ( int i = 0; i < _size ; i++ ) { - if( _selected != i ) { - _matrix[_selected][i] = 0 ; - _matrix[i][_selected] = 1 ; - } - } - } -} - -void MatrixArbiter::AddRequest( int input, int id, int pri ) -{ - _last_req = input; - Arbiter::AddRequest(input, id, pri); -} - -int MatrixArbiter::Arbitrate( int* id, int* pri ) { - - // avoid running arbiter if it has not recevied at least two requests - // (in this case, requests and grants are identical) - if ( _num_reqs < 2 ) { - - _selected = _last_req ; - - } else { - - _selected = -1 ; - - for ( int input = 0 ; input < _size ; input++ ) { - if(_request[input].valid) { - - bool grant = true; - for ( int i = 0 ; i < _size ; i++ ) { - if ( _request[i].valid && - ( ( ( _request[i].pri == _request[input].pri ) && - _matrix[i][input]) || - ( _request[i].pri > _request[input].pri ) - ) ) { - grant = false ; - break ; - } - } - - if ( grant ) { - _selected = input ; - break ; - } - } - - } - } - - return Arbiter::Arbitrate(id, pri); -} - -void MatrixArbiter::Clear() -{ - _last_req = -1; - Arbiter::Clear(); -} diff --git a/src/intersim2/.svn/pristine/33/337f567cc4b77aad754f713a5fd363118f925249.svn-base b/src/intersim2/.svn/pristine/33/337f567cc4b77aad754f713a5fd363118f925249.svn-base deleted file mode 100644 index f9e7801..0000000 --- a/src/intersim2/.svn/pristine/33/337f567cc4b77aad754f713a5fd363118f925249.svn-base +++ /dev/null @@ -1,52 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "booksim.hpp" -#include "misc_utils.hpp" - -int powi( int x, int y ) // compute x to the y -{ - int r = 1; - - for ( int i = 0; i < y; ++i ) { - r *= x; - } - - return r; -} - -int log_two( int x ) -{ - int r = 0; - - x >>= 1; - while( x ) { - r++; x >>= 1; - } - - return r; -} diff --git a/src/intersim2/.svn/pristine/38/38bf48ff0300a37f3005867f74e32b80297f8b09.svn-base b/src/intersim2/.svn/pristine/38/38bf48ff0300a37f3005867f74e32b80297f8b09.svn-base deleted file mode 100644 index d8db065..0000000 --- a/src/intersim2/.svn/pristine/38/38bf48ff0300a37f3005867f74e32b80297f8b09.svn-base +++ /dev/null @@ -1,75 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _BATCHTRAFFICMANAGER_HPP_ -#define _BATCHTRAFFICMANAGER_HPP_ - -#include - -#include "config_utils.hpp" -#include "stats.hpp" -#include "trafficmanager.hpp" - -class BatchTrafficManager : public TrafficManager { - -protected: - - int _max_outstanding; - int _batch_size; - int _batch_count; - int _last_id; - int _last_pid; - - Stats * _batch_time; - double _overall_min_batch_time; - double _overall_avg_batch_time; - double _overall_max_batch_time; - - ostream * _sent_packets_out; - - virtual void _RetireFlit( Flit *f, int dest ); - - virtual int _IssuePacket( int source, int cl ); - virtual void _ClearStats( ); - virtual bool _SingleSim( ); - - virtual void _UpdateOverallStats( ); - - virtual string _OverallStatsCSV(int c = 0) const; - -public: - - BatchTrafficManager( const Configuration &config, const vector & net ); - virtual ~BatchTrafficManager( ); - - virtual void WriteStats( ostream & os = cout ) const; - virtual void DisplayStats( ostream & os = cout ) const; - virtual void DisplayOverallStats( ostream & os = cout ) const; - -}; - -#endif diff --git a/src/intersim2/.svn/pristine/39/398668283dbbef318596ac5cdfdb72a53973f2d1.svn-base b/src/intersim2/.svn/pristine/39/398668283dbbef318596ac5cdfdb72a53973f2d1.svn-base deleted file mode 100644 index 1abff33..0000000 --- a/src/intersim2/.svn/pristine/39/398668283dbbef318596ac5cdfdb72a53973f2d1.svn-base +++ /dev/null @@ -1,161 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _BUFFER_HPP_ -#define _BUFFER_HPP_ - -#include - -#include "vc.hpp" -#include "flit.hpp" -#include "outputset.hpp" -#include "routefunc.hpp" -#include "config_utils.hpp" - -class Buffer : public Module { - - int _occupancy; - int _size; - - vector _vc; - -#ifdef TRACK_BUFFERS - vector _class_occupancy; -#endif - -public: - - Buffer( const Configuration& config, int outputs, - Module *parent, const string& name ); - ~Buffer(); - - void AddFlit( int vc, Flit *f ); - - inline Flit *RemoveFlit( int vc ) - { - --_occupancy; -#ifdef TRACK_BUFFERS - int cl = _vc[vc]->FrontFlit()->cl; - assert(_class_occupancy[cl] > 0); - --_class_occupancy[cl]; -#endif - return _vc[vc]->RemoveFlit( ); - } - - inline Flit *FrontFlit( int vc ) const - { - return _vc[vc]->FrontFlit( ); - } - - inline bool Empty( int vc ) const - { - return _vc[vc]->Empty( ); - } - - inline bool Full( ) const - { - return _occupancy >= _size; - } - - inline VC::eVCState GetState( int vc ) const - { - return _vc[vc]->GetState( ); - } - - inline void SetState( int vc, VC::eVCState s ) - { - _vc[vc]->SetState(s); - } - - inline const OutputSet *GetRouteSet( int vc ) const - { - return _vc[vc]->GetRouteSet( ); - } - - inline void SetRouteSet( int vc, OutputSet * output_set ) - { - _vc[vc]->SetRouteSet(output_set); - } - - inline void SetOutput( int vc, int out_port, int out_vc ) - { - _vc[vc]->SetOutput(out_port, out_vc); - } - - inline int GetOutputPort( int vc ) const - { - return _vc[vc]->GetOutputPort( ); - } - - inline int GetOutputVC( int vc ) const - { - return _vc[vc]->GetOutputVC( ); - } - - inline int GetPriority( int vc ) const - { - return _vc[vc]->GetPriority( ); - } - - inline void Route( int vc, tRoutingFunction rf, const Router* router, const Flit* f, int in_channel ) - { - _vc[vc]->Route(rf, router, f, in_channel); - } - - // ==== Debug functions ==== - - inline void SetWatch( int vc, bool watch = true ) - { - _vc[vc]->SetWatch(watch); - } - - inline bool IsWatched( int vc ) const - { - return _vc[vc]->IsWatched( ); - } - - inline int GetOccupancy( ) const - { - return _occupancy; - } - - inline int GetOccupancy( int vc ) const - { - return _vc[vc]->GetOccupancy( ); - } - -#ifdef TRACK_BUFFERS - inline int GetOccupancyForClass(int c) const - { - return _class_occupancy[c]; - } -#endif - - void Display( ostream & os = cout ) const; -}; - -#endif diff --git a/src/intersim2/.svn/pristine/3a/3a771e1b366aae7e427d29b3f55d7f51045173d5.svn-base b/src/intersim2/.svn/pristine/3a/3a771e1b366aae7e427d29b3f55d7f51045173d5.svn-base deleted file mode 100644 index 6c15d25..0000000 --- a/src/intersim2/.svn/pristine/3a/3a771e1b366aae7e427d29b3f55d7f51045173d5.svn-base +++ /dev/null @@ -1,71 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// ---------------------------------------------------------------------- -// -// TreeArbiter -// -// ---------------------------------------------------------------------- - -#ifndef _TREE_ARB_HPP_ -#define _TREE_ARB_HPP_ - -#include "arbiter.hpp" - -class TreeArbiter : public Arbiter { - - int _group_size ; - - vector _group_arbiters; - Arbiter * _global_arbiter; - - vector _group_reqs; - -public: - - // Constructors - TreeArbiter( Module *parent, const string &name, int size, int groups, const string & arb_type ) ; - - ~TreeArbiter(); - - // Print priority matrix to standard output - virtual void PrintState() const ; - - // Update priority matrix based on last aribtration result - virtual void UpdateState() ; - - // Arbitrate amongst requests. Returns winning input and - // updates pointers to metadata when valid pointers are passed - virtual int Arbitrate( int* id = 0, int* pri = 0) ; - - virtual void AddRequest( int input, int id, int pri ) ; - - virtual void Clear(); - -} ; - -#endif diff --git a/src/intersim2/.svn/pristine/3b/3bdd451bbcde75941cf7ad8caf63c4465c856102.svn-base b/src/intersim2/.svn/pristine/3b/3bdd451bbcde75941cf7ad8caf63c4465c856102.svn-base deleted file mode 100644 index e587a7f..0000000 --- a/src/intersim2/.svn/pristine/3b/3bdd451bbcde75941cf7ad8caf63c4465c856102.svn-base +++ /dev/null @@ -1,187 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/*main.cpp - * - *The starting point of the network simulator - *-Include all network header files - *-initilize the network - *-initialize the traffic manager and set it to run - * - * - */ -#include - -#include -#include -#include -#include - - - -#include -#include "booksim.hpp" -#include "routefunc.hpp" -#include "traffic.hpp" -#include "booksim_config.hpp" -#include "trafficmanager.hpp" -#include "random_utils.hpp" -#include "network.hpp" -#include "injection.hpp" -#include "power_module.hpp" - - - -/////////////////////////////////////////////////////////////////////////////// -//Global declarations -////////////////////// - - /* the current traffic manager instance */ -TrafficManager * trafficManager = NULL; - -int GetSimTime() { - return trafficManager->getTime(); -} - -class Stats; -Stats * GetStats(const std::string & name) { - Stats* test = trafficManager->getStats(name); - if(test == 0){ - cout<<"warning statistics "< net; - - int subnets = config.GetInt("subnets"); - /*To include a new network, must register the network here - *add an else if statement with the name of the network - */ - net.resize(subnets); - for (int i = 0; i < subnets; ++i) { - ostringstream name; - name << "network_" << i; - net[i] = Network::New( config, name.str() ); - } - - /*tcc and characterize are legacy - *not sure how to use them - */ - - assert(trafficManager == NULL); - trafficManager = TrafficManager::New( config, net ) ; - - /*Start the simulation run - */ - - double total_time; /* Amount of time we've run */ - struct timeval start_time, end_time; /* Time before/after user code */ - total_time = 0.0; - gettimeofday(&start_time, NULL); - - bool result = trafficManager->Run() ; - - - gettimeofday(&end_time, NULL); - total_time = ((double)(end_time.tv_sec) + (double)(end_time.tv_usec)/1000000.0) - - ((double)(start_time.tv_sec) + (double)(start_time.tv_usec)/1000000.0); - - cout<<"Total run time "< 0){ - Power_Module pnet(net[i], config); - pnet.run(); - } - - delete net[i]; - } - - delete trafficManager; - trafficManager = NULL; - - return result; -} - - -int main( int argc, char **argv ) -{ - - BookSimConfig config; - - - if ( !ParseArgs( &config, argc, argv ) ) { - cerr << "Usage: " << argv[0] << " configfile... [param=value...]" << endl; - return 0; - } - - - /*initialize routing, traffic, injection functions - */ - InitializeRoutingMap( config ); - - gPrintActivity = (config.GetInt("print_activity") > 0); - gTrace = (config.GetInt("viewer_trace") > 0); - - string watch_out_file = config.GetStr( "watch_out" ); - if(watch_out_file == "") { - gWatchOut = NULL; - } else if(watch_out_file == "-") { - gWatchOut = &cout; - } else { - gWatchOut = new ofstream(watch_out_file.c_str()); - } - - - /*configure and run the simulator - */ - bool result = Simulate( config ); - return result ? -1 : 0; -} diff --git a/src/intersim2/.svn/pristine/3b/3bebc9fde5e475aaa53b6d4abda241d37117421b.svn-base b/src/intersim2/.svn/pristine/3b/3bebc9fde5e475aaa53b6d4abda241d37117421b.svn-base deleted file mode 100644 index 2e20502..0000000 --- a/src/intersim2/.svn/pristine/3b/3bebc9fde5e475aaa53b6d4abda241d37117421b.svn-base +++ /dev/null @@ -1,67 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "switch_monitor.hpp" - -#include "flit.hpp" - -SwitchMonitor::SwitchMonitor( int inputs, int outputs, int classes ) -: _cycles(0), _inputs(inputs), _outputs(outputs), _classes(classes) { - _event.resize(inputs * outputs * classes, 0) ; -} - -int SwitchMonitor::index( int input, int output, int cl ) const { - assert((input >= 0) && (input < _inputs)); - assert((output >= 0) && (output < _outputs)); - assert((cl >= 0) && (cl < _classes)); - return cl + _classes * ( output + _outputs * input ) ; -} - -void SwitchMonitor::cycle() { - _cycles++ ; -} - -void SwitchMonitor::traversal( int input, int output, Flit const * f ) { - _event[ index( input, output, f->cl) ]++ ; -} - -void SwitchMonitor::display(ostream & os) const { - for ( int i = 0 ; i < _inputs ; i++ ) { - for ( int o = 0 ; o < _outputs ; o++) { - os << "[" << i << " -> " << o << "] " ; - for ( int c = 0 ; c < _classes ; c++ ) { - os << c << ":" << _event[index(i,o,c)] << " " ; - } - os << endl ; - } - } -} - -ostream & operator<<( ostream & os, SwitchMonitor const & obj ) { - obj.display(os); - return os ; -} diff --git a/src/intersim2/.svn/pristine/3c/3c57b304902a442e45bf4e4225aac564cd2bdc26.svn-base b/src/intersim2/.svn/pristine/3c/3c57b304902a442e45bf4e4225aac564cd2bdc26.svn-base deleted file mode 100644 index 37133f0..0000000 --- a/src/intersim2/.svn/pristine/3c/3c57b304902a442e45bf4e4225aac564cd2bdc26.svn-base +++ /dev/null @@ -1,62 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _MODULE_HPP_ -#define _MODULE_HPP_ - -#include "booksim.hpp" - -#include -#include -#include - -class Module { -private: - string _name; - string _fullname; - - vector _children; - -protected: - void _AddChild( Module *child ); - -public: - Module( Module *parent, const string& name ); - virtual ~Module( ) { } - - inline const string & Name() const { return _name; } - inline const string & FullName() const { return _fullname; } - - void DisplayHierarchy( int level = 0, ostream & os = cout ) const; - - void Error( const string& msg ) const; - void Debug( const string& msg ) const; - - virtual void Display( ostream & os = cout ) const; -}; - -#endif diff --git a/src/intersim2/.svn/pristine/3c/3c8671257ad287c8e877c0942bdc9f16e9f7fe0c.svn-base b/src/intersim2/.svn/pristine/3c/3c8671257ad287c8e877c0942bdc9f16e9f7fe0c.svn-base deleted file mode 100644 index 2084eec..0000000 --- a/src/intersim2/.svn/pristine/3c/3c8671257ad287c8e877c0942bdc9f16e9f7fe0c.svn-base +++ /dev/null @@ -1,162 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "booksim.hpp" -#include -#include - -#include "fly.hpp" -#include "misc_utils.hpp" - -//#define DEBUG_FLY - -KNFly::KNFly( const Configuration &config, const string & name ) : -Network( config, name ) -{ - _ComputeSize( config ); - _Alloc( ); - _BuildNet( config ); -} - -void KNFly::_ComputeSize( const Configuration &config ) -{ - _k = config.GetInt( "k" ); - _n = config.GetInt( "n" ); - - gK = _k; gN = _n; - - _nodes = powi( _k, _n ); - - // n stages of k^(n-1) k x k switches - _size = _n*powi( _k, _n-1 ); - - // n-1 sets of wiring between the stages - _channels = (_n-1)*_nodes; -} - -void KNFly::_BuildNet( const Configuration &config ) -{ - ostringstream router_name; - - int per_stage = powi( _k, _n-1 ); - - int node = 0; - int c; - - for ( int stage = 0; stage < _n; ++stage ) { - for ( int addr = 0; addr < per_stage; ++addr ) { - - router_name << "router_" << stage << "_" << addr; - _routers[node] = Router::NewRouter( config, this, router_name.str( ), - node, _k, _k ); - _timed_modules.push_back(_routers[node]); - router_name.str(""); - -#ifdef DEBUG_FLY - cout << "connecting node " << node << " to:" << endl; -#endif - - for ( int port = 0; port < _k; ++port ) { - // Input connections - if ( stage == 0 ) { - c = addr*_k + port; - _routers[node]->AddInputChannel( _inject[c], _inject_cred[c] ); -#ifdef DEBUG_FLY - cout << " injection channel " << c << endl; -#endif - } else { - c = _InChannel( stage, addr, port ); - _routers[node]->AddInputChannel( _chan[c], _chan_cred[c] ); - _chan[c]->SetLatency( 1 ); - -#ifdef DEBUG_FLY - cout << " input channel " << c << endl; -#endif - } - - // Output connections - if ( stage == _n - 1 ) { - c = addr*_k + port; - _routers[node]->AddOutputChannel( _eject[c], _eject_cred[c] ); -#ifdef DEBUG_FLY - cout << " ejection channel " << c << endl; -#endif - } else { - c = _OutChannel( stage, addr, port ); - _routers[node]->AddOutputChannel( _chan[c], _chan_cred[c] ); -#ifdef DEBUG_FLY - cout << " output channel " << c << endl; -#endif - } - } - - ++node; - } - } -} - -int KNFly::_OutChannel( int stage, int addr, int port ) const -{ - return stage*_nodes + addr*_k + port; -} - -int KNFly::_InChannel( int stage, int addr, int port ) const -{ - int in_addr; - int in_port; - - // Channels are between {node,port} - // { d_{n-1} ... d_{n-stage} ... d_0 } and - // { d_{n-1} ... d_0 ... d_{n-stage} } - - int shift = powi( _k, _n-stage-1 ); - - int last_digit = port; - int zero_digit = ( addr / shift ) % _k; - - // swap zero and last digit to get first node's address - in_addr = addr - zero_digit*shift + last_digit*shift; - in_port = zero_digit; - - return (stage-1)*_nodes + in_addr*_k + in_port; -} - -int KNFly::GetN( ) const -{ - return _n; -} - -int KNFly::GetK( ) const -{ - return _k; -} - -double KNFly::Capacity( ) const -{ - return 1.0; -} - diff --git a/src/intersim2/.svn/pristine/3f/3f4cacd217f3c1d154a11537511bf6b6e96a8e6b.svn-base b/src/intersim2/.svn/pristine/3f/3f4cacd217f3c1d154a11537511bf6b6e96a8e6b.svn-base deleted file mode 100644 index 43876dc..0000000 --- a/src/intersim2/.svn/pristine/3f/3f4cacd217f3c1d154a11537511bf6b6e96a8e6b.svn-base +++ /dev/null @@ -1,76 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _STATS_HPP_ -#define _STATS_HPP_ - -#include "module.hpp" - -class Stats : public Module { - int _num_samples; - double _sample_sum; - double _sample_squared_sum; - - //bool _reset; - double _min; - double _max; - - int _num_bins; - double _bin_size; - - vector _hist; - -public: - Stats( Module *parent, const string &name, - double bin_size = 1.0, int num_bins = 10 ); - - void Clear( ); - - double Average( ) const; - double Variance( ) const; - double Max( ) const; - double Min( ) const; - double Sum( ) const; - double SquaredSum( ) const; - int NumSamples( ) const; - - void AddSample( double val ); - inline void AddSample( int val ) { - AddSample( (double)val ); - } - - int GetBin(int b){ return _hist[b];} - - void Display( ostream & os = cout ) const; - - friend ostream & operator<<(ostream & os, const Stats & s); - -}; - -ostream & operator<<(ostream & os, const Stats & s); - -#endif diff --git a/src/intersim2/.svn/pristine/42/42777bd5ccda83625dfbf29e7aec13f2e773373a.svn-base b/src/intersim2/.svn/pristine/42/42777bd5ccda83625dfbf29e7aec13f2e773373a.svn-base deleted file mode 100644 index 6260406..0000000 --- a/src/intersim2/.svn/pristine/42/42777bd5ccda83625dfbf29e7aec13f2e773373a.svn-base +++ /dev/null @@ -1,1999 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/*routefunc.cpp - * - *This is where most of the routing functions reside. Some of the topologies - *has their own "register routing functions" which must be called to access - *those routing functions. - * - *After writing a routing function, don't forget to register it. The reg - *format is rfname_topologyname. - * - */ - -#include -#include -#include - -#include "booksim.hpp" -#include "routefunc.hpp" -#include "kncube.hpp" -#include "random_utils.hpp" -#include "misc_utils.hpp" -#include "fattree.hpp" -#include "tree4.hpp" -#include "qtree.hpp" -#include "cmesh.hpp" - - - -map gRoutingFunctionMap; - -/* Global information used by routing functions */ - -int gNumVCs; - -/* Add more functions here - * - */ - -// ============================================================ -// Balfour-Schultz -int gReadReqBeginVC, gReadReqEndVC; -int gWriteReqBeginVC, gWriteReqEndVC; -int gReadReplyBeginVC, gReadReplyEndVC; -int gWriteReplyBeginVC, gWriteReplyEndVC; - -// ============================================================ -// QTree: Nearest Common Ancestor -// === -void qtree_nca( const Router *r, const Flit *f, - int in_channel, OutputSet* outputs, bool inject) -{ - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - int height = QTree::HeightFromID( r->GetID() ); - int pos = QTree::PosFromID( r->GetID() ); - - int dest = f->dest; - - for (int i = height+1; i < gN; i++) - dest /= gK; - if ( pos == dest / gK ) - // Route down to child - out_port = dest % gK ; - else - // Route up to parent - out_port = gK; - - } - - outputs->Clear( ); - - outputs->AddRange( out_port, vcBegin, vcEnd ); -} - -// ============================================================ -// Tree4: Nearest Common Ancestor w/ Adaptive Routing Up -// === -void tree4_anca( const Router *r, const Flit *f, - int in_channel, OutputSet* outputs, bool inject) -{ - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int range = 1; - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - int dest = f->dest; - - const int NPOS = 16; - - int rH = r->GetID( ) / NPOS; - int rP = r->GetID( ) % NPOS; - - if ( rH == 0 ) { - dest /= 16; - out_port = 2 * dest + RandomInt(1); - } else if ( rH == 1 ) { - dest /= 4; - if ( dest / 4 == rP / 2 ) - out_port = dest % 4; - else { - out_port = gK; - range = gK; - } - } else { - if ( dest/4 == rP ) - out_port = dest % 4; - else { - out_port = gK; - range = 2; - } - } - - // cout << "Router("< dest ) ) || - ( ( dir == 1 ) && ( cur < dest ) ) ) { - *partition = 1; - } else if ( ( ( dir == 0 ) && ( cur <= (gK-1)/2 ) && ( dest > (gK-1)/2 ) ) || - ( ( dir == 1 ) && ( cur > (gK-1)/2 ) && ( dest <= (gK-1)/2 ) ) ) { - *partition = 0; - } else { - *partition = RandomInt( 1 ); // use either VC set - } - } else { - // Deterministic, fixed dateline between nodes k-1 and 0 - - if ( ( ( dir == 0 ) && ( cur > dest ) ) || - ( ( dir == 1 ) && ( dest < cur ) ) ) { - *partition = 1; - } else { - *partition = 0; - } - } - } - } else { - // Inverting the least significant bit keeps - // the packet moving in the same direction - *out_port = in_port ^ 0x1; - } - - } else { - *out_port = 2*gN; // Eject - } -} - -//============================================================= - -void dim_order_mesh( const Router *r, const Flit *f, int in_channel, OutputSet *outputs, bool inject ) -{ - int out_port = inject ? -1 : dor_next_mesh( r->GetID( ), f->dest ); - - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - if ( !inject && f->watch ) { - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << "Adding VC range [" - << vcBegin << "," - << vcEnd << "]" - << " at output port " << out_port - << " for flit " << f->id - << " (input port " << in_channel - << ", destination " << f->dest << ")" - << "." << endl; - } - - outputs->Clear(); - - outputs->AddRange( out_port, vcBegin, vcEnd ); -} - -//============================================================= - -void dim_order_ni_mesh( const Router *r, const Flit *f, int in_channel, OutputSet *outputs, bool inject ) -{ - int out_port = inject ? -1 : dor_next_mesh( r->GetID( ), f->dest ); - - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - // at the destination router, we don't need to separate VCs by destination - if(inject || (r->GetID() != f->dest)) { - - int const vcs_per_dest = (vcEnd - vcBegin + 1) / gNodes; - assert(vcs_per_dest > 0); - - vcBegin += f->dest * vcs_per_dest; - vcEnd = vcBegin + vcs_per_dest - 1; - - } - - if( !inject && f->watch ) { - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << "Adding VC range [" - << vcBegin << "," - << vcEnd << "]" - << " at output port " << out_port - << " for flit " << f->id - << " (input port " << in_channel - << ", destination " << f->dest << ")" - << "." << endl; - } - - outputs->Clear( ); - - outputs->AddRange( out_port, vcBegin, vcEnd ); -} - -//============================================================= - -void dim_order_pni_mesh( const Router *r, const Flit *f, int in_channel, OutputSet *outputs, bool inject ) -{ - int out_port = inject ? -1 : dor_next_mesh( r->GetID(), f->dest ); - - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - if(inject || (r->GetID() != f->dest)) { - int next_coord = f->dest; - if(!inject) { - int out_dim = out_port / 2; - for(int d = 0; d < out_dim; ++d) { - next_coord /= gK; - } - } - next_coord %= gK; - assert(next_coord >= 0 && next_coord < gK); - int vcs_per_dest = (vcEnd - vcBegin + 1) / gK; - assert(vcs_per_dest > 0); - vcBegin += next_coord * vcs_per_dest; - vcEnd = vcBegin + vcs_per_dest - 1; - } - - if( !inject && f->watch ) { - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << "Adding VC range [" - << vcBegin << "," - << vcEnd << "]" - << " at output port " << out_port - << " for flit " << f->id - << " (input port " << in_channel - << ", destination " << f->dest << ")" - << "." << endl; - } - - outputs->Clear( ); - - outputs->AddRange( out_port, vcBegin, vcEnd ); -} - -//============================================================= - -// Random intermediate in the minimal quadrant defined -// by the source and destination -int rand_min_intr_mesh( int src, int dest ) -{ - int dist; - - int intm = 0; - int offset = 1; - - for ( int n = 0; n < gN; ++n ) { - dist = ( dest % gK ) - ( src % gK ); - - if ( dist > 0 ) { - intm += offset * ( ( src % gK ) + RandomInt( dist ) ); - } else { - intm += offset * ( ( dest % gK ) + RandomInt( -dist ) ); - } - - offset *= gK; - dest /= gK; src /= gK; - } - - return intm; -} - -//============================================================= - -void romm_mesh( const Router *r, const Flit *f, int in_channel, OutputSet *outputs, bool inject ) -{ - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - if ( in_channel == 2*gN ) { - f->ph = 0; // Phase 0 - f->intm = rand_min_intr_mesh( f->src, f->dest ); - } - - if ( ( f->ph == 0 ) && ( r->GetID( ) == f->intm ) ) { - f->ph = 1; // Go to phase 1 - } - - out_port = dor_next_mesh( r->GetID( ), (f->ph == 0) ? f->intm : f->dest ); - - // at the destination router, we don't need to separate VCs by phase - if(r->GetID() != f->dest) { - - //each class must have at least 2 vcs assigned or else valiant valiant will deadlock - int available_vcs = (vcEnd - vcBegin + 1) / 2; - assert(available_vcs > 0); - - if(f->ph == 0) { - vcEnd -= available_vcs; - } else { - assert(f->ph == 1); - vcBegin += available_vcs; - } - } - - } - - outputs->Clear( ); - - outputs->AddRange( out_port, vcBegin, vcEnd ); -} - -//============================================================= - -void romm_ni_mesh( const Router *r, const Flit *f, int in_channel, OutputSet *outputs, bool inject ) -{ - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - // at the destination router, we don't need to separate VCs by destination - if(inject || (r->GetID() != f->dest)) { - - int const vcs_per_dest = (vcEnd - vcBegin + 1) / gNodes; - assert(vcs_per_dest > 0); - - vcBegin += f->dest * vcs_per_dest; - vcEnd = vcBegin + vcs_per_dest - 1; - - } - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - if ( in_channel == 2*gN ) { - f->ph = 0; // Phase 0 - f->intm = rand_min_intr_mesh( f->src, f->dest ); - } - - if ( ( f->ph == 0 ) && ( r->GetID( ) == f->intm ) ) { - f->ph = 1; // Go to phase 1 - } - - out_port = dor_next_mesh( r->GetID( ), (f->ph == 0) ? f->intm : f->dest ); - - } - - outputs->Clear( ); - - outputs->AddRange( out_port, vcBegin, vcEnd ); -} - -//============================================================= - -void min_adapt_mesh( const Router *r, const Flit *f, int in_channel, OutputSet *outputs, bool inject ) -{ - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - outputs->Clear( ); - - if(inject) { - // injection can use all VCs - outputs->AddRange(-1, vcBegin, vcEnd); - return; - } else if(r->GetID() == f->dest) { - // ejection can also use all VCs - outputs->AddRange(2*gN, vcBegin, vcEnd); - return; - } - - int in_vc; - - if ( in_channel == 2*gN ) { - in_vc = vcEnd; // ignore the injection VC - } else { - in_vc = f->vc; - } - - // DOR for the escape channel (VC 0), low priority - int out_port = dor_next_mesh( r->GetID( ), f->dest ); - outputs->AddRange( out_port, 0, vcBegin, vcBegin ); - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << "Adding VC range [" - << vcBegin << "," - << vcBegin << "]" - << " at output port " << out_port - << " for flit " << f->id - << " (input port " << in_channel - << ", destination " << f->dest << ")" - << "." << endl; - } - - if ( in_vc != vcBegin ) { // If not in the escape VC - // Minimal adaptive for all other channels - int cur = r->GetID( ); - int dest = f->dest; - - for ( int n = 0; n < gN; ++n ) { - if ( ( cur % gK ) != ( dest % gK ) ) { - // Add minimal direction in dimension 'n' - if ( ( cur % gK ) < ( dest % gK ) ) { // Right - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << "Adding VC range [" - << (vcBegin+1) << "," - << vcEnd << "]" - << " at output port " << 2*n - << " with priority " << 1 - << " for flit " << f->id - << " (input port " << in_channel - << ", destination " << f->dest << ")" - << "." << endl; - } - outputs->AddRange( 2*n, vcBegin+1, vcEnd, 1 ); - } else { // Left - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << "Adding VC range [" - << (vcBegin+1) << "," - << vcEnd << "]" - << " at output port " << 2*n+1 - << " with priority " << 1 - << " for flit " << f->id - << " (input port " << in_channel - << ", destination " << f->dest << ")" - << "." << endl; - } - outputs->AddRange( 2*n + 1, vcBegin+1, vcEnd, 1 ); - } - } - cur /= gK; - dest /= gK; - } - } -} - -//============================================================= - -void planar_adapt_mesh( const Router *r, const Flit *f, int in_channel, OutputSet *outputs, bool inject ) -{ - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - outputs->Clear( ); - - if(inject) { - // injection can use all VCs - outputs->AddRange(-1, vcBegin, vcEnd); - return; - } - - int cur = r->GetID( ); - int dest = f->dest; - - if ( cur != dest ) { - - int in_vc = f->vc; - int vc_mult = (vcEnd - vcBegin + 1) / 3; - - // Find the first unmatched dimension -- except - // for when we're in the first dimension because - // of misrouting in the last adaptive plane. - // In this case, go to the last dimension instead. - - int n; - for ( n = 0; n < gN; ++n ) { - if ( ( ( cur % gK ) != ( dest % gK ) ) && - !( ( in_channel/2 == 0 ) && - ( n == 0 ) && - ( in_vc < vcBegin+2*vc_mult ) ) ) { - break; - } - - cur /= gK; - dest /= gK; - } - - assert( n < gN ); - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << "PLANAR ADAPTIVE: flit " << f->id - << " in adaptive plane " << n << "." << endl; - } - - // We're in adaptive plane n - - // Can route productively in d_{i,2} - bool increase; - bool fault; - if ( ( cur % gK ) < ( dest % gK ) ) { // Increasing - increase = true; - if ( !r->IsFaultyOutput( 2*n ) ) { - outputs->AddRange( 2*n, vcBegin+2*vc_mult, vcEnd ); - fault = false; - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << "PLANAR ADAPTIVE: increasing in dimension " << n - << "." << endl; - } - } else { - fault = true; - } - } else { // Decreasing - increase = false; - if ( !r->IsFaultyOutput( 2*n + 1 ) ) { - outputs->AddRange( 2*n + 1, vcBegin+2*vc_mult, vcEnd ); - fault = false; - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << "PLANAR ADAPTIVE: decreasing in dimension " << n - << "." << endl; - } - } else { - fault = true; - } - } - - n = ( n + 1 ) % gN; - cur /= gK; - dest /= gK; - - if ( !increase ) { - vcBegin += vc_mult; - } - vcEnd = vcBegin + vc_mult - 1; - - int d1_min_c; - if ( ( cur % gK ) < ( dest % gK ) ) { // Increasing in d_{i+1} - d1_min_c = 2*n; - } else if ( ( cur % gK ) != ( dest % gK ) ) { // Decreasing in d_{i+1} - d1_min_c = 2*n + 1; - } else { - d1_min_c = -1; - } - - // do we want to 180? if so, the last - // route was a misroute in this dimension, - // if there is no fault in d_i, just ignore - // this dimension, otherwise continue to misroute - if ( d1_min_c == in_channel ) { - if ( fault ) { - d1_min_c = in_channel ^ 1; - } else { - d1_min_c = -1; - } - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << "PLANAR ADAPTIVE: avoiding 180 in dimension " << n - << "." << endl; - } - } - - if ( d1_min_c != -1 ) { - if ( !r->IsFaultyOutput( d1_min_c ) ) { - outputs->AddRange( d1_min_c, vcBegin, vcEnd ); - } else if ( fault ) { - // major problem ... fault in d_i and d_{i+1} - r->Error( "There seem to be faults in d_i and d_{i+1}" ); - } - } else if ( fault ) { // need to misroute! - bool atedge; - if ( cur % gK == 0 ) { - d1_min_c = 2*n; - atedge = true; - } else if ( cur % gK == gK - 1 ) { - d1_min_c = 2*n + 1; - atedge = true; - } else { - d1_min_c = 2*n + RandomInt( 1 ); // random misroute - - if ( d1_min_c == in_channel ) { // don't 180 - d1_min_c = in_channel ^ 1; - } - atedge = false; - } - - if ( !r->IsFaultyOutput( d1_min_c ) ) { - outputs->AddRange( d1_min_c, vcBegin, vcEnd ); - } else if ( !atedge && !r->IsFaultyOutput( d1_min_c ^ 1 ) ) { - outputs->AddRange( d1_min_c ^ 1, vcBegin, vcEnd ); - } else { - // major problem ... fault in d_i and d_{i+1} - r->Error( "There seem to be faults in d_i and d_{i+1}" ); - } - } - } else { - outputs->AddRange( 2*gN, vcBegin, vcEnd ); - } -} - -//============================================================= -/* - FIXME: This is broken (note that f->dr is never actually modified). - Even if it were, this should really use f->ph instead of introducing a single- - use field. - -void limited_adapt_mesh( const Router *r, const Flit *f, int in_channel, OutputSet *outputs, bool inject ) -{ - outputs->Clear( ); - - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - if ( inject ) { - outputs->AddRange( -1, vcBegin, vcEnd - 1 ); - f->dr = 0; // zero dimension reversals - return; - } - - int cur = r->GetID( ); - int dest = f->dest; - - if ( cur != dest ) { - if ( ( f->vc != vcEnd ) && - ( f->dr != vcEnd - 1 ) ) { - - for ( int n = 0; n < gN; ++n ) { - if ( ( cur % gK ) != ( dest % gK ) ) { - int min_port; - if ( ( cur % gK ) < ( dest % gK ) ) { - min_port = 2*n; // Right - } else { - min_port = 2*n + 1; // Left - } - - // Go in a productive direction with high priority - outputs->AddRange( min_port, vcBegin, vcEnd - 1, 2 ); - - // Go in the non-productive direction with low priority - outputs->AddRange( min_port ^ 0x1, vcBegin, vcEnd - 1, 1 ); - } else { - // Both directions are non-productive - outputs->AddRange( 2*n, vcBegin, vcEnd - 1, 1 ); - outputs->AddRange( 2*n+1, vcBegin, vcEnd - 1, 1 ); - } - - cur /= gK; - dest /= gK; - } - - } else { - outputs->AddRange( dor_next_mesh( cur, dest ), - vcEnd, vcEnd, 0 ); - } - - } else { // at destination - outputs->AddRange( 2*gN, vcBegin, vcEnd ); - } -} -*/ -//============================================================= - -void valiant_mesh( const Router *r, const Flit *f, int in_channel, OutputSet *outputs, bool inject ) -{ - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - if ( in_channel == 2*gN ) { - f->ph = 0; // Phase 0 - f->intm = RandomInt( gNodes - 1 ); - } - - if ( ( f->ph == 0 ) && ( r->GetID( ) == f->intm ) ) { - f->ph = 1; // Go to phase 1 - } - - out_port = dor_next_mesh( r->GetID( ), (f->ph == 0) ? f->intm : f->dest ); - - // at the destination router, we don't need to separate VCs by phase - if(r->GetID() != f->dest) { - - //each class must have at least 2 vcs assigned or else valiant valiant will deadlock - int const available_vcs = (vcEnd - vcBegin + 1) / 2; - assert(available_vcs > 0); - - if(f->ph == 0) { - vcEnd -= available_vcs; - } else { - assert(f->ph == 1); - vcBegin += available_vcs; - } - } - - } - - outputs->Clear( ); - - outputs->AddRange( out_port, vcBegin, vcEnd ); -} - -//============================================================= - -void valiant_torus( const Router *r, const Flit *f, int in_channel, OutputSet *outputs, bool inject ) -{ - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - int phase; - if ( in_channel == 2*gN ) { - phase = 0; // Phase 0 - f->intm = RandomInt( gNodes - 1 ); - } else { - phase = f->ph / 2; - } - - if ( ( phase == 0 ) && ( r->GetID( ) == f->intm ) ) { - phase = 1; // Go to phase 1 - in_channel = 2*gN; // ensures correct vc selection at the beginning of phase 2 - } - - int ring_part; - dor_next_torus( r->GetID( ), (phase == 0) ? f->intm : f->dest, in_channel, - &out_port, &ring_part, false ); - - f->ph = 2 * phase + ring_part; - - // at the destination router, we don't need to separate VCs by phase, etc. - if(r->GetID() != f->dest) { - - int const ring_available_vcs = (vcEnd - vcBegin + 1) / 2; - assert(ring_available_vcs > 0); - - if(ring_part == 0) { - vcEnd -= ring_available_vcs; - } else { - assert(ring_part == 1); - vcBegin += ring_available_vcs; - } - - int const ph_available_vcs = ring_available_vcs / 2; - assert(ph_available_vcs > 0); - - if(phase == 0) { - vcEnd -= ph_available_vcs; - } else { - assert(phase == 1); - vcBegin += ph_available_vcs; - } - } - - } - - outputs->Clear( ); - - outputs->AddRange( out_port, vcBegin, vcEnd ); -} - -//============================================================= - -void valiant_ni_torus( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - // at the destination router, we don't need to separate VCs by destination - if(inject || (r->GetID() != f->dest)) { - - int const vcs_per_dest = (vcEnd - vcBegin + 1) / gNodes; - assert(vcs_per_dest > 0); - - vcBegin += f->dest * vcs_per_dest; - vcEnd = vcBegin + vcs_per_dest - 1; - - } - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - int phase; - if ( in_channel == 2*gN ) { - phase = 0; // Phase 0 - f->intm = RandomInt( gNodes - 1 ); - } else { - phase = f->ph / 2; - } - - if ( ( f->ph == 0 ) && ( r->GetID( ) == f->intm ) ) { - f->ph = 1; // Go to phase 1 - in_channel = 2*gN; // ensures correct vc selection at the beginning of phase 2 - } - - int ring_part; - dor_next_torus( r->GetID( ), (f->ph == 0) ? f->intm : f->dest, in_channel, - &out_port, &ring_part, false ); - - f->ph = 2 * phase + ring_part; - - // at the destination router, we don't need to separate VCs by phase, etc. - if(r->GetID() != f->dest) { - - int const ring_available_vcs = (vcEnd - vcBegin + 1) / 2; - assert(ring_available_vcs > 0); - - if(ring_part == 0) { - vcEnd -= ring_available_vcs; - } else { - assert(ring_part == 1); - vcBegin += ring_available_vcs; - } - - int const ph_available_vcs = ring_available_vcs / 2; - assert(ph_available_vcs > 0); - - if(phase == 0) { - vcEnd -= ph_available_vcs; - } else { - assert(phase == 1); - vcBegin += ph_available_vcs; - } - } - - if (f->watch) { - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << "Adding VC range [" - << vcBegin << "," - << vcEnd << "]" - << " at output port " << out_port - << " for flit " << f->id - << " (input port " << in_channel - << ", destination " << f->dest << ")" - << "." << endl; - } - - } - - outputs->Clear( ); - - outputs->AddRange( out_port, vcBegin, vcEnd ); -} - -//============================================================= - -void dim_order_torus( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - int cur = r->GetID( ); - int dest = f->dest; - - dor_next_torus( cur, dest, in_channel, - &out_port, &f->ph, false ); - - - // at the destination router, we don't need to separate VCs by ring partition - if(cur != dest) { - - int const available_vcs = (vcEnd - vcBegin + 1) / 2; - assert(available_vcs > 0); - - if ( f->ph == 0 ) { - vcEnd -= available_vcs; - } else { - vcBegin += available_vcs; - } - } - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << "Adding VC range [" - << vcBegin << "," - << vcEnd << "]" - << " at output port " << out_port - << " for flit " << f->id - << " (input port " << in_channel - << ", destination " << f->dest << ")" - << "." << endl; - } - - } - - outputs->Clear( ); - - outputs->AddRange( out_port, vcBegin, vcEnd ); -} - -//============================================================= - -void dim_order_ni_torus( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - int cur = r->GetID( ); - int dest = f->dest; - - dor_next_torus( cur, dest, in_channel, - &out_port, NULL, false ); - - // at the destination router, we don't need to separate VCs by destination - if(cur != dest) { - - int const vcs_per_dest = (vcEnd - vcBegin + 1) / gNodes; - assert(vcs_per_dest); - - vcBegin += f->dest * vcs_per_dest; - vcEnd = vcBegin + vcs_per_dest - 1; - - } - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << "Adding VC range [" - << vcBegin << "," - << vcEnd << "]" - << " at output port " << out_port - << " for flit " << f->id - << " (input port " << in_channel - << ", destination " << f->dest << ")" - << "." << endl; - } - - } - - outputs->Clear( ); - - outputs->AddRange( out_port, vcBegin, vcEnd ); -} - -//============================================================= - -void dim_order_bal_torus( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - int cur = r->GetID( ); - int dest = f->dest; - - dor_next_torus( cur, dest, in_channel, - &out_port, &f->ph, true ); - - // at the destination router, we don't need to separate VCs by ring partition - if(cur != dest) { - - int const available_vcs = (vcEnd - vcBegin + 1) / 2; - assert(available_vcs > 0); - - if ( f->ph == 0 ) { - vcEnd -= available_vcs; - } else { - assert(f->ph == 1); - vcBegin += available_vcs; - } - } - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << "Adding VC range [" - << vcBegin << "," - << vcEnd << "]" - << " at output port " << out_port - << " for flit " << f->id - << " (input port " << in_channel - << ", destination " << f->dest << ")" - << "." << endl; - } - - } - - outputs->Clear( ); - - outputs->AddRange( out_port, vcBegin, vcEnd ); -} - -//============================================================= - -void min_adapt_torus( const Router *r, const Flit *f, int in_channel, OutputSet *outputs, bool inject ) -{ - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - outputs->Clear( ); - - if(inject) { - // injection can use all VCs - outputs->AddRange(-1, vcBegin, vcEnd); - return; - } else if(r->GetID() == f->dest) { - // ejection can also use all VCs - outputs->AddRange(2*gN, vcBegin, vcEnd); - } - - int in_vc; - if ( in_channel == 2*gN ) { - in_vc = vcEnd; // ignore the injection VC - } else { - in_vc = f->vc; - } - - int cur = r->GetID( ); - int dest = f->dest; - - int out_port; - - if ( in_vc > ( vcBegin + 1 ) ) { // If not in the escape VCs - // Minimal adaptive for all other channels - - for ( int n = 0; n < gN; ++n ) { - if ( ( cur % gK ) != ( dest % gK ) ) { - int dist2 = gK - 2 * ( ( ( dest % gK ) - ( cur % gK ) + gK ) % gK ); - - if ( dist2 > 0 ) { /*) || - ( ( dist2 == 0 ) && ( RandomInt( 1 ) ) ) ) {*/ - outputs->AddRange( 2*n, vcBegin+3, vcBegin+3, 1 ); // Right - } else { - outputs->AddRange( 2*n + 1, vcBegin+3, vcBegin+3, 1 ); // Left - } - } - - cur /= gK; - dest /= gK; - } - - // DOR for the escape channel (VCs 0-1), low priority --- - // trick the algorithm with the in channel. want VC assignment - // as if we had injected at this node - dor_next_torus( r->GetID( ), f->dest, 2*gN, - &out_port, &f->ph, false ); - } else { - // DOR for the escape channel (VCs 0-1), low priority - dor_next_torus( cur, dest, in_channel, - &out_port, &f->ph, false ); - } - - if ( f->ph == 0 ) { - outputs->AddRange( out_port, vcBegin, vcBegin, 0 ); - } else { - outputs->AddRange( out_port, vcBegin+1, vcBegin+1, 0 ); - } -} - -//============================================================= - -void dest_tag_fly( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - int stage = ( r->GetID( ) * gK ) / gNodes; - int dest = f->dest; - - while( stage < ( gN - 1 ) ) { - dest /= gK; - ++stage; - } - - out_port = dest % gK; - } - - outputs->Clear( ); - - outputs->AddRange( out_port, vcBegin, vcEnd ); -} - - - -//============================================================= - -void chaos_torus( const Router *r, const Flit *f, - int in_channel, OutputSet *outputs, bool inject ) -{ - outputs->Clear( ); - - if(inject) { - outputs->AddRange(-1, 0, 0); - return; - } - - int cur = r->GetID( ); - int dest = f->dest; - - if ( cur != dest ) { - for ( int n = 0; n < gN; ++n ) { - - if ( ( cur % gK ) != ( dest % gK ) ) { - int dist2 = gK - 2 * ( ( ( dest % gK ) - ( cur % gK ) + gK ) % gK ); - - if ( dist2 >= 0 ) { - outputs->AddRange( 2*n, 0, 0 ); // Right - } - - if ( dist2 <= 0 ) { - outputs->AddRange( 2*n + 1, 0, 0 ); // Left - } - } - - cur /= gK; - dest /= gK; - } - } else { - outputs->AddRange( 2*gN, 0, 0 ); - } -} - - -//============================================================= - -void chaos_mesh( const Router *r, const Flit *f, - int in_channel, OutputSet *outputs, bool inject ) -{ - outputs->Clear( ); - - if(inject) { - outputs->AddRange(-1, 0, 0); - return; - } - - int cur = r->GetID( ); - int dest = f->dest; - - if ( cur != dest ) { - for ( int n = 0; n < gN; ++n ) { - if ( ( cur % gK ) != ( dest % gK ) ) { - // Add minimal direction in dimension 'n' - if ( ( cur % gK ) < ( dest % gK ) ) { // Right - outputs->AddRange( 2*n, 0, 0 ); - } else { // Left - outputs->AddRange( 2*n + 1, 0, 0 ); - } - } - cur /= gK; - dest /= gK; - } - } else { - outputs->AddRange( 2*gN, 0, 0 ); - } -} - -//============================================================= - -void InitializeRoutingMap( const Configuration & config ) -{ - - gNumVCs = config.GetInt( "num_vcs" ); - - // - // traffic class partitions - // - gReadReqBeginVC = config.GetInt("read_request_begin_vc"); - if(gReadReqBeginVC < 0) { - gReadReqBeginVC = 0; - } - gReadReqEndVC = config.GetInt("read_request_end_vc"); - if(gReadReqEndVC < 0) { - gReadReqEndVC = gNumVCs / 2 - 1; - } - gWriteReqBeginVC = config.GetInt("write_request_begin_vc"); - if(gWriteReqBeginVC < 0) { - gWriteReqBeginVC = 0; - } - gWriteReqEndVC = config.GetInt("write_request_end_vc"); - if(gWriteReqEndVC < 0) { - gWriteReqEndVC = gNumVCs / 2 - 1; - } - gReadReplyBeginVC = config.GetInt("read_reply_begin_vc"); - if(gReadReplyBeginVC < 0) { - gReadReplyBeginVC = gNumVCs / 2; - } - gReadReplyEndVC = config.GetInt("read_reply_end_vc"); - if(gReadReplyEndVC < 0) { - gReadReplyEndVC = gNumVCs - 1; - } - gWriteReplyBeginVC = config.GetInt("write_reply_begin_vc"); - if(gWriteReplyBeginVC < 0) { - gWriteReplyBeginVC = gNumVCs / 2; - } - gWriteReplyEndVC = config.GetInt("write_reply_end_vc"); - if(gWriteReplyEndVC < 0) { - gWriteReplyEndVC = gNumVCs - 1; - } - - /* Register routing functions here */ - - // =================================================== - // Balfour-Schultz - gRoutingFunctionMap["nca_fattree"] = &fattree_nca; - gRoutingFunctionMap["anca_fattree"] = &fattree_anca; - gRoutingFunctionMap["nca_qtree"] = &qtree_nca; - gRoutingFunctionMap["nca_tree4"] = &tree4_nca; - gRoutingFunctionMap["anca_tree4"] = &tree4_anca; - gRoutingFunctionMap["dor_mesh"] = &dim_order_mesh; - gRoutingFunctionMap["xy_yx_mesh"] = &xy_yx_mesh; - gRoutingFunctionMap["adaptive_xy_yx_mesh"] = &adaptive_xy_yx_mesh; - // End Balfour-Schultz - // =================================================== - - gRoutingFunctionMap["dim_order_mesh"] = &dim_order_mesh; - gRoutingFunctionMap["dim_order_ni_mesh"] = &dim_order_ni_mesh; - gRoutingFunctionMap["dim_order_pni_mesh"] = &dim_order_pni_mesh; - gRoutingFunctionMap["dim_order_torus"] = &dim_order_torus; - gRoutingFunctionMap["dim_order_ni_torus"] = &dim_order_ni_torus; - gRoutingFunctionMap["dim_order_bal_torus"] = &dim_order_bal_torus; - - gRoutingFunctionMap["romm_mesh"] = &romm_mesh; - gRoutingFunctionMap["romm_ni_mesh"] = &romm_ni_mesh; - - gRoutingFunctionMap["min_adapt_mesh"] = &min_adapt_mesh; - gRoutingFunctionMap["min_adapt_torus"] = &min_adapt_torus; - - gRoutingFunctionMap["planar_adapt_mesh"] = &planar_adapt_mesh; - - // FIXME: This is broken. - // gRoutingFunctionMap["limited_adapt_mesh"] = &limited_adapt_mesh; - - gRoutingFunctionMap["valiant_mesh"] = &valiant_mesh; - gRoutingFunctionMap["valiant_torus"] = &valiant_torus; - gRoutingFunctionMap["valiant_ni_torus"] = &valiant_ni_torus; - - gRoutingFunctionMap["dest_tag_fly"] = &dest_tag_fly; - - gRoutingFunctionMap["chaos_mesh"] = &chaos_mesh; - gRoutingFunctionMap["chaos_torus"] = &chaos_torus; -} diff --git a/src/intersim2/.svn/pristine/47/471f8248dcd907fcddacc3b42c965e4919cb2f35.svn-base b/src/intersim2/.svn/pristine/47/471f8248dcd907fcddacc3b42c965e4919cb2f35.svn-base deleted file mode 100644 index 9e65de5..0000000 --- a/src/intersim2/.svn/pristine/47/471f8248dcd907fcddacc3b42c965e4919cb2f35.svn-base +++ /dev/null @@ -1,48 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _ISLIP_HPP_ -#define _ISLIP_HPP_ - -#include - -#include "allocator.hpp" - -class iSLIP_Sparse : public SparseAllocator { - int _iSLIP_iter; - - vector _gptrs; - vector _aptrs; - -public: - iSLIP_Sparse( Module *parent, const string& name, - int inputs, int outputs, int iters ); - - void Allocate( ); -}; - -#endif diff --git a/src/intersim2/.svn/pristine/4d/4d8326ecf3cc79ffda12daf20e4a46b4439ada88.svn-base b/src/intersim2/.svn/pristine/4d/4d8326ecf3cc79ffda12daf20e4a46b4439ada88.svn-base deleted file mode 100644 index d96bd56..0000000 --- a/src/intersim2/.svn/pristine/4d/4d8326ecf3cc79ffda12daf20e4a46b4439ada88.svn-base +++ /dev/null @@ -1,290 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/*network.cpp - * - *This class is the basis of the entire network, it contains, all the routers - *channels in the network, and is extended by all the network topologies - * - */ - -#include -#include - -#include "booksim.hpp" -#include "network.hpp" - -#include "kncube.hpp" -#include "fly.hpp" -#include "cmesh.hpp" -#include "flatfly_onchip.hpp" -#include "qtree.hpp" -#include "tree4.hpp" -#include "fattree.hpp" -#include "anynet.hpp" -#include "dragonfly.hpp" - - -Network::Network( const Configuration &config, const string & name ) : - TimedModule( 0, name ) -{ - _size = -1; - _nodes = -1; - _channels = -1; - _classes = config.GetInt("classes"); -} - -Network::~Network( ) -{ - for ( int r = 0; r < _size; ++r ) { - if ( _routers[r] ) delete _routers[r]; - } - for ( int s = 0; s < _nodes; ++s ) { - if ( _inject[s] ) delete _inject[s]; - if ( _inject_cred[s] ) delete _inject_cred[s]; - } - for ( int d = 0; d < _nodes; ++d ) { - if ( _eject[d] ) delete _eject[d]; - if ( _eject_cred[d] ) delete _eject_cred[d]; - } - for ( int c = 0; c < _channels; ++c ) { - if ( _chan[c] ) delete _chan[c]; - if ( _chan_cred[c] ) delete _chan_cred[c]; - } -} - -Network * Network::New(const Configuration & config, const string & name) -{ - const string topo = config.GetStr( "topology" ); - Network * n = NULL; - if ( topo == "torus" ) { - KNCube::RegisterRoutingFunctions() ; - n = new KNCube( config, name, false ); - } else if ( topo == "mesh" ) { - KNCube::RegisterRoutingFunctions() ; - n = new KNCube( config, name, true ); - } else if ( topo == "cmesh" ) { - CMesh::RegisterRoutingFunctions() ; - n = new CMesh( config, name ); - } else if ( topo == "fly" ) { - KNFly::RegisterRoutingFunctions() ; - n = new KNFly( config, name ); - } else if ( topo == "qtree" ) { - QTree::RegisterRoutingFunctions() ; - n = new QTree( config, name ); - } else if ( topo == "tree4" ) { - Tree4::RegisterRoutingFunctions() ; - n = new Tree4( config, name ); - } else if ( topo == "fattree" ) { - FatTree::RegisterRoutingFunctions() ; - n = new FatTree( config, name ); - } else if ( topo == "flatfly" ) { - FlatFlyOnChip::RegisterRoutingFunctions() ; - n = new FlatFlyOnChip( config, name ); - } else if ( topo == "anynet"){ - AnyNet::RegisterRoutingFunctions() ; - n = new AnyNet(config, name); - } else if ( topo == "dragonflynew"){ - DragonFlyNew::RegisterRoutingFunctions() ; - n = new DragonFlyNew(config, name); - } else { - cerr << "Unknown topology: " << topo << endl; - } - - /*legacy code that insert random faults in the networks - *not sure how to use this - */ - if ( n && ( config.GetInt( "link_failures" ) > 0 ) ) { - n->InsertRandomFaults( config ); - } - return n; -} - -void Network::_Alloc( ) -{ - assert( ( _size != -1 ) && - ( _nodes != -1 ) && - ( _channels != -1 ) ); - - _routers.resize(_size); - gNodes = _nodes; - - /*booksim used arrays of flits as the channels which makes have capacity of - *one. To simulate channel latency, flitchannel class has been added - *which are fifos with depth = channel latency and each cycle the channel - *shifts by one - *credit channels are the necessary counter part - */ - _inject.resize(_nodes); - _inject_cred.resize(_nodes); - for ( int s = 0; s < _nodes; ++s ) { - ostringstream name; - name << Name() << "_fchan_ingress" << s; - _inject[s] = new FlitChannel(this, name.str(), _classes); - _inject[s]->SetSource(NULL, s); - _timed_modules.push_back(_inject[s]); - name.str(""); - name << Name() << "_cchan_ingress" << s; - _inject_cred[s] = new CreditChannel(this, name.str()); - _timed_modules.push_back(_inject_cred[s]); - } - _eject.resize(_nodes); - _eject_cred.resize(_nodes); - for ( int d = 0; d < _nodes; ++d ) { - ostringstream name; - name << Name() << "_fchan_egress" << d; - _eject[d] = new FlitChannel(this, name.str(), _classes); - _eject[d]->SetSink(NULL, d); - _timed_modules.push_back(_eject[d]); - name.str(""); - name << Name() << "_cchan_egress" << d; - _eject_cred[d] = new CreditChannel(this, name.str()); - _timed_modules.push_back(_eject_cred[d]); - } - _chan.resize(_channels); - _chan_cred.resize(_channels); - for ( int c = 0; c < _channels; ++c ) { - ostringstream name; - name << Name() << "_fchan_" << c; - _chan[c] = new FlitChannel(this, name.str(), _classes); - _timed_modules.push_back(_chan[c]); - name.str(""); - name << Name() << "_cchan_" << c; - _chan_cred[c] = new CreditChannel(this, name.str()); - _timed_modules.push_back(_chan_cred[c]); - } -} - -void Network::ReadInputs( ) -{ - for(deque::const_iterator iter = _timed_modules.begin(); - iter != _timed_modules.end(); - ++iter) { - (*iter)->ReadInputs( ); - } -} - -void Network::Evaluate( ) -{ - for(deque::const_iterator iter = _timed_modules.begin(); - iter != _timed_modules.end(); - ++iter) { - (*iter)->Evaluate( ); - } -} - -void Network::WriteOutputs( ) -{ - for(deque::const_iterator iter = _timed_modules.begin(); - iter != _timed_modules.end(); - ++iter) { - (*iter)->WriteOutputs( ); - } -} - -void Network::WriteFlit( Flit *f, int source ) -{ - assert( ( source >= 0 ) && ( source < _nodes ) ); - _inject[source]->Send(f); -} - -Flit *Network::ReadFlit( int dest ) -{ - assert( ( dest >= 0 ) && ( dest < _nodes ) ); - return _eject[dest]->Receive(); -} - -void Network::WriteCredit( Credit *c, int dest ) -{ - assert( ( dest >= 0 ) && ( dest < _nodes ) ); - _eject_cred[dest]->Send(c); -} - -Credit *Network::ReadCredit( int source ) -{ - assert( ( source >= 0 ) && ( source < _nodes ) ); - return _inject_cred[source]->Receive(); -} - -void Network::InsertRandomFaults( const Configuration &config ) -{ - Error( "InsertRandomFaults not implemented for this topology!" ); -} - -void Network::OutChannelFault( int r, int c, bool fault ) -{ - assert( ( r >= 0 ) && ( r < _size ) ); - _routers[r]->OutChannelFault( c, fault ); -} - -double Network::Capacity( ) const -{ - return 1.0; -} - -/* this function can be heavily modified to display any information - * neceesary of the network, by default, call display on each router - * and display the channel utilization rate - */ -void Network::Display( ostream & os ) const -{ - for ( int r = 0; r < _size; ++r ) { - _routers[r]->Display( os ); - } -} - -void Network::DumpChannelMap( ostream & os, string const & prefix ) const -{ - os << prefix << "source_router,source_port,dest_router,dest_port" << endl; - for(int c = 0; c < _nodes; ++c) - os << prefix - << "-1," - << _inject[c]->GetSourcePort() << ',' - << _inject[c]->GetSink()->GetID() << ',' - << _inject[c]->GetSinkPort() << endl; - for(int c = 0; c < _channels; ++c) - os << prefix - << _chan[c]->GetSource()->GetID() << ',' - << _chan[c]->GetSourcePort() << ',' - << _chan[c]->GetSink()->GetID() << ',' - << _chan[c]->GetSinkPort() << endl; - for(int c = 0; c < _nodes; ++c) - os << prefix - << _eject[c]->GetSource()->GetID() << ',' - << _eject[c]->GetSourcePort() << ',' - << "-1," - << _eject[c]->GetSinkPort() << endl; -} - -void Network::DumpNodeMap( ostream & os, string const & prefix ) const -{ - os << prefix << "source_router,dest_router" << endl; - for(int s = 0; s < _nodes; ++s) - os << prefix - << _eject[s]->GetSource()->GetID() << ',' - << _inject[s]->GetSink()->GetID() << endl; -} diff --git a/src/intersim2/.svn/pristine/52/52025d7789c8bb45a38bad2e58ac67cc26f3b4ed.svn-base b/src/intersim2/.svn/pristine/52/52025d7789c8bb45a38bad2e58ac67cc26f3b4ed.svn-base deleted file mode 100644 index 261c411..0000000 --- a/src/intersim2/.svn/pristine/52/52025d7789c8bb45a38bad2e58ac67cc26f3b4ed.svn-base +++ /dev/null @@ -1,99 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// ---------------------------------------------------------------------- -// -// File Name: flitchannel.hpp -// -// The FlitChannel models a flit channel with a multi-cycle -// transmission delay. The channel latency can be specified as -// an integer number of simulator cycles. -// ---------------------------------------------------------------------- - -#ifndef FLITCHANNEL_HPP -#define FLITCHANNEL_HPP - -// ---------------------------------------------------------------------- -// $Author: jbalfour $ -// $Date: 2007/06/27 23:10:17 $ -// $Id$ -// ---------------------------------------------------------------------- - -#include "channel.hpp" -#include "flit.hpp" - -using namespace std; - -class Router ; - -class FlitChannel : public Channel { -public: - FlitChannel(Module * parent, string const & name, int classes); - - void SetSource(Router const * const router, int port) ; - inline Router const * const GetSource() const { - return _routerSource; - } - inline int const & GetSourcePort() const { - return _routerSourcePort; - } - void SetSink(Router const * const router, int port) ; - inline Router const * const GetSink() const { - return _routerSink; - } - inline int const & GetSinkPort() const { - return _routerSinkPort; - } - inline vector const & GetActivity() const { - return _active; - } - - // Send flit - virtual void Send(Flit * flit); - - virtual void ReadInputs(); - virtual void WriteOutputs(); - -private: - - //////////////////////////////////////// - // - // Power Models OBSOLETE - // - //////////////////////////////////////// - - Router const * _routerSource; - int _routerSourcePort; - Router const * _routerSink; - int _routerSinkPort; - - // Statistics for Activity Factors - vector _active; - int _idle; -}; - -#endif diff --git a/src/intersim2/.svn/pristine/55/5559780a67de13b98fb00d7f052ce254551f229b.svn-base b/src/intersim2/.svn/pristine/55/5559780a67de13b98fb00d7f052ce254551f229b.svn-base deleted file mode 100644 index 4387d46..0000000 --- a/src/intersim2/.svn/pristine/55/5559780a67de13b98fb00d7f052ce254551f229b.svn-base +++ /dev/null @@ -1,88 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _FlatFlyOnChip_HPP_ -#define _FlatFlyOnChip_HPP_ - -#include "network.hpp" - -#include "routefunc.hpp" -#include - - -class FlatFlyOnChip : public Network { - - int _m; - int _n; - int _r; - int _k; - int _c; - int _radix; - int _net_size; - int _stageout; - int _numinput; - int _stages; - int _num_of_switch; - - void _ComputeSize( const Configuration &config ); - void _BuildNet( const Configuration &config ); - - int _OutChannel( int stage, int addr, int port, int outputs ) const; - int _InChannel( int stage, int addr, int port ) const; - -public: - FlatFlyOnChip( const Configuration &config, const string & name ); - - int GetN( ) const; - int GetK( ) const; - - static void RegisterRoutingFunctions() ; - double Capacity( ) const; - void InsertRandomFaults( const Configuration &config ); -}; -void adaptive_xyyx_flatfly( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ); -void xyyx_flatfly( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ); -void min_flatfly( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ); -void ugal_xyyx_flatfly_onchip( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ); -void ugal_flatfly_onchip( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ); -void ugal_pni_flatfly_onchip( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ); -void valiant_flatfly( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ); - -int find_distance (int src, int dest); -int find_ran_intm (int src, int dest); -int flatfly_outport(int dest, int rID); -int flatfly_transformation(int dest); -int flatfly_outport_yx(int dest, int rID); - -#endif diff --git a/src/intersim2/.svn/pristine/55/55ee19fa1932804a55ee815f4456c4a6f21a355f.svn-base b/src/intersim2/.svn/pristine/55/55ee19fa1932804a55ee815f4456c4a6f21a355f.svn-base deleted file mode 100644 index 5d38938..0000000 --- a/src/intersim2/.svn/pristine/55/55ee19fa1932804a55ee815f4456c4a6f21a355f.svn-base +++ /dev/null @@ -1,239 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _BUFFER_STATE_HPP_ -#define _BUFFER_STATE_HPP_ - -#include -#include - -#include "module.hpp" -#include "flit.hpp" -#include "credit.hpp" -#include "config_utils.hpp" - -class BufferState : public Module { - - class BufferPolicy : public Module { - protected: - BufferState const * const _buffer_state; - public: - BufferPolicy(Configuration const & config, BufferState * parent, - const string & name); - virtual void SetMinLatency(int min_latency) {} - virtual void TakeBuffer(int vc = 0); - virtual void SendingFlit(Flit const * const f); - virtual void FreeSlotFor(int vc = 0); - virtual bool IsFullFor(int vc = 0) const = 0; - virtual int AvailableFor(int vc = 0) const = 0; - virtual int LimitFor(int vc = 0) const = 0; - - static BufferPolicy * New(Configuration const & config, - BufferState * parent, const string & name); - }; - - class PrivateBufferPolicy : public BufferPolicy { - protected: - int _vc_buf_size; - public: - PrivateBufferPolicy(Configuration const & config, BufferState * parent, - const string & name); - virtual void SendingFlit(Flit const * const f); - virtual bool IsFullFor(int vc = 0) const; - virtual int AvailableFor(int vc = 0) const; - virtual int LimitFor(int vc = 0) const; - }; - - class SharedBufferPolicy : public BufferPolicy { - protected: - int _buf_size; - vector _private_buf_vc_map; - vector _private_buf_size; - vector _private_buf_occupancy; - int _shared_buf_size; - int _shared_buf_occupancy; - vector _reserved_slots; - void ProcessFreeSlot(int vc = 0); - public: - SharedBufferPolicy(Configuration const & config, BufferState * parent, - const string & name); - virtual void SendingFlit(Flit const * const f); - virtual void FreeSlotFor(int vc = 0); - virtual bool IsFullFor(int vc = 0) const; - virtual int AvailableFor(int vc = 0) const; - virtual int LimitFor(int vc = 0) const; - }; - - class LimitedSharedBufferPolicy : public SharedBufferPolicy { - protected: - int _vcs; - int _active_vcs; - int _max_held_slots; - public: - LimitedSharedBufferPolicy(Configuration const & config, - BufferState * parent, - const string & name); - virtual void TakeBuffer(int vc = 0); - virtual void SendingFlit(Flit const * const f); - virtual bool IsFullFor(int vc = 0) const; - virtual int AvailableFor(int vc = 0) const; - virtual int LimitFor(int vc = 0) const; - }; - - class DynamicLimitedSharedBufferPolicy : public LimitedSharedBufferPolicy { - public: - DynamicLimitedSharedBufferPolicy(Configuration const & config, - BufferState * parent, - const string & name); - virtual void TakeBuffer(int vc = 0); - virtual void SendingFlit(Flit const * const f); - }; - - class ShiftingDynamicLimitedSharedBufferPolicy : public DynamicLimitedSharedBufferPolicy { - public: - ShiftingDynamicLimitedSharedBufferPolicy(Configuration const & config, - BufferState * parent, - const string & name); - virtual void TakeBuffer(int vc = 0); - virtual void SendingFlit(Flit const * const f); - }; - - class FeedbackSharedBufferPolicy : public SharedBufferPolicy { - protected: - int _ComputeRTT(int vc, int last_rtt) const; - int _ComputeLimit(int rtt) const; - int _ComputeMaxSlots(int vc) const; - int _vcs; - vector _occupancy_limit; - vector _round_trip_time; - vector > _flit_sent_time; - int _min_latency; - int _total_mapped_size; - int _aging_scale; - int _offset; - public: - FeedbackSharedBufferPolicy(Configuration const & config, - BufferState * parent, const string & name); - virtual void SetMinLatency(int min_latency); - virtual void SendingFlit(Flit const * const f); - virtual void FreeSlotFor(int vc = 0); - virtual bool IsFullFor(int vc = 0) const; - virtual int AvailableFor(int vc = 0) const; - virtual int LimitFor(int vc = 0) const; - }; - - class SimpleFeedbackSharedBufferPolicy : public FeedbackSharedBufferPolicy { - protected: - vector _pending_credits; - public: - SimpleFeedbackSharedBufferPolicy(Configuration const & config, - BufferState * parent, const string & name); - virtual void SendingFlit(Flit const * const f); - virtual void FreeSlotFor(int vc = 0); - }; - - bool _wait_for_tail_credit; - int _size; - int _occupancy; - vector _vc_occupancy; - int _vcs; - - BufferPolicy * _buffer_policy; - - vector _in_use_by; - vector _tail_sent; - vector _last_id; - vector _last_pid; - -#ifdef TRACK_BUFFERS - int _classes; - vector > _outstanding_classes; - vector _class_occupancy; -#endif - -public: - - BufferState( const Configuration& config, - Module *parent, const string& name ); - - ~BufferState(); - - inline void SetMinLatency(int min_latency) { - _buffer_policy->SetMinLatency(min_latency); - } - - void ProcessCredit( Credit const * const c ); - void SendingFlit( Flit const * const f ); - - void TakeBuffer( int vc = 0, int tag = 0 ); - - inline bool IsFull() const { - assert(_occupancy <= _size); - return (_occupancy == _size); - } - inline bool IsFullFor( int vc = 0 ) const { - return _buffer_policy->IsFullFor(vc); - } - inline int AvailableFor( int vc = 0 ) const { - return _buffer_policy->AvailableFor(vc); - } - inline int LimitFor( int vc = 0 ) const { - return _buffer_policy->LimitFor(vc); - } - inline bool IsEmptyFor(int vc = 0) const { - assert((vc >= 0) && (vc < _vcs)); - return (_vc_occupancy[vc] == 0); - } - inline bool IsAvailableFor( int vc = 0 ) const { - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - return _in_use_by[vc] < 0; - } - inline int UsedBy(int vc = 0) const { - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - return _in_use_by[vc]; - } - - inline int Occupancy() const { - return _occupancy; - } - - inline int OccupancyFor( int vc = 0 ) const { - assert((vc >= 0) && (vc < _vcs)); - return _vc_occupancy[vc]; - } - -#ifdef TRACK_BUFFERS - inline int OccupancyForClass(int c) const { - assert((c >= 0) && (c < _classes)); - return _class_occupancy[c]; - } -#endif - - void Display( ostream & os = cout ) const; -}; - -#endif diff --git a/src/intersim2/.svn/pristine/56/569d5254648903d6589a32c30a98b3276cdbdebd.svn-base b/src/intersim2/.svn/pristine/56/569d5254648903d6589a32c30a98b3276cdbdebd.svn-base deleted file mode 100644 index 5ecb0f9..0000000 --- a/src/intersim2/.svn/pristine/56/569d5254648903d6589a32c30a98b3276cdbdebd.svn-base +++ /dev/null @@ -1,91 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// ---------------------------------------------------------------------- -// -// File Name: flitchannel.cpp -// Author: James Balfour, Rebecca Schultz -// -// ---------------------------------------------------------------------- - -#include "flitchannel.hpp" - -#include -#include - -#include "router.hpp" -#include "globals.hpp" - -// ---------------------------------------------------------------------- -// $Author: jbalfour $ -// $Date: 2007/06/27 23:10:17 $ -// $Id$ -// ---------------------------------------------------------------------- -FlitChannel::FlitChannel(Module * parent, string const & name, int classes) -: Channel(parent, name), _routerSource(NULL), _routerSourcePort(-1), - _routerSink(NULL), _routerSinkPort(-1), _idle(0) { - _active.resize(classes, 0); -} - -void FlitChannel::SetSource(Router const * const router, int port) { - _routerSource = router; - _routerSourcePort = port; -} - -void FlitChannel::SetSink(Router const * const router, int port) { - _routerSink = router; - _routerSinkPort = port; -} - -void FlitChannel::Send(Flit * f) { - if(f) { - ++_active[f->cl]; - } else { - ++_idle; - } - Channel::Send(f); -} - -void FlitChannel::ReadInputs() { - Flit const * const & f = _input; - if(f && f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Beginning channel traversal for flit " << f->id - << " with delay " << _delay - << "." << endl; - } - Channel::ReadInputs(); -} - -void FlitChannel::WriteOutputs() { - Channel::WriteOutputs(); - if(_output && _output->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Completed channel traversal for flit " << _output->id - << "." << endl; - } -} diff --git a/src/intersim2/.svn/pristine/58/589a6050104bd5e828d72f3efdc31796eae32683.svn-base b/src/intersim2/.svn/pristine/58/589a6050104bd5e828d72f3efdc31796eae32683.svn-base deleted file mode 100644 index 59249e6..0000000 --- a/src/intersim2/.svn/pristine/58/589a6050104bd5e828d72f3efdc31796eae32683.svn-base +++ /dev/null @@ -1,51 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _MAXSIZE_HPP_ -#define _MAXSIZE_HPP_ - -#include - -#include "allocator.hpp" - -class MaxSizeMatch : public DenseAllocator { - vector _from; // array to hold breadth-first tree - int *_s; // stack of leaf nodes in tree - int *_ns; // next stack - int _prio; // priority pointer to ensure fairness - - bool _ShortestAugmenting( ); - -public: - MaxSizeMatch( Module *parent, const string& name, - int inputs, int ouputs ); - ~MaxSizeMatch( ); - - void Allocate( ); -}; - -#endif diff --git a/src/intersim2/.svn/pristine/59/59bcc26ad66045a58e3f0590f2b12ad7eba5991f.svn-base b/src/intersim2/.svn/pristine/59/59bcc26ad66045a58e3f0590f2b12ad7eba5991f.svn-base deleted file mode 100644 index 5919b56..0000000 --- a/src/intersim2/.svn/pristine/59/59bcc26ad66045a58e3f0590f2b12ad7eba5991f.svn-base +++ /dev/null @@ -1,71 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// ---------------------------------------------------------------------- -// -// Matrix: Matrix Arbiter -// -// ---------------------------------------------------------------------- - -#ifndef _MATRIX_ARB_HPP_ -#define _MATRIX_ARB_HPP_ - -#include - -#include "arbiter.hpp" - -using namespace std; - -class MatrixArbiter : public Arbiter { - - // Priority matrix - vector > _matrix ; - - int _last_req ; - -public: - - // Constructors - MatrixArbiter( Module *parent, const string &name, int size ) ; - - // Print priority matrix to standard output - virtual void PrintState() const ; - - // Update priority matrix based on last aribtration result - virtual void UpdateState() ; - - // Arbitrate amongst requests. Returns winning input and - // updates pointers to metadata when valid pointers are passed - virtual int Arbitrate( int* id = 0, int* pri = 0) ; - - virtual void AddRequest( int input, int id, int pri ) ; - - virtual void Clear(); - -} ; - -#endif diff --git a/src/intersim2/.svn/pristine/5c/5cc61faafce12ea44fa63fb32a14f8f0c74c7338.svn-base b/src/intersim2/.svn/pristine/5c/5cc61faafce12ea44fa63fb32a14f8f0c74c7338.svn-base deleted file mode 100644 index d438ee6..0000000 --- a/src/intersim2/.svn/pristine/5c/5cc61faafce12ea44fa63fb32a14f8f0c74c7338.svn-base +++ /dev/null @@ -1,66 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _OUTPUTSET_HPP_ -#define _OUTPUTSET_HPP_ - -#include - -class OutputSet { - - -public: - struct sSetElement { - int vc_start; - int vc_end; - int pri; - int output_port; - }; - - void Clear( ); - void Add( int output_port, int vc, int pri = 0 ); - void AddRange( int output_port, int vc_start, int vc_end, int pri = 0 ); - - bool OutputEmpty( int output_port ) const; - int NumVCs( int output_port ) const; - - const set & GetSet() const; - - int GetVC( int output_port, int vc_index, int *pri = 0 ) const; - bool GetPortVC( int *out_port, int *out_vc ) const; -private: - set _outputs; -}; - -inline bool operator<(const OutputSet::sSetElement & se1, - const OutputSet::sSetElement & se2) { - return se1.pri > se2.pri; // higher priorities first! -} - -#endif - - diff --git a/src/intersim2/.svn/pristine/5f/5f655d8c1cb25991e3f079611f3bad0ba05c6b6d.svn-base b/src/intersim2/.svn/pristine/5f/5f655d8c1cb25991e3f079611f3bad0ba05c6b6d.svn-base deleted file mode 100644 index 44d597c..0000000 --- a/src/intersim2/.svn/pristine/5f/5f655d8c1cb25991e3f079611f3bad0ba05c6b6d.svn-base +++ /dev/null @@ -1,187 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -//////////////////////////////////////////////////////////////////////// -// -// QTree: A Quad-Tree Indirect Network. -// -// -//////////////////////////////////////////////////////////////////////// -// -// RCS Information: -// $Author: jbalfour $ -// $Date: 2007/05/17 17:14:07 $ -// $Id$ -// -//////////////////////////////////////////////////////////////////////// - -#include "booksim.hpp" -#include -#include -#include "qtree.hpp" -#include "misc_utils.hpp" - -QTree::QTree( const Configuration& config, const string & name ) -: Network ( config, name ) -{ - _ComputeSize( config ); - _Alloc( ); - _BuildNet( config ); -} - - -void QTree::_ComputeSize( const Configuration& config ) -{ - - _k = config.GetInt( "k" ); - _n = config.GetInt( "n" ); - - assert( _k == 4 && _n == 3 ); - - gK = _k; gN = _n; - - _nodes = powi( _k, _n ); - - _size = 0; - for (int i = 0; i < _n; i++) - _size += powi( _k, i ); - - _channels = 0; - for (int j = 1; j < _n; j++) - _channels += 2 * powi( _k, j ); - -} - -void QTree::RegisterRoutingFunctions(){ - -} - -void QTree::_BuildNet( const Configuration& config ) -{ - - ostringstream routerName; - int h, r, pos, port; - - for (h = 0; h < _n; h++) { - for (pos = 0 ; pos < powi( _k, h ) ; ++pos ) { - - int id = h * 256 + pos; - r = _RouterIndex( h, pos ); - - routerName << "router_" << h << "_" << pos; - - int d = ( h == 0 ) ? _k : _k + 1; - _routers[r] = Router::NewRouter( config, this, - routerName.str( ), - id, d, d); - _timed_modules.push_back(_routers[r]); - routerName.str(""); - } - } - - // Injection & Ejection Channels - for ( pos = 0 ; pos < powi( _k, _n-1 ) ; ++pos ) { - r = _RouterIndex( _n-1, pos ); - for ( port = 0 ; port < _k ; port++ ) { - - _routers[r]->AddInputChannel( _inject[_k*pos+port], - _inject_cred[_k*pos+port]); - - _routers[r]->AddOutputChannel( _eject[_k*pos+port], - _eject_cred[_k*pos+port]); - } - } - - int c; - for ( h = 0 ; h < _n ; ++h ) { - for ( pos = 0 ; pos < powi( _k, h ) ; ++pos ) { - for ( port = 0 ; port < _k ; port++ ) { - - r = _RouterIndex( h, pos ); - - if ( h < _n-1 ) { - // Channels to Children Nodes - c = _InputIndex( h , pos, port ); - _routers[r]->AddInputChannel( _chan[c], - _chan_cred[c] ); - - c = _OutputIndex( h, pos, port ); - _routers[r]->AddOutputChannel( _chan[c], - _chan_cred[c] ); - - } - } - if ( h > 0 ) { - // Channels to Parent Nodes - c = _OutputIndex( h - 1, pos / _k, pos % _k ); - _routers[r]->AddInputChannel( _chan[c], - _chan_cred[c] ); - - c = _InputIndex( h - 1, pos / _k, pos % _k ); - _routers[r]->AddOutputChannel( _chan[c], - _chan_cred[c]); - } - } - } -} - -int QTree::_RouterIndex( int height, int pos ) -{ - int r = 0; - for ( int h = 0; h < height; h++ ) - r += powi( _k, h ); - return (r + pos); -} - -int QTree::_InputIndex( int height, int pos, int port ) -{ - assert( height >= 0 && height < powi( _k,_n-1 ) ); - int c = 0; - for ( int h = 0; h < height; h++) - c += powi( _k, h+1 ); - return ( c + _k * pos + port ); -} - -int QTree::_OutputIndex( int height, int pos, int port ) -{ - assert( height >= 0 && height < powi( _k,_n-1 ) ); - int c = _channels / 2; - for ( int h = 0; h < height; h++) - c += powi( _k, h+1 ); - return ( c + _k * pos + port ); -} - - -int QTree::HeightFromID( int id ) -{ - return id / 256; -} - -int QTree::PosFromID( int id ) -{ - return id % 256; -} diff --git a/src/intersim2/.svn/pristine/65/650f86454fd17051ddb2eca80fd985027770a1ba.svn-base b/src/intersim2/.svn/pristine/65/650f86454fd17051ddb2eca80fd985027770a1ba.svn-base deleted file mode 100644 index 466583e..0000000 --- a/src/intersim2/.svn/pristine/65/650f86454fd17051ddb2eca80fd985027770a1ba.svn-base +++ /dev/null @@ -1,49 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _LOA_HPP_ -#define _LOA_HPP_ - -#include - -#include "allocator.hpp" - -class LOA : public DenseAllocator { - vector _counts; - vector _req; - - vector _rptr; - vector _gptr; - -public: - LOA( Module *parent, const string& name, - int inputs, int outputs ); - - void Allocate( ); -}; - -#endif diff --git a/src/intersim2/.svn/pristine/66/6699bbb1b4cb750a8857780e76ee4923ef317c90.svn-base b/src/intersim2/.svn/pristine/66/6699bbb1b4cb750a8857780e76ee4923ef317c90.svn-base deleted file mode 100644 index 3667472..0000000 --- a/src/intersim2/.svn/pristine/66/6699bbb1b4cb750a8857780e76ee4923ef317c90.svn-base +++ /dev/null @@ -1,34 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _MISC_UTILS_HPP_ -#define _MISC_UTILS_HPP_ - -int log_two( int x ); -int powi( int x, int y ); - -#endif diff --git a/src/intersim2/.svn/pristine/69/691260433188a985b38ff49ca3f51e6c0b731c0a.svn-base b/src/intersim2/.svn/pristine/69/691260433188a985b38ff49ca3f51e6c0b731c0a.svn-base deleted file mode 100644 index f9e727a..0000000 --- a/src/intersim2/.svn/pristine/69/691260433188a985b38ff49ca3f51e6c0b731c0a.svn-base +++ /dev/null @@ -1,118 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _NETWORK_HPP_ -#define _NETWORK_HPP_ - -#include -#include - -#include "module.hpp" -#include "flit.hpp" -#include "credit.hpp" -#include "router.hpp" -#include "module.hpp" -#include "timed_module.hpp" -#include "flitchannel.hpp" -#include "channel.hpp" -#include "config_utils.hpp" -#include "globals.hpp" - -typedef Channel CreditChannel; - - -class Network : public TimedModule { -protected: - - int _size; - int _nodes; - int _channels; - int _classes; - - vector _routers; - - vector _inject; - vector _inject_cred; - - vector _eject; - vector _eject_cred; - - vector _chan; - vector _chan_cred; - - deque _timed_modules; - - virtual void _ComputeSize( const Configuration &config ) = 0; - virtual void _BuildNet( const Configuration &config ) = 0; - - void _Alloc( ); - -public: - Network( const Configuration &config, const string & name ); - virtual ~Network( ); - - static Network *New( const Configuration &config, const string & name ); - - virtual void WriteFlit( Flit *f, int source ); - virtual Flit *ReadFlit( int dest ); - - virtual void WriteCredit( Credit *c, int dest ); - virtual Credit *ReadCredit( int source ); - - inline int NumNodes( ) const {return _nodes;} - - virtual void InsertRandomFaults( const Configuration &config ); - void OutChannelFault( int r, int c, bool fault = true ); - - virtual double Capacity( ) const; - - virtual void ReadInputs( ); - virtual void Evaluate( ); - virtual void WriteOutputs( ); - - void Display( ostream & os = cout ) const; - void DumpChannelMap( ostream & os = cout, string const & prefix = "" ) const; - void DumpNodeMap( ostream & os = cout, string const & prefix = "" ) const; - - int NumChannels() const {return _channels;} - const vector & GetInject() {return _inject;} - FlitChannel * GetInject(int index) {return _inject[index];} - const vector & GetInjectCred() {return _inject_cred;} - CreditChannel * GetInjectCred(int index) {return _inject_cred[index];} - const vector & GetEject(){return _eject;} - FlitChannel * GetEject(int index) {return _eject[index];} - const vector & GetEjectCred(){return _eject_cred;} - CreditChannel * GetEjectCred(int index) {return _eject_cred[index];} - const vector & GetChannels(){return _chan;} - const vector & GetChannelsCred(){return _chan_cred;} - const vector & GetRouters(){return _routers;} - Router * GetRouter(int index) {return _routers[index];} - int NumRouters() const {return _size;} -}; - -#endif - diff --git a/src/intersim2/.svn/pristine/6c/6c86a0b772d76fae9d90046d17b6ec12b77551d0.svn-base b/src/intersim2/.svn/pristine/6c/6c86a0b772d76fae9d90046d17b6ec12b77551d0.svn-base deleted file mode 100644 index 58a3ba5..0000000 --- a/src/intersim2/.svn/pristine/6c/6c86a0b772d76fae9d90046d17b6ec12b77551d0.svn-base +++ /dev/null @@ -1,130 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/*stats.cpp - * - *class stores statistics gnerated by the trafficmanager such as the latency - *hope count of the the flits - * - *reset option resets the min and max alues of this statistiscs - */ - -#include "booksim.hpp" -#include -#include -#include -#include -#include - -#include "stats.hpp" - -Stats::Stats( Module *parent, const string &name, - double bin_size, int num_bins ) : - Module( parent, name ), _num_bins( num_bins ), _bin_size( bin_size ) -{ - Clear(); -} - -void Stats::Clear( ) -{ - _num_samples = 0; - _sample_sum = 0.0; - _sample_squared_sum = 0.0; - - _hist.assign(_num_bins, 0); - - _min = numeric_limits::quiet_NaN(); - _max = -numeric_limits::quiet_NaN(); - - // _reset = true; -} - -double Stats::Average( ) const -{ - return _sample_sum / (double)_num_samples; -} - -double Stats::Variance( ) const -{ - return (_sample_squared_sum * (double)_num_samples - _sample_sum * _sample_sum) / ((double)_num_samples * (double)_num_samples); -} - -double Stats::Min( ) const -{ - return _min; -} - -double Stats::Max( ) const -{ - return _max; -} - -double Stats::Sum( ) const -{ - return _sample_sum; -} - -double Stats::SquaredSum( ) const -{ - return _sample_squared_sum; -} - -int Stats::NumSamples( ) const -{ - return _num_samples; -} - -void Stats::AddSample( double val ) -{ - ++_num_samples; - _sample_sum += val; - - // NOTE: the negation ensures that NaN values are handled correctly! - _max = !(val <= _max) ? val : _max; - _min = !(val >= _min) ? val : _min; - - //double clamp between 0 and num_bins-1 - int b = (int)fmax(floor( val / _bin_size ), 0.0); - b = (b >= _num_bins) ? (_num_bins - 1) : b; - - _hist[b]++; -} - -void Stats::Display( ostream & os ) const -{ - os << *this << endl; -} - -ostream & operator<<(ostream & os, const Stats & s) { - vector const & v = s._hist; - os << "[ "; - for(size_t i = 0; i < v.size(); ++i) { - os << v[i] << " "; - } - os << "]"; - return os; -} diff --git a/src/intersim2/.svn/pristine/6d/6d0272df1c727d8c5fa77a3bfa9155d50335a5c6.svn-base b/src/intersim2/.svn/pristine/6d/6d0272df1c727d8c5fa77a3bfa9155d50335a5c6.svn-base deleted file mode 100644 index bbda15a..0000000 --- a/src/intersim2/.svn/pristine/6d/6d0272df1c727d8c5fa77a3bfa9155d50335a5c6.svn-base +++ /dev/null @@ -1,95 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -//////////////////////////////////////////////////////////////////////// -// -// CMesh: Mesh topology with concentration and express links along the -// edge of the network -// -//////////////////////////////////////////////////////////////////////// -// -// RCS Information: -// $Author: jbalfour $ -// $Date: 2007/06/26 22:49:23 $ -// $Id$ -// -//////////////////////////////////////////////////////////////////////// -#ifndef _CMESH_HPP_ -#define _CMESH_HPP_ - -#include "network.hpp" -#include "routefunc.hpp" - -class CMesh : public Network { -public: - CMesh( const Configuration &config, const string & name ); - int GetN() const; - int GetK() const; - - static int NodeToRouter( int address ) ; - static int NodeToPort( int address ) ; - - static void RegisterRoutingFunctions() ; - -private: - - static int _cX ; - static int _cY ; - - static int _memo_NodeShiftX ; - static int _memo_NodeShiftY ; - static int _memo_PortShiftY ; - - void _ComputeSize( const Configuration &config ); - void _BuildNet( const Configuration& config ); - - int _k ; - int _n ; - int _c ; - int _xcount; - int _ycount; - int _xrouter; - int _yrouter; - bool _express_channels; -}; - -// -// Routing Functions -// -void xy_yx_cmesh( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) ; - -void xy_yx_no_express_cmesh( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) ; - -void dor_cmesh( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) ; - -void dor_no_express_cmesh( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) ; - -#endif diff --git a/src/intersim2/.svn/pristine/6e/6ee04608f65a1c9be65fcbe3def54f38d00f1bf5.svn-base b/src/intersim2/.svn/pristine/6e/6ee04608f65a1c9be65fcbe3def54f38d00f1bf5.svn-base deleted file mode 100644 index 9df88db..0000000 --- a/src/intersim2/.svn/pristine/6e/6ee04608f65a1c9be65fcbe3def54f38d00f1bf5.svn-base +++ /dev/null @@ -1,518 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include -#include -#include "random_utils.hpp" -#include "traffic.hpp" - -TrafficPattern::TrafficPattern(int nodes) -: _nodes(nodes) -{ - if(nodes <= 0) { - cout << "Error: Traffic patterns require at least one node." << endl; - exit(-1); - } -} - -void TrafficPattern::reset() -{ - -} - -TrafficPattern * TrafficPattern::New(string const & pattern, int nodes, - Configuration const * const config) -{ - string pattern_name; - string param_str; - size_t left = pattern.find_first_of('('); - if(left == string::npos) { - pattern_name = pattern; - } else { - pattern_name = pattern.substr(0, left); - size_t right = pattern.find_last_of(')'); - if(right == string::npos) { - param_str = pattern.substr(left+1); - } else { - param_str = pattern.substr(left+1, right-left-1); - } - } - vector params = tokenize_str(param_str); - - TrafficPattern * result = NULL; - if(pattern_name == "bitcomp") { - result = new BitCompTrafficPattern(nodes); - } else if(pattern_name == "transpose") { - result = new TransposeTrafficPattern(nodes); - } else if(pattern_name == "bitrev") { - result = new BitRevTrafficPattern(nodes); - } else if(pattern_name == "shuffle") { - result = new ShuffleTrafficPattern(nodes); - } else if(pattern_name == "randperm") { - int perm_seed = -1; - if(params.empty()) { - if(config) { - perm_seed = config->GetInt("perm_seed"); - } else { - cout << "Error: Missing parameter for random permutation traffic pattern: " << pattern << endl; - exit(-1); - } - } else { - perm_seed = atoi(params[0].c_str()); - } - result = new RandomPermutationTrafficPattern(nodes, perm_seed); - } else if(pattern_name == "uniform") { - result = new UniformRandomTrafficPattern(nodes); - } else if(pattern_name == "background") { - vector excludes = tokenize_int(params[0]); - result = new UniformBackgroundTrafficPattern(nodes, excludes); - } else if(pattern_name == "diagonal") { - result = new DiagonalTrafficPattern(nodes); - } else if(pattern_name == "asymmetric") { - result = new AsymmetricTrafficPattern(nodes); - } else if(pattern_name == "taper64") { - result = new Taper64TrafficPattern(nodes); - } else if(pattern_name == "bad_dragon") { - bool missing_params = false; - int k = -1; - if(params.size() < 1) { - if(config) { - k = config->GetInt("k"); - } else { - missing_params = true; - } - } else { - k = atoi(params[0].c_str()); - } - int n = -1; - if(params.size() < 2) { - if(config) { - n = config->GetInt("n"); - } else { - missing_params = true; - } - } else { - n = atoi(params[1].c_str()); - } - if(missing_params) { - cout << "Error: Missing parameters for dragonfly bad permutation traffic pattern: " << pattern << endl; - exit(-1); - } - result = new BadPermDFlyTrafficPattern(nodes, k, n); - } else if((pattern_name == "tornado") || (pattern_name == "neighbor") || - (pattern_name == "badperm_yarc")) { - bool missing_params = false; - int k = -1; - if(params.size() < 1) { - if(config) { - k = config->GetInt("k"); - } else { - missing_params = true; - } - } else { - k = atoi(params[0].c_str()); - } - int n = -1; - if(params.size() < 2) { - if(config) { - n = config->GetInt("n"); - } else { - missing_params = true; - } - } else { - n = atoi(params[1].c_str()); - } - int xr = -1; - if(params.size() < 3) { - if(config) { - xr = config->GetInt("xr"); - } else { - missing_params = true; - } - } else { - xr = atoi(params[2].c_str()); - } - if(missing_params) { - cout << "Error: Missing parameters for digit permutation traffic pattern: " << pattern << endl; - exit(-1); - } - if(pattern_name == "tornado") { - result = new TornadoTrafficPattern(nodes, k, n, xr); - } else if(pattern_name == "neighbor") { - result = new NeighborTrafficPattern(nodes, k, n, xr); - } else if(pattern_name == "badperm_yarc") { - result = new BadPermYarcTrafficPattern(nodes, k, n, xr); - } - } else if(pattern_name == "hotspot") { - if(params.empty()) { - params.push_back("-1"); - } - vector hotspots = tokenize_int(params[0]); - for(size_t i = 0; i < hotspots.size(); ++i) { - if(hotspots[i] < 0) { - hotspots[i] = RandomInt(nodes - 1); - } - } - vector rates; - if(params.size() >= 2) { - rates = tokenize_int(params[1]); - rates.resize(hotspots.size(), rates.back()); - } else { - rates.resize(hotspots.size(), 1); - } - result = new HotSpotTrafficPattern(nodes, hotspots, rates); - } else { - cout << "Error: Unknown traffic pattern: " << pattern << endl; - exit(-1); - } - return result; -} - -PermutationTrafficPattern::PermutationTrafficPattern(int nodes) - : TrafficPattern(nodes) -{ - -} - -BitPermutationTrafficPattern::BitPermutationTrafficPattern(int nodes) - : PermutationTrafficPattern(nodes) -{ - if((nodes & -nodes) != nodes) { - cout << "Error: Bit permutation traffic patterns require the number of " - << "nodes to be a power of two." << endl; - exit(-1); - } -} - -BitCompTrafficPattern::BitCompTrafficPattern(int nodes) - : BitPermutationTrafficPattern(nodes) -{ - -} - -int BitCompTrafficPattern::dest(int source) -{ - assert((source >= 0) && (source < _nodes)); - int const mask = _nodes - 1; - return ~source & mask; -} - -TransposeTrafficPattern::TransposeTrafficPattern(int nodes) - : BitPermutationTrafficPattern(nodes), _shift(0) -{ - while(nodes >>= 1) { - ++_shift; - } - if(_shift % 2) { - cout << "Error: Transpose traffic pattern requires the number of nodes to " - << "be an even power of two." << endl; - exit(-1); - } - _shift >>= 1; -} - -int TransposeTrafficPattern::dest(int source) -{ - assert((source >= 0) && (source < _nodes)); - int const mask_lo = (1 << _shift) - 1; - int const mask_hi = mask_lo << _shift; - return (((source >> _shift) & mask_lo) | ((source << _shift) & mask_hi)); -} - -BitRevTrafficPattern::BitRevTrafficPattern(int nodes) - : BitPermutationTrafficPattern(nodes) -{ - -} - -int BitRevTrafficPattern::dest(int source) -{ - assert((source >= 0) && (source < _nodes)); - int result = 0; - for(int n = _nodes; n > 1; n >>= 1) { - result = (result << 1) | (source % 2); - source >>= 1; - } - return result; -} - -ShuffleTrafficPattern::ShuffleTrafficPattern(int nodes) - : BitPermutationTrafficPattern(nodes) -{ - -} - -int ShuffleTrafficPattern::dest(int source) -{ - assert((source >= 0) && (source < _nodes)); - int const shifted = source << 1; - return ((shifted & (_nodes - 1)) | bool(shifted & _nodes)); -} - -DigitPermutationTrafficPattern::DigitPermutationTrafficPattern(int nodes, int k, - int n, int xr) - : PermutationTrafficPattern(nodes), _k(k), _n(n), _xr(xr) -{ - -} - -TornadoTrafficPattern::TornadoTrafficPattern(int nodes, int k, int n, int xr) - : DigitPermutationTrafficPattern(nodes, k, n, xr) -{ - -} - -int TornadoTrafficPattern::dest(int source) -{ - assert((source >= 0) && (source < _nodes)); - - int offset = 1; - int result = 0; - - for(int n = 0; n < _n; ++n) { - result += offset * - (((source / offset) % (_xr * _k) + ((_xr * _k + 1) / 2 - 1)) % (_xr * _k)); - offset *= (_xr * _k); - } - return result; -} - -NeighborTrafficPattern::NeighborTrafficPattern(int nodes, int k, int n, int xr) - : DigitPermutationTrafficPattern(nodes, k, n, xr) -{ - -} - -int NeighborTrafficPattern::dest(int source) -{ - assert((source >= 0) && (source < _nodes)); - - int offset = 1; - int result = 0; - - for(int n = 0; n < _n; ++n) { - result += offset * - (((source / offset) % (_xr * _k) + 1) % (_xr * _k)); - offset *= (_xr * _k); - } - return result; -} - -RandomPermutationTrafficPattern::RandomPermutationTrafficPattern(int nodes, - int seed) - : TrafficPattern(nodes) -{ - _dest.resize(nodes); - randomize(seed); -} - -void RandomPermutationTrafficPattern::randomize(int seed) -{ - unsigned long prev_seed = RandomIntLong( ); - RandomSeed(seed); - - _dest.assign(_nodes, -1); - - for(int i = 0; i < _nodes; ++i) { - int ind = RandomInt(_nodes - 1 - i); - - int j = 0; - int cnt = 0; - while((cnt < ind) || (_dest[j] != -1)) { - if(_dest[j] == -1) { - ++cnt; - } - ++j; - assert(j < _nodes); - } - - _dest[j] = i; - } - - RandomSeed(prev_seed); -} - -int RandomPermutationTrafficPattern::dest(int source) -{ - assert((source >= 0) && (source < _nodes)); - assert((_dest[source] >= 0) && (_dest[source] < _nodes)); - return _dest[source]; -} - -RandomTrafficPattern::RandomTrafficPattern(int nodes) - : TrafficPattern(nodes) -{ - -} - -UniformRandomTrafficPattern::UniformRandomTrafficPattern(int nodes) - : RandomTrafficPattern(nodes) -{ - -} - -int UniformRandomTrafficPattern::dest(int source) -{ - assert((source >= 0) && (source < _nodes)); - return RandomInt(_nodes - 1); -} - -UniformBackgroundTrafficPattern::UniformBackgroundTrafficPattern(int nodes, vector excluded_nodes) - : RandomTrafficPattern(nodes) -{ - for(size_t i = 0; i < excluded_nodes.size(); ++i) { - int const node = excluded_nodes[i]; - assert((node >= 0) && (node < _nodes)); - _excluded.insert(node); - } -} - -int UniformBackgroundTrafficPattern::dest(int source) -{ - assert((source >= 0) && (source < _nodes)); - - int result; - - do { - result = RandomInt(_nodes - 1); - } while(_excluded.count(result) > 0); - - return result; -} - -DiagonalTrafficPattern::DiagonalTrafficPattern(int nodes) - : RandomTrafficPattern(nodes) -{ - -} - -int DiagonalTrafficPattern::dest(int source) -{ - assert((source >= 0) && (source < _nodes)); - return ((RandomInt(2) == 0) ? ((source + 1) % _nodes) : source); -} - -AsymmetricTrafficPattern::AsymmetricTrafficPattern(int nodes) - : RandomTrafficPattern(nodes) -{ - -} - -int AsymmetricTrafficPattern::dest(int source) -{ - assert((source >= 0) && (source < _nodes)); - int const half = _nodes / 2; - return (source % half) + (RandomInt(1) ? half : 0); -} - -Taper64TrafficPattern::Taper64TrafficPattern(int nodes) - : RandomTrafficPattern(nodes) -{ - if(nodes != 64) { - cout << "Error: Tthe Taper64 traffic pattern requires the number of nodes " - << "to be exactly 64." << endl; - exit(-1); - } -} - -int Taper64TrafficPattern::dest(int source) -{ - assert((source >= 0) && (source < _nodes)); - if(RandomInt(1)) { - return ((64 + source + 8 * (RandomInt(2) - 1) + (RandomInt(2) - 1)) % 64); - } else { - return RandomInt(_nodes - 1); - } -} - -BadPermDFlyTrafficPattern::BadPermDFlyTrafficPattern(int nodes, int k, int n) - : DigitPermutationTrafficPattern(nodes, k, n, 1) -{ - -} - -int BadPermDFlyTrafficPattern::dest(int source) -{ - assert((source >= 0) && (source < _nodes)); - - int const grp_size_routers = 2 * _k; - int const grp_size_nodes = grp_size_routers * _k; - - return ((RandomInt(grp_size_nodes - 1) + ((source / grp_size_nodes) + 1) * grp_size_nodes) % _nodes); -} - -BadPermYarcTrafficPattern::BadPermYarcTrafficPattern(int nodes, int k, int n, - int xr) - : DigitPermutationTrafficPattern(nodes, k, n, xr) -{ - -} - -int BadPermYarcTrafficPattern::dest(int source) -{ - assert((source >= 0) && (source < _nodes)); - int const row = source / (_xr * _k); - return RandomInt((_xr * _k) - 1) * (_xr * _k) + row; -} - -HotSpotTrafficPattern::HotSpotTrafficPattern(int nodes, vector hotspots, - vector rates) - : TrafficPattern(nodes), _hotspots(hotspots), _rates(rates), _max_val(-1) -{ - assert(!_hotspots.empty()); - size_t const size = _hotspots.size(); - _rates.resize(size, _rates.empty() ? 1 : _rates.back()); - for(size_t i = 0; i < size; ++i) { - int const hotspot = _hotspots[i]; - assert((hotspot >= 0) && (hotspot < _nodes)); - int const rate = _rates[i]; - assert(rate >= 0); - _max_val += rate; - } -} - -int HotSpotTrafficPattern::dest(int source) -{ - assert((source >= 0) && (source < _nodes)); - - if(_hotspots.size() == 1) { - return _hotspots[0]; - } - - int pct = RandomInt(_max_val); - - for(size_t i = 0; i < (_hotspots.size() - 1); ++i) { - int const limit = _rates[i]; - if(limit > pct) { - return _hotspots[i]; - } else { - pct -= limit; - } - } - assert(_rates.back() > pct); - return _hotspots.back(); -} diff --git a/src/intersim2/.svn/pristine/70/7052ff59571d88c99070cd8d659460b1534cf1b3.svn-base b/src/intersim2/.svn/pristine/70/7052ff59571d88c99070cd8d659460b1534cf1b3.svn-base deleted file mode 100644 index 05382f5..0000000 --- a/src/intersim2/.svn/pristine/70/7052ff59571d88c99070cd8d659460b1534cf1b3.svn-base +++ /dev/null @@ -1,86 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// ---------------------------------------------------------------------- -// -// SeparableAllocator: Separable Allocator Base Class -// -// ---------------------------------------------------------------------- - -#include "separable.hpp" - -#include - -#include "arbiter.hpp" - -SeparableAllocator::SeparableAllocator( Module* parent, const string& name, - int inputs, int outputs, - const string& arb_type ) - : SparseAllocator( parent, name, inputs, outputs ) -{ - - _input_arb.resize(inputs); - - for (int i = 0; i < inputs; ++i) { - ostringstream arb_name("arb_i"); - arb_name << i; - _input_arb[i] = Arbiter::NewArbiter(this, arb_name.str(), arb_type, outputs); - } - - _output_arb.resize(outputs); - - for (int i = 0; i < outputs; ++i) { - ostringstream arb_name("arb_o"); - arb_name << i; - _output_arb[i] = Arbiter::NewArbiter(this, arb_name.str( ), arb_type, inputs); - } - -} - -SeparableAllocator::~SeparableAllocator() { - - for (int i = 0; i < _inputs; ++i) { - delete _input_arb[i]; - } - - for (int i = 0; i < _outputs; ++i) { - delete _output_arb[i]; - } - -} - -void SeparableAllocator::Clear() { - for ( int i = 0 ; i < _inputs ; i++ ) { - if(_input_arb[i]-> _num_reqs) - _input_arb[i]->Clear(); - } - for ( int o = 0; o < _outputs; o++ ) { - if(_output_arb[o]->_num_reqs) - _output_arb[o]->Clear(); - } - SparseAllocator::Clear(); -} diff --git a/src/intersim2/.svn/pristine/72/72bdb07d5ae6b1010a5ae388c45b5fbe2d549f92.svn-base b/src/intersim2/.svn/pristine/72/72bdb07d5ae6b1010a5ae388c45b5fbe2d549f92.svn-base deleted file mode 100644 index 8b1f029..0000000 --- a/src/intersim2/.svn/pristine/72/72bdb07d5ae6b1010a5ae388c45b5fbe2d549f92.svn-base +++ /dev/null @@ -1,75 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// ---------------------------------------------------------------------- -// -// RoundRobin: Round Robin Arbiter -// -// ---------------------------------------------------------------------- - -#ifndef _ROUNDROBIN_HPP_ -#define _ROUNDROBIN_HPP_ - -#include "arbiter.hpp" - -class RoundRobinArbiter : public Arbiter { - - // Priority pointer - int _pointer ; - -public: - - // Constructors - RoundRobinArbiter( Module *parent, const string &name, int size ) ; - - // Print priority matrix to standard output - virtual void PrintState() const ; - - // Update priority matrix based on last aribtration result - virtual void UpdateState() ; - - // Arbitrate amongst requests. Returns winning input and - // updates pointers to metadata when valid pointers are passed - virtual int Arbitrate( int* id = 0, int* pri = 0) ; - - virtual void AddRequest( int input, int id, int pri ) ; - - virtual void Clear(); - - static inline bool Supersedes(int input1, int pri1, int input2, int pri2, int offset, int size) - { - // in a round-robin scheme with the given number of positions and current - // offset, should a request at input1 with priority pri1 supersede a - // request at input2 with priority pri2? - return ((pri1 > pri2) || - ((pri1 == pri2) && - (((input1 - offset + size) % size) < ((input2 - offset + size) % size)))); - } - -} ; - -#endif diff --git a/src/intersim2/.svn/pristine/75/75fab6aaa53ec97ae2f9769ab873fea5abf9516b.svn-base b/src/intersim2/.svn/pristine/75/75fab6aaa53ec97ae2f9769ab873fea5abf9516b.svn-base deleted file mode 100644 index cef5539..0000000 --- a/src/intersim2/.svn/pristine/75/75fab6aaa53ec97ae2f9769ab873fea5abf9516b.svn-base +++ /dev/null @@ -1,83 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include - -#include "globals.hpp" -#include "booksim.hpp" -#include "buffer.hpp" - -Buffer::Buffer( const Configuration& config, int outputs, - Module *parent, const string& name ) : -Module( parent, name ), _occupancy(0) -{ - int num_vcs = config.GetInt( "num_vcs" ); - - _size = config.GetInt("buf_size"); - if(_size < 0) { - _size = num_vcs * config.GetInt( "vc_buf_size" ); - }; - - _vc.resize(num_vcs); - - for(int i = 0; i < num_vcs; ++i) { - ostringstream vc_name; - vc_name << "vc_" << i; - _vc[i] = new VC(config, outputs, this, vc_name.str( ) ); - } - -#ifdef TRACK_BUFFERS - int classes = config.GetInt("classes"); - _class_occupancy.resize(classes, 0); -#endif -} - -Buffer::~Buffer() -{ - for(vector::iterator i = _vc.begin(); i != _vc.end(); ++i) { - delete *i; - } -} - -void Buffer::AddFlit( int vc, Flit *f ) -{ - if(_occupancy >= _size) { - Error("Flit buffer overflow."); - } - ++_occupancy; - _vc[vc]->AddFlit(f); -#ifdef TRACK_BUFFERS - ++_class_occupancy[f->cl]; -#endif -} - -void Buffer::Display( ostream & os ) const -{ - for(vector::const_iterator i = _vc.begin(); i != _vc.end(); ++i) { - (*i)->Display(os); - } -} diff --git a/src/intersim2/.svn/pristine/76/7692129db779b4e8cd14cf7ab6fac567093153b2.svn-base b/src/intersim2/.svn/pristine/76/7692129db779b4e8cd14cf7ab6fac567093153b2.svn-base deleted file mode 100644 index 12898c2..0000000 --- a/src/intersim2/.svn/pristine/76/7692129db779b4e8cd14cf7ab6fac567093153b2.svn-base +++ /dev/null @@ -1,52 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// ---------------------------------------------------------------------- -// -// SeparableInputFirstAllocator: Separable Input-First Allocator -// -// ---------------------------------------------------------------------- - -#ifndef _SEPARABLE_INPUT_FIRST_HPP_ -#define _SEPARABLE_INPUT_FIRST_HPP_ - -#include - -#include "separable.hpp" - -class SeparableInputFirstAllocator : public SeparableAllocator { - -public: - - SeparableInputFirstAllocator( Module* parent, const string& name, int inputs, - int outputs, const string& arb_type ) ; - - virtual void Allocate() ; - -} ; - -#endif diff --git a/src/intersim2/.svn/pristine/77/77d1aaef881a98fa412061c4daa8137d12ee6f3f.svn-base b/src/intersim2/.svn/pristine/77/77d1aaef881a98fa412061c4daa8137d12ee6f3f.svn-base deleted file mode 100644 index 3622918..0000000 --- a/src/intersim2/.svn/pristine/77/77d1aaef881a98fa412061c4daa8137d12ee6f3f.svn-base +++ /dev/null @@ -1,158 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _ALLOCATOR_HPP_ -#define _ALLOCATOR_HPP_ - -#include -#include -#include -#include - -#include "module.hpp" -#include "config_utils.hpp" - -class Allocator : public Module { -protected: - const int _inputs; - const int _outputs; - - bool _dirty; - - vector _inmatch; - vector _outmatch; - -public: - - struct sRequest { - int port; - int label; - int in_pri; - int out_pri; - }; - - Allocator( Module *parent, const string& name, - int inputs, int outputs ); - - virtual void Clear( ); - - virtual int ReadRequest( int in, int out ) const = 0; - virtual bool ReadRequest( sRequest &req, int in, int out ) const = 0; - - virtual void AddRequest( int in, int out, int label = 1, - int in_pri = 0, int out_pri = 0 ); - virtual void RemoveRequest( int in, int out, int label = 1 ) = 0; - - virtual void Allocate( ) = 0; - - int OutputAssigned( int in ) const; - int InputAssigned( int out ) const; - - virtual bool OutputHasRequests( int out ) const = 0; - virtual bool InputHasRequests( int in ) const = 0; - - virtual int NumOutputRequests( int out ) const = 0; - virtual int NumInputRequests( int in ) const = 0; - - virtual void PrintRequests( ostream * os = NULL ) const = 0; - void PrintGrants( ostream * os = NULL ) const; - - static Allocator *NewAllocator( Module *parent, const string& name, - const string &alloc_type, - int inputs, int outputs, - Configuration const * const config = NULL ); -}; - -//================================================== -// A dense allocator stores the entire request -// matrix. -//================================================== - -class DenseAllocator : public Allocator { -protected: - vector > _request; - -public: - DenseAllocator( Module *parent, const string& name, - int inputs, int outputs ); - - void Clear( ); - - int ReadRequest( int in, int out ) const; - bool ReadRequest( sRequest &req, int in, int out ) const; - - void AddRequest( int in, int out, int label = 1, - int in_pri = 0, int out_pri = 0 ); - void RemoveRequest( int in, int out, int label = 1 ); - - bool OutputHasRequests( int out ) const; - bool InputHasRequests( int in ) const; - - int NumOutputRequests( int out ) const; - int NumInputRequests( int in ) const; - - void PrintRequests( ostream * os = NULL ) const; - -}; - -//================================================== -// A sparse allocator only stores the requests -// (allows for a more efficient implementation). -//================================================== - -class SparseAllocator : public Allocator { -protected: - set _in_occ; - set _out_occ; - - vector > _in_req; - vector > _out_req; - -public: - SparseAllocator( Module *parent, const string& name, - int inputs, int outputs ); - - void Clear( ); - - int ReadRequest( int in, int out ) const; - bool ReadRequest( sRequest &req, int in, int out ) const; - - void AddRequest( int in, int out, int label = 1, - int in_pri = 0, int out_pri = 0 ); - void RemoveRequest( int in, int out, int label = 1 ); - - bool OutputHasRequests( int out ) const; - bool InputHasRequests( int in ) const; - - int NumOutputRequests( int out ) const; - int NumInputRequests( int in ) const; - - void PrintRequests( ostream * os = NULL ) const; - -}; - -#endif diff --git a/src/intersim2/.svn/pristine/78/78c651a126efa354bfbf06841fb91bf72d970003.svn-base b/src/intersim2/.svn/pristine/78/78c651a126efa354bfbf06841fb91bf72d970003.svn-base deleted file mode 100644 index 1295ab7..0000000 --- a/src/intersim2/.svn/pristine/78/78c651a126efa354bfbf06841fb91bf72d970003.svn-base +++ /dev/null @@ -1,57 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _WAVEFRONT_HPP_ -#define _WAVEFRONT_HPP_ - -#include - -#include "allocator.hpp" - -class Wavefront : public DenseAllocator { - -private: - int _last_in; - int _last_out; - set > _priorities; - bool _skip_diags; - -protected: - int _square; - int _pri; - int _num_requests; - -public: - Wavefront( Module *parent, const string& name, - int inputs, int outputs, bool skip_diags = false ); - - virtual void AddRequest( int in, int out, int label = 1, - int in_pri = 0, int out_pri = 0 ); - virtual void Allocate( ); -}; - -#endif diff --git a/src/intersim2/.svn/pristine/78/78db9a8009e2eeebfa8c1d67e38108237e7cf1b3.svn-base b/src/intersim2/.svn/pristine/78/78db9a8009e2eeebfa8c1d67e38108237e7cf1b3.svn-base deleted file mode 100644 index f8b6b4d..0000000 --- a/src/intersim2/.svn/pristine/78/78db9a8009e2eeebfa8c1d67e38108237e7cf1b3.svn-base +++ /dev/null @@ -1,72 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -//////////////////////////////////////////////////////////////////////// -// -// Tree4: Network with 64 Terminal Nodes arranged in a tree topology -// with 4 routers at the root of the tree -// -//////////////////////////////////////////////////////////////////////// -// -// RCS Information: -// $Author: jbalfour $ -// $Date: 2007/06/26 22:49:23 $ -// $Id$ -// -//////////////////////////////////////////////////////////////////////// - -#ifndef _TREE4_HPP_ -#define _TREE4_HPP_ -#include -#include "network.hpp" - -class Tree4 : public Network { - - int _k; - int _n; - - int _channelWidth; - - void _ComputeSize( const Configuration& config ); - void _BuildNet( const Configuration& config ); - - - Router*& _Router( int height, int pos ); - - int _WireLatency( int height1, int pos1, int height2, int pos2 ); - -public: - - Tree4( const Configuration& config, const string & name ); - static void RegisterRoutingFunctions() ; - - static int HeightFromID( int id ); - static int PosFromID( int id ); - static int SpeedUp( int height ); -}; - -#endif diff --git a/src/intersim2/.svn/pristine/7a/7a54a566c36bec4672c4c004940eb007ffb11730.svn-base b/src/intersim2/.svn/pristine/7a/7a54a566c36bec4672c4c004940eb007ffb11730.svn-base deleted file mode 100644 index 108d139..0000000 --- a/src/intersim2/.svn/pristine/7a/7a54a566c36bec4672c4c004940eb007ffb11730.svn-base +++ /dev/null @@ -1,289 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -//////////////////////////////////////////////////////////////////////// -// -// Tree4: Network with 64 Terminal Nodes arranged in a tree topology -// with 4 routers at the root of the tree -// -// Level 0 : 4 8 x 8 Routers (8 Descending Links per Router) -// Level 1 : 8 8 x 8 Routers (4 Descending Links per Router) -// Level 2 : 16 6 x 6 Routers (4 Descending Links per Router) -// Level 3 : 64 Terminal Nodes -// -//////////////////////////////////////////////////////////////////////// -// -// RCS Information: -// $Author: jbalfour $ -// $Date: 2007/06/26 22:49:23 $ -// $Id$ -// -//////////////////////////////////////////////////////////////////////// - -#include "booksim.hpp" -#include -#include -#include - -#include "tree4.hpp" -#include "misc_utils.hpp" - -Tree4::Tree4( const Configuration& config, const string & name ) -: Network ( config, name ) -{ - _ComputeSize( config ); - _Alloc( ); - _BuildNet( config ); -} - -void Tree4::_ComputeSize( const Configuration& config ) -{ - int h; - - _k = config.GetInt( "k" ); - assert(_k == 4); - _n = config.GetInt( "n" ); - assert(_n == 3); - - gK = _k; gN = _n; - - _nodes = powi( _k, _n ); - - _size = 0; - for ( h = 0; h < _n; ++h ) - _size += (4 >> h) * powi( _k, h ); - - _channels = 2 // Two Channels per Connection - * ( 2 * powi( _k, 1) ) // Number of Middle Routers - * ( 2 * _k ); // Connectivity of Middle Routers -} - -void Tree4::RegisterRoutingFunctions(){ - -} - -void Tree4::_BuildNet( const Configuration& config ) -{ - - // - // Allocate Routers - // - ostringstream name; - int h, pos, nPos, degree, id; - - for ( h = 0; h < _n; h++ ) { - nPos = (4 >> h) * powi( _k, h ); - for ( pos = 0; pos < nPos; ++pos) { - if ( h < _n-1 ) - degree = 8; - else - degree = 6; - - name.str(""); - name << "router_" << h << "_" << pos; - id = h * powi( _k, _n-1 ) + pos; - Router * r = Router::NewRouter( config, this, name.str( ), - id, degree, degree ); - _Router( h, pos ) = r; - _timed_modules.push_back(r); - } - } - - // - // Connect Channels to Routers - // - int pp, pc; - // - // Connection Rule: Output Ports 0:3 Move DOWN Network - // Output Ports 4:7 Move UP Network - // - - // Injection & Ejection Channels - nPos = powi( _k, _n - 1 ); - for ( pos = 0 ; pos < nPos ; ++pos ) { - for ( int port = 0 ; port < _k ; ++port ) { - - _Router( _n-1, pos)->AddInputChannel( _inject[_k*pos+port], - _inject_cred[_k*pos+port]); - - - _inject[_k*pos+port]->SetLatency( 1 ); - _inject_cred[_k*pos+port]->SetLatency( 1 ); - - _Router( _n-1, pos)->AddOutputChannel( _eject[_k*pos+port], - _eject_cred[_k*pos+port]); - - _eject[_k*pos+port]->SetLatency( 1 ); - _eject_cred[_k*pos+port]->SetLatency( 1 ); - - } - } - - // Connections between h = 1 and h = 2 Levels - int c = 0; - nPos = 2 * powi( _k, 1 ); - for ( pos = 0; pos < nPos; ++pos ) { - for ( int port = 0; port < _k; ++port ) { - - pp = pos; - pc = _k * ( pos / 2 ) + port; - - // cout << "connecting (1,"< (2,"<AddOutputChannel( _chan[c], _chan_cred[c] ); - _Router( 2, pc)->AddInputChannel( _chan[c], _chan_cred[c] ); - - //_chan[c]->SetLatency( L ); - //_chan_cred[c]->SetLatency( L ); - - _chan[c]->SetLatency( 1 ); - _chan_cred[c]->SetLatency( 1 ); - - c++; - - _Router(1, pp)->AddInputChannel( _chan[c], _chan_cred[c] ); - _Router(2, pc)->AddOutputChannel( _chan[c], _chan_cred[c] ); - - //_chan[c]->SetLatency( L ); - //_chan_cred[c]->SetLatency( L ); - _chan[c]->SetLatency( 1 ); - _chan_cred[c]->SetLatency( 1 ); - - c++; - } - } - - // Connections between h = 0 and h = 1 Levels - nPos = 4 * powi( _k, 0 ); - for ( pos = 0; pos < nPos; ++pos ) { - for ( int port = 0; port < 2 * _k; ++port ) { - pp = pos; - pc = port; - - // cout << "connecting (0,"< (1,"<AddOutputChannel( _chan[c], _chan_cred[c] ); - _Router(1, pc)->AddInputChannel( _chan[c], _chan_cred[c] ); - - // _chan[c]->SetLatency( L ); - //_chan_cred[c]->SetLatency( L ); - _chan[c]->SetLatency( 1 ); - _chan_cred[c]->SetLatency( 1 ); - - c++; - - _Router(0, pp)->AddInputChannel( _chan[c], _chan_cred[c] ); - _Router(1, pc)->AddOutputChannel( _chan[c], _chan_cred[c] ); - - // _chan[c]->SetLatency( L ); - // _chan_cred[c]->SetLatency( L ); - _chan[c]->SetLatency( 1 ); - _chan_cred[c]->SetLatency( 1 ); - c++; - } - } - - // cout << "Used " << c << " of " << _channels << " channels" << endl; - -} - -Router*& Tree4::_Router( int height, int pos ) -{ - assert( height < _n ); - assert( pos < (4 >> height) * powi( _k, height) ); - - int i = 0; - for ( int h = 0; h < height; ++h ) - i += (4 >> h) * powi( _k, h ); - return _routers[i+pos]; - -} - -int Tree4::_WireLatency( int height1, int pos1, int height2, int pos2 ) -{ - int heightChild, heightParent, posChild, posParent; - - int L; - - if (height1 < height2) { - heightChild = height2; - posChild = pos2; - heightParent = height1; - posParent = pos1; - } else { - heightChild = height1; - posChild = pos1; - heightParent = height2; - posParent = pos2; - } - - int _length_d2_d1 = 2 ; - int _length_d1_d0_0 = 2 ; - int _length_d1_d0_1 = 2 ; - int _length_d1_d0_2 = 6 ; - int _length_d1_d0_3 = 6 ; - - assert( heightChild == heightParent+1 ); - - // We must decrement the delays by one to account for how the - // simulator interprets the specified delay (with 0 indicating one - // cycle of delay). - - if ( heightChild == 2 ) - L = _length_d2_d1; - else { - if ( posChild == 0 || posChild == 6 ) - switch ( posParent ) { - case 0: L =_length_d1_d0_0; break; - case 1: L =_length_d1_d0_1; break; - case 2: L =_length_d1_d0_2; break; - case 3: L =_length_d1_d0_3; break; - } - if ( posChild == 1 || posChild == 7 ) - switch ( posParent ) { - case 0: L =_length_d1_d0_3; break; - case 1: L =_length_d1_d0_2; break; - case 2: L =_length_d1_d0_1; break; - case 3: L =_length_d1_d0_0; break; - } - if ( posChild == 2 || posChild == 4 ) - switch ( posParent ) { - case 0: L = _length_d1_d0_0; break; - case 1: L = _length_d1_d0_1; break; - case 2: L = _length_d1_d0_2; break; - case 3: L = _length_d1_d0_3; break; - } - if ( posChild == 3|| posChild == 5 ) - switch ( posParent ) { - case 0: L =_length_d1_d0_3; break; - case 1: L =_length_d1_d0_2; break; - case 2: L =_length_d1_d0_1; break; - case 3: L =_length_d1_d0_0; break; - } - } - return L; -} diff --git a/src/intersim2/.svn/pristine/7b/7b0efd00926de5ec0c6efc86d8ddfbba35da0f82.svn-base b/src/intersim2/.svn/pristine/7b/7b0efd00926de5ec0c6efc86d8ddfbba35da0f82.svn-base deleted file mode 100644 index 5481d1e..0000000 --- a/src/intersim2/.svn/pristine/7b/7b0efd00926de5ec0c6efc86d8ddfbba35da0f82.svn-base +++ /dev/null @@ -1,44 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _TIMED_MODULE_HPP_ -#define _TIMED_MODULE_HPP_ - -#include "module.hpp" - -class TimedModule : public Module { - -public: - TimedModule(Module * parent, string const & name) : Module(parent, name) {} - virtual ~TimedModule() {} - - virtual void ReadInputs() = 0; - virtual void Evaluate() = 0; - virtual void WriteOutputs() = 0; -}; - -#endif diff --git a/src/intersim2/.svn/pristine/7b/7b445ae8a3f265094d5af4956c88457b77c18fa5.svn-base b/src/intersim2/.svn/pristine/7b/7b445ae8a3f265094d5af4956c88457b77c18fa5.svn-base deleted file mode 100644 index 46ba99b..0000000 --- a/src/intersim2/.svn/pristine/7b/7b445ae8a3f265094d5af4956c88457b77c18fa5.svn-base +++ /dev/null @@ -1,220 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include -#include -#include - -#include "packet_reply_info.hpp" -#include "random_utils.hpp" -#include "batchtrafficmanager.hpp" - -BatchTrafficManager::BatchTrafficManager( const Configuration &config, - const vector & net ) -: TrafficManager(config, net), _last_id(-1), _last_pid(-1), - _overall_min_batch_time(0), _overall_avg_batch_time(0), - _overall_max_batch_time(0) -{ - - _max_outstanding = config.GetInt ("max_outstanding_requests"); - - _batch_size = config.GetInt( "batch_size" ); - _batch_count = config.GetInt( "batch_count" ); - - _batch_time = new Stats( this, "batch_time", 1.0, 1000 ); - _stats["batch_time"] = _batch_time; - - string sent_packets_out_file = config.GetStr( "sent_packets_out" ); - if(sent_packets_out_file == "") { - _sent_packets_out = NULL; - } else { - _sent_packets_out = new ofstream(sent_packets_out_file.c_str()); - } -} - -BatchTrafficManager::~BatchTrafficManager( ) -{ - delete _batch_time; - if(_sent_packets_out) delete _sent_packets_out; -} - -void BatchTrafficManager::_RetireFlit( Flit *f, int dest ) -{ - _last_id = f->id; - _last_pid = f->pid; - TrafficManager::_RetireFlit(f, dest); -} - -int BatchTrafficManager::_IssuePacket( int source, int cl ) -{ - int result = 0; - if(_use_read_write[cl]) { //read write packets - //check queue for waiting replies. - //check to make sure it is on time yet - if(!_repliesPending[source].empty()) { - if(_repliesPending[source].front()->time <= _time) { - result = -1; - } - } else { - if((_packet_seq_no[source] < _batch_size) && - ((_max_outstanding <= 0) || - (_requestsOutstanding[source] < _max_outstanding))) { - - //coin toss to determine request type. - result = (RandomFloat() < 0.5) ? 2 : 1; - - _requestsOutstanding[source]++; - } - } - } else { //normal - if((_packet_seq_no[source] < _batch_size) && - ((_max_outstanding <= 0) || - (_requestsOutstanding[source] < _max_outstanding))) { - result = _GetNextPacketSize(cl); - _requestsOutstanding[source]++; - } - } - if(result != 0) { - _packet_seq_no[source]++; - } - return result; -} - -void BatchTrafficManager::_ClearStats( ) -{ - TrafficManager::_ClearStats(); - _batch_time->Clear( ); -} - -bool BatchTrafficManager::_SingleSim( ) -{ - int batch_index = 0; - while(batch_index < _batch_count) { - _packet_seq_no.assign(_nodes, 0); - _last_id = -1; - _last_pid = -1; - _sim_state = running; - int start_time = _time; - bool batch_complete; - cout << "Sending batch " << batch_index + 1 << " (" << _batch_size << " packets)..." << endl; - do { - _Step(); - batch_complete = true; - for(int i = 0; i < _nodes; ++i) { - if(_packet_seq_no[i] < _batch_size) { - batch_complete = false; - break; - } - } - if(_sent_packets_out) { - *_sent_packets_out << _packet_seq_no << endl; - } - } while(!batch_complete); - cout << "Batch injected. Time used is " << _time - start_time << " cycles." << endl; - - int sent_time = _time; - cout << "Waiting for batch to complete..." << endl; - - int empty_steps = 0; - - bool packets_left = false; - for(int c = 0; c < _classes; ++c) { - packets_left |= !_total_in_flight_flits[c].empty(); - } - - while( packets_left ) { - _Step( ); - - ++empty_steps; - - if ( empty_steps % 1000 == 0 ) { - _DisplayRemaining( ); - cout << "."; - } - - packets_left = false; - for(int c = 0; c < _classes; ++c) { - packets_left |= !_total_in_flight_flits[c].empty(); - } - } - cout << endl; - cout << "Batch received. Time used is " << _time - sent_time << " cycles." << endl - << "Last packet was " << _last_pid << ", last flit was " << _last_id << "." << endl; - - _batch_time->AddSample(_time - start_time); - - cout << _sim_state << endl; - - UpdateStats(); - DisplayStats(); - - ++batch_index; - } - _sim_state = draining; - _drain_time = _time; - return 1; -} - -void BatchTrafficManager::_UpdateOverallStats() { - TrafficManager::_UpdateOverallStats(); - _overall_min_batch_time += _batch_time->Min(); - _overall_avg_batch_time += _batch_time->Average(); - _overall_max_batch_time += _batch_time->Max(); -} - -string BatchTrafficManager::_OverallStatsCSV(int c) const -{ - ostringstream os; - os << TrafficManager::_OverallStatsCSV(c) << ',' - << _overall_min_batch_time / (double)_total_sims << ',' - << _overall_avg_batch_time / (double)_total_sims << ',' - << _overall_max_batch_time / (double)_total_sims; - return os.str(); -} - -void BatchTrafficManager::WriteStats(ostream & os) const -{ - TrafficManager::WriteStats(os); - os << "batch_time = " << _batch_time->Average() << ";" << endl; -} - -void BatchTrafficManager::DisplayStats(ostream & os) const { - TrafficManager::DisplayStats(); - os << "Minimum batch duration = " << _batch_time->Min() << endl; - os << "Average batch duration = " << _batch_time->Average() << endl; - os << "Maximum batch duration = " << _batch_time->Max() << endl; -} - -void BatchTrafficManager::DisplayOverallStats(ostream & os) const { - TrafficManager::DisplayOverallStats(os); - os << "Overall min batch duration = " << _overall_min_batch_time / (double)_total_sims - << " (" << _total_sims << " samples)" << endl - << "Overall min batch duration = " << _overall_avg_batch_time / (double)_total_sims - << " (" << _total_sims << " samples)" << endl - << "Overall min batch duration = " << _overall_max_batch_time / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; -} diff --git a/src/intersim2/.svn/pristine/7c/7c4fde53686972fa2db885e0743742173afd1bb9.svn-base b/src/intersim2/.svn/pristine/7c/7c4fde53686972fa2db885e0743742173afd1bb9.svn-base deleted file mode 100644 index f7f84ac..0000000 --- a/src/intersim2/.svn/pristine/7c/7c4fde53686972fa2db885e0743742173afd1bb9.svn-base +++ /dev/null @@ -1,57 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "packet_reply_info.hpp" - -stack PacketReplyInfo::_all; -stack PacketReplyInfo::_free; - -PacketReplyInfo * PacketReplyInfo::New() -{ - PacketReplyInfo * pr; - if(_free.empty()) { - pr = new PacketReplyInfo(); - _all.push(pr); - } else { - pr = _free.top(); - _free.pop(); - } - return pr; -} - -void PacketReplyInfo::Free() -{ - _free.push(this); -} - -void PacketReplyInfo::FreeAll() -{ - while(!_all.empty()) { - delete _all.top(); - _all.pop(); - } -} diff --git a/src/intersim2/.svn/pristine/7f/7fdf02535ae5ba5ca9a2b15879dbcdd928095585.svn-base b/src/intersim2/.svn/pristine/7f/7fdf02535ae5ba5ca9a2b15879dbcdd928095585.svn-base deleted file mode 100644 index b3972d2..0000000 --- a/src/intersim2/.svn/pristine/7f/7fdf02535ae5ba5ca9a2b15879dbcdd928095585.svn-base +++ /dev/null @@ -1,202 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _ROUTER_HPP_ -#define _ROUTER_HPP_ - -#include -#include - -#include "timed_module.hpp" -#include "flit.hpp" -#include "credit.hpp" -#include "flitchannel.hpp" -#include "channel.hpp" -#include "config_utils.hpp" - -typedef Channel CreditChannel; - -class Router : public TimedModule { - -protected: - - static int const STALL_BUFFER_BUSY; - static int const STALL_BUFFER_CONFLICT; - static int const STALL_BUFFER_FULL; - static int const STALL_BUFFER_RESERVED; - static int const STALL_CROSSBAR_CONFLICT; - - int _id; - - int _inputs; - int _outputs; - - int _classes; - - int _input_speedup; - int _output_speedup; - - double _internal_speedup; - double _partial_internal_cycles; - - int _crossbar_delay; - int _credit_delay; - - vector _input_channels; - vector _input_credits; - vector _output_channels; - vector _output_credits; - vector _channel_faults; - -#ifdef TRACK_FLOWS - vector > _received_flits; - vector > _stored_flits; - vector > _sent_flits; - vector > _outstanding_credits; - vector > _active_packets; -#endif - -#ifdef TRACK_STALLS - vector _buffer_busy_stalls; - vector _buffer_conflict_stalls; - vector _buffer_full_stalls; - vector _buffer_reserved_stalls; - vector _crossbar_conflict_stalls; -#endif - - virtual void _InternalStep() = 0; - -public: - Router( const Configuration& config, - Module *parent, const string & name, int id, - int inputs, int outputs ); - - static Router *NewRouter( const Configuration& config, - Module *parent, const string & name, int id, - int inputs, int outputs ); - - virtual void AddInputChannel( FlitChannel *channel, CreditChannel *backchannel ); - virtual void AddOutputChannel( FlitChannel *channel, CreditChannel *backchannel ); - - inline FlitChannel * GetInputChannel( int input ) const { - assert((input >= 0) && (input < _inputs)); - return _input_channels[input]; - } - inline FlitChannel * GetOutputChannel( int output ) const { - assert((output >= 0) && (output < _outputs)); - return _output_channels[output]; - } - - virtual void ReadInputs( ) = 0; - virtual void Evaluate( ); - virtual void WriteOutputs( ) = 0; - - void OutChannelFault( int c, bool fault = true ); - bool IsFaultyOutput( int c ) const; - - inline int GetID( ) const {return _id;} - - - virtual int GetUsedCredit(int o) const = 0; - virtual int GetBufferOccupancy(int i) const = 0; - -#ifdef TRACK_BUFFERS - virtual int GetUsedCreditForClass(int output, int cl) const = 0; - virtual int GetBufferOccupancyForClass(int input, int cl) const = 0; -#endif - -#ifdef TRACK_FLOWS - inline vector const & GetReceivedFlits(int c) const { - assert((c >= 0) && (c < _classes)); - return _received_flits[c]; - } - inline vector const & GetStoredFlits(int c) const { - assert((c >= 0) && (c < _classes)); - return _stored_flits[c]; - } - inline vector const & GetSentFlits(int c) const { - assert((c >= 0) && (c < _classes)); - return _sent_flits[c]; - } - inline vector const & GetOutstandingCredits(int c) const { - assert((c >= 0) && (c < _classes)); - return _outstanding_credits[c]; - } - - inline vector const & GetActivePackets(int c) const { - assert((c >= 0) && (c < _classes)); - return _active_packets[c]; - } - - inline void ResetFlowStats(int c) { - assert((c >= 0) && (c < _classes)); - _received_flits[c].assign(_received_flits[c].size(), 0); - _sent_flits[c].assign(_sent_flits[c].size(), 0); - } -#endif - - virtual vector UsedCredits() const = 0; - virtual vector FreeCredits() const = 0; - virtual vector MaxCredits() const = 0; - -#ifdef TRACK_STALLS - inline int GetBufferBusyStalls(int c) const { - assert((c >= 0) && (c < _classes)); - return _buffer_busy_stalls[c]; - } - inline int GetBufferConflictStalls(int c) const { - assert((c >= 0) && (c < _classes)); - return _buffer_conflict_stalls[c]; - } - inline int GetBufferFullStalls(int c) const { - assert((c >= 0) && (c < _classes)); - return _buffer_full_stalls[c]; - } - inline int GetBufferReservedStalls(int c) const { - assert((c >= 0) && (c < _classes)); - return _buffer_reserved_stalls[c]; - } - inline int GetCrossbarConflictStalls(int c) const { - assert((c >= 0) && (c < _classes)); - return _crossbar_conflict_stalls[c]; - } - - inline void ResetStallStats(int c) { - assert((c >= 0) && (c < _classes)); - _buffer_busy_stalls[c] = 0; - _buffer_conflict_stalls[c] = 0; - _buffer_full_stalls[c] = 0; - _buffer_reserved_stalls[c] = 0; - _crossbar_conflict_stalls[c] = 0; - } -#endif - - inline int NumInputs() const {return _inputs;} - inline int NumOutputs() const {return _outputs;} -}; - -#endif diff --git a/src/intersim2/.svn/pristine/82/829eb51edd8ef3cc3c06778a3e3a379f352728e1.svn-base b/src/intersim2/.svn/pristine/82/829eb51edd8ef3cc3c06778a3e3a379f352728e1.svn-base deleted file mode 100644 index 89c5e21..0000000 --- a/src/intersim2/.svn/pristine/82/829eb51edd8ef3cc3c06778a3e3a379f352728e1.svn-base +++ /dev/null @@ -1,254 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "booksim.hpp" -#include - -#include "selalloc.hpp" -#include "random_utils.hpp" - -//#define DEBUG_SELALLOC - -SelAlloc::SelAlloc( Module *parent, const string& name, - int inputs, int outputs, int iters ) : - SparseAllocator( parent, name, inputs, outputs ) -{ - _iter = iters; - - _gptrs.resize(outputs, 0); - _aptrs.resize(inputs, 0); - _outmask.resize(outputs, 0); -} - -void SelAlloc::Allocate( ) -{ - int input; - int output; - - int input_offset; - int output_offset; - - map::iterator p; - set::iterator outer_iter; - bool wrapped; - - int max_index; - int max_pri; - - vector grants(_outputs, -1); - - for ( int iter = 0; iter < _iter; ++iter ) { - // Grant phase - - for( outer_iter = _out_occ.begin( ); - outer_iter != _out_occ.end( ); ++outer_iter ) { - output = *outer_iter; - - // Skip loop if there are no requests - // or the output is already matched or - // the output is masked - if ( ( _out_req[output].empty( ) ) || - ( _outmatch[output] != -1 ) || - ( _outmask[output] != 0 ) ) { - continue; - } - - // A round-robin arbiter between input requests - input_offset = _gptrs[output]; - - p = _out_req[output].begin( ); - while( ( p != _out_req[output].end( ) ) && - ( p->second.port < input_offset ) ) { - p++; - } - - max_index = -1; - max_pri = 0; - - wrapped = false; - while( (!wrapped) || - ( ( p != _out_req[output].end() ) && - ( p->second.port < input_offset ) ) ) { - if ( p == _out_req[output].end( ) ) { - if ( wrapped ) { break; } - // p is valid here because empty lists - // are skipped (above) - p = _out_req[output].begin( ); - wrapped = true; - } - - input = p->second.port; - - // we know the output is free (above) and - // if the input is free, check if request is the - // highest priority so far - if ( ( _inmatch[input] == -1 ) && - ( ( p->second.out_pri > max_pri ) || ( max_index == -1 ) ) ) { - max_pri = p->second.out_pri; - max_index = input; - } - - p++; - } - - if ( max_index != -1 ) { // grant - grants[output] = max_index; - } - } - -#ifdef DEBUG_SELALLOC - cout << "grants: "; - for ( int i = 0; i < _outputs; ++i ) { - cout << grants[i] << " "; - } - cout << endl; - - cout << "aptrs: "; - for ( int i = 0; i < _inputs; ++i ) { - cout << _aptrs[i] << " "; - } - cout << endl; -#endif - - // Accept phase - - for ( outer_iter = _in_occ.begin( ); - outer_iter != _in_occ.end( ); ++outer_iter ) { - input = *outer_iter; - - if ( _in_req[input].empty( ) ) { - continue; - } - - // A round-robin arbiter between output grants - output_offset = _aptrs[input]; - - p = _in_req[input].begin( ); - while( ( p != _in_req[input].end( ) ) && - ( p->second.port < output_offset ) ) { - p++; - } - - max_index = -1; - max_pri = 0; - - wrapped = false; - while( (!wrapped) || - ( ( p != _in_req[input].end() ) && - ( p->second.port < output_offset ) ) ) { - if ( p == _in_req[input].end( ) ) { - if ( wrapped ) { break; } - // p is valid here because empty lists - // are skipped (above) - p = _in_req[input].begin( ); - wrapped = true; - } - - output = p->second.port; - - // we know the output is free (above) and - // if the input is free, check if the highest - // priroity - if ( ( grants[output] == input ) && - ( !_out_req[output].empty( ) ) && - ( ( p->second.in_pri > max_pri ) || ( max_index == -1 ) ) ) { - max_pri = p->second.in_pri; - max_index = output; - } - - p++; - } - - if ( max_index != -1 ) { - // Accept - output = max_index; - - _inmatch[input] = output; - _outmatch[output] = input; - - // Only update pointers if accepted during the 1st iteration - if ( iter == 0 ) { - _gptrs[output] = ( input + 1 ) % _inputs; - _aptrs[input] = ( output + 1 ) % _outputs; - } - } - } - } - -#ifdef DEBUG_SELALLOC - cout << "input match: "; - for ( int i = 0; i < _inputs; ++i ) { - cout << _inmatch[i] << " "; - } - cout << endl; - - cout << "output match: "; - for ( int j = 0; j < _outputs; ++j ) { - cout << _outmatch[j] << " "; - } - cout << endl; -#endif -} - -void SelAlloc::MaskOutput( int out, int mask ) -{ - assert( ( out >= 0 ) && ( out < _outputs ) ); - _outmask[out] = mask; -} - -void SelAlloc::PrintRequests( ostream * os ) const -{ - map::const_iterator iter; - - if(!os) os = &cout; - - *os << "Input requests = [ "; - for ( int input = 0; input < _inputs; ++input ) { - *os << input << " -> [ "; - for ( iter = _in_req[input].begin( ); - iter != _in_req[input].end( ); iter++ ) { - *os << iter->second.port << " "; - } - *os << "] "; - } - *os << "], output requests = [ "; - for ( int output = 0; output < _outputs; ++output ) { - *os << output << " -> "; - if ( _outmask[output] == 0 ) { - *os << "[ "; - for ( iter = _out_req[output].begin( ); - iter != _out_req[output].end( ); iter++ ) { - *os << iter->second.port << " "; - } - *os << "] "; - } else { - *os << "masked "; - } - } - *os << "]." << endl; -} - diff --git a/src/intersim2/.svn/pristine/8c/8c5b24b41796edbfedbb98138da7278e7c22d832.svn-base b/src/intersim2/.svn/pristine/8c/8c5b24b41796edbfedbb98138da7278e7c22d832.svn-base deleted file mode 100644 index 48000bf..0000000 --- a/src/intersim2/.svn/pristine/8c/8c5b24b41796edbfedbb98138da7278e7c22d832.svn-base +++ /dev/null @@ -1,34 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#define main rng_main -#include "rng.c" - -long ran_next( ) -{ - return ran_arr_next( ); -} diff --git a/src/intersim2/.svn/pristine/8e/8e7a59b2896a3ee93a308768d554d28b324b26aa.svn-base b/src/intersim2/.svn/pristine/8e/8e7a59b2896a3ee93a308768d554d28b324b26aa.svn-base deleted file mode 100644 index d92ad08..0000000 --- a/src/intersim2/.svn/pristine/8e/8e7a59b2896a3ee93a308768d554d28b324b26aa.svn-base +++ /dev/null @@ -1,2283 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include -#include -#include -#include -#include - -#include "booksim.hpp" -#include "booksim_config.hpp" -#include "trafficmanager.hpp" -#include "batchtrafficmanager.hpp" -#include "random_utils.hpp" -#include "vc.hpp" -#include "packet_reply_info.hpp" - -TrafficManager * TrafficManager::New(Configuration const & config, - vector const & net) -{ - TrafficManager * result = NULL; - string sim_type = config.GetStr("sim_type"); - if((sim_type == "latency") || (sim_type == "throughput")) { - result = new TrafficManager(config, net); - } else if(sim_type == "batch") { - result = new BatchTrafficManager(config, net); - } else { - cerr << "Unknown simulation type: " << sim_type << endl; - } - return result; -} - -TrafficManager::TrafficManager( const Configuration &config, const vector & net ) - : Module( 0, "traffic_manager" ), _net(net), _empty_network(false), _deadlock_timer(0), _reset_time(0), _drain_time(-1), _cur_id(0), _cur_pid(0), _time(0) -{ - - _nodes = _net[0]->NumNodes( ); - _routers = _net[0]->NumRouters( ); - - _vcs = config.GetInt("num_vcs"); - _subnets = config.GetInt("subnets"); - - _subnet.resize(Flit::NUM_FLIT_TYPES); - _subnet[Flit::READ_REQUEST] = config.GetInt("read_request_subnet"); - _subnet[Flit::READ_REPLY] = config.GetInt("read_reply_subnet"); - _subnet[Flit::WRITE_REQUEST] = config.GetInt("write_request_subnet"); - _subnet[Flit::WRITE_REPLY] = config.GetInt("write_reply_subnet"); - - // ============ Message priorities ============ - - string priority = config.GetStr( "priority" ); - - if ( priority == "class" ) { - _pri_type = class_based; - } else if ( priority == "age" ) { - _pri_type = age_based; - } else if ( priority == "network_age" ) { - _pri_type = network_age_based; - } else if ( priority == "local_age" ) { - _pri_type = local_age_based; - } else if ( priority == "queue_length" ) { - _pri_type = queue_length_based; - } else if ( priority == "hop_count" ) { - _pri_type = hop_count_based; - } else if ( priority == "sequence" ) { - _pri_type = sequence_based; - } else if ( priority == "none" ) { - _pri_type = none; - } else { - Error( "Unkown priority value: " + priority ); - } - - // ============ Routing ============ - - string rf = config.GetStr("routing_function") + "_" + config.GetStr("topology"); - map::const_iterator rf_iter = gRoutingFunctionMap.find(rf); - if(rf_iter == gRoutingFunctionMap.end()) { - Error("Invalid routing function: " + rf); - } - _rf = rf_iter->second; - - _lookahead_routing = !config.GetInt("routing_delay"); - _noq = config.GetInt("noq"); - if(_noq) { - if(!_lookahead_routing) { - Error("NOQ requires lookahead routing to be enabled."); - } - } - - // ============ Traffic ============ - - _classes = config.GetInt("classes"); - - _use_read_write = config.GetIntArray("use_read_write"); - if(_use_read_write.empty()) { - _use_read_write.push_back(config.GetInt("use_read_write")); - } - _use_read_write.resize(_classes, _use_read_write.back()); - - _write_fraction = config.GetFloatArray("write_fraction"); - if(_write_fraction.empty()) { - _write_fraction.push_back(config.GetFloat("write_fraction")); - } - _write_fraction.resize(_classes, _write_fraction.back()); - - _read_request_size = config.GetIntArray("read_request_size"); - if(_read_request_size.empty()) { - _read_request_size.push_back(config.GetInt("read_request_size")); - } - _read_request_size.resize(_classes, _read_request_size.back()); - - _read_reply_size = config.GetIntArray("read_reply_size"); - if(_read_reply_size.empty()) { - _read_reply_size.push_back(config.GetInt("read_reply_size")); - } - _read_reply_size.resize(_classes, _read_reply_size.back()); - - _write_request_size = config.GetIntArray("write_request_size"); - if(_write_request_size.empty()) { - _write_request_size.push_back(config.GetInt("write_request_size")); - } - _write_request_size.resize(_classes, _write_request_size.back()); - - _write_reply_size = config.GetIntArray("write_reply_size"); - if(_write_reply_size.empty()) { - _write_reply_size.push_back(config.GetInt("write_reply_size")); - } - _write_reply_size.resize(_classes, _write_reply_size.back()); - - string packet_size_str = config.GetStr("packet_size"); - if(packet_size_str.empty()) { - _packet_size.push_back(vector(1, config.GetInt("packet_size"))); - } else { - vector packet_size_strings = tokenize_str(packet_size_str); - for(size_t i = 0; i < packet_size_strings.size(); ++i) { - _packet_size.push_back(tokenize_int(packet_size_strings[i])); - } - } - _packet_size.resize(_classes, _packet_size.back()); - - string packet_size_rate_str = config.GetStr("packet_size_rate"); - if(packet_size_rate_str.empty()) { - int rate = config.GetInt("packet_size_rate"); - assert(rate >= 0); - for(int c = 0; c < _classes; ++c) { - int size = _packet_size[c].size(); - _packet_size_rate.push_back(vector(size, rate)); - _packet_size_max_val.push_back(size * rate - 1); - } - } else { - vector packet_size_rate_strings = tokenize_str(packet_size_rate_str); - packet_size_rate_strings.resize(_classes, packet_size_rate_strings.back()); - for(int c = 0; c < _classes; ++c) { - vector rates = tokenize_int(packet_size_rate_strings[c]); - rates.resize(_packet_size[c].size(), rates.back()); - _packet_size_rate.push_back(rates); - int size = rates.size(); - int max_val = -1; - for(int i = 0; i < size; ++i) { - int rate = rates[i]; - assert(rate >= 0); - max_val += rate; - } - _packet_size_max_val.push_back(max_val); - } - } - - for(int c = 0; c < _classes; ++c) { - if(_use_read_write[c]) { - _packet_size[c] = - vector(1, (_read_request_size[c] + _read_reply_size[c] + - _write_request_size[c] + _write_reply_size[c]) / 2); - _packet_size_rate[c] = vector(1, 1); - _packet_size_max_val[c] = 0; - } - } - - _load = config.GetFloatArray("injection_rate"); - if(_load.empty()) { - _load.push_back(config.GetFloat("injection_rate")); - } - _load.resize(_classes, _load.back()); - - if(config.GetInt("injection_rate_uses_flits")) { - for(int c = 0; c < _classes; ++c) - _load[c] /= _GetAveragePacketSize(c); - } - - _traffic = config.GetStrArray("traffic"); - _traffic.resize(_classes, _traffic.back()); - - _traffic_pattern.resize(_classes); - - _class_priority = config.GetIntArray("class_priority"); - if(_class_priority.empty()) { - _class_priority.push_back(config.GetInt("class_priority")); - } - _class_priority.resize(_classes, _class_priority.back()); - - vector injection_process = config.GetStrArray("injection_process"); - injection_process.resize(_classes, injection_process.back()); - - _injection_process.resize(_classes); - - for(int c = 0; c < _classes; ++c) { - _traffic_pattern[c] = TrafficPattern::New(_traffic[c], _nodes, &config); - _injection_process[c] = InjectionProcess::New(injection_process[c], _nodes, _load[c], &config); - } - - // ============ Injection VC states ============ - - _buf_states.resize(_nodes); - _last_vc.resize(_nodes); - _last_class.resize(_nodes); - - for ( int source = 0; source < _nodes; ++source ) { - _buf_states[source].resize(_subnets); - _last_class[source].resize(_subnets, 0); - _last_vc[source].resize(_subnets); - for ( int subnet = 0; subnet < _subnets; ++subnet ) { - ostringstream tmp_name; - tmp_name << "terminal_buf_state_" << source << "_" << subnet; - BufferState * bs = new BufferState( config, this, tmp_name.str( ) ); - int vc_alloc_delay = config.GetInt("vc_alloc_delay"); - int sw_alloc_delay = config.GetInt("sw_alloc_delay"); - int router_latency = config.GetInt("routing_delay") + (config.GetInt("speculative") ? max(vc_alloc_delay, sw_alloc_delay) : (vc_alloc_delay + sw_alloc_delay)); - int min_latency = 1 + _net[subnet]->GetInject(source)->GetLatency() + router_latency + _net[subnet]->GetInjectCred(source)->GetLatency(); - bs->SetMinLatency(min_latency); - _buf_states[source][subnet] = bs; - _last_vc[source][subnet].resize(_classes, -1); - } - } - -#ifdef TRACK_FLOWS - _outstanding_credits.resize(_classes); - for(int c = 0; c < _classes; ++c) { - _outstanding_credits[c].resize(_subnets, vector(_nodes, 0)); - } - _outstanding_classes.resize(_nodes); - for(int n = 0; n < _nodes; ++n) { - _outstanding_classes[n].resize(_subnets, vector >(_vcs)); - } -#endif - - // ============ Injection queues ============ - - _qtime.resize(_nodes); - _qdrained.resize(_nodes); - _partial_packets.resize(_nodes); - - for ( int s = 0; s < _nodes; ++s ) { - _qtime[s].resize(_classes); - _qdrained[s].resize(_classes); - _partial_packets[s].resize(_classes); - } - - _total_in_flight_flits.resize(_classes); - _measured_in_flight_flits.resize(_classes); - _retired_packets.resize(_classes); - - _packet_seq_no.resize(_nodes); - _repliesPending.resize(_nodes); - _requestsOutstanding.resize(_nodes); - - _hold_switch_for_packet = config.GetInt("hold_switch_for_packet"); - - // ============ Simulation parameters ============ - - _total_sims = config.GetInt( "sim_count" ); - - _router.resize(_subnets); - for (int i=0; i < _subnets; ++i) { - _router[i] = _net[i]->GetRouters(); - } - - //seed the network - RandomSeed(config.GetInt("seed")); - - _measure_latency = (config.GetStr("sim_type") == "latency"); - - _sample_period = config.GetInt( "sample_period" ); - _max_samples = config.GetInt( "max_samples" ); - _warmup_periods = config.GetInt( "warmup_periods" ); - - _measure_stats = config.GetIntArray( "measure_stats" ); - if(_measure_stats.empty()) { - _measure_stats.push_back(config.GetInt("measure_stats")); - } - _measure_stats.resize(_classes, _measure_stats.back()); - _pair_stats = (config.GetInt("pair_stats")==1); - - _latency_thres = config.GetFloatArray( "latency_thres" ); - if(_latency_thres.empty()) { - _latency_thres.push_back(config.GetFloat("latency_thres")); - } - _latency_thres.resize(_classes, _latency_thres.back()); - - _warmup_threshold = config.GetFloatArray( "warmup_thres" ); - if(_warmup_threshold.empty()) { - _warmup_threshold.push_back(config.GetFloat("warmup_thres")); - } - _warmup_threshold.resize(_classes, _warmup_threshold.back()); - - _acc_warmup_threshold = config.GetFloatArray( "acc_warmup_thres" ); - if(_acc_warmup_threshold.empty()) { - _acc_warmup_threshold.push_back(config.GetFloat("acc_warmup_thres")); - } - _acc_warmup_threshold.resize(_classes, _acc_warmup_threshold.back()); - - _stopping_threshold = config.GetFloatArray( "stopping_thres" ); - if(_stopping_threshold.empty()) { - _stopping_threshold.push_back(config.GetFloat("stopping_thres")); - } - _stopping_threshold.resize(_classes, _stopping_threshold.back()); - - _acc_stopping_threshold = config.GetFloatArray( "acc_stopping_thres" ); - if(_acc_stopping_threshold.empty()) { - _acc_stopping_threshold.push_back(config.GetFloat("acc_stopping_thres")); - } - _acc_stopping_threshold.resize(_classes, _acc_stopping_threshold.back()); - - _include_queuing = config.GetInt( "include_queuing" ); - - _print_csv_results = config.GetInt( "print_csv_results" ); - _deadlock_warn_timeout = config.GetInt( "deadlock_warn_timeout" ); - - string watch_file = config.GetStr( "watch_file" ); - if((watch_file != "") && (watch_file != "-")) { - _LoadWatchList(watch_file); - } - - vector watch_flits = config.GetIntArray("watch_flits"); - for(size_t i = 0; i < watch_flits.size(); ++i) { - _flits_to_watch.insert(watch_flits[i]); - } - - vector watch_packets = config.GetIntArray("watch_packets"); - for(size_t i = 0; i < watch_packets.size(); ++i) { - _packets_to_watch.insert(watch_packets[i]); - } - - string stats_out_file = config.GetStr( "stats_out" ); - if(stats_out_file == "") { - _stats_out = NULL; - } else if(stats_out_file == "-") { - _stats_out = &cout; - } else { - _stats_out = new ofstream(stats_out_file.c_str()); - config.WriteMatlabFile(_stats_out); - } - -#ifdef TRACK_FLOWS - _injected_flits.resize(_classes, vector(_nodes, 0)); - _ejected_flits.resize(_classes, vector(_nodes, 0)); - string injected_flits_out_file = config.GetStr( "injected_flits_out" ); - if(injected_flits_out_file == "") { - _injected_flits_out = NULL; - } else { - _injected_flits_out = new ofstream(injected_flits_out_file.c_str()); - } - string received_flits_out_file = config.GetStr( "received_flits_out" ); - if(received_flits_out_file == "") { - _received_flits_out = NULL; - } else { - _received_flits_out = new ofstream(received_flits_out_file.c_str()); - } - string stored_flits_out_file = config.GetStr( "stored_flits_out" ); - if(stored_flits_out_file == "") { - _stored_flits_out = NULL; - } else { - _stored_flits_out = new ofstream(stored_flits_out_file.c_str()); - } - string sent_flits_out_file = config.GetStr( "sent_flits_out" ); - if(sent_flits_out_file == "") { - _sent_flits_out = NULL; - } else { - _sent_flits_out = new ofstream(sent_flits_out_file.c_str()); - } - string outstanding_credits_out_file = config.GetStr( "outstanding_credits_out" ); - if(outstanding_credits_out_file == "") { - _outstanding_credits_out = NULL; - } else { - _outstanding_credits_out = new ofstream(outstanding_credits_out_file.c_str()); - } - string ejected_flits_out_file = config.GetStr( "ejected_flits_out" ); - if(ejected_flits_out_file == "") { - _ejected_flits_out = NULL; - } else { - _ejected_flits_out = new ofstream(ejected_flits_out_file.c_str()); - } - string active_packets_out_file = config.GetStr( "active_packets_out" ); - if(active_packets_out_file == "") { - _active_packets_out = NULL; - } else { - _active_packets_out = new ofstream(active_packets_out_file.c_str()); - } -#endif - -#ifdef TRACK_CREDITS - string used_credits_out_file = config.GetStr( "used_credits_out" ); - if(used_credits_out_file == "") { - _used_credits_out = NULL; - } else { - _used_credits_out = new ofstream(used_credits_out_file.c_str()); - } - string free_credits_out_file = config.GetStr( "free_credits_out" ); - if(free_credits_out_file == "") { - _free_credits_out = NULL; - } else { - _free_credits_out = new ofstream(free_credits_out_file.c_str()); - } - string max_credits_out_file = config.GetStr( "max_credits_out" ); - if(max_credits_out_file == "") { - _max_credits_out = NULL; - } else { - _max_credits_out = new ofstream(max_credits_out_file.c_str()); - } -#endif - - // ============ Statistics ============ - - _plat_stats.resize(_classes); - _overall_min_plat.resize(_classes, 0.0); - _overall_avg_plat.resize(_classes, 0.0); - _overall_max_plat.resize(_classes, 0.0); - - _nlat_stats.resize(_classes); - _overall_min_nlat.resize(_classes, 0.0); - _overall_avg_nlat.resize(_classes, 0.0); - _overall_max_nlat.resize(_classes, 0.0); - - _flat_stats.resize(_classes); - _overall_min_flat.resize(_classes, 0.0); - _overall_avg_flat.resize(_classes, 0.0); - _overall_max_flat.resize(_classes, 0.0); - - _frag_stats.resize(_classes); - _overall_min_frag.resize(_classes, 0.0); - _overall_avg_frag.resize(_classes, 0.0); - _overall_max_frag.resize(_classes, 0.0); - - if(_pair_stats){ - _pair_plat.resize(_classes); - _pair_nlat.resize(_classes); - _pair_flat.resize(_classes); - } - - _hop_stats.resize(_classes); - _overall_hop_stats.resize(_classes, 0.0); - - _sent_packets.resize(_classes); - _overall_min_sent_packets.resize(_classes, 0.0); - _overall_avg_sent_packets.resize(_classes, 0.0); - _overall_max_sent_packets.resize(_classes, 0.0); - _accepted_packets.resize(_classes); - _overall_min_accepted_packets.resize(_classes, 0.0); - _overall_avg_accepted_packets.resize(_classes, 0.0); - _overall_max_accepted_packets.resize(_classes, 0.0); - - _sent_flits.resize(_classes); - _overall_min_sent.resize(_classes, 0.0); - _overall_avg_sent.resize(_classes, 0.0); - _overall_max_sent.resize(_classes, 0.0); - _accepted_flits.resize(_classes); - _overall_min_accepted.resize(_classes, 0.0); - _overall_avg_accepted.resize(_classes, 0.0); - _overall_max_accepted.resize(_classes, 0.0); - -#ifdef TRACK_STALLS - _buffer_busy_stalls.resize(_classes); - _buffer_conflict_stalls.resize(_classes); - _buffer_full_stalls.resize(_classes); - _buffer_reserved_stalls.resize(_classes); - _crossbar_conflict_stalls.resize(_classes); - _overall_buffer_busy_stalls.resize(_classes, 0); - _overall_buffer_conflict_stalls.resize(_classes, 0); - _overall_buffer_full_stalls.resize(_classes, 0); - _overall_buffer_reserved_stalls.resize(_classes, 0); - _overall_crossbar_conflict_stalls.resize(_classes, 0); -#endif - - for ( int c = 0; c < _classes; ++c ) { - ostringstream tmp_name; - - tmp_name << "plat_stat_" << c; - _plat_stats[c] = new Stats( this, tmp_name.str( ), 1.0, 1000 ); - _stats[tmp_name.str()] = _plat_stats[c]; - tmp_name.str(""); - - tmp_name << "nlat_stat_" << c; - _nlat_stats[c] = new Stats( this, tmp_name.str( ), 1.0, 1000 ); - _stats[tmp_name.str()] = _nlat_stats[c]; - tmp_name.str(""); - - tmp_name << "flat_stat_" << c; - _flat_stats[c] = new Stats( this, tmp_name.str( ), 1.0, 1000 ); - _stats[tmp_name.str()] = _flat_stats[c]; - tmp_name.str(""); - - tmp_name << "frag_stat_" << c; - _frag_stats[c] = new Stats( this, tmp_name.str( ), 1.0, 100 ); - _stats[tmp_name.str()] = _frag_stats[c]; - tmp_name.str(""); - - tmp_name << "hop_stat_" << c; - _hop_stats[c] = new Stats( this, tmp_name.str( ), 1.0, 20 ); - _stats[tmp_name.str()] = _hop_stats[c]; - tmp_name.str(""); - - if(_pair_stats){ - _pair_plat[c].resize(_nodes*_nodes); - _pair_nlat[c].resize(_nodes*_nodes); - _pair_flat[c].resize(_nodes*_nodes); - } - - _sent_packets[c].resize(_nodes, 0); - _accepted_packets[c].resize(_nodes, 0); - _sent_flits[c].resize(_nodes, 0); - _accepted_flits[c].resize(_nodes, 0); - -#ifdef TRACK_STALLS - _buffer_busy_stalls[c].resize(_subnets*_routers, 0); - _buffer_conflict_stalls[c].resize(_subnets*_routers, 0); - _buffer_full_stalls[c].resize(_subnets*_routers, 0); - _buffer_reserved_stalls[c].resize(_subnets*_routers, 0); - _crossbar_conflict_stalls[c].resize(_subnets*_routers, 0); -#endif - if(_pair_stats){ - for ( int i = 0; i < _nodes; ++i ) { - for ( int j = 0; j < _nodes; ++j ) { - tmp_name << "pair_plat_stat_" << c << "_" << i << "_" << j; - _pair_plat[c][i*_nodes+j] = new Stats( this, tmp_name.str( ), 1.0, 250 ); - _stats[tmp_name.str()] = _pair_plat[c][i*_nodes+j]; - tmp_name.str(""); - - tmp_name << "pair_nlat_stat_" << c << "_" << i << "_" << j; - _pair_nlat[c][i*_nodes+j] = new Stats( this, tmp_name.str( ), 1.0, 250 ); - _stats[tmp_name.str()] = _pair_nlat[c][i*_nodes+j]; - tmp_name.str(""); - - tmp_name << "pair_flat_stat_" << c << "_" << i << "_" << j; - _pair_flat[c][i*_nodes+j] = new Stats( this, tmp_name.str( ), 1.0, 250 ); - _stats[tmp_name.str()] = _pair_flat[c][i*_nodes+j]; - tmp_name.str(""); - } - } - } - } - - _slowest_flit.resize(_classes, -1); - _slowest_packet.resize(_classes, -1); - - - -} - -TrafficManager::~TrafficManager( ) -{ - - for ( int source = 0; source < _nodes; ++source ) { - for ( int subnet = 0; subnet < _subnets; ++subnet ) { - delete _buf_states[source][subnet]; - } - } - - for ( int c = 0; c < _classes; ++c ) { - delete _plat_stats[c]; - delete _nlat_stats[c]; - delete _flat_stats[c]; - delete _frag_stats[c]; - delete _hop_stats[c]; - - delete _traffic_pattern[c]; - delete _injection_process[c]; - if(_pair_stats){ - for ( int i = 0; i < _nodes; ++i ) { - for ( int j = 0; j < _nodes; ++j ) { - delete _pair_plat[c][i*_nodes+j]; - delete _pair_nlat[c][i*_nodes+j]; - delete _pair_flat[c][i*_nodes+j]; - } - } - } - } - - if(gWatchOut && (gWatchOut != &cout)) delete gWatchOut; - if(_stats_out && (_stats_out != &cout)) delete _stats_out; - -#ifdef TRACK_FLOWS - if(_injected_flits_out) delete _injected_flits_out; - if(_received_flits_out) delete _received_flits_out; - if(_stored_flits_out) delete _stored_flits_out; - if(_sent_flits_out) delete _sent_flits_out; - if(_outstanding_credits_out) delete _outstanding_credits_out; - if(_ejected_flits_out) delete _ejected_flits_out; - if(_active_packets_out) delete _active_packets_out; -#endif - -#ifdef TRACK_CREDITS - if(_used_credits_out) delete _used_credits_out; - if(_free_credits_out) delete _free_credits_out; - if(_max_credits_out) delete _max_credits_out; -#endif - - PacketReplyInfo::FreeAll(); - Flit::FreeAll(); - Credit::FreeAll(); -} - - -void TrafficManager::_RetireFlit( Flit *f, int dest ) -{ - _deadlock_timer = 0; - - assert(_total_in_flight_flits[f->cl].count(f->id) > 0); - _total_in_flight_flits[f->cl].erase(f->id); - - if(f->record) { - assert(_measured_in_flight_flits[f->cl].count(f->id) > 0); - _measured_in_flight_flits[f->cl].erase(f->id); - } - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " - << "node" << dest << " | " - << "Retiring flit " << f->id - << " (packet " << f->pid - << ", src = " << f->src - << ", dest = " << f->dest - << ", hops = " << f->hops - << ", flat = " << f->atime - f->itime - << ")." << endl; - } - - if ( f->head && ( f->dest != dest ) ) { - ostringstream err; - err << "Flit " << f->id << " arrived at incorrect output " << dest; - Error( err.str( ) ); - } - - if((_slowest_flit[f->cl] < 0) || - (_flat_stats[f->cl]->Max() < (f->atime - f->itime))) - _slowest_flit[f->cl] = f->id; - _flat_stats[f->cl]->AddSample( f->atime - f->itime); - if(_pair_stats){ - _pair_flat[f->cl][f->src*_nodes+dest]->AddSample( f->atime - f->itime ); - } - - if ( f->tail ) { - Flit * head; - if(f->head) { - head = f; - } else { - map::iterator iter = _retired_packets[f->cl].find(f->pid); - assert(iter != _retired_packets[f->cl].end()); - head = iter->second; - _retired_packets[f->cl].erase(iter); - assert(head->head); - assert(f->pid == head->pid); - } - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " - << "node" << dest << " | " - << "Retiring packet " << f->pid - << " (plat = " << f->atime - head->ctime - << ", nlat = " << f->atime - head->itime - << ", frag = " << (f->atime - head->atime) - (f->id - head->id) // NB: In the spirit of solving problems using ugly hacks, we compute the packet length by taking advantage of the fact that the IDs of flits within a packet are contiguous. - << ", src = " << head->src - << ", dest = " << head->dest - << ")." << endl; - } - - //code the source of request, look carefully, its tricky ;) - if (f->type == Flit::READ_REQUEST || f->type == Flit::WRITE_REQUEST) { - PacketReplyInfo* rinfo = PacketReplyInfo::New(); - rinfo->source = f->src; - rinfo->time = f->atime; - rinfo->record = f->record; - rinfo->type = f->type; - _repliesPending[dest].push_back(rinfo); - } else { - if(f->type == Flit::READ_REPLY || f->type == Flit::WRITE_REPLY ){ - _requestsOutstanding[dest]--; - } else if(f->type == Flit::ANY_TYPE) { - _requestsOutstanding[f->src]--; - } - - } - - // Only record statistics once per packet (at tail) - // and based on the simulation state - if ( ( _sim_state == warming_up ) || f->record ) { - - _hop_stats[f->cl]->AddSample( f->hops ); - - if((_slowest_packet[f->cl] < 0) || - (_plat_stats[f->cl]->Max() < (f->atime - head->itime))) - _slowest_packet[f->cl] = f->pid; - _plat_stats[f->cl]->AddSample( f->atime - head->ctime); - _nlat_stats[f->cl]->AddSample( f->atime - head->itime); - _frag_stats[f->cl]->AddSample( (f->atime - head->atime) - (f->id - head->id) ); - - if(_pair_stats){ - _pair_plat[f->cl][f->src*_nodes+dest]->AddSample( f->atime - head->ctime ); - _pair_nlat[f->cl][f->src*_nodes+dest]->AddSample( f->atime - head->itime ); - } - } - - if(f != head) { - head->Free(); - } - - } - - if(f->head && !f->tail) { - _retired_packets[f->cl].insert(make_pair(f->pid, f)); - } else { - f->Free(); - } -} - -int TrafficManager::_IssuePacket( int source, int cl ) -{ - int result = 0; - if(_use_read_write[cl]){ //use read and write - //check queue for waiting replies. - //check to make sure it is on time yet - if (!_repliesPending[source].empty()) { - if(_repliesPending[source].front()->time <= _time) { - result = -1; - } - } else { - - //produce a packet - if(_injection_process[cl]->test(source)) { - - //coin toss to determine request type. - result = (RandomFloat() < _write_fraction[cl]) ? 2 : 1; - - _requestsOutstanding[source]++; - } - } - } else { //normal mode - result = _injection_process[cl]->test(source) ? 1 : 0; - _requestsOutstanding[source]++; - } - if(result != 0) { - _packet_seq_no[source]++; - } - return result; -} - -void TrafficManager::_GeneratePacket( int source, int stype, - int cl, int time ) -{ - assert(stype!=0); - - Flit::FlitType packet_type = Flit::ANY_TYPE; - int size = _GetNextPacketSize(cl); //input size - int pid = _cur_pid++; - assert(_cur_pid); - int packet_destination = _traffic_pattern[cl]->dest(source); - bool record = false; - bool watch = gWatchOut && (_packets_to_watch.count(pid) > 0); - if(_use_read_write[cl]){ - if(stype > 0) { - if (stype == 1) { - packet_type = Flit::READ_REQUEST; - size = _read_request_size[cl]; - } else if (stype == 2) { - packet_type = Flit::WRITE_REQUEST; - size = _write_request_size[cl]; - } else { - ostringstream err; - err << "Invalid packet type: " << packet_type; - Error( err.str( ) ); - } - } else { - PacketReplyInfo* rinfo = _repliesPending[source].front(); - if (rinfo->type == Flit::READ_REQUEST) {//read reply - size = _read_reply_size[cl]; - packet_type = Flit::READ_REPLY; - } else if(rinfo->type == Flit::WRITE_REQUEST) { //write reply - size = _write_reply_size[cl]; - packet_type = Flit::WRITE_REPLY; - } else { - ostringstream err; - err << "Invalid packet type: " << rinfo->type; - Error( err.str( ) ); - } - packet_destination = rinfo->source; - time = rinfo->time; - record = rinfo->record; - _repliesPending[source].pop_front(); - rinfo->Free(); - } - } - - if ((packet_destination <0) || (packet_destination >= _nodes)) { - ostringstream err; - err << "Incorrect packet destination " << packet_destination - << " for stype " << packet_type; - Error( err.str( ) ); - } - - if ( ( _sim_state == running ) || - ( ( _sim_state == draining ) && ( time < _drain_time ) ) ) { - record = _measure_stats[cl]; - } - - int subnetwork = ((packet_type == Flit::ANY_TYPE) ? - RandomInt(_subnets-1) : - _subnet[packet_type]); - - if ( watch ) { - *gWatchOut << GetSimTime() << " | " - << "node" << source << " | " - << "Enqueuing packet " << pid - << " at time " << time - << "." << endl; - } - - for ( int i = 0; i < size; ++i ) { - Flit * f = Flit::New(); - f->id = _cur_id++; - assert(_cur_id); - f->pid = pid; - f->watch = watch | (gWatchOut && (_flits_to_watch.count(f->id) > 0)); - f->subnetwork = subnetwork; - f->src = source; - f->ctime = time; - f->record = record; - f->cl = cl; - - _total_in_flight_flits[f->cl].insert(make_pair(f->id, f)); - if(record) { - _measured_in_flight_flits[f->cl].insert(make_pair(f->id, f)); - } - - if(gTrace){ - cout<<"New Flit "<src<type = packet_type; - - if ( i == 0 ) { // Head flit - f->head = true; - //packets are only generated to nodes smaller or equal to limit - f->dest = packet_destination; - } else { - f->head = false; - f->dest = -1; - } - switch( _pri_type ) { - case class_based: - f->pri = _class_priority[cl]; - assert(f->pri >= 0); - break; - case age_based: - f->pri = numeric_limits::max() - time; - assert(f->pri >= 0); - break; - case sequence_based: - f->pri = numeric_limits::max() - _packet_seq_no[source]; - assert(f->pri >= 0); - break; - default: - f->pri = 0; - } - if ( i == ( size - 1 ) ) { // Tail flit - f->tail = true; - } else { - f->tail = false; - } - - f->vc = -1; - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " - << "node" << source << " | " - << "Enqueuing flit " << f->id - << " (packet " << f->pid - << ") at time " << time - << "." << endl; - } - - _partial_packets[source][cl].push_back( f ); - } -} - -void TrafficManager::_Inject(){ - - for ( int input = 0; input < _nodes; ++input ) { - for ( int c = 0; c < _classes; ++c ) { - // Potentially generate packets for any (input,class) - // that is currently empty - if ( _partial_packets[input][c].empty() ) { - bool generated = false; - while( !generated && ( _qtime[input][c] <= _time ) ) { - int stype = _IssuePacket( input, c ); - - if ( stype != 0 ) { //generate a packet - _GeneratePacket( input, stype, c, - _include_queuing==1 ? - _qtime[input][c] : _time ); - generated = true; - } - // only advance time if this is not a reply packet - if(!_use_read_write[c] || (stype >= 0)){ - ++_qtime[input][c]; - } - } - - if ( ( _sim_state == draining ) && - ( _qtime[input][c] > _drain_time ) ) { - _qdrained[input][c] = true; - } - } - } - } -} - -void TrafficManager::_Step( ) -{ - bool flits_in_flight = false; - for(int c = 0; c < _classes; ++c) { - flits_in_flight |= !_total_in_flight_flits[c].empty(); - } - if(flits_in_flight && (_deadlock_timer++ >= _deadlock_warn_timeout)){ - _deadlock_timer = 0; - cout << "WARNING: Possible network deadlock.\n"; - } - - vector > flits(_subnets); - - for ( int subnet = 0; subnet < _subnets; ++subnet ) { - for ( int n = 0; n < _nodes; ++n ) { - Flit * const f = _net[subnet]->ReadFlit( n ); - if ( f ) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " - << "node" << n << " | " - << "Ejecting flit " << f->id - << " (packet " << f->pid << ")" - << " from VC " << f->vc - << "." << endl; - } - flits[subnet].insert(make_pair(n, f)); - if((_sim_state == warming_up) || (_sim_state == running)) { - ++_accepted_flits[f->cl][n]; - if(f->tail) { - ++_accepted_packets[f->cl][n]; - } - } - } - - Credit * const c = _net[subnet]->ReadCredit( n ); - if ( c ) { -#ifdef TRACK_FLOWS - for(set::const_iterator iter = c->vc.begin(); iter != c->vc.end(); ++iter) { - int const vc = *iter; - assert(!_outstanding_classes[n][subnet][vc].empty()); - int cl = _outstanding_classes[n][subnet][vc].front(); - _outstanding_classes[n][subnet][vc].pop(); - assert(_outstanding_credits[cl][subnet][n] > 0); - --_outstanding_credits[cl][subnet][n]; - } -#endif - _buf_states[n][subnet]->ProcessCredit(c); - c->Free(); - } - } - _net[subnet]->ReadInputs( ); - } - - if ( !_empty_network ) { - _Inject(); - } - - for(int subnet = 0; subnet < _subnets; ++subnet) { - - for(int n = 0; n < _nodes; ++n) { - - Flit * f = NULL; - - BufferState * const dest_buf = _buf_states[n][subnet]; - - int const last_class = _last_class[n][subnet]; - - int class_limit = _classes; - - if(_hold_switch_for_packet) { - list const & pp = _partial_packets[n][last_class]; - if(!pp.empty() && !pp.front()->head && - !dest_buf->IsFullFor(pp.front()->vc)) { - f = pp.front(); - assert(f->vc == _last_vc[n][subnet][last_class]); - - // if we're holding the connection, we don't need to check that class - // again in the for loop - --class_limit; - } - } - - for(int i = 1; i <= class_limit; ++i) { - - int const c = (last_class + i) % _classes; - - list const & pp = _partial_packets[n][c]; - - if(pp.empty()) { - continue; - } - - Flit * const cf = pp.front(); - assert(cf); - assert(cf->cl == c); - - if(cf->subnetwork != subnet) { - continue; - } - - if(f && (f->pri >= cf->pri)) { - continue; - } - - if(cf->head && cf->vc == -1) { // Find first available VC - - OutputSet route_set; - _rf(NULL, cf, -1, &route_set, true); - set const & os = route_set.GetSet(); - assert(os.size() == 1); - OutputSet::sSetElement const & se = *os.begin(); - assert(se.output_port == -1); - int vc_start = se.vc_start; - int vc_end = se.vc_end; - int vc_count = vc_end - vc_start + 1; - if(_noq) { - assert(_lookahead_routing); - const FlitChannel * inject = _net[subnet]->GetInject(n); - const Router * router = inject->GetSink(); - assert(router); - int in_channel = inject->GetSinkPort(); - - // NOTE: Because the lookahead is not for injection, but for the - // first hop, we have to temporarily set cf's VC to be non-negative - // in order to avoid seting of an assertion in the routing function. - cf->vc = vc_start; - _rf(router, cf, in_channel, &cf->la_route_set, false); - cf->vc = -1; - - if(cf->watch) { - *gWatchOut << GetSimTime() << " | " - << "node" << n << " | " - << "Generating lookahead routing info for flit " << cf->id - << " (NOQ)." << endl; - } - set const sl = cf->la_route_set.GetSet(); - assert(sl.size() == 1); - int next_output = sl.begin()->output_port; - vc_count /= router->NumOutputs(); - vc_start += next_output * vc_count; - vc_end = vc_start + vc_count - 1; - assert(vc_start >= se.vc_start && vc_start <= se.vc_end); - assert(vc_end >= se.vc_start && vc_end <= se.vc_end); - assert(vc_start <= vc_end); - } - if(cf->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Finding output VC for flit " << cf->id - << ":" << endl; - } - for(int i = 1; i <= vc_count; ++i) { - int const lvc = _last_vc[n][subnet][c]; - int const vc = - (lvc < vc_start || lvc > vc_end) ? - vc_start : - (vc_start + (lvc - vc_start + i) % vc_count); - assert((vc >= vc_start) && (vc <= vc_end)); - if(!dest_buf->IsAvailableFor(vc)) { - if(cf->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Output VC " << vc << " is busy." << endl; - } - } else { - if(dest_buf->IsFullFor(vc)) { - if(cf->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Output VC " << vc << " is full." << endl; - } - } else { - if(cf->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Selected output VC " << vc << "." << endl; - } - cf->vc = vc; - break; - } - } - } - } - - if(cf->vc == -1) { - if(cf->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "No output VC found for flit " << cf->id - << "." << endl; - } - } else { - if(dest_buf->IsFullFor(cf->vc)) { - if(cf->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Selected output VC " << cf->vc - << " is full for flit " << cf->id - << "." << endl; - } - } else { - f = cf; - } - } - } - - if(f) { - - assert(f->subnetwork == subnet); - - int const c = f->cl; - - if(f->head) { - - if (_lookahead_routing) { - if(!_noq) { - const FlitChannel * inject = _net[subnet]->GetInject(n); - const Router * router = inject->GetSink(); - assert(router); - int in_channel = inject->GetSinkPort(); - _rf(router, f, in_channel, &f->la_route_set, false); - if(f->watch) { - *gWatchOut << GetSimTime() << " | " - << "node" << n << " | " - << "Generating lookahead routing info for flit " << f->id - << "." << endl; - } - } else if(f->watch) { - *gWatchOut << GetSimTime() << " | " - << "node" << n << " | " - << "Already generated lookahead routing info for flit " << f->id - << " (NOQ)." << endl; - } - } else { - f->la_route_set.Clear(); - } - - dest_buf->TakeBuffer(f->vc); - _last_vc[n][subnet][c] = f->vc; - } - - _last_class[n][subnet] = c; - - _partial_packets[n][c].pop_front(); - -#ifdef TRACK_FLOWS - ++_outstanding_credits[c][subnet][n]; - _outstanding_classes[n][subnet][f->vc].push(c); -#endif - - dest_buf->SendingFlit(f); - - if(_pri_type == network_age_based) { - f->pri = numeric_limits::max() - _time; - assert(f->pri >= 0); - } - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " - << "node" << n << " | " - << "Injecting flit " << f->id - << " into subnet " << subnet - << " at time " << _time - << " with priority " << f->pri - << "." << endl; - } - f->itime = _time; - - // Pass VC "back" - if(!_partial_packets[n][c].empty() && !f->tail) { - Flit * const nf = _partial_packets[n][c].front(); - nf->vc = f->vc; - } - - if((_sim_state == warming_up) || (_sim_state == running)) { - ++_sent_flits[c][n]; - if(f->head) { - ++_sent_packets[c][n]; - } - } - -#ifdef TRACK_FLOWS - ++_injected_flits[c][n]; -#endif - - _net[subnet]->WriteFlit(f, n); - - } - } - } - - for(int subnet = 0; subnet < _subnets; ++subnet) { - for(int n = 0; n < _nodes; ++n) { - map::const_iterator iter = flits[subnet].find(n); - if(iter != flits[subnet].end()) { - Flit * const f = iter->second; - - f->atime = _time; - if(f->watch) { - *gWatchOut << GetSimTime() << " | " - << "node" << n << " | " - << "Injecting credit for VC " << f->vc - << " into subnet " << subnet - << "." << endl; - } - Credit * const c = Credit::New(); - c->vc.insert(f->vc); - _net[subnet]->WriteCredit(c, n); - -#ifdef TRACK_FLOWS - ++_ejected_flits[f->cl][n]; -#endif - - _RetireFlit(f, n); - } - } - flits[subnet].clear(); - _net[subnet]->Evaluate( ); - _net[subnet]->WriteOutputs( ); - } - - ++_time; - assert(_time); - if(gTrace){ - cout<<"TIME "<<_time<first << " "; - } - if(_total_in_flight_flits[c].size() > 10) - os << "[...] "; - - os << "(" << _total_in_flight_flits[c].size() << " flits)" << endl; - - os << "Measured flits: "; - for ( iter = _measured_in_flight_flits[c].begin( ), i = 0; - ( iter != _measured_in_flight_flits[c].end( ) ) && ( i < 10 ); - iter++, i++ ) { - os << iter->first << " "; - } - if(_measured_in_flight_flits[c].size() > 10) - os << "[...] "; - - os << "(" << _measured_in_flight_flits[c].size() << " flits)" << endl; - - } -} - -bool TrafficManager::_SingleSim( ) -{ - int converged = 0; - - //once warmed up, we require 3 converging runs to end the simulation - vector prev_latency(_classes, 0.0); - vector prev_accepted(_classes, 0.0); - bool clear_last = false; - int total_phases = 0; - while( ( total_phases < _max_samples ) && - ( ( _sim_state != running ) || - ( converged < 3 ) ) ) { - - if ( clear_last || (( ( _sim_state == warming_up ) && ( ( total_phases % 2 ) == 0 ) )) ) { - clear_last = false; - _ClearStats( ); - } - - - for ( int iter = 0; iter < _sample_period; ++iter ) - _Step( ); - - //cout << _sim_state << endl; - - UpdateStats(); - DisplayStats(); - - int lat_exc_class = -1; - int lat_chg_exc_class = -1; - int acc_chg_exc_class = -1; - - for(int c = 0; c < _classes; ++c) { - - if(_measure_stats[c] == 0) { - continue; - } - - double cur_latency = _plat_stats[c]->Average( ); - - int total_accepted_count; - _ComputeStats( _accepted_flits[c], &total_accepted_count ); - double total_accepted_rate = (double)total_accepted_count / (double)(_time - _reset_time); - double cur_accepted = total_accepted_rate / (double)_nodes; - - double latency_change = fabs((cur_latency - prev_latency[c]) / cur_latency); - prev_latency[c] = cur_latency; - - double accepted_change = fabs((cur_accepted - prev_accepted[c]) / cur_accepted); - prev_accepted[c] = cur_accepted; - - double latency = (double)_plat_stats[c]->Sum(); - double count = (double)_plat_stats[c]->NumSamples(); - - map::const_iterator iter; - for(iter = _total_in_flight_flits[c].begin(); - iter != _total_in_flight_flits[c].end(); - iter++) { - latency += (double)(_time - iter->second->ctime); - count++; - } - - if((lat_exc_class < 0) && - (_latency_thres[c] >= 0.0) && - ((latency / count) > _latency_thres[c])) { - lat_exc_class = c; - } - - cout << "latency change = " << latency_change << endl; - if(lat_chg_exc_class < 0) { - if((_sim_state == warming_up) && - (_warmup_threshold[c] >= 0.0) && - (latency_change > _warmup_threshold[c])) { - lat_chg_exc_class = c; - } else if((_sim_state == running) && - (_stopping_threshold[c] >= 0.0) && - (latency_change > _stopping_threshold[c])) { - lat_chg_exc_class = c; - } - } - - cout << "throughput change = " << accepted_change << endl; - if(acc_chg_exc_class < 0) { - if((_sim_state == warming_up) && - (_acc_warmup_threshold[c] >= 0.0) && - (accepted_change > _acc_warmup_threshold[c])) { - acc_chg_exc_class = c; - } else if((_sim_state == running) && - (_acc_stopping_threshold[c] >= 0.0) && - (accepted_change > _acc_stopping_threshold[c])) { - acc_chg_exc_class = c; - } - } - - } - - // Fail safe for latency mode, throughput will ust continue - if ( _measure_latency && ( lat_exc_class >= 0 ) ) { - - cout << "Average latency for class " << lat_exc_class << " exceeded " << _latency_thres[lat_exc_class] << " cycles. Aborting simulation." << endl; - converged = 0; - _sim_state = draining; - _drain_time = _time; - if(_stats_out) { - WriteStats(*_stats_out); - } - break; - - } - - if ( _sim_state == warming_up ) { - if ( ( _warmup_periods > 0 ) ? - ( total_phases + 1 >= _warmup_periods ) : - ( ( !_measure_latency || ( lat_chg_exc_class < 0 ) ) && - ( acc_chg_exc_class < 0 ) ) ) { - cout << "Warmed up ..." << "Time used is " << _time << " cycles" <Sum(); - double acc_count = (double)_plat_stats[c]->NumSamples(); - - map::const_iterator iter; - for(iter = _total_in_flight_flits[c].begin(); - iter != _total_in_flight_flits[c].end(); - iter++) { - acc_latency += (double)(_time - iter->second->ctime); - acc_count++; - } - - if((acc_latency / acc_count) > threshold) { - lat_exc_class = c; - break; - } - } - - if(lat_exc_class >= 0) { - cout << "Average latency for class " << lat_exc_class << " exceeded " << _latency_thres[lat_exc_class] << " cycles. Aborting simulation." << endl; - converged = 0; - _sim_state = warming_up; - if(_stats_out) { - WriteStats(*_stats_out); - } - break; - } - - _DisplayRemaining( ); - - } - } - } - } else { - cout << "Too many sample periods needed to converge" << endl; - } - - return ( converged > 0 ); -} - -bool TrafficManager::Run( ) -{ - for ( int sim = 0; sim < _total_sims; ++sim ) { - - _time = 0; - - //remove any pending request from the previous simulations - _requestsOutstanding.assign(_nodes, 0); - for (int i=0;i<_nodes;i++) { - while(!_repliesPending[i].empty()) { - _repliesPending[i].front()->Free(); - _repliesPending[i].pop_front(); - } - } - - //reset queuetime for all sources - for ( int s = 0; s < _nodes; ++s ) { - _qtime[s].assign(_classes, 0); - _qdrained[s].assign(_classes, false); - } - - // warm-up ... - // reset stats, all packets after warmup_time marked - // converge - // draing, wait until all packets finish - _sim_state = warming_up; - - _ClearStats( ); - - for(int c = 0; c < _classes; ++c) { - _traffic_pattern[c]->reset(); - _injection_process[c]->reset(); - } - - if ( !_SingleSim( ) ) { - cout << "Simulation unstable, ending ..." << endl; - return false; - } - - // Empty any remaining packets - cout << "Draining remaining packets ..." << endl; - _empty_network = true; - int empty_steps = 0; - - bool packets_left = false; - for(int c = 0; c < _classes; ++c) { - packets_left |= !_total_in_flight_flits[c].empty(); - } - - while( packets_left ) { - _Step( ); - - ++empty_steps; - - if ( empty_steps % 1000 == 0 ) { - _DisplayRemaining( ); - } - - packets_left = false; - for(int c = 0; c < _classes; ++c) { - packets_left |= !_total_in_flight_flits[c].empty(); - } - } - //wait until all the credits are drained as well - while(Credit::OutStanding()!=0){ - _Step(); - } - _empty_network = false; - - //for the love of god don't ever say "Time taken" anywhere else - //the power script depend on it - cout << "Time taken is " << _time << " cycles" <Min(); - _overall_avg_plat[c] += _plat_stats[c]->Average(); - _overall_max_plat[c] += _plat_stats[c]->Max(); - _overall_min_nlat[c] += _nlat_stats[c]->Min(); - _overall_avg_nlat[c] += _nlat_stats[c]->Average(); - _overall_max_nlat[c] += _nlat_stats[c]->Max(); - _overall_min_flat[c] += _flat_stats[c]->Min(); - _overall_avg_flat[c] += _flat_stats[c]->Average(); - _overall_max_flat[c] += _flat_stats[c]->Max(); - - _overall_min_frag[c] += _frag_stats[c]->Min(); - _overall_avg_frag[c] += _frag_stats[c]->Average(); - _overall_max_frag[c] += _frag_stats[c]->Max(); - - _overall_hop_stats[c] += _hop_stats[c]->Average(); - - int count_min, count_sum, count_max; - double rate_min, rate_sum, rate_max; - double rate_avg; - double time_delta = (double)(_drain_time - _reset_time); - _ComputeStats( _sent_flits[c], &count_sum, &count_min, &count_max ); - rate_min = (double)count_min / time_delta; - rate_sum = (double)count_sum / time_delta; - rate_max = (double)count_max / time_delta; - rate_avg = rate_sum / (double)_nodes; - _overall_min_sent[c] += rate_min; - _overall_avg_sent[c] += rate_avg; - _overall_max_sent[c] += rate_max; - _ComputeStats( _sent_packets[c], &count_sum, &count_min, &count_max ); - rate_min = (double)count_min / time_delta; - rate_sum = (double)count_sum / time_delta; - rate_max = (double)count_max / time_delta; - rate_avg = rate_sum / (double)_nodes; - _overall_min_sent_packets[c] += rate_min; - _overall_avg_sent_packets[c] += rate_avg; - _overall_max_sent_packets[c] += rate_max; - _ComputeStats( _accepted_flits[c], &count_sum, &count_min, &count_max ); - rate_min = (double)count_min / time_delta; - rate_sum = (double)count_sum / time_delta; - rate_max = (double)count_max / time_delta; - rate_avg = rate_sum / (double)_nodes; - _overall_min_accepted[c] += rate_min; - _overall_avg_accepted[c] += rate_avg; - _overall_max_accepted[c] += rate_max; - _ComputeStats( _accepted_packets[c], &count_sum, &count_min, &count_max ); - rate_min = (double)count_min / time_delta; - rate_sum = (double)count_sum / time_delta; - rate_max = (double)count_max / time_delta; - rate_avg = rate_sum / (double)_nodes; - _overall_min_accepted_packets[c] += rate_min; - _overall_avg_accepted_packets[c] += rate_avg; - _overall_max_accepted_packets[c] += rate_max; - -#ifdef TRACK_STALLS - _ComputeStats(_buffer_busy_stalls[c], &count_sum); - rate_sum = (double)count_sum / time_delta; - rate_avg = rate_sum / (double)(_subnets*_routers); - _overall_buffer_busy_stalls[c] += rate_avg; - _ComputeStats(_buffer_conflict_stalls[c], &count_sum); - rate_sum = (double)count_sum / time_delta; - rate_avg = rate_sum / (double)(_subnets*_routers); - _overall_buffer_conflict_stalls[c] += rate_avg; - _ComputeStats(_buffer_full_stalls[c], &count_sum); - rate_sum = (double)count_sum / time_delta; - rate_avg = rate_sum / (double)(_subnets*_routers); - _overall_buffer_full_stalls[c] += rate_avg; - _ComputeStats(_buffer_reserved_stalls[c], &count_sum); - rate_sum = (double)count_sum / time_delta; - rate_avg = rate_sum / (double)(_subnets*_routers); - _overall_buffer_reserved_stalls[c] += rate_avg; - _ComputeStats(_crossbar_conflict_stalls[c], &count_sum); - rate_sum = (double)count_sum / time_delta; - rate_avg = rate_sum / (double)(_subnets*_routers); - _overall_crossbar_conflict_stalls[c] += rate_avg; -#endif - - } -} - -void TrafficManager::WriteStats(ostream & os) const { - - os << "%=================================" << endl; - - for(int c = 0; c < _classes; ++c) { - - if(_measure_stats[c] == 0) { - continue; - } - - //c+1 due to matlab array starting at 1 - os << "plat(" << c+1 << ") = " << _plat_stats[c]->Average() << ";" << endl - << "plat_hist(" << c+1 << ",:) = " << *_plat_stats[c] << ";" << endl - << "nlat(" << c+1 << ") = " << _nlat_stats[c]->Average() << ";" << endl - << "nlat_hist(" << c+1 << ",:) = " << *_nlat_stats[c] << ";" << endl - << "flat(" << c+1 << ") = " << _flat_stats[c]->Average() << ";" << endl - << "flat_hist(" << c+1 << ",:) = " << *_flat_stats[c] << ";" << endl - << "frag_hist(" << c+1 << ",:) = " << *_frag_stats[c] << ";" << endl - << "hops(" << c+1 << ",:) = " << *_hop_stats[c] << ";" << endl; - if(_pair_stats){ - os<< "pair_sent(" << c+1 << ",:) = [ "; - for(int i = 0; i < _nodes; ++i) { - for(int j = 0; j < _nodes; ++j) { - os << _pair_plat[c][i*_nodes+j]->NumSamples() << " "; - } - } - os << "];" << endl - << "pair_plat(" << c+1 << ",:) = [ "; - for(int i = 0; i < _nodes; ++i) { - for(int j = 0; j < _nodes; ++j) { - os << _pair_plat[c][i*_nodes+j]->Average( ) << " "; - } - } - os << "];" << endl - << "pair_nlat(" << c+1 << ",:) = [ "; - for(int i = 0; i < _nodes; ++i) { - for(int j = 0; j < _nodes; ++j) { - os << _pair_nlat[c][i*_nodes+j]->Average( ) << " "; - } - } - os << "];" << endl - << "pair_flat(" << c+1 << ",:) = [ "; - for(int i = 0; i < _nodes; ++i) { - for(int j = 0; j < _nodes; ++j) { - os << _pair_flat[c][i*_nodes+j]->Average( ) << " "; - } - } - } - - double time_delta = (double)(_drain_time - _reset_time); - - os << "];" << endl - << "sent_packets(" << c+1 << ",:) = [ "; - for ( int d = 0; d < _nodes; ++d ) { - os << (double)_sent_packets[c][d] / time_delta << " "; - } - os << "];" << endl - << "accepted_packets(" << c+1 << ",:) = [ "; - for ( int d = 0; d < _nodes; ++d ) { - os << (double)_accepted_packets[c][d] / time_delta << " "; - } - os << "];" << endl - << "sent_flits(" << c+1 << ",:) = [ "; - for ( int d = 0; d < _nodes; ++d ) { - os << (double)_sent_flits[c][d] / time_delta << " "; - } - os << "];" << endl - << "accepted_flits(" << c+1 << ",:) = [ "; - for ( int d = 0; d < _nodes; ++d ) { - os << (double)_accepted_flits[c][d] / time_delta << " "; - } - os << "];" << endl - << "sent_packet_size(" << c+1 << ",:) = [ "; - for ( int d = 0; d < _nodes; ++d ) { - os << (double)_sent_flits[c][d] / (double)_sent_packets[c][d] << " "; - } - os << "];" << endl - << "accepted_packet_size(" << c+1 << ",:) = [ "; - for ( int d = 0; d < _nodes; ++d ) { - os << (double)_accepted_flits[c][d] / (double)_accepted_packets[c][d] << " "; - } - os << "];" << endl; -#ifdef TRACK_STALLS - os << "buffer_busy_stalls(" << c+1 << ",:) = [ "; - for ( int d = 0; d < _subnets*_routers; ++d ) { - os << (double)_buffer_busy_stalls[c][d] / time_delta << " "; - } - os << "];" << endl - << "buffer_conflict_stalls(" << c+1 << ",:) = [ "; - for ( int d = 0; d < _subnets*_routers; ++d ) { - os << (double)_buffer_conflict_stalls[c][d] / time_delta << " "; - } - os << "];" << endl - << "buffer_full_stalls(" << c+1 << ",:) = [ "; - for ( int d = 0; d < _subnets*_routers; ++d ) { - os << (double)_buffer_full_stalls[c][d] / time_delta << " "; - } - os << "];" << endl - << "buffer_reserved_stalls(" << c+1 << ",:) = [ "; - for ( int d = 0; d < _subnets*_routers; ++d ) { - os << (double)_buffer_reserved_stalls[c][d] / time_delta << " "; - } - os << "];" << endl - << "crossbar_conflict_stalls(" << c+1 << ",:) = [ "; - for ( int d = 0; d < _subnets*_routers; ++d ) { - os << (double)_crossbar_conflict_stalls[c][d] / time_delta << " "; - } - os << "];" << endl; -#endif - } -} - -void TrafficManager::UpdateStats() { -#if defined(TRACK_FLOWS) || defined(TRACK_STALLS) - for(int c = 0; c < _classes; ++c) { -#ifdef TRACK_FLOWS - { - char trail_char = (c == _classes - 1) ? '\n' : ','; - if(_injected_flits_out) *_injected_flits_out << _injected_flits[c] << trail_char; - _injected_flits[c].assign(_nodes, 0); - if(_ejected_flits_out) *_ejected_flits_out << _ejected_flits[c] << trail_char; - _ejected_flits[c].assign(_nodes, 0); - } -#endif - for(int subnet = 0; subnet < _subnets; ++subnet) { -#ifdef TRACK_FLOWS - if(_outstanding_credits_out) *_outstanding_credits_out << _outstanding_credits[c][subnet] << ','; - if(_stored_flits_out) *_stored_flits_out << vector(_nodes, 0) << ','; -#endif - for(int router = 0; router < _routers; ++router) { - Router * const r = _router[subnet][router]; -#ifdef TRACK_FLOWS - char trail_char = - ((router == _routers - 1) && (subnet == _subnets - 1) && (c == _classes - 1)) ? '\n' : ','; - if(_received_flits_out) *_received_flits_out << r->GetReceivedFlits(c) << trail_char; - if(_stored_flits_out) *_stored_flits_out << r->GetStoredFlits(c) << trail_char; - if(_sent_flits_out) *_sent_flits_out << r->GetSentFlits(c) << trail_char; - if(_outstanding_credits_out) *_outstanding_credits_out << r->GetOutstandingCredits(c) << trail_char; - if(_active_packets_out) *_active_packets_out << r->GetActivePackets(c) << trail_char; - r->ResetFlowStats(c); -#endif -#ifdef TRACK_STALLS - _buffer_busy_stalls[c][subnet*_routers+router] += r->GetBufferBusyStalls(c); - _buffer_conflict_stalls[c][subnet*_routers+router] += r->GetBufferConflictStalls(c); - _buffer_full_stalls[c][subnet*_routers+router] += r->GetBufferFullStalls(c); - _buffer_reserved_stalls[c][subnet*_routers+router] += r->GetBufferReservedStalls(c); - _crossbar_conflict_stalls[c][subnet*_routers+router] += r->GetCrossbarConflictStalls(c); - r->ResetStallStats(c); -#endif - } - } - } -#ifdef TRACK_FLOWS - if(_injected_flits_out) *_injected_flits_out << flush; - if(_received_flits_out) *_received_flits_out << flush; - if(_stored_flits_out) *_stored_flits_out << flush; - if(_sent_flits_out) *_sent_flits_out << flush; - if(_outstanding_credits_out) *_outstanding_credits_out << flush; - if(_ejected_flits_out) *_ejected_flits_out << flush; - if(_active_packets_out) *_active_packets_out << flush; -#endif -#endif - -#ifdef TRACK_CREDITS - for(int s = 0; s < _subnets; ++s) { - for(int n = 0; n < _nodes; ++n) { - BufferState const * const bs = _buf_states[n][s]; - for(int v = 0; v < _vcs; ++v) { - if(_used_credits_out) *_used_credits_out << bs->OccupancyFor(v) << ','; - if(_free_credits_out) *_free_credits_out << bs->AvailableFor(v) << ','; - if(_max_credits_out) *_max_credits_out << bs->LimitFor(v) << ','; - } - } - for(int r = 0; r < _routers; ++r) { - Router const * const rtr = _router[s][r]; - char trail_char = - ((r == _routers - 1) && (s == _subnets - 1)) ? '\n' : ','; - if(_used_credits_out) *_used_credits_out << rtr->UsedCredits() << trail_char; - if(_free_credits_out) *_free_credits_out << rtr->FreeCredits() << trail_char; - if(_max_credits_out) *_max_credits_out << rtr->MaxCredits() << trail_char; - } - } - if(_used_credits_out) *_used_credits_out << flush; - if(_free_credits_out) *_free_credits_out << flush; - if(_max_credits_out) *_max_credits_out << flush; -#endif - -} - -void TrafficManager::DisplayStats(ostream & os) const { - - for(int c = 0; c < _classes; ++c) { - - if(_measure_stats[c] == 0) { - continue; - } - - cout << "Class " << c << ":" << endl; - - cout - << "Packet latency average = " << _plat_stats[c]->Average() << endl - << "\tminimum = " << _plat_stats[c]->Min() << endl - << "\tmaximum = " << _plat_stats[c]->Max() << endl - << "Network latency average = " << _nlat_stats[c]->Average() << endl - << "\tminimum = " << _nlat_stats[c]->Min() << endl - << "\tmaximum = " << _nlat_stats[c]->Max() << endl - << "Slowest packet = " << _slowest_packet[c] << endl - << "Flit latency average = " << _flat_stats[c]->Average() << endl - << "\tminimum = " << _flat_stats[c]->Min() << endl - << "\tmaximum = " << _flat_stats[c]->Max() << endl - << "Slowest flit = " << _slowest_flit[c] << endl - << "Fragmentation average = " << _frag_stats[c]->Average() << endl - << "\tminimum = " << _frag_stats[c]->Min() << endl - << "\tmaximum = " << _frag_stats[c]->Max() << endl; - - int count_sum, count_min, count_max; - double rate_sum, rate_min, rate_max; - double rate_avg; - int sent_packets, sent_flits, accepted_packets, accepted_flits; - int min_pos, max_pos; - double time_delta = (double)(_time - _reset_time); - _ComputeStats(_sent_packets[c], &count_sum, &count_min, &count_max, &min_pos, &max_pos); - rate_sum = (double)count_sum / time_delta; - rate_min = (double)count_min / time_delta; - rate_max = (double)count_max / time_delta; - rate_avg = rate_sum / (double)_nodes; - sent_packets = count_sum; - cout << "Injected packet rate average = " << rate_avg << endl - << "\tminimum = " << rate_min - << " (at node " << min_pos << ")" << endl - << "\tmaximum = " << rate_max - << " (at node " << max_pos << ")" << endl; - _ComputeStats(_accepted_packets[c], &count_sum, &count_min, &count_max, &min_pos, &max_pos); - rate_sum = (double)count_sum / time_delta; - rate_min = (double)count_min / time_delta; - rate_max = (double)count_max / time_delta; - rate_avg = rate_sum / (double)_nodes; - accepted_packets = count_sum; - cout << "Accepted packet rate average = " << rate_avg << endl - << "\tminimum = " << rate_min - << " (at node " << min_pos << ")" << endl - << "\tmaximum = " << rate_max - << " (at node " << max_pos << ")" << endl; - _ComputeStats(_sent_flits[c], &count_sum, &count_min, &count_max, &min_pos, &max_pos); - rate_sum = (double)count_sum / time_delta; - rate_min = (double)count_min / time_delta; - rate_max = (double)count_max / time_delta; - rate_avg = rate_sum / (double)_nodes; - sent_flits = count_sum; - cout << "Injected flit rate average = " << rate_avg << endl - << "\tminimum = " << rate_min - << " (at node " << min_pos << ")" << endl - << "\tmaximum = " << rate_max - << " (at node " << max_pos << ")" << endl; - _ComputeStats(_accepted_flits[c], &count_sum, &count_min, &count_max, &min_pos, &max_pos); - rate_sum = (double)count_sum / time_delta; - rate_min = (double)count_min / time_delta; - rate_max = (double)count_max / time_delta; - rate_avg = rate_sum / (double)_nodes; - accepted_flits = count_sum; - cout << "Accepted flit rate average= " << rate_avg << endl - << "\tminimum = " << rate_min - << " (at node " << min_pos << ")" << endl - << "\tmaximum = " << rate_max - << " (at node " << max_pos << ")" << endl; - - cout << "Injected packet length average = " << (double)sent_flits / (double)sent_packets << endl - << "Accepted packet length average = " << (double)accepted_flits / (double)accepted_packets << endl; - - cout << "Total in-flight flits = " << _total_in_flight_flits[c].size() - << " (" << _measured_in_flight_flits[c].size() << " measured)" - << endl; - -#ifdef TRACK_STALLS - _ComputeStats(_buffer_busy_stalls[c], &count_sum); - rate_sum = (double)count_sum / time_delta; - rate_avg = rate_sum / (double)(_subnets*_routers); - os << "Buffer busy stall rate = " << rate_avg << endl; - _ComputeStats(_buffer_conflict_stalls[c], &count_sum); - rate_sum = (double)count_sum / time_delta; - rate_avg = rate_sum / (double)(_subnets*_routers); - os << "Buffer conflict stall rate = " << rate_avg << endl; - _ComputeStats(_buffer_full_stalls[c], &count_sum); - rate_sum = (double)count_sum / time_delta; - rate_avg = rate_sum / (double)(_subnets*_routers); - os << "Buffer full stall rate = " << rate_avg << endl; - _ComputeStats(_buffer_reserved_stalls[c], &count_sum); - rate_sum = (double)count_sum / time_delta; - rate_avg = rate_sum / (double)(_subnets*_routers); - os << "Buffer reserved stall rate = " << rate_avg << endl; - _ComputeStats(_crossbar_conflict_stalls[c], &count_sum); - rate_sum = (double)count_sum / time_delta; - rate_avg = rate_sum / (double)(_subnets*_routers); - os << "Crossbar conflict stall rate = " << rate_avg << endl; -#endif - - } -} - -void TrafficManager::DisplayOverallStats( ostream & os ) const { - - os << "====== Overall Traffic Statistics ======" << endl; - for ( int c = 0; c < _classes; ++c ) { - - if(_measure_stats[c] == 0) { - continue; - } - - os << "====== Traffic class " << c << " ======" << endl; - - os << "Packet latency average = " << _overall_avg_plat[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tminimum = " << _overall_min_plat[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tmaximum = " << _overall_max_plat[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - - os << "Network latency average = " << _overall_avg_nlat[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tminimum = " << _overall_min_nlat[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tmaximum = " << _overall_max_nlat[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - - os << "Flit latency average = " << _overall_avg_flat[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tminimum = " << _overall_min_flat[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tmaximum = " << _overall_max_flat[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - - os << "Fragmentation average = " << _overall_avg_frag[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tminimum = " << _overall_min_frag[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tmaximum = " << _overall_max_frag[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - - os << "Injected packet rate average = " << _overall_avg_sent_packets[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tminimum = " << _overall_min_sent_packets[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tmaximum = " << _overall_max_sent_packets[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - - os << "Accepted packet rate average = " << _overall_avg_accepted_packets[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tminimum = " << _overall_min_accepted_packets[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tmaximum = " << _overall_max_accepted_packets[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - - os << "Injected flit rate average = " << _overall_avg_sent[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tminimum = " << _overall_min_sent[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tmaximum = " << _overall_max_sent[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - - os << "Accepted flit rate average = " << _overall_avg_accepted[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tminimum = " << _overall_min_accepted[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - os << "\tmaximum = " << _overall_max_accepted[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - - os << "Injected packet size average = " << _overall_avg_sent[c] / _overall_avg_sent_packets[c] - << " (" << _total_sims << " samples)" << endl; - - os << "Accepted packet size average = " << _overall_avg_accepted[c] / _overall_avg_accepted_packets[c] - << " (" << _total_sims << " samples)" << endl; - - os << "Hops average = " << _overall_hop_stats[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; - -#ifdef TRACK_STALLS - os << "Buffer busy stall rate = " << (double)_overall_buffer_busy_stalls[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl - << "Buffer conflict stall rate = " << (double)_overall_buffer_conflict_stalls[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl - << "Buffer full stall rate = " << (double)_overall_buffer_full_stalls[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl - << "Buffer reserved stall rate = " << (double)_overall_buffer_reserved_stalls[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl - << "Crossbar conflict stall rate = " << (double)_overall_crossbar_conflict_stalls[c] / (double)_total_sims - << " (" << _total_sims << " samples)" << endl; -#endif - - } - -} - -string TrafficManager::_OverallStatsCSV(int c) const -{ - ostringstream os; - os << _traffic[c] - << ',' << _use_read_write[c] - << ',' << _load[c] - << ',' << _overall_min_plat[c] / (double)_total_sims - << ',' << _overall_avg_plat[c] / (double)_total_sims - << ',' << _overall_max_plat[c] / (double)_total_sims - << ',' << _overall_min_nlat[c] / (double)_total_sims - << ',' << _overall_avg_nlat[c] / (double)_total_sims - << ',' << _overall_max_nlat[c] / (double)_total_sims - << ',' << _overall_min_flat[c] / (double)_total_sims - << ',' << _overall_avg_flat[c] / (double)_total_sims - << ',' << _overall_max_flat[c] / (double)_total_sims - << ',' << _overall_min_frag[c] / (double)_total_sims - << ',' << _overall_avg_frag[c] / (double)_total_sims - << ',' << _overall_max_frag[c] / (double)_total_sims - << ',' << _overall_min_sent_packets[c] / (double)_total_sims - << ',' << _overall_avg_sent_packets[c] / (double)_total_sims - << ',' << _overall_max_sent_packets[c] / (double)_total_sims - << ',' << _overall_min_accepted_packets[c] / (double)_total_sims - << ',' << _overall_avg_accepted_packets[c] / (double)_total_sims - << ',' << _overall_max_accepted_packets[c] / (double)_total_sims - << ',' << _overall_min_sent[c] / (double)_total_sims - << ',' << _overall_avg_sent[c] / (double)_total_sims - << ',' << _overall_max_sent[c] / (double)_total_sims - << ',' << _overall_min_accepted[c] / (double)_total_sims - << ',' << _overall_avg_accepted[c] / (double)_total_sims - << ',' << _overall_max_accepted[c] / (double)_total_sims - << ',' << _overall_avg_sent[c] / _overall_avg_sent_packets[c] - << ',' << _overall_avg_accepted[c] / _overall_avg_accepted_packets[c] - << ',' << _overall_hop_stats[c] / (double)_total_sims; - -#ifdef TRACK_STALLS - os << ',' << (double)_overall_buffer_busy_stalls[c] / (double)_total_sims - << ',' << (double)_overall_buffer_conflict_stalls[c] / (double)_total_sims - << ',' << (double)_overall_buffer_full_stalls[c] / (double)_total_sims - << ',' << (double)_overall_buffer_reserved_stalls[c] / (double)_total_sims - << ',' << (double)_overall_crossbar_conflict_stalls[c] / (double)_total_sims; -#endif - - return os.str(); -} - -void TrafficManager::DisplayOverallStatsCSV(ostream & os) const { - for(int c = 0; c < _classes; ++c) { - os << "results:" << c << ',' << _OverallStatsCSV() << endl; - } -} - -//read the watchlist -void TrafficManager::_LoadWatchList(const string & filename){ - ifstream watch_list; - watch_list.open(filename.c_str()); - - string line; - if(watch_list.is_open()) { - while(!watch_list.eof()) { - getline(watch_list, line); - if(line != "") { - if(line[0] == 'p') { - _packets_to_watch.insert(atoi(line.c_str()+1)); - } else { - _flits_to_watch.insert(atoi(line.c_str())); - } - } - } - - } else { - Error("Unable to open flit watch file: " + filename); - } -} - -int TrafficManager::_GetNextPacketSize(int cl) const -{ - assert(cl >= 0 && cl < _classes); - - vector const & psize = _packet_size[cl]; - int sizes = psize.size(); - - if(sizes == 1) { - return psize[0]; - } - - vector const & prate = _packet_size_rate[cl]; - int max_val = _packet_size_max_val[cl]; - - int pct = RandomInt(max_val); - - for(int i = 0; i < (sizes - 1); ++i) { - int const limit = prate[i]; - if(limit > pct) { - return psize[i]; - } else { - pct -= limit; - } - } - assert(prate.back() > pct); - return psize.back(); -} - -double TrafficManager::_GetAveragePacketSize(int cl) const -{ - vector const & psize = _packet_size[cl]; - int sizes = psize.size(); - if(sizes == 1) { - return (double)psize[0]; - } - vector const & prate = _packet_size_rate[cl]; - int sum = 0; - for(int i = 0; i < sizes; ++i) { - sum += psize[i] * prate[i]; - } - return (double)sum / (double)(_packet_size_max_val[cl] + 1); -} diff --git a/src/intersim2/.svn/pristine/8f/8fa65cdf95f29e2fd90afe3901d296d085ff768b.svn-base b/src/intersim2/.svn/pristine/8f/8fa65cdf95f29e2fd90afe3901d296d085ff768b.svn-base deleted file mode 100644 index bc0c5ba..0000000 --- a/src/intersim2/.svn/pristine/8f/8fa65cdf95f29e2fd90afe3901d296d085ff768b.svn-base +++ /dev/null @@ -1,43 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _BOOKSIM_HPP_ -#define _BOOKSIM_HPP_ - -#include -#include -#include -#include -#include -#ifdef _WIN32_ -#pragma warning (disable: 4786) -#include -#endif - -using namespace std; - -#endif diff --git a/src/intersim2/.svn/pristine/8f/8fca73abe4a7446a1a53687a6baca97dc056eabf.svn-base b/src/intersim2/.svn/pristine/8f/8fca73abe4a7446a1a53687a6baca97dc056eabf.svn-base deleted file mode 100644 index b1a60ea..0000000 --- a/src/intersim2/.svn/pristine/8f/8fca73abe4a7446a1a53687a6baca97dc056eabf.svn-base +++ /dev/null @@ -1,34 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#define main rng_double_main -#include "rng-double.c" - -double ranf_next( ) -{ - return ranf_arr_next( ); -} diff --git a/src/intersim2/.svn/pristine/8f/8fd71b46841aae63fcfe44908c2a1827741661fb.svn-base b/src/intersim2/.svn/pristine/8f/8fd71b46841aae63fcfe44908c2a1827741661fb.svn-base deleted file mode 100644 index a10b781..0000000 --- a/src/intersim2/.svn/pristine/8f/8fd71b46841aae63fcfe44908c2a1827741661fb.svn-base +++ /dev/null @@ -1,111 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// ---------------------------------------------------------------------- -// -// Arbiter: Base class for Matrix and Round Robin Arbiter -// -// ---------------------------------------------------------------------- - -#include "arbiter.hpp" -#include "roundrobin_arb.hpp" -#include "matrix_arb.hpp" -#include "tree_arb.hpp" - -#include -#include - -using namespace std ; - -Arbiter::Arbiter( Module *parent, const string &name, int size ) - : Module( parent, name ), - _size(size), _selected(-1), _highest_pri(numeric_limits::min()), - _best_input(-1), _num_reqs(0) -{ - _request.resize(size); - for ( int i = 0 ; i < size ; i++ ) - _request[i].valid = false ; -} - -void Arbiter::AddRequest( int input, int id, int pri ) -{ - assert( 0 <= input && input < _size ) ; - assert( !_request[input].valid ); - - _num_reqs++ ; - _request[input].valid = true ; - _request[input].id = id ; - _request[input].pri = pri ; -} - -int Arbiter::Arbitrate( int* id, int* pri ) -{ - if ( _selected != -1 ) { - if ( id ) - *id = _request[_selected].id ; - if ( pri ) - *pri = _request[_selected].pri ; - } - - assert((_selected >= 0) || (_num_reqs == 0)); - - return _selected ; -} - -void Arbiter::Clear() -{ - if(_num_reqs > 0) { - - // clear the request vector - for ( int i = 0; i < _size ; i++ ) - _request[i].valid = false ; - _num_reqs = 0 ; - _selected = -1; - } -} - -Arbiter *Arbiter::NewArbiter( Module *parent, const string& name, - const string &arb_type, int size) -{ - Arbiter *a = NULL; - if(arb_type == "round_robin") { - a = new RoundRobinArbiter( parent, name, size ); - } else if(arb_type == "matrix") { - a = new MatrixArbiter( parent, name, size ); - } else if(arb_type.substr(0, 5) == "tree(") { - size_t left = 4; - size_t middle = arb_type.find_first_of(','); - assert(middle != string::npos); - size_t right = arb_type.find_last_of(')'); - assert(right != string::npos); - string groups_str = arb_type.substr(left+1, middle-left-1); - int groups = atoi(groups_str.c_str()); - string sub_arb_type = arb_type.substr(middle+1, right-middle-1); - a = new TreeArbiter( parent, name, size, groups, sub_arb_type ); - } else assert(false); - return a; -} diff --git a/src/intersim2/.svn/pristine/90/90e277f393024f15eeb6e024bd34ac972b818aaf.svn-base b/src/intersim2/.svn/pristine/90/90e277f393024f15eeb6e024bd34ac972b818aaf.svn-base deleted file mode 100644 index 0fda1c1..0000000 --- a/src/intersim2/.svn/pristine/90/90e277f393024f15eeb6e024bd34ac972b818aaf.svn-base +++ /dev/null @@ -1,210 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - Neither the name of the Stanford University nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "booksim.hpp" -#include - -#include "maxsize.hpp" - -// shortest augmenting path: -// -// for all unmatched left nodes, -// push node onto work stack -// end -// -// for all j, -// from[j] = undefined -// end -// -// do, -// -// while( !stack.empty ), -// -// nl = stack.pop -// for each edge (nl,j), -// if ( ( lmatch[nl] != j ) && ( from[j] == undefined ) ), -// if ( rmatch[j] == undefined ), -// stop // augmenting path found -// else -// from[j] = nl -// newstack.push( rmatch[j] ) -// end -// end -// end -// end -// -// stack = newstack -// end -// - -//#define DEBUG_MAXSIZE -//#define PRINT_MATCHING - -MaxSizeMatch::MaxSizeMatch( Module *parent, const string& name, - int inputs, int outputs ) : - DenseAllocator( parent, name, inputs, outputs ) -{ - _from.resize(outputs); - _s = new int [inputs]; - _ns = new int [inputs]; - _prio = 0; -} - -MaxSizeMatch::~MaxSizeMatch( ) -{ - delete [] _s; - delete [] _ns; -} - -void MaxSizeMatch::Allocate( ) -{ - - // augment as many times as possible - // (this is an O(N^3) maximum-size matching algorithm) - while( _ShortestAugmenting( ) ); - - // next time, start at next input to ensure fairness - _prio = (_prio + 1) % _inputs; -} - - -bool MaxSizeMatch::_ShortestAugmenting( ) -{ - int i, j, jn; - int slen, nslen; - - // start with empty stack - slen = 0; - - // push all unassigned inputs to the stack - for ( i = 0; i < _inputs; ++i ) { - j = (i + _prio) % _inputs; - if ( _inmatch[j] == -1 ) { // start with unmatched left nodes - _s[slen++] = j; - } - } - - _from.assign(_inputs, -1); - - for ( int iter = 0; iter < _inputs; iter++ ) { - nslen = 0; - - for ( int e = 0; e < slen; ++e ) { - i = _s[e]; - - for ( j = 0; j < _outputs; ++j ) { - if ( ( _request[i][j].label != -1 ) && // edge (i,j) exists - ( _inmatch[i] != j ) && // (i,j) is not contained in the current matching - ( _from[j] == -1 ) ) { // no shorter path to j exists - - _from[j] = i; // how did we get to j? - -#ifdef DEBUG_MAXSIZE - cout << " got to " << j << " from " << i << endl; -#endif - if ( _outmatch[j] == -1 ) { // j is unmatched -- augmenting path found - goto found_augmenting; - } else { // j is matched - _ns[nslen] = _outmatch[j]; // add the destination of this edge to the leaf nodes - nslen++; - -#ifdef DEBUG_MAXSIZE - cout << " adding " << _outmatch[j] << endl; -#endif - } - } - } - } - - // no augmenting path found yet, swap stacks - int * t = _s; - _s = _ns; - _ns = t; - slen = nslen; - } - - return false; // no augmenting paths - - found_augmenting: - - // the augmenting path ends at node j on the right - -#ifdef DEBUG_MAXSIZE - cout << "Found path: " << j << "c <- "; -#endif - - i = _from[j]; - _outmatch[j] = i; - -#ifdef DEBUG_MAXSIZE - cout << i; -#endif - - while ( _inmatch[i] != -1 ) { // loop until the end of the path - jn = _inmatch[i]; // remove previous edge (i,jn) and add (i,j) - _inmatch[i] = j; - -#ifdef DEBUG_MAXSIZE - cout << " <- " << j << "c <- "; -#endif - - j = jn; // add edge from (jn,in) - i = _from[j]; - _outmatch[j] = i; - -#ifdef DEBUG_MAXSIZE - cout << i; -#endif - } - -#ifdef DEBUG_MAXSIZE - cout << endl; -#endif - - _inmatch[i] = j; - -#ifdef PRINT_MATCHING - cout << "left matching: "; - - for ( i = 0; i < _inputs; i++ ) { - cout << _inmatch[i] << " "; - } - cout << endl; - - cout << "right matching: "; - for ( i = 0; i < _outputs; i++ ) { - cout << _outmatch[i] << " "; - } - cout << endl; -#endif - - return true; -} diff --git a/src/intersim2/.svn/pristine/90/90f780ee11bbe517547a3648019db3592a5e7675.svn-base b/src/intersim2/.svn/pristine/90/90f780ee11bbe517547a3648019db3592a5e7675.svn-base deleted file mode 100644 index 8cdb445..0000000 --- a/src/intersim2/.svn/pristine/90/90f780ee11bbe517547a3648019db3592a5e7675.svn-base +++ /dev/null @@ -1,88 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/*module.cpp - * - *The basic class that is extended by all other components of the network - *Provides the basic hierarchy structure and basic fuctions - * - */ - -#include -#include - -#include "booksim.hpp" -#include "module.hpp" - -Module::Module( Module *parent, const string& name ) -{ - _name = name; - - if ( parent ) { - parent->_AddChild( this ); - _fullname = parent->_fullname + "/" + name; - } else { - _fullname = name; - } -} - -void Module::_AddChild( Module *child ) -{ - _children.push_back( child ); -} - -void Module::DisplayHierarchy( int level, ostream & os ) const -{ - vector::const_iterator mod_iter; - - for ( int l = 0; l < level; l++ ) { - os << " "; - } - - os << _name << endl; - - for ( mod_iter = _children.begin( ); - mod_iter != _children.end( ); mod_iter++ ) { - (*mod_iter)->DisplayHierarchy( level + 1 ); - } -} - -void Module::Error( const string& msg ) const -{ - cout << "Error in " << _fullname << " : " << msg << endl; - exit( -1 ); -} - -void Module::Debug( const string& msg ) const -{ - cout << "Debug (" << _fullname << ") : " << msg << endl; -} - -void Module::Display( ostream & os ) const -{ - os << "Display method not implemented for " << _fullname << endl; -} diff --git a/src/intersim2/.svn/pristine/94/941911d54bdc048828d97698138c156dd9becc6c.svn-base b/src/intersim2/.svn/pristine/94/941911d54bdc048828d97698138c156dd9becc6c.svn-base deleted file mode 100644 index 715878a..0000000 --- a/src/intersim2/.svn/pristine/94/941911d54bdc048828d97698138c156dd9becc6c.svn-base +++ /dev/null @@ -1,69 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -//////////////////////////////////////////////////////////////////////// -// -// QTree: A Quad-Tree Indirect Network. -// -// -//////////////////////////////////////////////////////////////////////// -// -// RCS Information: -// $Author: jbalfour $ -// $Date: 2007/05/17 17:14:07 $ -// $Id$ -// -//////////////////////////////////////////////////////////////////////// - -#ifndef _QTREE_HPP_ -#define _QTREE_HPP_ -#include -#include "network.hpp" - -class QTree : public Network { - - int _k; - int _n; - - void _ComputeSize( const Configuration& config ); - void _BuildNet( const Configuration& config ); - - int _RouterIndex( int height, int pos ); - int _InputIndex( int height, int pos, int port ); - int _OutputIndex( int height, int pos, int port ); - -public: - - QTree( const Configuration& config, const string & name ); - static void RegisterRoutingFunctions() ; - - static int HeightFromID( int id ); - static int PosFromID( int id ); - -}; - -#endif diff --git a/src/intersim2/.svn/pristine/95/9532d33b08220b7f51a001451336e589a0a92e97.svn-base b/src/intersim2/.svn/pristine/95/9532d33b08220b7f51a001451336e589a0a92e97.svn-base deleted file mode 100644 index 2afa56a..0000000 --- a/src/intersim2/.svn/pristine/95/9532d33b08220b7f51a001451336e589a0a92e97.svn-base +++ /dev/null @@ -1,69 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _ANYNET_HPP_ -#define _ANYNET_HPP_ - -#include "network.hpp" -#include "routefunc.hpp" -#include -#include -#include -#include - -class AnyNet : public Network { - - string file_name; - //associtation between nodes and routers - map node_list; - //[link type][src router][dest router]=(port, latency) - vector > > > router_list; - //stores minimal routing information from every router to every node - //[router][dest_node]=port - vector > routing_table; - - void _ComputeSize( const Configuration &config ); - void _BuildNet( const Configuration &config ); - void readFile(); - void buildRoutingTable(); - void route(int r_start); - -public: - AnyNet( const Configuration &config, const string & name ); - ~AnyNet(); - - int GetN( ) const{ return -1;} - int GetK( ) const{ return -1;} - - static void RegisterRoutingFunctions(); - double Capacity( ) const {return -1;} - void InsertRandomFaults( const Configuration &config ){} -}; - -void min_anynet( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ); -#endif diff --git a/src/intersim2/.svn/pristine/96/968162a2f3ef193e7baffadd696d73fccaf5d69c.svn-base b/src/intersim2/.svn/pristine/96/968162a2f3ef193e7baffadd696d73fccaf5d69c.svn-base deleted file mode 100644 index 70c9052..0000000 --- a/src/intersim2/.svn/pristine/96/968162a2f3ef193e7baffadd696d73fccaf5d69c.svn-base +++ /dev/null @@ -1,160 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "booksim.hpp" -#include - -#include "prio_arb.hpp" - - -PriorityArbiter::PriorityArbiter( const Configuration &config, - Module *parent, const string& name, - int inputs ) -: Module( parent, name ), _rr_ptr(0), _inputs( inputs ) -{ - -} - -void PriorityArbiter::Clear( ) -{ - _requests.clear( ); -} - -void PriorityArbiter::AddRequest( int in, int label, int pri ) -{ - sRequest r; - list::iterator insert_point; - - r.in = in; r.label = label; r.pri = pri; - - insert_point = _requests.begin( ); - while( ( insert_point != _requests.end( ) ) && - ( insert_point->in < in ) ) { - insert_point++; - } - - bool del = false; - bool add = true; - - // For consistant behavior, delete the existing request - // if it is for the same input and has a higher - // priority - - if ( ( insert_point != _requests.end( ) ) && - ( insert_point->in == in ) ) { - if ( insert_point->pri < pri ) { - del = true; - } else { - add = false; - } - } - - if ( add ) { - _requests.insert( insert_point, r ); - } - - if ( del ) { - _requests.erase( insert_point ); - } -} - -void PriorityArbiter::RemoveRequest( int in, int label ) -{ - list::iterator erase_point; - - erase_point = _requests.begin( ); - while( ( erase_point != _requests.end( ) ) && - ( erase_point->in < in ) ) { - erase_point++; - } - - assert( erase_point != _requests.end( ) ); - _requests.erase( erase_point ); -} - -int PriorityArbiter::Match( ) const -{ - return _match; -} - -void PriorityArbiter::Arbitrate( ) -{ - list::iterator p; - - int max_index, max_pri; - bool wrapped; - - //MERGENOTE - //booksim does not have this if statement - //as far as I can tell they are identical in function - if ( _requests.begin( ) != _requests.end( ) ) { - // A round-robin arbiter between input requests - p = _requests.begin( ); - while( ( p != _requests.end( ) ) && - ( p->in < _rr_ptr ) ) { - p++; - } - - max_index = -1; - max_pri = 0; - - wrapped = false; - while( (!wrapped) || ( p->in < _rr_ptr ) ) { - if ( p == _requests.end( ) ) { - if ( wrapped ) { break; } - // p is valid here because empty lists - // are skipped (above) - p = _requests.begin( ); - wrapped = true; - } - - // check if request is the highest priority so far - if ( ( p->pri > max_pri ) || ( max_index == -1 ) ) { - max_pri = p->pri; - max_index = p->in; - } - - p++; - } - - _match = max_index; // -1 for no match - if ( _match != -1 ) { - _rr_ptr = ( _match + 1 ) % _inputs; - } - - } else { - _match = -1; - } -} - -//MERGENOTE -//added update function to priorityarbiter - -void PriorityArbiter::Update( ) -{ - _rr_ptr = ( _rr_ptr + 1 ) % _inputs; -} diff --git a/src/intersim2/.svn/pristine/97/9709aa53e9b91e3103a5c627cfd4c83d5857c451.svn-base b/src/intersim2/.svn/pristine/97/9709aa53e9b91e3103a5c627cfd4c83d5857c451.svn-base deleted file mode 100644 index e262f47..0000000 --- a/src/intersim2/.svn/pristine/97/9709aa53e9b91e3103a5c627cfd4c83d5857c451.svn-base +++ /dev/null @@ -1,187 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _EVENT_ROUTER_HPP_ -#define _EVENT_ROUTER_HPP_ - -#include -#include -#include - -#include "module.hpp" -#include "router.hpp" -#include "buffer.hpp" -#include "vc.hpp" -#include "prio_arb.hpp" -#include "routefunc.hpp" -#include "outputset.hpp" -#include "pipefifo.hpp" - -class EventNextVCState : public Module { -public: - enum eNextVCState { idle, busy, tail_pending }; - - struct tWaiting { - int input; - int vc; - int id; - int pres; - bool watch; - }; - -private: - int _buf_size; - int _vcs; - - vector _credits; - vector _presence; - vector _input; - vector _inputVC; - - vector > _waiting; - - vector _state; - -public: - - EventNextVCState( const Configuration& config, - Module *parent, const string& name ); - - eNextVCState GetState( int vc ) const; - int GetPresence( int vc ) const; - int GetCredits( int vc ) const; - int GetInput( int vc ) const; - int GetInputVC( int vc ) const; - - bool IsWaiting( int vc ) const; - bool IsInputWaiting( int vc, int w_input, int w_vc ) const; - - void PushWaiting( int vc, tWaiting *w ); - void IncrWaiting( int vc, int w_input, int w_vc ); - tWaiting *PopWaiting( int vc ); - - void SetState( int vc, eNextVCState state ); - void SetCredits( int vc, int value ); - void SetPresence( int vc, int value ); - void SetInput( int vc, int input ); - void SetInputVC( int vc, int in_vc ); -}; - -class EventRouter : public Router { - int _vcs; - - int _vct; - - vector _buf; - vector > _active; - - tRoutingFunction _rf; - - vector _output_state; - - PipelineFIFO *_crossbar_pipe; - PipelineFIFO *_credit_pipe; - - vector > _input_buffer; - vector > _output_buffer; - - vector > _in_cred_buffer; - vector > _out_cred_buffer; - - struct tArrivalEvent { - int input; - int output; - int src_vc; - int dst_vc; - bool head; - bool tail; - - int id; // debug - bool watch; // debug - }; - - PipelineFIFO *_arrival_pipe; - vector > _arrival_queue; - vector _arrival_arbiter; - - struct tTransportEvent { - int input; - int src_vc; - int dst_vc; - - int id; // debug - bool watch; // debug - }; - - vector > _transport_queue; - vector _transport_arbiter; - - vector _transport_free; - vector _transport_match; - - void _ReceiveFlits( ); - void _ReceiveCredits( ); - - void _IncomingFlits( ); - void _ArrivalRequests( int input ); - void _ArrivalArb( int output ); - void _SendTransport( int input, int output, tArrivalEvent *aevt ); - void _ProcessWaiting( int output, int out_vc ); - void _TransportRequests( int output ); - void _TransportArb( int input ); - void _OutputQueuing( ); - - void _SendFlits( ); - void _SendCredits( ); - - virtual void _InternalStep( ); - -public: - EventRouter( const Configuration& config, - Module *parent, const string & name, int id, - int inputs, int outputs ); - virtual ~EventRouter( ); - - virtual void ReadInputs( ); - virtual void WriteOutputs( ); - - virtual int GetUsedCredit(int o) const {return 0;} - virtual int GetBufferOccupancy(int i) const {return 0;} - -#ifdef TRACK_BUFFERS - virtual int GetUsedCreditForClass(int output, int cl) const {return 0;} - virtual int GetBufferOccupancyForClass(int input, int cl) const {return 0;} -#endif - - virtual vector UsedCredits() const { return vector(); } - virtual vector FreeCredits() const { return vector(); } - virtual vector MaxCredits() const { return vector(); } - - void Display( ostream & os = cout ) const; -}; - -#endif diff --git a/src/intersim2/.svn/pristine/9a/9a6a33f2fd931773aa82485ef360d84c227abb12.svn-base b/src/intersim2/.svn/pristine/9a/9a6a33f2fd931773aa82485ef360d84c227abb12.svn-base deleted file mode 100644 index 98d07bb..0000000 --- a/src/intersim2/.svn/pristine/9a/9a6a33f2fd931773aa82485ef360d84c227abb12.svn-base +++ /dev/null @@ -1,76 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -//////////////////////////////////////////////////////////////////////// -// -// FatTree -// -//////////////////////////////////////////////////////////////////////// -// -// RCS Information: -// $Author: jbalfour $ -// $Date: 2007/06/26 22:49:23 $ -// $Id$ -// -//////////////////////////////////////////////////////////////////////// - -#ifndef _FatTree_HPP_ -#define _FatTree_HPP_ - -#include "network.hpp" - -class FatTree : public Network { - - int _k; - int _n; - - - void _ComputeSize( const Configuration& config ); - void _BuildNet( const Configuration& config ); - - Router*& _Router( int depth, int pos ); - - int _mapSize; - int* _inputChannelMap; - int* _outputChannelMap; - int* _latencyMap; - - - -public: - - FatTree( const Configuration& config ,const string & name ); - static void RegisterRoutingFunctions() ; - - // - // Methods to Assit Routing Functions - // - static int PreferedPort( const Router* r, int index ); - -}; - -#endif diff --git a/src/intersim2/.svn/pristine/9a/9a75723858a7c299341d4e68fbb1581f9865b898.svn-base b/src/intersim2/.svn/pristine/9a/9a75723858a7c299341d4e68fbb1581f9865b898.svn-base deleted file mode 100644 index c0bdc89..0000000 --- a/src/intersim2/.svn/pristine/9a/9a75723858a7c299341d4e68fbb1581f9865b898.svn-base +++ /dev/null @@ -1,47 +0,0 @@ -// $Id$ - -// Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -//concentrated mesh configuration file running batch mode -//xr, yr, x, y, are use to indicate how the concnetration is formed. - -topology = cmesh; - -k = 4; -n = 2; -c = 4; -xr = 2; -yr = 2; - -x = 4; -y = 4; - -routing_function = dor_no_express; - -traffic = bitcomp; - -use_read_write = 0; - -batch_size = 2000; diff --git a/src/intersim2/.svn/pristine/9a/9aed09bfc8ce0fffa6872c93917412c0577120c2.svn-base b/src/intersim2/.svn/pristine/9a/9aed09bfc8ce0fffa6872c93917412c0577120c2.svn-base deleted file mode 100644 index 1d446a5..0000000 --- a/src/intersim2/.svn/pristine/9a/9aed09bfc8ce0fffa6872c93917412c0577120c2.svn-base +++ /dev/null @@ -1,322 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _TRAFFICMANAGER_HPP_ -#define _TRAFFICMANAGER_HPP_ - -#include -#include -#include -#include - -#include "module.hpp" -#include "config_utils.hpp" -#include "network.hpp" -#include "flit.hpp" -#include "buffer_state.hpp" -#include "stats.hpp" -#include "traffic.hpp" -#include "routefunc.hpp" -#include "outputset.hpp" -#include "injection.hpp" - -//register the requests to a node -class PacketReplyInfo; - -class TrafficManager : public Module { - -private: - - vector > _packet_size; - vector > _packet_size_rate; - vector _packet_size_max_val; - -protected: - int _nodes; - int _routers; - int _vcs; - - vector _net; - vector > _router; - - // ============ Traffic ============ - - int _classes; - - vector _load; - - vector _use_read_write; - vector _write_fraction; - - vector _read_request_size; - vector _read_reply_size; - vector _write_request_size; - vector _write_reply_size; - - vector _traffic; - - vector _class_priority; - - vector > _last_class; - - vector _traffic_pattern; - vector _injection_process; - - // ============ Message priorities ============ - - enum ePriority { class_based, age_based, network_age_based, local_age_based, queue_length_based, hop_count_based, sequence_based, none }; - - ePriority _pri_type; - - // ============ Injection VC states ============ - - vector > _buf_states; -#ifdef TRACK_FLOWS - vector > > _outstanding_credits; - vector > > > _outstanding_classes; -#endif - vector > > _last_vc; - - // ============ Routing ============ - - tRoutingFunction _rf; - bool _lookahead_routing; - bool _noq; - - // ============ Injection queues ============ - - vector > _qtime; - vector > _qdrained; - vector > > _partial_packets; - - vector > _total_in_flight_flits; - vector > _measured_in_flight_flits; - vector > _retired_packets; - bool _empty_network; - - bool _hold_switch_for_packet; - - // ============ physical sub-networks ========== - - int _subnets; - - vector _subnet; - - // ============ deadlock ========== - - int _deadlock_timer; - int _deadlock_warn_timeout; - - // ============ request & replies ========================== - - vector _packet_seq_no; - vector > _repliesPending; - vector _requestsOutstanding; - - // ============ Statistics ============ - - vector _plat_stats; - vector _overall_min_plat; - vector _overall_avg_plat; - vector _overall_max_plat; - - vector _nlat_stats; - vector _overall_min_nlat; - vector _overall_avg_nlat; - vector _overall_max_nlat; - - vector _flat_stats; - vector _overall_min_flat; - vector _overall_avg_flat; - vector _overall_max_flat; - - vector _frag_stats; - vector _overall_min_frag; - vector _overall_avg_frag; - vector _overall_max_frag; - - vector > _pair_plat; - vector > _pair_nlat; - vector > _pair_flat; - - vector _hop_stats; - vector _overall_hop_stats; - - vector > _sent_packets; - vector _overall_min_sent_packets; - vector _overall_avg_sent_packets; - vector _overall_max_sent_packets; - vector > _accepted_packets; - vector _overall_min_accepted_packets; - vector _overall_avg_accepted_packets; - vector _overall_max_accepted_packets; - vector > _sent_flits; - vector _overall_min_sent; - vector _overall_avg_sent; - vector _overall_max_sent; - vector > _accepted_flits; - vector _overall_min_accepted; - vector _overall_avg_accepted; - vector _overall_max_accepted; - -#ifdef TRACK_STALLS - vector > _buffer_busy_stalls; - vector > _buffer_conflict_stalls; - vector > _buffer_full_stalls; - vector > _buffer_reserved_stalls; - vector > _crossbar_conflict_stalls; - vector _overall_buffer_busy_stalls; - vector _overall_buffer_conflict_stalls; - vector _overall_buffer_full_stalls; - vector _overall_buffer_reserved_stalls; - vector _overall_crossbar_conflict_stalls; -#endif - - vector _slowest_packet; - vector _slowest_flit; - - map _stats; - - // ============ Simulation parameters ============ - - enum eSimState { warming_up, running, draining, done }; - eSimState _sim_state; - - bool _measure_latency; - - int _reset_time; - int _drain_time; - - int _total_sims; - int _sample_period; - int _max_samples; - int _warmup_periods; - - int _include_queuing; - - vector _measure_stats; - bool _pair_stats; - - vector _latency_thres; - - vector _stopping_threshold; - vector _acc_stopping_threshold; - - vector _warmup_threshold; - vector _acc_warmup_threshold; - - int _cur_id; - int _cur_pid; - int _time; - - set _flits_to_watch; - set _packets_to_watch; - - bool _print_csv_results; - - //flits to watch - ostream * _stats_out; - -#ifdef TRACK_FLOWS - vector > _injected_flits; - vector > _ejected_flits; - ostream * _injected_flits_out; - ostream * _received_flits_out; - ostream * _stored_flits_out; - ostream * _sent_flits_out; - ostream * _outstanding_credits_out; - ostream * _ejected_flits_out; - ostream * _active_packets_out; -#endif - -#ifdef TRACK_CREDITS - ostream * _used_credits_out; - ostream * _free_credits_out; - ostream * _max_credits_out; -#endif - - // ============ Internal methods ============ -protected: - - virtual void _RetireFlit( Flit *f, int dest ); - - void _Inject(); - void _Step( ); - - bool _PacketsOutstanding( ) const; - - virtual int _IssuePacket( int source, int cl ); - void _GeneratePacket( int source, int size, int cl, int time ); - - virtual void _ClearStats( ); - - void _ComputeStats( const vector & stats, int *sum, int *min = NULL, int *max = NULL, int *min_pos = NULL, int *max_pos = NULL ) const; - - virtual bool _SingleSim( ); - - void _DisplayRemaining( ostream & os = cout ) const; - - void _LoadWatchList(const string & filename); - - virtual void _UpdateOverallStats(); - - virtual string _OverallStatsCSV(int c = 0) const; - - int _GetNextPacketSize(int cl) const; - double _GetAveragePacketSize(int cl) const; - -public: - - static TrafficManager * New(Configuration const & config, - vector const & net); - - TrafficManager( const Configuration &config, const vector & net ); - virtual ~TrafficManager( ); - - bool Run( ); - - virtual void WriteStats( ostream & os = cout ) const ; - virtual void UpdateStats( ) ; - virtual void DisplayStats( ostream & os = cout ) const ; - virtual void DisplayOverallStats( ostream & os = cout ) const ; - virtual void DisplayOverallStatsCSV( ostream & os = cout ) const ; - - inline int getTime() { return _time;} - Stats * getStats(const string & name) { return _stats[name]; } - -}; - -template -ostream & operator<<(ostream & os, const vector & v) { - for(size_t i = 0; i < v.size() - 1; ++i) { - os << v[i] << ","; - } - os << v[v.size()-1]; - return os; -} - -#endif diff --git a/src/intersim2/.svn/pristine/9b/9b149c35e1f088a947ef877a58c79300dd5b074e.svn-base b/src/intersim2/.svn/pristine/9b/9b149c35e1f088a947ef877a58c79300dd5b074e.svn-base deleted file mode 100644 index 8409322..0000000 --- a/src/intersim2/.svn/pristine/9b/9b149c35e1f088a947ef877a58c79300dd5b074e.svn-base +++ /dev/null @@ -1,103 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// ---------------------------------------------------------------------- -// -// SeparableInputFirstAllocator: Separable Input-First Allocator -// -// ---------------------------------------------------------------------- - -#include "separable_input_first.hpp" - -#include "booksim.hpp" -#include "arbiter.hpp" - -#include -#include -#include - -SeparableInputFirstAllocator:: -SeparableInputFirstAllocator( Module* parent, const string& name, int inputs, - int outputs, const string& arb_type ) - : SeparableAllocator( parent, name, inputs, outputs, arb_type ) -{} - -void SeparableInputFirstAllocator::Allocate() { - - set::const_iterator port_iter = _in_occ.begin(); - while(port_iter != _in_occ.end()) { - - const int & input = *port_iter; - - // add requests to the input arbiter - - map::const_iterator req_iter = _in_req[input].begin(); - while(req_iter != _in_req[input].end()) { - - const sRequest & req = req_iter->second; - - _input_arb[input]->AddRequest(req.port, req.label, req.in_pri); - - ++req_iter; - } - - // Execute the input arbiters and propagate the grants to the - // output arbiters. - - int label = -1; - const int output = _input_arb[input]->Arbitrate(&label, NULL); - assert(output > -1); - - const sRequest & req = _out_req[output][input]; - assert((req.port == input) && (req.label == label)); - - _output_arb[output]->AddRequest(req.port, req.label, req.out_pri); - - ++port_iter; - } - - port_iter = _out_occ.begin(); - while(port_iter != _out_occ.end()) { - - const int & output = *port_iter; - - // Execute the output arbiters. - - const int input = _output_arb[output]->Arbitrate(NULL, NULL); - - if(input > -1) { - assert((_inmatch[input] == -1) && (_outmatch[output] == -1)); - - _inmatch[input] = output ; - _outmatch[output] = input ; - _input_arb[input]->UpdateState() ; - _output_arb[output]->UpdateState() ; - } - - ++port_iter; - } -} diff --git a/src/intersim2/.svn/pristine/9e/9ee6cbb1a61d3f7c2992c673ad86d0ed1d245ef8.svn-base b/src/intersim2/.svn/pristine/9e/9ee6cbb1a61d3f7c2992c673ad86d0ed1d245ef8.svn-base deleted file mode 100644 index ec440d8..0000000 --- a/src/intersim2/.svn/pristine/9e/9ee6cbb1a61d3f7c2992c673ad86d0ed1d245ef8.svn-base +++ /dev/null @@ -1,116 +0,0 @@ -// $Id$ - -// Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -//A flattened butterfly configurate file with many tweaks from the -//default settings. - - -// Flow control -// Total number of VCs must match the above assignments -num_vcs = 8; -vc_buf_size = 4; - -wait_for_tail_credit = 0; - -// -// Router architectureq -// -vc_allocator = islip; -sw_allocator = islip; -alloc_iters = 1; - -credit_delay = 2; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; -st_final_delay = 1; - -input_speedup = 1; -output_speedup = 1; -internal_speedup = 1.0; - -// -// Traffic -// - -warmup_periods = 3; - -sample_period = 1000; - -sim_count = 1; - -traffic = uniform; - - -// Flatfly -// -// #node = k^(n+1) -// -// x, y, specifies the arrangement of routers in x and y dim -// xr, yr specifiies the arayment of clients in a router -// -topology = flatfly; -subnets = 1; - -c = 4; -k = 4; -n = 2; - -x = 4; -y = 4; -xr = 2; -yr = 2; - -// -// Routing -// - -routing_function = ran_min; - -//1: batch mode, 0: injection mode -use_read_write = 0; - -//for injection mode -packet_size = 1; -injection_rate = 0.1; - -//for batch mode -read_request_size=1; -write_request_size=1; -read_reply_size=1; -write_reply_size=1; - -read_request_begin_vc = 0; -read_request_end_vc = 3; -write_reply_begin_vc = 4; -write_reply_end_vc = 7; -read_reply_begin_vc = 4; -read_reply_end_vc = 7; -write_request_begin_vc = 0; -write_request_end_vc = 3; - -//latency: drains all packet, throughput:no drain? -sim_type = latency; diff --git a/src/intersim2/.svn/pristine/9f/9f3bdc5b32d0fd02e717f7a9c517e280355586fb.svn-base b/src/intersim2/.svn/pristine/9f/9f3bdc5b32d0fd02e717f7a9c517e280355586fb.svn-base deleted file mode 100644 index 748506d..0000000 --- a/src/intersim2/.svn/pristine/9f/9f3bdc5b32d0fd02e717f7a9c517e280355586fb.svn-base +++ /dev/null @@ -1,103 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// ---------------------------------------------------------------------- -// -// SeparableOutputFirstAllocator: Separable Output-First Allocator -// -// ---------------------------------------------------------------------- - -#include "separable_output_first.hpp" - -#include "booksim.hpp" -#include "arbiter.hpp" - -#include -#include -#include - -SeparableOutputFirstAllocator:: -SeparableOutputFirstAllocator( Module* parent, const string& name, int inputs, - int outputs, const string& arb_type ) - : SeparableAllocator( parent, name, inputs, outputs, arb_type ) -{} - -void SeparableOutputFirstAllocator::Allocate() { - - set::const_iterator port_iter = _out_occ.begin(); - while(port_iter != _out_occ.end()) { - - const int & output = *port_iter; - - // add requests to the output arbiter - - map::const_iterator req_iter = _out_req[output].begin(); - while(req_iter != _out_req[output].end()) { - - const sRequest & req = req_iter->second; - - _output_arb[output]->AddRequest(req.port, req.label, req.out_pri); - - ++req_iter; - } - - // Execute the output arbiter and propagate the grants to the - // input arbiters. - - int label = -1; - const int input = _output_arb[output]->Arbitrate(&label, NULL); - assert(input > -1); - - const sRequest & req = _in_req[input][output]; - assert((req.port == output) && (req.label == label)); - - _input_arb[input]->AddRequest(req.port, req.label, req.in_pri); - - ++port_iter; - } - - port_iter = _in_occ.begin(); - while(port_iter != _in_occ.end()) { - - const int & input = *port_iter; - - // Execute the input arbiters. - - const int output = _input_arb[input]->Arbitrate(NULL, NULL); - - if(output > -1) { - assert((_inmatch[input] == -1) && (_outmatch[output] == -1)); - - _inmatch[input] = output; - _outmatch[output] = input; - _input_arb[input]->UpdateState() ; - _output_arb[output]->UpdateState() ; - } - - ++port_iter; - } -} diff --git a/src/intersim2/.svn/pristine/a4/a4359ad59061eaed8a442687bbf1e8693be96a72.svn-base b/src/intersim2/.svn/pristine/a4/a4359ad59061eaed8a442687bbf1e8693be96a72.svn-base deleted file mode 100644 index dccabf7..0000000 --- a/src/intersim2/.svn/pristine/a4/a4359ad59061eaed8a442687bbf1e8693be96a72.svn-base +++ /dev/null @@ -1,68 +0,0 @@ -// $Id$ - -// Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -//8X8 mesh with 20 flits per packet under injection mode -//injection rate here is packet per cycle, NOT flit per cycle - -// Topology - -topology = mesh; -k = 8; -n = 2; - -// Routing -routing_function = dor; - -// Flow control -num_vcs = 8; -vc_buf_size = 8; -wait_for_tail_credit = 1; - -// Router architecture -vc_allocator = islip; -sw_allocator = islip; -alloc_iters = 1; - -credit_delay = 2; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - - -// Traffic -traffic = transpose; -packet_size = 20; - - -// Simulation -sim_type = latency; - -injection_rate = 0.005; - diff --git a/src/intersim2/.svn/pristine/ad/ad824944d4de71c9e947f9e386f12aa8c6ec4355.svn-base b/src/intersim2/.svn/pristine/ad/ad824944d4de71c9e947f9e386f12aa8c6ec4355.svn-base deleted file mode 100644 index c05ef50..0000000 --- a/src/intersim2/.svn/pristine/ad/ad824944d4de71c9e947f9e386f12aa8c6ec4355.svn-base +++ /dev/null @@ -1,104 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _FLIT_HPP_ -#define _FLIT_HPP_ - -#include -#include - -#include "booksim.hpp" -#include "outputset.hpp" - -class Flit { - -public: - - const static int NUM_FLIT_TYPES = 5; - enum FlitType { READ_REQUEST = 0, - READ_REPLY = 1, - WRITE_REQUEST = 2, - WRITE_REPLY = 3, - ANY_TYPE = 4 }; - FlitType type; - - int vc; - - int cl; - - bool head; - bool tail; - - int ctime; - int itime; - int atime; - - int id; - int pid; - - bool record; - - int src; - int dest; - - int pri; - - int hops; - bool watch; - int subnetwork; - - // intermediate destination (if any) - mutable int intm; - - // phase in multi-phase algorithms - mutable int ph; - - // Fields for arbitrary data - void* data ; - - // Lookahead route info - OutputSet la_route_set; - - void Reset(); - - static Flit * New(); - void Free(); - static void FreeAll(); - -private: - - Flit(); - ~Flit() {} - - static stack _all; - static stack _free; - -}; - -ostream& operator<<( ostream& os, const Flit& f ); - -#endif diff --git a/src/intersim2/.svn/pristine/af/afde60b791408b0db1c56c113ccfe45105b846eb.svn-base b/src/intersim2/.svn/pristine/af/afde60b791408b0db1c56c113ccfe45105b846eb.svn-base deleted file mode 100644 index 665e5b3..0000000 --- a/src/intersim2/.svn/pristine/af/afde60b791408b0db1c56c113ccfe45105b846eb.svn-base +++ /dev/null @@ -1,119 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// ---------------------------------------------------------------------- -// -// TreeArbiter -// -// ---------------------------------------------------------------------- - -#include "tree_arb.hpp" -#include -#include - -using namespace std ; - -TreeArbiter::TreeArbiter( Module *parent, const string &name, - int size, int groups, const string & arb_type ) - : Arbiter( parent, name, size ) { - assert(size % groups == 0); - _group_arbiters.resize(groups); - _group_reqs.resize(groups, 0); - _group_size = size / groups; - for(int i = 0; i < groups; ++i) { - ostringstream group_arb_name; - group_arb_name << "group_arb" << i; - _group_arbiters[i] = Arbiter::NewArbiter(this, group_arb_name.str(), arb_type, _group_size); - } - _global_arbiter = Arbiter::NewArbiter(this, "global_arb", arb_type, groups); -} - -TreeArbiter::~TreeArbiter() { - for(int i = 0; i < (int)_group_arbiters.size(); ++i) { - delete _group_arbiters[i]; - } - delete _global_arbiter; -} - -void TreeArbiter::PrintState() const { - for(int i = 0; i < (int)_group_arbiters.size(); ++i) { - cout << "Group arbiter " << i << ":" << endl; - _group_arbiters[i]->PrintState(); - } - cout << "Global arbiter:" << endl; - _global_arbiter->PrintState(); -} - -void TreeArbiter::UpdateState() { - if(_selected > -1) { - int last_winner = _global_arbiter->LastWinner(); - assert(last_winner >= 0 && last_winner < (int)_group_arbiters.size()); - _group_arbiters[last_winner]->UpdateState(); - _global_arbiter->UpdateState(); - } -} - -void TreeArbiter::AddRequest( int input, int id, int pri ) -{ - Arbiter::AddRequest(input, id, pri); - int group_index = input / _group_size; - _group_arbiters[group_index]->AddRequest( input % _group_size, id, pri ); - ++_group_reqs[group_index]; -} - -int TreeArbiter::Arbitrate( int* id, int* pri ) { - if(!_num_reqs) { - return -1; - } - for(int i = 0; i < (int)_group_arbiters.size(); ++i) { - if(_group_reqs[i]) { - int group_id, group_pri; - _group_arbiters[i]->Arbitrate(&group_id, &group_pri); - _global_arbiter->AddRequest(i, group_id, group_pri); - } - } - int group = _global_arbiter->Arbitrate(NULL, NULL); - assert(group >= 0 && group < (int)_group_arbiters.size()); - int group_sel = _group_arbiters[group]->LastWinner(); - assert(group_sel >= 0 && group_sel < _group_size); - _selected = group * _group_size + group_sel; - assert(_selected >= 0 && _selected < _size); - return Arbiter::Arbitrate(id, pri); -} - -void TreeArbiter::Clear() -{ - if(!_num_reqs) { - return; - } - for(int i = 0; i < (int)_group_arbiters.size(); ++i) { - _group_arbiters[i]->Clear(); - _group_reqs[i] = 0; - } - _global_arbiter->Clear(); - Arbiter::Clear(); -} diff --git a/src/intersim2/.svn/pristine/b0/b0621120b70fa66b06fa3e7adc9b386974b8c0c3.svn-base b/src/intersim2/.svn/pristine/b0/b0621120b70fa66b06fa3e7adc9b386974b8c0c3.svn-base deleted file mode 100644 index 21c879a..0000000 --- a/src/intersim2/.svn/pristine/b0/b0621120b70fa66b06fa3e7adc9b386974b8c0c3.svn-base +++ /dev/null @@ -1,66 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _SWITCH_MONITOR_HPP_ -#define _SWITCH_MONITOR_HPP_ - -#include -#include - -using namespace std; - -class Flit; - -class SwitchMonitor { - int _cycles ; - int _inputs ; - int _outputs ; - int _classes ; - vector _event ; - int index( int input, int output, int cl ) const ; -public: - SwitchMonitor( int inputs, int outputs, int classes ) ; - void cycle() ; - vector const & GetActivity() const { - return _event; - } - inline int const & NumInputs() const { - return _inputs; - } - inline int const & NumOutputs() const { - return _outputs; - } - inline int const & NumClasses() const { - return _classes; - } - void traversal( int input, int output, Flit const * f ) ; - void display(ostream & os) const; -} ; - -ostream & operator<<( ostream & os, SwitchMonitor const & obj ) ; - -#endif diff --git a/src/intersim2/.svn/pristine/b4/b4f5b1485bfafbb63c019d5aadd0f1c58250fbe4.svn-base b/src/intersim2/.svn/pristine/b4/b4f5b1485bfafbb63c019d5aadd0f1c58250fbe4.svn-base deleted file mode 100644 index eb45bc2..0000000 --- a/src/intersim2/.svn/pristine/b4/b4f5b1485bfafbb63c019d5aadd0f1c58250fbe4.svn-base +++ /dev/null @@ -1,50 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// ---------------------------------------------------------------------- -// -// SeparableOutputFirstAllocator: Separable Output-First Allocator -// -// ---------------------------------------------------------------------- - -#ifndef _SEPARABLE_OUTPUT_FIRST_HPP_ -#define _SEPARABLE_OUTPUT_FIRST_HPP_ - -#include "separable.hpp" - -class SeparableOutputFirstAllocator : public SeparableAllocator { - -public: - - SeparableOutputFirstAllocator( Module* parent, const string& name, int inputs, - int outputs, const string& arb_type ) ; - - virtual void Allocate() ; - -} ; - -#endif diff --git a/src/intersim2/.svn/pristine/b6/b6c4fdbece4c23327c9e321b130c2ec595705f98.svn-base b/src/intersim2/.svn/pristine/b6/b6c4fdbece4c23327c9e321b130c2ec595705f98.svn-base deleted file mode 100644 index aeb258a..0000000 --- a/src/intersim2/.svn/pristine/b6/b6c4fdbece4c23327c9e321b130c2ec595705f98.svn-base +++ /dev/null @@ -1,183 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _IQ_ROUTER_HPP_ -#define _IQ_ROUTER_HPP_ - -#include -#include -#include -#include -#include - -#include "router.hpp" -#include "routefunc.hpp" - -using namespace std; - -class VC; -class Flit; -class Credit; -class Buffer; -class BufferState; -class Allocator; -class SwitchMonitor; -class BufferMonitor; - -class IQRouter : public Router { - - int _vcs; - - bool _vc_busy_when_full; - bool _vc_prioritize_empty; - bool _vc_shuffle_requests; - - bool _speculative; - bool _spec_check_elig; - bool _spec_check_cred; - bool _spec_mask_by_reqs; - - bool _active; - - int _routing_delay; - int _vc_alloc_delay; - int _sw_alloc_delay; - - map _in_queue_flits; - - deque > > _proc_credits; - - deque > > _route_vcs; - deque, int> > > _vc_alloc_vcs; - deque, int> > > _sw_hold_vcs; - deque, int> > > _sw_alloc_vcs; - - deque > > > _crossbar_flits; - - map _out_queue_credits; - - vector _buf; - vector _next_buf; - - Allocator *_vc_allocator; - Allocator *_sw_allocator; - Allocator *_spec_sw_allocator; - - vector _vc_rr_offset; - vector _sw_rr_offset; - - tRoutingFunction _rf; - - int _output_buffer_size; - vector > _output_buffer; - - vector > _credit_buffer; - - bool _hold_switch_for_packet; - vector _switch_hold_in; - vector _switch_hold_out; - vector _switch_hold_vc; - - bool _noq; - vector > _noq_next_output_port; - vector > _noq_next_vc_start; - vector > _noq_next_vc_end; - -#ifdef TRACK_FLOWS - vector > > _outstanding_classes; -#endif - - bool _ReceiveFlits( ); - bool _ReceiveCredits( ); - - virtual void _InternalStep( ); - - bool _SWAllocAddReq(int input, int vc, int output); - - void _InputQueuing( ); - - void _RouteEvaluate( ); - void _VCAllocEvaluate( ); - void _SWHoldEvaluate( ); - void _SWAllocEvaluate( ); - void _SwitchEvaluate( ); - - void _RouteUpdate( ); - void _VCAllocUpdate( ); - void _SWHoldUpdate( ); - void _SWAllocUpdate( ); - void _SwitchUpdate( ); - - void _OutputQueuing( ); - - void _SendFlits( ); - void _SendCredits( ); - - void _UpdateNOQ(int input, int vc, Flit const * f); - - // ---------------------------------------- - // - // Router Power Modellingyes - // - // ---------------------------------------- - - SwitchMonitor * _switchMonitor ; - BufferMonitor * _bufferMonitor ; - -public: - - IQRouter( Configuration const & config, - Module *parent, string const & name, int id, - int inputs, int outputs ); - - virtual ~IQRouter( ); - - virtual void AddOutputChannel(FlitChannel * channel, CreditChannel * backchannel); - - virtual void ReadInputs( ); - virtual void WriteOutputs( ); - - void Display( ostream & os = cout ) const; - - virtual int GetUsedCredit(int o) const; - virtual int GetBufferOccupancy(int i) const; - -#ifdef TRACK_BUFFERS - virtual int GetUsedCreditForClass(int output, int cl) const; - virtual int GetBufferOccupancyForClass(int input, int cl) const; -#endif - - virtual vector UsedCredits() const; - virtual vector FreeCredits() const; - virtual vector MaxCredits() const; - - SwitchMonitor const * const GetSwitchMonitor() const {return _switchMonitor;} - BufferMonitor const * const GetBufferMonitor() const {return _bufferMonitor;} - -}; - -#endif diff --git a/src/intersim2/.svn/pristine/b7/b755bb8c053f61f95a6ce87cddff8068f0fa19fa.svn-base b/src/intersim2/.svn/pristine/b7/b755bb8c053f61f95a6ce87cddff8068f0fa19fa.svn-base deleted file mode 100644 index df0f9fc..0000000 --- a/src/intersim2/.svn/pristine/b7/b755bb8c053f61f95a6ce87cddff8068f0fa19fa.svn-base +++ /dev/null @@ -1,137 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _VC_HPP_ -#define _VC_HPP_ - -#include - -#include "flit.hpp" -#include "outputset.hpp" -#include "routefunc.hpp" -#include "config_utils.hpp" - -class VC : public Module { -public: - enum eVCState { state_min = 0, idle = state_min, routing, vc_alloc, active, - state_max = active }; - struct state_info_t { - int cycles; - }; - static const char * const VCSTATE[]; - -private: - - deque _buffer; - - eVCState _state; - - OutputSet *_route_set; - int _out_port, _out_vc; - - enum ePrioType { local_age_based, queue_length_based, hop_count_based, none, other }; - - ePrioType _pri_type; - - int _pri; - - int _priority_donation; - - bool _watched; - - int _expected_pid; - - int _last_id; - int _last_pid; - - bool _lookahead_routing; - -public: - - VC( const Configuration& config, int outputs, - Module *parent, const string& name ); - ~VC(); - - void AddFlit( Flit *f ); - inline Flit *FrontFlit( ) const - { - return _buffer.empty() ? NULL : _buffer.front(); - } - - Flit *RemoveFlit( ); - - - inline bool Empty( ) const - { - return _buffer.empty( ); - } - - inline VC::eVCState GetState( ) const - { - return _state; - } - - - void SetState( eVCState s ); - - const OutputSet *GetRouteSet( ) const; - void SetRouteSet( OutputSet * output_set ); - - void SetOutput( int port, int vc ); - - inline int GetOutputPort( ) const - { - return _out_port; - } - - - inline int GetOutputVC( ) const - { - return _out_vc; - } - - void UpdatePriority(); - - inline int GetPriority( ) const - { - return _pri; - } - void Route( tRoutingFunction rf, const Router* router, const Flit* f, int in_channel ); - - inline int GetOccupancy() const - { - return (int)_buffer.size(); - } - - // ==== Debug functions ==== - - void SetWatch( bool watch = true ); - bool IsWatched( ) const; - void Display( ostream & os = cout ) const; -}; - -#endif diff --git a/src/intersim2/.svn/pristine/b8/b8715f9652140e4746a42ce2c1ca742a6dcc8ab1.svn-base b/src/intersim2/.svn/pristine/b8/b8715f9652140e4746a42ce2c1ca742a6dcc8ab1.svn-base deleted file mode 100644 index 3e8f5ae..0000000 --- a/src/intersim2/.svn/pristine/b8/b8715f9652140e4746a42ce2c1ca742a6dcc8ab1.svn-base +++ /dev/null @@ -1,68 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _INJECTION_HPP_ -#define _INJECTION_HPP_ - -#include "config_utils.hpp" - -using namespace std; - -class InjectionProcess { -protected: - int _nodes; - double _rate; - InjectionProcess(int nodes, double rate); -public: - virtual ~InjectionProcess() {} - virtual bool test(int source) = 0; - virtual void reset(); - static InjectionProcess * New(string const & inject, int nodes, double load, - Configuration const * const config = NULL); -}; - -class BernoulliInjectionProcess : public InjectionProcess { -public: - BernoulliInjectionProcess(int nodes, double rate); - virtual bool test(int source); -}; - -class OnOffInjectionProcess : public InjectionProcess { -private: - double _alpha; - double _beta; - double _r1; - vector _initial; - vector _state; -public: - OnOffInjectionProcess(int nodes, double rate, double alpha, double beta, - double r1, vector initial); - virtual void reset(); - virtual bool test(int source); -}; - -#endif diff --git a/src/intersim2/.svn/pristine/b9/b92275ee465ac160db13b1f1e271cf80bc843710.svn-base b/src/intersim2/.svn/pristine/b9/b92275ee465ac160db13b1f1e271cf80bc843710.svn-base deleted file mode 100644 index 1819d18..0000000 --- a/src/intersim2/.svn/pristine/b9/b92275ee465ac160db13b1f1e271cf80bc843710.svn-base +++ /dev/null @@ -1,183 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "booksim.hpp" -#include - -#include "islip.hpp" -#include "random_utils.hpp" - -//#define DEBUG_ISLIP - -iSLIP_Sparse::iSLIP_Sparse( Module *parent, const string& name, - int inputs, int outputs, int iters ) : - SparseAllocator( parent, name, inputs, outputs ), - _iSLIP_iter(iters) -{ - _gptrs.resize(_outputs, 0); - _aptrs.resize(_inputs, 0); -} - -void iSLIP_Sparse::Allocate( ) -{ - int input; - int output; - - int input_offset; - int output_offset; - - map::iterator p; - bool wrapped; - - for ( int iter = 0; iter < _iSLIP_iter; ++iter ) { - // Grant phase - - vector grants(_outputs, -1); - - for ( output = 0; output < _outputs; ++output ) { - - // Skip loop if there are no requests - // or the output is already matched - if ( ( _out_req[output].empty( ) ) || - ( _outmatch[output] != -1 ) ) { - continue; - } - - // A round-robin arbiter between input requests - input_offset = _gptrs[output]; - - p = _out_req[output].begin( ); - while( ( p != _out_req[output].end( ) ) && - ( p->second.port < input_offset ) ) { - p++; - } - - wrapped = false; - while( (!wrapped) || - ( ( p != _out_req[output].end( ) ) && - ( p->second.port < input_offset ) ) ) { - if ( p == _out_req[output].end( ) ) { - if ( wrapped ) { break; } - // p is valid here because empty lists - // are skipped (above) - p = _out_req[output].begin( ); - wrapped = true; - } - - input = p->second.port; - - // we know the output is free (above) and - // if the input is free, grant request - if ( _inmatch[input] == -1 ) { - grants[output] = input; - break; - } - - p++; - } - } - -#ifdef DEBUG_ISLIP - cout << "grants: "; - for ( int i = 0; i < _outputs; ++i ) { - cout << grants[i] << " "; - } - cout << endl; - - cout << "aptrs: "; - for ( int i = 0; i < _inputs; ++i ) { - cout << _aptrs[i] << " "; - } - cout << endl; -#endif - - // Accept phase - - for ( input = 0; input < _inputs; ++input ) { - - if ( _in_req[input].empty( ) ) { - continue; - } - - // A round-robin arbiter between output grants - output_offset = _aptrs[input]; - - p = _in_req[input].begin( ); - while( ( p != _in_req[input].end( ) ) && - ( p->second.port < output_offset ) ) { - p++; - } - - wrapped = false; - while( (!wrapped) || - ( ( p != _in_req[input].end( ) ) && - ( p->second.port < output_offset ) ) ) { - if ( p == _in_req[input].end( ) ) { - if ( wrapped ) { break; } - // p is valid here because empty lists - // are skipped (above) - p = _in_req[input].begin( ); - wrapped = true; - } - - output = p->second.port; - - // we know the output is free (above) and - // if the input is free, grant request - if ( grants[output] == input ) { - // Accept - _inmatch[input] = output; - _outmatch[output] = input; - - // Only update pointers if accepted during the 1st iteration - if ( iter == 0 ) { - _gptrs[output] = ( input + 1 ) % _inputs; - _aptrs[input] = ( output + 1 ) % _outputs; - } - - break; - } - - p++; - } - } - } - -#ifdef DEBUG_ISLIP - cout << "input match: "; - for ( int i = 0; i < _inputs; ++i ) { - cout << _inmatch[i] << " "; - } - cout << endl; - - cout << "output match: "; - for ( int j = 0; j < _outputs; ++j ) { - cout << _outmatch[j] << " "; - } - cout << endl; -#endif -} diff --git a/src/intersim2/.svn/pristine/bf/bf0b085441d2569f393cadb89df82945471cd4d4.svn-base b/src/intersim2/.svn/pristine/bf/bf0b085441d2569f393cadb89df82945471cd4d4.svn-base deleted file mode 100644 index 01a2281..0000000 --- a/src/intersim2/.svn/pristine/bf/bf0b085441d2569f393cadb89df82945471cd4d4.svn-base +++ /dev/null @@ -1,575 +0,0 @@ -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, - are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this list - of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - Neither the name of the Stanford University nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "booksim.hpp" -#include -#include - -#include "dragonfly.hpp" -#include "random_utils.hpp" -#include "misc_utils.hpp" -#include "globals.hpp" - -#define DRAGON_LATENCY - -int gP, gA, gG; - -//calculate the hop count between src and estination -int dragonflynew_hopcnt(int src, int dest) -{ - int hopcnt; - int dest_grp_ID, src_grp_ID; - int src_hopcnt, dest_hopcnt; - int src_intm, dest_intm; - int grp_output, dest_grp_output; - int grp_output_RID; - - int _grp_num_routers= gA; - int _grp_num_nodes =_grp_num_routers*gP; - - dest_grp_ID = int(dest/_grp_num_nodes); - src_grp_ID = int(src / _grp_num_nodes); - - //source and dest are in the same group, either 0-1 hop - if (dest_grp_ID == src_grp_ID) { - if ((int)(dest / gP) == (int)(src /gP)) - hopcnt = 0; - else - hopcnt = 1; - - } else { - //source and dest are in the same group - //find the number of hops in the source group - //find the number of hops in the dest group - if (src_grp_ID > dest_grp_ID) { - grp_output = dest_grp_ID; - dest_grp_output = src_grp_ID - 1; - } - else { - grp_output = dest_grp_ID - 1; - dest_grp_output = src_grp_ID; - } - grp_output_RID = ((int) (grp_output / (gP))) + src_grp_ID * _grp_num_routers; - src_intm = grp_output_RID * gP; - - grp_output_RID = ((int) (dest_grp_output / (gP))) + dest_grp_ID * _grp_num_routers; - dest_intm = grp_output_RID * gP; - - //hop count in source group - if ((int)( src_intm / gP) == (int)( src / gP ) ) - src_hopcnt = 0; - else - src_hopcnt = 1; - - //hop count in destination group - if ((int)( dest_intm / gP) == (int)( dest / gP ) ){ - dest_hopcnt = 0; - }else{ - dest_hopcnt = 1; - } - - //tally - hopcnt = src_hopcnt + 1 + dest_hopcnt; - } - - return hopcnt; -} - - -//packet output port based on the source, destination and current location -int dragonfly_port(int rID, int source, int dest){ - int _grp_num_routers= gA; - int _grp_num_nodes =_grp_num_routers*gP; - - int out_port = -1; - int grp_ID = int(rID / _grp_num_routers); - int dest_grp_ID = int(dest/_grp_num_nodes); - int grp_output=-1; - int grp_RID=-1; - int group_dest=-1; - - //which router within this group the packet needs to go to - if (dest_grp_ID == grp_ID) { - grp_RID = int(dest / gP); - } else { - if (grp_ID > dest_grp_ID) { - grp_output = dest_grp_ID; - } else { - grp_output = dest_grp_ID - 1; - } - grp_RID = int(grp_output /gP) + grp_ID * _grp_num_routers; - group_dest = grp_RID * gP; - } - - //At the last hop - if (dest >= rID*gP && dest < (rID+1)*gP) { - out_port = dest%gP; - } else if (grp_RID == rID) { - //At the optical link - out_port = gP + (gA-1) + grp_output %(gP); - } else { - //need to route within a group - assert(grp_RID!=-1); - - if (rID < grp_RID){ - out_port = (grp_RID % _grp_num_routers) - 1 + gP; - }else{ - out_port = (grp_RID % _grp_num_routers) + gP; - } - } - - assert(out_port!=-1); - return out_port; -} - - -DragonFlyNew::DragonFlyNew( const Configuration &config, const string & name ) : - Network( config, name ) -{ - - _ComputeSize( config ); - _Alloc( ); - _BuildNet( config ); -} - -void DragonFlyNew::_ComputeSize( const Configuration &config ) -{ - - // LIMITATION - // -- only one dimension between the group - // _n == # of dimensions within a group - // _p == # of processors within a router - // inter-group ports : _p - // terminal ports : _p - // intra-group ports : 2*_p - 1 - _p = config.GetInt( "k" ); // # of ports in each switch - _n = config.GetInt( "n" ); - - - assert(_n==1); - // dimension - - if (_n == 1) - _k = _p + _p + 2*_p - 1; - else - _k = _p + _p + 2*_p; - - - // FIX... - gK = _p; gN = _n; - - // with 1 dimension, total of 2p routers per group - // N = 2p * p * (2p^2 + 1) - // a = # of routers per group - // = 2p (if n = 1) - // = p^(n) (if n > 2) - // g = # of groups - // = a * p + 1 - // N = a * p * g; - - if (_n == 1) - _a = 2 * _p; - else - _a = powi(_p, _n); - - _g = _a * _p + 1; - _nodes = _a * _p * _g; - - _num_of_switch = _nodes / _p; - _channels = _num_of_switch * (_k - _p); - _size = _num_of_switch; - - - - gG = _g; - gP = _p; - gA = _a; - _grp_num_routers = gA; - _grp_num_nodes =_grp_num_routers*gP; - -} - -void DragonFlyNew::_BuildNet( const Configuration &config ) -{ - - int _output=-1; - int _input=-1; - int _dim_ID=-1; - int _num_ports_per_switch=-1; - int _dim_size=-1; - int c; - - ostringstream router_name; - - - - cout << " Dragonfly " << endl; - cout << " p = " << _p << " n = " << _n << endl; - cout << " each switch - total radix = "<< _k << endl; - cout << " # of switches = "<< _num_of_switch << endl; - cout << " # of channels = "<< _channels << endl; - cout << " # of nodes ( size of network ) = " << _nodes << endl; - cout << " # of groups (_g) = " << _g << endl; - cout << " # of routers per group (_a) = " << _a << endl; - - for ( int node = 0; node < _num_of_switch; ++node ) { - // ID of the group - int grp_ID; - grp_ID = (int) (node/_a); - router_name << "router"; - - router_name << "_" << node ; - - _routers[node] = Router::NewRouter( config, this, router_name.str( ), - node, _k, _k ); - _timed_modules.push_back(_routers[node]); - - router_name.str(""); - - for ( int cnt = 0; cnt < _p; ++cnt ) { - c = _p * node + cnt; - _routers[node]->AddInputChannel( _inject[c], _inject_cred[c] ); - - } - - for ( int cnt = 0; cnt < _p; ++cnt ) { - c = _p * node + cnt; - _routers[node]->AddOutputChannel( _eject[c], _eject_cred[c] ); - - } - - // add OUPUT channels - // _k == # of processor per router - // need 2*_k routers --thus, - // 2_k-1 outputs channels within group - // _k-1 outputs for intra-group - - // - - if (_n > 1 ) { cout << " ERROR: n>1 dimension NOT supported yet... " << endl; exit(-1); } - - //******************************************** - // connect OUTPUT channels - //******************************************** - // add intra-group output channel - for ( int dim = 0; dim < _n; ++dim ) { - for ( int cnt = 0; cnt < (2*_p -1); ++cnt ) { - _output = (2*_p-1 + _p) * _n * node + (2*_p-1) * dim + cnt; - - _routers[node]->AddOutputChannel( _chan[_output], _chan_cred[_output] ); - -#ifdef DRAGON_LATENCY - _chan[_output]->SetLatency(10); - _chan_cred[_output]->SetLatency(10); -#endif - } - } - - // add inter-group output channel - - for ( int cnt = 0; cnt < _p; ++cnt ) { - _output = (2*_p-1 + _p) * node + (2*_p - 1) + cnt; - - // _chan[_output].global = true; - _routers[node]->AddOutputChannel( _chan[_output], _chan_cred[_output] ); -#ifdef DRAGON_LATENCY - _chan[_output]->SetLatency(100); - _chan_cred[_output]->SetLatency(100); -#endif - } - - - //******************************************** - // connect INPUT channels - //******************************************** - // # of non-local nodes - _num_ports_per_switch = (_k - _p); - - - // intra-group GROUP channels - for ( int dim = 0; dim < _n; ++dim ) { - - _dim_size = powi(_k,dim); - - _dim_ID = ((int) (node / ( powi(_p, dim)))); - - - - // NODE ID withing group - _dim_ID = node % _a; - - - - - for ( int cnt = 0; cnt < (2*_p-1); ++cnt ) { - - if ( cnt < _dim_ID) { - - _input = grp_ID * _num_ports_per_switch * _a - - (_dim_ID - cnt) * _num_ports_per_switch + - _dim_ID * _num_ports_per_switch + - (_dim_ID - 1); - } - else { - - _input = grp_ID * _num_ports_per_switch * _a + - _dim_ID * _num_ports_per_switch + - (cnt - _dim_ID + 1) * _num_ports_per_switch + - _dim_ID; - - } - - if (_input < 0) { - cout << " ERROR: _input less than zero " << endl; - exit(-1); - } - - - _routers[node]->AddInputChannel( _chan[_input], _chan_cred[_input] ); - } - } - - - // add INPUT channels -- "optical" channels connecting the groups - int _grp_num_routers; - int grp_output; - int grp_ID2; - - for ( int cnt = 0; cnt < _p; ++cnt ) { - // _dim_ID - grp_output = _dim_ID* _p + cnt; - - _grp_num_routers = powi(_k, _n-1); - grp_ID2 = (int) ((grp_ID - 1) / (_k - 1)); - - if ( grp_ID > grp_output) { - - _input = (grp_output) * _num_ports_per_switch * _a + // starting point of group - (_num_ports_per_switch - _p) * (int) ((grp_ID - 1) / _p) + // find the correct router within grp - (_num_ports_per_switch - _p) + // add offset within router - grp_ID - 1; - } else { - - _input = (grp_output + 1) * _num_ports_per_switch * _a + - (_num_ports_per_switch - _p) * (int) ((grp_ID) / _p) + // find the correct router within grp - (_num_ports_per_switch - _p) + - grp_ID; - } - - _routers[node]->AddInputChannel( _chan[_input], _chan_cred[_input] ); - } - - } - - cout<<"Done links"<Clear( ); - - if(inject) { - int inject_vc= RandomInt(gNumVCs-1); - outputs->AddRange(-1, inject_vc, inject_vc); - return; - } - - int _grp_num_routers= gA; - - int dest = f->dest; - int rID = r->GetID(); - - int grp_ID = int(rID / _grp_num_routers); - int debug = f->watch; - int out_port = -1; - int out_vc = 0; - int dest_grp_ID=-1; - - if ( in_channel < gP ) { - out_vc = 0; - f->ph = 0; - if (dest_grp_ID == grp_ID) { - f->ph = 1; - } - } - - - out_port = dragonfly_port(rID, f->src, dest); - - //optical dateline - if (out_port >=gP + (gA-1)) { - f->ph = 1; - } - - out_vc = f->ph; - if (debug) - *gWatchOut << GetSimTime() << " | " << r->FullName() << " | " - << " through output port : " << out_port - << " out vc: " << out_vc << endl; - outputs->AddRange( out_port, out_vc, out_vc ); -} - - -//Basic adaptive routign algorithm for the dragonfly -void ugal_dragonflynew( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - //need 3 VCs for deadlock freedom - - assert(gNumVCs==3); - outputs->Clear( ); - if(inject) { - int inject_vc= RandomInt(gNumVCs-1); - outputs->AddRange(-1, inject_vc, inject_vc); - return; - } - - //this constant biases the adaptive decision toward minimum routing - //negative value woudl biases it towards nonminimum routing - int adaptive_threshold = 30; - - int _grp_num_routers= gA; - int _grp_num_nodes =_grp_num_routers*gP; - int _network_size = gA * gP * gG; - - - int dest = f->dest; - int rID = r->GetID(); - int grp_ID = (int) (rID / _grp_num_routers); - int dest_grp_ID = int(dest/_grp_num_nodes); - - int debug = f->watch; - int out_port = -1; - int out_vc = 0; - int min_queue_size, min_hopcnt; - int nonmin_queue_size, nonmin_hopcnt; - int intm_grp_ID; - int intm_rID; - - if(debug){ - cout<<"At router "<ph = 2; - } else { - //select a random node - f->intm =RandomInt(_network_size - 1); - intm_grp_ID = (int)(f->intm/_grp_num_nodes); - if (debug){ - cout<<"Intermediate node "<intm<<" grp id "<ph = 1; - } else { - //congestion metrics using queue length, obtained by GetUsedCredit() - min_hopcnt = dragonflynew_hopcnt(f->src, f->dest); - min_router_output = dragonfly_port(rID, f->src, f->dest); - min_queue_size = max(r->GetUsedCredit(min_router_output), 0) ; - - - nonmin_hopcnt = dragonflynew_hopcnt(f->src, f->intm) + - dragonflynew_hopcnt(f->intm,f->dest); - nonmin_router_output = dragonfly_port(rID, f->src, f->intm); - nonmin_queue_size = max(r->GetUsedCredit(nonmin_router_output), 0); - - //congestion comparison, could use hopcnt instead of 1 and 2 - if ((1 * min_queue_size ) <= (2 * nonmin_queue_size)+adaptive_threshold ) { - if (debug) cout << " MINIMAL routing " << endl; - f->ph = 1; - } else { - f->ph = 0; - } - } - } - } - - //transition from nonminimal phase to minimal - if(f->ph==0){ - intm_rID= (int)(f->intm/gP); - if( rID == intm_rID){ - f->ph = 1; - } - } - - //port assignement based on the phase - if(f->ph == 0){ - out_port = dragonfly_port(rID, f->src, f->intm); - } else if(f->ph == 1){ - out_port = dragonfly_port(rID, f->src, f->dest); - } else if(f->ph == 2){ - out_port = dragonfly_port(rID, f->src, f->dest); - } else { - assert(false); - } - - //optical dateline - if (f->ph == 1 && out_port >=gP + (gA-1)) { - f->ph = 2; - } - - //vc assignemnt based on phase - out_vc = f->ph; - - outputs->AddRange( out_port, out_vc, out_vc ); -} diff --git a/src/intersim2/.svn/pristine/c3/c3580bf85e8bc6015a74e1f37916987e00accdaa.svn-base b/src/intersim2/.svn/pristine/c3/c3580bf85e8bc6015a74e1f37916987e00accdaa.svn-base deleted file mode 100644 index 076ca87..0000000 --- a/src/intersim2/.svn/pristine/c3/c3580bf85e8bc6015a74e1f37916987e00accdaa.svn-base +++ /dev/null @@ -1,146 +0,0 @@ -# $Id $ - -# Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. - -# -# Makefile -# -LEX = flex -YACC = bison -y -DEFINE = -INCPATH = -I. -Iarbiters -Iallocators -Irouters -Inetworks -Ipower -CPPFLAGS += -Wall $(INCPATH) $(DEFINE) -CPPFLAGS += -O3 -CPPFLAGS += -g -LFLAGS += - - -OBJDIR := obj -PROG := booksim - -# simulator source files -CPP_SRCS = main.cpp \ - config_utils.cpp \ - booksim_config.cpp \ - module.cpp \ - buffer.cpp \ - vc.cpp \ - routefunc.cpp \ - traffic.cpp \ - flitchannel.cpp \ - trafficmanager.cpp \ - batchtrafficmanager.cpp \ - packet_reply_info.cpp \ - buffer_state.cpp \ - stats.cpp \ - credit.cpp \ - outputset.cpp \ - flit.cpp \ - injection.cpp\ - misc_utils.cpp\ - rng_wrapper.cpp\ - rng_double_wrapper.cpp\ - power_module.cpp \ - switch_monitor.cpp \ - buffer_monitor.cpp - - - -LEX_OBJS = ${OBJDIR}/lex.yy.o -YACC_OBJS = ${OBJDIR}/y.tab.o - -# networks -NETWORKS:= $(wildcard networks/*.cpp) -ALLOCATORS:= $(wildcard allocators/*.cpp) -ARBITERS:= $(wildcard arbiters/*.cpp) -ROUTERS:= $(wildcard routers/*.cpp) -POWER:= $(wildcard power/*.cpp) - -#--- Make rules --- -OBJS := $(LEX_OBJS) $(YACC_OBJS)\ - $(CPP_SRCS:%.cpp=${OBJDIR}/%.o)\ - $(NETWORKS:networks/%.cpp=${OBJDIR}/%.o)\ - $(ALLOCATORS:allocators/%.cpp=${OBJDIR}/%.o)\ - $(ARBITERS:arbiters/%.cpp=${OBJDIR}/%.o)\ - $(ROUTERS:routers/%.cpp=${OBJDIR}/%.o)\ - $(POWER:power/%.cpp=${OBJDIR}/%.o) - -.PHONY: clean - -all:$(PROG) - -$(PROG): $(OBJS) - $(CXX) $(LFLAGS) $^ -o $@ - -# rules to compile simulator - - -${LEX_OBJS}: lex.yy.c y.tab.h - $(CC) $(CPPFLAGS) -c $< -o $@ - -${YACC_OBJS}: y.tab.c y.tab.h - $(CC) $(CPPFLAGS) -c $< -o $@ - -${OBJDIR}/%.o: %.cpp - $(CXX) $(CPPFLAGS) -c $< -o $@ - -# rules to compile networks -${OBJDIR}/%.o: networks/%.cpp - $(CXX) $(CPPFLAGS) -c $< -o $@ - -# rules to compile arbiters -${OBJDIR}/%.o: arbiters/%.cpp - $(CXX) $(CPPFLAGS) -c $< -o $@ - -# rules to compile allocators -${OBJDIR}/%.o: allocators/%.cpp - $(CXX) $(CPPFLAGS) -c $< -o $@ - -# rules to compile routers -${OBJDIR}/%.o: routers/%.cpp - $(CXX) $(CPPFLAGS) -c $< -o $@ - -# rules to compile power classes -${OBJDIR}/%.o: power/%.cpp - $(CXX) $(CPPFLAGS) -c $< -o $@ - -clean: - rm -f $(OBJS) - rm -f $(PROG) - rm -f *~ - rm -f allocators/*~ - rm -f arbiters/*~ - rm -f networks/*~ - rm -f runfiles/*~ - rm -f routers/*~ - rm -f examples/*~ - rm -f y.tab.c y.tab.h lex.yy.c - rm -f moc_bgui.cpp - -y.tab.c y.tab.h: config.y - $(YACC) -d $< - -lex.yy.c: config.l - $(LEX) $< diff --git a/src/intersim2/.svn/pristine/c3/c3dce16b735e5ff4045d124ee30299d4ff39f5b1.svn-base b/src/intersim2/.svn/pristine/c3/c3dce16b735e5ff4045d124ee30299d4ff39f5b1.svn-base deleted file mode 100644 index 7d12faf..0000000 --- a/src/intersim2/.svn/pristine/c3/c3dce16b735e5ff4045d124ee30299d4ff39f5b1.svn-base +++ /dev/null @@ -1,95 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _CONFIG_UTILS_HPP_ -#define _CONFIG_UTILS_HPP_ - -#include "booksim.hpp" - -#include -#include -#include -#include - -extern "C" int yyparse(); - -class Configuration { - static Configuration * theConfig; - FILE * _config_file; - string _config_string; - -protected: - map _str_map; - map _int_map; - map _float_map; - -public: - Configuration(); - - void AddStrField(string const & field, string const & value); - - void Assign(string const & field, string const & value); - void Assign(string const & field, int value); - void Assign(string const & field, double value); - - string GetStr(string const & field) const; - int GetInt(string const & field) const; - double GetFloat(string const & field) const; - - vector GetStrArray(const string & field) const; - vector GetIntArray(const string & field) const; - vector GetFloatArray(const string & field) const; - - void ParseFile(string const & filename); - void ParseString(string const & str); - int Input(char * line, int max_size); - void ParseError(string const & msg, unsigned int lineno = 0) const; - - void WriteFile(string const & filename); - void WriteMatlabFile(ostream * o) const; - - inline const map & GetStrMap() const { - return _str_map; - } - inline const map & GetIntMap() const { - return _int_map; - } - inline const map & GetFloatMap() const { - return _float_map; - } - - static Configuration * GetTheConfig(); - -}; - -bool ParseArgs(Configuration * cf, int argc, char **argv); - -vector tokenize_str(string const & data); -vector tokenize_int(string const & data); -vector tokenize_float(string const & data); - -#endif diff --git a/src/intersim2/.svn/pristine/c5/c5213fecc8710817b2514c72787b0207849f9280.svn-base b/src/intersim2/.svn/pristine/c5/c5213fecc8710817b2514c72787b0207849f9280.svn-base deleted file mode 100644 index 13bd09d..0000000 --- a/src/intersim2/.svn/pristine/c5/c5213fecc8710817b2514c72787b0207849f9280.svn-base +++ /dev/null @@ -1,80 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// ---------------------------------------------------------------------- -// -// RoundRobin: RoundRobin Arbiter -// -// ---------------------------------------------------------------------- - -#include "roundrobin_arb.hpp" -#include -#include - -using namespace std ; - -RoundRobinArbiter::RoundRobinArbiter( Module *parent, const string &name, - int size ) - : Arbiter( parent, name, size ), _pointer( 0 ) { -} - -void RoundRobinArbiter::PrintState() const { - cout << "Round Robin Priority Pointer: " << endl ; - cout << " _pointer = " << _pointer << endl ; -} - -void RoundRobinArbiter::UpdateState() { - // update priority matrix using last grant - if ( _selected > -1 ) - _pointer = ( _selected + 1 ) % _size ; -} - -void RoundRobinArbiter::AddRequest( int input, int id, int pri ) -{ - if(!_request[input].valid || (_request[input].pri < pri)) { - if((_num_reqs == 0) || - Supersedes(input, pri, _best_input, _highest_pri, _pointer,_size )) { - _highest_pri = pri; - _best_input = input; - } - } - Arbiter::AddRequest(input, id, pri); -} - -int RoundRobinArbiter::Arbitrate( int* id, int* pri ) { - - _selected = _best_input; - - return Arbiter::Arbitrate(id, pri); -} - -void RoundRobinArbiter::Clear() -{ - _highest_pri = numeric_limits::min(); - _best_input = -1; - Arbiter::Clear(); -} diff --git a/src/intersim2/.svn/pristine/cb/cb7c673e590ba7e01169bf437b3753f478aa55ac.svn-base b/src/intersim2/.svn/pristine/cb/cb7c673e590ba7e01169bf437b3753f478aa55ac.svn-base deleted file mode 100644 index 7f6b286..0000000 --- a/src/intersim2/.svn/pristine/cb/cb7c673e590ba7e01169bf437b3753f478aa55ac.svn-base +++ /dev/null @@ -1,71 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "buffer_monitor.hpp" - -#include "flit.hpp" - -BufferMonitor::BufferMonitor( int inputs, int classes ) -: _cycles(0), _inputs(inputs), _classes(classes) { - _reads.resize(inputs * classes, 0) ; - _writes.resize(inputs * classes, 0) ; -} - -int BufferMonitor::index( int input, int cl ) const { - assert((input >= 0) && (input < _inputs)); - assert((cl >= 0) && (cl < _classes)); - return cl + _classes * input ; -} - -void BufferMonitor::cycle() { - _cycles++ ; -} - -void BufferMonitor::write( int input, Flit const * f ) { - _writes[ index(input, f->cl) ]++ ; -} - -void BufferMonitor::read( int input, Flit const * f ) { - _reads[ index(input, f->cl) ]++ ; -} - -void BufferMonitor::display(ostream & os) const { - for ( int i = 0 ; i < _inputs ; i++ ) { - os << "[ " << i << " ] " ; - for ( int c = 0 ; c < _classes ; c++ ) { - os << "Type=" << c - << ":(R#" << _reads[ index( i, c) ] << "," - << "W#" << _writes[ index( i, c) ] << ")" << " " ; - } - os << endl ; - } -} - -ostream & operator<<( ostream & os, BufferMonitor const & obj ) { - obj.display(os); - return os ; -} diff --git a/src/intersim2/.svn/pristine/cd/cdcc1ba4154908a4bfefe5993832475af05a62e6.svn-base b/src/intersim2/.svn/pristine/cd/cdcc1ba4154908a4bfefe5993832475af05a62e6.svn-base deleted file mode 100644 index c1983d4..0000000 --- a/src/intersim2/.svn/pristine/cd/cdcc1ba4154908a4bfefe5993832475af05a62e6.svn-base +++ /dev/null @@ -1,53 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _GLOBALS_HPP_ -#define _GLOBALS_HPP_ -#include -#include -#include - -/*all declared in main.cpp*/ - -int GetSimTime(); - -class Stats; -Stats * GetStats(const std::string & name); - -extern bool gPrintActivity; - -extern int gK; -extern int gN; -extern int gC; - -extern int gNodes; - -extern bool gTrace; - -extern std::ostream * gWatchOut; - -#endif diff --git a/src/intersim2/.svn/pristine/ce/ce3f71fc2f0c6cac1246ba0e26b6af41edef501d.svn-base b/src/intersim2/.svn/pristine/ce/ce3f71fc2f0c6cac1246ba0e26b6af41edef501d.svn-base deleted file mode 100644 index 1894af7..0000000 --- a/src/intersim2/.svn/pristine/ce/ce3f71fc2f0c6cac1246ba0e26b6af41edef501d.svn-base +++ /dev/null @@ -1,890 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include -#include -#include -#include -#include - -#include "event_router.hpp" -#include "stats.hpp" -#include "globals.hpp" - -EventRouter::EventRouter( const Configuration& config, - Module *parent, const string & name, int id, - int inputs, int outputs ) - : Router( config, - parent, name, - id, - inputs, outputs ) -{ - ostringstream module_name; - - _vcs = config.GetInt( "num_vcs" ); - - // Cut-through mode --- packets are not broken - // up and input buffers are assumed to be - // expressed in units of maximum size packets. - - _vct = config.GetInt( "vct" ); - - // Routing - - string rf = config.GetStr("routing_function") + "_" + config.GetStr("topology"); - map::iterator rf_iter = gRoutingFunctionMap.find(rf); - if(rf_iter == gRoutingFunctionMap.end()) { - Error("Invalid routing function: " + rf); - } - _rf = rf_iter->second; - - // Alloc VC's - - _buf.resize(_inputs); - _active.resize(_inputs); - - for ( int i = 0; i < _inputs; ++i ) { - module_name << "buf_" << i; - _buf[i] = new Buffer( config, _outputs, this, module_name.str( ) ); - module_name.seekp( 0, ios::beg ); - _active[i].resize(_vcs, false); - } - - // Alloc next VCs' state - - _output_state.resize(_outputs); - - for ( int o = 0; o < _outputs; ++o ) { - module_name << "output" << o << "_vc_state"; - _output_state[o] = new EventNextVCState(config, this, module_name.str()); - module_name.seekp( 0, ios::beg ); - } - - // Alloc arbiters - - _arrival_arbiter.resize(_outputs); - - for ( int o = 0; o < _outputs; ++o ) { - module_name << "arrival_arb_output" << o; - _arrival_arbiter[o] = - new PriorityArbiter( config, this, module_name.str( ), _inputs ); - module_name.seekp( 0, ios::beg ); - } - - _transport_arbiter.resize(_inputs); - - for ( int i = 0; i < _inputs; ++i ) { - module_name << "transport_arb_input" << i; - _transport_arbiter[i] = - new PriorityArbiter( config, this, module_name.str( ), _outputs ); - module_name.seekp( 0, ios::beg ); - } - - // Alloc pipelines (to simulate processing/transmission delays) - - _crossbar_pipe = - new PipelineFIFO( this, "crossbar_pipeline", _outputs, - _crossbar_delay ); - - _credit_pipe = - new PipelineFIFO( this, "credit_pipeline", _inputs, - _credit_delay ); - - _arrival_pipe = - new PipelineFIFO( this, "arrival_pipeline", _inputs, - 0 /* FIX THIS EVENTUALLY */); - - // Queues - - _input_buffer.resize(_inputs); - _output_buffer.resize(_outputs); - - _in_cred_buffer.resize(_inputs); - _out_cred_buffer.resize(_outputs); - - _arrival_queue.resize(_inputs); - _transport_queue.resize(_outputs); - - // Misc. - - _transport_free.resize(_inputs, true); - _transport_match.resize(_inputs, -1); -} - -EventRouter::~EventRouter( ) -{ - for ( int i = 0; i < _inputs; ++i ) { - delete _buf[i]; - } - - for ( int o = 0; o < _outputs; ++o ) { - delete _output_state[o]; - } - - for ( int o = 0; o < _outputs; ++o ) { - delete _arrival_arbiter[o]; - } - - for ( int i = 0; i < _inputs; ++i ) { - delete _transport_arbiter[i]; - } - - delete _crossbar_pipe; - delete _credit_pipe; - delete _arrival_pipe; -} - -void EventRouter::ReadInputs( ) -{ - _ReceiveFlits( ); - _ReceiveCredits( ); -} - -void EventRouter::_InternalStep( ) -{ - // Receive incoming flits - _IncomingFlits( ); - - // The input pipe simulates routing delay - _arrival_pipe->Advance( ); - - // Clear output requests - for ( int output = 0; output < _outputs; ++output ) { - _arrival_arbiter[output]->Clear( ); - } - - // Check input arrival queues and generate - // requests for the outputs - for ( int input = 0; input < _inputs; ++input ) { - _ArrivalRequests( input ); - } - - // Arbitrate between requests at outputs - for ( int output = 0; output < _outputs; ++output ) { - _ArrivalArb( output ); - } - - for ( int input = 0; input < _inputs; ++input ) { - _transport_arbiter[input]->Clear( ); - } - - _crossbar_pipe->WriteAll( 0 ); - _credit_pipe->WriteAll( 0 ); - - // Generate transport events and their - // requests for the inputs - for ( int output = 0; output < _outputs; ++output ) { - _TransportRequests( output ); - } - - // Arbitrate between requests at inputs - for ( int input = 0; input < _inputs; ++input ) { - _TransportArb( input ); - } - - _crossbar_pipe->Advance( ); - _credit_pipe->Advance( ); - - _OutputQueuing( ); -} - -void EventRouter::WriteOutputs( ) -{ - _SendFlits( ); - _SendCredits( ); -} - -void EventRouter::_ReceiveFlits( ) -{ - Flit *f; - - for ( int input = 0; input < _inputs; ++input ) { - f = _input_channels[input]->Receive(); - - if ( f ) { - _input_buffer[input].push( f ); - } - } -} - -void EventRouter::_ReceiveCredits( ) -{ - Credit *c; - - for ( int output = 0; output < _outputs; ++output ) { - c = _output_credits[output]->Receive(); - - if ( c ) { - _out_cred_buffer[output].push( c ); - } - } -} - -void EventRouter::_ProcessWaiting( int output, int out_vc ) -{ - // out_vc just sent the transport event for out_vc, - // check if any events are queued on that vc. if so, - // generate another transport event and set the - // owner of the vc, otherwise set the vc to idle. - - int credits; - - tTransportEvent *tevt; - - EventNextVCState::tWaiting *w; - - if ( _output_state[output]->IsWaiting( out_vc ) ) { - - // State remains as busy, but the waiting VC takes over - w = _output_state[output]->PopWaiting( out_vc ); - - _output_state[output]->SetState( out_vc, EventNextVCState::busy ); - _output_state[output]->SetInput( out_vc, w->input ); - _output_state[output]->SetInputVC( out_vc, w->vc ); - - if ( w->watch ) { - cout << "Dequeuing waiting arrival event at " << FullName() - << " for flit " << w->id << endl; - } - - credits = _output_state[output]->GetCredits( out_vc ); - - // Try to queue a transmit event for a waiting packet - if ( credits > 0 ) { - tevt = new tTransportEvent; - tevt->src_vc = w->vc; - tevt->dst_vc = out_vc; - tevt->input = w->input; - tevt->watch = w->watch; // just to have something here - tevt->id = w->id; - - _transport_queue[output].push( tevt ); - - if ( tevt->watch ) { - cout << "Injecting transport event at " << FullName() - << " for flit " << tevt->id << endl; - } - - credits--; - _output_state[output]->SetCredits( out_vc, credits ); - _output_state[output]->SetPresence( out_vc, w->pres - 1 ); - - } else { - // No credits available, just store presence - _output_state[output]->SetPresence( out_vc, w->pres ); - } - - delete w; - - } else { - // Tail sent, none waiting => VC is idle - _output_state[output]->SetState( out_vc, EventNextVCState::idle ); - } -} - -void EventRouter::_IncomingFlits( ) -{ - Flit *f; - Buffer *cur_buf; - - tArrivalEvent *aevt; - - _arrival_pipe->WriteAll( 0 ); - - for ( int input = 0; input < _inputs; ++input ) { - if ( !_input_buffer[input].empty( ) ) { - f = _input_buffer[input].front( ); - _input_buffer[input].pop( ); - - cur_buf = _buf[input]; - int vc = f->vc; - - cur_buf->AddFlit( vc, f ); - - // Head flit arriving at idle VC - if ( !_active[input][vc] ) { - - if ( !f->head ) { - cout << "Non-head flit:" << endl; - cout << *f; - Error( "Received non-head flit at idle VC" ); - } - - const OutputSet *route_set; - int out_vc, out_port; - - cur_buf->Route( vc, _rf, this, f, input ); - route_set = cur_buf->GetRouteSet( vc ); - - if ( !route_set->GetPortVC( &out_port, &out_vc ) ) { - Error( "The event-driven router requires routing functions with a single (port,vc) output" ); - } - - cur_buf->SetOutput( vc, out_port, out_vc ); - _active[input][vc] = true; - } else { - if ( f->head ) { - cout << *f; - Error( "Received head flit at non-idle VC." ); - } - } - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Received flit at " << FullName() << ". Output port = " - << cur_buf->GetOutputPort( vc ) << ", output VC = " - << cur_buf->GetOutputVC( vc ) << endl - << *f; - } - - // In cut-through mode, only head flits generate arrivals, - // otherwise all flits generate - - if ( ( !_vct ) || ( _vct && f->head ) ) { - // Add the arrival event to a delay pipeline to - // account for routing/decoding time - - aevt = new tArrivalEvent; - - aevt->input = input; - aevt->output = cur_buf->GetOutputPort( vc ); - aevt->src_vc = f->vc; - aevt->dst_vc = cur_buf->GetOutputVC( vc ); - aevt->head = f->head; - aevt->tail = f->tail; - - //if ( f->head && f->tail ) { - // Error( "Head/tail packets not supported." ); - //} - - aevt->watch = f->watch; - aevt->id = f->id; - - _arrival_pipe->Write( aevt, input ); - - if ( aevt->watch ) { - cout << "Injected arrival event at " << FullName() - << " for flit " << aevt->id << endl; - } - } - } - } -} - -void EventRouter::_ArrivalRequests( int input ) -{ - tArrivalEvent *aevt; - - aevt = _arrival_pipe->Read( input ); - if ( aevt ) { - _arrival_queue[input].push( aevt ); - } - - if ( !_arrival_queue[input].empty( ) ) { - aevt = _arrival_queue[input].front( ); - _arrival_arbiter[aevt->output]->AddRequest( input ); - } -} - -void EventRouter::_SendTransport( int input, int output, tArrivalEvent *aevt ) -{ - // Try to send a transport event - - tTransportEvent *tevt; - - int credits; - int pres; - - credits = _output_state[output]->GetCredits( aevt->dst_vc ); - - if ( credits > 0 ) { - // Take a credit and queue a transport event - credits--; - _output_state[output]->SetCredits( aevt->dst_vc, credits ); - - tevt = new tTransportEvent; - tevt->src_vc = aevt->src_vc; - tevt->dst_vc = aevt->dst_vc; - tevt->input = input; - tevt->watch = aevt->watch; - tevt->id = aevt->id; - - _transport_queue[output].push( tevt ); - - if ( tevt->watch ) { - cout << "Injecting transport event at " << FullName() - << " for flit " << tevt->id << endl; - } - } else { - if ( aevt->watch ) { - cout << "No credits available at " << FullName() - << " for flit " << aevt->id << " storing presence." << endl; - } - - // No credits available, just store presence - pres = _output_state[output]->GetPresence( aevt->dst_vc ); - _output_state[output]->SetPresence( aevt->dst_vc, pres + 1 ); - } -} - -void EventRouter::_ArrivalArb( int output ) -{ - tArrivalEvent *aevt; - tTransportEvent *tevt; - Credit *c; - - EventNextVCState::tWaiting *w; - - int input; - int credits; - int pres; - - // Incoming credits can produce or enable - // transport events --- process them first - - if ( !_out_cred_buffer[output].empty( ) ) { - c = _out_cred_buffer[output].front( ); - _out_cred_buffer[output].pop( ); - - assert( c->vc.size() == 1 ); - int vc = *c->vc.begin(); - - EventNextVCState::eNextVCState state = - _output_state[output]->GetState( vc ); - - credits = _output_state[output]->GetCredits( vc ); - pres = _output_state[output]->GetPresence( vc ); - - if ( _vct ) { - // In cut-through mode, only head credits indicate a change in - // channel state. - - if ( c->head ) { - credits++; - _output_state[output]->SetCredits( vc, credits ); - _ProcessWaiting( output, vc ); - } - } else { - credits++; - _output_state[output]->SetCredits( vc, credits ); - - if ( c->tail ) { // tail flit -- recycle VC - if ( state != EventNextVCState::busy ) { - Error( "Received tail credit at non-busy output VC" ); - } - - _ProcessWaiting( output, vc ); - } else if ( ( state == EventNextVCState::busy ) && ( pres > 0 ) ) { - // Flit is present => generate transport event - - tevt = new tTransportEvent; - tevt->input = _output_state[output]->GetInput( vc ); - tevt->src_vc = _output_state[output]->GetInputVC( vc ); - tevt->dst_vc = vc; - tevt->watch = false; - tevt->id = -1; - - _transport_queue[output].push( tevt ); - - pres--; - credits--; - _output_state[output]->SetPresence( vc, pres ); - _output_state[output]->SetCredits( vc, credits ); - } - } - - c->Free(); - } - - // Now process arrival events - - _arrival_arbiter[output]->Arbitrate( ); - input = _arrival_arbiter[output]->Match( ); - - if ( input != -1 ) { - // Winning arrival event gets access to output - - aevt = _arrival_queue[input].front( ); - _arrival_queue[input].pop( ); - - if ( aevt->watch ) { - cout << "Processing arrival event at " << FullName() - << " for flit " << aevt->id << endl; - } - - EventNextVCState::eNextVCState state = - _output_state[output]->GetState( aevt->dst_vc ); - - if ( aevt->head ) { // Head flits - if ( state == EventNextVCState::idle ) { - // Allocate the output VC and queue a transport event - _output_state[output]->SetState( aevt->dst_vc, EventNextVCState::busy ); - _output_state[output]->SetInput( aevt->dst_vc, input ); - _output_state[output]->SetInputVC( aevt->dst_vc, aevt->src_vc ); - - _SendTransport( input, output, aevt ); - } else { - // VC busy => queue a waiting event - - w = new EventNextVCState::tWaiting; - - w->input = input; - w->vc = aevt->src_vc; - w->id = aevt->id; - w->watch = aevt->watch; - w->pres = 1; - - _output_state[output]->PushWaiting( aevt->dst_vc, w ); - } - } else { - if ( _vct ) { - Error( "Received arrival event for non-head flit in cut-through mode" ); - } - - if ( state != EventNextVCState::busy ) { - cout << "flit id = " << aevt->id << endl; - Error( "Received a body flit at a non-busy output VC" ); - } - - if ( ( !_output_state[output]->IsInputWaiting( aevt->dst_vc, input, aevt->src_vc ) ) && - ( input == _output_state[output]->GetInput( aevt->dst_vc ) ) && - ( aevt->src_vc == _output_state[output]->GetInputVC( aevt->dst_vc ) ) ) { - // Body flit part of the current active VC => queue transport event - // (the weird IsInputWaiting call handles a body flit waiting in addition - // to a head flit) - - _SendTransport( input, output, aevt ); - } else { - - // VC busy with a differnet transaction => update waiting event - _output_state[output]->IncrWaiting( aevt->dst_vc, input, aevt->src_vc ); - } - } - - delete aevt; - } -} - -void EventRouter::_TransportRequests( int output ) -{ - tTransportEvent *tevt; - - if ( !_transport_queue[output].empty( ) ) { - tevt = _transport_queue[output].front( ); - _transport_arbiter[tevt->input]->AddRequest( output ); - } -} - -void EventRouter::_TransportArb( int input ) -{ - tTransportEvent *tevt; - - int output; - Buffer *cur_buf; - Flit *f; - Credit *c; - - if ( _transport_free[input] ) { - _transport_arbiter[input]->Arbitrate( ); - output = _transport_arbiter[input]->Match( ); - } else { - output = _transport_match[input]; - } - - if ( output != -1 ) { - // This completes the match from input to output => - // one flit can be transferred - - tevt = _transport_queue[output].front( ); - - if ( tevt->watch ) { - cout << "Processing transport event at " << FullName() - << " for flit " << tevt->id << endl; - } - - cur_buf = _buf[input]; - int vc = tevt->src_vc; - - // Some sanity checking first - - if ( !_active[input][vc] ) { - Error( "Non-active VC received grant." ); - } - - if ( cur_buf->Empty( vc ) ) { - return; //Error( "Empty VC received grant." ); - } - - if ( tevt->dst_vc != cur_buf->GetOutputVC( vc ) ) { - Error( "Transport event's VC does not match input's destination VC." ); - } - - f = cur_buf->RemoveFlit( vc ); - - if ( _vct ) { - if ( f->tail ) { - _transport_free[input] = true; - _transport_match[input] = -1; - - _transport_queue[output].pop( ); - delete tevt; - - _active[input][vc] = false; - } else { - _transport_free[input] = false; - _transport_match[input] = output; - } - } else { - _transport_free[input] = true; - _transport_match[input] = -1; - - _transport_queue[output].pop( ); - delete tevt; - - if ( f->tail ) { - _active[input][vc] = false; - } - } - - c = Credit::New( ); - c->vc.insert(f->vc); - c->head = f->head; - c->tail = f->tail; - c->id = f->id; - _credit_pipe->Write( c, input ); - - if ( f->watch && c->tail ) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << FullName() << " sending tail credit back for flit " << f->id << endl; - } - - // Update and forward the flit to the crossbar - - f->hops++; - f->vc = cur_buf->GetOutputVC( vc ); - _crossbar_pipe->Write( f, output ); - - if ( f->watch ) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Forwarding flit through crossbar at " << FullName() << ":" << endl - << *f; - } - } -} - -void EventRouter::_OutputQueuing( ) -{ - Flit *f; - Credit *c; - - for ( int output = 0; output < _outputs; ++output ) { - f = _crossbar_pipe->Read( output ); - - if ( f ) { - _output_buffer[output].push( f ); - } - } - - for ( int input = 0; input < _inputs; ++input ) { - c = _credit_pipe->Read( input ); - - if ( c ) { - _in_cred_buffer[input].push( c ); - } - } -} - -void EventRouter::_SendFlits( ) -{ - for ( int output = 0; output < _outputs; ++output ) { - if ( !_output_buffer[output].empty( ) ) { - Flit *f = _output_buffer[output].front( ); - _output_buffer[output].pop( ); - _output_channels[output]->Send( f ); - } - } -} - -void EventRouter::_SendCredits( ) -{ - for ( int input = 0; input < _inputs; ++input ) { - if ( !_in_cred_buffer[input].empty( ) ) { - Credit *c = _in_cred_buffer[input].front( ); - _in_cred_buffer[input].pop( ); - _input_credits[input]->Send( c ); - } - } -} - -void EventRouter::Display( ostream & os ) const -{ - for ( int input = 0; input < _inputs; ++input ) { - _buf[input]->Display( os ); - } -} - -EventNextVCState::EventNextVCState( const Configuration& config, - Module *parent, const string& name ) : - Module( parent, name ) -{ - _buf_size = config.GetInt( "vc_buf_size" ); - _vcs = config.GetInt( "num_vcs" ); - - _credits.resize(_vcs, _buf_size); - _presence.resize(_vcs, 0); - _input.resize(_vcs); - _inputVC.resize(_vcs); - _waiting.resize(_vcs); - _state.resize(_vcs, idle); -} - -EventNextVCState::eNextVCState EventNextVCState::GetState( int vc ) const -{ - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - return _state[vc]; -} - -int EventNextVCState::GetPresence( int vc ) const -{ - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - return _presence[vc]; -} - -int EventNextVCState::GetCredits( int vc ) const -{ - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - return _credits[vc]; -} - -int EventNextVCState::GetInput( int vc ) const -{ - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - return _input[vc]; -} - -int EventNextVCState::GetInputVC( int vc ) const -{ - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - return _inputVC[vc]; -} - -bool EventNextVCState::IsWaiting( int vc ) const -{ - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - return !_waiting[vc].empty( ); -} - -void EventNextVCState::PushWaiting( int vc, tWaiting *w ) -{ - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - - if ( w->watch ) { - cout << FullName() << " pushing flit " << w->id - << " onto a waiting queue of length " << _waiting[vc].size( ) << endl; - } - - _waiting[vc].push_back( w ); -} - -void EventNextVCState::IncrWaiting( int vc, int w_input, int w_vc ) -{ - list::iterator match; - - // search for match - for ( match = _waiting[vc].begin( ); match != _waiting[vc].end( ); match++ ) { - if ( ( (*match)->input == w_input ) && - ( (*match)->vc == w_vc ) ) break; - } - - if ( match != _waiting[vc].end( ) ) { - (*match)->pres++; - } else { - Error( "Did not find match in IncrWaiting" ); - } -} - -bool EventNextVCState::IsInputWaiting( int vc, int w_input, int w_vc ) const -{ - list::const_iterator match; - bool r; - - // search for match - for ( match = _waiting[vc].begin( ); match != _waiting[vc].end( ); match++ ) { - if ( ( (*match)->input == w_input ) && - ( (*match)->vc == w_vc ) ) break; - } - - if ( match != _waiting[vc].end( ) ) { - r = true; - } else { - r = false; - } - - return r; -} - -EventNextVCState::tWaiting *EventNextVCState::PopWaiting( int vc ) -{ - tWaiting *w; - - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - - w = _waiting[vc].front( ); - _waiting[vc].pop_front( ); - - return w; -} - -void EventNextVCState::SetState( int vc, eNextVCState state ) -{ - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - _state[vc] = state; -} - -void EventNextVCState::SetCredits( int vc, int value ) -{ - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - _credits[vc] = value; -} - -void EventNextVCState::SetPresence( int vc, int value ) -{ - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - _presence[vc] = value; -} - -void EventNextVCState::SetInput( int vc, int input ) -{ - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - _input[vc] = input; -} - -void EventNextVCState::SetInputVC( int vc, int in_vc ) -{ - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - _inputVC[vc] = in_vc; -} diff --git a/src/intersim2/.svn/pristine/d0/d0f90a9d59a9b0c3aa0cf7a6059e041d762561d1.svn-base b/src/intersim2/.svn/pristine/d0/d0f90a9d59a9b0c3aa0cf7a6059e041d762561d1.svn-base deleted file mode 100644 index 3e4549a..0000000 --- a/src/intersim2/.svn/pristine/d0/d0f90a9d59a9b0c3aa0cf7a6059e041d762561d1.svn-base +++ /dev/null @@ -1,47 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _PIM_HPP_ -#define _PIM_HPP_ - -#include - -#include "allocator.hpp" - -class PIM : public DenseAllocator { - int _PIM_iter; - -public: - PIM( Module *parent, const string& name, - int inputs, int outputs, int iters ); - - ~PIM( ); - - void Allocate( ); -}; - -#endif diff --git a/src/intersim2/.svn/pristine/d3/d37925d1e5c51c8adc54f266e526d96fd3468e65.svn-base b/src/intersim2/.svn/pristine/d3/d37925d1e5c51c8adc54f266e526d96fd3468e65.svn-base deleted file mode 100644 index 6fc6ffc..0000000 --- a/src/intersim2/.svn/pristine/d3/d37925d1e5c51c8adc54f266e526d96fd3468e65.svn-base +++ /dev/null @@ -1,86 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// ---------------------------------------------------------------------- -// -// Arbiter: Base class for Matrix and Round Robin Arbiter -// -// ---------------------------------------------------------------------- - -#ifndef _ARBITER_HPP_ -#define _ARBITER_HPP_ - -#include - -#include "module.hpp" - -class Arbiter : public Module { - -protected: - - typedef struct { - bool valid ; - int id ; - int pri ; - } entry_t ; - - vector _request ; - int _size ; - - int _selected ; - int _highest_pri; - int _best_input; - -public: - int _num_reqs ; - // Constructors - Arbiter( Module *parent, const string &name, int size ) ; - - // Print priority matrix to standard output - virtual void PrintState() const = 0 ; - - // Register request with arbiter - virtual void AddRequest( int input, int id, int pri ) ; - - // Update priority matrix based on last aribtration result - virtual void UpdateState() = 0 ; - - // Arbitrate amongst requests. Returns winning input and - // updates pointers to metadata when valid pointers are passed - virtual int Arbitrate( int* id = 0, int* pri = 0 ) ; - - virtual void Clear(); - - inline int LastWinner() const { - return _selected; - } - - static Arbiter *NewArbiter( Module *parent, const string &name, - const string &arb_type, int size ); -} ; - -#endif diff --git a/src/intersim2/.svn/pristine/d6/d61d8cfbf8e0ae5784d8d94c0bb085d6d1e7b214.svn-base b/src/intersim2/.svn/pristine/d6/d61d8cfbf8e0ae5784d8d94c0bb085d6d1e7b214.svn-base deleted file mode 100644 index 6d9a906..0000000 --- a/src/intersim2/.svn/pristine/d6/d61d8cfbf8e0ae5784d8d94c0bb085d6d1e7b214.svn-base +++ /dev/null @@ -1,60 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _CREDIT_HPP_ -#define _CREDIT_HPP_ - -#include -#include - -class Credit { - -public: - - set vc; - - // these are only used by the event router - bool head, tail; - int id; - - void Reset(); - - static Credit * New(); - void Free(); - static void FreeAll(); - static int OutStanding(); -private: - - static stack _all; - static stack _free; - - Credit(); - ~Credit() {} - -}; - -#endif diff --git a/src/intersim2/.svn/pristine/d8/d829c556dee3dc27d19528e00200847c1b338e0e.svn-base b/src/intersim2/.svn/pristine/d8/d829c556dee3dc27d19528e00200847c1b338e0e.svn-base deleted file mode 100644 index 377d467..0000000 --- a/src/intersim2/.svn/pristine/d8/d829c556dee3dc27d19528e00200847c1b338e0e.svn-base +++ /dev/null @@ -1,37 +0,0 @@ -%{ - -int yylex(void); -void yyerror(char * msg); -void config_assign_string( char const * field, char const * value ); -void config_assign_int( char const * field, int value ); -void config_assign_float( char const * field, double value ); - -#ifdef _WIN32 -#pragma warning ( disable : 4102 ) -#pragma warning ( disable : 4244 ) -#endif - -%} - -%union { - char *name; - int num; - double fnum; -} - -%token STR -%token NUM -%token FNUM - -%% - -commands : commands command - | command -; - -command : STR '=' STR ';' { config_assign_string( $1, $3 ); free( $1 ); free( $3 ); } - | STR '=' NUM ';' { config_assign_int( $1, $3 ); free( $1 ); } - | STR '=' FNUM ';' { config_assign_float( $1, $3 ); free( $1 ); } -; - -%% diff --git a/src/intersim2/.svn/pristine/da/dace18d8332403831e17e47c9f2dac7ee20fe786.svn-base b/src/intersim2/.svn/pristine/da/dace18d8332403831e17e47c9f2dac7ee20fe786.svn-base deleted file mode 100644 index eba0184..0000000 --- a/src/intersim2/.svn/pristine/da/dace18d8332403831e17e47c9f2dac7ee20fe786.svn-base +++ /dev/null @@ -1,125 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -////////////////////////////////////////////////////////////////////// -// -// File Name: channel.hpp -// -// The Channel models a generic channel with a multi-cycle -// transmission delay. The channel latency can be specified as -// an integer number of simulator cycles. -// -///// -#ifndef _CHANNEL_HPP -#define _CHANNEL_HPP - -#include -#include - -#include "globals.hpp" -#include "module.hpp" -#include "timed_module.hpp" - -using namespace std; - -template -class Channel : public TimedModule { -public: - Channel(Module * parent, string const & name); - virtual ~Channel() {} - - // Physical Parameters - void SetLatency(int cycles); - int GetLatency() const { return _delay ; } - - // Send data - virtual void Send(T * data); - - // Receive data - virtual T * Receive(); - - virtual void ReadInputs(); - virtual void Evaluate() {} - virtual void WriteOutputs(); - -protected: - int _delay; - T * _input; - T * _output; - queue > _wait_queue; - -}; - -template -Channel::Channel(Module * parent, string const & name) - : TimedModule(parent, name), _delay(1), _input(0), _output(0) { -} - -template -void Channel::SetLatency(int cycles) { - if(cycles <= 0) { - Error("Channel must have positive delay."); - } - _delay = cycles ; -} - -template -void Channel::Send(T * data) { - _input = data; -} - -template -T * Channel::Receive() { - return _output; -} - -template -void Channel::ReadInputs() { - if(_input) { - _wait_queue.push(make_pair(GetSimTime() + _delay - 1, _input)); - _input = 0; - } -} - -template -void Channel::WriteOutputs() { - _output = 0; - if(_wait_queue.empty()) { - return; - } - pair const & item = _wait_queue.front(); - int const & time = item.first; - if(GetSimTime() < time) { - return; - } - assert(GetSimTime() == time); - _output = item.second; - assert(_output); - _wait_queue.pop(); -} - -#endif diff --git a/src/intersim2/.svn/pristine/de/de391802bf06c5a01ef346b8b98d27244c296855.svn-base b/src/intersim2/.svn/pristine/de/de391802bf06c5a01ef346b8b98d27244c296855.svn-base deleted file mode 100644 index 08bb021..0000000 --- a/src/intersim2/.svn/pristine/de/de391802bf06c5a01ef346b8b98d27244c296855.svn-base +++ /dev/null @@ -1,856 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// ---------------------------------------------------------------------- -// -// CMesh: Network with Terminal Nodes arranged in a concentrated -// mesh topology -// -// ---------------------------------------------------------------------- - -// ---------------------------------------------------------------------- -// $Author: jbalfour $ -// $Date: 2007/06/28 17:24:35 $ -// $Id$ -// Modified 11/6/2007 by Ted Jiang -// Now handeling n = most power of 2: 16, 64, 256, 1024 -// ---------------------------------------------------------------------- -#include "booksim.hpp" -#include -#include -#include -#include "random_utils.hpp" -#include "misc_utils.hpp" -#include "cmesh.hpp" - -int CMesh::_cX = 0 ; -int CMesh::_cY = 0 ; -int CMesh::_memo_NodeShiftX = 0 ; -int CMesh::_memo_NodeShiftY = 0 ; -int CMesh::_memo_PortShiftY = 0 ; - -CMesh::CMesh( const Configuration& config, const string & name ) - : Network(config, name) -{ - _ComputeSize( config ); - _Alloc(); - _BuildNet(config); -} - -void CMesh::RegisterRoutingFunctions() { - gRoutingFunctionMap["dor_cmesh"] = &dor_cmesh; - gRoutingFunctionMap["dor_no_express_cmesh"] = &dor_no_express_cmesh; - gRoutingFunctionMap["xy_yx_cmesh"] = &xy_yx_cmesh; - gRoutingFunctionMap["xy_yx_no_express_cmesh"] = &xy_yx_no_express_cmesh; -} - -void CMesh::_ComputeSize( const Configuration &config ) { - - int k = config.GetInt( "k" ); - int n = config.GetInt( "n" ); - assert(n <= 2); // broken for n > 2 - int c = config.GetInt( "c" ); - assert(c == 4); // broken for c != 4 - - ostringstream router_name; - //how many routers in the x or y direction - _xcount = config.GetInt("x"); - _ycount = config.GetInt("y"); - assert(_xcount == _ycount); // broken for asymmetric topologies - //configuration of hohw many clients in X and Y per router - _xrouter = config.GetInt("xr"); - _yrouter = config.GetInt("yr"); - assert(_xrouter == _yrouter); // broken for asymmetric concentration - - gK = _k = k ; - gN = _n = n ; - gC = _c = c ; - - assert(c == _xrouter*_yrouter); - - _nodes = _c * powi( _k, _n); // Number of nodes in network - _size = powi( _k, _n); // Number of routers in network - _channels = 2 * _n * _size; // Number of channels in network - - _cX = _c / _n ; // Concentration in X Dimension - _cY = _c / _cX ; // Concentration in Y Dimension - - // - _memo_NodeShiftX = _cX >> 1 ; - _memo_NodeShiftY = log_two(gK * _cX) + ( _cY >> 1 ) ; - _memo_PortShiftY = log_two(gK * _cX) ; - -} - -void CMesh::_BuildNet( const Configuration& config ) { - - int x_index ; - int y_index ; - - //standard trace configuration - if(gTrace){ - cout<<"Setup Finished Router"< channel_vector(_nodes, false) ; - - // - // Routers and Channel - // - for (int node = 0; node < _size; ++node) { - - // Router index derived from mesh index - y_index = node / _k ; - x_index = node % _k ; - - const int degree_in = 2 *_n + _c ; - const int degree_out = 2 *_n + _c ; - - name << "router_" << y_index << '_' << x_index; - _routers[node] = Router::NewRouter( config, - this, - name.str(), - node, - degree_in, - degree_out); - _timed_modules.push_back(_routers[node]); - name.str(""); - - // - // Port Numbering: as best as I can determine, the order in - // which the input and output channels are added to the - // router determines the associated port number that must be - // used by the router. Output port number increases with - // each new channel - // - - // - // Processing node channels - // - for (int y = 0; y < _cY ; y++) { - for (int x = 0; x < _cX ; x++) { - int link = (_k * _cX) * (_cY * y_index + y) + (_cX * x_index + x) ; - assert( link >= 0 ) ; - assert( link < _nodes ) ; - assert( channel_vector[ link ] == false ) ; - channel_vector[link] = true ; - // Ingress Ports - _routers[node]->AddInputChannel(_inject[link], _inject_cred[link]); - // Egress Ports - _routers[node]->AddOutputChannel(_eject[link], _eject_cred[link]); - //injeciton ejection latency is 1 - _inject[link]->SetLatency( 1 ); - _eject[link]->SetLatency( 1 ); - } - } - - // - // router to router channels - // - const int x = node % _k ; - const int y = node / _k ; - const int offset = powi( _k, _n ) ; - - //the channel number of the input output channels. - int px_out = _k * y + x + 0 * offset ; - int nx_out = _k * y + x + 1 * offset ; - int py_out = _k * y + x + 2 * offset ; - int ny_out = _k * y + x + 3 * offset ; - int px_in = _k * y + ((x+1)) + 1 * offset ; - int nx_in = _k * y + ((x-1)) + 0 * offset ; - int py_in = _k * ((y+1)) + x + 3 * offset ; - int ny_in = _k * ((y-1)) + x + 2 * offset ; - - // Express Channels - if (x == 0){ - // Router on left edge of mesh. Connect to -x output of - // another router on the left edge of the mesh. - if (y < _k / 2 ) - nx_in = _k * (y + _k/2) + x + offset ; - else - nx_in = _k * (y - _k/2) + x + offset ; - } - - if (x == (_k-1)){ - // Router on right edge of mesh. Connect to +x output of - // another router on the right edge of the mesh. - if (y < _k / 2) - px_in = _k * (y + _k/2) + x ; - else - px_in = _k * (y - _k/2) + x ; - } - - if (y == 0) { - // Router on bottom edge of mesh. Connect to -y output of - // another router on the bottom edge of the mesh. - if (x < _k / 2) - ny_in = _k * y + (x + _k/2) + 3 * offset ; - else - ny_in = _k * y + (x - _k/2) + 3 * offset ; - } - - if (y == (_k-1)) { - // Router on top edge of mesh. Connect to +y output of - // another router on the top edge of the mesh - if (x < _k / 2) - py_in = _k * y + (x + _k/2) + 2 * offset ; - else - py_in = _k * y + (x - _k/2) + 2 * offset ; - } - - /*set latency and add the channels*/ - - // Port 0: +x channel - if(use_noc_latency) { - int const px_latency = (x == _k-1) ? (_cY*_k/2) : _cX; - _chan[px_out]->SetLatency( px_latency ); - _chan_cred[px_out]->SetLatency( px_latency ); - } else { - _chan[px_out]->SetLatency( 1 ); - _chan_cred[px_out]->SetLatency( 1 ); - } - _routers[node]->AddOutputChannel( _chan[px_out], _chan_cred[px_out] ); - _routers[node]->AddInputChannel( _chan[px_in], _chan_cred[px_in] ); - - if(gTrace) { - cout<<"Link "<<" "<GetLatency()<SetLatency( nx_latency ); - _chan_cred[nx_out]->SetLatency( nx_latency ); - } else { - _chan[nx_out]->SetLatency( 1 ); - _chan_cred[nx_out]->SetLatency( 1 ); - } - _routers[node]->AddOutputChannel( _chan[nx_out], _chan_cred[nx_out] ); - _routers[node]->AddInputChannel( _chan[nx_in], _chan_cred[nx_in] ); - - if(gTrace){ - cout<<"Link "<<" "<GetLatency()<SetLatency( py_latency ); - _chan_cred[py_out]->SetLatency( py_latency ); - } else { - _chan[py_out]->SetLatency( 1 ); - _chan_cred[py_out]->SetLatency( 1 ); - } - _routers[node]->AddOutputChannel( _chan[py_out], _chan_cred[py_out] ); - _routers[node]->AddInputChannel( _chan[py_in], _chan_cred[py_in] ); - - if(gTrace){ - cout<<"Link "<<" "<GetLatency()<SetLatency( ny_latency ); - _chan_cred[ny_out]->SetLatency( ny_latency ); - } else { - _chan[ny_out]->SetLatency( 1 ); - _chan_cred[ny_out]->SetLatency( 1 ); - } - _routers[node]->AddOutputChannel( _chan[ny_out], _chan_cred[ny_out] ); - _routers[node]->AddInputChannel( _chan[ny_in], _chan_cred[ny_in] ); - - if(gTrace){ - cout<<"Link "<<" "<GetLatency()< 1){ - if (cur_y == 0) - return gC + NEGATIVE_Y ; - if (cur_y == (gK-1)) - return gC + POSITIVE_Y ; - } - return gC + POSITIVE_X ; - } - if (cur_x > dest_x) { - // Express ? - if ((cur_x - dest_x) > 1){ - if (cur_y == 0) - return gC + NEGATIVE_Y ; - if (cur_y == (gK-1)) - return gC + POSITIVE_Y ; - } - return gC + NEGATIVE_X ; - } - if (cur_y < dest_y) { - // Express? - if ((dest_y - cur_y) > 1) { - if (cur_x == 0) - return gC + NEGATIVE_X ; - if (cur_x == (gK-1)) - return gC + POSITIVE_X ; - } - return gC + POSITIVE_Y ; - } - if (cur_y > dest_y) { - // Express ? - if ((cur_y - dest_y) > 1 ){ - if (cur_x == 0) - return gC + NEGATIVE_X ; - if (cur_x == (gK-1)) - return gC + POSITIVE_X ; - } - return gC + NEGATIVE_Y ; - } - return 0; -} - -// Concentrated Mesh: Y-X -int cmesh_yx( int cur, int dest ) { - const int POSITIVE_X = 0 ; - const int NEGATIVE_X = 1 ; - const int POSITIVE_Y = 2 ; - const int NEGATIVE_Y = 3 ; - - int cur_y = cur / gK ; - int cur_x = cur % gK ; - int dest_y = dest / gK ; - int dest_x = dest % gK ; - - // Dimension-order Routing: y, x - if (cur_y < dest_y) { - // Express? - if ((dest_y - cur_y) > 1) { - if (cur_x == 0) - return gC + NEGATIVE_X ; - if (cur_x == (gK-1)) - return gC + POSITIVE_X ; - } - return gC + POSITIVE_Y ; - } - if (cur_y > dest_y) { - // Express ? - if ((cur_y - dest_y) > 1 ){ - if (cur_x == 0) - return gC + NEGATIVE_X ; - if (cur_x == (gK-1)) - return gC + POSITIVE_X ; - } - return gC + NEGATIVE_Y ; - } - if (cur_x < dest_x) { - // Express? - if ((dest_x - cur_x) > 1){ - if (cur_y == 0) - return gC + NEGATIVE_Y ; - if (cur_y == (gK-1)) - return gC + POSITIVE_Y ; - } - return gC + POSITIVE_X ; - } - if (cur_x > dest_x) { - // Express ? - if ((cur_x - dest_x) > 1){ - if (cur_y == 0) - return gC + NEGATIVE_Y ; - if (cur_y == (gK-1)) - return gC + POSITIVE_Y ; - } - return gC + NEGATIVE_X ; - } - return 0; -} - -void xy_yx_cmesh( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - - // ( Traffic Class , Routing Order ) -> Virtual Channel Range - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - // Current Router - int cur_router = r->GetID(); - - // Destination Router - int dest_router = CMesh::NodeToRouter( f->dest ) ; - - if (dest_router == cur_router) { - - // Forward to processing element - out_port = CMesh::NodeToPort( f->dest ); - - } else { - - // Forward to neighbouring router - - //each class must have at least 2 vcs assigned or else xy_yx will deadlock - int const available_vcs = (vcEnd - vcBegin + 1) / 2; - assert(available_vcs > 0); - - // randomly select dimension order at first hop - bool x_then_y = ((in_channel < gC) ? - (RandomInt(1) > 0) : - (f->vc < (vcBegin + available_vcs))); - - if(x_then_y) { - out_port = cmesh_xy( cur_router, dest_router ); - vcEnd -= available_vcs; - } else { - out_port = cmesh_yx( cur_router, dest_router ); - vcBegin += available_vcs; - } - } - - } - - outputs->Clear(); - - outputs->AddRange( out_port , vcBegin, vcEnd ); -} - -// ---------------------------------------------------------------------- -// -// Concentrated Mesh: Random XY-YX w/o Express Links -// -// cur: current router address -/// dest: destination router address -// -// ---------------------------------------------------------------------- - -int cmesh_xy_no_express( int cur, int dest ) { - - const int POSITIVE_X = 0 ; - const int NEGATIVE_X = 1 ; - const int POSITIVE_Y = 2 ; - const int NEGATIVE_Y = 3 ; - - const int cur_y = cur / gK ; - const int cur_x = cur % gK ; - const int dest_y = dest / gK ; - const int dest_x = dest % gK ; - - - // Note: channel numbers bellow gC (degree of concentration) are - // injection and ejection links - - // Dimension-order Routing: X , Y - if (cur_x < dest_x) { - return gC + POSITIVE_X ; - } - if (cur_x > dest_x) { - return gC + NEGATIVE_X ; - } - if (cur_y < dest_y) { - return gC + POSITIVE_Y ; - } - if (cur_y > dest_y) { - return gC + NEGATIVE_Y ; - } - return 0; -} - -int cmesh_yx_no_express( int cur, int dest ) { - - const int POSITIVE_X = 0 ; - const int NEGATIVE_X = 1 ; - const int POSITIVE_Y = 2 ; - const int NEGATIVE_Y = 3 ; - - const int cur_y = cur / gK ; - const int cur_x = cur % gK ; - const int dest_y = dest / gK ; - const int dest_x = dest % gK ; - - // Note: channel numbers bellow gC (degree of concentration) are - // injection and ejection links - - // Dimension-order Routing: X , Y - if (cur_y < dest_y) { - return gC + POSITIVE_Y ; - } - if (cur_y > dest_y) { - return gC + NEGATIVE_Y ; - } - if (cur_x < dest_x) { - return gC + POSITIVE_X ; - } - if (cur_x > dest_x) { - return gC + NEGATIVE_X ; - } - return 0; -} - -void xy_yx_no_express_cmesh( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - // ( Traffic Class , Routing Order ) -> Virtual Channel Range - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - // Current Router - int cur_router = r->GetID(); - - // Destination Router - int dest_router = CMesh::NodeToRouter( f->dest ); - - if (dest_router == cur_router) { - - // Forward to processing element - out_port = CMesh::NodeToPort( f->dest ); - - } else { - - // Forward to neighbouring router - - //each class must have at least 2 vcs assigned or else xy_yx will deadlock - int const available_vcs = (vcEnd - vcBegin + 1) / 2; - assert(available_vcs > 0); - - // randomly select dimension order at first hop - bool x_then_y = ((in_channel < gC) ? - (RandomInt(1) > 0) : - (f->vc < (vcBegin + available_vcs))); - - if(x_then_y) { - out_port = cmesh_xy_no_express( cur_router, dest_router ); - vcEnd -= available_vcs; - } else { - out_port = cmesh_yx_no_express( cur_router, dest_router ); - vcBegin += available_vcs; - } - } - } - - outputs->Clear(); - - outputs->AddRange( out_port , vcBegin, vcEnd ); -} -//============================================================ -// -//===== -int cmesh_next( int cur, int dest ) { - - const int POSITIVE_X = 0 ; - const int NEGATIVE_X = 1 ; - const int POSITIVE_Y = 2 ; - const int NEGATIVE_Y = 3 ; - - int cur_y = cur / gK ; - int cur_x = cur % gK ; - int dest_y = dest / gK ; - int dest_x = dest % gK ; - - // Dimension-order Routing: x , y - if (cur_x < dest_x) { - // Express? - if ((dest_x - cur_x) > gK/2-1){ - if (cur_y == 0) - return gC + NEGATIVE_Y ; - if (cur_y == (gK-1)) - return gC + POSITIVE_Y ; - } - return gC + POSITIVE_X ; - } - if (cur_x > dest_x) { - // Express ? - if ((cur_x - dest_x) > gK/2-1){ - if (cur_y == 0) - return gC + NEGATIVE_Y ; - if (cur_y == (gK-1)) - return gC + POSITIVE_Y ; - } - return gC + NEGATIVE_X ; - } - if (cur_y < dest_y) { - // Express? - if ((dest_y - cur_y) > gK/2-1) { - if (cur_x == 0) - return gC + NEGATIVE_X ; - if (cur_x == (gK-1)) - return gC + POSITIVE_X ; - } - return gC + POSITIVE_Y ; - } - if (cur_y > dest_y) { - // Express ? - if ((cur_y - dest_y) > gK/2-1){ - if (cur_x == 0) - return gC + NEGATIVE_X ; - if (cur_x == (gK-1)) - return gC + POSITIVE_X ; - } - return gC + NEGATIVE_Y ; - } - - assert(false); - return -1; -} - -void dor_cmesh( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - // ( Traffic Class , Routing Order ) -> Virtual Channel Range - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - // Current Router - int cur_router = r->GetID(); - - // Destination Router - int dest_router = CMesh::NodeToRouter( f->dest ) ; - - if (dest_router == cur_router) { - - // Forward to processing element - out_port = CMesh::NodeToPort( f->dest ) ; - - } else { - - // Forward to neighbouring router - out_port = cmesh_next( cur_router, dest_router ); - } - } - - outputs->Clear(); - - outputs->AddRange( out_port, vcBegin, vcEnd); -} - -//============================================================ -// -//===== -int cmesh_next_no_express( int cur, int dest ) { - - const int POSITIVE_X = 0 ; - const int NEGATIVE_X = 1 ; - const int POSITIVE_Y = 2 ; - const int NEGATIVE_Y = 3 ; - - //magic constant 2, which is supose to be _cX and _cY - int cur_y = cur/gK ; - int cur_x = cur%gK ; - int dest_y = dest/gK; - int dest_x = dest%gK ; - - // Dimension-order Routing: x , y - if (cur_x < dest_x) { - return gC + POSITIVE_X ; - } - if (cur_x > dest_x) { - return gC + NEGATIVE_X ; - } - if (cur_y < dest_y) { - return gC + POSITIVE_Y ; - } - if (cur_y > dest_y) { - return gC + NEGATIVE_Y ; - } - assert(false); - return -1; -} - -void dor_no_express_cmesh( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ) -{ - // ( Traffic Class , Routing Order ) -> Virtual Channel Range - int vcBegin = 0, vcEnd = gNumVCs-1; - if ( f->type == Flit::READ_REQUEST ) { - vcBegin = gReadReqBeginVC; - vcEnd = gReadReqEndVC; - } else if ( f->type == Flit::WRITE_REQUEST ) { - vcBegin = gWriteReqBeginVC; - vcEnd = gWriteReqEndVC; - } else if ( f->type == Flit::READ_REPLY ) { - vcBegin = gReadReplyBeginVC; - vcEnd = gReadReplyEndVC; - } else if ( f->type == Flit::WRITE_REPLY ) { - vcBegin = gWriteReplyBeginVC; - vcEnd = gWriteReplyEndVC; - } - assert(((f->vc >= vcBegin) && (f->vc <= vcEnd)) || (inject && (f->vc < 0))); - - int out_port; - - if(inject) { - - out_port = -1; - - } else { - - // Current Router - int cur_router = r->GetID(); - - // Destination Router - int dest_router = CMesh::NodeToRouter( f->dest ) ; - - if (dest_router == cur_router) { - - // Forward to processing element - out_port = CMesh::NodeToPort( f->dest ); - - } else { - - // Forward to neighbouring router - out_port = cmesh_next_no_express( cur_router, dest_router ); - } - } - - outputs->Clear(); - - outputs->AddRange( out_port, vcBegin, vcEnd ); -} diff --git a/src/intersim2/.svn/pristine/e0/e0e6b10f519b612fdd24fcc64ea62b4d5fdf89fc.svn-base b/src/intersim2/.svn/pristine/e0/e0e6b10f519b612fdd24fcc64ea62b4d5fdf89fc.svn-base deleted file mode 100644 index 02228ef..0000000 --- a/src/intersim2/.svn/pristine/e0/e0e6b10f519b612fdd24fcc64ea62b4d5fdf89fc.svn-base +++ /dev/null @@ -1,74 +0,0 @@ -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - - - -#ifndef _DragonFly_HPP_ -#define _DragonFly_HPP_ - -#include "network.hpp" -#include "routefunc.hpp" - -class DragonFlyNew : public Network { - - int _m; - int _n; - int _r; - int _k; - int _p, _a, _g; - int _radix; - int _net_size; - int _stageout; - int _numinput; - int _stages; - int _num_of_switch; - int _grp_num_routers; - int _grp_num_nodes; - - - void _ComputeSize( const Configuration &config ); - void _BuildNet( const Configuration &config ); - - - -public: - DragonFlyNew( const Configuration &config, const string & name ); - - int GetN( ) const; - int GetK( ) const; - - double Capacity( ) const; - static void RegisterRoutingFunctions(); - void InsertRandomFaults( const Configuration &config ); - -}; -int dragonfly_port(int rID, int source, int dest); - -void ugal_dragonflynew( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ); -void min_dragonflynew( const Router *r, const Flit *f, int in_channel, - OutputSet *outputs, bool inject ); - -#endif diff --git a/src/intersim2/.svn/pristine/e2/e216ca41a2789704029b85d462988590d43813f3.svn-base b/src/intersim2/.svn/pristine/e2/e216ca41a2789704029b85d462988590d43813f3.svn-base deleted file mode 100644 index c27740f..0000000 --- a/src/intersim2/.svn/pristine/e2/e216ca41a2789704029b85d462988590d43813f3.svn-base +++ /dev/null @@ -1,108 +0,0 @@ -/* This program by D E Knuth is in the public domain and freely copyable. - * It is explained in Seminumerical Algorithms, 3rd edition, Section 3.6 - * (or in the errata to the 2nd edition --- see - * http://www-cs-faculty.stanford.edu/~knuth/taocp.html - * in the changes to Volume 2 on pages 171 and following). */ - -/* N.B. The MODIFICATIONS introduced in the 9th printing (2002) are - included here; there's no backwards compatibility with the original. */ - -/* This version also adopts Brendan McKay's suggestion to - accommodate naive users who forget to call ran_start(seed). */ - -/* If you find any bugs, please report them immediately to - * taocp@cs.stanford.edu - * (and you will be rewarded if the bug is genuine). Thanks! */ - -/************ see the book for explanations and caveats! *******************/ -/************ in particular, you need two's complement arithmetic **********/ - -#define KK 100 /* the long lag */ -#define LL 37 /* the short lag */ -#define MM (1L<<30) /* the modulus */ -#define mod_diff(x,y) (((x)-(y))&(MM-1)) /* subtraction mod MM */ - -long ran_x[KK]; /* the generator state */ - -#ifdef __STDC__ -void ran_array(long aa[],int n) -#else -void ran_array(aa,n) /* put n new random numbers in aa */ - long *aa; /* destination */ - int n; /* array length (must be at least KK) */ -#endif -{ - register int i,j; - for (j=0;j=MM) ss-=MM-2; /* cyclic shift 29 bits */ - } - x[1]++; /* make x[1] (and only x[1]) odd */ - for (ss=seed&(MM-1),t=TT-1; t; ) { - for (j=KK-1;j>0;j--) x[j+j]=x[j], x[j+j-1]=0; /* "square" */ - for (j=KK+KK-2;j>=KK;j--) - x[j-(KK-LL)]=mod_diff(x[j-(KK-LL)],x[j]), - x[j-KK]=mod_diff(x[j-KK],x[j]); - if (is_odd(ss)) { /* "multiply by z" */ - for (j=KK;j>0;j--) x[j]=x[j-1]; - x[0]=x[KK]; /* shift the buffer cyclically */ - x[LL]=mod_diff(x[LL],x[KK]); - } - if (ss) ss>>=1; else t--; - } - for (j=0;j=0? *ran_arr_ptr++: ran_arr_cycle()) -long ran_arr_cycle() -{ - if (ran_arr_ptr==&ran_arr_dummy) - ran_start(314159L); /* the user forgot to initialize */ - ran_array(ran_arr_buf,QUALITY); - ran_arr_buf[KK]=-1; - ran_arr_ptr=ran_arr_buf+1; - return ran_arr_buf[0]; -} - -#include -int main() -{ - register int m; long a[2009]; - ran_start(310952L); - for (m=0;m<=2009;m++) ran_array(a,1009); - printf("%ld\n", a[0]); /* 995235265 */ - ran_start(310952L); - for (m=0;m<=1009;m++) ran_array(a,2009); - printf("%ld\n", a[0]); /* 995235265 */ - return 0; -} diff --git a/src/intersim2/.svn/pristine/e3/e3245c11796bcda90ba6909bb34dced14101b2c3.svn-base b/src/intersim2/.svn/pristine/e3/e3245c11796bcda90ba6909bb34dced14101b2c3.svn-base deleted file mode 100644 index e6f382c..0000000 --- a/src/intersim2/.svn/pristine/e3/e3245c11796bcda90ba6909bb34dced14101b2c3.svn-base +++ /dev/null @@ -1,346 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/*booksim_config.cpp - * - *Contains all the configurable parameters in a network - * - */ - - -#include "booksim.hpp" -#include "booksim_config.hpp" - -BookSimConfig::BookSimConfig( ) -{ - //======================================================== - // Network options - //======================================================== - - // Channel length listing file - AddStrField( "channel_file", "" ) ; - - // Physical sub-networks - _int_map["subnets"] = 1; - - //==== Topology options ======================= - AddStrField( "topology", "torus" ); - _int_map["k"] = 8; //network radix - _int_map["n"] = 2; //network dimension - _int_map["c"] = 1; //concentration - AddStrField( "routing_function", "none" ); - - //simulator tries to correclty adjust latency for node/router placement - _int_map["use_noc_latency"] = 1; - - - //used for noc latency calcualtion for network with concentration - _int_map["x"] = 8; //number of routers in X - _int_map["y"] = 8; //number of routers in Y - _int_map["xr"] = 1; //number of nodes per router in X only if c>1 - _int_map["yr"] = 1; //number of nodes per router in Y only if c>1 - - - _int_map["link_failures"] = 0; //legacy - _int_map["fail_seed"] = 0; //legacy - - //==== Single-node options =============================== - - _int_map["in_ports"] = 5; - _int_map["out_ports"] = 5; - - //======================================================== - // Router options - //======================================================== - - //==== General options =================================== - - AddStrField( "router", "iq" ); - - _int_map["output_delay"] = 0; - _int_map["credit_delay"] = 0; - _float_map["internal_speedup"] = 1.0; - - //with switch speedup flits requires otuput buffering - //full output buffer will cancel switch allocation requests - //default setting is unlimited - _int_map["output_buffer_size"] = -1; - - // enable next-hop-output queueing - _int_map["noq"] = 0; - - //==== Input-queued ====================================== - - // Control of virtual channel speculation - _int_map["speculative"] = 0 ; - _int_map["spec_check_elig"] = 1 ; - _int_map["spec_check_cred"] = 1 ; - _int_map["spec_mask_by_reqs"] = 0 ; - AddStrField("spec_sw_allocator", "prio"); - - _int_map["num_vcs"] = 16; - _int_map["vc_buf_size"] = 8; //per vc buffer size - _int_map["buf_size"] = -1; //shared buffer size - AddStrField("buffer_policy", "private"); //buffer sharing policy - - _int_map["private_bufs"] = -1; - _int_map["private_buf_size"] = 1; - AddStrField("private_buf_size", ""); - _int_map["private_buf_start_vc"] = -1; - AddStrField("private_buf_start_vc", ""); - _int_map["private_buf_end_vc"] = -1; - AddStrField("private_buf_end_vc", ""); - - _int_map["max_held_slots"] = -1; - - _int_map["feedback_aging_scale"] = 1; - _int_map["feedback_offset"] = 0; - - _int_map["wait_for_tail_credit"] = 0; // reallocate a VC before a tail credit? - _int_map["vc_busy_when_full"] = 0; // mark VCs as in use when they have no credit available - _int_map["vc_prioritize_empty"] = 0; // prioritize empty VCs over non-empty ones in VC allocation - _int_map["vc_priority_donation"] = 0; // allow high-priority flits to donate their priority to low-priority that they are queued up behind - _int_map["vc_shuffle_requests"] = 0; // rearrange VC allocator requests to avoid unfairness - - _int_map["hold_switch_for_packet"] = 0; // hold a switch config for the entire packet - - _int_map["input_speedup"] = 1; // expansion of input ports into crossbar - _int_map["output_speedup"] = 1; // expansion of output ports into crossbar - - _int_map["routing_delay"] = 1; - _int_map["vc_alloc_delay"] = 1; - _int_map["sw_alloc_delay"] = 1; - _int_map["st_prepare_delay"] = 0; - _int_map["st_final_delay"] = 1; - - //==== Event-driven ===================================== - - _int_map["vct"] = 0; - - //==== Allocators ======================================== - - AddStrField( "vc_allocator", "islip" ); - AddStrField( "sw_allocator", "islip" ); - - AddStrField( "arb_type", "round_robin" ); - - _int_map["alloc_iters"] = 1; - - //==== Traffic ======================================== - - _int_map["classes"] = 1; - - AddStrField( "traffic", "uniform" ); - - _int_map["class_priority"] = 0; - AddStrField("class_priority", ""); // workaraound to allow for vector specification - - _int_map["perm_seed"] = 0; // seed value for random permuation trafficpattern generator - - _float_map["injection_rate"] = 0.1; - AddStrField("injection_rate", ""); // workaraound to allow for vector specification - - _int_map["injection_rate_uses_flits"] = 0; - - // number of flits per packet - _int_map["packet_size"] = 1; - AddStrField("packet_size", ""); // workaraound to allow for vector specification - - // if multiple values are specified per class, set probabilities for each - _int_map["packet_size_rate"] = 1; - AddStrField("packet_size_rate", ""); // workaraound to allow for vector specification - - AddStrField( "injection_process", "bernoulli" ); - - _float_map["burst_alpha"] = 0.5; // burst interval - _float_map["burst_beta"] = 0.5; // burst length - _float_map["burst_r1"] = -1.0; // burst rate - - AddStrField( "priority", "none" ); // message priorities - - _int_map["batch_size"] = 1000; - _int_map["batch_count"] = 1; - _int_map["max_outstanding_requests"] = 0; // 0 = unlimited - - // Use read/write request reply scheme - _int_map["use_read_write"] = 0; - AddStrField("use_read_write", ""); // workaraound to allow for vector specification - _float_map["write_fraction"] = 0.5; - AddStrField("write_fraction", ""); - - // Control assignment of packets to VCs - _int_map["read_request_begin_vc"] = 0; - _int_map["read_request_end_vc"] = 5; - _int_map["write_request_begin_vc"] = 2; - _int_map["write_request_end_vc"] = 7; - _int_map["read_reply_begin_vc"] = 8; - _int_map["read_reply_end_vc"] = 13; - _int_map["write_reply_begin_vc"] = 10; - _int_map["write_reply_end_vc"] = 15; - - // Control Injection of Packets into Replicated Networks - _int_map["read_request_subnet"] = 0; - _int_map["read_reply_subnet"] = 0; - _int_map["write_request_subnet"] = 0; - _int_map["write_reply_subnet"] = 0; - - // Set packet length in flits - _int_map["read_request_size"] = 1; - AddStrField("read_request_size", ""); // workaraound to allow for vector specification - _int_map["write_request_size"] = 1; - AddStrField("write_request_size", ""); // workaraound to allow for vector specification - _int_map["read_reply_size"] = 1; - AddStrField("read_reply_size", ""); // workaraound to allow for vector specification - _int_map["write_reply_size"] = 1; - AddStrField("write_reply_size", ""); // workaraound to allow for vector specification - - //==== Simulation parameters ========================== - - // types: - // latency - average + latency distribution for a particular injection rate - // throughput - sustained throughput for a particular injection rate - - AddStrField( "sim_type", "latency" ); - - _int_map["warmup_periods"] = 3; // number of samples periods to "warm-up" the simulation - - _int_map["sample_period"] = 1000; // how long between measurements - _int_map["max_samples"] = 10; // maximum number of sample periods in a simulation - - // whether or not to measure statistics for a given traffic class - _int_map["measure_stats"] = 1; - AddStrField("measure_stats", ""); // workaround to allow for vector specification - //whether to enable per pair statistics, caution N^2 memory usage - _int_map["pair_stats"] = 0; - - // if avg. latency exceeds the threshold, assume unstable - _float_map["latency_thres"] = 500.0; - AddStrField("latency_thres", ""); // workaround to allow for vector specification - - // consider warmed up once relative change in latency / throughput between successive iterations is smaller than this - _float_map["warmup_thres"] = 0.05; - AddStrField("warmup_thres", ""); // workaround to allow for vector specification - _float_map["acc_warmup_thres"] = 0.05; - AddStrField("acc_warmup_thres", ""); // workaround to allow for vector specification - - // consider converged once relative change in latency / throughput between successive iterations is smaller than this - _float_map["stopping_thres"] = 0.05; - AddStrField("stopping_thres", ""); // workaround to allow for vector specification - _float_map["acc_stopping_thres"] = 0.05; - AddStrField("acc_stopping_thres", ""); // workaround to allow for vector specification - - _int_map["sim_count"] = 1; // number of simulations to perform - - - _int_map["include_queuing"] =1; // non-zero includes source queuing latency - - // _int_map["reorder"] = 0; // know what you're doing - - //_int_map["flit_timing"] = 0; // know what you're doing - //_int_map["split_packets"] = 0; // know what you're doing - - _int_map["seed"] = 0; //random seed for simulation, e.g. traffic - - _int_map["print_activity"] = 0; - - _int_map["print_csv_results"] = 0; - - _int_map["deadlock_warn_timeout"] = 256; - - _int_map["viewer_trace"] = 0; - - AddStrField("watch_file", ""); - - AddStrField("watch_flits", ""); - AddStrField("watch_packets", ""); - AddStrField("watch_transactions", ""); - - AddStrField("watch_out", ""); - - AddStrField("stats_out", ""); - -#ifdef TRACK_FLOWS - AddStrField("injected_flits_out", ""); - AddStrField("received_flits_out", ""); - AddStrField("stored_flits_out", ""); - AddStrField("sent_flits_out", ""); - AddStrField("outstanding_credits_out", ""); - AddStrField("ejected_flits_out", ""); - AddStrField("active_packets_out", ""); -#endif - -#ifdef TRACK_CREDITS - AddStrField("used_credits_out", ""); - AddStrField("free_credits_out", ""); - AddStrField("max_credits_out", ""); -#endif - - // batch only -- packet sequence numbers - AddStrField("sent_packets_out", ""); - - //==================Power model params===================== - _int_map["sim_power"] = 0; - AddStrField("power_output_file","pwr_tmp"); - AddStrField("tech_file", ""); - _int_map["channel_width"] = 128; - _int_map["channel_sweep"] = 0; - - //==================Network file=========================== - AddStrField("network_file",""); -} - - - -PowerConfig::PowerConfig( ) -{ - - _int_map["H_INVD2"] = 0; - _int_map["W_INVD2"] = 0; - _int_map["H_DFQD1"] = 0; - _int_map["W_DFQD1"] = 0; - _int_map["H_ND2D1"] = 0; - _int_map["W_ND2D1"] = 0; - _int_map["H_SRAM"] = 0; - _int_map["W_SRAM"] = 0; - _float_map["Vdd"] = 0; - _float_map["R"] = 0; - _float_map["IoffSRAM"] = 0; - _float_map["IoffP"] = 0; - _float_map["IoffN"] = 0; - _float_map["Cg_pwr"] = 0; - _float_map["Cd_pwr"] = 0; - _float_map["Cgdl"] = 0; - _float_map["Cg"] = 0; - _float_map["Cd"] = 0; - _float_map["LAMBDA"] = 0; - _float_map["MetalPitch"] = 0; - _float_map["Rw"] = 0; - _float_map["Cw_gnd"] = 0; - _float_map["Cw_cpl"] = 0; - _float_map["wire_length"] = 0; - -} diff --git a/src/intersim2/.svn/pristine/e6/e64fcd97a677ff77ec1692273171f513fe794507.svn-base b/src/intersim2/.svn/pristine/e6/e64fcd97a677ff77ec1692273171f513fe794507.svn-base deleted file mode 100644 index 265f6cd..0000000 --- a/src/intersim2/.svn/pristine/e6/e64fcd97a677ff77ec1692273171f513fe794507.svn-base +++ /dev/null @@ -1,132 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _CHAOS_ROUTER_HPP_ -#define _CHAOS_ROUTER_HPP_ - -#include -#include -#include - -#include "module.hpp" -#include "router.hpp" -#include "allocator.hpp" -#include "routefunc.hpp" -#include "outputset.hpp" -#include "buffer_state.hpp" -#include "pipefifo.hpp" -#include "vc.hpp" - -class ChaosRouter : public Router { - - tRoutingFunction _rf; - - vector _input_route; - vector _mq_route; - - enum eQState { - empty, // input avail - filling, // >**H ready to send - full, // T****H ready to send - leaving, // T***> input avail - cut_through, // >***> - shared // >**HT**> - }; - - PipelineFIFO *_crossbar_pipe; - - int _multi_queue_size; - int _buffer_size; - - vector > _input_frame; - vector > _output_frame; - vector > _multi_queue; - - vector _next_queue_cnt; - - vector > _credit_queue; - - vector _input_state; - vector _multi_state; - - vector _input_output_match; - vector _input_mq_match; - vector _multi_match; - - vector _mq_age; - - vector _output_matched; - vector _mq_matched; - - int _cur_channel; - int _read_stall; - - bool _IsInjectionChan( int chan ) const; - bool _IsEjectionChan( int chan ) const; - - bool _InputReady( int input ) const; - bool _OutputFull( int out ) const; - bool _OutputAvail( int out ) const; - bool _MultiQueueFull( int mq ) const; - - int _InputForOutput( int output ) const; - int _MultiQueueForOutput( int output ) const; - int _FindAvailMultiQueue( ) const; - - void _NextInterestingChannel( ); - void _OutputAdvance( ); - void _SendFlits( ); - void _SendCredits( ); - - virtual void _InternalStep( ); - -public: - ChaosRouter( const Configuration& config, - Module *parent, const string & name, int id, - int inputs, int outputs ); - - virtual ~ChaosRouter( ); - - virtual void ReadInputs( ); - virtual void WriteOutputs( ); - - virtual int GetUsedCredit(int out) const {return 0;} - virtual int GetBufferOccupancy(int i) const {return 0;} - -#ifdef TRACK_BUFFERS - virtual int GetUsedCreditForClass(int output, int cl) const {return 0;} - virtual int GetBufferOccupancyForClass(int input, int cl) const {return 0;} -#endif - - virtual vector UsedCredits() const { return vector(); } - virtual vector FreeCredits() const { return vector(); } - virtual vector MaxCredits() const { return vector(); } - - void Display( ostream & os = cout ) const; -}; - -#endif diff --git a/src/intersim2/.svn/pristine/eb/ebec0a8c0098e95bd530e52b0baed6d9a60a33c1.svn-base b/src/intersim2/.svn/pristine/eb/ebec0a8c0098e95bd530e52b0baed6d9a60a33c1.svn-base deleted file mode 100644 index 9da2282..0000000 --- a/src/intersim2/.svn/pristine/eb/ebec0a8c0098e95bd530e52b0baed6d9a60a33c1.svn-base +++ /dev/null @@ -1,190 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include -#include -#include -#include -#include "random_utils.hpp" -#include "injection.hpp" - -using namespace std; - -InjectionProcess::InjectionProcess(int nodes, double rate) - : _nodes(nodes), _rate(rate) -{ - if(nodes <= 0) { - cout << "Error: Number of nodes must be greater than zero." << endl; - exit(-1); - } - if((rate < 0.0) || (rate > 1.0)) { - cout << "Error: Injection process must have load between 0.0 and 1.0." - << endl; - exit(-1); - } -} - -void InjectionProcess::reset() -{ - -} - -InjectionProcess * InjectionProcess::New(string const & inject, int nodes, - double load, - Configuration const * const config) -{ - string process_name; - string param_str; - size_t left = inject.find_first_of('('); - if(left == string::npos) { - process_name = inject; - } else { - process_name = inject.substr(0, left); - size_t right = inject.find_last_of(')'); - if(right == string::npos) { - param_str = inject.substr(left+1); - } else { - param_str = inject.substr(left+1, right-left-1); - } - } - vector params = tokenize_str(param_str); - - InjectionProcess * result = NULL; - if(process_name == "bernoulli") { - result = new BernoulliInjectionProcess(nodes, load); - } else if(process_name == "on_off") { - bool missing_params = false; - double alpha = numeric_limits::quiet_NaN(); - if(params.size() < 1) { - if(config) { - alpha = config->GetFloat("burst_alpha"); - } else { - missing_params = true; - } - } else { - alpha = atof(params[0].c_str()); - } - double beta = numeric_limits::quiet_NaN(); - if(params.size() < 2) { - if(config) { - beta = config->GetFloat("burst_beta"); - } else { - missing_params = true; - } - } else { - beta = atof(params[1].c_str()); - } - double r1 = numeric_limits::quiet_NaN(); - if(params.size() < 3) { - r1 = config ? config->GetFloat("burst_r1") : -1.0; - } else { - r1 = atof(params[2].c_str()); - } - if(missing_params) { - cout << "Missing parameters for injection process: " << inject << endl; - exit(-1); - } - if((alpha < 0.0 && beta < 0.0) || - (alpha < 0.0 && r1 < 0.0) || - (beta < 0.0 && r1 < 0.0) || - (alpha >= 0.0 && beta >= 0.0 && r1 >= 0.0)) { - cout << "Invalid parameters for injection process: " << inject << endl; - exit(-1); - } - vector initial(nodes); - if(params.size() > 3) { - initial = tokenize_int(params[2]); - initial.resize(nodes, initial.back()); - } else { - for(int n = 0; n < nodes; ++n) { - initial[n] = RandomInt(1); - } - } - result = new OnOffInjectionProcess(nodes, load, alpha, beta, r1, initial); - } else { - cout << "Invalid injection process: " << inject << endl; - exit(-1); - } - return result; -} - -//============================================================= - -BernoulliInjectionProcess::BernoulliInjectionProcess(int nodes, double rate) - : InjectionProcess(nodes, rate) -{ - -} - -bool BernoulliInjectionProcess::test(int source) -{ - assert((source >= 0) && (source < _nodes)); - return (RandomFloat() < _rate); -} - -//============================================================= - -OnOffInjectionProcess::OnOffInjectionProcess(int nodes, double rate, - double alpha, double beta, - double r1, vector initial) - : InjectionProcess(nodes, rate), - _alpha(alpha), _beta(beta), _r1(r1), _initial(initial) -{ - assert(alpha <= 1.0); - assert(beta <= 1.0); - assert(r1 <= 1.0); - if(alpha < 0.0) { - assert(beta >= 0.0); - assert(r1 >= 0.0); - _alpha = beta * rate / (r1 - rate); - } else if(beta < 0.0) { - assert(alpha >= 0.0); - assert(r1 >= 0.0); - _beta = alpha * (r1 - rate) / rate; - } else { - assert(r1 < 0.0); - _r1 = rate * (alpha + beta) / alpha; - } - reset(); -} - -void OnOffInjectionProcess::reset() -{ - _state = _initial; -} - -bool OnOffInjectionProcess::test(int source) -{ - assert((source >= 0) && (source < _nodes)); - - // advance state - _state[source] = - _state[source] ? (RandomFloat() >= _beta) : (RandomFloat() < _alpha); - - // generate packet - return _state[source] && (RandomFloat() < _r1); -} diff --git a/src/intersim2/.svn/pristine/ec/ec23715e6e01d44320732e4a8fc186d6b209a3bb.svn-base b/src/intersim2/.svn/pristine/ec/ec23715e6e01d44320732e4a8fc186d6b209a3bb.svn-base deleted file mode 100644 index 8a9833d..0000000 --- a/src/intersim2/.svn/pristine/ec/ec23715e6e01d44320732e4a8fc186d6b209a3bb.svn-base +++ /dev/null @@ -1,120 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "booksim.hpp" -#include - -#include "pim.hpp" -#include "random_utils.hpp" - -//#define DEBUG_PIM - -PIM::PIM( Module *parent, const string& name, - int inputs, int outputs, int iters ) : - DenseAllocator( parent, name, inputs, outputs ), - _PIM_iter(iters) -{ -} - -PIM::~PIM( ) -{ -} - -void PIM::Allocate( ) -{ - int input; - int output; - - int input_offset; - int output_offset; - - for ( int iter = 0; iter < _PIM_iter; ++iter ) { - // Grant phase --- outputs randomly choose - // between one of their requests - - vector grants(_outputs, -1); - - for ( output = 0; output < _outputs; ++output ) { - - // A random arbiter between input requests - input_offset = RandomInt( _inputs - 1 ); - - for ( int i = 0; i < _inputs; ++i ) { - input = ( i + input_offset ) % _inputs; - - if ( ( _request[input][output].label != -1 ) && - ( _inmatch[input] == -1 ) && - ( _outmatch[output] == -1 ) ) { - - // Grant - grants[output] = input; - break; - } - } - } - - // Accept phase -- inputs randomly choose - // between input_speedup of their grants - - for ( input = 0; input < _inputs; ++input ) { - - // A random arbiter between output grants - output_offset = RandomInt( _outputs - 1 ); - - for ( int o = 0; o < _outputs; ++o ) { - output = ( o + output_offset ) % _outputs; - - if ( grants[output] == input ) { - - // Accept - _inmatch[input] = output; - _outmatch[output] = input; - - break; - } - } - } - } - -#ifdef DEBUG_PIM - if ( _outputs == 8 ) { - cout << "input match: " << endl; - for ( int i = 0; i < _inputs; ++i ) { - cout << " from " << i << " to " << _inmatch[i] << endl; - } - cout << endl; - } - - cout << "output match: "; - for ( int j = 0; j < _outputs; ++j ) { - cout << _outmatch[j] << " "; - } - cout << endl; -#endif -} - - diff --git a/src/intersim2/.svn/pristine/ef/ef53e3bc23eac89edf00c7903de88ebb2f4084b6.svn-base b/src/intersim2/.svn/pristine/ef/ef53e3bc23eac89edf00c7903de88ebb2f4084b6.svn-base deleted file mode 100644 index b4202ff..0000000 --- a/src/intersim2/.svn/pristine/ef/ef53e3bc23eac89edf00c7903de88ebb2f4084b6.svn-base +++ /dev/null @@ -1,76 +0,0 @@ -// $Id: dragonflyconfig 3555 2011-05-16 23:37:55Z dub $ - -// Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - - -hold_switch_for_packet=1; - -vc_buf_size = 16; - - -wait_for_tail_credit = 0; - -// -// Router architecture -// -vc_allocator = separable_input_first; -sw_allocator = separable_input_first; -alloc_iters = 1; - -credit_delay = 2; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; -st_final_delay = 1; - -input_speedup = 1; -output_speedup = 1; -internal_speedup = 1.0; - - -warmup_periods = 3; -sim_count = 1; - -sample_period = 10000; - - - -routing_function = nca; -num_vcs = 4; - -priority = none; -traffic = uniform; - -injection_rate = 0.6; -packet_size = 1; -injection_rate_uses_flits=1; - -topology = fattree; - - -k = 4; -n = 3; - -watch_out=-; \ No newline at end of file diff --git a/src/intersim2/.svn/pristine/f0/f0994d52a0bff0a75bf779e8ec53715b011bfd97.svn-base b/src/intersim2/.svn/pristine/f0/f0994d52a0bff0a75bf779e8ec53715b011bfd97.svn-base deleted file mode 100644 index c2640f9..0000000 --- a/src/intersim2/.svn/pristine/f0/f0994d52a0bff0a75bf779e8ec53715b011bfd97.svn-base +++ /dev/null @@ -1,112 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "booksim.hpp" -#include - -#include "loa.hpp" -#include "random_utils.hpp" - -LOA::LOA( Module *parent, const string& name, - int inputs, int outputs ) : - DenseAllocator( parent, name, inputs, outputs ) -{ - _req.resize(inputs); - _counts.resize(outputs); - - _rptr.resize(inputs); - _gptr.resize(outputs); -} - -void LOA::Allocate( ) -{ - int input; - int output; - - int input_offset; - int output_offset; - - int lonely; - int lonely_cnt; - - // Count phase --- the number of requests - // per output is counted - - for ( int j = 0; j < _outputs; ++j ) { - _counts[j] = 0; - for ( int i = 0; i < _inputs; ++i ) { - _counts[j] += ( _request[i][j].label != -1 ) ? 1 : 0; - } - } - - // Request phase - for ( input = 0; input < _inputs; ++input ) { - - // Find the lonely output - output_offset = _rptr[input]; - lonely = -1; - lonely_cnt = _inputs + 1; - - for ( int o = 0; o < _outputs; ++o ) { - output = ( o + output_offset ) % _outputs; - - if ( ( _request[input][output].label != -1 ) && - ( _counts[output] < lonely_cnt ) ) { - lonely = output; - lonely_cnt = _counts[output]; - } - } - - // Request the lonely output (-1 for no request) - _req[input] = lonely; - } - - // Grant phase - for ( output = 0; output < _outputs; ++output ) { - input_offset = _gptr[output]; - - for ( int i = 0; i < _inputs; ++i ) { - input = ( i + input_offset ) % _inputs; - - if ( _req[input] == output ) { - // Grant! - - _inmatch[input] = output; - _outmatch[output] = input; - - _rptr[input] = ( _rptr[input] + 1 ) % _outputs; - _gptr[output] = ( _gptr[output] + 1 ) % _inputs; - - break; - } - } - } - - -} - - diff --git a/src/intersim2/.svn/pristine/f1/f18798b1a209786e47ee28ef3d5c7b5e908e0642.svn-base b/src/intersim2/.svn/pristine/f1/f18798b1a209786e47ee28ef3d5c7b5e908e0642.svn-base deleted file mode 100644 index 835d627..0000000 --- a/src/intersim2/.svn/pristine/f1/f18798b1a209786e47ee28ef3d5c7b5e908e0642.svn-base +++ /dev/null @@ -1,48 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _ROUTEFUNC_HPP_ -#define _ROUTEFUNC_HPP_ - -#include "flit.hpp" -#include "router.hpp" -#include "outputset.hpp" -#include "config_utils.hpp" - -typedef void (*tRoutingFunction)( const Router *, const Flit *, int in_channel, OutputSet *, bool ); - -void InitializeRoutingMap( const Configuration & config ); - -extern map gRoutingFunctionMap; - -extern int gNumVCs; -extern int gReadReqBeginVC, gReadReqEndVC; -extern int gWriteReqBeginVC, gWriteReqEndVC; -extern int gReadReplyBeginVC, gReadReplyEndVC; -extern int gWriteReplyBeginVC, gWriteReplyEndVC; - -#endif diff --git a/src/intersim2/.svn/pristine/f3/f3f385cd24e067dc09ab89284d234593352ee0bf.svn-base b/src/intersim2/.svn/pristine/f3/f3f385cd24e067dc09ab89284d234593352ee0bf.svn-base deleted file mode 100644 index 7d5e0e3..0000000 --- a/src/intersim2/.svn/pristine/f3/f3f385cd24e067dc09ab89284d234593352ee0bf.svn-base +++ /dev/null @@ -1,153 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/*outputset.cpp - * - *output set assigns a flit which output to go to in a router - *used by the VC class - *the output assignment is done by the routing algorithms.. - * - */ - -#include - -#include "booksim.hpp" -#include "outputset.hpp" - -void OutputSet::Clear( ) -{ - _outputs.clear( ); -} - -void OutputSet::Add( int output_port, int vc, int pri ) -{ - AddRange( output_port, vc, vc, pri ); -} - -void OutputSet::AddRange( int output_port, int vc_start, int vc_end, int pri ) -{ - - sSetElement s; - - s.vc_start = vc_start; - s.vc_end = vc_end; - s.pri = pri; - s.output_port = output_port; - _outputs.insert( s ); -} - -//legacy support, for performance, just use GetSet() -int OutputSet::NumVCs( int output_port ) const -{ - int total = 0; - set::const_iterator i = _outputs.begin( ); - while(i!=_outputs.end( )){ - if(i->output_port == output_port){ - total += (i->vc_end - i->vc_start + 1); - } - i++; - } - return total; -} - -bool OutputSet::OutputEmpty( int output_port ) const -{ - set::const_iterator i = _outputs.begin( ); - while(i!=_outputs.end( )){ - if(i->output_port == output_port){ - return false; - } - i++; - } - return true; -} - - -const set & OutputSet::GetSet() const{ - return _outputs; -} - -//legacy support, for performance, just use GetSet() -int OutputSet::GetVC( int output_port, int vc_index, int *pri ) const -{ - - int range; - int remaining = vc_index; - int vc = -1; - - if ( pri ) { *pri = -1; } - - set::const_iterator i = _outputs.begin( ); - while(i!=_outputs.end( )){ - if(i->output_port == output_port){ - range = i->vc_end - i->vc_start + 1; - if ( remaining >= range ) { - remaining -= range; - } else { - vc = i->vc_start + remaining; - if ( pri ) { - *pri = i->pri; - } - break; - } - } - i++; - } - return vc; -} - -//legacy support, for performance, just use GetSet() -bool OutputSet::GetPortVC( int *out_port, int *out_vc ) const -{ - - - bool single_output = false; - int used_outputs = 0; - - set::const_iterator i = _outputs.begin( ); - if(i!=_outputs.end( )){ - used_outputs = i->output_port; - } - while(i!=_outputs.end( )){ - - if ( i->vc_start == i->vc_end ) { - *out_vc = i->vc_start; - *out_port = i->output_port; - single_output = true; - } else { - // multiple vc's selected - break; - } - if (used_outputs != i->output_port) { - // multiple outputs selected - single_output = false; - break; - } - i++; - } - return single_output; -} diff --git a/src/intersim2/.svn/pristine/f4/f47cc0dc517c023ddeaf70f92c90e0ecfe343030.svn-base b/src/intersim2/.svn/pristine/f4/f47cc0dc517c023ddeaf70f92c90e0ecfe343030.svn-base deleted file mode 100644 index c953713..0000000 --- a/src/intersim2/.svn/pristine/f4/f47cc0dc517c023ddeaf70f92c90e0ecfe343030.svn-base +++ /dev/null @@ -1,26 +0,0 @@ -// 2007 ITRS predictions for a 32nm high-performance library -H_INVD2 = 8;//int -W_INVD2 = 3;//int -H_DFQD1 = 8;//int -W_DFQD1 = 16;//int -H_ND2D1 = 8;//int -W_ND2D1 = 3;//int -H_SRAM = 8;//int -W_SRAM = 6;//int -Vdd = 0.9;//float -R = 606.321;//float -IoffSRAM = 0.00000032;//float -// 70 C -IoffP = 0.00000102;//float -IoffN = 0.00000102;//float -Cg_pwr = 0.000000000000000534;//float -Cd_pwr = 0.000000000000000267;//float -Cgdl = 0.0000000000000001068;//float -Cg = 0.000000000000000534;//float -Cd = 0.000000000000000267;//float -LAMBDA = 0.016;//float -MetalPitch = 0.000080;//float -Rw = 0.720044;//float -Cw_gnd = 0.000000000000267339;//float -Cw_cpl = 0.000000000000267339;//float -wire_length = 2.0;//float \ No newline at end of file diff --git a/src/intersim2/.svn/pristine/f4/f48f9ec9cbd794b900c47d4fa1af919f73f844ab.svn-base b/src/intersim2/.svn/pristine/f4/f48f9ec9cbd794b900c47d4fa1af919f73f844ab.svn-base deleted file mode 100644 index be47efa..0000000 --- a/src/intersim2/.svn/pristine/f4/f48f9ec9cbd794b900c47d4fa1af919f73f844ab.svn-base +++ /dev/null @@ -1,53 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _FLY_HPP_ -#define _FLY_HPP_ - -#include "network.hpp" - -class KNFly : public Network { - - int _k; - int _n; - - void _ComputeSize( const Configuration &config ); - void _BuildNet( const Configuration &config ); - - int _OutChannel( int stage, int addr, int port ) const; - int _InChannel( int stage, int addr, int port ) const; - -public: - KNFly( const Configuration &config, const string & name ); - - int GetN( ) const; - int GetK( ) const; - static void RegisterRoutingFunctions(){}; - double Capacity( ) const; -}; - -#endif diff --git a/src/intersim2/.svn/pristine/f7/f7c0ca6108d1e538b05438c69b603d0d1903688f.svn-base b/src/intersim2/.svn/pristine/f7/f7c0ca6108d1e538b05438c69b603d0d1903688f.svn-base deleted file mode 100644 index b6b3ffb..0000000 --- a/src/intersim2/.svn/pristine/f7/f7c0ca6108d1e538b05438c69b603d0d1903688f.svn-base +++ /dev/null @@ -1,79 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/*credit.cpp - * - *A class for credits - */ - -#include "booksim.hpp" -#include "credit.hpp" - -stack Credit::_all; -stack Credit::_free; - -Credit::Credit() -{ - Reset(); -} - -void Credit::Reset() -{ - vc.clear(); - head = false; - tail = false; - id = -1; -} - -Credit * Credit::New() { - Credit * c; - if(_free.empty()) { - c = new Credit(); - _all.push(c); - } else { - c = _free.top(); - c->Reset(); - _free.pop(); - } - return c; -} - -void Credit::Free() { - _free.push(this); -} - -void Credit::FreeAll() { - while(!_all.empty()) { - delete _all.top(); - _all.pop(); - } -} - - -int Credit::OutStanding(){ - return _all.size()-_free.size(); -} diff --git a/src/intersim2/.svn/pristine/f8/f88e58811f1c40d35b795e6d317579cc2c3668d0.svn-base b/src/intersim2/.svn/pristine/f8/f88e58811f1c40d35b795e6d317579cc2c3668d0.svn-base deleted file mode 100644 index b2db309..0000000 --- a/src/intersim2/.svn/pristine/f8/f88e58811f1c40d35b795e6d317579cc2c3668d0.svn-base +++ /dev/null @@ -1,2385 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include "iq_router.hpp" - -#include -#include -#include -#include -#include -#include -#include - -#include "globals.hpp" -#include "random_utils.hpp" -#include "vc.hpp" -#include "routefunc.hpp" -#include "outputset.hpp" -#include "buffer.hpp" -#include "buffer_state.hpp" -#include "roundrobin_arb.hpp" -#include "allocator.hpp" -#include "switch_monitor.hpp" -#include "buffer_monitor.hpp" - -IQRouter::IQRouter( Configuration const & config, Module *parent, - string const & name, int id, int inputs, int outputs ) -: Router( config, parent, name, id, inputs, outputs ), _active(false) -{ - _vcs = config.GetInt( "num_vcs" ); - - _vc_busy_when_full = (config.GetInt("vc_busy_when_full") > 0); - _vc_prioritize_empty = (config.GetInt("vc_prioritize_empty") > 0); - _vc_shuffle_requests = (config.GetInt("vc_shuffle_requests") > 0); - - _speculative = (config.GetInt("speculative") > 0); - _spec_check_elig = (config.GetInt("spec_check_elig") > 0); - _spec_check_cred = (config.GetInt("spec_check_cred") > 0); - _spec_mask_by_reqs = (config.GetInt("spec_mask_by_reqs") > 0); - - _routing_delay = config.GetInt( "routing_delay" ); - _vc_alloc_delay = config.GetInt( "vc_alloc_delay" ); - if(!_vc_alloc_delay) { - Error("VC allocator cannot have zero delay."); - } - _sw_alloc_delay = config.GetInt( "sw_alloc_delay" ); - if(!_sw_alloc_delay) { - Error("Switch allocator cannot have zero delay."); - } - - // Routing - string const rf = config.GetStr("routing_function") + "_" + config.GetStr("topology"); - map::const_iterator rf_iter = gRoutingFunctionMap.find(rf); - if(rf_iter == gRoutingFunctionMap.end()) { - Error("Invalid routing function: " + rf); - } - _rf = rf_iter->second; - - // Alloc VC's - _buf.resize(_inputs); - for ( int i = 0; i < _inputs; ++i ) { - ostringstream module_name; - module_name << "buf_" << i; - _buf[i] = new Buffer(config, _outputs, this, module_name.str( ) ); - module_name.str(""); - } - - // Alloc next VCs' buffer state - _next_buf.resize(_outputs); - for (int j = 0; j < _outputs; ++j) { - ostringstream module_name; - module_name << "next_vc_o" << j; - _next_buf[j] = new BufferState( config, this, module_name.str( ) ); - module_name.str(""); - } - - // Alloc allocators - string vc_alloc_type = config.GetStr( "vc_allocator" ); - if(vc_alloc_type == "piggyback") { - if(!_speculative) { - Error("Piggyback VC allocation requires speculative switch allocation to be enabled."); - } - _vc_allocator = NULL; - _vc_rr_offset.resize(_outputs*_classes, -1); - } else { - _vc_allocator = Allocator::NewAllocator( this, "vc_allocator", - vc_alloc_type, - _vcs*_inputs, - _vcs*_outputs ); - - if ( !_vc_allocator ) { - Error("Unknown vc_allocator type: " + vc_alloc_type); - } - } - - string sw_alloc_type = config.GetStr( "sw_allocator" ); - _sw_allocator = Allocator::NewAllocator( this, "sw_allocator", - sw_alloc_type, - _inputs*_input_speedup, - _outputs*_output_speedup ); - - if ( !_sw_allocator ) { - Error("Unknown sw_allocator type: " + sw_alloc_type); - } - - string spec_sw_alloc_type = config.GetStr( "spec_sw_allocator" ); - if ( _speculative && ( spec_sw_alloc_type != "prio" ) ) { - _spec_sw_allocator = Allocator::NewAllocator( this, "spec_sw_allocator", - spec_sw_alloc_type, - _inputs*_input_speedup, - _outputs*_output_speedup ); - if ( !_spec_sw_allocator ) { - Error("Unknown spec_sw_allocator type: " + spec_sw_alloc_type); - } - } else { - _spec_sw_allocator = NULL; - } - - _sw_rr_offset.resize(_inputs*_input_speedup); - for(int i = 0; i < _inputs*_input_speedup; ++i) - _sw_rr_offset[i] = i % _input_speedup; - - _noq = config.GetInt("noq") > 0; - if(_noq) { - if(_routing_delay) { - Error("NOQ requires lookahead routing to be enabled."); - } - if(_vcs < _outputs) { - Error("NOQ requires at least as many VCs as router outputs."); - } - } - _noq_next_output_port.resize(_inputs, vector(_vcs, -1)); - _noq_next_vc_start.resize(_inputs, vector(_vcs, -1)); - _noq_next_vc_end.resize(_inputs, vector(_vcs, -1)); - - // Output queues - _output_buffer_size = config.GetInt("output_buffer_size"); - _output_buffer.resize(_outputs); - _credit_buffer.resize(_inputs); - - // Switch configuration (when held for multiple cycles) - _hold_switch_for_packet = (config.GetInt("hold_switch_for_packet") > 0); - _switch_hold_in.resize(_inputs*_input_speedup, -1); - _switch_hold_out.resize(_outputs*_output_speedup, -1); - _switch_hold_vc.resize(_inputs*_input_speedup, -1); - - _bufferMonitor = new BufferMonitor(inputs, _classes); - _switchMonitor = new SwitchMonitor(inputs, outputs, _classes); - -#ifdef TRACK_FLOWS - for(int c = 0; c < _classes; ++c) { - _stored_flits[c].resize(_inputs, 0); - _active_packets[c].resize(_inputs, 0); - } - _outstanding_classes.resize(_outputs, vector >(_vcs)); -#endif -} - -IQRouter::~IQRouter( ) -{ - - if(gPrintActivity) { - cout << Name() << ".bufferMonitor:" << endl ; - cout << *_bufferMonitor << endl ; - - cout << Name() << ".switchMonitor:" << endl ; - cout << "Inputs=" << _inputs ; - cout << "Outputs=" << _outputs ; - cout << *_switchMonitor << endl ; - } - - for(int i = 0; i < _inputs; ++i) - delete _buf[i]; - - for(int j = 0; j < _outputs; ++j) - delete _next_buf[j]; - - delete _vc_allocator; - delete _sw_allocator; - if(_spec_sw_allocator) - delete _spec_sw_allocator; - - delete _bufferMonitor; - delete _switchMonitor; -} - -void IQRouter::AddOutputChannel(FlitChannel * channel, CreditChannel * backchannel) -{ - int alloc_delay = _speculative ? max(_vc_alloc_delay, _sw_alloc_delay) : (_vc_alloc_delay + _sw_alloc_delay); - int min_latency = 1 + _crossbar_delay + channel->GetLatency() + _routing_delay + alloc_delay + backchannel->GetLatency() + _credit_delay; - _next_buf[_output_channels.size()]->SetMinLatency(min_latency); - Router::AddOutputChannel(channel, backchannel); -} - -void IQRouter::ReadInputs( ) -{ - bool have_flits = _ReceiveFlits( ); - bool have_credits = _ReceiveCredits( ); - _active = _active || have_flits || have_credits; -} - -void IQRouter::_InternalStep( ) -{ - if(!_active) { - return; - } - - _InputQueuing( ); - bool activity = !_proc_credits.empty(); - - if(!_route_vcs.empty()) - _RouteEvaluate( ); - if(_vc_allocator) { - _vc_allocator->Clear(); - if(!_vc_alloc_vcs.empty()) - _VCAllocEvaluate( ); - } - if(_hold_switch_for_packet) { - if(!_sw_hold_vcs.empty()) - _SWHoldEvaluate( ); - } - _sw_allocator->Clear(); - if(_spec_sw_allocator) - _spec_sw_allocator->Clear(); - if(!_sw_alloc_vcs.empty()) - _SWAllocEvaluate( ); - if(!_crossbar_flits.empty()) - _SwitchEvaluate( ); - - if(!_route_vcs.empty()) { - _RouteUpdate( ); - activity = activity || !_route_vcs.empty(); - } - if(!_vc_alloc_vcs.empty()) { - _VCAllocUpdate( ); - activity = activity || !_vc_alloc_vcs.empty(); - } - if(_hold_switch_for_packet) { - if(!_sw_hold_vcs.empty()) { - _SWHoldUpdate( ); - activity = activity || !_sw_hold_vcs.empty(); - } - } - if(!_sw_alloc_vcs.empty()) { - _SWAllocUpdate( ); - activity = activity || !_sw_alloc_vcs.empty(); - } - if(!_crossbar_flits.empty()) { - _SwitchUpdate( ); - activity = activity || !_crossbar_flits.empty(); - } - - _active = activity; - - _OutputQueuing( ); - - _bufferMonitor->cycle( ); - _switchMonitor->cycle( ); -} - -void IQRouter::WriteOutputs( ) -{ - _SendFlits( ); - _SendCredits( ); -} - - -//------------------------------------------------------------------------------ -// read inputs -//------------------------------------------------------------------------------ - -bool IQRouter::_ReceiveFlits( ) -{ - bool activity = false; - for(int input = 0; input < _inputs; ++input) { - Flit * const f = _input_channels[input]->Receive(); - if(f) { - -#ifdef TRACK_FLOWS - ++_received_flits[f->cl][input]; -#endif - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Received flit " << f->id - << " from channel at input " << input - << "." << endl; - } - _in_queue_flits.insert(make_pair(input, f)); - activity = true; - } - } - return activity; -} - -bool IQRouter::_ReceiveCredits( ) -{ - bool activity = false; - for(int output = 0; output < _outputs; ++output) { - Credit * const c = _output_credits[output]->Receive(); - if(c) { - _proc_credits.push_back(make_pair(GetSimTime() + _credit_delay, - make_pair(c, output))); - activity = true; - } - } - return activity; -} - - -//------------------------------------------------------------------------------ -// input queuing -//------------------------------------------------------------------------------ - -void IQRouter::_InputQueuing( ) -{ - for(map::const_iterator iter = _in_queue_flits.begin(); - iter != _in_queue_flits.end(); - ++iter) { - - int const input = iter->first; - assert((input >= 0) && (input < _inputs)); - - Flit * const f = iter->second; - assert(f); - - int const vc = f->vc; - assert((vc >= 0) && (vc < _vcs)); - - Buffer * const cur_buf = _buf[input]; - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Adding flit " << f->id - << " to VC " << vc - << " at input " << input - << " (state: " << VC::VCSTATE[cur_buf->GetState(vc)]; - if(cur_buf->Empty(vc)) { - *gWatchOut << ", empty"; - } else { - assert(cur_buf->FrontFlit(vc)); - *gWatchOut << ", front: " << cur_buf->FrontFlit(vc)->id; - } - *gWatchOut << ")." << endl; - } - cur_buf->AddFlit(vc, f); - -#ifdef TRACK_FLOWS - ++_stored_flits[f->cl][input]; - if(f->head) ++_active_packets[f->cl][input]; -#endif - - _bufferMonitor->write(input, f) ; - - if(cur_buf->GetState(vc) == VC::idle) { - assert(cur_buf->FrontFlit(vc) == f); - assert(cur_buf->GetOccupancy(vc) == 1); - assert(f->head); - assert(_switch_hold_vc[input*_input_speedup + vc%_input_speedup] != vc); - if(_routing_delay) { - cur_buf->SetState(vc, VC::routing); - _route_vcs.push_back(make_pair(-1, make_pair(input, vc))); - } else { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Using precomputed lookahead routing information for VC " << vc - << " at input " << input - << " (front: " << f->id - << ")." << endl; - } - cur_buf->SetRouteSet(vc, &f->la_route_set); - cur_buf->SetState(vc, VC::vc_alloc); - if(_speculative) { - _sw_alloc_vcs.push_back(make_pair(-1, make_pair(make_pair(input, vc), - -1))); - } - if(_vc_allocator) { - _vc_alloc_vcs.push_back(make_pair(-1, make_pair(make_pair(input, vc), - -1))); - } - if(_noq) { - _UpdateNOQ(input, vc, f); - } - } - } else if((cur_buf->GetState(vc) == VC::active) && - (cur_buf->FrontFlit(vc) == f)) { - if(_switch_hold_vc[input*_input_speedup + vc%_input_speedup] == vc) { - _sw_hold_vcs.push_back(make_pair(-1, make_pair(make_pair(input, vc), - -1))); - } else { - _sw_alloc_vcs.push_back(make_pair(-1, make_pair(make_pair(input, vc), - -1))); - } - } - } - _in_queue_flits.clear(); - - while(!_proc_credits.empty()) { - - pair > const & item = _proc_credits.front(); - - int const time = item.first; - if(GetSimTime() < time) { - break; - } - - Credit * const c = item.second.first; - assert(c); - - int const output = item.second.second; - assert((output >= 0) && (output < _outputs)); - - BufferState * const dest_buf = _next_buf[output]; - -#ifdef TRACK_FLOWS - for(set::const_iterator iter = c->vc.begin(); iter != c->vc.end(); ++iter) { - int const vc = *iter; - assert(!_outstanding_classes[output][vc].empty()); - int cl = _outstanding_classes[output][vc].front(); - _outstanding_classes[output][vc].pop(); - assert(_outstanding_credits[cl][output] > 0); - --_outstanding_credits[cl][output]; - } -#endif - - dest_buf->ProcessCredit(c); - c->Free(); - _proc_credits.pop_front(); - } -} - - -//------------------------------------------------------------------------------ -// routing -//------------------------------------------------------------------------------ - -void IQRouter::_RouteEvaluate( ) -{ - assert(_routing_delay); - - for(deque > >::iterator iter = _route_vcs.begin(); - iter != _route_vcs.end(); - ++iter) { - - int const time = iter->first; - if(time >= 0) { - break; - } - iter->first = GetSimTime() + _routing_delay - 1; - - int const input = iter->second.first; - assert((input >= 0) && (input < _inputs)); - int const vc = iter->second.second; - assert((vc >= 0) && (vc < _vcs)); - - Buffer const * const cur_buf = _buf[input]; - assert(!cur_buf->Empty(vc)); - assert(cur_buf->GetState(vc) == VC::routing); - - Flit const * const f = cur_buf->FrontFlit(vc); - assert(f); - assert(f->vc == vc); - assert(f->head); - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Beginning routing for VC " << vc - << " at input " << input - << " (front: " << f->id - << ")." << endl; - } - } -} - -void IQRouter::_RouteUpdate( ) -{ - assert(_routing_delay); - - while(!_route_vcs.empty()) { - - pair > const & item = _route_vcs.front(); - - int const time = item.first; - if((time < 0) || (GetSimTime() < time)) { - break; - } - assert(GetSimTime() == time); - - int const input = item.second.first; - assert((input >= 0) && (input < _inputs)); - int const vc = item.second.second; - assert((vc >= 0) && (vc < _vcs)); - - Buffer * const cur_buf = _buf[input]; - assert(!cur_buf->Empty(vc)); - assert(cur_buf->GetState(vc) == VC::routing); - - Flit * const f = cur_buf->FrontFlit(vc); - assert(f); - assert(f->vc == vc); - assert(f->head); - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Completed routing for VC " << vc - << " at input " << input - << " (front: " << f->id - << ")." << endl; - } - - cur_buf->Route(vc, _rf, this, f, input); - cur_buf->SetState(vc, VC::vc_alloc); - if(_speculative) { - _sw_alloc_vcs.push_back(make_pair(-1, make_pair(item.second, -1))); - } - if(_vc_allocator) { - _vc_alloc_vcs.push_back(make_pair(-1, make_pair(item.second, -1))); - } - // NOTE: No need to handle NOQ here, as it requires lookahead routing! - _route_vcs.pop_front(); - } -} - - -//------------------------------------------------------------------------------ -// VC allocation -//------------------------------------------------------------------------------ - -void IQRouter::_VCAllocEvaluate( ) -{ - assert(_vc_allocator); - - bool watched = false; - - for(deque, int> > >::iterator iter = _vc_alloc_vcs.begin(); - iter != _vc_alloc_vcs.end(); - ++iter) { - - int const time = iter->first; - if(time >= 0) { - break; - } - - int const input = iter->second.first.first; - assert((input >= 0) && (input < _inputs)); - int const vc = iter->second.first.second; - assert((vc >= 0) && (vc < _vcs)); - - assert(iter->second.second == -1); - - Buffer const * const cur_buf = _buf[input]; - assert(!cur_buf->Empty(vc)); - assert(cur_buf->GetState(vc) == VC::vc_alloc); - - Flit const * const f = cur_buf->FrontFlit(vc); - assert(f); - assert(f->vc == vc); - assert(f->head); - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Beginning VC allocation for VC " << vc - << " at input " << input - << " (front: " << f->id - << ")." << endl; - } - - OutputSet const * const route_set = cur_buf->GetRouteSet(vc); - assert(route_set); - - int const out_priority = cur_buf->GetPriority(vc); - set const setlist = route_set->GetSet(); - - bool elig = false; - bool cred = false; - bool reserved = false; - - assert(!_noq || (setlist.size() == 1)); - - for(set::const_iterator iset = setlist.begin(); - iset != setlist.end(); - ++iset) { - - int const out_port = iset->output_port; - assert((out_port >= 0) && (out_port < _outputs)); - - BufferState const * const dest_buf = _next_buf[out_port]; - - int vc_start; - int vc_end; - - if(_noq && _noq_next_output_port[input][vc] >= 0) { - assert(!_routing_delay); - vc_start = _noq_next_vc_start[input][vc]; - vc_end = _noq_next_vc_end[input][vc]; - } else { - vc_start = iset->vc_start; - vc_end = iset->vc_end; - } - assert(vc_start >= 0 && vc_start < _vcs); - assert(vc_end >= 0 && vc_end < _vcs); - assert(vc_end >= vc_start); - - for(int out_vc = vc_start; out_vc <= vc_end; ++out_vc) { - assert((out_vc >= 0) && (out_vc < _vcs)); - - int in_priority = iset->pri; - if(_vc_prioritize_empty && !dest_buf->IsEmptyFor(out_vc)) { - assert(in_priority >= 0); - in_priority += numeric_limits::min(); - } - - // On the input input side, a VC might request several output VCs. - // These VCs can be prioritized by the routing function, and this is - // reflected in "in_priority". On the output side, if multiple VCs are - // requesting the same output VC, the priority of VCs is based on the - // actual packet priorities, which is reflected in "out_priority". - - if(!dest_buf->IsAvailableFor(out_vc)) { - if(f->watch) { - int const use_input_and_vc = dest_buf->UsedBy(out_vc); - int const use_input = use_input_and_vc / _vcs; - int const use_vc = use_input_and_vc % _vcs; - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " VC " << out_vc - << " at output " << out_port - << " is in use by VC " << use_vc - << " at input " << use_input; - Flit * cf = _buf[use_input]->FrontFlit(use_vc); - if(cf) { - *gWatchOut << " (front flit: " << cf->id << ")"; - } else { - *gWatchOut << " (empty)"; - } - *gWatchOut << "." << endl; - } - } else { - elig = true; - if(_vc_busy_when_full && dest_buf->IsFullFor(out_vc)) { - if(f->watch) - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " VC " << out_vc - << " at output " << out_port - << " is full." << endl; - reserved |= !dest_buf->IsFull(); - } else { - cred = true; - if(f->watch){ - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Requesting VC " << out_vc - << " at output " << out_port - << " (in_pri: " << in_priority - << ", out_pri: " << out_priority - << ")." << endl; - watched = true; - } - int const input_and_vc - = _vc_shuffle_requests ? (vc*_inputs + input) : (input*_vcs + vc); - _vc_allocator->AddRequest(input_and_vc, out_port*_vcs + out_vc, - 0, in_priority, out_priority); - } - } - } - } - if(!elig) { - iter->second.second = STALL_BUFFER_BUSY; - } else if(_vc_busy_when_full && !cred) { - iter->second.second = reserved ? STALL_BUFFER_RESERVED : STALL_BUFFER_FULL; - } - } - - if(watched) { - *gWatchOut << GetSimTime() << " | " << _vc_allocator->FullName() << " | "; - _vc_allocator->PrintRequests( gWatchOut ); - } - - _vc_allocator->Allocate(); - - if(watched) { - *gWatchOut << GetSimTime() << " | " << _vc_allocator->FullName() << " | "; - _vc_allocator->PrintGrants( gWatchOut ); - } - - for(deque, int> > >::iterator iter = _vc_alloc_vcs.begin(); - iter != _vc_alloc_vcs.end(); - ++iter) { - - int const time = iter->first; - if(time >= 0) { - break; - } - iter->first = GetSimTime() + _vc_alloc_delay - 1; - - int const input = iter->second.first.first; - assert((input >= 0) && (input < _inputs)); - int const vc = iter->second.first.second; - assert((vc >= 0) && (vc < _vcs)); - - if(iter->second.second < -1) { - continue; - } - - assert(iter->second.second == -1); - - Buffer const * const cur_buf = _buf[input]; - assert(!cur_buf->Empty(vc)); - assert(cur_buf->GetState(vc) == VC::vc_alloc); - - Flit const * const f = cur_buf->FrontFlit(vc); - assert(f); - assert(f->vc == vc); - assert(f->head); - - int const input_and_vc - = _vc_shuffle_requests ? (vc*_inputs + input) : (input*_vcs + vc); - int const output_and_vc = _vc_allocator->OutputAssigned(input_and_vc); - - if(output_and_vc >= 0) { - - int const match_output = output_and_vc / _vcs; - assert((match_output >= 0) && (match_output < _outputs)); - int const match_vc = output_and_vc % _vcs; - assert((match_vc >= 0) && (match_vc < _vcs)); - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Assigning VC " << match_vc - << " at output " << match_output - << " to VC " << vc - << " at input " << input - << "." << endl; - } - - iter->second.second = output_and_vc; - - } else { - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "VC allocation failed for VC " << vc - << " at input " << input - << "." << endl; - } - - iter->second.second = STALL_BUFFER_CONFLICT; - - } - } - - if(_vc_alloc_delay <= 1) { - return; - } - - for(deque, int> > >::iterator iter = _vc_alloc_vcs.begin(); - iter != _vc_alloc_vcs.end(); - ++iter) { - - int const time = iter->first; - assert(time >= 0); - if(GetSimTime() < time) { - break; - } - - assert(iter->second.second != -1); - - int const output_and_vc = iter->second.second; - - if(output_and_vc >= 0) { - - int const match_output = output_and_vc / _vcs; - assert((match_output >= 0) && (match_output < _outputs)); - int const match_vc = output_and_vc % _vcs; - assert((match_vc >= 0) && (match_vc < _vcs)); - - BufferState const * const dest_buf = _next_buf[match_output]; - - int const input = iter->second.first.first; - assert((input >= 0) && (input < _inputs)); - int const vc = iter->second.first.second; - assert((vc >= 0) && (vc < _vcs)); - - Buffer const * const cur_buf = _buf[input]; - assert(!cur_buf->Empty(vc)); - assert(cur_buf->GetState(vc) == VC::vc_alloc); - - Flit const * const f = cur_buf->FrontFlit(vc); - assert(f); - assert(f->vc == vc); - assert(f->head); - - if(!dest_buf->IsAvailableFor(match_vc)) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Discarding previously generated grant for VC " << vc - << " at input " << input - << ": VC " << match_vc - << " at output " << match_output - << " is no longer available." << endl; - } - iter->second.second = STALL_BUFFER_BUSY; - } else if(_vc_busy_when_full && dest_buf->IsFullFor(match_vc)) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Discarding previously generated grant for VC " << vc - << " at input " << input - << ": VC " << match_vc - << " at output " << match_output - << " has become full." << endl; - } - iter->second.second = dest_buf->IsFull() ? STALL_BUFFER_FULL : STALL_BUFFER_RESERVED; - } - } - } -} - -void IQRouter::_VCAllocUpdate( ) -{ - assert(_vc_allocator); - - while(!_vc_alloc_vcs.empty()) { - - pair, int> > const & item = _vc_alloc_vcs.front(); - - int const time = item.first; - if((time < 0) || (GetSimTime() < time)) { - break; - } - assert(GetSimTime() == time); - - int const input = item.second.first.first; - assert((input >= 0) && (input < _inputs)); - int const vc = item.second.first.second; - assert((vc >= 0) && (vc < _vcs)); - - assert(item.second.second != -1); - - Buffer * const cur_buf = _buf[input]; - assert(!cur_buf->Empty(vc)); - assert(cur_buf->GetState(vc) == VC::vc_alloc); - - Flit const * const f = cur_buf->FrontFlit(vc); - assert(f); - assert(f->vc == vc); - assert(f->head); - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Completed VC allocation for VC " << vc - << " at input " << input - << " (front: " << f->id - << ")." << endl; - } - - int const output_and_vc = item.second.second; - - if(output_and_vc >= 0) { - - int const match_output = output_and_vc / _vcs; - assert((match_output >= 0) && (match_output < _outputs)); - int const match_vc = output_and_vc % _vcs; - assert((match_vc >= 0) && (match_vc < _vcs)); - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Acquiring assigned VC " << match_vc - << " at output " << match_output - << "." << endl; - } - - BufferState * const dest_buf = _next_buf[match_output]; - assert(dest_buf->IsAvailableFor(match_vc)); - - dest_buf->TakeBuffer(match_vc, input*_vcs + vc); - - cur_buf->SetOutput(vc, match_output, match_vc); - cur_buf->SetState(vc, VC::active); - if(!_speculative) { - _sw_alloc_vcs.push_back(make_pair(-1, make_pair(item.second.first, -1))); - } - } else { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " No output VC allocated." << endl; - } - -#ifdef TRACK_STALLS - assert((output_and_vc == STALL_BUFFER_BUSY) || - (output_and_vc == STALL_BUFFER_CONFLICT)); - if(output_and_vc == STALL_BUFFER_BUSY) { - ++_buffer_busy_stalls[f->cl]; - } else if(output_and_vc == STALL_BUFFER_CONFLICT) { - ++_buffer_conflict_stalls[f->cl]; - } -#endif - - _vc_alloc_vcs.push_back(make_pair(-1, make_pair(item.second.first, -1))); - } - _vc_alloc_vcs.pop_front(); - } -} - - -//------------------------------------------------------------------------------ -// switch holding -//------------------------------------------------------------------------------ - -void IQRouter::_SWHoldEvaluate( ) -{ - assert(_hold_switch_for_packet); - - for(deque, int> > >::iterator iter = _sw_hold_vcs.begin(); - iter != _sw_hold_vcs.end(); - ++iter) { - - int const time = iter->first; - if(time >= 0) { - break; - } - iter->first = GetSimTime(); - - int const input = iter->second.first.first; - assert((input >= 0) && (input < _inputs)); - int const vc = iter->second.first.second; - assert((vc >= 0) && (vc < _vcs)); - - assert(iter->second.second == -1); - - Buffer const * const cur_buf = _buf[input]; - assert(!cur_buf->Empty(vc)); - assert(cur_buf->GetState(vc) == VC::active); - - Flit const * const f = cur_buf->FrontFlit(vc); - assert(f); - assert(f->vc == vc); - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Beginning held switch allocation for VC " << vc - << " at input " << input - << " (front: " << f->id - << ")." << endl; - } - - int const expanded_input = input * _input_speedup + vc % _input_speedup; - assert(_switch_hold_vc[expanded_input] == vc); - - int const match_port = cur_buf->GetOutputPort(vc); - assert((match_port >= 0) && (match_port < _outputs)); - int const match_vc = cur_buf->GetOutputVC(vc); - assert((match_vc >= 0) && (match_vc < _vcs)); - - int const expanded_output = match_port*_output_speedup + input%_output_speedup; - assert(_switch_hold_in[expanded_input] == expanded_output); - - BufferState const * const dest_buf = _next_buf[match_port]; - - if(dest_buf->IsFullFor(match_vc)) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Unable to reuse held connection from input " << input - << "." << (expanded_input % _input_speedup) - << " to output " << match_port - << "." << (expanded_output % _output_speedup) - << ": No credit available." << endl; - } - iter->second.second = dest_buf->IsFull() ? STALL_BUFFER_FULL : STALL_BUFFER_RESERVED; - } else { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Reusing held connection from input " << input - << "." << (expanded_input % _input_speedup) - << " to output " << match_port - << "." << (expanded_output % _output_speedup) - << "." << endl; - } - iter->second.second = expanded_output; - } - } -} - -void IQRouter::_SWHoldUpdate( ) -{ - assert(_hold_switch_for_packet); - - while(!_sw_hold_vcs.empty()) { - - pair, int> > const & item = _sw_hold_vcs.front(); - - int const time = item.first; - if(time < 0) { - break; - } - assert(GetSimTime() == time); - - int const input = item.second.first.first; - assert((input >= 0) && (input < _inputs)); - int const vc = item.second.first.second; - assert((vc >= 0) && (vc < _vcs)); - - assert(item.second.second != -1); - - Buffer * const cur_buf = _buf[input]; - assert(!cur_buf->Empty(vc)); - assert(cur_buf->GetState(vc) == VC::active); - - Flit * const f = cur_buf->FrontFlit(vc); - assert(f); - assert(f->vc == vc); - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Completed held switch allocation for VC " << vc - << " at input " << input - << " (front: " << f->id - << ")." << endl; - } - - int const expanded_input = input * _input_speedup + vc % _input_speedup; - assert(_switch_hold_vc[expanded_input] == vc); - - int const expanded_output = item.second.second; - - if(expanded_output >= 0 && ( _output_buffer_size==-1 || _output_buffer[expanded_output].size()= 0) && (output < _outputs)); - assert(cur_buf->GetOutputPort(vc) == output); - - int const match_vc = cur_buf->GetOutputVC(vc); - assert((match_vc >= 0) && (match_vc < _vcs)); - - BufferState * const dest_buf = _next_buf[output]; - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Scheduling switch connection from input " << input - << "." << (vc % _input_speedup) - << " to output " << output - << "." << (expanded_output % _output_speedup) - << "." << endl; - } - - cur_buf->RemoveFlit(vc); - -#ifdef TRACK_FLOWS - --_stored_flits[f->cl][input]; - if(f->tail) --_active_packets[f->cl][input]; -#endif - - _bufferMonitor->read(input, f) ; - - f->hops++; - f->vc = match_vc; - - if(!_routing_delay && f->head) { - const FlitChannel * channel = _output_channels[output]; - const Router * router = channel->GetSink(); - if(router) { - if(_noq) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Updating lookahead routing information for flit " << f->id - << " (NOQ)." << endl; - } - int next_output_port = _noq_next_output_port[input][vc]; - assert(next_output_port >= 0); - _noq_next_output_port[input][vc] = -1; - int next_vc_start = _noq_next_vc_start[input][vc]; - assert(next_vc_start >= 0 && next_vc_start < _vcs); - _noq_next_vc_start[input][vc] = -1; - int next_vc_end = _noq_next_vc_end[input][vc]; - assert(next_vc_end >= 0 && next_vc_end < _vcs); - _noq_next_vc_end[input][vc] = -1; - f->la_route_set.Clear(); - f->la_route_set.AddRange(next_output_port, next_vc_start, next_vc_end); - } else { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Updating lookahead routing information for flit " << f->id - << "." << endl; - } - int in_channel = channel->GetSinkPort(); - _rf(router, f, in_channel, &f->la_route_set, false); - } - } else { - f->la_route_set.Clear(); - } - } - -#ifdef TRACK_FLOWS - ++_outstanding_credits[f->cl][output]; - _outstanding_classes[output][f->vc].push(f->cl); -#endif - - dest_buf->SendingFlit(f); - - _crossbar_flits.push_back(make_pair(-1, make_pair(f, make_pair(expanded_input, expanded_output)))); - - if(_out_queue_credits.count(input) == 0) { - _out_queue_credits.insert(make_pair(input, Credit::New())); - } - _out_queue_credits.find(input)->second->vc.insert(vc); - - if(cur_buf->Empty(vc)) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Cancelling held connection from input " << input - << "." << (expanded_input % _input_speedup) - << " to " << output - << "." << (expanded_output % _output_speedup) - << ": No more flits." << endl; - } - _switch_hold_vc[expanded_input] = -1; - _switch_hold_in[expanded_input] = -1; - _switch_hold_out[expanded_output] = -1; - if(f->tail) { - cur_buf->SetState(vc, VC::idle); - } - } else { - Flit * const nf = cur_buf->FrontFlit(vc); - assert(nf); - assert(nf->vc == vc); - if(f->tail) { - assert(nf->head); - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Cancelling held connection from input " << input - << "." << (expanded_input % _input_speedup) - << " to " << output - << "." << (expanded_output % _output_speedup) - << ": End of packet." << endl; - } - _switch_hold_vc[expanded_input] = -1; - _switch_hold_in[expanded_input] = -1; - _switch_hold_out[expanded_output] = -1; - if(_routing_delay) { - cur_buf->SetState(vc, VC::routing); - _route_vcs.push_back(make_pair(-1, item.second.first)); - } else { - if(nf->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Using precomputed lookahead routing information for VC " << vc - << " at input " << input - << " (front: " << nf->id - << ")." << endl; - } - cur_buf->SetRouteSet(vc, &nf->la_route_set); - cur_buf->SetState(vc, VC::vc_alloc); - if(_speculative) { - _sw_alloc_vcs.push_back(make_pair(-1, make_pair(item.second.first, - -1))); - } - if(_vc_allocator) { - _vc_alloc_vcs.push_back(make_pair(-1, make_pair(item.second.first, - -1))); - } - if(_noq) { - _UpdateNOQ(input, vc, nf); - } - } - } else { - _sw_hold_vcs.push_back(make_pair(-1, make_pair(item.second.first, - -1))); - } - } - } else { - //when internal speedup >1.0, the buffer stall stats may not be accruate - assert((expanded_output == STALL_BUFFER_FULL) || - (expanded_output == STALL_BUFFER_RESERVED) || !( _output_buffer_size==-1 || _output_buffer[expanded_output].size()= 0); - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Cancelling held connection from input " << input - << "." << (expanded_input % _input_speedup) - << " to " << (held_expanded_output / _output_speedup) - << "." << (held_expanded_output % _output_speedup) - << ": Flit not sent." << endl; - } - _switch_hold_vc[expanded_input] = -1; - _switch_hold_in[expanded_input] = -1; - _switch_hold_out[held_expanded_output] = -1; - _sw_alloc_vcs.push_back(make_pair(-1, make_pair(item.second.first, - -1))); - } - _sw_hold_vcs.pop_front(); - } -} - - -//------------------------------------------------------------------------------ -// switch allocation -//------------------------------------------------------------------------------ - -bool IQRouter::_SWAllocAddReq(int input, int vc, int output) -{ - assert(input >= 0 && input < _inputs); - assert(vc >= 0 && vc < _vcs); - assert(output >= 0 && output < _outputs); - - // When input_speedup > 1, the virtual channel buffers are interleaved to - // create multiple input ports to the switch. Similarily, the output ports - // are interleaved based on their originating input when output_speedup > 1. - - int const expanded_input = input * _input_speedup + vc % _input_speedup; - int const expanded_output = output * _output_speedup + input % _output_speedup; - - Buffer const * const cur_buf = _buf[input]; - assert(!cur_buf->Empty(vc)); - assert((cur_buf->GetState(vc) == VC::active) || - (_speculative && (cur_buf->GetState(vc) == VC::vc_alloc))); - - Flit const * const f = cur_buf->FrontFlit(vc); - assert(f); - assert(f->vc == vc); - - if((_switch_hold_in[expanded_input] < 0) && - (_switch_hold_out[expanded_output] < 0)) { - - Allocator * allocator = _sw_allocator; - int prio = cur_buf->GetPriority(vc); - - if(_speculative && (cur_buf->GetState(vc) == VC::vc_alloc)) { - if(_spec_sw_allocator) { - allocator = _spec_sw_allocator; - } else { - assert(prio >= 0); - prio += numeric_limits::min(); - } - } - - Allocator::sRequest req; - - if(allocator->ReadRequest(req, expanded_input, expanded_output)) { - if(RoundRobinArbiter::Supersedes(vc, prio, req.label, req.in_pri, - _sw_rr_offset[expanded_input], _vcs)) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Replacing earlier request from VC " << req.label - << " for output " << output - << "." << (expanded_output % _output_speedup) - << " with priority " << req.in_pri - << " (" << ((cur_buf->GetState(vc) == VC::active) ? - "non-spec" : - "spec") - << ", pri: " << prio - << ")." << endl; - } - allocator->RemoveRequest(expanded_input, expanded_output, req.label); - allocator->AddRequest(expanded_input, expanded_output, vc, prio, prio); - return true; - } - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Output " << output - << "." << (expanded_output % _output_speedup) - << " was already requested by VC " << req.label - << " with priority " << req.in_pri - << " (pri: " << prio - << ")." << endl; - } - return false; - } - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Requesting output " << output - << "." << (expanded_output % _output_speedup) - << " (" << ((cur_buf->GetState(vc) == VC::active) ? - "non-spec" : - "spec") - << ", pri: " << prio - << ")." << endl; - } - allocator->AddRequest(expanded_input, expanded_output, vc, prio, prio); - return true; - } - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Ignoring output " << output - << "." << (expanded_output % _output_speedup) - << " due to switch hold ("; - if(_switch_hold_in[expanded_input] >= 0) { - *gWatchOut << "input: " << input - << "." << (expanded_input % _input_speedup); - if(_switch_hold_out[expanded_output] >= 0) { - *gWatchOut << ", "; - } - } - if(_switch_hold_out[expanded_output] >= 0) { - *gWatchOut << "output: " << output - << "." << (expanded_output % _output_speedup); - } - *gWatchOut << ")." << endl; - } - return false; -} - -void IQRouter::_SWAllocEvaluate( ) -{ - bool watched = false; - - for(deque, int> > >::iterator iter = _sw_alloc_vcs.begin(); - iter != _sw_alloc_vcs.end(); - ++iter) { - - int const time = iter->first; - if(time >= 0) { - break; - } - - int const input = iter->second.first.first; - assert((input >= 0) && (input < _inputs)); - int const vc = iter->second.first.second; - assert((vc >= 0) && (vc < _vcs)); - - assert(iter->second.second == -1); - - assert(_switch_hold_vc[input * _input_speedup + vc % _input_speedup] != vc); - - Buffer const * const cur_buf = _buf[input]; - assert(!cur_buf->Empty(vc)); - assert((cur_buf->GetState(vc) == VC::active) || - (_speculative && (cur_buf->GetState(vc) == VC::vc_alloc))); - - Flit const * const f = cur_buf->FrontFlit(vc); - assert(f); - assert(f->vc == vc); - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Beginning switch allocation for VC " << vc - << " at input " << input - << " (front: " << f->id - << ")." << endl; - } - - if(cur_buf->GetState(vc) == VC::active) { - - int const dest_output = cur_buf->GetOutputPort(vc); - assert((dest_output >= 0) && (dest_output < _outputs)); - int const dest_vc = cur_buf->GetOutputVC(vc); - assert((dest_vc >= 0) && (dest_vc < _vcs)); - - BufferState const * const dest_buf = _next_buf[dest_output]; - - if(dest_buf->IsFullFor(dest_vc) || ( _output_buffer_size!=-1 && _output_buffer[dest_output].size()>=(size_t)(_output_buffer_size))) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " VC " << dest_vc - << " at output " << dest_output - << " is full." << endl; - } - iter->second.second = dest_buf->IsFull() ? STALL_BUFFER_FULL : STALL_BUFFER_RESERVED; - continue; - } - bool const requested = _SWAllocAddReq(input, vc, dest_output); - watched |= requested && f->watch; - continue; - } - assert(_speculative && (cur_buf->GetState(vc) == VC::vc_alloc)); - assert(f->head); - - // The following models the speculative VC allocation aspects of the - // pipeline. An input VC with a request in for an egress virtual channel - // will also speculatively bid for the switch regardless of whether the VC - // allocation succeeds. - - OutputSet const * const route_set = cur_buf->GetRouteSet(vc); - assert(route_set); - - set const setlist = route_set->GetSet(); - - assert(!_noq || (setlist.size() == 1)); - - for(set::const_iterator iset = setlist.begin(); - iset != setlist.end(); - ++iset) { - - int const dest_output = iset->output_port; - assert((dest_output >= 0) && (dest_output < _outputs)); - - // for lower levels of speculation, ignore credit availability and always - // issue requests for all output ports in route set - - BufferState const * const dest_buf = _next_buf[dest_output]; - - bool elig = false; - bool cred = false; - - if(_spec_check_elig) { - - // for higher levels of speculation, check if at least one suitable VC - // is available at the current output - - int vc_start; - int vc_end; - - if(_noq && _noq_next_output_port[input][vc] >= 0) { - assert(!_routing_delay); - vc_start = _noq_next_vc_start[input][vc]; - vc_end = _noq_next_vc_end[input][vc]; - } else { - vc_start = iset->vc_start; - vc_end = iset->vc_end; - } - assert(vc_start >= 0 && vc_start < _vcs); - assert(vc_end >= 0 && vc_end < _vcs); - assert(vc_end >= vc_start); - - for(int dest_vc = vc_start; dest_vc <= vc_end; ++dest_vc) { - assert((dest_vc >= 0) && (dest_vc < _vcs)); - - if(dest_buf->IsAvailableFor(dest_vc) && ( _output_buffer_size==-1 || _output_buffer[dest_output].size()<(size_t)(_output_buffer_size))) { - elig = true; - if(!_spec_check_cred || !dest_buf->IsFullFor(dest_vc)) { - cred = true; - break; - } - } - } - } - - if(_spec_check_elig && !elig) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Output " << dest_output - << " has no suitable VCs available." << endl; - } - iter->second.second = STALL_BUFFER_BUSY; - } else if(_spec_check_cred && !cred) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " All suitable VCs at output " << dest_output - << " are full." << endl; - } - iter->second.second = dest_buf->IsFull() ? STALL_BUFFER_FULL : STALL_BUFFER_RESERVED; - } else { - bool const requested = _SWAllocAddReq(input, vc, dest_output); - watched |= requested && f->watch; - } - } - } - - if(watched) { - *gWatchOut << GetSimTime() << " | " << _sw_allocator->FullName() << " | "; - _sw_allocator->PrintRequests(gWatchOut); - if(_spec_sw_allocator) { - *gWatchOut << GetSimTime() << " | " << _spec_sw_allocator->FullName() << " | "; - _spec_sw_allocator->PrintRequests(gWatchOut); - } - } - - _sw_allocator->Allocate(); - if(_spec_sw_allocator) - _spec_sw_allocator->Allocate(); - - if(watched) { - *gWatchOut << GetSimTime() << " | " << _sw_allocator->FullName() << " | "; - _sw_allocator->PrintGrants(gWatchOut); - if(_spec_sw_allocator) { - *gWatchOut << GetSimTime() << " | " << _spec_sw_allocator->FullName() << " | "; - _spec_sw_allocator->PrintGrants(gWatchOut); - } - } - - for(deque, int> > >::iterator iter = _sw_alloc_vcs.begin(); - iter != _sw_alloc_vcs.end(); - ++iter) { - - int const time = iter->first; - if(time >= 0) { - break; - } - iter->first = GetSimTime() + _sw_alloc_delay - 1; - - int const input = iter->second.first.first; - assert((input >= 0) && (input < _inputs)); - int const vc = iter->second.first.second; - assert((vc >= 0) && (vc < _vcs)); - - if(iter->second.second < -1) { - continue; - } - - assert(iter->second.second == -1); - - Buffer const * const cur_buf = _buf[input]; - assert(!cur_buf->Empty(vc)); - assert((cur_buf->GetState(vc) == VC::active) || - (_speculative && (cur_buf->GetState(vc) == VC::vc_alloc))); - - Flit const * const f = cur_buf->FrontFlit(vc); - assert(f); - assert(f->vc == vc); - - int const expanded_input = input * _input_speedup + vc % _input_speedup; - - int expanded_output = _sw_allocator->OutputAssigned(expanded_input); - - if(expanded_output >= 0) { - assert((expanded_output % _output_speedup) == (input % _output_speedup)); - int const granted_vc = _sw_allocator->ReadRequest(expanded_input, expanded_output); - if(granted_vc == vc) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Assigning output " << (expanded_output / _output_speedup) - << "." << (expanded_output % _output_speedup) - << " to VC " << vc - << " at input " << input - << "." << (vc % _input_speedup) - << "." << endl; - } - _sw_rr_offset[expanded_input] = (vc + _input_speedup) % _vcs; - iter->second.second = expanded_output; - } else { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Switch allocation failed for VC " << vc - << " at input " << input - << ": Granted to VC " << granted_vc << "." << endl; - } - iter->second.second = STALL_CROSSBAR_CONFLICT; - } - } else if(_spec_sw_allocator) { - expanded_output = _spec_sw_allocator->OutputAssigned(expanded_input); - if(expanded_output >= 0) { - assert((expanded_output % _output_speedup) == (input % _output_speedup)); - if(_spec_mask_by_reqs && - _sw_allocator->OutputHasRequests(expanded_output)) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Discarding speculative grant for VC " << vc - << " at input " << input - << "." << (vc % _input_speedup) - << " because output " << (expanded_output / _output_speedup) - << "." << (expanded_output % _output_speedup) - << " has non-speculative requests." << endl; - } - iter->second.second = STALL_CROSSBAR_CONFLICT; - } else if(!_spec_mask_by_reqs && - (_sw_allocator->InputAssigned(expanded_output) >= 0)) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Discarding speculative grant for VC " << vc - << " at input " << input - << "." << (vc % _input_speedup) - << " because output " << (expanded_output / _output_speedup) - << "." << (expanded_output % _output_speedup) - << " has a non-speculative grant." << endl; - } - iter->second.second = STALL_CROSSBAR_CONFLICT; - } else { - int const granted_vc = _spec_sw_allocator->ReadRequest(expanded_input, - expanded_output); - if(granted_vc == vc) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Assigning output " << (expanded_output / _output_speedup) - << "." << (expanded_output % _output_speedup) - << " to VC " << vc - << " at input " << input - << "." << (vc % _input_speedup) - << "." << endl; - } - _sw_rr_offset[expanded_input] = (vc + _input_speedup) % _vcs; - iter->second.second = expanded_output; - } else { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Switch allocation failed for VC " << vc - << " at input " << input - << ": Granted to VC " << granted_vc << "." << endl; - } - iter->second.second = STALL_CROSSBAR_CONFLICT; - } - } - } else { - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Switch allocation failed for VC " << vc - << " at input " << input - << ": No output granted." << endl; - } - - iter->second.second = STALL_CROSSBAR_CONFLICT; - - } - } else { - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Switch allocation failed for VC " << vc - << " at input " << input - << ": No output granted." << endl; - } - - iter->second.second = STALL_CROSSBAR_CONFLICT; - - } - } - - if(!_speculative && (_sw_alloc_delay <= 1)) { - return; - } - - for(deque, int> > >::iterator iter = _sw_alloc_vcs.begin(); - iter != _sw_alloc_vcs.end(); - ++iter) { - - int const time = iter->first; - assert(time >= 0); - if(GetSimTime() < time) { - break; - } - - assert(iter->second.second != -1); - - int const expanded_output = iter->second.second; - - if(expanded_output >= 0) { - - int const output = expanded_output / _output_speedup; - assert((output >= 0) && (output < _outputs)); - - BufferState const * const dest_buf = _next_buf[output]; - - int const input = iter->second.first.first; - assert((input >= 0) && (input < _inputs)); - assert((input % _output_speedup) == (expanded_output % _output_speedup)); - int const vc = iter->second.first.second; - assert((vc >= 0) && (vc < _vcs)); - - int const expanded_input = input * _input_speedup + vc % _input_speedup; - assert(_switch_hold_vc[expanded_input] != vc); - - Buffer const * const cur_buf = _buf[input]; - assert(!cur_buf->Empty(vc)); - assert((cur_buf->GetState(vc) == VC::active) || - (_speculative && (cur_buf->GetState(vc) == VC::vc_alloc))); - - Flit const * const f = cur_buf->FrontFlit(vc); - assert(f); - assert(f->vc == vc); - - if((_switch_hold_in[expanded_input] >= 0) || - (_switch_hold_out[expanded_output] >= 0)) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Discarding grant from input " << input - << "." << (vc % _input_speedup) - << " to output " << output - << "." << (expanded_output % _output_speedup) - << " due to conflict with held connection at "; - if(_switch_hold_in[expanded_input] >= 0) { - *gWatchOut << "input"; - } - if((_switch_hold_in[expanded_input] >= 0) && - (_switch_hold_out[expanded_output] >= 0)) { - *gWatchOut << " and "; - } - if(_switch_hold_out[expanded_output] >= 0) { - *gWatchOut << "output"; - } - *gWatchOut << "." << endl; - } - iter->second.second = STALL_CROSSBAR_CONFLICT; - } else if(_speculative && (cur_buf->GetState(vc) == VC::vc_alloc)) { - - assert(f->head); - - if(_vc_allocator) { // separate VC and switch allocators - - int const input_and_vc = - _vc_shuffle_requests ? (vc*_inputs + input) : (input*_vcs + vc); - int const output_and_vc = _vc_allocator->OutputAssigned(input_and_vc); - - if(output_and_vc < 0) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Discarding grant from input " << input - << "." << (vc % _input_speedup) - << " to output " << output - << "." << (expanded_output % _output_speedup) - << " due to misspeculation." << endl; - } - iter->second.second = -1; // stall is counted in VC allocation path! - } else if((output_and_vc / _vcs) != output) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Discarding grant from input " << input - << "." << (vc % _input_speedup) - << " to output " << output - << "." << (expanded_output % _output_speedup) - << " due to port mismatch between VC and switch allocator." << endl; - } - iter->second.second = STALL_BUFFER_CONFLICT; // count this case as if we had failed allocation - } else if(dest_buf->IsFullFor((output_and_vc % _vcs))) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Discarding grant from input " << input - << "." << (vc % _input_speedup) - << " to output " << output - << "." << (expanded_output % _output_speedup) - << " due to lack of credit." << endl; - } - iter->second.second = dest_buf->IsFull() ? STALL_BUFFER_FULL : STALL_BUFFER_RESERVED; - } - - } else { // VC allocation is piggybacked onto switch allocation - - OutputSet const * const route_set = cur_buf->GetRouteSet(vc); - assert(route_set); - - set const setlist = route_set->GetSet(); - - bool busy = true; - bool full = true; - bool reserved = false; - - assert(!_noq || (setlist.size() == 1)); - - for(set::const_iterator iset = setlist.begin(); - iset != setlist.end(); - ++iset) { - if(iset->output_port == output) { - - int vc_start; - int vc_end; - - if(_noq && _noq_next_output_port[input][vc] >= 0) { - assert(!_routing_delay); - vc_start = _noq_next_vc_start[input][vc]; - vc_end = _noq_next_vc_end[input][vc]; - } else { - vc_start = iset->vc_start; - vc_end = iset->vc_end; - } - assert(vc_start >= 0 && vc_start < _vcs); - assert(vc_end >= 0 && vc_end < _vcs); - assert(vc_end >= vc_start); - - for(int out_vc = vc_start; out_vc <= vc_end; ++out_vc) { - assert((out_vc >= 0) && (out_vc < _vcs)); - if(dest_buf->IsAvailableFor(out_vc)) { - busy = false; - if(!dest_buf->IsFullFor(out_vc)) { - full = false; - break; - } else if(!dest_buf->IsFull()) { - reserved = true; - } - } - } - if(!full) { - break; - } - } - } - - if(busy) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Discarding grant from input " << input - << "." << (vc % _input_speedup) - << " to output " << output - << "." << (expanded_output % _output_speedup) - << " because no suitable output VC for piggyback allocation is available." << endl; - } - iter->second.second = STALL_BUFFER_BUSY; - } else if(full) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Discarding grant from input " << input - << "." << (vc % _input_speedup) - << " to output " << output - << "." << (expanded_output % _output_speedup) - << " because all suitable output VCs for piggyback allocation are full." << endl; - } - iter->second.second = reserved ? STALL_BUFFER_RESERVED : STALL_BUFFER_FULL; - } - - } - - } else { - assert(cur_buf->GetOutputPort(vc) == output); - - int const match_vc = cur_buf->GetOutputVC(vc); - assert((match_vc >= 0) && (match_vc < _vcs)); - - if(dest_buf->IsFullFor(match_vc)) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Discarding grant from input " << input - << "." << (vc % _input_speedup) - << " to output " << output - << "." << (expanded_output % _output_speedup) - << " due to lack of credit." << endl; - } - iter->second.second = dest_buf->IsFull() ? STALL_BUFFER_FULL : STALL_BUFFER_RESERVED; - } - } - } - } -} - -void IQRouter::_SWAllocUpdate( ) -{ - while(!_sw_alloc_vcs.empty()) { - - pair, int> > const & item = _sw_alloc_vcs.front(); - - int const time = item.first; - if((time < 0) || (GetSimTime() < time)) { - break; - } - assert(GetSimTime() == time); - - int const input = item.second.first.first; - assert((input >= 0) && (input < _inputs)); - int const vc = item.second.first.second; - assert((vc >= 0) && (vc < _vcs)); - - Buffer * const cur_buf = _buf[input]; - assert(!cur_buf->Empty(vc)); - assert((cur_buf->GetState(vc) == VC::active) || - (_speculative && (cur_buf->GetState(vc) == VC::vc_alloc))); - - Flit * const f = cur_buf->FrontFlit(vc); - assert(f); - assert(f->vc == vc); - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Completed switch allocation for VC " << vc - << " at input " << input - << " (front: " << f->id - << ")." << endl; - } - - int const expanded_output = item.second.second; - - if(expanded_output >= 0) { - - int const expanded_input = input * _input_speedup + vc % _input_speedup; - assert(_switch_hold_vc[expanded_input] < 0); - assert(_switch_hold_in[expanded_input] < 0); - assert(_switch_hold_out[expanded_output] < 0); - - int const output = expanded_output / _output_speedup; - assert((output >= 0) && (output < _outputs)); - - BufferState * const dest_buf = _next_buf[output]; - - int match_vc; - - if(!_vc_allocator && (cur_buf->GetState(vc) == VC::vc_alloc)) { - - assert(f->head); - - int const cl = f->cl; - assert((cl >= 0) && (cl < _classes)); - - int const vc_offset = _vc_rr_offset[output*_classes+cl]; - - match_vc = -1; - int match_prio = numeric_limits::min(); - - const OutputSet * route_set = cur_buf->GetRouteSet(vc); - set const setlist = route_set->GetSet(); - - assert(!_noq || (setlist.size() == 1)); - - for(set::const_iterator iset = setlist.begin(); - iset != setlist.end(); - ++iset) { - if(iset->output_port == output) { - - int vc_start; - int vc_end; - - if(_noq && _noq_next_output_port[input][vc] >= 0) { - assert(!_routing_delay); - vc_start = _noq_next_vc_start[input][vc]; - vc_end = _noq_next_vc_end[input][vc]; - } else { - vc_start = iset->vc_start; - vc_end = iset->vc_end; - } - assert(vc_start >= 0 && vc_start < _vcs); - assert(vc_end >= 0 && vc_end < _vcs); - assert(vc_end >= vc_start); - - for(int out_vc = vc_start; out_vc <= vc_end; ++out_vc) { - assert((out_vc >= 0) && (out_vc < _vcs)); - - int vc_prio = iset->pri; - if(_vc_prioritize_empty && !dest_buf->IsEmptyFor(out_vc)) { - assert(vc_prio >= 0); - vc_prio += numeric_limits::min(); - } - - // FIXME: This check should probably be performed in Evaluate(), - // not Update(), as the latter can cause the outcome to depend on - // the order of evaluation! - if(dest_buf->IsAvailableFor(out_vc) && - !dest_buf->IsFullFor(out_vc) && - ((match_vc < 0) || - RoundRobinArbiter::Supersedes(out_vc, vc_prio, - match_vc, match_prio, - vc_offset, _vcs))) { - match_vc = out_vc; - match_prio = vc_prio; - } - } - } - } - assert(match_vc >= 0); - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Allocating VC " << match_vc - << " at output " << output - << " via piggyback VC allocation." << endl; - } - - cur_buf->SetState(vc, VC::active); - cur_buf->SetOutput(vc, output, match_vc); - dest_buf->TakeBuffer(match_vc, input*_vcs + vc); - - _vc_rr_offset[output*_classes+cl] = (match_vc + 1) % _vcs; - - } else { - - assert(cur_buf->GetOutputPort(vc) == output); - - match_vc = cur_buf->GetOutputVC(vc); - - } - assert((match_vc >= 0) && (match_vc < _vcs)); - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " Scheduling switch connection from input " << input - << "." << (vc % _input_speedup) - << " to output " << output - << "." << (expanded_output % _output_speedup) - << "." << endl; - } - - cur_buf->RemoveFlit(vc); - -#ifdef TRACK_FLOWS - --_stored_flits[f->cl][input]; - if(f->tail) --_active_packets[f->cl][input]; -#endif - - _bufferMonitor->read(input, f) ; - - f->hops++; - f->vc = match_vc; - - if(!_routing_delay && f->head) { - const FlitChannel * channel = _output_channels[output]; - const Router * router = channel->GetSink(); - if(router) { - if(_noq) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Updating lookahead routing information for flit " << f->id - << " (NOQ)." << endl; - } - int next_output_port = _noq_next_output_port[input][vc]; - assert(next_output_port >= 0); - _noq_next_output_port[input][vc] = -1; - int next_vc_start = _noq_next_vc_start[input][vc]; - assert(next_vc_start >= 0 && next_vc_start < _vcs); - _noq_next_vc_start[input][vc] = -1; - int next_vc_end = _noq_next_vc_end[input][vc]; - assert(next_vc_end >= 0 && next_vc_end < _vcs); - _noq_next_vc_end[input][vc] = -1; - f->la_route_set.Clear(); - f->la_route_set.AddRange(next_output_port, next_vc_start, next_vc_end); - } else { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Updating lookahead routing information for flit " << f->id - << "." << endl; - } - int in_channel = channel->GetSinkPort(); - _rf(router, f, in_channel, &f->la_route_set, false); - } - } else { - f->la_route_set.Clear(); - } - } - -#ifdef TRACK_FLOWS - ++_outstanding_credits[f->cl][output]; - _outstanding_classes[output][f->vc].push(f->cl); -#endif - - dest_buf->SendingFlit(f); - - _crossbar_flits.push_back(make_pair(-1, make_pair(f, make_pair(expanded_input, expanded_output)))); - - if(_out_queue_credits.count(input) == 0) { - _out_queue_credits.insert(make_pair(input, Credit::New())); - } - _out_queue_credits.find(input)->second->vc.insert(vc); - - if(cur_buf->Empty(vc)) { - if(f->tail) { - cur_buf->SetState(vc, VC::idle); - } - } else { - Flit * const nf = cur_buf->FrontFlit(vc); - assert(nf); - assert(nf->vc == vc); - if(f->tail) { - assert(nf->head); - if(_routing_delay) { - cur_buf->SetState(vc, VC::routing); - _route_vcs.push_back(make_pair(-1, item.second.first)); - } else { - if(nf->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Using precomputed lookahead routing information for VC " << vc - << " at input " << input - << " (front: " << nf->id - << ")." << endl; - } - cur_buf->SetRouteSet(vc, &nf->la_route_set); - cur_buf->SetState(vc, VC::vc_alloc); - if(_speculative) { - _sw_alloc_vcs.push_back(make_pair(-1, make_pair(item.second.first, - -1))); - } - if(_vc_allocator) { - _vc_alloc_vcs.push_back(make_pair(-1, make_pair(item.second.first, - -1))); - } - if(_noq) { - _UpdateNOQ(input, vc, nf); - } - } - } else { - if(_hold_switch_for_packet) { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Setting up switch hold for VC " << vc - << " at input " << input - << "." << (expanded_input % _input_speedup) - << " to output " << output - << "." << (expanded_output % _output_speedup) - << "." << endl; - } - _switch_hold_vc[expanded_input] = vc; - _switch_hold_in[expanded_input] = expanded_output; - _switch_hold_out[expanded_output] = expanded_input; - _sw_hold_vcs.push_back(make_pair(-1, make_pair(item.second.first, - -1))); - } else { - _sw_alloc_vcs.push_back(make_pair(-1, make_pair(item.second.first, - -1))); - } - } - } - } else { - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << " No output port allocated." << endl; - } - -#ifdef TRACK_STALLS - assert((expanded_output == -1) || // for stalls that are accounted for in VC allocation path - (expanded_output == STALL_BUFFER_BUSY) || - (expanded_output == STALL_BUFFER_CONFLICT) || - (expanded_output == STALL_BUFFER_FULL) || - (expanded_output == STALL_BUFFER_RESERVED) || - (expanded_output == STALL_CROSSBAR_CONFLICT)); - if(expanded_output == STALL_BUFFER_BUSY) { - ++_buffer_busy_stalls[f->cl]; - } else if(expanded_output == STALL_BUFFER_CONFLICT) { - ++_buffer_conflict_stalls[f->cl]; - } else if(expanded_output == STALL_BUFFER_FULL) { - ++_buffer_full_stalls[f->cl]; - } else if(expanded_output == STALL_BUFFER_RESERVED) { - ++_buffer_reserved_stalls[f->cl]; - } else if(expanded_output == STALL_CROSSBAR_CONFLICT) { - ++_crossbar_conflict_stalls[f->cl]; - } -#endif - - _sw_alloc_vcs.push_back(make_pair(-1, make_pair(item.second.first, -1))); - } - _sw_alloc_vcs.pop_front(); - } -} - - -//------------------------------------------------------------------------------ -// switch traversal -//------------------------------------------------------------------------------ - -void IQRouter::_SwitchEvaluate( ) -{ - for(deque > > >::iterator iter = _crossbar_flits.begin(); - iter != _crossbar_flits.end(); - ++iter) { - - int const time = iter->first; - if(time >= 0) { - break; - } - iter->first = GetSimTime() + _crossbar_delay - 1; - - Flit const * const f = iter->second.first; - assert(f); - - int const expanded_input = iter->second.second.first; - int const expanded_output = iter->second.second.second; - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Beginning crossbar traversal for flit " << f->id - << " from input " << (expanded_input / _input_speedup) - << "." << (expanded_input % _input_speedup) - << " to output " << (expanded_output / _output_speedup) - << "." << (expanded_output % _output_speedup) - << "." << endl; - } - } -} - -void IQRouter::_SwitchUpdate( ) -{ - while(!_crossbar_flits.empty()) { - - pair > > const & item = _crossbar_flits.front(); - - int const time = item.first; - if((time < 0) || (GetSimTime() < time)) { - break; - } - assert(GetSimTime() == time); - - Flit * const f = item.second.first; - assert(f); - - int const expanded_input = item.second.second.first; - int const input = expanded_input / _input_speedup; - assert((input >= 0) && (input < _inputs)); - int const expanded_output = item.second.second.second; - int const output = expanded_output / _output_speedup; - assert((output >= 0) && (output < _outputs)); - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Completed crossbar traversal for flit " << f->id - << " from input " << input - << "." << (expanded_input % _input_speedup) - << " to output " << output - << "." << (expanded_output % _output_speedup) - << "." << endl; - } - _switchMonitor->traversal(input, output, f) ; - - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Buffering flit " << f->id - << " at output " << output - << "." << endl; - } - _output_buffer[output].push(f); - //the output buffer size isn't precise due to flits in flight - //but there is a maximum bound based on output speed up and ST traversal - assert(_output_buffer[output].size()<=(size_t)_output_buffer_size+ _crossbar_delay* _output_speedup+( _output_speedup-1) ||_output_buffer_size==-1); - _crossbar_flits.pop_front(); - } -} - - -//------------------------------------------------------------------------------ -// output queuing -//------------------------------------------------------------------------------ - -void IQRouter::_OutputQueuing( ) -{ - for(map::const_iterator iter = _out_queue_credits.begin(); - iter != _out_queue_credits.end(); - ++iter) { - - int const input = iter->first; - assert((input >= 0) && (input < _inputs)); - - Credit * const c = iter->second; - assert(c); - assert(!c->vc.empty()); - - _credit_buffer[input].push(c); - } - _out_queue_credits.clear(); -} - -//------------------------------------------------------------------------------ -// write outputs -//------------------------------------------------------------------------------ - -void IQRouter::_SendFlits( ) -{ - for ( int output = 0; output < _outputs; ++output ) { - if ( !_output_buffer[output].empty( ) ) { - Flit * const f = _output_buffer[output].front( ); - assert(f); - _output_buffer[output].pop( ); - -#ifdef TRACK_FLOWS - ++_sent_flits[f->cl][output]; -#endif - - if(f->watch) - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Sending flit " << f->id - << " to channel at output " << output - << "." << endl; - if(gTrace) { - cout << "Outport " << output << endl << "Stop Mark" << endl; - } - _output_channels[output]->Send( f ); - } - } -} - -void IQRouter::_SendCredits( ) -{ - for ( int input = 0; input < _inputs; ++input ) { - if ( !_credit_buffer[input].empty( ) ) { - Credit * const c = _credit_buffer[input].front( ); - assert(c); - _credit_buffer[input].pop( ); - _input_credits[input]->Send( c ); - } - } -} - - -//------------------------------------------------------------------------------ -// misc. -//------------------------------------------------------------------------------ - -void IQRouter::Display( ostream & os ) const -{ - for ( int input = 0; input < _inputs; ++input ) { - _buf[input]->Display( os ); - } -} - -int IQRouter::GetUsedCredit(int o) const -{ - assert((o >= 0) && (o < _outputs)); - BufferState const * const dest_buf = _next_buf[o]; - return dest_buf->Occupancy(); -} - -int IQRouter::GetBufferOccupancy(int i) const { - assert(i >= 0 && i < _inputs); - return _buf[i]->GetOccupancy(); -} - -#ifdef TRACK_BUFFERS -int IQRouter::GetUsedCreditForClass(int output, int cl) const -{ - assert((output >= 0) && (output < _outputs)); - BufferState const * const dest_buf = _next_buf[output]; - return dest_buf->OccupancyForClass(cl); -} - -int IQRouter::GetBufferOccupancyForClass(int input, int cl) const -{ - assert((input >= 0) && (input < _inputs)); - return _buf[input]->GetOccupancyForClass(cl); -} -#endif - -vector IQRouter::UsedCredits() const -{ - vector result(_outputs*_vcs); - for(int o = 0; o < _outputs; ++o) { - for(int v = 0; v < _vcs; ++v) { - result[o*_vcs+v] = _next_buf[o]->OccupancyFor(v); - } - } - return result; -} - -vector IQRouter::FreeCredits() const -{ - vector result(_outputs*_vcs); - for(int o = 0; o < _outputs; ++o) { - for(int v = 0; v < _vcs; ++v) { - result[o*_vcs+v] = _next_buf[o]->AvailableFor(v); - } - } - return result; -} - -vector IQRouter::MaxCredits() const -{ - vector result(_outputs*_vcs); - for(int o = 0; o < _outputs; ++o) { - for(int v = 0; v < _vcs; ++v) { - result[o*_vcs+v] = _next_buf[o]->LimitFor(v); - } - } - return result; -} - -void IQRouter::_UpdateNOQ(int input, int vc, Flit const * f) { - assert(!_routing_delay); - assert(f); - assert(f->vc == vc); - assert(f->head); - set sl = f->la_route_set.GetSet(); - assert(sl.size() == 1); - int out_port = sl.begin()->output_port; - const FlitChannel * channel = _output_channels[out_port]; - const Router * router = channel->GetSink(); - if(router) { - int in_channel = channel->GetSinkPort(); - OutputSet nos; - _rf(router, f, in_channel, &nos, false); - sl = nos.GetSet(); - assert(sl.size() == 1); - OutputSet::sSetElement const & se = *sl.begin(); - int next_output_port = se.output_port; - assert(next_output_port >= 0); - assert(_noq_next_output_port[input][vc] < 0); - _noq_next_output_port[input][vc] = next_output_port; - int next_vc_count = (se.vc_end - se.vc_start + 1) / router->NumOutputs(); - int next_vc_start = se.vc_start + next_output_port * next_vc_count; - assert(next_vc_start >= 0 && next_vc_start < _vcs); - assert(_noq_next_vc_start[input][vc] < 0); - _noq_next_vc_start[input][vc] = next_vc_start; - int next_vc_end = se.vc_start + (next_output_port + 1) * next_vc_count - 1; - assert(next_vc_end >= 0 && next_vc_end < _vcs); - assert(_noq_next_vc_end[input][vc] < 0); - _noq_next_vc_end[input][vc] = next_vc_end; - assert(next_vc_start <= next_vc_end); - if(f->watch) { - *gWatchOut << GetSimTime() << " | " << FullName() << " | " - << "Computing lookahead routing information for flit " << f->id - << " (NOQ)." << endl; - } - } -} diff --git a/src/intersim2/.svn/pristine/f9/f9cf31dbae18e4e1930dc0632175d9c420d3c067.svn-base b/src/intersim2/.svn/pristine/f9/f9cf31dbae18e4e1930dc0632175d9c420d3c067.svn-base deleted file mode 100644 index d58d4a1..0000000 --- a/src/intersim2/.svn/pristine/f9/f9cf31dbae18e4e1930dc0632175d9c420d3c067.svn-base +++ /dev/null @@ -1,107 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/*flit.cpp - * - *flit struct is a flit, carries all the control signals that a flit needs - *Add additional signals as necessary. Flits has no concept of length - *it is a singluar object. - * - *When adding objects make sure to set a default value in this constructor - */ - -#include "booksim.hpp" -#include "flit.hpp" - -stack Flit::_all; -stack Flit::_free; - -ostream& operator<<( ostream& os, const Flit& f ) -{ - os << " Flit ID: " << f.id << " (" << &f << ")" - << " Packet ID: " << f.pid - << " Type: " << f.type - << " Head: " << f.head - << " Tail: " << f.tail << endl; - os << " Source: " << f.src << " Dest: " << f.dest << " Intm: "<Reset(); - _free.pop(); - } - return f; -} - -void Flit::Free() { - _free.push(this); -} - -void Flit::FreeAll() { - while(!_all.empty()) { - delete _all.top(); - _all.pop(); - } -} diff --git a/src/intersim2/.svn/pristine/f9/f9ef776d4727c7e2a1e057f5839da76e854ccae5.svn-base b/src/intersim2/.svn/pristine/f9/f9ef776d4727c7e2a1e057f5839da76e854ccae5.svn-base deleted file mode 100644 index 024104e..0000000 --- a/src/intersim2/.svn/pristine/f9/f9ef776d4727c7e2a1e057f5839da76e854ccae5.svn-base +++ /dev/null @@ -1,40 +0,0 @@ -// $Id$ - -// Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// Redistributions in binary form must reproduce the above copyright notice, -// this list of conditions and the following disclaimer in the documentation -// and/or other materials provided with the distribution. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -// POSSIBILITY OF SUCH DAMAGE. - -//simple 8X8 torus under injection mode - - -// Topology -topology = torus; -k = 8; -n = 2; -// Routing -routing_function = dim_order; -// Flow control -num_vcs = 2; -// Traffic -traffic = uniform; -injection_rate = 0.15; diff --git a/src/intersim2/.svn/pristine/fa/fad571d200d6232ee119a96b2ae1820f3d6903fa.svn-base b/src/intersim2/.svn/pristine/fa/fad571d200d6232ee119a96b2ae1820f3d6903fa.svn-base deleted file mode 100644 index 174d030..0000000 --- a/src/intersim2/.svn/pristine/fa/fad571d200d6232ee119a96b2ae1820f3d6903fa.svn-base +++ /dev/null @@ -1,676 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/*buffer_state.cpp - * - * This class is the buffere state of the next router down the channel - * tracks the credit and how much of the buffer is in use - */ - -#include -#include -#include -#include -#include - -#include "booksim.hpp" -#include "buffer_state.hpp" -#include "random_utils.hpp" -#include "globals.hpp" - -//#define DEBUG_FEEDBACK -//#define DEBUG_SIMPLEFEEDBACK - -BufferState::BufferPolicy::BufferPolicy(Configuration const & config, BufferState * parent, const string & name) -: Module(parent, name), _buffer_state(parent) -{ -} - -void BufferState::BufferPolicy::TakeBuffer(int vc) { -} - -void BufferState::BufferPolicy::SendingFlit(Flit const * const f) { -} - -void BufferState::BufferPolicy::FreeSlotFor(int vc) { -} - -BufferState::BufferPolicy * BufferState::BufferPolicy::New(Configuration const & config, BufferState * parent, const string & name) -{ - BufferPolicy * sp = NULL; - string buffer_policy = config.GetStr("buffer_policy"); - if(buffer_policy == "private") { - sp = new PrivateBufferPolicy(config, parent, name); - } else if(buffer_policy == "shared") { - sp = new SharedBufferPolicy(config, parent, name); - } else if(buffer_policy == "limited") { - sp = new LimitedSharedBufferPolicy(config, parent, name); - } else if(buffer_policy == "dynamic") { - sp = new DynamicLimitedSharedBufferPolicy(config, parent, name); - } else if(buffer_policy == "shifting") { - sp = new ShiftingDynamicLimitedSharedBufferPolicy(config, parent, name); - } else if(buffer_policy == "feedback") { - sp = new FeedbackSharedBufferPolicy(config, parent, name); - } else if(buffer_policy == "simplefeedback") { - sp = new SimpleFeedbackSharedBufferPolicy(config, parent, name); - } else { - cout << "Unknown buffer policy: " << buffer_policy << endl; - } - return sp; -} - -BufferState::PrivateBufferPolicy::PrivateBufferPolicy(Configuration const & config, BufferState * parent, const string & name) - : BufferPolicy(config, parent, name) -{ - int const vcs = config.GetInt( "num_vcs" ); - int const buf_size = config.GetInt("buf_size"); - if(buf_size <= 0) { - _vc_buf_size = config.GetInt("vc_buf_size"); - } else { - _vc_buf_size = buf_size / vcs; - } - assert(_vc_buf_size > 0); -} - -void BufferState::PrivateBufferPolicy::SendingFlit(Flit const * const f) -{ - int const vc = f->vc; - if(_buffer_state->OccupancyFor(vc) > _vc_buf_size) { - ostringstream err; - err << "Buffer overflow for VC " << vc; - Error(err.str()); - } -} - -bool BufferState::PrivateBufferPolicy::IsFullFor(int vc) const -{ - return (_buffer_state->OccupancyFor(vc) >= _vc_buf_size); -} - -int BufferState::PrivateBufferPolicy::AvailableFor(int vc) const -{ - return _vc_buf_size - _buffer_state->OccupancyFor(vc); -} - -int BufferState::PrivateBufferPolicy::LimitFor(int vc) const -{ - return _vc_buf_size; -} - -BufferState::SharedBufferPolicy::SharedBufferPolicy(Configuration const & config, BufferState * parent, const string & name) - : BufferPolicy(config, parent, name), _shared_buf_occupancy(0) -{ - int const vcs = config.GetInt( "num_vcs" ); - int num_private_bufs = config.GetInt("private_bufs"); - if(num_private_bufs < 0) { - num_private_bufs = vcs; - } else if(num_private_bufs == 0) { - num_private_bufs = 1; - } - - _private_buf_occupancy.resize(num_private_bufs, 0); - - _buf_size = config.GetInt("buf_size"); - if(_buf_size < 0) { - _buf_size = vcs * config.GetInt("vc_buf_size"); - } - - _private_buf_size = config.GetIntArray("private_buf_size"); - if(_private_buf_size.empty()) { - int const bs = config.GetInt("private_buf_size"); - if(bs < 0) { - _private_buf_size.push_back(_buf_size / num_private_bufs); - } else { - _private_buf_size.push_back(bs); - } - } - _private_buf_size.resize(num_private_bufs, _private_buf_size.back()); - - vector start_vc = config.GetIntArray("private_buf_start_vc"); - if(start_vc.empty()) { - int const sv = config.GetInt("private_buf_start_vc"); - if(sv < 0) { - start_vc.resize(num_private_bufs); - for(int i = 0; i < num_private_bufs; ++i) { - start_vc[i] = i * vcs / num_private_bufs; - } - } else { - start_vc.push_back(sv); - } - } - - vector end_vc = config.GetIntArray("private_buf_end_vc"); - if(end_vc.empty()) { - int const ev = config.GetInt("private_buf_end_vc"); - if(ev < 0) { - end_vc.resize(num_private_bufs); - for(int i = 0; i < num_private_bufs; ++i) { - end_vc[i] = (i + 1) * vcs / num_private_bufs - 1; - } - } else { - end_vc.push_back(ev); - } - } - - _private_buf_vc_map.resize(vcs, -1); - _shared_buf_size = _buf_size; - for(int i = 0; i < num_private_bufs; ++i) { - _shared_buf_size -= _private_buf_size[i]; - assert(start_vc[i] <= end_vc[i]); - for(int v = start_vc[i]; v <= end_vc[i]; ++v) { - assert(_private_buf_vc_map[v] < 0); - _private_buf_vc_map[v] = i; - } - } - assert(_shared_buf_size >= 0); - - _reserved_slots.resize(vcs, 0); -} - -void BufferState::SharedBufferPolicy::ProcessFreeSlot(int vc) -{ - int i = _private_buf_vc_map[vc]; - --_private_buf_occupancy[i]; - if(_private_buf_occupancy[i] < 0) { - ostringstream err; - err << "Private buffer occupancy fell below zero for buffer " << i; - Error(err.str()); - } else if(_private_buf_occupancy[i] >= _private_buf_size[i]) { - --_shared_buf_occupancy; - if(_shared_buf_occupancy < 0) { - Error("Shared buffer occupancy fell below zero."); - } - } -} - -void BufferState::SharedBufferPolicy::SendingFlit(Flit const * const f) -{ - int const vc = f->vc; - if(_reserved_slots[vc] > 0) { - --_reserved_slots[vc]; - } else { - int i = _private_buf_vc_map[vc]; - ++_private_buf_occupancy[i]; - if(_private_buf_occupancy[i] > _private_buf_size[i]) { - ++_shared_buf_occupancy; - if(_shared_buf_occupancy > _shared_buf_size) { - Error("Shared buffer overflow."); - } - } - } - if(f->tail) { - while(_reserved_slots[vc]) { - --_reserved_slots[vc]; - ProcessFreeSlot(vc); - } - } -} - -void BufferState::SharedBufferPolicy::FreeSlotFor(int vc) -{ - if(!_buffer_state->IsAvailableFor(vc) && _buffer_state->IsEmptyFor(vc)) { - ++_reserved_slots[vc]; - } else { - ProcessFreeSlot(vc); - } -} - -bool BufferState::SharedBufferPolicy::IsFullFor(int vc) const -{ - int i = _private_buf_vc_map[vc]; - return ((_reserved_slots[vc] == 0) && - (_private_buf_occupancy[i] >= _private_buf_size[i]) && - (_shared_buf_occupancy >= _shared_buf_size)); -} - -int BufferState::SharedBufferPolicy::AvailableFor(int vc) const -{ - int i = _private_buf_vc_map[vc]; - return (_reserved_slots[vc] + - max(_private_buf_size[i] - _private_buf_occupancy[i], 0) + - (_shared_buf_size - _shared_buf_occupancy)); -} - -int BufferState::SharedBufferPolicy::LimitFor(int vc) const -{ - int i = _private_buf_vc_map[vc]; - return (_private_buf_size[i] + _shared_buf_size); -} - -BufferState::LimitedSharedBufferPolicy::LimitedSharedBufferPolicy(Configuration const & config, BufferState * parent, const string & name) - : SharedBufferPolicy(config, parent, name), _active_vcs(0) -{ - _vcs = config.GetInt("num_vcs"); - _max_held_slots = config.GetInt("max_held_slots"); - if(_max_held_slots < 0) { - _max_held_slots = _buf_size; - } -} - -void BufferState::LimitedSharedBufferPolicy::TakeBuffer(int vc) -{ - ++_active_vcs; - if(_active_vcs > _vcs) { - Error("Number of active VCs is too large."); - } -} - -void BufferState::LimitedSharedBufferPolicy::SendingFlit(Flit const * const f) -{ - SharedBufferPolicy::SendingFlit(f); - if(f->tail) { - --_active_vcs; - if(_active_vcs < 0) { - Error("Number of active VCs fell below zero."); - } - } -} - -bool BufferState::LimitedSharedBufferPolicy::IsFullFor(int vc) const -{ - return (SharedBufferPolicy::IsFullFor(vc) || - (_buffer_state->OccupancyFor(vc) >= _max_held_slots)); -} - -int BufferState::LimitedSharedBufferPolicy::AvailableFor(int vc) const -{ - return min(SharedBufferPolicy::AvailableFor(vc), - _max_held_slots - _buffer_state->OccupancyFor(vc)); -} - -int BufferState::LimitedSharedBufferPolicy::LimitFor(int vc) const -{ - return min(SharedBufferPolicy::LimitFor(vc), _max_held_slots); -} - -BufferState::DynamicLimitedSharedBufferPolicy::DynamicLimitedSharedBufferPolicy(Configuration const & config, BufferState * parent, const string & name) - : LimitedSharedBufferPolicy(config, parent, name) -{ - _max_held_slots = _buf_size; -} - -void BufferState::DynamicLimitedSharedBufferPolicy::TakeBuffer(int vc) -{ - LimitedSharedBufferPolicy::TakeBuffer(vc); - assert(_active_vcs > 0); - _max_held_slots = _buf_size / _active_vcs; - assert(_max_held_slots > 0); -} - -void BufferState::DynamicLimitedSharedBufferPolicy::SendingFlit(Flit const * const f) -{ - LimitedSharedBufferPolicy::SendingFlit(f); - if(f->tail && _active_vcs) { - _max_held_slots = _buf_size / _active_vcs; - } - assert(_max_held_slots > 0); -} - -BufferState::ShiftingDynamicLimitedSharedBufferPolicy::ShiftingDynamicLimitedSharedBufferPolicy(Configuration const & config, BufferState * parent, const string & name) - : DynamicLimitedSharedBufferPolicy(config, parent, name) -{ - -} - -void BufferState::ShiftingDynamicLimitedSharedBufferPolicy::TakeBuffer(int vc) -{ - LimitedSharedBufferPolicy::TakeBuffer(vc); - assert(_active_vcs); - int i = _active_vcs - 1; - _max_held_slots = _buf_size; - while(i) { - _max_held_slots >>= 1; - i >>= 1; - } - assert(_max_held_slots > 0); -} - -void BufferState::ShiftingDynamicLimitedSharedBufferPolicy::SendingFlit(Flit const * const f) -{ - LimitedSharedBufferPolicy::SendingFlit(f); - if(f->tail && _active_vcs) { - int i = _active_vcs - 1; - _max_held_slots = _buf_size; - while(i) { - _max_held_slots >>= 1; - i >>= 1; - } - } - assert(_max_held_slots > 0); -} - -BufferState::FeedbackSharedBufferPolicy::FeedbackSharedBufferPolicy(Configuration const & config, BufferState * parent, const string & name) - : SharedBufferPolicy(config, parent, name) -{ - _aging_scale = config.GetInt("feedback_aging_scale"); - _offset = config.GetInt("feedback_offset"); - _vcs = config.GetInt("num_vcs"); - - _occupancy_limit.resize(_vcs, _buf_size); - _round_trip_time.resize(_vcs, -1); - _flit_sent_time.resize(_vcs); - _total_mapped_size = _buf_size * _vcs; - _min_latency = -1; -} - -void BufferState::FeedbackSharedBufferPolicy::SetMinLatency(int min_latency) -{ -#ifdef DEBUG_FEEDBACK - cerr << FullName() << ": Setting minimum latency to " - << min_latency << "." << endl; -#endif - _min_latency = min_latency; -} - -void BufferState::FeedbackSharedBufferPolicy::SendingFlit(Flit const * const f) -{ - SharedBufferPolicy::SendingFlit(f); - _flit_sent_time[f->vc].push(GetSimTime()); -} - -int BufferState::FeedbackSharedBufferPolicy::_ComputeRTT(int vc, int last_rtt) const -{ - // compute moving average of round-trip time - int rtt = _round_trip_time[vc]; - if(rtt < 0) { - return last_rtt; - } - return ((rtt << _aging_scale) + last_rtt - rtt) >> _aging_scale; -} - -int BufferState::FeedbackSharedBufferPolicy::_ComputeLimit(int rtt) const -{ - // for every cycle that the measured average round trip time exceeded the - // observed minimum round trip time, reduce buffer occupancy limit by one - assert(_min_latency >= 0); - return max((_min_latency << 1) - rtt + _offset, 1); -} - -int BufferState::FeedbackSharedBufferPolicy::_ComputeMaxSlots(int vc) const -{ - int max_slots = _occupancy_limit[vc]; - if(!_flit_sent_time[vc].empty()) { - int min_rtt = GetSimTime() - _flit_sent_time[vc].front(); - int rtt = _ComputeRTT(vc, min_rtt); - int limit = _ComputeLimit(rtt); - max_slots = min(max_slots, limit); - } - return max_slots; -} - -void BufferState::FeedbackSharedBufferPolicy::FreeSlotFor(int vc) -{ - SharedBufferPolicy::FreeSlotFor(vc); - assert(!_flit_sent_time[vc].empty()); - int const last_rtt = GetSimTime() - _flit_sent_time[vc].front(); -#ifdef DEBUG_FEEDBACK - cerr << FullName() << ": Probe for VC " - << vc << " came back after " - << last_rtt << " cycles." - << endl; -#endif - _flit_sent_time[vc].pop(); - - int rtt = _ComputeRTT(vc, last_rtt); -#ifdef DEBUG_FEEDBACK - int old_rtt = _round_trip_time[vc]; - if(rtt != old_rtt) { - cerr << FullName() << ": Updating RTT estimate for VC " - << vc << " from " - << old_rtt << " to " - << rtt << " cycles." - << endl; - } -#endif - _round_trip_time[vc] = rtt; - - int limit = _ComputeLimit(rtt); -#ifdef DEBUG_FEEDBACK - int old_limit = _occupancy_limit[vc]; - int old_mapped_size = _total_mapped_size; -#endif - _total_mapped_size += (limit - _occupancy_limit[vc]); - _occupancy_limit[vc] = limit; -#ifdef DEBUG_FEEDBACK - if(limit != old_limit) { - cerr << FullName() << ": Occupancy limit for VC " - << vc << " changed from " - << old_limit << " to " - << limit << " slots." - << endl; - cerr << FullName() << ": Total mapped buffer space changed from " - << old_mapped_size << " to " - << _total_mapped_size << " slots." - << endl; - } -#endif -} - -bool BufferState::FeedbackSharedBufferPolicy::IsFullFor(int vc) const -{ - if(SharedBufferPolicy::IsFullFor(vc)) { - return true; - } - return (_buffer_state->OccupancyFor(vc) >= _ComputeMaxSlots(vc)); -} - -int BufferState::FeedbackSharedBufferPolicy::AvailableFor(int vc) const -{ - return min(SharedBufferPolicy::AvailableFor(vc), - _ComputeMaxSlots(vc) - _buffer_state->OccupancyFor(vc)); -} - -int BufferState::FeedbackSharedBufferPolicy::LimitFor(int vc) const -{ - return min(SharedBufferPolicy::LimitFor(vc), _ComputeMaxSlots(vc)); -} - -BufferState::SimpleFeedbackSharedBufferPolicy::SimpleFeedbackSharedBufferPolicy(Configuration const & config, BufferState * parent, const string & name) - : FeedbackSharedBufferPolicy(config, parent, name) -{ - _pending_credits.resize(_vcs, 0); -} - -void BufferState::SimpleFeedbackSharedBufferPolicy::SendingFlit(Flit const * const f) -{ - int const & vc = f->vc; - if(_flit_sent_time[vc].empty()) { - assert(_buffer_state->OccupancyFor(vc) > 0); - _pending_credits[vc] = _buffer_state->OccupancyFor(vc) - 1; -#ifdef DEBUG_SIMPLEFEEDBACK - cerr << FullName() << ": Sending probe flit for VC " - << vc << "; " - << _pending_credits[vc] << " non-probe flits in flight." - << endl; -#endif - FeedbackSharedBufferPolicy::SendingFlit(f); - return; - } - SharedBufferPolicy::SendingFlit(f); -} - -void BufferState::SimpleFeedbackSharedBufferPolicy::FreeSlotFor(int vc) -{ - if(!_flit_sent_time[vc].empty() && _pending_credits[vc] == 0) { -#ifdef DEBUG_SIMPLEFEEDBACK - cerr << FullName() << ": Probe credit for VC " - << vc << " came back." << endl; -#endif - FeedbackSharedBufferPolicy::FreeSlotFor(vc); - return; - } - if(_pending_credits[vc] > 0) { - assert(!_flit_sent_time[vc].empty()); - --_pending_credits[vc]; -#ifdef DEBUG_SIMPLEFEEDBACK - cerr << FullName() << ": Ignoring non-probe credit for VC " - << vc << "; " - << _pending_credits[vc] << " remaining." - << endl; -#endif - } - SharedBufferPolicy::FreeSlotFor(vc); -} - -BufferState::BufferState( const Configuration& config, Module *parent, const string& name ) : - Module( parent, name ), _occupancy(0) -{ - _vcs = config.GetInt( "num_vcs" ); - _size = config.GetInt("buf_size"); - if(_size < 0) { - _size = _vcs * config.GetInt("vc_buf_size"); - } - - _buffer_policy = BufferPolicy::New(config, this, "policy"); - - _wait_for_tail_credit = config.GetInt( "wait_for_tail_credit" ); - - _vc_occupancy.resize(_vcs, 0); - - _in_use_by.resize(_vcs, -1); - _tail_sent.resize(_vcs, false); - - _last_id.resize(_vcs, -1); - _last_pid.resize(_vcs, -1); - -#ifdef TRACK_BUFFERS - _classes = config.GetInt("classes"); - _outstanding_classes.resize(_vcs); - _class_occupancy.resize(_classes, 0); -#endif -} - -BufferState::~BufferState() -{ - delete _buffer_policy; -} - -void BufferState::ProcessCredit( Credit const * const c ) -{ - assert( c ); - - set::iterator iter = c->vc.begin(); - while(iter != c->vc.end()) { - - int const vc = *iter; - - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - - if ( ( _wait_for_tail_credit ) && - ( _in_use_by[vc] < 0 ) ) { - ostringstream err; - err << "Received credit for idle VC " << vc; - Error( err.str() ); - } - --_occupancy; - if(_occupancy < 0) { - Error("Buffer occupancy fell below zero."); - } - --_vc_occupancy[vc]; - if(_vc_occupancy[vc] < 0) { - ostringstream err; - err << "Buffer occupancy fell below zero for VC " << vc; - Error(err.str()); - } - if(_wait_for_tail_credit && !_vc_occupancy[vc] && _tail_sent[vc]) { - assert(_in_use_by[vc] >= 0); - _in_use_by[vc] = -1; - } - -#ifdef TRACK_BUFFERS - assert(!_outstanding_classes[vc].empty()); - int cl = _outstanding_classes[vc].front(); - _outstanding_classes[vc].pop(); - assert((cl >= 0) && (cl < _classes)); - assert(_class_occupancy[cl] > 0); - --_class_occupancy[cl]; -#endif - - _buffer_policy->FreeSlotFor(vc); - - ++iter; - } -} - - -void BufferState::SendingFlit( Flit const * const f ) -{ - int const vc = f->vc; - - assert( f && ( vc >= 0 ) && ( vc < _vcs ) ); - - ++_occupancy; - if(_occupancy > _size) { - Error("Buffer overflow."); - } - - ++_vc_occupancy[vc]; - - _buffer_policy->SendingFlit(f); - -#ifdef TRACK_BUFFERS - _outstanding_classes[vc].push(f->cl); - ++_class_occupancy[f->cl]; -#endif - - if ( f->tail ) { - _tail_sent[vc] = true; - - if ( !_wait_for_tail_credit ) { - assert(_in_use_by[vc] >= 0); - _in_use_by[vc] = -1; - } - } - _last_id[vc] = f->id; - _last_pid[vc] = f->pid; -} - -void BufferState::TakeBuffer( int vc, int tag ) -{ - assert( ( vc >= 0 ) && ( vc < _vcs ) ); - - if ( _in_use_by[vc] >= 0 ) { - ostringstream err; - err << "Buffer taken while in use for VC " << vc; - Error( err.str() ); - } - _in_use_by[vc] = tag; - _tail_sent[vc] = false; - _buffer_policy->TakeBuffer(vc); -} - -void BufferState::Display( ostream & os ) const -{ - os << FullName() << " :" << endl; - os << " occupied = " << _occupancy << endl; - for ( int v = 0; v < _vcs; ++v ) { - os << " VC " << v << ": "; - os << "in_use_by = " << _in_use_by[v] - << ", tail_sent = " << _tail_sent[v] - << ", occupied = " << _vc_occupancy[v] << endl; - } -} diff --git a/src/intersim2/.svn/pristine/fc/fc7b3404406776df7852a99657a25fb9feadbc84.svn-base b/src/intersim2/.svn/pristine/fc/fc7b3404406776df7852a99657a25fb9feadbc84.svn-base deleted file mode 100644 index 2388b6c..0000000 --- a/src/intersim2/.svn/pristine/fc/fc7b3404406776df7852a99657a25fb9feadbc84.svn-base +++ /dev/null @@ -1,55 +0,0 @@ -// $Id$ - -/* - Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR - ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#ifndef _SELALLOC_HPP_ -#define _SELALLOC_HPP_ - -#include - -#include "allocator.hpp" - -class SelAlloc : public SparseAllocator { - int _iter; - - vector _aptrs; - vector _gptrs; - - vector _outmask; - -public: - SelAlloc( Module *parent, const string& name, - int inputs, int outputs, int iters ); - - void Allocate( ); - - void MaskOutput( int out, int mask = 1 ); - - virtual void PrintRequests( ostream * os = NULL ) const; - -}; - -#endif diff --git a/src/intersim2/.svn/wc.db b/src/intersim2/.svn/wc.db deleted file mode 100644 index 4c38197..0000000 Binary files a/src/intersim2/.svn/wc.db and /dev/null differ -- cgit v1.3 From 0b55a95f4389a45fec6ff94e35ded72b42433a29 Mon Sep 17 00:00:00 2001 From: Myrice Date: Wed, 8 Apr 2015 20:39:41 -0700 Subject: Modified CHANGES for intersim2 svn removal Signed-off-by: Myrice --- CHANGES | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGES b/CHANGES index 96b66f8..4a6f6e2 100644 --- a/CHANGES +++ b/CHANGES @@ -6,6 +6,7 @@ Version 3.2.3+edits (development branch) versus 3.2.3 - Added support for named barriers. - Added support for bar.arrive and bar.red instructions. - Initial support for CUDA 5.0,5.5 and 6.0 to get template running. +- Removed intersim2 svn repository files - Bug fixes: - Fixed bug #81, fix ordering of pushing branch entries to the stack -- cgit v1.3 From 93b270cd01a1f0cfa6d67e4dc16df3214f9ffc5a Mon Sep 17 00:00:00 2001 From: Myrice Date: Wed, 8 Apr 2015 20:42:07 -0700 Subject: Fixed bug #88. Initial ejection buffer and boundary buffer with the interconnection node number Signed-off-by: Myrice --- CHANGES | 1 + src/intersim2/interconnect_interface.cpp | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/CHANGES b/CHANGES index 4a6f6e2..216490e 100644 --- a/CHANGES +++ b/CHANGES @@ -11,6 +11,7 @@ Version 3.2.3+edits (development branch) versus 3.2.3 - Bug fixes: - Fixed bug #81, fix ordering of pushing branch entries to the stack - Fixed a bug where for each icache miss we also count a hit + - Fixed bug #88, Ejection buffer and Boundary buffer in Intersim2 initialization with a wrong node number Version 3.2.3 versus 3.2.2 - Bug fixes: diff --git a/src/intersim2/interconnect_interface.cpp b/src/intersim2/interconnect_interface.cpp index 18a7083..4386821 100644 --- a/src/intersim2/interconnect_interface.cpp +++ b/src/intersim2/interconnect_interface.cpp @@ -364,7 +364,7 @@ Flit* InterconnectInterface::GetEjectedFlit(int subnet, int node) void InterconnectInterface::_CreateBuffer() { - unsigned nodes = _n_shader + _n_mem; + unsigned nodes = _net[0]->NumNodes(); _boundary_buffer.resize(_subnets); _ejection_buffer.resize(_subnets); -- cgit v1.3 From aafc8c5817a5c6bc1eba432c0ef84491aef5d2f8 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 5 Jun 2015 14:19:06 -0700 Subject: Adding in changes to put generated code files in the build directory instead of the source directory - since this causes issues for parallel buildwq --- cuobjdump_to_ptxplus/Makefile | 40 +++++++++++++++++++++++++--------------- libcuda/Makefile | 15 +++++++++------ src/intersim2/Makefile | 12 ++++++------ 3 files changed, 40 insertions(+), 27 deletions(-) diff --git a/cuobjdump_to_ptxplus/Makefile b/cuobjdump_to_ptxplus/Makefile index 0358970..242a066 100644 --- a/cuobjdump_to_ptxplus/Makefile +++ b/cuobjdump_to_ptxplus/Makefile @@ -27,41 +27,52 @@ $(OUTPUT_DIR)/cuobjdump_to_ptxplus: $(OUTPUT_DIR)/cuobjdumpInst.o $(OUTPUT_DIR)/ ${LD} ${LDFLAGS} -o $@ $(OUTPUT_DIR)/cuobjdumpInst.o $(OUTPUT_DIR)/cuobjdumpInstList.o $(OUTPUT_DIR)/cuobjdump_to_ptxplus.o $(PTX_PARSER_OBJECTS) $(SASS_PARSER_OBJECTS) $(ELF_PARSER_OBJECTS) $(HEADER_PARSER_OBJECTS) -lex.ptx_.c : ../src/cuda-sim/ptx.l - ${LEX} ${LEXFLAGS} ../src/cuda-sim/ptx.l +$(OUTPUT_DIR)/lex.ptx_.c : ../src/cuda-sim/ptx.l + ${LEX} ${LEXFLAGS} -o$(OUTPUT_DIR)/lex.ptx_.c ../src/cuda-sim/ptx.l -ptx.tab.c : ../src/cuda-sim/ptx.y - ${YACC} ${YFLAGS} --name-prefix=ptx_ -v ../src/cuda-sim/ptx.y +$(OUTPUT_DIR)/ptx.tab.c : ../src/cuda-sim/ptx.y + ${YACC} ${YFLAGS} --name-prefix=ptx_ -v ../src/cuda-sim/ptx.y --file-prefix=$(OUTPUT_DIR)/ptx -ptx.tab.h : ptx.tab.c +$(OUTPUT_DIR)/ptx.tab.h :$(OUTPUT_DIR)/ptx.tab.c -$(OUTPUT_DIR)/lex.ptx_.o : lex.ptx_.c ptx.tab.h - ${CXX} ${CXXFLAGS} -c lex.ptx_.c -o $@ +$(OUTPUT_DIR)/lex.ptx_.o : $(OUTPUT_DIR)/lex.ptx_.c $(OUTPUT_DIR)/ptx.tab.h + ${CXX} ${CXXFLAGS} -c $(OUTPUT_DIR)/lex.ptx_.c -o $@ -$(OUTPUT_DIR)/ptx.tab.o : ptx.tab.c ptx_parser.h - ${CXX} ${CXXFLAGS} -c ptx.tab.c -o $@ +$(OUTPUT_DIR)/ptx.tab.o : $(OUTPUT_DIR)/ptx.tab.c ptx_parser.h + ${CXX} ${CXXFLAGS} -c $(OUTPUT_DIR)/ptx.tab.c -o $@ - -%_lexer.cc: %.l %_parser.hh +$(OUTPUT_DIR)/%_lexer.cc: %.l $(OUTPUT_DIR)/%_parser.hh $(LEX) $(LEXFLAGS) -P $*_ -o$@ $< -%_parser.cc: %.y - $(YACC) $(YFLAGS) -p $*_ -o$@ $< +$(OUTPUT_DIR)/%_parser.cc: %.y + $(YACC) $(YFLAGS) -p $*_ -o$@ $< --file-prefix=$(OUTPUT_DIR)/$@ # The ':' is needed otherwise make gets confused and doesn't understand that it knows how to make %Parser.hpp from %Parser.cpp. # : in bash is equivalent to NOP (no operation) -%_parser.hh: %_parser.cc +$(OUTPUT_DIR)/%_parser.hh: $(OUTPUT_DIR)/%_parser.cc + : + +$(OUTPUT_DIR)/%_parser.hh: %_parser.cc : $(OUTPUT_DIR)/%.o: %.cc $(CXX) ${CXXFLAGS} -c -o $@ $< +$(OUTPUT_DIR)/%.o: $(OUTPUT_DIR)/%.cc + $(CXX) ${CXXFLAGS} -c -o $@ $< + $(OUTPUT_DIR)/%.o: %.cpp %.h $(CXX) ${CXXFLAGS} -c -o $@ $< +$(OUTPUT_DIR)/%.o: $(OUTPUT_DIR)/%.cpp $(OUTPUT_DIR)/%.h + $(CXX) ${CXXFLAGS} -c -o $@ $< + $(OUTPUT_DIR)/%.o: %.c %.h ${CXX} ${CCFLAGS} -c -o $@ $< +$(OUTPUT_DIR)/%.o: $(OUTPUT_DIR)/%.c $(OUTPUT_DIR)/%.h + ${CXX} ${CCFLAGS} -c -o $@ $< + SRCS = $(shell ls *.cc) $(OUTPUT_DIR)/Makefile.makedepend: depend @@ -79,4 +90,3 @@ clean: rm -f $(OUTPUT_DIR)/Makefile.makedepend $(OUTPUT_DIR)/Makefile.makedepend.bak include $(OUTPUT_DIR)/Makefile.makedepend - diff --git a/libcuda/Makefile b/libcuda/Makefile index b1a6552..13932e2 100644 --- a/libcuda/Makefile +++ b/libcuda/Makefile @@ -108,20 +108,23 @@ lib$(PROG).a: $(OBJS) ar rcs $(OUTPUT_DIR)/lib$(PROG).a $(OBJS) $(OUTPUT_DIR)/%.o: %.cc - $(CPP) $(CXXFLAGS) -I./ -I$(CUDA_INSTALL_PATH)/include -c $< -o $@ + $(CPP) $(CXXFLAGS) -I./ -I$(OUTPUT_DIR) -I$(CUDA_INSTALL_PATH)/include -c $< -o $@ $(OUTPUT_DIR)/%.o: %.c - $(CC) $(CCFLAGS) -I./ -I$(CUDA_INSTALL_PATH)/include -c $< -o $@ + $(CC) $(CCFLAGS) -I./ -I$(OUTPUT_DIR) -I$(CUDA_INSTALL_PATH)/include -c $< -o $@ -cuobjdump_parser.c: cuobjdump.y - $(YACC) $(YFLAGS) -p cuobjdump_ -o$@ $< +$(OUTPUT_DIR)/%.o: $(OUTPUT_DIR)/%.c + $(CC) $(CCFLAGS) -I./ -I$(OUTPUT_DIR) -I$(CUDA_INSTALL_PATH)/include -c $< -o $@ -cuobjdump_lexer.c: cuobjdump.l cuobjdump_parser.h +$(OUTPUT_DIR)/cuobjdump_parser.c: cuobjdump.y + $(YACC) $(YFLAGS) -p cuobjdump_ -o$@ $< --file-prefix=$(OUTPUT_DIR)/cuobjdump + +$(OUTPUT_DIR)/cuobjdump_lexer.c: cuobjdump.l $(OUTPUT_DIR)/cuobjdump_parser.h $(LEX) $(LEXFLAGS) -P cuobjdump_ -o$@ $< # The next rule means just get parser.c and you will get parser.h with it # in other words, get parser.c and do nothing to get parser.h -%_parser.h: %_parser.c +$(OUTPUT_DIR)/%_parser.h: $(OUTPUT_DIR)/%_parser.c : $(OUTPUT_DIR)/Makefile.makedepend: depend diff --git a/src/intersim2/Makefile b/src/intersim2/Makefile index fd9fba8..ef948d6 100644 --- a/src/intersim2/Makefile +++ b/src/intersim2/Makefile @@ -126,10 +126,10 @@ endif # rules to compile simulator -${LEX_OBJS}: lex.yy.c y.tab.h +${LEX_OBJS}: $(OBJDIR)/lex.yy.c $(OBJDIR)/y.tab.h $(CC) $(CPPFLAGS) -c $< -o $@ -${YACC_OBJS}: y.tab.c y.tab.h +${YACC_OBJS}: $(OBJDIR)/y.tab.c $(OBJDIR)/y.tab.h $(CC) $(CPPFLAGS) -c $< -o $@ ${OBJDIR}/%.o: %.cpp @@ -168,8 +168,8 @@ clean: rm -f y.tab.c y.tab.h lex.yy.c rm -f moc_bgui.cpp -y.tab.c y.tab.h: config.y - $(YACC) -d $< +$(OBJDIR)/y.tab.c $(OBJDIR)/y.tab.h: config.y + $(YACC) -d $< --file-prefix=$(OBJDIR)/y -lex.yy.c: config.l - $(LEX) $< +$(OBJDIR)/lex.yy.c: config.l + $(LEX) -o$@ $< -- cgit v1.3 From 6a3f14861e13c2625108fdf5d35624ecc46439a9 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 5 Jun 2015 14:22:32 -0700 Subject: Adding a description of the makefile changes --- CHANGES | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGES b/CHANGES index 216490e..512993b 100644 --- a/CHANGES +++ b/CHANGES @@ -7,6 +7,7 @@ Version 3.2.3+edits (development branch) versus 3.2.3 - Added support for bar.arrive and bar.red instructions. - Initial support for CUDA 5.0,5.5 and 6.0 to get template running. - Removed intersim2 svn repository files +- Changed the makefile for cuobjdump_toptxplus,libcuda,intersim2 so that it outputs temporary files into the build directory - Bug fixes: - Fixed bug #81, fix ordering of pushing branch entries to the stack -- cgit v1.3 From 07b1e93f19bef20a9e35fcfc48b091fa36d56d1b Mon Sep 17 00:00:00 2001 From: Tayler Hetherington Date: Fri, 5 Jun 2015 14:49:14 -0700 Subject: Fixing bug with max cycle/instruction/cta + bug with C++ name de-mangling with spaces (e.g., using templates) --- src/cuda-sim/ptx_ir.cc | 6 ++++-- src/gpgpu-sim/gpu-sim.cc | 41 +++++++++++++++++++++++++++++++------ src/gpgpu-sim/gpu-sim.h | 16 +++++++++++---- src/gpgpu-sim/shader.cc | 6 +++--- src/gpgpusim_entrypoint.cc | 14 +++++++++---- src/stream_manager.cc | 51 +++++++++++++++++++++++++++++++++++----------- src/stream_manager.h | 1 + 7 files changed, 104 insertions(+), 31 deletions(-) diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 6943b48..fa37cc4 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1256,10 +1256,12 @@ unsigned function_info::print_insn( unsigned pc, FILE * fp ) const unsigned index = pc - m_start_PC; char command[1024]; char buffer[1024]; - snprintf(command,1024,"c++filt -p %s",m_name.c_str()); + memset(command, 0, 1024); + memset(buffer, 0, 1024); + snprintf(command,1024,"c++filt -p %s\n",m_name.c_str()); FILE *p = popen(command,"r"); buffer[0]=0; - fscanf(p,"%1023s",buffer); + fgets(buffer, 1023, p); fprintf(fp,"%s",buffer); if ( index >= m_instr_mem_size ) { fprintf(fp, "", m_start_PC + m_instr_mem_size - 1 ); diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 8b47c28..32de005 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -486,12 +486,29 @@ bool gpgpu_sim::can_start_kernel() return false; } -bool gpgpu_sim::get_more_cta_left() const -{ +bool gpgpu_sim::hit_max_cta_count() const { if (m_config.gpu_max_cta_opt != 0) { - if( m_total_cta_launched >= m_config.gpu_max_cta_opt ) - return false; + if( (gpu_tot_issued_cta + m_total_cta_launched) >= m_config.gpu_max_cta_opt ) + return true; } + return false; +} + +bool gpgpu_sim::kernel_more_cta_left(kernel_info_t *kernel) const { + if(hit_max_cta_count()) + return false; + + if(kernel && !kernel->no_more_ctas_to_run()) + return true; + + return false; +} + +bool gpgpu_sim::get_more_cta_left() const +{ + if(hit_max_cta_count()) + return false; + for(unsigned n=0; n < m_running_kernels.size(); n++ ) { if( m_running_kernels[n] && !m_running_kernels[n]->no_more_ctas_to_run() ) return true; @@ -503,7 +520,7 @@ kernel_info_t *gpgpu_sim::select_kernel() { for(unsigned n=0; n < m_running_kernels.size(); n++ ) { unsigned idx = (n+m_last_issued_kernel+1)%m_config.max_concurrent_kernel; - if( m_running_kernels[idx] && !m_running_kernels[idx]->no_more_ctas_to_run() ) { + if( kernel_more_cta_left(m_running_kernels[idx] ){ m_last_issued_kernel=idx; // record this kernel for stat print if it is the first time this kernel is selected for execution unsigned launch_uid = m_running_kernels[idx]->get_uid(); @@ -541,6 +558,16 @@ void gpgpu_sim::set_kernel_done( kernel_info_t *kernel ) assert( k != m_running_kernels.end() ); } +void gpgpu_sim::stop_all_running_kernels(){ + std::vector::iterator k; + for(k = m_running_kernels.begin(); k != m_running_kernels.end(); ++k){ + if(*k != NULL){ // If a kernel is active + set_kernel_done(*k); // Stop the kernel + assert(*k==NULL); + } + } +} + void set_ptx_warp_size(const struct core_config * warp_size); gpgpu_sim::gpgpu_sim( const gpgpu_sim_config &config ) @@ -564,6 +591,7 @@ gpgpu_sim::gpgpu_sim( const gpgpu_sim_config &config ) gpu_sim_insn = 0; gpu_tot_sim_insn = 0; gpu_tot_issued_cta = 0; + m_total_cta_launched = 0; gpu_deadlock = false; @@ -720,6 +748,7 @@ void gpgpu_sim::update_stats() { m_memory_stats->memlatstat_lat_pw(); gpu_tot_sim_cycle += gpu_sim_cycle; gpu_tot_sim_insn += gpu_sim_insn; + gpu_tot_issued_cta += m_total_cta_launched; } void gpgpu_sim::print_stats() @@ -892,7 +921,7 @@ void gpgpu_sim::gpu_print_stat() printf("gpu_tot_sim_cycle = %lld\n", gpu_tot_sim_cycle+gpu_sim_cycle); printf("gpu_tot_sim_insn = %lld\n", gpu_tot_sim_insn+gpu_sim_insn); printf("gpu_tot_ipc = %12.4f\n", (float)(gpu_tot_sim_insn+gpu_sim_insn) / (gpu_tot_sim_cycle+gpu_sim_cycle)); - printf("gpu_tot_issued_cta = %lld\n", gpu_tot_issued_cta); + printf("gpu_tot_issued_cta = %lld\n", gpu_tot_issued_cta + m_total_cta_launched); diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 4e6b7a5..33fffd3 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -372,10 +372,16 @@ public: bool can_start_kernel(); unsigned finished_kernel(); void set_kernel_done( kernel_info_t *kernel ); + void stop_all_running_kernels(); void init(); void cycle(); bool active(); + bool cycle_insn_cta_max_hit() { + return (m_config.gpu_max_cycle_opt && (gpu_tot_sim_cycle + gpu_sim_cycle) >= m_config.gpu_max_cycle_opt) || + (m_config.gpu_max_insn_opt && (gpu_tot_sim_insn + gpu_sim_insn) >= m_config.gpu_max_insn_opt) || + (m_config.gpu_max_cta_opt && (gpu_tot_issued_cta >= m_config.gpu_max_cta_opt) ); + } void print_stats(); void update_stats(); void deadlock_check(); @@ -391,6 +397,8 @@ public: unsigned threads_per_core() const; bool get_more_cta_left() const; + bool kernel_more_cta_left(kernel_info_t *kernel) const; + bool hit_max_cta_count() const; kernel_info_t *select_kernel(); const gpgpu_sim_config &get_config() const { return m_config; } @@ -445,7 +453,10 @@ private: unsigned m_last_issued_kernel; std::list m_finished_kernel; - unsigned m_total_cta_launched; + // m_total_cta_launched == per-kernel count. gpu_tot_issued_cta == global count. + unsigned long long m_total_cta_launched; + unsigned long long gpu_tot_issued_cta; + unsigned m_last_cluster_issue; float * average_pipeline_duty_cycle; float * active_sms; @@ -470,7 +481,6 @@ private: class memory_stats_t *m_memory_stats; class power_stat_t *m_power_stats; class gpgpu_sim_wrapper *m_gpgpusim_wrapper; - unsigned long long gpu_tot_issued_cta; unsigned long long last_gpu_sim_insn; unsigned long long last_liveness_message_time; @@ -488,8 +498,6 @@ public: unsigned long long gpu_sim_insn_last_update; unsigned gpu_sim_insn_last_update_sid; - - FuncCache get_cache_config(std::string kernel_name); void set_cache_config(std::string kernel_name, FuncCache cacheConfig ); bool has_special_cache_config(std::string kernel_name); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index f3ad1b0..ff2fac7 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -21,7 +21,7 @@ // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -// SERVICES; LOSSp OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. @@ -1932,7 +1932,7 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num ) m_kernel->dec_running(); printf("GPGPU-Sim uArch: Shader %u empty (release kernel %u \'%s\').\n", m_sid, m_kernel->get_uid(), m_kernel->name().c_str() ); - if( m_kernel->no_more_ctas_to_run() ) { + if( !m_gpu->kernel_more_cta_left(m_kernel) ) { if( !m_kernel->running() ) { printf("GPGPU-Sim uArch: GPU detected kernel \'%s\' finished on shader %u.\n", m_kernel->name().c_str(), m_sid ); m_gpu->set_kernel_done( m_kernel ); @@ -3246,7 +3246,7 @@ unsigned simt_core_cluster::issue_block2core() } } kernel_info_t *kernel = m_core[core]->get_kernel(); - if( kernel && !kernel->no_more_ctas_to_run() && (m_core[core]->get_n_active_cta() < m_config->max_cta(*kernel)) ) { + if( m_gpu->kernel_more_cta_left(kernel) && (m_core[core]->get_n_active_cta() < m_config->max_cta(*kernel)) ) { m_core[core]->issue_block2core(*kernel); num_blocks_issued++; m_cta_issue_next_core=core; diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index 28f909b..6ba38eb 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -96,10 +96,10 @@ void *gpgpu_sim_thread_concurrent(void*) { // concurrent kernel execution simulation thread do { - if(g_debug_execution >= 3) { - printf("GPGPU-Sim: *** simulation thread starting and spinning waiting for work ***\n"); - fflush(stdout); - } + if(g_debug_execution >= 3) { + printf("GPGPU-Sim: *** simulation thread starting and spinning waiting for work ***\n"); + fflush(stdout); + } while( g_stream_manager->empty_protected() && !g_sim_done ) ; if(g_debug_execution >= 3) { @@ -131,7 +131,13 @@ void *gpgpu_sim_thread_concurrent(void*) g_the_gpu->cycle(); sim_cycles = true; g_the_gpu->deadlock_check(); + }else { + if(g_the_gpu->cycle_insn_cta_max_hit()){ + g_stream_manager->stop_all_running_kernels(); + g_sim_done = true; + } } + active=g_the_gpu->active() || !g_stream_manager->empty_protected(); } while( active ); if(g_debug_execution >= 3) { diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 07cd44a..dd42f0a 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -223,19 +223,38 @@ bool stream_manager::register_finished_kernel(unsigned grid_uid) { // called by gpu simulation thread if(grid_uid > 0){ - CUstream_st *stream = m_grid_id_to_stream[grid_uid]; - kernel_info_t *kernel = stream->front().get_kernel(); - assert( grid_uid == kernel->get_uid() ); - stream->record_next_done(); - m_grid_id_to_stream.erase(grid_uid); - delete kernel; - return true; + CUstream_st *stream = m_grid_id_to_stream[grid_uid]; + kernel_info_t *kernel = stream->front().get_kernel(); + assert( grid_uid == kernel->get_uid() ); + stream->record_next_done(); + m_grid_id_to_stream.erase(grid_uid); + delete kernel; + return true; }else{ return false; } return false; } +void stream_manager::stop_all_running_kernels(){ + pthread_mutex_lock(&m_lock); + + // Signal m_gpu to stop all running kernels + m_gpu->stop_all_running_kernels(); + + // Clean up all streams waiting on running kernels + int count=0; + while(check_finished_kernel()){ + count++; + } + + // If any kernels completed, print out the current stats + if(count > 0) + m_gpu->print_stats(); + + pthread_mutex_unlock(&m_lock); +} + stream_operation stream_manager::front() { // called by gpu simulation thread @@ -366,11 +385,19 @@ void stream_manager::push( stream_operation op ) }; pthread_mutex_lock(&m_lock); - if( stream && !m_cuda_launch_blocking ) { - stream->push(op); - } else { - op.set_stream(&m_stream_zero); - m_stream_zero.push(op); + if(!m_gpu->cycle_insn_cta_max_hit()) { + // Accept the stream operation if the maximum cycle/instruction/cta counts are not triggered + if( stream && !m_cuda_launch_blocking ) { + stream->push(op); + } else { + op.set_stream(&m_stream_zero); + m_stream_zero.push(op); + } + }else { + // Otherwise, ignore operation and continue + printf("GPGPU-Sim API: Maximum cycle, instruction, or CTA count hit. Skipping:"); + op.print(stdout); + printf("\n"); } if(g_debug_execution >= 3) print_impl(stdout); diff --git a/src/stream_manager.h b/src/stream_manager.h index 7275402..701b33c 100644 --- a/src/stream_manager.h +++ b/src/stream_manager.h @@ -246,6 +246,7 @@ public: void print( FILE *fp); void push( stream_operation op ); bool operation(bool * sim); + void stop_all_running_kernels(); private: void print_impl( FILE *fp); -- cgit v1.3 From d3a28ecd166dbbb46804b1c73de139a0512b0d64 Mon Sep 17 00:00:00 2001 From: Tayler Hetherington Date: Fri, 5 Jun 2015 15:46:35 -0700 Subject: Fixing bug with local stats not being reset on call to update_stats. Added code to remove the trailing newline character from the C++ name de-mangling fix. Also, fixed small bug with previous commit --- src/cuda-sim/ptx_ir.cc | 5 ++++- src/gpgpu-sim/gpu-sim.cc | 6 +++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index fa37cc4..751b3f4 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1258,10 +1258,13 @@ unsigned function_info::print_insn( unsigned pc, FILE * fp ) const char buffer[1024]; memset(command, 0, 1024); memset(buffer, 0, 1024); - snprintf(command,1024,"c++filt -p %s\n",m_name.c_str()); + snprintf(command,1024,"c++filt -p %s",m_name.c_str()); FILE *p = popen(command,"r"); buffer[0]=0; fgets(buffer, 1023, p); + // Remove trailing "\n" in buffer + char *c; + if ((c=strchr(buffer, '\n')) != NULL) *c = '\0'; fprintf(fp,"%s",buffer); if ( index >= m_instr_mem_size ) { fprintf(fp, "", m_start_PC + m_instr_mem_size - 1 ); diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 32de005..eafb909 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -520,7 +520,7 @@ kernel_info_t *gpgpu_sim::select_kernel() { for(unsigned n=0; n < m_running_kernels.size(); n++ ) { unsigned idx = (n+m_last_issued_kernel+1)%m_config.max_concurrent_kernel; - if( kernel_more_cta_left(m_running_kernels[idx] ){ + if( kernel_more_cta_left(m_running_kernels[idx]) ){ m_last_issued_kernel=idx; // record this kernel for stat print if it is the first time this kernel is selected for execution unsigned launch_uid = m_running_kernels[idx]->get_uid(); @@ -749,6 +749,10 @@ void gpgpu_sim::update_stats() { gpu_tot_sim_cycle += gpu_sim_cycle; gpu_tot_sim_insn += gpu_sim_insn; gpu_tot_issued_cta += m_total_cta_launched; + + gpu_sim_cycle = 0; + gpu_sim_insn = 0; + m_total_cta_launched = 0; } void gpgpu_sim::print_stats() -- cgit v1.3 From 2dee85bd4e7558e190880e2ade20764131945569 Mon Sep 17 00:00:00 2001 From: Guillermo JuliaÌn Date: Fri, 10 Jul 2015 14:05:33 +0200 Subject: Increase line buffer size --- src/cuda-sim/ptx.l | 4 ++-- src/cuda-sim/ptx_parser.cc | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index dfed936..98d0b6c 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -36,7 +36,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "ptx.tab.h" #include -char linebuf[1024]; +char linebuf[4096]; unsigned col = 0; #define TC col+=strlen(ptx_text); #define CHECK_UNSIGNED \ @@ -370,7 +370,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; "//"[^\n]* TC; // eat single -\n.* col=0; strncpy(linebuf, yytext + 1, 1024); yyless( 1 ); +\n.* col=0; strncpy(linebuf, yytext + 1, sizeof(linebuf)); yyless( 1 ); " " TC; "\t" TC; diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index 824714a..2e5ed8e 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -240,7 +240,7 @@ void parse_assert_impl( int test_value, const char *file, unsigned line, const c parse_error_impl(file,line, msg); } -extern char linebuf[1024]; +extern char linebuf[4096]; void set_return() -- cgit v1.3 From 6d99ddf6d366302c29890a98f217a3885ce3d0e2 Mon Sep 17 00:00:00 2001 From: Guillermo JuliaÌn Date: Sat, 11 Jul 2015 11:16:42 +0200 Subject: Allow visible directives in variable specifications --- src/cuda-sim/ptx.y | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 79faddf..a6cdfda 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -320,6 +320,7 @@ var_spec_list: var_spec var_spec: space_spec | type_spec | align_spec + | VISIBLE_DIRECTIVE | EXTERN_DIRECTIVE { add_extern_spec(); } ; -- cgit v1.3 From b1fd283c064222579ee5174a980abf72e8e6ef26 Mon Sep 17 00:00:00 2001 From: Guillermo JuliaÌn Date: Sat, 11 Jul 2015 11:20:52 +0200 Subject: Allow const directives in the parameter specification --- src/cuda-sim/ptx.y | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index a6cdfda..8f47867 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -259,6 +259,7 @@ ptr_spec: /*empty*/ ptr_space_spec: GLOBAL_DIRECTIVE { add_ptr_spec(global_space); } | LOCAL_DIRECTIVE { add_ptr_spec(local_space); } | SHARED_DIRECTIVE { add_ptr_spec(shared_space); } + | CONST_DIRECTIVE { add_ptr_spec(global_space); } ptr_align_spec: ALIGN_DIRECTIVE INT_OPERAND -- cgit v1.3 From 09310926dce32645556786edff790c6f8579b932 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 5 Jun 2015 14:19:06 -0700 Subject: Adding in changes to put generated code files in the build directory instead of the source directory - since this causes issues for parallel buildwq --- cuobjdump_to_ptxplus/Makefile | 40 +++++++++++++++++++++++++--------------- libcuda/Makefile | 15 +++++++++------ src/intersim2/Makefile | 12 ++++++------ 3 files changed, 40 insertions(+), 27 deletions(-) diff --git a/cuobjdump_to_ptxplus/Makefile b/cuobjdump_to_ptxplus/Makefile index 0358970..242a066 100644 --- a/cuobjdump_to_ptxplus/Makefile +++ b/cuobjdump_to_ptxplus/Makefile @@ -27,41 +27,52 @@ $(OUTPUT_DIR)/cuobjdump_to_ptxplus: $(OUTPUT_DIR)/cuobjdumpInst.o $(OUTPUT_DIR)/ ${LD} ${LDFLAGS} -o $@ $(OUTPUT_DIR)/cuobjdumpInst.o $(OUTPUT_DIR)/cuobjdumpInstList.o $(OUTPUT_DIR)/cuobjdump_to_ptxplus.o $(PTX_PARSER_OBJECTS) $(SASS_PARSER_OBJECTS) $(ELF_PARSER_OBJECTS) $(HEADER_PARSER_OBJECTS) -lex.ptx_.c : ../src/cuda-sim/ptx.l - ${LEX} ${LEXFLAGS} ../src/cuda-sim/ptx.l +$(OUTPUT_DIR)/lex.ptx_.c : ../src/cuda-sim/ptx.l + ${LEX} ${LEXFLAGS} -o$(OUTPUT_DIR)/lex.ptx_.c ../src/cuda-sim/ptx.l -ptx.tab.c : ../src/cuda-sim/ptx.y - ${YACC} ${YFLAGS} --name-prefix=ptx_ -v ../src/cuda-sim/ptx.y +$(OUTPUT_DIR)/ptx.tab.c : ../src/cuda-sim/ptx.y + ${YACC} ${YFLAGS} --name-prefix=ptx_ -v ../src/cuda-sim/ptx.y --file-prefix=$(OUTPUT_DIR)/ptx -ptx.tab.h : ptx.tab.c +$(OUTPUT_DIR)/ptx.tab.h :$(OUTPUT_DIR)/ptx.tab.c -$(OUTPUT_DIR)/lex.ptx_.o : lex.ptx_.c ptx.tab.h - ${CXX} ${CXXFLAGS} -c lex.ptx_.c -o $@ +$(OUTPUT_DIR)/lex.ptx_.o : $(OUTPUT_DIR)/lex.ptx_.c $(OUTPUT_DIR)/ptx.tab.h + ${CXX} ${CXXFLAGS} -c $(OUTPUT_DIR)/lex.ptx_.c -o $@ -$(OUTPUT_DIR)/ptx.tab.o : ptx.tab.c ptx_parser.h - ${CXX} ${CXXFLAGS} -c ptx.tab.c -o $@ +$(OUTPUT_DIR)/ptx.tab.o : $(OUTPUT_DIR)/ptx.tab.c ptx_parser.h + ${CXX} ${CXXFLAGS} -c $(OUTPUT_DIR)/ptx.tab.c -o $@ - -%_lexer.cc: %.l %_parser.hh +$(OUTPUT_DIR)/%_lexer.cc: %.l $(OUTPUT_DIR)/%_parser.hh $(LEX) $(LEXFLAGS) -P $*_ -o$@ $< -%_parser.cc: %.y - $(YACC) $(YFLAGS) -p $*_ -o$@ $< +$(OUTPUT_DIR)/%_parser.cc: %.y + $(YACC) $(YFLAGS) -p $*_ -o$@ $< --file-prefix=$(OUTPUT_DIR)/$@ # The ':' is needed otherwise make gets confused and doesn't understand that it knows how to make %Parser.hpp from %Parser.cpp. # : in bash is equivalent to NOP (no operation) -%_parser.hh: %_parser.cc +$(OUTPUT_DIR)/%_parser.hh: $(OUTPUT_DIR)/%_parser.cc + : + +$(OUTPUT_DIR)/%_parser.hh: %_parser.cc : $(OUTPUT_DIR)/%.o: %.cc $(CXX) ${CXXFLAGS} -c -o $@ $< +$(OUTPUT_DIR)/%.o: $(OUTPUT_DIR)/%.cc + $(CXX) ${CXXFLAGS} -c -o $@ $< + $(OUTPUT_DIR)/%.o: %.cpp %.h $(CXX) ${CXXFLAGS} -c -o $@ $< +$(OUTPUT_DIR)/%.o: $(OUTPUT_DIR)/%.cpp $(OUTPUT_DIR)/%.h + $(CXX) ${CXXFLAGS} -c -o $@ $< + $(OUTPUT_DIR)/%.o: %.c %.h ${CXX} ${CCFLAGS} -c -o $@ $< +$(OUTPUT_DIR)/%.o: $(OUTPUT_DIR)/%.c $(OUTPUT_DIR)/%.h + ${CXX} ${CCFLAGS} -c -o $@ $< + SRCS = $(shell ls *.cc) $(OUTPUT_DIR)/Makefile.makedepend: depend @@ -79,4 +90,3 @@ clean: rm -f $(OUTPUT_DIR)/Makefile.makedepend $(OUTPUT_DIR)/Makefile.makedepend.bak include $(OUTPUT_DIR)/Makefile.makedepend - diff --git a/libcuda/Makefile b/libcuda/Makefile index b1a6552..13932e2 100644 --- a/libcuda/Makefile +++ b/libcuda/Makefile @@ -108,20 +108,23 @@ lib$(PROG).a: $(OBJS) ar rcs $(OUTPUT_DIR)/lib$(PROG).a $(OBJS) $(OUTPUT_DIR)/%.o: %.cc - $(CPP) $(CXXFLAGS) -I./ -I$(CUDA_INSTALL_PATH)/include -c $< -o $@ + $(CPP) $(CXXFLAGS) -I./ -I$(OUTPUT_DIR) -I$(CUDA_INSTALL_PATH)/include -c $< -o $@ $(OUTPUT_DIR)/%.o: %.c - $(CC) $(CCFLAGS) -I./ -I$(CUDA_INSTALL_PATH)/include -c $< -o $@ + $(CC) $(CCFLAGS) -I./ -I$(OUTPUT_DIR) -I$(CUDA_INSTALL_PATH)/include -c $< -o $@ -cuobjdump_parser.c: cuobjdump.y - $(YACC) $(YFLAGS) -p cuobjdump_ -o$@ $< +$(OUTPUT_DIR)/%.o: $(OUTPUT_DIR)/%.c + $(CC) $(CCFLAGS) -I./ -I$(OUTPUT_DIR) -I$(CUDA_INSTALL_PATH)/include -c $< -o $@ -cuobjdump_lexer.c: cuobjdump.l cuobjdump_parser.h +$(OUTPUT_DIR)/cuobjdump_parser.c: cuobjdump.y + $(YACC) $(YFLAGS) -p cuobjdump_ -o$@ $< --file-prefix=$(OUTPUT_DIR)/cuobjdump + +$(OUTPUT_DIR)/cuobjdump_lexer.c: cuobjdump.l $(OUTPUT_DIR)/cuobjdump_parser.h $(LEX) $(LEXFLAGS) -P cuobjdump_ -o$@ $< # The next rule means just get parser.c and you will get parser.h with it # in other words, get parser.c and do nothing to get parser.h -%_parser.h: %_parser.c +$(OUTPUT_DIR)/%_parser.h: $(OUTPUT_DIR)/%_parser.c : $(OUTPUT_DIR)/Makefile.makedepend: depend diff --git a/src/intersim2/Makefile b/src/intersim2/Makefile index fd9fba8..ef948d6 100644 --- a/src/intersim2/Makefile +++ b/src/intersim2/Makefile @@ -126,10 +126,10 @@ endif # rules to compile simulator -${LEX_OBJS}: lex.yy.c y.tab.h +${LEX_OBJS}: $(OBJDIR)/lex.yy.c $(OBJDIR)/y.tab.h $(CC) $(CPPFLAGS) -c $< -o $@ -${YACC_OBJS}: y.tab.c y.tab.h +${YACC_OBJS}: $(OBJDIR)/y.tab.c $(OBJDIR)/y.tab.h $(CC) $(CPPFLAGS) -c $< -o $@ ${OBJDIR}/%.o: %.cpp @@ -168,8 +168,8 @@ clean: rm -f y.tab.c y.tab.h lex.yy.c rm -f moc_bgui.cpp -y.tab.c y.tab.h: config.y - $(YACC) -d $< +$(OBJDIR)/y.tab.c $(OBJDIR)/y.tab.h: config.y + $(YACC) -d $< --file-prefix=$(OBJDIR)/y -lex.yy.c: config.l - $(LEX) $< +$(OBJDIR)/lex.yy.c: config.l + $(LEX) -o$@ $< -- cgit v1.3 From cdcb9dde7313f2b90914361df752b9dfd7aa0ed8 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 5 Jun 2015 14:22:32 -0700 Subject: Adding a description of the makefile changes --- CHANGES | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGES b/CHANGES index 216490e..512993b 100644 --- a/CHANGES +++ b/CHANGES @@ -7,6 +7,7 @@ Version 3.2.3+edits (development branch) versus 3.2.3 - Added support for bar.arrive and bar.red instructions. - Initial support for CUDA 5.0,5.5 and 6.0 to get template running. - Removed intersim2 svn repository files +- Changed the makefile for cuobjdump_toptxplus,libcuda,intersim2 so that it outputs temporary files into the build directory - Bug fixes: - Fixed bug #81, fix ordering of pushing branch entries to the stack -- cgit v1.3 From b2fc784cbb1c2e65736cea88d61509d08fddd83f Mon Sep 17 00:00:00 2001 From: ElTantawy Date: Thu, 12 May 2016 13:36:03 -0700 Subject: initial support for cuda 7.5 parsing --- libcuda/cuobjdump.l | 60 +++++++++++++++++++++++++++++++++++++++-------------- libcuda/cuobjdump.y | 30 +++++++++++++++++++++------ 2 files changed, 69 insertions(+), 21 deletions(-) diff --git a/libcuda/cuobjdump.l b/libcuda/cuobjdump.l index d7086ad..c86a861 100644 --- a/libcuda/cuobjdump.l +++ b/libcuda/cuobjdump.l @@ -52,8 +52,11 @@ void cuobjdump_error(const char*); %s ptxcode %s sasscode %s elfcode -%s header +%s elfheader +%s ptxheader %s endheader +%s identifier +%s identifierF alpha [a-zA-Z] numeric [0-9] @@ -67,16 +70,20 @@ newlines {newline}+ "ptxasOptions"{notnewline}*{newline} [1-9]{numeric}* yylval.string_value = strdup(yytext); return DECIMAL; +"has debug info"{newline} + "Fatbin ptx code:"{newline} { yy_push_state(ptxcode); - yy_push_state(header); + yy_push_state(identifier); + yy_push_state(ptxheader); yylval.string_value = strdup(yytext); return PTXHEADER; } "Fatbin elf code:"{newline} { yy_push_state(elfcode); - yy_push_state(header); + yy_push_state(identifier); + yy_push_state(elfheader); yylval.string_value = strdup(yytext); return ELFHEADER; } @@ -94,22 +101,45 @@ newlines {newline}+ /*SASS code tokens*/ {notnewline}*{newline} yylval.string_value = strdup(yytext); return SASSLINE; +"identifier = " BEGIN(identifierF); return H_IDENTIFIER; +"\n" yy_pop_state(); + +{notnewline}+ yylval.string_value = strdup(yytext); yy_pop_state(); return FILENAME; + + + + /*Header tokens*/ +[[:alnum:]_]+ yylval.string_value = strdup(yytext); return IDENTIFIER; +"================" return H_SEPARATOR; +"arch = " return H_ARCH; +"code version = " return H_CODEVERSION; +\[{numeric},{numeric}\] return CODEVERSION; +"producer = " return H_PRODUCER; +"" return H_UNKNOWN; +"host = " return H_HOST; +"compile_size = " BEGIN(endheader); return H_COMPILESIZE; + + /*Header tokens*/ -
[[:alnum:]_]+ yylval.string_value = strdup(yytext); return IDENTIFIER; -
"================" return H_SEPARATOR; -
"arch = " return H_ARCH; -
"code version = " return H_CODEVERSION; -
\[{numeric},{numeric}\] return CODEVERSION; -
"producer = " return H_PRODUCER; -
"host = " return H_HOST; -
"compile_size = " return H_COMPILESIZE; -
"compressed"{newline} -
"identifier = " BEGIN(endheader); return H_IDENTIFIER; -
"has debug info"{newline} +[[:alnum:]_]+ yylval.string_value = strdup(yytext); return IDENTIFIER; +"================" return H_SEPARATOR; +"arch = " return H_ARCH; +"code version = " return H_CODEVERSION; +\[{numeric},{numeric}\] return CODEVERSION; +"producer = " return H_PRODUCER; +"host = " return H_HOST; +"compile_size = " return H_COMPILESIZE; +"compressed"{newline} yy_pop_state(); return H_COMPRESSED; + + + + + /* Looking for the identifier (filename) then the header is done */ /* [[:alnum:]_\./]+ yylval.string_value = strdup(yytext); yy_pop_state(); return FILENAME; */ -{notnewline}+ yylval.string_value = strdup(yytext); yy_pop_state(); return FILENAME; +{notnewline}+ yylval.string_value = strdup(yytext); yy_pop_state(); return IDENTIFIER; + {newline} return NEWLINE; diff --git a/libcuda/cuobjdump.y b/libcuda/cuobjdump.y index ec97283..f86d445 100644 --- a/libcuda/cuobjdump.y +++ b/libcuda/cuobjdump.y @@ -39,6 +39,7 @@ void setCuobjdumpelffilename(const char* filename); void setCuobjdumpsassfilename(const char* filename); int elfserial = 1; int ptxserial = 1; +int yydebug=1; FILE *ptxfile; FILE *elffile; FILE *sassfile; @@ -47,7 +48,7 @@ char filename [1024]; %union { char* string_value; } -%token H_SEPARATOR H_ARCH H_CODEVERSION H_PRODUCER H_HOST H_COMPILESIZE H_IDENTIFIER +%token H_SEPARATOR H_ARCH H_CODEVERSION H_PRODUCER H_HOST H_COMPILESIZE H_IDENTIFIER H_UNKNOWN H_COMPRESSED %token CODEVERSION %token STRING %token FILENAME @@ -61,6 +62,7 @@ char filename [1024]; %% + program : {printf("######### cuobjdump parser ########\n");} emptylines section | program section; @@ -73,7 +75,7 @@ section : PTXHEADER { snprintf(filename, 1024, "_cuobjdump_%d.ptx", ptxserial++); ptxfile = fopen(filename, "w"); setCuobjdumpptxfilename(filename); - } headerinfo ptxcode { + } headerinfo identifier ptxcode { fclose(ptxfile); } | ELFHEADER { @@ -81,7 +83,8 @@ section : PTXHEADER { snprintf(filename, 1024, "_cuobjdump_%d.elf", elfserial); elffile = fopen(filename, "w"); setCuobjdumpelffilename(filename); - } headerinfo elfcode { + } headerinfo identifier{ + } elfcode { fclose(elffile); snprintf(filename, 1024, "_cuobjdump_%d.sass", elfserial++); sassfile = fopen(filename, "w"); @@ -91,17 +94,32 @@ section : PTXHEADER { }; headerinfo : H_SEPARATOR NEWLINE + H_ARCH IDENTIFIER NEWLINE + H_CODEVERSION CODEVERSION NEWLINE + H_PRODUCER H_UNKNOWN NEWLINE + H_HOST IDENTIFIER NEWLINE + H_COMPILESIZE IDENTIFIER emptylines {setCuobjdumparch($4);}; + | H_SEPARATOR NEWLINE H_ARCH IDENTIFIER NEWLINE H_CODEVERSION CODEVERSION NEWLINE H_PRODUCER IDENTIFIER NEWLINE H_HOST IDENTIFIER NEWLINE - H_COMPILESIZE IDENTIFIER NEWLINE - H_IDENTIFIER FILENAME emptylines {setCuobjdumparch($4); setCuobjdumpidentifier($19);}; + H_COMPILESIZE IDENTIFIER emptylines {setCuobjdumparch($4);}; + | H_SEPARATOR NEWLINE + H_ARCH IDENTIFIER NEWLINE + H_CODEVERSION CODEVERSION NEWLINE + H_PRODUCER IDENTIFIER NEWLINE + H_HOST IDENTIFIER NEWLINE + H_COMPILESIZE IDENTIFIER NEWLINE + H_COMPRESSED emptylines {setCuobjdumparch($4);}; + +identifier : H_IDENTIFIER FILENAME {setCuobjdumpidentifier($2);}; + | ; ptxcode : ptxcode PTXLINE {fprintf(ptxfile, "%s", $2);} | ; -elfcode : elfcode ELFLINE {fprintf(elffile, "%s", $2);} +elfcode : elfcode ELFLINE {printf(elffile, "%s", $2);} | ; sasscode : sasscode SASSLINE {fprintf(sassfile, "%s", $2);} -- cgit v1.3 From c0ed7da45b3836cefc08c6072fd183d2b33bbdeb Mon Sep 17 00:00:00 2001 From: Ahmed ElTantawy Date: Thu, 12 May 2016 14:25:14 -0700 Subject: updating Makefile and setup environment for 7.5 support --- Makefile | 2 +- setup_environment | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 080ca2d..9e2c576 100644 --- a/Makefile +++ b/Makefile @@ -155,7 +155,7 @@ $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib if [ ! -f $(SIM_LIB_DIR)/libcudart.so.5.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.5.0; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.5.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.5.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.6.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.6.0; fi - + if [ ! -f $(SIM_LIB_DIR)/libcudart.so.7.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.7.5; fi $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib g++ -dynamiclib -Wl,-headerpad_max_install_names,-undefined,dynamic_lookup,-compatibility_version,1.1,-current_version,1.1\ $(SIM_OBJ_FILES_DIR)/libcuda/*.o \ diff --git a/setup_environment b/setup_environment index c55d71f..2684514 100644 --- a/setup_environment +++ b/setup_environment @@ -43,7 +43,7 @@ CC_VERSION=`gcc --version | head -1 | awk '{for(i=1;i<=NF;i++){ if(match($i,/^[0 CUDA_VERSION_STRING=`$CUDA_INSTALL_PATH/bin/nvcc --version | awk '/release/ {print $5;}' | sed 's/,//'`; CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("%02u%02u", 10*int($1), 10*$2);}'` -if [ $CUDA_VERSION_NUMBER -gt 6000 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then +if [ $CUDA_VERSION_NUMBER -gt 7500 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then echo "ERROR ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; return elif [ $CUDA_VERSION_NUMBER -gt 4020 ]; then -- cgit v1.3 From b27f110d3ca92f7af869b298105ae014581367e9 Mon Sep 17 00:00:00 2001 From: speverel Date: Thu, 12 May 2016 14:45:11 -0700 Subject: Commented out line that checks for identifier in PTX file so that sim runs in 7.5 --- libcuda/cuda_runtime_api.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index eed4017..496d83c 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1525,7 +1525,7 @@ cuobjdumpPTXSection* findPTXSectionInList(std::list sectionli ){ cuobjdumpPTXSection* ptxsection; if((ptxsection=dynamic_cast(*iter)) != NULL){ - if(ptxsection->getIdentifier() == identifier) + //if(ptxsection->getIdentifier() == identifier) return ptxsection; } } -- cgit v1.3 From 4bdf48ed2098e036da1503405c30b71f39be0e94 Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 12 May 2016 16:54:39 -0700 Subject: added an assertion to pruneSectionList --- libcuda/cuda_runtime_api.cc | 2 ++ libcuda/cuobjdump.y | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 496d83c..7495767 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1484,6 +1484,8 @@ std::list pruneSectionList(std::list cuobj delete *iter; } } + + assert(!prunedList.empty() && "WARNING: Change -gpgpu_ptx_force_max_capability in gpgpusim.config to match the largest Gencode argument in the Makefile"); return prunedList; } diff --git a/libcuda/cuobjdump.y b/libcuda/cuobjdump.y index f86d445..5fc0c8f 100644 --- a/libcuda/cuobjdump.y +++ b/libcuda/cuobjdump.y @@ -39,7 +39,7 @@ void setCuobjdumpelffilename(const char* filename); void setCuobjdumpsassfilename(const char* filename); int elfserial = 1; int ptxserial = 1; -int yydebug=1; + FILE *ptxfile; FILE *elffile; FILE *sassfile; -- cgit v1.3 From 0b95282e887e6cc6eb48d93d5aa51252588c3260 Mon Sep 17 00:00:00 2001 From: Ahmed ElTantawy Date: Fri, 13 May 2016 08:06:17 -0700 Subject: getting the parsing compatible with previous version - tested on 4.2, 5.5 and 7.5 --- libcuda/cuobjdump.l | 20 +++++++++++++------- libcuda/cuobjdump.y | 21 +++++++++------------ 2 files changed, 22 insertions(+), 19 deletions(-) diff --git a/libcuda/cuobjdump.l b/libcuda/cuobjdump.l index c86a861..f63ee73 100644 --- a/libcuda/cuobjdump.l +++ b/libcuda/cuobjdump.l @@ -55,8 +55,9 @@ void cuobjdump_error(const char*); %s elfheader %s ptxheader %s endheader -%s identifier -%s identifierF +%x identifier +%x conidentifier +%s endidentifier alpha [a-zA-Z] numeric [0-9] @@ -101,10 +102,16 @@ newlines {newline}+ /*SASS code tokens*/ {notnewline}*{newline} yylval.string_value = strdup(yytext); return SASSLINE; -"identifier = " BEGIN(identifierF); return H_IDENTIFIER; -"\n" yy_pop_state(); +{newline}"compressed"{newline} BEGIN(conidentifier); return H_COMPRESSED; +{newline}"identifier = " BEGIN(endidentifier); return H_IDENTIFIER; +{newline}{newline} yy_pop_state(); -{notnewline}+ yylval.string_value = strdup(yytext); yy_pop_state(); return FILENAME; + +"identifier = " BEGIN(endidentifier); return H_IDENTIFIER; +{newline} yy_pop_state(); + + +{notnewline}+ yylval.string_value = strdup(yytext); yy_pop_state(); return FILENAME; @@ -128,8 +135,7 @@ newlines {newline}+ \[{numeric},{numeric}\] return CODEVERSION; "producer = " return H_PRODUCER; "host = " return H_HOST; -"compile_size = " return H_COMPILESIZE; -"compressed"{newline} yy_pop_state(); return H_COMPRESSED; +"compile_size = " BEGIN(endheader); return H_COMPILESIZE; diff --git a/libcuda/cuobjdump.y b/libcuda/cuobjdump.y index 5fc0c8f..29509e8 100644 --- a/libcuda/cuobjdump.y +++ b/libcuda/cuobjdump.y @@ -39,7 +39,7 @@ void setCuobjdumpelffilename(const char* filename); void setCuobjdumpsassfilename(const char* filename); int elfserial = 1; int ptxserial = 1; - +int yydebug = 1; FILE *ptxfile; FILE *elffile; FILE *sassfile; @@ -75,7 +75,7 @@ section : PTXHEADER { snprintf(filename, 1024, "_cuobjdump_%d.ptx", ptxserial++); ptxfile = fopen(filename, "w"); setCuobjdumpptxfilename(filename); - } headerinfo identifier ptxcode { + } headerinfo compressedkeyword identifier ptxcode { fclose(ptxfile); } | ELFHEADER { @@ -84,6 +84,7 @@ section : PTXHEADER { elffile = fopen(filename, "w"); setCuobjdumpelffilename(filename); } headerinfo identifier{ + printf("\nHeader Info and Identifier Parsed\n"); } elfcode { fclose(elffile); snprintf(filename, 1024, "_cuobjdump_%d.sass", elfserial++); @@ -98,24 +99,20 @@ headerinfo : H_SEPARATOR NEWLINE H_CODEVERSION CODEVERSION NEWLINE H_PRODUCER H_UNKNOWN NEWLINE H_HOST IDENTIFIER NEWLINE - H_COMPILESIZE IDENTIFIER emptylines {setCuobjdumparch($4);}; + H_COMPILESIZE IDENTIFIER {setCuobjdumparch($4);}; | H_SEPARATOR NEWLINE H_ARCH IDENTIFIER NEWLINE H_CODEVERSION CODEVERSION NEWLINE H_PRODUCER IDENTIFIER NEWLINE H_HOST IDENTIFIER NEWLINE - H_COMPILESIZE IDENTIFIER emptylines {setCuobjdumparch($4);}; - | H_SEPARATOR NEWLINE - H_ARCH IDENTIFIER NEWLINE - H_CODEVERSION CODEVERSION NEWLINE - H_PRODUCER IDENTIFIER NEWLINE - H_HOST IDENTIFIER NEWLINE - H_COMPILESIZE IDENTIFIER NEWLINE - H_COMPRESSED emptylines {setCuobjdumparch($4);}; + H_COMPILESIZE IDENTIFIER {setCuobjdumparch($4);}; -identifier : H_IDENTIFIER FILENAME {setCuobjdumpidentifier($2);}; +identifier : H_IDENTIFIER FILENAME emptylines {setCuobjdumpidentifier($2);}; | ; +compressedkeyword : H_COMPRESSED emptylines + | ; + ptxcode : ptxcode PTXLINE {fprintf(ptxfile, "%s", $2);} | ; -- cgit v1.3 From 7ac360c0a2defc5612fec6a106c703145e642aaa Mon Sep 17 00:00:00 2001 From: Ahmed ElTantawy Date: Fri, 13 May 2016 09:38:58 -0700 Subject: detailed error message when minimum found ptx capability is still larger than the maximum forced capability --- libcuda/cuda_runtime_api.cc | 22 ++++++++++++++-------- libcuda/cuobjdump.y | 6 ++---- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 7495767..f2e3359 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1457,18 +1457,22 @@ std::list pruneSectionList(std::list cuobj std::list prunedList; - //Find the highest capability (that is lower than the forces maximum) for each cubin file + //Find the highest capability (that is lower than the forced maximum) for each cubin file //and set it in cuobjdumpSectionMap. Do this only for ptx sections std::map cuobjdumpSectionMap; + int min_ptx_capability_found=0; for ( std::list::iterator iter = cuobjdumpSectionList.begin(); iter != cuobjdumpSectionList.end(); iter++){ unsigned capability = (*iter)->getArch(); - if(dynamic_cast(*iter) != NULL && - (capability <= forced_max_capability || - forced_max_capability==0)) { - if(cuobjdumpSectionMap[(*iter)->getIdentifier()] < capability) - cuobjdumpSectionMap[(*iter)->getIdentifier()] = capability; + if(dynamic_cast(*iter) != NULL){ + if(capabilitygetIdentifier()] < capability) || + (cuobjdumpSectionMap.find((*iter)->getIdentifier())==cuobjdumpSectionMap.end())) + cuobjdumpSectionMap[(*iter)->getIdentifier()] = capability; + } } } @@ -1484,8 +1488,10 @@ std::list pruneSectionList(std::list cuobj delete *iter; } } - - assert(!prunedList.empty() && "WARNING: Change -gpgpu_ptx_force_max_capability in gpgpusim.config to match the largest Gencode argument in the Makefile"); + if(prunedList.empty()){ + printf("Error: No PTX sections found with sm capability that is lower than current forced maximum capability \n minimum ptx capability found = %u, maximum forced ptx capability = %u \n User might want to change either the forced maximum capability from gpgpusim configuration or update the compilation to generate the required PTX version",min_ptx_capability_found,forced_max_capability); + abort(); + } return prunedList; } diff --git a/libcuda/cuobjdump.y b/libcuda/cuobjdump.y index 29509e8..dce7e3d 100644 --- a/libcuda/cuobjdump.y +++ b/libcuda/cuobjdump.y @@ -39,7 +39,6 @@ void setCuobjdumpelffilename(const char* filename); void setCuobjdumpsassfilename(const char* filename); int elfserial = 1; int ptxserial = 1; -int yydebug = 1; FILE *ptxfile; FILE *elffile; FILE *sassfile; @@ -84,7 +83,6 @@ section : PTXHEADER { elffile = fopen(filename, "w"); setCuobjdumpelffilename(filename); } headerinfo identifier{ - printf("\nHeader Info and Identifier Parsed\n"); } elfcode { fclose(elffile); snprintf(filename, 1024, "_cuobjdump_%d.sass", elfserial++); @@ -107,8 +105,8 @@ headerinfo : H_SEPARATOR NEWLINE H_HOST IDENTIFIER NEWLINE H_COMPILESIZE IDENTIFIER {setCuobjdumparch($4);}; -identifier : H_IDENTIFIER FILENAME emptylines {setCuobjdumpidentifier($2);}; - | ; +identifier : H_IDENTIFIER FILENAME emptylines {setCuobjdumpidentifier($2);} + | {setCuobjdumpidentifier("default");}; compressedkeyword : H_COMPRESSED emptylines | ; -- cgit v1.3 From 1f25b1cc7a71898eda0216ec0a74cb55266cd4f0 Mon Sep 17 00:00:00 2001 From: Ahmed ElTantawy Date: Fri, 13 May 2016 09:47:22 -0700 Subject: remove the hackish comment and assign a default identifier for CUDA>=7.5 --- libcuda/cuda_runtime_api.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index f2e3359..fc6ca03 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1533,7 +1533,7 @@ cuobjdumpPTXSection* findPTXSectionInList(std::list sectionli ){ cuobjdumpPTXSection* ptxsection; if((ptxsection=dynamic_cast(*iter)) != NULL){ - //if(ptxsection->getIdentifier() == identifier) + if(ptxsection->getIdentifier() == identifier) return ptxsection; } } @@ -1632,10 +1632,13 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) // - Obtains the pointer to the actual fatbin structure from the FatBin handle (fatCubin). // - An integer inside the fatbin structure contains the relative offset to the source code file name. // - This offset differs among different CUDA and GCC versions. + #if (CUDART_VERSION <= 6000) char * pfatbin = (char*) fatDeviceText->d; int offset = *((int*)(pfatbin+48)); char * filename = (pfatbin+16+offset); - + #else + char * filename = "default"; + #endif // The extracted file name is associated with a fat_cubin_handle passed // into cudaLaunch(). Inside cudaLaunch(), the associated file name is // used to find the PTX/SASS section from cuobjdump, which contains the -- cgit v1.3 From 2cbd1535c4babf19d3fa5a32f05633493d295146 Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 13 May 2016 11:51:08 -0700 Subject: changed the SM version flag for generating ptxinfo to be dynamic instead of 20 --- libcuda/cuda_runtime_api.cc | 22 ++++++++++++++++------ src/cuda-sim/ptx_loader.cc | 5 +++-- src/cuda-sim/ptx_loader.h | 2 +- 3 files changed, 20 insertions(+), 9 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index fc6ca03..910bebd 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1469,8 +1469,8 @@ std::list pruneSectionList(std::list cuobj if(capabilitygetIdentifier()] < capability) || - (cuobjdumpSectionMap.find((*iter)->getIdentifier())==cuobjdumpSectionMap.end())) + if((cuobjdumpSectionMap.find((*iter)->getIdentifier())==cuobjdumpSectionMap.end()) + || (cuobjdumpSectionMap[(*iter)->getIdentifier()] < capability)) cuobjdumpSectionMap[(*iter)->getIdentifier()] = capability; } } @@ -1489,7 +1489,7 @@ std::list pruneSectionList(std::list cuobj } } if(prunedList.empty()){ - printf("Error: No PTX sections found with sm capability that is lower than current forced maximum capability \n minimum ptx capability found = %u, maximum forced ptx capability = %u \n User might want to change either the forced maximum capability from gpgpusim configuration or update the compilation to generate the required PTX version",min_ptx_capability_found,forced_max_capability); + printf("Error: No PTX sections found with sm capability that is lower than current forced maximum capability \n minimum ptx capability found = %u, maximum forced ptx capability = %u \n User might want to change either the forced maximum capability from gpgpusim configuration or update the compilation to generate the required PTX version\n",min_ptx_capability_found,forced_max_capability); abort(); } return prunedList; @@ -1575,6 +1575,16 @@ void cuobjdumpParseBinary(unsigned int handle){ fatbin_registered[handle] = true; CUctx_st *context = GPGPUSim_Context(); + unsigned max_capability = 0; + for ( std::list::iterator iter = cuobjdumpSectionList.begin(); + iter != cuobjdumpSectionList.end(); + iter++){ + unsigned capability = (*iter)->getArch(); + if (capability > max_capability) max_capability = capability; + } + + if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); + std::string fname = fatbinmap[handle]; cuobjdumpPTXSection* ptx = findPTXSection(fname); @@ -1597,13 +1607,13 @@ void cuobjdumpParseBinary(unsigned int handle){ symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxplus_str, handle); printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); context->add_binary(symtab, handle); - gpgpu_ptxinfo_load_from_string( ptxcode, handle); + gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability ); delete[] ptxplus_str; } else { symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxcode, handle); printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); context->add_binary(symtab, handle); - gpgpu_ptxinfo_load_from_string( ptxcode, handle); + gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability ); } load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu()); load_constants(symtab,STATIC_ALLOC_LIMIT,context->get_device()->get_gpgpu()); @@ -1704,7 +1714,7 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) } else { symtab=gpgpu_ptx_sim_load_ptx_from_string(ptx,source_num); context->add_binary(symtab,fat_cubin_handle); - gpgpu_ptxinfo_load_from_string( ptx, source_num ); + gpgpu_ptxinfo_load_from_string( ptx, source_num, max_capability ); } source_num++; load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu()); diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index e293065..5a17ec3 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -182,7 +182,7 @@ symbol_table *gpgpu_ptx_sim_load_ptx_from_string( const char *p, unsigned source return symtab; } -void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num ) +void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version=20 ) { char fname[1024]; snprintf(fname,1024,"_ptx_XXXXXX"); @@ -216,7 +216,8 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num extra_flags[0]=0; #if CUDART_VERSION >= 3000 - snprintf(extra_flags,1024,"--gpu-name=sm_20"); + if (sm_version == 0) sm_version = 20; + snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); #endif snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", diff --git a/src/cuda-sim/ptx_loader.h b/src/cuda-sim/ptx_loader.h index cb02eda..e10db1c 100644 --- a/src/cuda-sim/ptx_loader.h +++ b/src/cuda-sim/ptx_loader.h @@ -32,7 +32,7 @@ extern bool g_override_embedded_ptx; class symbol_table *gpgpu_ptx_sim_load_ptx_from_string( const char *p, unsigned source_num ); -void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num ); +void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version ); char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptx_str, const std::string sass_str, const std::string elf_str); bool keep_intermediate_files(); -- cgit v1.3 From eafd8c0f7d4235b922e4ca8c8bb92ea5628d8011 Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 13 May 2016 15:21:27 -0700 Subject: changed gpgpu_ptxinfo_load_from_string definition for Ahmed --- src/cuda-sim/ptx_loader.cc | 2 +- src/cuda-sim/ptx_loader.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 5a17ec3..f7bf70e 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -182,7 +182,7 @@ symbol_table *gpgpu_ptx_sim_load_ptx_from_string( const char *p, unsigned source return symtab; } -void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version=20 ) +void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version ) { char fname[1024]; snprintf(fname,1024,"_ptx_XXXXXX"); diff --git a/src/cuda-sim/ptx_loader.h b/src/cuda-sim/ptx_loader.h index e10db1c..d3d0c92 100644 --- a/src/cuda-sim/ptx_loader.h +++ b/src/cuda-sim/ptx_loader.h @@ -32,7 +32,7 @@ extern bool g_override_embedded_ptx; class symbol_table *gpgpu_ptx_sim_load_ptx_from_string( const char *p, unsigned source_num ); -void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version ); +void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version=20 ); char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptx_str, const std::string sass_str, const std::string elf_str); bool keep_intermediate_files(); -- cgit v1.3 From 7dae3f76faa2742587a07ca01d87a55fab5598bb Mon Sep 17 00:00:00 2001 From: Ahmed ElTantawy Date: Sun, 15 May 2016 08:08:54 -0700 Subject: updating CHANGES --- CHANGES | 7 +++++-- libopencl/opencl_runtime_api.cc | 4 ++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/CHANGES b/CHANGES index 512993b..ce80cfd 100644 --- a/CHANGES +++ b/CHANGES @@ -5,10 +5,13 @@ Version 3.2.3+edits (development branch) versus 3.2.3 the two default cache sizes, 16KB/48KB with 32/64 sets. - Added support for named barriers. - Added support for bar.arrive and bar.red instructions. -- Initial support for CUDA 5.0,5.5 and 6.0 to get template running. +- Initial support for CUDA 5.0,5.5,6.0 and 7.5 to get basic sdk running (e.g., template, vectorAdd, ...) - Removed intersim2 svn repository files - Changed the makefile for cuobjdump_toptxplus,libcuda,intersim2 so that it outputs temporary files into the build directory - +- Bug fixes: + - Fixed a bug where sm_version was hard coded to sm_20. Now, it extracts the highest sm version that is lower than + the forced_max_capability configuration in GPGPUSim. + - Bug fixes: - Fixed bug #81, fix ordering of pushing branch entries to the stack - Fixed a bug where for each icache miss we also count a hit diff --git a/libopencl/opencl_runtime_api.cc b/libopencl/opencl_runtime_api.cc index 9da895d..020384f 100644 --- a/libopencl/opencl_runtime_api.cc +++ b/libopencl/opencl_runtime_api.cc @@ -268,7 +268,7 @@ cl_int _cl_kernel::bind_args( gpgpu_ptx_sim_arg_list_t &arg_list ) if( i->first != k ) return CL_INVALID_KERNEL_ARGS; arg_info arg = i->second; - gpgpu_ptx_sim_arg param( arg.m_arg_value, arg.m_arg_size, 0 ); + gpgpu_ptx_sim_arg param( arg.m_arg_value, arg.m_arg_size, 0); arg_list.push_front( param ); k++; } @@ -575,7 +575,7 @@ void _cl_program::Build(const char *options) } info.m_asm = tmp; info.m_symtab = gpgpu_ptx_sim_load_ptx_from_string( tmp, source_num ); - gpgpu_ptxinfo_load_from_string( tmp, source_num ); + gpgpu_ptxinfo_load_from_string( tmp, source_num); free(tmp); } printf("GPGPU-Sim OpenCL API: finished compiling OpenCL kernels.\n"); -- cgit v1.3 From 4ac4dafdb8b0a90168630ed53b1a2c3166e79a73 Mon Sep 17 00:00:00 2001 From: Ahmed ElTantawy Date: Sun, 15 May 2016 10:26:48 -0700 Subject: Crediting lonestartGPU in the CHANGES for their help in CUDA 5.5 support --- CHANGES | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CHANGES b/CHANGES index ce80cfd..9e6d112 100644 --- a/CHANGES +++ b/CHANGES @@ -5,7 +5,7 @@ Version 3.2.3+edits (development branch) versus 3.2.3 the two default cache sizes, 16KB/48KB with 32/64 sets. - Added support for named barriers. - Added support for bar.arrive and bar.red instructions. -- Initial support for CUDA 5.0,5.5,6.0 and 7.5 to get basic sdk running (e.g., template, vectorAdd, ...) +- Initial support for CUDA 5.0,5.5,6.0 and 7.5 to get basic sdk running (e.g., template, vectorAdd, ...). The issues required for CUDA 5.5 support were identified by the loneStarGPU group at The University of Texas at Austin - Removed intersim2 svn repository files - Changed the makefile for cuobjdump_toptxplus,libcuda,intersim2 so that it outputs temporary files into the build directory - Bug fixes: -- cgit v1.3 From a625477b025d21332368a5c31a9b779c6bb0351f Mon Sep 17 00:00:00 2001 From: Ahmed ElTantawy Date: Sun, 15 May 2016 10:40:37 -0700 Subject: fixing the credits --- CHANGES | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CHANGES b/CHANGES index 9e6d112..effc345 100644 --- a/CHANGES +++ b/CHANGES @@ -5,7 +5,7 @@ Version 3.2.3+edits (development branch) versus 3.2.3 the two default cache sizes, 16KB/48KB with 32/64 sets. - Added support for named barriers. - Added support for bar.arrive and bar.red instructions. -- Initial support for CUDA 5.0,5.5,6.0 and 7.5 to get basic sdk running (e.g., template, vectorAdd, ...). The issues required for CUDA 5.5 support were identified by the loneStarGPU group at The University of Texas at Austin +- Initial support for CUDA 5.0,5.5,6.0 and 7.5 to get basic sdk running (e.g., template, vectorAdd, ...). The issues required for CUDA 5.5 support were identified by the loneStarGPU group at The University of Texas at Austin and Texas State University. - Removed intersim2 svn repository files - Changed the makefile for cuobjdump_toptxplus,libcuda,intersim2 so that it outputs temporary files into the build directory - Bug fixes: -- cgit v1.3 From 041192e93f61bf27c7f7928d87afe5623cc08728 Mon Sep 17 00:00:00 2001 From: speverel Date: Wed, 1 Jun 2016 11:26:47 -0700 Subject: Added GTX750Ti config files. Also modified shader.h to support larger number of warps per CTA (64), which is necessary for Maxwell boards like the GTX750Ti. --- src/gpgpu-sim/shader.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 1aa468b..fe00770 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -267,7 +267,7 @@ private: inline unsigned hw_tid_from_wid(unsigned wid, unsigned warp_size, unsigned i){return wid * warp_size + i;}; inline unsigned wid_from_hw_tid(unsigned tid, unsigned warp_size){return tid/warp_size;}; -const unsigned WARP_PER_CTA_MAX = 48; +const unsigned WARP_PER_CTA_MAX = 64; typedef std::bitset warp_set_t; int register_bank(int regnum, int wid, unsigned num_banks, unsigned bank_warp_shift); -- cgit v1.3 From 88e1bcdaa3271fb79c999389c82733736154e48a Mon Sep 17 00:00:00 2001 From: speverel Date: Wed, 1 Jun 2016 11:33:01 -0700 Subject: Added new GTX750Ti config files. --- configs/GeForceGTX750Ti/config_fermi_islip.icnt | 70 +++ configs/GeForceGTX750Ti/gpgpusim.config | 128 ++++++ configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml | 538 ++++++++++++++++++++++++ 3 files changed, 736 insertions(+) create mode 100644 configs/GeForceGTX750Ti/config_fermi_islip.icnt create mode 100644 configs/GeForceGTX750Ti/gpgpusim.config create mode 100755 configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml diff --git a/configs/GeForceGTX750Ti/config_fermi_islip.icnt b/configs/GeForceGTX750Ti/config_fermi_islip.icnt new file mode 100644 index 0000000..069ca02 --- /dev/null +++ b/configs/GeForceGTX750Ti/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 7; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config new file mode 100644 index 0000000..afd3825 --- /dev/null +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -0,0 +1,128 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 20 + + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 5 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 2 +-gpgpu_n_sub_partition_per_mchannel 1 + +# Maxwell clock domains +#-gpgpu_clock_domains ::: +# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number. +-gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 2,1,1,2,1,1,2 +-gpgpu_num_sp_units 8 +-gpgpu_num_sfu_units 32 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 6,12,13,13,210 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 6,12,6,6,374 +-ptx_opcode_initiation_fp 1,1,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,16,8,8,130 + +-gpgpu_cache:dl1 none +# 32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_shmem_size 65536 + +# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected +#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 +#-gpgpu_shmem_size 16384 + +# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache +-gpgpu_cache:dl2 1024:128:8,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 + +-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 16:128:32,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_num_reg_banks 16 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 150 +-dram_latency 130 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 300 + +# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 32 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS + +# GDDR5 timing from hynix H5GQ1H24AFR +# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# Maxwell has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml b/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml new file mode 100755 index 0000000..304e0fd --- /dev/null +++ b/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.3 From 4971546a72dff7626bf7ac4eee3d5485b9d380b9 Mon Sep 17 00:00:00 2001 From: Scott Peverelle Date: Tue, 24 May 2016 09:49:36 -0800 Subject: Branch of GTX480 configs for Maxwell board [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21797] --- CHANGES | 1 + configs/GeForceGTX750Ti/gpgpusim.config | 133 ++++++ configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml | 538 +++++++++++++++++++++++++ 3 files changed, 672 insertions(+) create mode 100644 configs/GeForceGTX750Ti/gpgpusim.config create mode 100755 configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml diff --git a/CHANGES b/CHANGES index effc345..054ec9a 100644 --- a/CHANGES +++ b/CHANGES @@ -16,6 +16,7 @@ Version 3.2.3+edits (development branch) versus 3.2.3 - Fixed bug #81, fix ordering of pushing branch entries to the stack - Fixed a bug where for each icache miss we also count a hit - Fixed bug #88, Ejection buffer and Boundary buffer in Intersim2 initialization with a wrong node number +- Branching config file for GeForceGTX750Ti Version 3.2.3 versus 3.2.2 - Bug fixes: diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config new file mode 100644 index 0000000..436cb41 --- /dev/null +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -0,0 +1,133 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 20 + + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 15 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 6 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Fermi clock domains +#-gpgpu_clock_domains ::: +# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided +# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 +-gpgpu_clock_domains 700.0:700.0:700.0:924.0 + +# shader core pipeline config +-gpgpu_shader_registers 32768 + +# This implies a maximum of 48 warps/SM +-gpgpu_shader_core_pipeline 1536:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 2,1,1,2,1,1,2 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,1,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,16,8,8,130 + + +# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_shmem_size 49152 + +# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected +#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 +#-gpgpu_shmem_size 16384 + +# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache +-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 + +-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_num_reg_banks 16 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +-gpgpu_max_insn_issue_per_warp 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 116 + +# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS + +# GDDR5 timing from hynix H5GQ1H24AFR +# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml b/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml new file mode 100755 index 0000000..304e0fd --- /dev/null +++ b/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.3 From 104e6d5f802846f8758d35fa9123f6adc1a2470b Mon Sep 17 00:00:00 2001 From: Scott Peverelle Date: Tue, 24 May 2016 10:34:22 -0800 Subject: GeForceGTX750Ti correlation setup. Modified config file to reflect GTX750Ti architecture. Modified shader.h to allow for larger CTA per warp, to accomodate Maxwell specs. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21798] --- CHANGES | 9 ++-- configs/GeForceGTX750Ti/config_fermi_islip.icnt | 70 +++++++++++++++++++++++++ configs/GeForceGTX750Ti/gpgpusim.config | 35 +++++++------ src/gpgpu-sim/shader.h | 4 +- 4 files changed, 94 insertions(+), 24 deletions(-) create mode 100644 configs/GeForceGTX750Ti/config_fermi_islip.icnt diff --git a/CHANGES b/CHANGES index 054ec9a..f58d10d 100644 --- a/CHANGES +++ b/CHANGES @@ -8,15 +8,14 @@ Version 3.2.3+edits (development branch) versus 3.2.3 - Initial support for CUDA 5.0,5.5,6.0 and 7.5 to get basic sdk running (e.g., template, vectorAdd, ...). The issues required for CUDA 5.5 support were identified by the loneStarGPU group at The University of Texas at Austin and Texas State University. - Removed intersim2 svn repository files - Changed the makefile for cuobjdump_toptxplus,libcuda,intersim2 so that it outputs temporary files into the build directory -- Bug fixes: - - Fixed a bug where sm_version was hard coded to sm_20. Now, it extracts the highest sm version that is lower than - the forced_max_capability configuration in GPGPUSim. - +- Branching config file for GeForceGTX750Ti +- Branching correlation script for GeForceGTX750Ti. Modified config to fit Maxwell architecture. Modified shader.h to allow larger CTA per warp. - Bug fixes: - Fixed bug #81, fix ordering of pushing branch entries to the stack - Fixed a bug where for each icache miss we also count a hit - Fixed bug #88, Ejection buffer and Boundary buffer in Intersim2 initialization with a wrong node number -- Branching config file for GeForceGTX750Ti + - Fixed a bug where sm_version was hard coded to sm_20. Now, it extracts the highest sm version that is lower than + the forced_max_capability configuration in GPGPUSim. Version 3.2.3 versus 3.2.2 - Bug fixes: diff --git a/configs/GeForceGTX750Ti/config_fermi_islip.icnt b/configs/GeForceGTX750Ti/config_fermi_islip.icnt new file mode 100644 index 0000000..7820e4e --- /dev/null +++ b/configs/GeForceGTX750Ti/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 27; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index 436cb41..5b5ee90 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -9,22 +9,22 @@ -gpgpu_ptx_save_converted_ptxplus 0 # high level architecture configuration --gpgpu_n_clusters 15 +-gpgpu_n_clusters 5 -gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 6 --gpgpu_n_sub_partition_per_mchannel 2 +-gpgpu_n_mem 2 +-gpgpu_n_sub_partition_per_mchannel 1 # Fermi clock domains #-gpgpu_clock_domains ::: # In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided # by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 700.0:700.0:700.0:924.0 +-gpgpu_clock_domains 1080.0:1080.0:1080.0:1335.0 # shader core pipeline config --gpgpu_shader_registers 32768 +-gpgpu_shader_registers 65536 # This implies a maximum of 48 warps/SM --gpgpu_shader_core_pipeline 1536:32 +-gpgpu_shader_core_pipeline 2048:32 -gpgpu_shader_cta 8 -gpgpu_simd_model 1 @@ -32,13 +32,13 @@ # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB -gpgpu_pipeline_widths 2,1,1,2,1,1,2 -gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 1 +-gpgpu_num_sfu_units 8 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_latency_int 6,12,13,13,210 -ptx_opcode_initiation_int 1,2,2,1,8 --ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_latency_fp 6,12,6,6,374 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,16,8,8,130 @@ -49,14 +49,15 @@ # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. -gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 --gpgpu_shmem_size 49152 +-gpgpu_shmem_size 65536 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected #-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 #-gpgpu_shmem_size 16384 # 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache --gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32 +# Ignore above. Maxwell has 2MB of L2 cache. Configuration is unknown, so making a guess. +-gpgpu_cache:dl2 256:128:16,L:B:m:W:L,A:32:4,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 @@ -82,8 +83,8 @@ -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 120 --dram_latency 100 +-rop_latency 80 +-dram_latency 60 # dram model config -gpgpu_dram_scheduler 1 @@ -96,7 +97,7 @@ -gpgpu_dram_return_queue_size 116 # for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition --gpgpu_n_mem_per_ctrlr 2 +-gpgpu_n_mem_per_ctrlr 4 -gpgpu_dram_buswidth 4 -gpgpu_dram_burst_length 8 -dram_data_command_freq_ratio 4 # GDDR5 is QDR @@ -108,8 +109,8 @@ -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 2 +# Maxwell has four schedulers per core +-gpgpu_num_sched_per_core 4 # Two Level Scheduler with active and pending pools #-gpgpu_scheduler two_level_active:6:0:1 # Loose round robbin scheduler @@ -124,7 +125,7 @@ -visualizer_enabled 0 # power model configs --power_simulation_enabled 1 +-power_simulation_enabled 0 -gpuwattch_xml_file gpuwattch_gtx480.xml # tracing functionality diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 1aa468b..38d09e9 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -267,7 +267,7 @@ private: inline unsigned hw_tid_from_wid(unsigned wid, unsigned warp_size, unsigned i){return wid * warp_size + i;}; inline unsigned wid_from_hw_tid(unsigned tid, unsigned warp_size){return tid/warp_size;}; -const unsigned WARP_PER_CTA_MAX = 48; +const unsigned WARP_PER_CTA_MAX = 64; typedef std::bitset warp_set_t; int register_bank(int regnum, int wid, unsigned num_banks, unsigned bank_warp_shift); @@ -1331,7 +1331,7 @@ struct shader_core_config : public core_config struct shader_core_stats_pod { - void* shader_core_stats_pod_start[0]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure + void* shader_core_stats_pod_start[]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure unsigned long long *shader_cycles; unsigned *m_num_sim_insn; // number of scalar thread instructions committed by this shader core unsigned *m_num_sim_winsn; // number of warp instructions committed by this shader core -- cgit v1.3 From 5c62af183b1a7889e7f59725848fa592ca7cbcef Mon Sep 17 00:00:00 2001 From: Scott Peverelle Date: Tue, 24 May 2016 15:56:09 -0800 Subject: Modified config files to better represent Maxwell architecture; specifically, changed the number of clusters, controllers, and interconnect nodes. Also modified parse_and_compare to fix an occasional division by zero bug. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21812] --- CHANGES | 1 + configs/GeForceGTX750Ti/config_fermi_islip.icnt | 2 +- configs/GeForceGTX750Ti/gpgpusim.config | 29 ++++++++++++------------- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/CHANGES b/CHANGES index f58d10d..e3b3177 100644 --- a/CHANGES +++ b/CHANGES @@ -10,6 +10,7 @@ Version 3.2.3+edits (development branch) versus 3.2.3 - Changed the makefile for cuobjdump_toptxplus,libcuda,intersim2 so that it outputs temporary files into the build directory - Branching config file for GeForceGTX750Ti - Branching correlation script for GeForceGTX750Ti. Modified config to fit Maxwell architecture. Modified shader.h to allow larger CTA per warp. +- Additional changes to config file to reflect Maxwell uarch. - Bug fixes: - Fixed bug #81, fix ordering of pushing branch entries to the stack - Fixed a bug where for each icache miss we also count a hit diff --git a/configs/GeForceGTX750Ti/config_fermi_islip.icnt b/configs/GeForceGTX750Ti/config_fermi_islip.icnt index 7820e4e..069ca02 100644 --- a/configs/GeForceGTX750Ti/config_fermi_islip.icnt +++ b/configs/GeForceGTX750Ti/config_fermi_islip.icnt @@ -7,7 +7,7 @@ network_count = 2; // Topology topology = fly; -k = 27; +k = 7; n = 1; // Routing diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index 5b5ee90..0e69098 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -12,18 +12,18 @@ -gpgpu_n_clusters 5 -gpgpu_n_cores_per_cluster 1 -gpgpu_n_mem 2 --gpgpu_n_sub_partition_per_mchannel 1 +-gpgpu_n_sub_partition_per_mchannel 1 # Fermi clock domains #-gpgpu_clock_domains ::: # In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided # by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 1080.0:1080.0:1080.0:1335.0 +-gpgpu_clock_domains 1080.0:1080.0:1080.0:924.0 # shader core pipeline config --gpgpu_shader_registers 65536 +-gpgpu_shader_registers 32768 -# This implies a maximum of 48 warps/SM +# This implies a maximum of 64 warps/SM -gpgpu_shader_core_pipeline 2048:32 -gpgpu_shader_cta 8 -gpgpu_simd_model 1 @@ -32,13 +32,13 @@ # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB -gpgpu_pipeline_widths 2,1,1,2,1,1,2 -gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 8 +-gpgpu_num_sfu_units 1 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 6,12,13,13,210 +-ptx_opcode_latency_int 4,13,4,5,145 -ptx_opcode_initiation_int 1,2,2,1,8 --ptx_opcode_latency_fp 6,12,6,6,374 +-ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,16,8,8,130 @@ -49,15 +49,14 @@ # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. -gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 --gpgpu_shmem_size 65536 +-gpgpu_shmem_size 49152 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected #-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 #-gpgpu_shmem_size 16384 # 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache -# Ignore above. Maxwell has 2MB of L2 cache. Configuration is unknown, so making a guess. --gpgpu_cache:dl2 256:128:16,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 @@ -83,8 +82,8 @@ -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 80 --dram_latency 60 +-rop_latency 120 +-dram_latency 100 # dram model config -gpgpu_dram_scheduler 1 @@ -97,7 +96,7 @@ -gpgpu_dram_return_queue_size 116 # for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition --gpgpu_n_mem_per_ctrlr 4 +-gpgpu_n_mem_per_ctrlr 2 -gpgpu_dram_buswidth 4 -gpgpu_dram_burst_length 8 -dram_data_command_freq_ratio 4 # GDDR5 is QDR @@ -109,8 +108,8 @@ -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" -# Maxwell has four schedulers per core --gpgpu_num_sched_per_core 4 +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 # Two Level Scheduler with active and pending pools #-gpgpu_scheduler two_level_active:6:0:1 # Loose round robbin scheduler -- cgit v1.3 From fb871c36a565bff2e25f457b8e7a0d5a6ffc4b7f Mon Sep 17 00:00:00 2001 From: Scott Peverelle Date: Wed, 25 May 2016 11:25:09 -0800 Subject: Tweaked Maxwell config to improve correspondence in a number of areas; clock speed, DRAM bus width, L2 cache size etc. Adjusted parse_and_compare to match new clock frequency as per config file. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21818] --- configs/GeForceGTX750Ti/gpgpusim.config | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index 0e69098..9a3d73b 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -18,10 +18,10 @@ #-gpgpu_clock_domains ::: # In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided # by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 1080.0:1080.0:1080.0:924.0 +-gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0 # shader core pipeline config --gpgpu_shader_registers 32768 +-gpgpu_shader_registers 65536 # This implies a maximum of 64 warps/SM -gpgpu_shader_core_pipeline 2048:32 @@ -32,31 +32,30 @@ # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB -gpgpu_pipeline_widths 2,1,1,2,1,1,2 -gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 1 +-gpgpu_num_sfu_units 32 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,2,2,1,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_int 6,12,13,13,210 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 6,12,6,6,374 +-ptx_opcode_initiation_fp 1,1,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,16,8,8,130 - # In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. -gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 --gpgpu_shmem_size 49152 +-gpgpu_shmem_size 65536 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected #-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 #-gpgpu_shmem_size 16384 -# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache --gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32 +# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache +-gpgpu_cache:dl2 1024:128:8,L:B:m:W:L,A:32:4,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 @@ -97,7 +96,7 @@ # for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition -gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 4 +-gpgpu_dram_buswidth 32 -gpgpu_dram_burst_length 8 -dram_data_command_freq_ratio 4 # GDDR5 is QDR -gpgpu_mem_address_mask 1 @@ -108,8 +107,8 @@ -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 2 +# Maxwell has four schedulers per core +-gpgpu_num_sched_per_core 4 # Two Level Scheduler with active and pending pools #-gpgpu_scheduler two_level_active:6:0:1 # Loose round robbin scheduler -- cgit v1.3 From 65577fdc18e5d9b1d93054a644029ab20c598440 Mon Sep 17 00:00:00 2001 From: Scott Peverelle Date: Thu, 26 May 2016 15:28:47 -0800 Subject: Made additional improvements to Maxwell correlation in config file such as merger of L1/Texture cache. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21837] --- configs/GeForceGTX750Ti/gpgpusim.config | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index 9a3d73b..afd3825 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -14,10 +14,9 @@ -gpgpu_n_mem 2 -gpgpu_n_sub_partition_per_mchannel 1 -# Fermi clock domains +# Maxwell clock domains #-gpgpu_clock_domains ::: -# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided -# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 +# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number. -gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0 # shader core pipeline config @@ -31,7 +30,7 @@ # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB -gpgpu_pipeline_widths 2,1,1,2,1,1,2 --gpgpu_num_sp_units 2 +-gpgpu_num_sp_units 8 -gpgpu_num_sfu_units 32 # Instruction latencies and initiation intervals @@ -43,11 +42,8 @@ -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,16,8,8,130 -# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. --gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_cache:dl1 none +# 32:128:4,L:L:m:N:H,A:32:8,8 -gpgpu_shmem_size 65536 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected @@ -59,7 +55,7 @@ -gpgpu_cache:dl2_texture_only 0 -gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_tex_cache:l1 16:128:32,L:R:m:N:L,F:128:4,128:2 -gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 # enable operand collector @@ -74,15 +70,15 @@ -gpgpu_shmem_limited_broadcast 0 -gpgpu_shmem_warp_parts 1 --gpgpu_max_insn_issue_per_warp 1 +-gpgpu_max_insn_issue_per_warp 2 # interconnection -network_mode 1 -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 120 --dram_latency 100 +-rop_latency 150 +-dram_latency 130 # dram model config -gpgpu_dram_scheduler 1 @@ -92,9 +88,9 @@ # the minimum DRAM latency (100 core cycles). I.e. # Total buffer space required = 100 x 924MHz / 700MHz = 132 -gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 116 +-gpgpu_dram_return_queue_size 300 -# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition +# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition -gpgpu_n_mem_per_ctrlr 2 -gpgpu_dram_buswidth 32 -gpgpu_dram_burst_length 8 -- cgit v1.3 From 4cbb9730252dadcde68322cedbe004676420e9e6 Mon Sep 17 00:00:00 2001 From: speverel Date: Thu, 2 Jun 2016 11:28:15 -0700 Subject: Added handling of .cc option for arithmetic instructions. NOTE: Only made changes to parse instructions. Carry functionality NOT fully implemented; .cc instructions function like their unmodified ueqivelents. Also modified GTX750Ti config to model L1 data cache as simply not being used for global loads (instead of not existing at all). Changed ptxinfo parsing to avoid crashing when info includes texture information. --- configs/GeForceGTX750Ti/gpgpusim.config | 4 ++-- libcuda/cuda_runtime_api.cc | 8 +++++++- src/cuda-sim/cuda-sim.cc | 2 +- src/cuda-sim/instructions.cc | 2 +- src/cuda-sim/opcodes.def | 2 +- src/cuda-sim/ptx.l | 3 ++- src/cuda-sim/ptx.y | 2 ++ src/cuda-sim/ptx_ir.cc | 2 ++ src/cuda-sim/ptxinfo.l | 1 + src/cuda-sim/ptxinfo.y | 2 ++ 10 files changed, 21 insertions(+), 7 deletions(-) diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index afd3825..be3ae3c 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -42,8 +42,8 @@ -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,16,8,8,130 --gpgpu_cache:dl1 none -# 32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 +-gmem_skip_L1D 1 -gpgpu_shmem_size 65536 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 910bebd..e2626d2 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -109,6 +109,7 @@ #include #include #include +#include #include #include #ifdef OPENGL_SUPPORT @@ -1816,10 +1817,15 @@ void __cudaRegisterTexture( int ext ) //passes in a newly created textureReference { + std::string devStr (deviceName); + #if (CUDART_VERSION > 4020) + if (devStr.size() > 2 && devStr.data()[0] == ':' && devStr.data()[1] == ':') + devStr = devStr.replace(0, 2, ""); + #endif CUctx_st *context = GPGPUSim_Context(); gpgpu_t *gpu = context->get_device()->get_gpgpu(); printf("GPGPU-Sim PTX: in __cudaRegisterTexture:\n"); - gpu->gpgpu_ptx_sim_bindNameToTexture(deviceName, hostVar, dim, norm, ext); + gpu->gpgpu_ptx_sim_bindNameToTexture(devStr.data(), hostVar, dim, norm, ext); printf("GPGPU-Sim PTX: int dim = %d\n", dim); printf("GPGPU-Sim PTX: int norm = %d\n", norm); printf("GPGPU-Sim PTX: int ext = %d\n", ext); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 715be98..15417d1 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -719,7 +719,7 @@ void ptx_instruction::set_opcode_and_latency() break; } break; - case MAD_OP: case MADP_OP: + case MAD_OP: case MADC_OP: //MAD latency switch(get_type()){ case F32_TYPE: diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index cf7f04a..4dd5ed8 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2421,7 +2421,7 @@ void mad_impl( const ptx_instruction *pI, ptx_thread_info *thread ) mad_def(pI, thread, false); } -void madp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +void madc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { mad_def(pI, thread, true); } diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 7aaa14f..874acc7 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -69,7 +69,7 @@ OP_DEF(LDU_OP,ldu_impl,"ldu",1,5) OP_DEF(LG2_OP,lg2_impl,"lg2",1,4) OP_DEF(MAD24_OP,mad24_impl,"mad24",1,2) OP_DEF(MAD_OP,mad_impl,"mad",1,2) -OP_DEF(MADP_OP,madp_impl,"madp",1,2) +OP_DEF(MADC_OP,madc_impl,"madc",1,2) OP_DEF(MAX_OP,max_impl,"max",1,1) OP_DEF(MEMBAR_OP,membar_impl,"membar",1,3) OP_DEF(MIN_OP,min_impl,"min",1,1) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index dfed936..95ab74c 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -86,7 +86,7 @@ ldu TC; ptx_lval.int_value = LDU_OP; return OPCODE; lg2 TC; ptx_lval.int_value = LG2_OP; return OPCODE; mad24 TC; ptx_lval.int_value = MAD24_OP; return OPCODE; mad TC; ptx_lval.int_value = MAD_OP; return OPCODE; -madp TC; ptx_lval.int_value = MADP_OP; return OPCODE; +madc TC; ptx_lval.int_value = MADC_OP; return OPCODE; max TC; ptx_lval.int_value = MAX_OP; return OPCODE; membar TC; ptx_lval.int_value = MEMBAR_OP; return OPCODE; min TC; ptx_lval.int_value = MIN_OP; return OPCODE; @@ -249,6 +249,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.v4 TC; return V4_TYPE; \.half TC; return HALF_OPTION; /* ptxplus */ +\.cc TC; return EXTP_OPTION; /* extended precision option */ \.equ TC; return EQU_OPTION; \.neu TC; return NEU_OPTION; diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 79faddf..82abcbb 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -103,6 +103,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token COMMA %token PRED %token HALF_OPTION +%token EXTP_OPTION %token EQ_OPTION %token NE_OPTION %token LT_OPTION @@ -438,6 +439,7 @@ option: type_spec | atomic_operation_spec ; | TO_OPTION { add_option(TO_OPTION); } | HALF_OPTION { add_option(HALF_OPTION); } + | EXTP_OPTION { add_option(EXTP_OPTION); } | CA_OPTION { add_option(CA_OPTION); } | CG_OPTION { add_option(CG_OPTION); } | CS_OPTION { add_option(CS_OPTION); } diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 751b3f4..8f9c3d2 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1167,6 +1167,8 @@ ptx_instruction::ptx_instruction( int opcode, case HALF_OPTION: m_inst_size = 4; // bytes break; + case EXTP_OPTION: + break; default: assert(0); break; diff --git a/src/cuda-sim/ptxinfo.l b/src/cuda-sim/ptxinfo.l index 99ee1fc..f9b6846 100644 --- a/src/cuda-sim/ptxinfo.l +++ b/src/cuda-sim/ptxinfo.l @@ -59,6 +59,7 @@ unsigned ptxinfo_col = 0; "gmem" TC; return GMEM; "line" TC; return LINE; "for" TC; return FOR; +"textures" TC; return TEXTURES; [_A-Za-z$%][_0-9A-Za-z$]* TC; ptxinfo_lval.string_value = strdup(yytext); return IDENTIFIER; [-]{0,1}[0-9]+ TC; ptxinfo_lval.int_value = atoi(yytext); return INT_OPERAND; diff --git a/src/cuda-sim/ptxinfo.y b/src/cuda-sim/ptxinfo.y index 294412d..faa33eb 100644 --- a/src/cuda-sim/ptxinfo.y +++ b/src/cuda-sim/ptxinfo.y @@ -54,6 +54,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token LINE %token WARNING %token FOR +%token TEXTURES %{ #include @@ -104,6 +105,7 @@ info: USED INT_OPERAND REGS { ptxinfo_regs($2); } | INT_OPERAND BYTES SMEM { ptxinfo_smem($1,0); } | INT_OPERAND BYTES CMEM { ptxinfo_cmem($1,0); } | INT_OPERAND REGS { ptxinfo_regs($1); } + | INT_OPERAND TEXTURES {} ; tuple: INT_OPERAND PLUS INT_OPERAND BYTES { g_declared=$1; g_system=$3; } -- cgit v1.3 From 46aad91327a265c2fea2cfe629cc38eadb629200 Mon Sep 17 00:00:00 2001 From: speverel Date: Thu, 2 Jun 2016 11:28:15 -0700 Subject: Added handling of .cc option for arithmetic instructions. NOTE: Only made changes to parse instructions. Carry functionality NOT fully implemented; .cc instructions function like their unmodified ueqivelents. Also modified GTX750Ti config to model L1 data cache as simply not being used for global loads (instead of not existing at all). Changed ptxinfo parsing to avoid crashing when info includes texture information. --- configs/GeForceGTX750Ti/gpgpusim.config | 4 ++-- libcuda/cuda_runtime_api.cc | 8 +++++++- src/cuda-sim/cuda-sim.cc | 2 +- src/cuda-sim/instructions.cc | 2 +- src/cuda-sim/opcodes.def | 2 +- src/cuda-sim/ptx.l | 3 ++- src/cuda-sim/ptx.y | 2 ++ src/cuda-sim/ptx_ir.cc | 2 ++ src/cuda-sim/ptxinfo.l | 1 + src/cuda-sim/ptxinfo.y | 2 ++ 10 files changed, 21 insertions(+), 7 deletions(-) diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index afd3825..be3ae3c 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -42,8 +42,8 @@ -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,16,8,8,130 --gpgpu_cache:dl1 none -# 32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 +-gmem_skip_L1D 1 -gpgpu_shmem_size 65536 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 910bebd..e2626d2 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -109,6 +109,7 @@ #include #include #include +#include #include #include #ifdef OPENGL_SUPPORT @@ -1816,10 +1817,15 @@ void __cudaRegisterTexture( int ext ) //passes in a newly created textureReference { + std::string devStr (deviceName); + #if (CUDART_VERSION > 4020) + if (devStr.size() > 2 && devStr.data()[0] == ':' && devStr.data()[1] == ':') + devStr = devStr.replace(0, 2, ""); + #endif CUctx_st *context = GPGPUSim_Context(); gpgpu_t *gpu = context->get_device()->get_gpgpu(); printf("GPGPU-Sim PTX: in __cudaRegisterTexture:\n"); - gpu->gpgpu_ptx_sim_bindNameToTexture(deviceName, hostVar, dim, norm, ext); + gpu->gpgpu_ptx_sim_bindNameToTexture(devStr.data(), hostVar, dim, norm, ext); printf("GPGPU-Sim PTX: int dim = %d\n", dim); printf("GPGPU-Sim PTX: int norm = %d\n", norm); printf("GPGPU-Sim PTX: int ext = %d\n", ext); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 715be98..15417d1 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -719,7 +719,7 @@ void ptx_instruction::set_opcode_and_latency() break; } break; - case MAD_OP: case MADP_OP: + case MAD_OP: case MADC_OP: //MAD latency switch(get_type()){ case F32_TYPE: diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index cf7f04a..4dd5ed8 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2421,7 +2421,7 @@ void mad_impl( const ptx_instruction *pI, ptx_thread_info *thread ) mad_def(pI, thread, false); } -void madp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +void madc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { mad_def(pI, thread, true); } diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 7aaa14f..874acc7 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -69,7 +69,7 @@ OP_DEF(LDU_OP,ldu_impl,"ldu",1,5) OP_DEF(LG2_OP,lg2_impl,"lg2",1,4) OP_DEF(MAD24_OP,mad24_impl,"mad24",1,2) OP_DEF(MAD_OP,mad_impl,"mad",1,2) -OP_DEF(MADP_OP,madp_impl,"madp",1,2) +OP_DEF(MADC_OP,madc_impl,"madc",1,2) OP_DEF(MAX_OP,max_impl,"max",1,1) OP_DEF(MEMBAR_OP,membar_impl,"membar",1,3) OP_DEF(MIN_OP,min_impl,"min",1,1) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index dfed936..95ab74c 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -86,7 +86,7 @@ ldu TC; ptx_lval.int_value = LDU_OP; return OPCODE; lg2 TC; ptx_lval.int_value = LG2_OP; return OPCODE; mad24 TC; ptx_lval.int_value = MAD24_OP; return OPCODE; mad TC; ptx_lval.int_value = MAD_OP; return OPCODE; -madp TC; ptx_lval.int_value = MADP_OP; return OPCODE; +madc TC; ptx_lval.int_value = MADC_OP; return OPCODE; max TC; ptx_lval.int_value = MAX_OP; return OPCODE; membar TC; ptx_lval.int_value = MEMBAR_OP; return OPCODE; min TC; ptx_lval.int_value = MIN_OP; return OPCODE; @@ -249,6 +249,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.v4 TC; return V4_TYPE; \.half TC; return HALF_OPTION; /* ptxplus */ +\.cc TC; return EXTP_OPTION; /* extended precision option */ \.equ TC; return EQU_OPTION; \.neu TC; return NEU_OPTION; diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 79faddf..82abcbb 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -103,6 +103,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token COMMA %token PRED %token HALF_OPTION +%token EXTP_OPTION %token EQ_OPTION %token NE_OPTION %token LT_OPTION @@ -438,6 +439,7 @@ option: type_spec | atomic_operation_spec ; | TO_OPTION { add_option(TO_OPTION); } | HALF_OPTION { add_option(HALF_OPTION); } + | EXTP_OPTION { add_option(EXTP_OPTION); } | CA_OPTION { add_option(CA_OPTION); } | CG_OPTION { add_option(CG_OPTION); } | CS_OPTION { add_option(CS_OPTION); } diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 751b3f4..8f9c3d2 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1167,6 +1167,8 @@ ptx_instruction::ptx_instruction( int opcode, case HALF_OPTION: m_inst_size = 4; // bytes break; + case EXTP_OPTION: + break; default: assert(0); break; diff --git a/src/cuda-sim/ptxinfo.l b/src/cuda-sim/ptxinfo.l index 99ee1fc..f9b6846 100644 --- a/src/cuda-sim/ptxinfo.l +++ b/src/cuda-sim/ptxinfo.l @@ -59,6 +59,7 @@ unsigned ptxinfo_col = 0; "gmem" TC; return GMEM; "line" TC; return LINE; "for" TC; return FOR; +"textures" TC; return TEXTURES; [_A-Za-z$%][_0-9A-Za-z$]* TC; ptxinfo_lval.string_value = strdup(yytext); return IDENTIFIER; [-]{0,1}[0-9]+ TC; ptxinfo_lval.int_value = atoi(yytext); return INT_OPERAND; diff --git a/src/cuda-sim/ptxinfo.y b/src/cuda-sim/ptxinfo.y index 294412d..faa33eb 100644 --- a/src/cuda-sim/ptxinfo.y +++ b/src/cuda-sim/ptxinfo.y @@ -54,6 +54,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token LINE %token WARNING %token FOR +%token TEXTURES %{ #include @@ -104,6 +105,7 @@ info: USED INT_OPERAND REGS { ptxinfo_regs($2); } | INT_OPERAND BYTES SMEM { ptxinfo_smem($1,0); } | INT_OPERAND BYTES CMEM { ptxinfo_cmem($1,0); } | INT_OPERAND REGS { ptxinfo_regs($1); } + | INT_OPERAND TEXTURES {} ; tuple: INT_OPERAND PLUS INT_OPERAND BYTES { g_declared=$1; g_system=$3; } -- cgit v1.3 From 068e34728a0706cd8671b816eea466491ab2db06 Mon Sep 17 00:00:00 2001 From: speverel Date: Thu, 2 Jun 2016 13:29:46 -0700 Subject: Updated parser and config file to support compute versions up to 5.2. Full support is NOT claimed; however, it has been tested to work on a number of CUDA version 7.5 benchmarks such as matrix multiply and simpleMultiGPU. --- configs/GeForceGTX750Ti/gpgpusim.config | 2 +- src/cuda-sim/ptx.l | 1 + src/cuda-sim/ptx.y | 2 ++ 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index be3ae3c..7920763 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -1,7 +1,7 @@ # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 20 +-gpgpu_ptx_force_max_capability 52 # SASS execution (only supported with CUDA >= 4.0) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 95ab74c..66ff48f 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -181,6 +181,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.version TC; return VERSION_DIRECTIVE; \.visible TC; return VISIBLE_DIRECTIVE; \.address_size TC; return ADDRESS_SIZE_DIRECTIVE; +\.weak TC; return WEAK_DIRECTIVE; \.constptr TC; return CONSTPTR_DIRECTIVE; /* Ptx plus directive for pointer to constant memory */ \.ptr TC; return PTR_DIRECTIVE; /* Added for new OpenCL genrated code */ diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 82abcbb..fca94db 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -47,6 +47,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token PTR_DIRECTIVE %token ENTRY_DIRECTIVE %token EXTERN_DIRECTIVE +%token WEAK_DIRECTIVE %token FILE_DIRECTIVE %token FUNC_DIRECTIVE %token GLOBAL_DIRECTIVE @@ -243,6 +244,7 @@ function_decl_header: ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".ent | VISIBLE_DIRECTIVE ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } | FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } | VISIBLE_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } + | WEAK_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } | EXTERN_DIRECTIVE FUNC_DIRECTIVE { $$ = 2; g_func_decl=1; func_header(".func"); } ; -- cgit v1.3 From a2c48c472fc2ab159b826f3af1d1503c23eaed39 Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 3 Jun 2016 14:10:20 -0700 Subject: Added mergeSectionList to combine any PTX files that remain after pruning into a single file. --- libcuda/cuda_runtime_api.cc | 44 ++++++++++++++++++++++++++++++++++++++++++++ libcuda/cuobjdump.y | 2 +- 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index e2626d2..8049f43 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1496,6 +1496,49 @@ std::list pruneSectionList(std::list cuobj return prunedList; } +//! Merge all remaining PTX sections in the section list into one PTX file +// NOTE: this function needs some tweaking to deal with repeated fucntion/variable declarations/definitions +std::list mergeSectionList(std::list cuobjdumpSectionList){ + char *ptxcode = ""; + std::list::iterator old_iter; + cuobjdumpPTXSection* old_ptxsection = NULL; + cuobjdumpPTXSection* ptxsection; + std::list mergedList; + + for ( std::list::iterator iter = cuobjdumpSectionList.begin(); + iter != cuobjdumpSectionList.end(); + iter++){ + if((ptxsection=dynamic_cast(*iter)) != NULL){ + // Read and remove the last PTX section + if (old_ptxsection != NULL) { + ptxcode = readfile(old_ptxsection->getPTXfilename()); + // remove ptx file? + delete *old_iter; + } + + // Append all the PTX from the last PTX section into the current PTX section + // Add 50 to ptxcode to ignore the information regarding version/target/address_size + if (strlen(ptxcode) >= 50) { + FILE *ptxfile = fopen((ptxsection->getPTXfilename()).c_str(), "a"); + fprintf(ptxfile, "%s", ptxcode + 50); + fclose(ptxfile); + } + + old_iter = iter; + old_ptxsection = ptxsection; + } + // Store all non-PTX sections + else { + mergedList.push_back(*iter); + } + } + + // Store the final PTX section + mergedList.push_front(*old_iter); + + return mergedList; +} + //! Within the section list, find the ELF section corresponding to a given identifier cuobjdumpELFSection* findELFSectionInList(std::list sectionlist, const std::string identifier){ @@ -1559,6 +1602,7 @@ void cuobjdumpInit(){ CUctx_st *context = GPGPUSim_Context(); extract_code_using_cuobjdump(); //extract all the output of cuobjdump to _cuobjdump_*.* cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); + cuobjdumpSectionList = mergeSectionList(cuobjdumpSectionList); } std::map fatbinmap; diff --git a/libcuda/cuobjdump.y b/libcuda/cuobjdump.y index dce7e3d..9d61f25 100644 --- a/libcuda/cuobjdump.y +++ b/libcuda/cuobjdump.y @@ -114,7 +114,7 @@ compressedkeyword : H_COMPRESSED emptylines ptxcode : ptxcode PTXLINE {fprintf(ptxfile, "%s", $2);} | ; -elfcode : elfcode ELFLINE {printf(elffile, "%s", $2);} +elfcode : elfcode ELFLINE {fprintf(elffile, "%s", $2);} | ; sasscode : sasscode SASSLINE {fprintf(sassfile, "%s", $2);} -- cgit v1.3 From 71ccce6074de5d7eef3fbe2cda1dbca008549f07 Mon Sep 17 00:00:00 2001 From: speverel Date: Fri, 3 Jun 2016 15:24:40 -0700 Subject: Added support for %laneid SFR. Also added a notice clarifying that power modeling for GTX750Ti is currently completely untested and should not be considered supported. --- configs/GeForceGTX750Ti/gpgpusim.config | 4 +++- configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml | 1 + src/cuda-sim/ptx_sim.cc | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index 7920763..8b030b6 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -119,8 +119,10 @@ -visualizer_enabled 0 # power model configs +# power modeling is currently disabled for GTX750Ti. The gpuwattch_gtx750ti.xml file present is only a placeholder and has NOT been tested for accuracy. +# proper modeling of Maxwell power is planned, but should be considered completely unsupported at present. -power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx480.xml +-gpuwattch_xml_file gpuwattch_gtx750Ti.xml # tracing functionality #-trace_enabled 1 diff --git a/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml b/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml index 304e0fd..e2b2324 100755 --- a/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml +++ b/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml @@ -1,3 +1,4 @@ + diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc index 9b32e68..09844ae 100644 --- a/src/cuda-sim/ptx_sim.cc +++ b/src/cuda-sim/ptx_sim.cc @@ -240,7 +240,7 @@ unsigned ptx_thread_info::get_builtin( int builtin_id, unsigned dim_mod ) } case GRIDID_REG: return m_gridid; - case LANEID_REG: feature_not_implemented( "%laneid" ); return 0; + case LANEID_REG: return get_hw_tid() % m_core->get_warp_size(); case LANEMASK_EQ_REG: feature_not_implemented( "%lanemask_eq" ); return 0; case LANEMASK_LE_REG: feature_not_implemented( "%lanemask_le" ); return 0; case LANEMASK_LT_REG: feature_not_implemented( "%lanemask_lt" ); return 0; -- cgit v1.3 From 8ed1522aede92bcafc60f69d7e03e6d48c44a86c Mon Sep 17 00:00:00 2001 From: speverel Date: Mon, 6 Jun 2016 14:48:13 -0700 Subject: Added support for BFE (Bit field extract) instruction. --- src/cuda-sim/instructions.cc | 77 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 76 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 4dd5ed8..02ce01c 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1336,7 +1336,82 @@ void bar_impl( const ptx_instruction *pIin, ptx_thread_info *thread ) thread->m_last_dram_callback.instruction = pIin; } -void bfe_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void bfe_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + unsigned i_type = pI->get_type(); + unsigned msb = (i_type == U32_TYPE || i_type == S32_TYPE) ? 31 : 63; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); + ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); + ptx_reg_t c = thread->get_operand_value(src3, dst, i_type, thread, 1); + unsigned pos = b.u32 & 0xFF; + unsigned len = c.u32 & 0xFF; + unsigned d = 0; + switch (i_type) + { + case U32_TYPE: + { + unsigned mask; + d = a.u32 >> pos; + mask = 0xFFFFFFFF >> (32 - len); + d &= mask; + break; + } + case U64_TYPE: + { + unsigned long mask; + d = a.u64 >> pos; + mask = 0xFFFFFFFFFFFFFFFF >> (64 - len); + d &= mask; + break; + } + case S32_TYPE: + { + unsigned mask; + unsigned min = MY_MIN_I(pos + len - 1, msb); + unsigned sbit = len == 0 ? 0 : (a.s32 >> min) & 0x1; + d = a.s32 >> pos; + if (sbit > 0) + { + mask = 0xFFFFFFFF << len; + d |= mask; + } + else + { + mask = 0xFFFFFFFF >> (32 - len); + d &= mask; + } + break; + } + case S64_TYPE: + { + unsigned long mask; + unsigned min = MY_MIN_I(pos + len - 1, msb); + unsigned sbit = len == 0 ? 0 : (a.s64 >> min) & 0x1; + d = a.s64 >> pos; + if (sbit > 0) + { + mask = 0xFFFFFFFFFFFFFFFF << len; + d |= mask; + } + else + { + mask = 0xFFFFFFFFFFFFFFFF >> (64 - len); + d &= mask; + } + break; + } + default: + printf("Operand type not supported for BFE instruction.\n"); + abort(); + return; + } + thread->set_operand_value(dst,d, i_type, thread, pI); +} + void bfi_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } void bfind_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -- cgit v1.3 From 7aeadc95cc50d266f93cdb3ada1c192d9b5a1046 Mon Sep 17 00:00:00 2001 From: speverel Date: Tue, 7 Jun 2016 14:24:24 -0700 Subject: Added support for cudaMemcpyDefault flag in cudaMemcpy. Also increased the maximum allowable memory to 2GB and the compute version to 5.2. --- libcuda/cuda_runtime_api.cc | 23 ++++++++++++++++++++--- src/abstract_hardware_model.h | 2 +- 2 files changed, 21 insertions(+), 4 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 8049f43..018b387 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -134,6 +134,7 @@ #include "../src/cuda-sim/ptx_parser.h" #include "../src/gpgpusim_entrypoint.h" #include "../src/stream_manager.h" +#include "../src/abstract_hardware_model.h" #include #include @@ -320,9 +321,9 @@ class _cuda_device_id *GPGPUSim_Init() cudaDeviceProp *prop = (cudaDeviceProp *) calloc(sizeof(cudaDeviceProp),1); snprintf(prop->name,256,"GPGPU-Sim_v%s", g_gpgpusim_version_string ); - prop->major = 2; - prop->minor = 0; - prop->totalGlobalMem = 0x40000000 /* 1 GB */; + prop->major = 5; + prop->minor = 2; + prop->totalGlobalMem = 0x80000000 /* 2 GB */; prop->memPitch = 0; prop->maxThreadsPerBlock = 512; prop->maxThreadsDim[0] = 512; @@ -533,6 +534,22 @@ __host__ cudaError_t CUDARTAPI cudaMemcpy(void *dst, const void *src, size_t cou g_stream_manager->push( stream_operation((size_t)src,dst,count,0) ); else if( kind == cudaMemcpyDeviceToDevice ) g_stream_manager->push( stream_operation((size_t)src,(size_t)dst,count,0) ); + else if ( kind == cudaMemcpyDefault ) { + if ((size_t)src >= GLOBAL_HEAP_START) { + if ((size_t)dst >= GLOBAL_HEAP_START) + g_stream_manager->push( stream_operation((size_t)src,(size_t)dst,count,0) ); // device to device + else + g_stream_manager->push( stream_operation((size_t)src,dst,count,0) ); // device to host + } + else { + if ((size_t)dst >= GLOBAL_HEAP_START) + g_stream_manager->push( stream_operation(src,(size_t)dst,count,0) ); + else { + printf("GPGPU-Sim PTX: cudaMemcpy - ERROR : unsupported transfer: host to host\n"); + abort(); + } + } + } else { printf("GPGPU-Sim PTX: cudaMemcpy - ERROR : unsupported cudaMemcpyKind\n"); abort(); diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index ba4ea29..b29f918 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -334,7 +334,7 @@ protected: std::deque m_stack; }; -#define GLOBAL_HEAP_START 0x80000000 +#define GLOBAL_HEAP_START 0x703E20000 // start allocating from this address (lower values used for allocating globals in .ptx file) #define SHARED_MEM_SIZE_MAX (64*1024) #define LOCAL_MEM_SIZE_MAX (8*1024) -- cgit v1.3 From 587853a81f6fa6088b7f3d93fc8862a8b2610da7 Mon Sep 17 00:00:00 2001 From: sspenst Date: Tue, 7 Jun 2016 16:22:45 -0700 Subject: The ptx parser now recognizes the NC option for ld.global, however this option is not actually implemented --- libcuda/cuobjdump.y | 3 +-- src/cuda-sim/ptx.l | 2 ++ src/cuda-sim/ptx.y | 2 ++ src/cuda-sim/ptx_ir.cc | 2 ++ 4 files changed, 7 insertions(+), 2 deletions(-) diff --git a/libcuda/cuobjdump.y b/libcuda/cuobjdump.y index 9d61f25..31760f7 100644 --- a/libcuda/cuobjdump.y +++ b/libcuda/cuobjdump.y @@ -82,8 +82,7 @@ section : PTXHEADER { snprintf(filename, 1024, "_cuobjdump_%d.elf", elfserial); elffile = fopen(filename, "w"); setCuobjdumpelffilename(filename); - } headerinfo identifier{ - } elfcode { + } headerinfo compressedkeyword identifier elfcode { fclose(elffile); snprintf(filename, 1024, "_cuobjdump_%d.sass", elfserial++); sassfile = fopen(filename, "w"); diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 66ff48f..a44177b 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -326,6 +326,8 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.wb TC; return WB_OPTION; \.wt TC; return WT_OPTION; +\.nc TC; return NC_OPTION; + \.popc TC; return ATOMIC_POPC; \.and TC; return ATOMIC_AND; \.or TC; return ATOMIC_OR; diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index fca94db..4de39d1 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -193,6 +193,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token CV_OPTION; %token WB_OPTION; %token WT_OPTION; +%token NC_OPTION; %type function_decl_header %type function_decl @@ -449,6 +450,7 @@ option: type_spec | CV_OPTION { add_option(CV_OPTION); } | WB_OPTION { add_option(WB_OPTION); } | WT_OPTION { add_option(WT_OPTION); } + | NC_OPTION { add_option(NC_OPTION); } ; atomic_operation_spec: ATOMIC_AND { add_option(ATOMIC_AND); } diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 8f9c3d2..2eccabc 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1169,6 +1169,8 @@ ptx_instruction::ptx_instruction( int opcode, break; case EXTP_OPTION: break; + case NC_OPTION: + break; default: assert(0); break; -- cgit v1.3 From 41dbdd842f315645cc4cd05e3b6263b982d1be2e Mon Sep 17 00:00:00 2001 From: sspenst Date: Tue, 7 Jun 2016 16:43:09 -0700 Subject: Updated the PTX section merging to be able to deal with multiple identifiers --- libcuda/cuda_runtime_api.cc | 43 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 7 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 018b387..862e2b9 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1513,9 +1513,8 @@ std::list pruneSectionList(std::list cuobj return prunedList; } -//! Merge all remaining PTX sections in the section list into one PTX file -// NOTE: this function needs some tweaking to deal with repeated fucntion/variable declarations/definitions -std::list mergeSectionList(std::list cuobjdumpSectionList){ +//! Merge all PTX sections that have a specific identifier into one file +std::list mergeMatchingSections(std::list cuobjdumpSectionList, std::string identifier){ char *ptxcode = ""; std::list::iterator old_iter; cuobjdumpPTXSection* old_ptxsection = NULL; @@ -1525,7 +1524,8 @@ std::list mergeSectionList(std::list cuobj for ( std::list::iterator iter = cuobjdumpSectionList.begin(); iter != cuobjdumpSectionList.end(); iter++){ - if((ptxsection=dynamic_cast(*iter)) != NULL){ + if((ptxsection=dynamic_cast(*iter)) != NULL && + strcmp(ptxsection->getIdentifier().c_str(), identifier.c_str()) == 0){ // Read and remove the last PTX section if (old_ptxsection != NULL) { ptxcode = readfile(old_ptxsection->getPTXfilename()); @@ -1544,18 +1544,47 @@ std::list mergeSectionList(std::list cuobj old_iter = iter; old_ptxsection = ptxsection; } - // Store all non-PTX sections + // Store all non-PTX sections and PTX sections with non-matching identifiers else { mergedList.push_back(*iter); } } // Store the final PTX section - mergedList.push_front(*old_iter); + mergedList.push_back(*old_iter); return mergedList; } +//! Merge any PTX sections with matching identifiers +std::list mergeSections(std::list cuobjdumpSectionList){ + std::vector identifier; + cuobjdumpPTXSection* ptxsection; + + // Add all identifiers present in PTX sections to a vector + for ( std::list::iterator iter = cuobjdumpSectionList.begin(); + iter != cuobjdumpSectionList.end(); + iter++){ + if((ptxsection=dynamic_cast(*iter)) != NULL){ + std::string current_id = ptxsection->getIdentifier(); + + // If we haven't yet seen a given identifier, add it to the vector + if (std::find(identifier.begin(), identifier.end(), current_id) == identifier.end()) { + identifier.push_back(current_id); + } + } + } + + // Call mergeMatchingSections on all identifiers in the vector + for ( std::vector::iterator iter = identifier.begin(); + iter != identifier.end(); + iter++) { + cuobjdumpSectionList = mergeMatchingSections(cuobjdumpSectionList, *iter); + } + + return cuobjdumpSectionList; +} + //! Within the section list, find the ELF section corresponding to a given identifier cuobjdumpELFSection* findELFSectionInList(std::list sectionlist, const std::string identifier){ @@ -1619,7 +1648,7 @@ void cuobjdumpInit(){ CUctx_st *context = GPGPUSim_Context(); extract_code_using_cuobjdump(); //extract all the output of cuobjdump to _cuobjdump_*.* cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); - cuobjdumpSectionList = mergeSectionList(cuobjdumpSectionList); + cuobjdumpSectionList = mergeSections(cuobjdumpSectionList); } std::map fatbinmap; -- cgit v1.3 From 5e9b6521e625d30f9f3efbb292fd22bdab5c884a Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 9 Jun 2016 13:38:13 -0700 Subject: Added a basic implementation of cudaStreamCreateWithFlags --- libcuda/cuda_runtime_api.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 862e2b9..77456d4 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -984,6 +984,10 @@ __host__ cudaError_t CUDARTAPI cudaStreamCreate(cudaStream_t *stream) return g_last_cudaError = cudaSuccess; } +__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *stream, unsigned int flags) { + cudaStreamCreate(stream); +} + __host__ cudaError_t CUDARTAPI cudaStreamDestroy(cudaStream_t stream) { #if (CUDART_VERSION >= 3000) -- cgit v1.3 From adabbc7070704d1be79465786d59e170030c7b0d Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 9 Jun 2016 14:23:28 -0700 Subject: Forgot to add a return value --- libcuda/cuda_runtime_api.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 77456d4..4cc002d 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -985,7 +985,7 @@ __host__ cudaError_t CUDARTAPI cudaStreamCreate(cudaStream_t *stream) } __host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *stream, unsigned int flags) { - cudaStreamCreate(stream); + return cudaStreamCreate(stream); } __host__ cudaError_t CUDARTAPI cudaStreamDestroy(cudaStream_t stream) -- cgit v1.3 From ac11fd57b93e22ee5a50ebf8f6d6b4d6dadbe3cb Mon Sep 17 00:00:00 2001 From: speverel Date: Thu, 9 Jun 2016 14:58:38 -0700 Subject: Modified runtime API to support synchronization with the null stream. --- libcuda/cuda_runtime_api.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 77456d4..350ba0b 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -440,6 +440,10 @@ extern "C" { * * * * *******************************************************************************/ +cudaError_t cudaPeekAtLastError(void) +{ + return g_last_cudaError; +} __host__ cudaError_t CUDARTAPI cudaMalloc(void **devPtr, size_t size) { @@ -1000,7 +1004,8 @@ __host__ cudaError_t CUDARTAPI cudaStreamSynchronize(cudaStream_t stream) { #if (CUDART_VERSION >= 3000) if( stream == NULL ) - return g_last_cudaError = cudaErrorInvalidResourceHandle; + synchronize(); + return g_last_cudaError = cudaSuccess; stream->synchronize(); #else printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); -- cgit v1.3 From 7356669b66425ee73ba61466f37fe25b886a3641 Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 10 Jun 2016 14:32:00 -0700 Subject: Vastly improved runtime by relating symbol tables to file names --- libcuda/cuda_runtime_api.cc | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 5558c4b..e8a0e91 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1662,6 +1662,7 @@ void cuobjdumpInit(){ std::map fatbinmap; std::mapfatbin_registered; +std::map name_symtab; //! Keep track of the association between filename and cubin handle void cuobjdumpRegisterFatBinary(unsigned int handle, char* filename){ @@ -1674,6 +1675,13 @@ void cuobjdumpParseBinary(unsigned int handle){ if(fatbin_registered[handle]) return; fatbin_registered[handle] = true; CUctx_st *context = GPGPUSim_Context(); + std::string fname = fatbinmap[handle]; + + if (name_symtab.find(fname) != name_symtab.end()) { + symbol_table *symtab = name_symtab[fname]; + context->add_binary(symtab, handle); + return; + } unsigned max_capability = 0; for ( std::list::iterator iter = cuobjdumpSectionList.begin(); @@ -1682,16 +1690,13 @@ void cuobjdumpParseBinary(unsigned int handle){ unsigned capability = (*iter)->getArch(); if (capability > max_capability) max_capability = capability; } - if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); - std::string fname = fatbinmap[handle]; cuobjdumpPTXSection* ptx = findPTXSection(fname); - symbol_table *symtab; char *ptxcode; const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); - if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL) { + if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL) { ptxcode = readfile(ptx->getPTXfilename()); } else { printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); @@ -1717,6 +1722,7 @@ void cuobjdumpParseBinary(unsigned int handle){ } load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu()); load_constants(symtab,STATIC_ALLOC_LIMIT,context->get_device()->get_gpgpu()); + name_symtab[fname] = symtab; //TODO: Remove temporarily files as per configurations } -- cgit v1.3 From 547ce656018a6439e658be3c283721a961b0217f Mon Sep 17 00:00:00 2001 From: sspenst Date: Mon, 13 Jun 2016 01:08:36 -0700 Subject: If ptxas notices any duplicate errors, they now automatically get resolved and the program continues with the duplicate function/variable declarations removed. --- src/cuda-sim/cuda-sim.cc | 19 +++++++ src/cuda-sim/ptx_loader.cc | 126 +++++++++++++++++++++++++++++++++++++++++++-- src/cuda-sim/ptxinfo.l | 4 ++ src/cuda-sim/ptxinfo.y | 16 +++++- 4 files changed, 160 insertions(+), 5 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 15417d1..fba3a59 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1864,10 +1864,14 @@ unsigned translate_pc_to_ptxlineno(unsigned pc) // ptxinfo parser +extern std::map get_duplicate(); + int g_ptxinfo_error_detected; static char *g_ptxinfo_kname = NULL; static struct gpgpu_ptx_sim_info g_ptxinfo; +static std::map g_duplicate; +static const char *g_last_dup_type; const char *get_ptxinfo_kname() { @@ -1897,6 +1901,21 @@ struct gpgpu_ptx_sim_info get_ptxinfo() return g_ptxinfo; } +std::map get_duplicate() +{ + return g_duplicate; +} + +void ptxinfo_linenum( unsigned linenum ) +{ + g_duplicate[linenum] = g_last_dup_type; +} + +void ptxinfo_dup_type( const char *dup_type ) +{ + g_last_dup_type = dup_type; +} + void ptxinfo_function(const char *fname ) { clear_ptxinfo(); diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index f7bf70e..9bb5008 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -46,6 +46,8 @@ bool g_override_embedded_ptx = false; extern int ptx_parse(); extern int ptx__scan_string(const char*); +extern std::map get_duplicate(); + const char *g_ptxinfo_filename; extern int ptxinfo_parse(); extern int ptxinfo_debug; @@ -182,6 +184,109 @@ symbol_table *gpgpu_ptx_sim_load_ptx_from_string( const char *p, unsigned source return symtab; } +void fix_duplicate_errors(char fname2[1024]) { + char tempfile[1024] = "_temp_ptx"; + char commandline[1024]; + + // change the name of the ptx file to _temp_ptx + snprintf(commandline,1024,"mv %s %s",fname2,tempfile); + printf("Running: %s\n", commandline); + int result = system(commandline); + if (result != 0) { + printf("GPGPU-Sim PTX: ERROR ** while changing filename from %s to %s", fname2, tempfile); + exit(1); + } + + // store all of the ptx into a char array + FILE *ptxsource = fopen(tempfile,"r"); + fseek(ptxsource, 0, SEEK_END); + long filesize = ftell(ptxsource); + rewind(ptxsource); + char *ptxdata = (char*)malloc((filesize+1)*sizeof(char)); + fread(ptxdata, filesize, 1, ptxsource); + fclose(ptxsource); + + FILE *ptxdest = fopen(fname2,"w"); + std::map duplicate = get_duplicate(); + unsigned offset; + unsigned oldlinenum = 1; + unsigned linenum; + char *startptr = ptxdata; + char *funcptr; + char *tempptr = ptxdata - 1; + char *lineptr = ptxdata - 1; + + // recreate the ptx file without duplications + for ( std::map::iterator iter = duplicate.begin(); + iter != duplicate.end(); + iter++){ + // find the line of the next error + linenum = iter->first; + for (int i = oldlinenum; i < linenum; i++) { + lineptr = strchr(lineptr + 1, '\n'); + } + + // find the end of the current section to be copied over + // then find the start of the next section that will be copied + if (strcmp("function", iter->second) == 0) { + // get location of most recent .func + while (tempptr < lineptr && tempptr != NULL) { + funcptr = tempptr; + tempptr = strstr(funcptr + 1, ".func"); + } + + // get the start of the previous line + offset = 0; + while (*(funcptr - offset) != '\n') offset++; + + fwrite(startptr, sizeof(char), funcptr - offset + 1 - startptr, ptxdest); + + //find next location of startptr + if (*(lineptr + 3) == ';') { + // for function definitions + startptr = lineptr + 5; + } else if (*(lineptr + 3) == '{') { + // for functions enclosed with curly brackets + offset = 5; + unsigned bracket = 1; + while (bracket != 0) { + if (*(lineptr + offset) == '{') bracket++; + else if (*(lineptr + offset) == '}') bracket--; + offset++; + } + startptr = lineptr + offset + 1; + } else { + printf("GPGPU-Sim PTX: ERROR ** Unrecognized function format\n"); + abort(); + } + } else if (strcmp("variable", iter->second) == 0) { + fwrite(startptr, sizeof(char), (int)(lineptr + 1 - startptr), ptxdest); + + //find next location of startptr + offset = 1; + while (*(lineptr + offset) != '\n') offset++; + startptr = lineptr + offset + 1; + } else { + printf("GPGPU-Sim PTX: ERROR ** Unsupported duplicate type: %s\n", iter->second); + } + + oldlinenum = linenum; + } + // copy over the rest of the file + fwrite(startptr, sizeof(char), ptxdata + filesize - startptr, ptxdest); + + // cleanup + free(ptxdata); + fclose(ptxdest); + snprintf(commandline,1024,"rm -f %s",tempfile); + printf("Running: %s\n", commandline); + result = system(commandline); + if (result != 0) { + printf("GPGPU-Sim PTX: ERROR ** while deleting %s", tempfile); + exit(1); + } +} + void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version ) { char fname[1024]; @@ -225,14 +330,29 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); result = system(commandline); if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); - printf(" Ensure ptxas is in your path.\n"); - exit(1); + // 65280 = duplicate errors + if (result == 65280) { + ptxinfo_in = fopen(tempfile_ptxinfo,"r"); + g_ptxinfo_filename = tempfile_ptxinfo; + ptxinfo_parse(); + + fix_duplicate_errors(fname2); + snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", + extra_flags, fname2, tempfile_ptxinfo); + printf("GPGPU-Sim PTX: regenerating ptxinfo using \"%s\"\n", commandline); + result = system(commandline); + } + if (result != 0) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); + printf(" Ensure ptxas is in your path.\n"); + exit(1); + } } ptxinfo_in = fopen(tempfile_ptxinfo,"r"); g_ptxinfo_filename = tempfile_ptxinfo; ptxinfo_parse(); + if( ! g_save_embedded_ptx ) { snprintf(commandline,1024,"rm -f %s %s %s", fname, fname2, tempfile_ptxinfo); printf("GPGPU-Sim PTX: removing ptxinfo using \"%s\"\n", commandline); diff --git a/src/cuda-sim/ptxinfo.l b/src/cuda-sim/ptxinfo.l index f9b6846..33c2748 100644 --- a/src/cuda-sim/ptxinfo.l +++ b/src/cuda-sim/ptxinfo.l @@ -60,6 +60,10 @@ unsigned ptxinfo_col = 0; "line" TC; return LINE; "for" TC; return FOR; "textures" TC; return TEXTURES; +"error : Duplicate definition of" TC; return DUPLICATE; +"function" TC; ptxinfo_lval.string_value = strdup(yytext); return FUNCTION; +"variable" TC; ptxinfo_lval.string_value = strdup(yytext); return VARIABLE; +"fatal : Ptx assembly aborted due to errors" TC; return FATAL; [_A-Za-z$%][_0-9A-Za-z$]* TC; ptxinfo_lval.string_value = strdup(yytext); return IDENTIFIER; [-]{0,1}[0-9]+ TC; ptxinfo_lval.int_value = atoi(yytext); return INT_OPERAND; diff --git a/src/cuda-sim/ptxinfo.y b/src/cuda-sim/ptxinfo.y index faa33eb..37092f4 100644 --- a/src/cuda-sim/ptxinfo.y +++ b/src/cuda-sim/ptxinfo.y @@ -55,11 +55,15 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token WARNING %token FOR %token TEXTURES +%token DUPLICATE +%token FUNCTION +%token VARIABLE +%token FATAL %{ #include #include - + static unsigned g_declared; static unsigned g_system; int ptxinfo_lex(void); @@ -71,6 +75,8 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. void ptxinfo_smem( unsigned declared, unsigned system ); void ptxinfo_cmem( unsigned nbytes, unsigned bank ); int ptxinfo_error(const char*); + void ptxinfo_linenum( unsigned ); + void ptxinfo_dup_type( const char* ); %} %% @@ -82,6 +88,8 @@ input: /* empty */ line: HEADER INFO COLON line_info | HEADER IDENTIFIER COMMA LINE INT_OPERAND SEMICOLON WARNING | HEADER WARNING { printf("GPGPU-Sim: ptxas %s\n", $2); } + | HEADER IDENTIFIER COMMA LINE INT_OPERAND SEMICOLON DUPLICATE duplicate { ptxinfo_linenum($5); } + | HEADER FATAL ; line_info: function_name @@ -89,7 +97,7 @@ line_info: function_name ; function_name: FUNC QUOTE IDENTIFIER QUOTE { ptxinfo_function($3); } - | FUNC QUOTE IDENTIFIER QUOTE FOR QUOTE IDENTIFIER QUOTE {ptxinfo_function($3); } + | FUNC QUOTE IDENTIFIER QUOTE FOR QUOTE IDENTIFIER QUOTE { ptxinfo_function($3); } ; function_info: info @@ -110,6 +118,10 @@ info: USED INT_OPERAND REGS { ptxinfo_regs($2); } tuple: INT_OPERAND PLUS INT_OPERAND BYTES { g_declared=$1; g_system=$3; } +duplicate: FUNCTION QUOTE IDENTIFIER QUOTE { ptxinfo_dup_type($1); } + | VARIABLE QUOTE IDENTIFIER QUOTE { ptxinfo_dup_type($1); } + ; + %% -- cgit v1.3 From 281798191f9bc37a75592d34a5e38cc5d6c41b6d Mon Sep 17 00:00:00 2001 From: speverel Date: Thu, 16 Jun 2016 15:51:17 -0700 Subject: Added the ability to inject arbitrary PTX instructions. This will be used to add custom instructions in the future; the imaginary instructions 'spr' and 'ama' have been added as samples. --- src/cuda-sim/instructions.cc | 10 ++++++++++ src/cuda-sim/opcodes.def | 2 ++ src/cuda-sim/ptx.l | 6 +++++- 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 02ce01c..922e14a 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -816,6 +816,11 @@ void add_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void addc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void ama_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + printf("AMA instruction found.\n"); +} + void and_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { ptx_reg_t src1_data, src2_data, data; @@ -3698,6 +3703,11 @@ void slct_impl( const ptx_instruction *pI, ptx_thread_info *thread ) thread->set_operand_value(dst,d, i_type, thread, pI); } +void spr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + printf("SPR instruction found.\n"); +} + void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { ptx_reg_t a, d; diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 874acc7..33ee0ca 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -41,6 +41,7 @@ OP_DEF(ABS_OP,abs_impl,"abs",1,1) OP_DEF(ADD_OP,add_impl,"add",1,1) OP_DEF(ADDP_OP,addp_impl,"addp",1,1) OP_DEF(ADDC_OP,addc_impl,"addc",1,1) +OP_DEF(AMA_OP,ama_impl,"ama",1,2) OP_DEF(AND_OP,and_impl,"and",1,1) OP_DEF(ANDN_OP,andn_impl,"andn",1,1) OP_DEF(ATOM_OP,atom_impl,"atom",1,3) @@ -101,6 +102,7 @@ OP_DEF(SHL_OP,shl_impl,"shl",1,1) OP_DEF(SHR_OP,shr_impl,"shr",1,1) OP_DEF(SIN_OP,sin_impl,"sin",1,4) OP_DEF(SLCT_OP,slct_impl,"slct",1,1) +OP_DEF(SPR_OP,spr_impl,"spr",1,1) OP_DEF(SQRT_OP,sqrt_impl,"sqrt",1,4) OP_DEF(SSY_OP,ssy_impl,"ssy",0,3) OP_DEF(ST_OP,st_impl,"st",0,5) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index a44177b..026270a 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -145,6 +145,8 @@ xor TC; ptx_lval.int_value = XOR_OP; return OPCODE; nop TC; ptx_lval.int_value = NOP_OP; return OPCODE; break TC; ptx_lval.int_value = BREAK_OP; return OPCODE; breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; +spr TC; ptx_lval.int_value = SPR_OP; return OPCODE; +ama TC; ptx_lval.int_value = AMA_OP; return OPCODE; { @@ -390,7 +392,9 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; } { "*/" BEGIN(INITIAL); -[^*\n]+ // eat comment in chunks +"CPTX_BEGIN" printf("BEGINNING CUSTOM PTX.\n"); BEGIN(INITIAL); +[^C*\n]+ // eat comment in chunks +"C" "*" // eat the lone star \n TC; } -- cgit v1.3 From 308c35d296d648e683cbee757e6961c3b9c7ca50 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Fri, 1 Jul 2016 17:34:23 -0700 Subject: adding Travis configuration file --- .travis.yml | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 .travis.yml diff --git a/.travis.yml b/.travis.yml new file mode 100644 index 0000000..dd89db1 --- /dev/null +++ b/.travis.yml @@ -0,0 +1,9 @@ +dist: trusty +before_install: + - wget http://developer.download.nvidia.com/compute/cuda/repos/ubuntu1404/x86_64/cuda-repo-ubuntu1404_7.5-18_amd64.deb + - sudo dpkg -i cuda-repo-ubuntu1404_7.5-18_amd64.deb + - sudo apt-get -qq update + - sudo apt-get install -y cuda + - sudo apt-get install -y build-essential xutils-dev bison zlib1g-dev flex libglu1-mesa-dev +language: cpp +script: source ./setup_environment && make -- cgit v1.3 From 3af9c3a49c9fbae3760c38ac76f7bc334b6b8d27 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Fri, 1 Jul 2016 17:54:29 -0700 Subject: set CUDA_INSTALL_PATH in Travis configuration file --- .travis.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.travis.yml b/.travis.yml index dd89db1..18fcd7a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -5,5 +5,7 @@ before_install: - sudo apt-get -qq update - sudo apt-get install -y cuda - sudo apt-get install -y build-essential xutils-dev bison zlib1g-dev flex libglu1-mesa-dev +env: + - CUDA_INSTALL_PATH=/usr/local/cuda-7.5/ language: cpp script: source ./setup_environment && make -- cgit v1.3 From f7c57e76c086ce417626f37ffc91097c839c687d Mon Sep 17 00:00:00 2001 From: sspenst Date: Mon, 4 Jul 2016 09:43:36 -0700 Subject: Reverted part of the previous commit so that our new changes related to DNNs can be done in a different branch --- src/cuda-sim/instructions.cc | 10 ---------- src/cuda-sim/opcodes.def | 2 -- src/cuda-sim/ptx.l | 2 -- 3 files changed, 14 deletions(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 922e14a..02ce01c 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -816,11 +816,6 @@ void add_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void addc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void ama_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - printf("AMA instruction found.\n"); -} - void and_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { ptx_reg_t src1_data, src2_data, data; @@ -3703,11 +3698,6 @@ void slct_impl( const ptx_instruction *pI, ptx_thread_info *thread ) thread->set_operand_value(dst,d, i_type, thread, pI); } -void spr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - printf("SPR instruction found.\n"); -} - void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { ptx_reg_t a, d; diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 33ee0ca..874acc7 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -41,7 +41,6 @@ OP_DEF(ABS_OP,abs_impl,"abs",1,1) OP_DEF(ADD_OP,add_impl,"add",1,1) OP_DEF(ADDP_OP,addp_impl,"addp",1,1) OP_DEF(ADDC_OP,addc_impl,"addc",1,1) -OP_DEF(AMA_OP,ama_impl,"ama",1,2) OP_DEF(AND_OP,and_impl,"and",1,1) OP_DEF(ANDN_OP,andn_impl,"andn",1,1) OP_DEF(ATOM_OP,atom_impl,"atom",1,3) @@ -102,7 +101,6 @@ OP_DEF(SHL_OP,shl_impl,"shl",1,1) OP_DEF(SHR_OP,shr_impl,"shr",1,1) OP_DEF(SIN_OP,sin_impl,"sin",1,4) OP_DEF(SLCT_OP,slct_impl,"slct",1,1) -OP_DEF(SPR_OP,spr_impl,"spr",1,1) OP_DEF(SQRT_OP,sqrt_impl,"sqrt",1,4) OP_DEF(SSY_OP,ssy_impl,"ssy",0,3) OP_DEF(ST_OP,st_impl,"st",0,5) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 026270a..b8ce497 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -145,8 +145,6 @@ xor TC; ptx_lval.int_value = XOR_OP; return OPCODE; nop TC; ptx_lval.int_value = NOP_OP; return OPCODE; break TC; ptx_lval.int_value = BREAK_OP; return OPCODE; breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; -spr TC; ptx_lval.int_value = SPR_OP; return OPCODE; -ama TC; ptx_lval.int_value = AMA_OP; return OPCODE; { -- cgit v1.3 From 9aa7de6492a0237369cc339abf4b1cfc3d99a1eb Mon Sep 17 00:00:00 2001 From: Ahmed ElTantawy Date: Mon, 4 Jul 2016 11:14:07 -0700 Subject: fix a silly typo --- libcuda/cuobjdump.y | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcuda/cuobjdump.y b/libcuda/cuobjdump.y index dce7e3d..9d61f25 100644 --- a/libcuda/cuobjdump.y +++ b/libcuda/cuobjdump.y @@ -114,7 +114,7 @@ compressedkeyword : H_COMPRESSED emptylines ptxcode : ptxcode PTXLINE {fprintf(ptxfile, "%s", $2);} | ; -elfcode : elfcode ELFLINE {printf(elffile, "%s", $2);} +elfcode : elfcode ELFLINE {fprintf(elffile, "%s", $2);} | ; sasscode : sasscode SASSLINE {fprintf(sassfile, "%s", $2);} -- cgit v1.3 From 2683b8bd7ba9950e0aa174915ef9ff64e0a20421 Mon Sep 17 00:00:00 2001 From: speverel Date: Mon, 4 Jul 2016 15:07:50 -0700 Subject: Restored madp instruction. --- src/cuda-sim/cuda-sim.cc | 2 +- src/cuda-sim/instructions.cc | 5 +++++ src/cuda-sim/opcodes.def | 1 + src/cuda-sim/ptx.l | 1 + 4 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index fba3a59..09e9a81 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -719,7 +719,7 @@ void ptx_instruction::set_opcode_and_latency() break; } break; - case MAD_OP: case MADC_OP: + case MAD_OP: case MADC_OP: case MADP_OP: //MAD latency switch(get_type()){ case F32_TYPE: diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 02ce01c..7b0f4fa 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2496,6 +2496,11 @@ void mad_impl( const ptx_instruction *pI, ptx_thread_info *thread ) mad_def(pI, thread, false); } +void madp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + mad_def(pI, thread, true); +} + void madc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { mad_def(pI, thread, true); diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 874acc7..2ee6976 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -70,6 +70,7 @@ OP_DEF(LG2_OP,lg2_impl,"lg2",1,4) OP_DEF(MAD24_OP,mad24_impl,"mad24",1,2) OP_DEF(MAD_OP,mad_impl,"mad",1,2) OP_DEF(MADC_OP,madc_impl,"madc",1,2) +OP_DEF(MADP_OP,madp_impl,"madp",1,2) OP_DEF(MAX_OP,max_impl,"max",1,1) OP_DEF(MEMBAR_OP,membar_impl,"membar",1,3) OP_DEF(MIN_OP,min_impl,"min",1,1) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index b8ce497..88ccf6a 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -87,6 +87,7 @@ lg2 TC; ptx_lval.int_value = LG2_OP; return OPCODE; mad24 TC; ptx_lval.int_value = MAD24_OP; return OPCODE; mad TC; ptx_lval.int_value = MAD_OP; return OPCODE; madc TC; ptx_lval.int_value = MADC_OP; return OPCODE; +madp TC; ptx_lval.int_value = MADP_OP; return OPCODE; max TC; ptx_lval.int_value = MAX_OP; return OPCODE; membar TC; ptx_lval.int_value = MEMBAR_OP; return OPCODE; min TC; ptx_lval.int_value = MIN_OP; return OPCODE; -- cgit v1.3 From 91b2afe09dbeb0fa1c5eb57cd4b416a5eb24bf60 Mon Sep 17 00:00:00 2001 From: sspenst Date: Mon, 4 Jul 2016 16:25:11 -0700 Subject: Initial SST recognition from PTX parser --- src/cuda-sim/instructions.cc | 5 +++++ src/cuda-sim/opcodes.def | 1 + src/cuda-sim/ptx.l | 1 + 3 files changed, 7 insertions(+) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 7b0f4fa..36aa29f 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3734,6 +3734,11 @@ void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) thread->set_operand_value(dst,d, i_type, thread, pI); } +void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + printf("SST instruction found.\n"); +} + void ssy_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { //printf("Execution Warning: unimplemented ssy instruction is treated as a nop\n"); diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 2ee6976..0c0eda9 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -103,6 +103,7 @@ OP_DEF(SHR_OP,shr_impl,"shr",1,1) OP_DEF(SIN_OP,sin_impl,"sin",1,4) OP_DEF(SLCT_OP,slct_impl,"slct",1,1) OP_DEF(SQRT_OP,sqrt_impl,"sqrt",1,4) +OP_DEF(SST_OP,sst_impl,"sst",1,1) OP_DEF(SSY_OP,ssy_impl,"ssy",0,3) OP_DEF(ST_OP,st_impl,"st",0,5) OP_DEF(SUB_OP,sub_impl,"sub",1,1) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 88ccf6a..1ac047c 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -120,6 +120,7 @@ shr TC; ptx_lval.int_value = SHR_OP; return OPCODE; sin TC; ptx_lval.int_value = SIN_OP; return OPCODE; slct TC; ptx_lval.int_value = SLCT_OP; return OPCODE; sqrt TC; ptx_lval.int_value = SQRT_OP; return OPCODE; +sst TC; ptx_lval.int_value = SST_OP; return OPCODE; ssy TC; ptx_lval.int_value = SSY_OP; return OPCODE; st TC; ptx_lval.int_value = ST_OP; return OPCODE; st.volatile TC; ptx_lval.int_value = ST_OP; return OPCODE; -- cgit v1.3 From fabf1747e3f798c76ddc9c5fae26a8d4d3cdedec Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Thu, 25 Sep 2014 16:15:09 -0400 Subject: MOD: add support for cuda65 ptx header --- Makefile | 2 ++ libcuda/cuda_runtime_api.cc | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 9e2c576..a044648 100644 --- a/Makefile +++ b/Makefile @@ -155,7 +155,9 @@ $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib if [ ! -f $(SIM_LIB_DIR)/libcudart.so.5.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.5.0; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.5.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.5.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.6.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.6.0; fi + if [ ! -f $(SIM_LIB_DIR)/libcudart.so.6.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.6.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.7.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.7.5; fi + $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib g++ -dynamiclib -Wl,-headerpad_max_install_names,-undefined,dynamic_lookup,-compatibility_version,1.1,-current_version,1.1\ $(SIM_OBJ_FILES_DIR)/libcuda/*.o \ diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 910bebd..e7a534e 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1519,7 +1519,7 @@ cuobjdumpELFSection* findELFSection(const std::string identifier){ if (sec!=NULL)return sec; sec = findELFSectionInList(libSectionList, identifier); if (sec!=NULL)return sec; - std::cout << "Cound not find " << identifier << std::endl; + std::cout << "Could not find " << identifier << std::endl; assert(0 && "Could not find the required ELF section"); return NULL; } @@ -1546,7 +1546,7 @@ cuobjdumpPTXSection* findPTXSection(const std::string identifier){ if (sec!=NULL)return sec; sec = findPTXSectionInList(libSectionList, identifier); if (sec!=NULL)return sec; - std::cout << "Cound not find " << identifier << std::endl; + std::cout << "Could not find " << identifier << std::endl; assert(0 && "Could not find the required PTX section"); return NULL; } -- cgit v1.3 From e6d1487acd58c7db0fc260447ac256a4f71f6916 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Fri, 26 Sep 2014 12:41:58 -0400 Subject: ADD: support ptxinfo for sm_35 and cuda 6.5 --- src/cuda-sim/ptx.l | 1 + src/cuda-sim/ptx.y | 2 ++ src/cuda-sim/ptxinfo.y | 4 ++++ 3 files changed, 7 insertions(+) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index dfed936..58bdf3d 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -180,6 +180,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.union TC; return UNION_DIRECTIVE; /* not in PTX 2.1 */ \.version TC; return VERSION_DIRECTIVE; \.visible TC; return VISIBLE_DIRECTIVE; +\.weak TC; return WEAK_DIRECTIVE; \.address_size TC; return ADDRESS_SIZE_DIRECTIVE; \.constptr TC; return CONSTPTR_DIRECTIVE; /* Ptx plus directive for pointer to constant memory */ diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 79faddf..2f85213 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -71,6 +71,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token VERSION_DIRECTIVE %token ADDRESS_SIZE_DIRECTIVE %token VISIBLE_DIRECTIVE +%token WEAK_DIRECTIVE %token IDENTIFIER %token INT_OPERAND %token FLOAT_OPERAND @@ -243,6 +244,7 @@ function_decl_header: ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".ent | FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } | VISIBLE_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } | EXTERN_DIRECTIVE FUNC_DIRECTIVE { $$ = 2; g_func_decl=1; func_header(".func"); } + | WEAK_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } ; param_list: /*empty*/ diff --git a/src/cuda-sim/ptxinfo.y b/src/cuda-sim/ptxinfo.y index 294412d..1233da4 100644 --- a/src/cuda-sim/ptxinfo.y +++ b/src/cuda-sim/ptxinfo.y @@ -85,6 +85,7 @@ line: HEADER INFO COLON line_info line_info: function_name | function_info { ptxinfo_addinfo(); } + | gmem_info ; function_name: FUNC QUOTE IDENTIFIER QUOTE { ptxinfo_function($3); } @@ -95,6 +96,9 @@ function_info: info | function_info COMMA info ; +gmem_info: INT_OPERAND BYTES GMEM + ; + info: USED INT_OPERAND REGS { ptxinfo_regs($2); } | tuple LMEM { ptxinfo_lmem(g_declared,g_system); } | tuple SMEM { ptxinfo_smem(g_declared,g_system); } -- cgit v1.3 From 0c5684afcd55e8352fe4b05d9c75a54593417b5f Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Mon, 29 Sep 2014 14:24:55 -0400 Subject: BUG: cuobjdump for sm_35 with CDP --- libcuda/cuda_runtime_api.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index e7a534e..bdfc47c 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1326,7 +1326,8 @@ void extract_code_using_cuobjdump(){ printf("Running md5sum using \"%s\"\n", command); system(command); // Running cuobjdump using dynamic link to current process - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass %s > %s", app_binary.c_str(), fname); + // Needs the option '-all' to extract PTX from CDP-enabled binary + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); bool parse_output = true; int result = system(command); if(result) { -- cgit v1.3 From e340759d5d886661722e978912b28cd1259c00ec Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Mon, 29 Sep 2014 14:26:42 -0400 Subject: MOD: Hack warning for cuda device runtime lib function registration --- libcuda/cuda_runtime_api.cc | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index bdfc47c..5dc9cc1 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -260,10 +260,20 @@ struct CUctx_st { { if( m_code.find(fat_cubin_handle) != m_code.end() ) { symbol *s = m_code[fat_cubin_handle]->lookup(deviceFun); - assert( s != NULL ); - function_info *f = s->get_pc(); - assert( f != NULL ); - m_kernel_lookup[hostFun] = f; + if(s != NULL) { + function_info *f = s->get_pc(); + assert( f != NULL ); + m_kernel_lookup[hostFun] = f; + } + else { + m_code[fat_cubin_handle]->dump(); + printf("Warning: cannot find deviceFun %s\n", deviceFun); + m_kernel_lookup[hostFun] = NULL; + } + // assert( s != NULL ); + // function_info *f = s->get_pc(); + // assert( f != NULL ); + // m_kernel_lookup[hostFun] = f; } else { m_kernel_lookup[hostFun] = NULL; } -- cgit v1.3 From 5cc6392a98bf736a05ffa7c7c557c4556753c8c2 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Wed, 1 Oct 2014 23:23:51 -0400 Subject: ADD: handle child kernel name in mov instruction. ADD: detect call cudaGetParameterBufferV2 and call cudaLaunchDeviceV2 --- libcuda/cuda_runtime_api.cc | 1 - src/cuda-sim/instructions.cc | 13 ++++++++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 5dc9cc1..5310a52 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -266,7 +266,6 @@ struct CUctx_st { m_kernel_lookup[hostFun] = f; } else { - m_code[fat_cubin_handle]->dump(); printf("Warning: cannot find deviceFun %s\n", deviceFun); m_kernel_lookup[hostFun] = NULL; } diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index cf7f04a..254427b 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -148,6 +148,9 @@ ptx_reg_t ptx_thread_info::get_operand_value( const operand_info &op, operand_in result.u64 = op.get_symbol()->get_address(); } else if ( op.is_local() ) { result.u64 = op.get_symbol()->get_address(); + } else if ( op.is_function_address() ) { + result.u64 = op.get_symbol()->get_pc()->get_start_PC(); + printf("Get pc for kernel function %u\n", op.get_symbol()->get_pc()->get_start_PC()); } else { const char *name = op.name().c_str(); printf("GPGPU-Sim PTX: ERROR ** get_operand_value : unknown operand type for %s\n", name ); @@ -1407,7 +1410,15 @@ void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) if( fname == "vprintf" ) { gpgpusim_cuda_vprintf(pI, thread, target_func); return; - } + } + else if(fname == "cudaGetParameterBufferV2") { + printf("calling cudaGetParameterBufferV2\n"); + return; + } + else if(fname == "cudaLaunchDeviceV2") { + printf("calling cudaLaunchDeviceV2\n"); + return; + } // read source arguements into register specified in declaration of function arg_buffer_list_t arg_values; -- cgit v1.3 From db5fe9600dd57ce59864b0f22c9d5407231ab5b1 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Fri, 3 Oct 2014 19:08:39 -0400 Subject: ADD: initial support for instruction group used by CDP --- cuobjdump_to_ptxplus/ptx_parser.h | 5 +++++ src/cuda-sim/ptx.y | 4 ++-- src/cuda-sim/ptx_ir.cc | 40 +++++++++++++++++++++++++++++++++++++++ src/cuda-sim/ptx_ir.h | 9 +++++++++ src/cuda-sim/ptx_parser.cc | 11 +++++++++++ src/cuda-sim/ptx_parser.h | 4 ++++ 6 files changed, 71 insertions(+), 2 deletions(-) diff --git a/cuobjdump_to_ptxplus/ptx_parser.h b/cuobjdump_to_ptxplus/ptx_parser.h index 1c96b46..418a733 100644 --- a/cuobjdump_to_ptxplus/ptx_parser.h +++ b/cuobjdump_to_ptxplus/ptx_parser.h @@ -110,6 +110,11 @@ void add_alignment_spec( int ) {PTX_PARSE_DPRINTF(" ");} void add_pragma( const char *a ) {PTX_PARSE_DPRINTF(" ");} void add_constptr(const char* identifier1, const char* identifier2, int offset) {PTX_PARSE_DPRINTF(" ");} +//Jin: handle instructino group for cdp +void start_inst_group(){PTX_PARSE_DPRINTF(" ");}; +void end_inst_group(){PTX_PARSE_DPRINTF(" ");}; + + /*non-dummy stuff below this point*/ extern cuobjdumpInstList *g_headerList; diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 2f85213..c8208ea 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -270,8 +270,8 @@ statement_list: directive_statement { add_directive(); } | instruction_statement { add_instruction(); } | statement_list directive_statement { add_directive(); } | statement_list instruction_statement { add_instruction(); } - | statement_list statement_block - | statement_block + | statement_list {start_inst_group();} statement_block {end_inst_group();} + | {start_inst_group();} statement_block {end_inst_group();} ; directive_statement: variable_declaration SEMI_COLON diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 751b3f4..915c623 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -90,6 +90,11 @@ symbol_table::symbol_table( const char *scope_name, unsigned entry_point, symbol m_const_next = 0; m_global_next = 0x100; m_local_next = 0; + m_tex_next = 0; + + //Jin: handle instruction group for cdp + m_inst_group_id = 0; + m_parent = parent; if ( m_parent ) { m_shared_next = m_parent->m_shared_next; @@ -170,6 +175,41 @@ void symbol_table::add_function( function_info *func, const char *filename, unsi m_symbols[ func->get_name() ] = s; } +//Jin: handle instruction group for cdp +symbol_table* symbol_table::start_inst_group() { + char inst_group_name[1024]; + snprintf(inst_group_name, 1024, "%s_inst_group_%u", m_scope_name.c_str(), m_inst_group_id); + + //previous added + assert(m_inst_group_symtab.find(std::string(inst_group_name)) == m_inst_group_symtab.end()); + symbol_table *sym_table = new symbol_table(inst_group_name, 3/*inst group*/, this ); + + sym_table->m_global_next = m_global_next; + sym_table->m_shared_next = m_shared_next; + sym_table->m_local_next = m_local_next; + sym_table->m_reg_allocator = m_reg_allocator; + sym_table->m_tex_next = m_tex_next; + sym_table->m_const_next = m_const_next; + + m_inst_group_symtab[std::string(inst_group_name)] = sym_table; + + return sym_table; +} + +symbol_table * symbol_table::end_inst_group() { + symbol_table * sym_table = m_parent; + + sym_table->m_global_next = m_global_next; + sym_table->m_shared_next = m_shared_next; + sym_table->m_local_next = m_local_next; + sym_table->m_reg_allocator = m_reg_allocator; + sym_table->m_tex_next = m_tex_next; + sym_table->m_const_next = m_const_next; + sym_table->m_inst_group_id++; + + return sym_table; +} + void register_ptx_function( const char *name, function_info *impl ); // either libcuda or libopencl bool symbol_table::add_function_decl( const char *name, int entry_point, function_info **func_info, symbol_table **sym_table ) diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 601a13d..7325e5f 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -330,6 +330,11 @@ public: iterator const_iterator_end() { return m_consts.end();} void dump(); + + //Jin: handle instruction group for cdp + symbol_table* start_inst_group(); + symbol_table* end_inst_group(); + private: unsigned m_reg_allocator; unsigned m_shared_next; @@ -347,6 +352,10 @@ private: std::list m_consts; std::map m_function_info_lookup; std::map m_function_symtab_lookup; + + //Jin: handle instruction group for cdp + unsigned m_inst_group_id; + std::map m_inst_group_symtab; }; class operand_info { diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index 824714a..39257da 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -187,6 +187,17 @@ void add_function_name( const char *name ) g_global_symbol_table->add_function( g_func_info, g_filename, ptx_lineno ); } +//Jin: handle instruction group for cdp +void start_inst_group() { + PTX_PARSE_DPRINTF("start_instruction_group"); + g_current_symbol_table = g_current_symbol_table->start_inst_group(); +} + +void end_inst_group() { + PTX_PARSE_DPRINTF("end_instruction_group"); + g_current_symbol_table = g_current_symbol_table->end_inst_group(); +} + void add_directive() { PTX_PARSE_DPRINTF("add_directive"); diff --git a/src/cuda-sim/ptx_parser.h b/src/cuda-sim/ptx_parser.h index fef7635..32f3903 100644 --- a/src/cuda-sim/ptx_parser.h +++ b/src/cuda-sim/ptx_parser.h @@ -94,6 +94,10 @@ void change_operand_neg( ); void set_immediate_operand_type( ); void version_header(double a); +//Jin: handle instructino group for cdp +void start_inst_group(); +void end_inst_group(); + #define NON_ARRAY_IDENTIFIER 1 #define ARRAY_IDENTIFIER_NO_DIM 2 #define ARRAY_IDENTIFIER 3 -- cgit v1.3 From 70e02ee5283cb96f0edcb46a15edf0ab6e1d0697 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Mon, 13 Oct 2014 18:58:37 -0400 Subject: ADD: add cudaGetParameterBufferV2 and add cudaLaunchDeviceV2 implementation. Kernel launch to stream not yet implemented --- src/cuda-sim/Makefile | 3 +- src/cuda-sim/cuda-sim.cc | 10 +++ src/cuda-sim/cuda_device_runtime.cc | 175 ++++++++++++++++++++++++++++++++++++ src/cuda-sim/cuda_device_runtime.h | 7 ++ src/cuda-sim/instructions.cc | 12 ++- src/cuda-sim/ptx_ir.h | 4 +- src/cuda-sim/ptx_parser.cc | 14 +++ 7 files changed, 219 insertions(+), 6 deletions(-) create mode 100644 src/cuda-sim/cuda_device_runtime.cc create mode 100644 src/cuda-sim/cuda_device_runtime.h diff --git a/src/cuda-sim/Makefile b/src/cuda-sim/Makefile index 166e256..f479294 100644 --- a/src/cuda-sim/Makefile +++ b/src/cuda-sim/Makefile @@ -62,7 +62,7 @@ ifeq ($(GNUC_CPP0X),1) endif endif -OBJS := $(OUTPUT_DIR)/ptx_parser.o $(OUTPUT_DIR)/ptx_loader.o $(OUTPUT_DIR)/cuda_device_printf.o $(OUTPUT_DIR)/instructions.o $(OUTPUT_DIR)/cuda-sim.o $(OUTPUT_DIR)/ptx_ir.o $(OUTPUT_DIR)/ptx_sim.o $(OUTPUT_DIR)/memory.o $(OUTPUT_DIR)/ptx-stats.o $(OUTPUT_DIR)/decuda_pred_table/decuda_pred_table.o $(OUTPUT_DIR)/ptx.tab.o $(OUTPUT_DIR)/lex.ptx_.o $(OUTPUT_DIR)/ptxinfo.tab.o $(OUTPUT_DIR)/lex.ptxinfo_.o +OBJS := $(OUTPUT_DIR)/ptx_parser.o $(OUTPUT_DIR)/ptx_loader.o $(OUTPUT_DIR)/cuda_device_printf.o $(OUTPUT_DIR)/instructions.o $(OUTPUT_DIR)/cuda-sim.o $(OUTPUT_DIR)/ptx_ir.o $(OUTPUT_DIR)/ptx_sim.o $(OUTPUT_DIR)/memory.o $(OUTPUT_DIR)/ptx-stats.o $(OUTPUT_DIR)/decuda_pred_table/decuda_pred_table.o $(OUTPUT_DIR)/ptx.tab.o $(OUTPUT_DIR)/lex.ptx_.o $(OUTPUT_DIR)/ptxinfo.tab.o $(OUTPUT_DIR)/lex.ptxinfo_.o $(OUTPUT_DIR)/cuda_device_runtime.o OPT += -DCUDART_VERSION=$(CUDART_VERSION) @@ -145,5 +145,6 @@ $(OUTPUT_DIR)/ptx_sim.o: $(OUTPUT_DIR)/ptx.tab.c $(OUTPUT_DIR)/cuda-sim.o: $(OUTPUT_DIR)/ptx.tab.c $(OUTPUT_DIR)/lex.ptxinfo_.o: $(OUTPUT_DIR)/ptx.tab.c $(OUTPUT_DIR)/lex.ptx_.o: $(OUTPUT_DIR)/ptx.tab.c +$(OUTPUT_DIR)/cuda_device_runtime.o: $(OUTPUT_DIR)/ptx.tab.c include $(OUTPUT_DIR)/Makefile.makedepend diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 715be98..4933029 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1065,6 +1065,16 @@ void function_info::add_param_data( unsigned argn, struct gpgpu_ptx_sim_arg *arg } } +unsigned function_info::get_args_aligned_size() { + unsigned int align_size = 4; // a word + unsigned int total_size = 0; + for(unsigned int i = 0; i < num_args(); i++) { + total_size += ((m_args[i]->get_size_in_bytes() + align_size - 1) / align_size) * align_size; + } + return total_size; +} + + void function_info::finalize( memory_space *param_mem ) { unsigned param_address = 0; diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc new file mode 100644 index 0000000..937eec8 --- /dev/null +++ b/src/cuda-sim/cuda_device_runtime.cc @@ -0,0 +1,175 @@ +//Jin: cuda_device_runtime.cc +//Defines CUDA device runtime APIs for CDP support + +#include +#include + +#define __CUDA_RUNTIME_API_H__ + +#include +#include +#include "../gpgpu-sim/gpu-sim.h" +#include "cuda-sim.h" +#include "ptx_ir.h" +#include "../stream_manager.h" +#include "cuda_device_runtime.h" + +#define DEV_RUNTIME_REPORT(a) \ + if( g_debug_execution ) { \ + std::cout << __FILE__ << ", " << __LINE__ << ": " << a << "\n"; \ + std::cout.flush(); \ + } + +std::map g_cuda_device_launch_map; +struct CUstream_st * g_device_default_stream = NULL; +extern stream_manager *g_stream_manager; + +//Handling device runtime api: +//void * cudaGetParameterBufferV2(void *func, dim3 gridDimension, dim3 blockDimension, unsigned int sharedMemSize) +void gpgpusim_cuda_getParameterBufferV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func) +{ + DEV_RUNTIME_REPORT("Calling cudaGetParameterBufferV2"); + + unsigned n_return = target_func->has_return(); + assert(n_return); + unsigned n_args = target_func->num_args(); + assert( n_args == 4 ); + + function_info * child_kernel_entry; + struct dim3 gridDim, blockDim; + unsigned int sharedMem; + + for( unsigned arg=0; arg < n_args; arg ++ ) { + const operand_info &actual_param_op = pI->operand_lookup(n_return+1+arg); //param# + const symbol *formal_param = target_func->get_arg(arg); //cudaGetParameterBufferV2_param_# + unsigned size=formal_param->get_size_in_bytes(); + assert( formal_param->is_param_local() ); + assert( actual_param_op.is_param_local() ); + addr_t from_addr = actual_param_op.get_symbol()->get_address(); + + if(arg == 0) {//function_info* for the child kernel + unsigned long long buf; + assert(size == sizeof(function_info *)); + thread->m_local_mem->read(from_addr, size, &buf); + child_kernel_entry = (function_info *)buf; + assert(child_kernel_entry); + DEV_RUNTIME_REPORT("child kernel name " << child_kernel_entry->get_name()); + } + else if(arg == 1) { //dim3 gridDim for the child kernel + assert(size == sizeof(struct dim3)); + thread->m_local_mem->read(from_addr, size, & gridDim); + DEV_RUNTIME_REPORT("grid (" << gridDim.x << ", " << gridDim.y << ", " << gridDim.z << ")"); + } + else if(arg == 2) { //dim3 blockDim for the child kernel + assert(size == sizeof(struct dim3)); + thread->m_local_mem->read(from_addr, size, & blockDim); + DEV_RUNTIME_REPORT("block (" << blockDim.x << ", " << blockDim.y << ", " << blockDim.z << ")"); + } + else if(arg == 3) { //unsigned int sharedMem + assert(size == sizeof(unsigned int)); + thread->m_local_mem->read(from_addr, size, & sharedMem); + DEV_RUNTIME_REPORT("shared memory " << sharedMem); + } + } + + //get total child kernel argument size and malloc buffer in global memory + unsigned child_kernel_arg_size = child_kernel_entry->get_args_aligned_size(); + void * param_buffer = thread->get_gpu()->gpu_malloc(child_kernel_arg_size); + DEV_RUNTIME_REPORT("child kernel arg size total " << child_kernel_arg_size << ", parameter buffer allocated at " << param_buffer); + + //create child kernel_info_t and index it with parameter_buffer address + kernel_info_t * child_grid = new kernel_info_t(gridDim, blockDim, child_kernel_entry); + assert(g_cuda_device_launch_map.find(param_buffer) == g_cuda_device_launch_map.end()); + g_cuda_device_launch_map[param_buffer] = child_grid; + + //copy the buffer address to retval0 + const operand_info &actual_return_op = pI->operand_lookup(0); //retval0 + const symbol *formal_return = target_func->get_return_var(); //void * + unsigned int return_size = formal_return->get_size_in_bytes(); + DEV_RUNTIME_REPORT("cudaGetParameterBufferV2 return value has size of " << return_size); + assert(actual_return_op.is_param_local()); + assert(actual_return_op.get_symbol()->get_size_in_bytes() == return_size && return_size == sizeof(void *)); + addr_t ret_param_addr = actual_return_op.get_symbol()->get_address(); + thread->m_local_mem->write(ret_param_addr, return_size, ¶m_buffer, NULL, NULL); + +} + +//Handling device runtime api: +//cudaError_t cudaLaunchDeviceV2(void *parameterBuffer, cudaStream_t stream) +void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func) { + DEV_RUNTIME_REPORT("Calling cudaLaunchDeviceV2"); + + unsigned n_return = target_func->has_return(); + assert(n_return); + unsigned n_args = target_func->num_args(); + assert( n_args == 2 ); + + kernel_info_t * child_grid = NULL; + function_info * child_kernel_entry = NULL; + void * parameter_buffer; + struct CUstream_st * child_stream; + for( unsigned arg=0; arg < n_args; arg ++ ) { + const operand_info &actual_param_op = pI->operand_lookup(n_return+1+arg); //param# + const symbol *formal_param = target_func->get_arg(arg); //cudaLaunchDeviceV2_param_# + unsigned size=formal_param->get_size_in_bytes(); + assert( formal_param->is_param_local() ); + assert( actual_param_op.is_param_local() ); + addr_t from_addr = actual_param_op.get_symbol()->get_address(); + + if(arg == 0) {//paramter buffer for child kernel (in global memory) + //get parameter_buffer from the cudaDeviceLaunchV2_param0 + assert(size == sizeof(void *)); + thread->m_local_mem->read(from_addr, size, ¶meter_buffer); + assert((size_t)parameter_buffer >= GLOBAL_HEAP_START); + DEV_RUNTIME_REPORT("Parameter buffer locating at global memory " << parameter_buffer); + + //get child grid info through parameter_buffer address + assert(g_cuda_device_launch_map.find(parameter_buffer) != g_cuda_device_launch_map.end()); + child_grid = g_cuda_device_launch_map[parameter_buffer]; + child_kernel_entry = child_grid->entry(); + DEV_RUNTIME_REPORT("find child kernel " << child_kernel_entry->get_name()); + + //copy data in parameter_buffer to child kernel param memory + unsigned child_kernel_arg_size = child_kernel_entry->get_args_aligned_size(); + DEV_RUNTIME_REPORT("child_kernel_arg_size " << child_kernel_arg_size); + memory_space *child_kernel_param_mem = child_grid->get_param_memory(); + size_t param_start_address = 0; + for(unsigned n = 0; n < child_kernel_arg_size; n++) { + unsigned char one_byte; + thread->get_gpu()->get_global_memory()->read((size_t)parameter_buffer + n, 1, &one_byte); + child_kernel_param_mem->write(param_start_address + n, 1, &one_byte, NULL, NULL); + } + } + else if(arg == 1) { //cudaStream for the child kernel + assert(size == sizeof(cudaStream_t)); + thread->m_local_mem->read(from_addr, size, &child_stream); + if(child_stream == 0) { //default stream on device + if(!g_device_default_stream) { + //g_device_default_stream = new struct CUstream_st(); + //g_stream_manager->add_stream(g_device_default_stream); + } + child_stream = g_device_default_stream; + } +// DEV_RUNTIME_REPORT("launching child kernel to stream " << child_stream->get_uid()); + } + + } + + //launch child kernel + stream_operation op(child_grid, g_ptx_sim_mode, child_stream); +// g_stream_manager->push(op); +// g_cuda_device_launch_map.erase(parameter_buffer); + + //set retval0 + const operand_info &actual_return_op = pI->operand_lookup(0); //retval0 + const symbol *formal_return = target_func->get_return_var(); //cudaError_t + unsigned int return_size = formal_return->get_size_in_bytes(); + DEV_RUNTIME_REPORT("cudaLaunchDeviceV2 return value has size of " << return_size); + assert(actual_return_op.is_param_local()); + assert(actual_return_op.get_symbol()->get_size_in_bytes() == return_size + && return_size == sizeof(cudaError_t)); + cudaError_t error = cudaSuccess; + addr_t ret_param_addr = actual_return_op.get_symbol()->get_address(); + thread->m_local_mem->write(ret_param_addr, return_size, &error, NULL, NULL); + +} diff --git a/src/cuda-sim/cuda_device_runtime.h b/src/cuda-sim/cuda_device_runtime.h new file mode 100644 index 0000000..1b10407 --- /dev/null +++ b/src/cuda-sim/cuda_device_runtime.h @@ -0,0 +1,7 @@ +//Jin: cuda_device_runtime.h +//Defines CUDA device runtime APIs for CDP support + +#pragma once + +void gpgpusim_cuda_getParameterBufferV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func); +void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func); diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 254427b..1c47ad3 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -41,6 +41,9 @@ #include "../gpgpu-sim/gpu-sim.h" #include "../gpgpu-sim/shader.h" +//Jin: include device runtime for CDP +#include "cuda_device_runtime.h" + #include unsigned ptx_instruction::g_num_ptx_inst_uid=0; @@ -149,8 +152,7 @@ ptx_reg_t ptx_thread_info::get_operand_value( const operand_info &op, operand_in } else if ( op.is_local() ) { result.u64 = op.get_symbol()->get_address(); } else if ( op.is_function_address() ) { - result.u64 = op.get_symbol()->get_pc()->get_start_PC(); - printf("Get pc for kernel function %u\n", op.get_symbol()->get_pc()->get_start_PC()); + result.u64 = (size_t)op.get_symbol()->get_pc(); } else { const char *name = op.name().c_str(); printf("GPGPU-Sim PTX: ERROR ** get_operand_value : unknown operand type for %s\n", name ); @@ -1411,12 +1413,14 @@ void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) gpgpusim_cuda_vprintf(pI, thread, target_func); return; } + + //Jin: handle device runtime apis for CDP else if(fname == "cudaGetParameterBufferV2") { - printf("calling cudaGetParameterBufferV2\n"); + gpgpusim_cuda_getParameterBufferV2(pI, thread, target_func); return; } else if(fname == "cudaLaunchDeviceV2") { - printf("calling cudaLaunchDeviceV2\n"); + gpgpusim_cuda_launchDeviceV2(pI, thread, target_func); return; } diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 7325e5f..a7ca27e 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -699,7 +699,7 @@ public: } bool is_immediate_address() const { - return m_immediate_address; + return m_immediate_address; } bool is_literal() const { return m_type == int_t || @@ -1209,6 +1209,8 @@ public: { return m_args.size(); } + unsigned get_args_aligned_size(); + const symbol* get_arg( unsigned n ) const { assert( n < m_args.size() ); diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index 39257da..baa3bcd 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -120,6 +120,20 @@ symbol_table *init_parser( const char *ptx_filename ) #define DEF(X,Y) g_ptx_token_decode[X] = Y; #include "ptx_parser_decode.def" #undef DEF + g_ptx_token_decode[undefined_space] = "undefined_space"; + g_ptx_token_decode[undefined_space] = "undefined_space=0"; + g_ptx_token_decode[reg_space] = "reg_space"; + g_ptx_token_decode[local_space] = "local_space"; + g_ptx_token_decode[shared_space] = "shared_space"; + g_ptx_token_decode[param_space_unclassified] = "param_space_unclassified"; + g_ptx_token_decode[param_space_kernel] = "param_space_kernel"; + g_ptx_token_decode[param_space_local] = "param_space_local"; + g_ptx_token_decode[const_space] = "const_space"; + g_ptx_token_decode[tex_space] = "tex_space"; + g_ptx_token_decode[surf_space] = "surf_space"; + g_ptx_token_decode[global_space] = "global_space"; + g_ptx_token_decode[generic_space] = "generic_space"; + g_ptx_token_decode[instruction_space] = "instruction_space"; return g_global_symbol_table; } -- cgit v1.3 From 582106ec595bb7745db092f2f4aa2b0fb9521b16 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Sat, 18 Oct 2014 23:07:53 -0400 Subject: MOD: add child kernel stream and scheduling support --- src/abstract_hardware_model.cc | 77 +++++++++++++++++++++++++++++++++++++ src/abstract_hardware_model.h | 39 +++++++++++++++++++ src/cuda-sim/cuda-sim.cc | 9 ++++- src/cuda-sim/cuda_device_runtime.cc | 31 +++++++++------ src/cuda-sim/ptx_sim.h | 3 ++ src/gpgpu-sim/gpu-sim.cc | 4 ++ src/gpgpu-sim/gpu-sim.h | 20 ++++++++++ src/gpgpusim_entrypoint.cc | 9 +++++ src/stream_manager.cc | 39 ++++++++++--------- 9 files changed, 199 insertions(+), 32 deletions(-) diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index 84d165c..b19b9d1 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -565,6 +565,10 @@ kernel_info_t::kernel_info_t( dim3 gridDim, dim3 blockDim, class function_info * m_num_cores_running=0; m_uid = m_next_uid++; m_param_mem = new memory_space_impl<8192>("param",64*1024); + + //Jin: parent and child kernel management for CDP + m_parent_kernel = NULL; + } kernel_info_t::~kernel_info_t() @@ -578,6 +582,79 @@ std::string kernel_info_t::name() const return m_kernel_entry->get_name(); } +//Jin: parent and child kernel management for CDP +void kernel_info_t::set_parent(kernel_info_t * parent, + dim3 parent_ctaid, dim3 parent_tid) { + m_parent_kernel = parent; + m_parent_ctaid = parent_ctaid; + m_parent_tid = parent_tid; + parent->set_child(this); +} + +void kernel_info_t::set_child(kernel_info_t * child) { + m_child_kernels.push_back(child); +} + +bool kernel_info_t::is_finished() { + if(done() && children_all_finished()) + return true; + else + return false; +} + +bool kernel_info_t::children_all_finished() { + for(auto child = m_child_kernels.begin(); child != m_child_kernels.end(); child++) + { + if(!(*child)->is_finished()) + return false; + } + return true; +} + +void kernel_info_t::notify_parent_finished() { + if(m_parent_kernel) { + g_stream_manager->register_finished_kernel(m_parent_kernel->get_uid()); + } +} + +CUstream_st * kernel_info_t::create_stream_cta(dim3 ctaid) { + assert(get_default_stream_cta(ctaid)); + CUstream_st * stream = new CUstream_st(); + g_stream_manager->add_stream(stream); + assert(m_cta_streams.find(ctaid) != m_cta_streams.end()); + assert(m_cta_streams[ctaid].size() >= 1); //must have default stream + m_cta_streams[ctaid].push_back(stream); + + return stream; +} + +CUstream_st * kernel_info_t::get_default_stream_cta(dim3 ctaid) { + if(m_cta_streams.find(ctaid) != m_cta_streams.end()) { + assert(m_cta_streams[ctaid].size() >= 1); //already created, must have default stream + return *(m_cta_streams[ctaid].begin()); + } + else { + m_cta_streams[ctaid] = std::list(); + CUstream_st * stream = new CUstream_st(); + g_stream_manager->add_stream(stream); + m_cta_streams[ctaid].push_back(stream); + return stream; + } +} + +bool kernel_info_t::cta_has_stream(dim3 ctaid, CUstream_st* stream) { + if(m_cta_streams.find(ctaid) == m_cta_streams.end()) + return false; + + std::list &stream_list = m_cta_streams[ctaid]; + if(std::find(stream_list.begin(), stream_list.end(), stream) + == stream_list.end()) + return false; + else + return true; +} + + simt_stack::simt_stack( unsigned wid, unsigned warpSize) { m_warp_id=wid; diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index ba4ea29..16f4b31 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -154,15 +154,35 @@ enum _memory_op_t { #include #include #include +#include #if !defined(__VECTOR_TYPES_H__) struct dim3 { unsigned int x, y, z; }; #endif +struct dim3comp { + bool operator() (const dim3 & a, const dim3 & b) const + { + if(a.z < b.z) + return true; + else if(a.y < b.y) + return true; + else if (a.x < b.x) + return true; + else + return false; + } +}; void increment_x_then_y_then_z( dim3 &i, const dim3 &bound); +//Jin: child kernel information for CDP +#include "stream_manager.h" +class stream_manager; +struct CUstream_st; +extern stream_manager * g_stream_manager; + class kernel_info_t { public: // kernel_info_t() @@ -250,6 +270,25 @@ private: std::list m_active_threads; class memory_space *m_param_mem; + +public: + //Jin: parent and child kernel management for CDP + void set_parent(kernel_info_t * parent, dim3 parent_ctaid, dim3 parent_tid); + void set_child(kernel_info_t * child); + bool is_finished(); + bool children_all_finished(); + void notify_parent_finished(); + CUstream_st * create_stream_cta(dim3 ctaid); + CUstream_st * get_default_stream_cta(dim3 ctaid); + bool cta_has_stream(dim3 ctaid, CUstream_st* stream); + +private: + kernel_info_t * m_parent_kernel; + dim3 m_parent_ctaid; + dim3 m_parent_tid; + std::list m_child_kernels; //child kernel launched + std::map< dim3, std::list, dim3comp > m_cta_streams; //streams created in each CTA + }; struct core_config { diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 4933029..482e3f6 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1762,8 +1762,13 @@ void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL ) extern stream_manager *g_stream_manager; //openCL kernel simulation calls don't register the kernel so we don't register its exit - if(!openCL) - g_stream_manager->register_finished_kernel(kernel.get_uid()); + if(!openCL) { + + //Jin: for CDP, children should be finished first + if(kernel.is_finished()) { + g_stream_manager->register_finished_kernel(kernel.get_uid()); + } + } //******PRINTING******* printf( "GPGPU-Sim: Done functional simulation (%u instructions simulated).\n", g_ptx_sim_num_insn ); diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc index 937eec8..4d8d1e1 100644 --- a/src/cuda-sim/cuda_device_runtime.cc +++ b/src/cuda-sim/cuda_device_runtime.cc @@ -21,8 +21,7 @@ } std::map g_cuda_device_launch_map; -struct CUstream_st * g_device_default_stream = NULL; -extern stream_manager *g_stream_manager; +extern stream_manager * g_stream_manager; //Handling device runtime api: //void * cudaGetParameterBufferV2(void *func, dim3 gridDimension, dim3 blockDimension, unsigned int sharedMemSize) @@ -78,7 +77,13 @@ void gpgpusim_cuda_getParameterBufferV2(const ptx_instruction * pI, ptx_thread_i DEV_RUNTIME_REPORT("child kernel arg size total " << child_kernel_arg_size << ", parameter buffer allocated at " << param_buffer); //create child kernel_info_t and index it with parameter_buffer address - kernel_info_t * child_grid = new kernel_info_t(gridDim, blockDim, child_kernel_entry); + kernel_info_t * child_grid = new kernel_info_t(gridDim, blockDim, child_kernel_entry); + kernel_info_t & parent_grid = thread->get_kernel(); + DEV_RUNTIME_REPORT("child kernel launched by " << parent_grid.name() << ", cta (" << + thread->get_ctaid().x << ", " << thread->get_ctaid().y << ", " << thread->get_ctaid().z << + "), thread (" << thread->get_tid().x << ", " << thread->get_tid().y << ", " << thread->get_tid().z << + ")"); + child_grid->set_parent(&parent_grid, thread->get_ctaid(), thread->get_tid()); assert(g_cuda_device_launch_map.find(param_buffer) == g_cuda_device_launch_map.end()); g_cuda_device_launch_map[param_buffer] = child_grid; @@ -137,28 +142,30 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * for(unsigned n = 0; n < child_kernel_arg_size; n++) { unsigned char one_byte; thread->get_gpu()->get_global_memory()->read((size_t)parameter_buffer + n, 1, &one_byte); + std::cout << "one byte " << std::hex << one_byte << "\n"; child_kernel_param_mem->write(param_start_address + n, 1, &one_byte, NULL, NULL); } } else if(arg == 1) { //cudaStream for the child kernel assert(size == sizeof(cudaStream_t)); thread->m_local_mem->read(from_addr, size, &child_stream); - if(child_stream == 0) { //default stream on device - if(!g_device_default_stream) { - //g_device_default_stream = new struct CUstream_st(); - //g_stream_manager->add_stream(g_device_default_stream); - } - child_stream = g_device_default_stream; + + kernel_info_t & parent_kernel = thread->get_kernel(); + if(child_stream == 0) { //default stream on device for current CTA + child_stream = parent_kernel.get_default_stream_cta(thread->get_ctaid()); + } + else { + assert(parent_kernel.cta_has_stream(thread->get_ctaid(), child_stream)); } -// DEV_RUNTIME_REPORT("launching child kernel to stream " << child_stream->get_uid()); + DEV_RUNTIME_REPORT("launching child kernel to stream " << child_stream->get_uid() << " " << child_stream); } } //launch child kernel stream_operation op(child_grid, g_ptx_sim_mode, child_stream); -// g_stream_manager->push(op); -// g_cuda_device_launch_map.erase(parameter_buffer); + g_stream_manager->push(op); + g_cuda_device_launch_map.erase(parameter_buffer); //set retval0 const operand_info &actual_return_op = pI->operand_lookup(0); //retval0 diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index f926e6d..ea171c5 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -418,6 +418,9 @@ public: void or_reduction(unsigned ctaid, unsigned barid, bool value) {m_core->or_reduction(ctaid,barid,value);} void popc_reduction(unsigned ctaid, unsigned barid, bool value) {m_core->popc_reduction(ctaid,barid,value);} + //Jin: get corresponding kernel grid for CDP purpose + kernel_info_t & get_kernel() { return m_kernel; } + public: addr_t m_last_effective_address; bool m_branch_taken; diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index eafb909..47dbc89 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -622,6 +622,10 @@ gpgpu_sim::gpgpu_sim( const gpgpu_sim_config &config ) *active_sms=0; last_liveness_message_time = 0; + + //Jin: functional simulation for CDP + m_functional_sim = false; + m_functional_sim_kernel = NULL; } int gpgpu_sim::shared_mem_size() const diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 33fffd3..a2d1b9b 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -492,6 +492,7 @@ private: std::string executed_kernel_info_string(); //< format the kernel information into a string for stat printout void clear_executed_kernel_info(); //< clear the kernel information after stat printout + public: unsigned long long gpu_sim_insn; unsigned long long gpu_tot_sim_insn; @@ -504,6 +505,25 @@ public: void change_cache_config(FuncCache cache_config); void set_cache_config(std::string kernel_name); + //Jin: functional simulation for CDP +private: + //set by stream operation every time a functoinal simulation is done + bool m_functional_sim; + kernel_info_t * m_functional_sim_kernel; + +public: + bool is_functional_sim() { return m_functional_sim; } + kernel_info_t * get_functional_kernel() { return m_functional_sim_kernel; } + void functional_launch(kernel_info_t * k) { + m_functional_sim = true; + m_functional_sim_kernel = k; + } + void finish_functional_sim(kernel_info_t * k) { + assert(m_functional_sim); + assert(m_functional_sim_kernel == k); + m_functional_sim = false; + m_functional_sim_kernel = NULL; + } }; #endif diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index 6ba38eb..31f3a41 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -127,6 +127,15 @@ void *gpgpu_sim_thread_concurrent(void*) if(g_stream_manager->operation(&sim_cycles) && !g_the_gpu->active()) break; + //functional simulation + if( g_the_gpu->is_functional_sim()) { + kernel_info_t * kernel = g_the_gpu->get_functional_kernel(); + assert(kernel); + gpgpu_cuda_ptx_sim_main_func(*kernel); + g_the_gpu->finish_functional_sim(kernel); + } + + //performance simulation if( g_the_gpu->active() ) { g_the_gpu->cycle(); sim_cycles = true; diff --git a/src/stream_manager.cc b/src/stream_manager.cc index dd42f0a..1f93c03 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -155,7 +155,7 @@ void stream_operation::do_operation( gpgpu_sim *gpu ) gpu->set_cache_config(m_kernel->name()); printf("kernel \'%s\' transfer to GPU hardware scheduler\n", m_kernel->name().c_str() ); if( m_sim_mode ) - gpgpu_cuda_ptx_sim_main_func( *m_kernel ); + gpu->functional_launch( m_kernel ); else gpu->launch( m_kernel ); } @@ -212,11 +212,9 @@ bool stream_manager::operation( bool * sim) bool stream_manager::check_finished_kernel() { - - unsigned grid_uid = m_gpu->finished_kernel(); - bool check=register_finished_kernel(grid_uid); - return check; - + unsigned grid_uid = m_gpu->finished_kernel(); + bool check=register_finished_kernel(grid_uid); + return check; } bool stream_manager::register_finished_kernel(unsigned grid_uid) @@ -226,13 +224,17 @@ bool stream_manager::register_finished_kernel(unsigned grid_uid) CUstream_st *stream = m_grid_id_to_stream[grid_uid]; kernel_info_t *kernel = stream->front().get_kernel(); assert( grid_uid == kernel->get_uid() ); - stream->record_next_done(); - m_grid_id_to_stream.erase(grid_uid); - delete kernel; - return true; - }else{ - return false; + + //Jin: should check children kernels for CDP + if(kernel->is_finished()) { + stream->record_next_done(); + m_grid_id_to_stream.erase(grid_uid); + kernel->notify_parent_finished(); + delete kernel; + return true; + } } + return false; } @@ -259,21 +261,22 @@ stream_operation stream_manager::front() { // called by gpu simulation thread stream_operation result; - if( concurrent_streams_empty() ) - m_service_stream_zero = true; +// if( concurrent_streams_empty() ) + m_service_stream_zero = true; if( m_service_stream_zero ) { - if( !m_stream_zero.empty() ) { - if( !m_stream_zero.busy() ) { + if( !m_stream_zero.empty() && !m_stream_zero.busy() ) { result = m_stream_zero.next(); if( result.is_kernel() ) { unsigned grid_id = result.get_kernel()->get_uid(); m_grid_id_to_stream[grid_id] = &m_stream_zero; } - } } else { m_service_stream_zero = false; } - } else { + } + + if(!m_service_stream_zero) + { std::list::iterator s; for( s=m_streams.begin(); s != m_streams.end(); s++) { CUstream_st *stream = *s; -- cgit v1.3 From d31c2da2b34d3d7a63d9980335c85d5e1a19ad02 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Sun, 19 Oct 2014 01:02:20 -0400 Subject: BUG: parameter alignment --- src/cuda-sim/cuda-sim.cc | 26 +++++++++++++++++++++----- src/cuda-sim/cuda_device_runtime.cc | 1 - 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 482e3f6..4281913 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1066,12 +1066,24 @@ void function_info::add_param_data( unsigned argn, struct gpgpu_ptx_sim_arg *arg } unsigned function_info::get_args_aligned_size() { - unsigned int align_size = 4; // a word + + unsigned param_address = 0; unsigned int total_size = 0; - for(unsigned int i = 0; i < num_args(); i++) { - total_size += ((m_args[i]->get_size_in_bytes() + align_size - 1) / align_size) * align_size; + for( std::map::iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { + param_info &p = i->second; + std::string name = p.get_name(); + symbol *param = m_symtab->lookup(name.c_str()); + + size_t arg_size = p.get_size(); // size of param in bytes + total_size = (total_size + arg_size - 1) / arg_size * arg_size; //aligned + p.add_offset(total_size); + param_address += total_size; + param->set_address(param_address); + total_size += arg_size; } - return total_size; + + return (total_size + 3) / 4; //final size aligned to word + } @@ -1097,13 +1109,17 @@ void function_info::finalize( memory_space *param_mem ) size = (size<(p.get_size()/8))?size:(p.get_size()/8); } // copy the parameter over word-by-word so that parameter that crosses a memory page can be copied over + //Jin: copy parameter using aligned rules const size_t word_size = 4; + param_address = (param_address + size - 1) / size * size; //aligned with size for (size_t idx = 0; idx < size; idx += word_size) { const char *pdata = reinterpret_cast(param_value.pdata) + idx; // cast to char * for ptr arithmetic param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); } + unsigned offset = p.get_offset(); + assert(offset == param_address); param->set_address(param_address); - param_address += size; + param_address += size; } } diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc index 4d8d1e1..148471b 100644 --- a/src/cuda-sim/cuda_device_runtime.cc +++ b/src/cuda-sim/cuda_device_runtime.cc @@ -142,7 +142,6 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * for(unsigned n = 0; n < child_kernel_arg_size; n++) { unsigned char one_byte; thread->get_gpu()->get_global_memory()->read((size_t)parameter_buffer + n, 1, &one_byte); - std::cout << "one byte " << std::hex << one_byte << "\n"; child_kernel_param_mem->write(param_start_address + n, 1, &one_byte, NULL, NULL); } } -- cgit v1.3 From 5fc7bf5872aad126a09cad4b385054c4b3a094aa Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Mon, 20 Oct 2014 17:19:32 -0400 Subject: BUG: do not handle cudaGetParameterBufferV2 and cudaLaunchDeviceV2 as call.uni in reconvergence --- src/abstract_hardware_model.h | 2 ++ src/cuda-sim/cuda-sim.cc | 6 ++++-- src/cuda-sim/ptx_ir.cc | 3 +++ 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 16f4b31..11fee10 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -864,6 +864,7 @@ public: m_mem_accesses_created=false; m_cache_hit=false; m_is_printf=false; + m_is_cdp = false; } virtual ~warp_inst_t(){ } @@ -1016,6 +1017,7 @@ protected: unsigned cycles; // used for implementing initiation interval delay bool m_isatomic; bool m_is_printf; + bool m_is_cdp; unsigned m_warp_id; unsigned m_dynamic_warp_id; const core_config *m_config; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 4281913..58bd4e0 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -638,7 +638,7 @@ void ptx_instruction::set_opcode_and_latency() case MEMBAR_OP: op = MEMORY_BARRIER_OP; break; case CALL_OP: { - if(m_is_printf) + if(m_is_printf || m_is_cdp) op = ALU_OP; else op = CALL_OPS; @@ -646,7 +646,7 @@ void ptx_instruction::set_opcode_and_latency() } case CALLP_OP: { - if(m_is_printf) + if(m_is_printf || m_is_cdp) op = ALU_OP; else op = CALL_OPS; @@ -1219,6 +1219,8 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) bool skip = false; int op_classification = 0; addr_t pc = next_instr(); + if(pc == 440) + pc = 440; assert( pc == inst.pc ); // make sure timing model and functional model are in sync const ptx_instruction *pI = m_func_info->get_instruction(pc); set_npc( pc + pI->inst_size() ); diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 915c623..861f0dc 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1241,6 +1241,9 @@ ptx_instruction::ptx_instruction( int opcode, if (fname =="vprintf"){ m_is_printf = true; } + if (fname == "cudaGetParameterBufferV2" + || fname == "cudaLaunchDeviceV2") + m_is_cdp = true; } } -- cgit v1.3 From 6286547cfdc5d14c84568505db267f5e8dd9841f Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Mon, 20 Oct 2014 23:23:00 -0400 Subject: BUG: multiple child kernels finish --- src/abstract_hardware_model.cc | 22 ++++++++++++++++++---- src/abstract_hardware_model.h | 2 ++ src/cuda-sim/cuda-sim.cc | 6 +----- src/stream_manager.cc | 3 ++- 4 files changed, 23 insertions(+), 10 deletions(-) diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index b19b9d1..f3c5b21 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -595,6 +595,12 @@ void kernel_info_t::set_child(kernel_info_t * child) { m_child_kernels.push_back(child); } +void kernel_info_t::remove_child(kernel_info_t * child) { + assert(std::find(m_child_kernels.begin(), m_child_kernels.end(), child) + != m_child_kernels.end()); + m_child_kernels.remove(child); +} + bool kernel_info_t::is_finished() { if(done() && children_all_finished()) return true; @@ -603,16 +609,15 @@ bool kernel_info_t::is_finished() { } bool kernel_info_t::children_all_finished() { - for(auto child = m_child_kernels.begin(); child != m_child_kernels.end(); child++) - { - if(!(*child)->is_finished()) + if(!m_child_kernels.empty()) return false; - } + return true; } void kernel_info_t::notify_parent_finished() { if(m_parent_kernel) { + m_parent_kernel->remove_child(this); g_stream_manager->register_finished_kernel(m_parent_kernel->get_uid()); } } @@ -654,6 +659,15 @@ bool kernel_info_t::cta_has_stream(dim3 ctaid, CUstream_st* stream) { return true; } +void kernel_info_t::print_parent_info() { + if(m_parent_kernel) { + printf("Parent %d: \'%s\', Block (%d, %d, %d), Thread (%d, %d, %d)\n", + m_parent_kernel->get_uid(), m_parent_kernel->name().c_str(), + m_parent_ctaid.x, m_parent_ctaid.y, m_parent_ctaid.z, + m_parent_tid.x, m_parent_tid.y, m_parent_tid.z); + } +} + simt_stack::simt_stack( unsigned wid, unsigned warpSize) { diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 11fee10..a0bf80d 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -275,12 +275,14 @@ public: //Jin: parent and child kernel management for CDP void set_parent(kernel_info_t * parent, dim3 parent_ctaid, dim3 parent_tid); void set_child(kernel_info_t * child); + void remove_child(kernel_info_t * child); bool is_finished(); bool children_all_finished(); void notify_parent_finished(); CUstream_st * create_stream_cta(dim3 ctaid); CUstream_st * get_default_stream_cta(dim3 ctaid); bool cta_has_stream(dim3 ctaid, CUstream_st* stream); + void print_parent_info(); private: kernel_info_t * m_parent_kernel; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 58bd4e0..8dd1078 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1781,11 +1781,7 @@ void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL ) //openCL kernel simulation calls don't register the kernel so we don't register its exit if(!openCL) { - - //Jin: for CDP, children should be finished first - if(kernel.is_finished()) { - g_stream_manager->register_finished_kernel(kernel.get_uid()); - } + g_stream_manager->register_finished_kernel(kernel.get_uid()); } //******PRINTING******* diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 1f93c03..687d544 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -153,7 +153,8 @@ void stream_operation::do_operation( gpgpu_sim *gpu ) case stream_kernel_launch: if( gpu->can_start_kernel() ) { gpu->set_cache_config(m_kernel->name()); - printf("kernel \'%s\' transfer to GPU hardware scheduler\n", m_kernel->name().c_str() ); + printf("kernel %d: \'%s\' transfer to GPU hardware scheduler\n", m_kernel->get_uid(), m_kernel->name().c_str() ); + m_kernel->print_parent_info(); if( m_sim_mode ) gpu->functional_launch( m_kernel ); else -- cgit v1.3 From 3bb32d87175d873e7089ad50a0069acc195edb34 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Tue, 21 Oct 2014 01:24:26 -0400 Subject: ADD: add support for cudaStreamCreateWithFlags --- src/cuda-sim/cuda_device_runtime.cc | 61 ++++++++++++++++++++++++++++++++++++- src/cuda-sim/cuda_device_runtime.h | 1 + src/cuda-sim/instructions.cc | 4 +++ src/cuda-sim/ptx_ir.cc | 3 +- 4 files changed, 67 insertions(+), 2 deletions(-) diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc index 148471b..be87f6a 100644 --- a/src/cuda-sim/cuda_device_runtime.cc +++ b/src/cuda-sim/cuda_device_runtime.cc @@ -152,11 +152,12 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * kernel_info_t & parent_kernel = thread->get_kernel(); if(child_stream == 0) { //default stream on device for current CTA child_stream = parent_kernel.get_default_stream_cta(thread->get_ctaid()); + DEV_RUNTIME_REPORT("launching child kernel to default stream of the cta " << child_stream->get_uid() << ": " << child_stream); } else { assert(parent_kernel.cta_has_stream(thread->get_ctaid(), child_stream)); + DEV_RUNTIME_REPORT("launching child kernel to stream " << child_stream->get_uid() << ": " << child_stream); } - DEV_RUNTIME_REPORT("launching child kernel to stream " << child_stream->get_uid() << " " << child_stream); } } @@ -179,3 +180,61 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * thread->m_local_mem->write(ret_param_addr, return_size, &error, NULL, NULL); } + + +//Handling device runtime api: +//cudaError_t cudaStreamCreateWithFlags ( cudaStream_t* pStream, unsigned int flags) +//flags can only be cudaStreamNonBlocking +void gpgpusim_cuda_streamCreateWithFlags(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func) { + DEV_RUNTIME_REPORT("Calling cudaStreamCreateWithFlags"); + + unsigned n_return = target_func->has_return(); + assert(n_return); + unsigned n_args = target_func->num_args(); + assert( n_args == 2 ); + + size_t generic_pStream_addr; + addr_t pStream_addr; + unsigned int flags; + for( unsigned arg=0; arg < n_args; arg ++ ) { + const operand_info &actual_param_op = pI->operand_lookup(n_return+1+arg); //param# + const symbol *formal_param = target_func->get_arg(arg); //cudaStreamCreateWithFlags_param_# + unsigned size=formal_param->get_size_in_bytes(); + assert( formal_param->is_param_local() ); + assert( actual_param_op.is_param_local() ); + addr_t from_addr = actual_param_op.get_symbol()->get_address(); + + if(arg == 0) {//cudaStream_t * pStream, address of cudaStream_t + assert(size == sizeof(cudaStream_t *)); + thread->m_local_mem->read(from_addr, size, &generic_pStream_addr); + + //pStream should be non-zero address in local memory + pStream_addr = generic_to_local(thread->get_hw_sid(), thread->get_hw_tid(), generic_pStream_addr); + + DEV_RUNTIME_REPORT("pStream locating at local memory " << pStream_addr); + } + else if(arg == 1) { //unsigned int flags, should be cudaStreamNonBlocking + assert(size == sizeof(unsigned int)); + thread->m_local_mem->read(from_addr, size, &flags); + assert(flags == cudaStreamNonBlocking); + } + } + + //create stream and write back to param0 + CUstream_st * stream = thread->get_kernel().create_stream_cta(thread->get_ctaid()); + DEV_RUNTIME_REPORT("Create stream " << stream->get_uid() << ": " << stream); + thread->m_local_mem->write(pStream_addr, sizeof(cudaStream_t), &stream, NULL, NULL); + + //set retval0 + const operand_info &actual_return_op = pI->operand_lookup(0); //retval0 + const symbol *formal_return = target_func->get_return_var(); //cudaError_t + unsigned int return_size = formal_return->get_size_in_bytes(); + DEV_RUNTIME_REPORT("cudaStreamCreateWithFlags return value has size of " << return_size); + assert(actual_return_op.is_param_local()); + assert(actual_return_op.get_symbol()->get_size_in_bytes() == return_size + && return_size == sizeof(cudaError_t)); + cudaError_t error = cudaSuccess; + addr_t ret_param_addr = actual_return_op.get_symbol()->get_address(); + thread->m_local_mem->write(ret_param_addr, return_size, &error, NULL, NULL); + +} diff --git a/src/cuda-sim/cuda_device_runtime.h b/src/cuda-sim/cuda_device_runtime.h index 1b10407..7447d5a 100644 --- a/src/cuda-sim/cuda_device_runtime.h +++ b/src/cuda-sim/cuda_device_runtime.h @@ -5,3 +5,4 @@ void gpgpusim_cuda_getParameterBufferV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func); void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func); +void gpgpusim_cuda_streamCreateWithFlags(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func); diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 1c47ad3..5d909d3 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1423,6 +1423,10 @@ void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) gpgpusim_cuda_launchDeviceV2(pI, thread, target_func); return; } + else if(fname == "cudaStreamCreateWithFlags") { + gpgpusim_cuda_streamCreateWithFlags(pI, thread, target_func); + return; + } // read source arguements into register specified in declaration of function arg_buffer_list_t arg_values; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 861f0dc..bdc8381 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1242,7 +1242,8 @@ ptx_instruction::ptx_instruction( int opcode, m_is_printf = true; } if (fname == "cudaGetParameterBufferV2" - || fname == "cudaLaunchDeviceV2") + || fname == "cudaLaunchDeviceV2" + || fname == "cudaStreamCreateWithFlags") m_is_cdp = true; } -- cgit v1.3 From f372a4c641b9e6d38470ead6ae25743d26c5fed1 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Thu, 23 Oct 2014 15:33:59 -0400 Subject: BUG: kernels should return to stream if not pushed to concurrent kernel pool --- src/cuda-sim/cuda_device_runtime.cc | 8 +++++--- src/gpgpu-sim/shader.cc | 3 ++- src/stream_manager.cc | 37 ++++++++++++++++++++++++++++++++----- src/stream_manager.h | 3 ++- 4 files changed, 41 insertions(+), 10 deletions(-) diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc index be87f6a..c53ea04 100644 --- a/src/cuda-sim/cuda_device_runtime.cc +++ b/src/cuda-sim/cuda_device_runtime.cc @@ -122,7 +122,7 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * addr_t from_addr = actual_param_op.get_symbol()->get_address(); if(arg == 0) {//paramter buffer for child kernel (in global memory) - //get parameter_buffer from the cudaDeviceLaunchV2_param0 + //get parameter_buffer from the cudaLaunchDeviceV2_param0 assert(size == sizeof(void *)); thread->m_local_mem->read(from_addr, size, ¶meter_buffer); assert((size_t)parameter_buffer >= GLOBAL_HEAP_START); @@ -152,11 +152,13 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * kernel_info_t & parent_kernel = thread->get_kernel(); if(child_stream == 0) { //default stream on device for current CTA child_stream = parent_kernel.get_default_stream_cta(thread->get_ctaid()); - DEV_RUNTIME_REPORT("launching child kernel to default stream of the cta " << child_stream->get_uid() << ": " << child_stream); + DEV_RUNTIME_REPORT("launching child kernel " << child_grid->get_uid() << + " to default stream of the cta " << child_stream->get_uid() << ": " << child_stream); } else { assert(parent_kernel.cta_has_stream(thread->get_ctaid(), child_stream)); - DEV_RUNTIME_REPORT("launching child kernel to stream " << child_stream->get_uid() << ": " << child_stream); + DEV_RUNTIME_REPORT("launching child kernel " << child_grid->get_uid() << + " to stream " << child_stream->get_uid() << ": " << child_stream); } } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index ff2fac7..de5bcf6 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1934,7 +1934,8 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num ) m_kernel->name().c_str() ); if( !m_gpu->kernel_more_cta_left(m_kernel) ) { if( !m_kernel->running() ) { - printf("GPGPU-Sim uArch: GPU detected kernel \'%s\' finished on shader %u.\n", m_kernel->name().c_str(), m_sid ); + printf("GPGPU-Sim uArch: GPU detected kernel %u \'%s\' finished on shader %u.\n", m_kernel->get_uid(), + m_kernel->name().c_str(), m_sid ); m_gpu->set_kernel_done( m_kernel ); } } diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 687d544..546ab3b 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -95,6 +95,15 @@ stream_operation CUstream_st::next() return result; } +void CUstream_st::cancel_front() +{ + pthread_mutex_lock(&m_lock); + assert(m_pending); + m_pending = false; + pthread_mutex_unlock(&m_lock); + +} + void CUstream_st::print(FILE *fp) { pthread_mutex_lock(&m_lock); @@ -111,10 +120,10 @@ void CUstream_st::print(FILE *fp) } -void stream_operation::do_operation( gpgpu_sim *gpu ) +bool stream_operation::do_operation( gpgpu_sim *gpu ) { if( is_noop() ) - return; + return true; assert(!m_done && m_stream); if(g_debug_execution >= 3) @@ -153,16 +162,23 @@ void stream_operation::do_operation( gpgpu_sim *gpu ) case stream_kernel_launch: if( gpu->can_start_kernel() ) { gpu->set_cache_config(m_kernel->name()); - printf("kernel %d: \'%s\' transfer to GPU hardware scheduler\n", m_kernel->get_uid(), m_kernel->name().c_str() ); + if(g_debug_execution >= 3) + printf("kernel %d: \'%s\' transfer to GPU hardware scheduler\n", m_kernel->get_uid(), m_kernel->name().c_str() ); m_kernel->print_parent_info(); if( m_sim_mode ) gpu->functional_launch( m_kernel ); else gpu->launch( m_kernel ); } + else { + if(g_debug_execution >= 3) + printf("kernel %d: \'%s\' not ready to transfer to GPU hardware scheduler\n", m_kernel->get_uid(), m_kernel->name().c_str() ); + return false; + } break; case stream_event: { - printf("event update\n"); + if(g_debug_execution >= 3) + printf("event update\n"); time_t wallclock = time((time_t *)NULL); m_event->update( gpu_tot_sim_cycle, wallclock ); m_stream->record_next_done(); @@ -173,6 +189,7 @@ void stream_operation::do_operation( gpgpu_sim *gpu ) } m_done=true; fflush(stdout); + return true; } void stream_operation::print( FILE *fp ) const @@ -204,7 +221,16 @@ bool stream_manager::operation( bool * sim) bool check=check_finished_kernel(); if(check)m_gpu->print_stats(); stream_operation op =front(); - op.do_operation( m_gpu ); + if(!op.do_operation( m_gpu )) //not ready to execute + { + //cancel operation + if( op.is_kernel() ) { + unsigned grid_uid = op.get_kernel()->get_uid(); + m_grid_id_to_stream.erase(grid_uid); + } + op.get_stream()->cancel_front(); + + } pthread_mutex_unlock(&m_lock); //pthread_mutex_lock(&m_lock); // simulate a clock cycle on the GPU @@ -228,6 +254,7 @@ bool stream_manager::register_finished_kernel(unsigned grid_uid) //Jin: should check children kernels for CDP if(kernel->is_finished()) { + printf("kernel %d finishes, retires from stream %d\n", grid_uid, stream->get_uid()); stream->record_next_done(); m_grid_id_to_stream.erase(grid_uid); kernel->notify_parent_finished(); diff --git a/src/stream_manager.h b/src/stream_manager.h index 701b33c..222a1b2 100644 --- a/src/stream_manager.h +++ b/src/stream_manager.h @@ -150,7 +150,7 @@ public: bool is_noop() const { return m_type == stream_no_op; } bool is_done() const { return m_done; } kernel_info_t *get_kernel() { return m_kernel; } - void do_operation( gpgpu_sim *gpu ); + bool do_operation( gpgpu_sim *gpu ); void print( FILE *fp ) const; struct CUstream_st *get_stream() { return m_stream; } void set_stream( CUstream_st *stream ) { m_stream = stream; } @@ -218,6 +218,7 @@ public: void push( const stream_operation &op ); void record_next_done(); stream_operation next(); + void cancel_front(); //front operation fails, cancle the pending status stream_operation &front() { return m_operations.front(); } void print( FILE *fp ); unsigned get_uid() const { return m_uid; } -- cgit v1.3 From cf507ddb207337bc7a67ded7c4438f0cb0bed26f Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Sun, 2 Nov 2014 19:24:37 -0500 Subject: BUG: PTX section id. ADD: cudaDeviceSetLimit. BUG: parameter addresses for child kernels in CDP. BUG: .weak .entry and .weak .global directives in ptx file. BUG: empty_protected() for stream manager causes deadlock, change to empty() --- libcuda/cuda_runtime_api.cc | 5 +++++ src/cuda-sim/cuda-sim.cc | 9 +++------ src/cuda-sim/cuda_device_runtime.cc | 9 +++++---- src/cuda-sim/ptx.y | 2 ++ src/gpgpusim_entrypoint.cc | 2 +- 5 files changed, 16 insertions(+), 11 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 5310a52..30bf823 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -2018,6 +2018,11 @@ __host__ cudaError_t CUDARTAPI cudaFuncSetCacheConfig(const char *func, enum cud context->get_device()->get_gpgpu()->set_cache_config(context->get_kernel(func)->get_name(), (FuncCache)cacheConfig); return g_last_cudaError = cudaSuccess; } + +//Jin: hack for cdp +__host__ cudaError_t CUDARTAPI cudaDeviceSetLimit(enum cudaLimit limit, size_t value) { + return g_last_cudaError = cudaSuccess; +} #endif #endif diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 8dd1078..980afc8 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1074,15 +1074,14 @@ unsigned function_info::get_args_aligned_size() { std::string name = p.get_name(); symbol *param = m_symtab->lookup(name.c_str()); - size_t arg_size = p.get_size(); // size of param in bytes + size_t arg_size = p.get_size() / 8; // size of param in bytes total_size = (total_size + arg_size - 1) / arg_size * arg_size; //aligned p.add_offset(total_size); - param_address += total_size; - param->set_address(param_address); + param->set_address(param_address + total_size); total_size += arg_size; } - return (total_size + 3) / 4; //final size aligned to word + return (total_size + 3) / 4 * 4; //final size aligned to word } @@ -1219,8 +1218,6 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) bool skip = false; int op_classification = 0; addr_t pc = next_instr(); - if(pc == 440) - pc = 440; assert( pc == inst.pc ); // make sure timing model and functional model are in sync const ptx_instruction *pI = m_func_info->get_instruction(pc); set_npc( pc + pI->inst_size() ); diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc index c53ea04..2a90cba 100644 --- a/src/cuda-sim/cuda_device_runtime.cc +++ b/src/cuda-sim/cuda_device_runtime.cc @@ -139,10 +139,11 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * DEV_RUNTIME_REPORT("child_kernel_arg_size " << child_kernel_arg_size); memory_space *child_kernel_param_mem = child_grid->get_param_memory(); size_t param_start_address = 0; - for(unsigned n = 0; n < child_kernel_arg_size; n++) { - unsigned char one_byte; - thread->get_gpu()->get_global_memory()->read((size_t)parameter_buffer + n, 1, &one_byte); - child_kernel_param_mem->write(param_start_address + n, 1, &one_byte, NULL, NULL); + //copy in word + for(unsigned n = 0; n < child_kernel_arg_size; n += 4) { + unsigned int oneword; + thread->get_gpu()->get_global_memory()->read((size_t)parameter_buffer + n, 4, &oneword); + child_kernel_param_mem->write(param_start_address + n, 4, &oneword, NULL, NULL); } } else if(arg == 1) { //cudaStream for the child kernel diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index c8208ea..e29b973 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -241,6 +241,7 @@ function_ident_param: IDENTIFIER { add_function_name($1); } LEFT_PAREN {func_hea function_decl_header: ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } | VISIBLE_DIRECTIVE ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } + | WEAK_DIRECTIVE ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } | FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } | VISIBLE_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } | EXTERN_DIRECTIVE FUNC_DIRECTIVE { $$ = 2; g_func_decl=1; func_header(".func"); } @@ -323,6 +324,7 @@ var_spec: space_spec | type_spec | align_spec | EXTERN_DIRECTIVE { add_extern_spec(); } + | WEAK_DIRECTIVE ; align_spec: ALIGN_DIRECTIVE INT_OPERAND { add_alignment_spec($2); } diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index 31f3a41..fb17eed 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -100,7 +100,7 @@ void *gpgpu_sim_thread_concurrent(void*) printf("GPGPU-Sim: *** simulation thread starting and spinning waiting for work ***\n"); fflush(stdout); } - while( g_stream_manager->empty_protected() && !g_sim_done ) + while( g_stream_manager->empty() && !g_sim_done ) ; if(g_debug_execution >= 3) { printf("GPGPU-Sim: ** START simulation thread (detected work) **\n"); -- cgit v1.3 From 38f811ab4d094e56b2065e1c8cb39327ad9f157b Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Thu, 30 Jun 2016 08:48:40 -0400 Subject: ADD: delete streams created by cta when deleting kernel --- src/abstract_hardware_model.cc | 12 ++++++++++++ src/abstract_hardware_model.h | 1 + 2 files changed, 13 insertions(+) diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index f3c5b21..4db5f2f 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -574,6 +574,7 @@ kernel_info_t::kernel_info_t( dim3 gridDim, dim3 blockDim, class function_info * kernel_info_t::~kernel_info_t() { assert( m_active_threads.empty() ); + destroy_cta_streams(); delete m_param_mem; } @@ -668,6 +669,17 @@ void kernel_info_t::print_parent_info() { } } +void kernel_info_t::destroy_cta_streams() { + printf("Destroy streams for kernel %d: ", get_uid()); size_t stream_size = 0; + for(auto s = m_cta_streams.begin(); s != m_cta_streams.end(); s++) { + stream_size += s->second.size(); + for(auto ss = s->second.begin(); ss != s->second.end(); ss++) + g_stream_manager->destroy_stream(*ss); + s->second.clear(); + } + printf("size %lu\n", stream_size); + m_cta_streams.clear(); +} simt_stack::simt_stack( unsigned wid, unsigned warpSize) { diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index a0bf80d..3a268ad 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -282,6 +282,7 @@ public: CUstream_st * create_stream_cta(dim3 ctaid); CUstream_st * get_default_stream_cta(dim3 ctaid); bool cta_has_stream(dim3 ctaid, CUstream_st* stream); + void destroy_cta_streams(); void print_parent_info(); private: -- cgit v1.3 From 3656376ccd83d5c514389c4c3818f1969bc30e0c Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Fri, 1 Jul 2016 05:29:58 -0400 Subject: MOD: schedule one child kernel each cycle --- src/cuda-sim/cuda_device_runtime.cc | 214 ++++++++++++++++++++++++------------ src/cuda-sim/cuda_device_runtime.h | 2 + src/gpgpu-sim/gpu-sim.cc | 4 + src/stream_manager.cc | 2 +- 4 files changed, 148 insertions(+), 74 deletions(-) diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc index 2a90cba..df2653e 100644 --- a/src/cuda-sim/cuda_device_runtime.cc +++ b/src/cuda-sim/cuda_device_runtime.cc @@ -20,8 +20,45 @@ std::cout.flush(); \ } -std::map g_cuda_device_launch_map; -extern stream_manager * g_stream_manager; +class device_launch_config_t { + +public: + device_launch_config_t() {} + + device_launch_config_t(dim3 _grid_dim, + dim3 _block_dim, + unsigned int _shared_mem, + function_info * _entry): + grid_dim(_grid_dim), + block_dim(_block_dim), + shared_mem(_shared_mem), + entry(_entry) {} + + dim3 grid_dim; + dim3 block_dim; + unsigned int shared_mem; + function_info * entry; + +}; + +class device_launch_operation_t { + +public: + device_launch_operation_t() {} + device_launch_operation_t(kernel_info_t *_grid, + CUstream_st * _stream) : + grid(_grid), stream(_stream) {} + + kernel_info_t * grid; //a new child grid + + CUstream_st * stream; + +}; + + +std::map g_cuda_device_launch_param_map; +std::list g_cuda_device_launch_op; +extern stream_manager *g_stream_manager; //Handling device runtime api: //void * cudaGetParameterBufferV2(void *func, dim3 gridDimension, dim3 blockDimension, unsigned int sharedMemSize) @@ -35,8 +72,8 @@ void gpgpusim_cuda_getParameterBufferV2(const ptx_instruction * pI, ptx_thread_i assert( n_args == 4 ); function_info * child_kernel_entry; - struct dim3 gridDim, blockDim; - unsigned int sharedMem; + struct dim3 grid_dim, block_dim; + unsigned int shared_mem; for( unsigned arg=0; arg < n_args; arg ++ ) { const operand_info &actual_param_op = pI->operand_lookup(n_return+1+arg); //param# @@ -48,54 +85,48 @@ void gpgpusim_cuda_getParameterBufferV2(const ptx_instruction * pI, ptx_thread_i if(arg == 0) {//function_info* for the child kernel unsigned long long buf; - assert(size == sizeof(function_info *)); + assert(size == sizeof(function_info *)); thread->m_local_mem->read(from_addr, size, &buf); child_kernel_entry = (function_info *)buf; assert(child_kernel_entry); DEV_RUNTIME_REPORT("child kernel name " << child_kernel_entry->get_name()); } - else if(arg == 1) { //dim3 gridDim for the child kernel - assert(size == sizeof(struct dim3)); - thread->m_local_mem->read(from_addr, size, & gridDim); - DEV_RUNTIME_REPORT("grid (" << gridDim.x << ", " << gridDim.y << ", " << gridDim.z << ")"); + else if(arg == 1) { //dim3 grid_dim for the child kernel + assert(size == sizeof(struct dim3)); + thread->m_local_mem->read(from_addr, size, & grid_dim); + DEV_RUNTIME_REPORT("grid (" << grid_dim.x << ", " << grid_dim.y << ", " << grid_dim.z << ")"); } - else if(arg == 2) { //dim3 blockDim for the child kernel - assert(size == sizeof(struct dim3)); - thread->m_local_mem->read(from_addr, size, & blockDim); - DEV_RUNTIME_REPORT("block (" << blockDim.x << ", " << blockDim.y << ", " << blockDim.z << ")"); + else if(arg == 2) { //dim3 block_dim for the child kernel + assert(size == sizeof(struct dim3)); + thread->m_local_mem->read(from_addr, size, & block_dim); + DEV_RUNTIME_REPORT("block (" << block_dim.x << ", " << block_dim.y << ", " << block_dim.z << ")"); } - else if(arg == 3) { //unsigned int sharedMem - assert(size == sizeof(unsigned int)); - thread->m_local_mem->read(from_addr, size, & sharedMem); - DEV_RUNTIME_REPORT("shared memory " << sharedMem); + else if(arg == 3) { //unsigned int shared_mem + assert(size == sizeof(unsigned int)); + thread->m_local_mem->read(from_addr, size, & shared_mem); + DEV_RUNTIME_REPORT("shared memory " << shared_mem); } } - //get total child kernel argument size and malloc buffer in global memory - unsigned child_kernel_arg_size = child_kernel_entry->get_args_aligned_size(); - void * param_buffer = thread->get_gpu()->gpu_malloc(child_kernel_arg_size); - DEV_RUNTIME_REPORT("child kernel arg size total " << child_kernel_arg_size << ", parameter buffer allocated at " << param_buffer); - - //create child kernel_info_t and index it with parameter_buffer address - kernel_info_t * child_grid = new kernel_info_t(gridDim, blockDim, child_kernel_entry); - kernel_info_t & parent_grid = thread->get_kernel(); - DEV_RUNTIME_REPORT("child kernel launched by " << parent_grid.name() << ", cta (" << - thread->get_ctaid().x << ", " << thread->get_ctaid().y << ", " << thread->get_ctaid().z << - "), thread (" << thread->get_tid().x << ", " << thread->get_tid().y << ", " << thread->get_tid().z << - ")"); - child_grid->set_parent(&parent_grid, thread->get_ctaid(), thread->get_tid()); - assert(g_cuda_device_launch_map.find(param_buffer) == g_cuda_device_launch_map.end()); - g_cuda_device_launch_map[param_buffer] = child_grid; - - //copy the buffer address to retval0 + //get total child kernel argument size and malloc buffer in global memory + unsigned child_kernel_arg_size = child_kernel_entry->get_args_aligned_size(); + void * param_buffer = thread->get_gpu()->gpu_malloc(child_kernel_arg_size); + DEV_RUNTIME_REPORT("child kernel arg size total " << child_kernel_arg_size << ", parameter buffer allocated at " << param_buffer); + + //store param buffer address and launch config + device_launch_config_t device_launch_config(grid_dim, block_dim, shared_mem, child_kernel_entry); + assert(g_cuda_device_launch_param_map.find(param_buffer) == g_cuda_device_launch_param_map.end()); + g_cuda_device_launch_param_map[param_buffer] = device_launch_config; + + //copy the buffer address to retval0 const operand_info &actual_return_op = pI->operand_lookup(0); //retval0 const symbol *formal_return = target_func->get_return_var(); //void * - unsigned int return_size = formal_return->get_size_in_bytes(); - DEV_RUNTIME_REPORT("cudaGetParameterBufferV2 return value has size of " << return_size); - assert(actual_return_op.is_param_local()); - assert(actual_return_op.get_symbol()->get_size_in_bytes() == return_size && return_size == sizeof(void *)); + unsigned int return_size = formal_return->get_size_in_bytes(); + DEV_RUNTIME_REPORT("cudaGetParameterBufferV2 return value has size of " << return_size); + assert(actual_return_op.is_param_local()); + assert(actual_return_op.get_symbol()->get_size_in_bytes() == return_size && return_size == sizeof(void *)); addr_t ret_param_addr = actual_return_op.get_symbol()->get_address(); - thread->m_local_mem->write(ret_param_addr, return_size, ¶m_buffer, NULL, NULL); + thread->m_local_mem->write(ret_param_addr, return_size, ¶m_buffer, NULL, NULL); } @@ -109,10 +140,13 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * unsigned n_args = target_func->num_args(); assert( n_args == 2 ); - kernel_info_t * child_grid = NULL; - function_info * child_kernel_entry = NULL; + kernel_info_t * device_grid = NULL; + function_info * device_kernel_entry = NULL; void * parameter_buffer; struct CUstream_st * child_stream; + device_launch_config_t config; + device_launch_operation_t device_launch_op; + for( unsigned arg=0; arg < n_args; arg ++ ) { const operand_info &actual_param_op = pI->operand_lookup(n_return+1+arg); //param# const symbol *formal_param = target_func->get_arg(arg); //cudaLaunchDeviceV2_param_# @@ -123,64 +157,80 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * if(arg == 0) {//paramter buffer for child kernel (in global memory) //get parameter_buffer from the cudaLaunchDeviceV2_param0 - assert(size == sizeof(void *)); + assert(size == sizeof(void *)); thread->m_local_mem->read(from_addr, size, ¶meter_buffer); assert((size_t)parameter_buffer >= GLOBAL_HEAP_START); DEV_RUNTIME_REPORT("Parameter buffer locating at global memory " << parameter_buffer); //get child grid info through parameter_buffer address - assert(g_cuda_device_launch_map.find(parameter_buffer) != g_cuda_device_launch_map.end()); - child_grid = g_cuda_device_launch_map[parameter_buffer]; - child_kernel_entry = child_grid->entry(); - DEV_RUNTIME_REPORT("find child kernel " << child_kernel_entry->get_name()); - - //copy data in parameter_buffer to child kernel param memory - unsigned child_kernel_arg_size = child_kernel_entry->get_args_aligned_size(); - DEV_RUNTIME_REPORT("child_kernel_arg_size " << child_kernel_arg_size); - memory_space *child_kernel_param_mem = child_grid->get_param_memory(); + assert(g_cuda_device_launch_param_map.find(parameter_buffer) != g_cuda_device_launch_param_map.end()); + config = g_cuda_device_launch_param_map[parameter_buffer]; + //device_grid = op.grid; + device_kernel_entry = config.entry; + DEV_RUNTIME_REPORT("find device kernel " << device_kernel_entry->get_name()); + + //copy data in parameter_buffer to device kernel param memory + unsigned device_kernel_arg_size = device_kernel_entry->get_args_aligned_size(); + DEV_RUNTIME_REPORT("device_kernel_arg_size " << device_kernel_arg_size); + memory_space *device_kernel_param_mem; + + //create child kernel_info_t and index it with parameter_buffer address + device_grid = new kernel_info_t(config.grid_dim, config.block_dim, device_kernel_entry); + kernel_info_t & parent_grid = thread->get_kernel(); + DEV_RUNTIME_REPORT("child kernel launched by " << parent_grid.name() << ", cta (" << + thread->get_ctaid().x << ", " << thread->get_ctaid().y << ", " << thread->get_ctaid().z << + "), thread (" << thread->get_tid().x << ", " << thread->get_tid().y << ", " << thread->get_tid().z << + ")"); + device_grid->set_parent(&parent_grid, thread->get_ctaid(), thread->get_tid()); + device_launch_op = device_launch_operation_t(device_grid, NULL); + device_kernel_param_mem = device_grid->get_param_memory(); //kernel param + size_t param_start_address = 0; //copy in word - for(unsigned n = 0; n < child_kernel_arg_size; n += 4) { + for(unsigned n = 0; n < device_kernel_arg_size; n += 4) { unsigned int oneword; thread->get_gpu()->get_global_memory()->read((size_t)parameter_buffer + n, 4, &oneword); - child_kernel_param_mem->write(param_start_address + n, 4, &oneword, NULL, NULL); + device_kernel_param_mem->write(param_start_address + n, 4, &oneword, NULL, NULL); } } else if(arg == 1) { //cudaStream for the child kernel - assert(size == sizeof(cudaStream_t)); - thread->m_local_mem->read(from_addr, size, &child_stream); + assert(size == sizeof(cudaStream_t)); + thread->m_local_mem->read(from_addr, size, &child_stream); + kernel_info_t & parent_kernel = thread->get_kernel(); if(child_stream == 0) { //default stream on device for current CTA child_stream = parent_kernel.get_default_stream_cta(thread->get_ctaid()); - DEV_RUNTIME_REPORT("launching child kernel " << child_grid->get_uid() << + DEV_RUNTIME_REPORT("launching child kernel " << device_grid->get_uid() << " to default stream of the cta " << child_stream->get_uid() << ": " << child_stream); } else { assert(parent_kernel.cta_has_stream(thread->get_ctaid(), child_stream)); - DEV_RUNTIME_REPORT("launching child kernel " << child_grid->get_uid() << + DEV_RUNTIME_REPORT("launching child kernel " << device_grid->get_uid() << " to stream " << child_stream->get_uid() << ": " << child_stream); } + + device_launch_op.stream = child_stream; + } } - } + //launch child kernel - stream_operation op(child_grid, g_ptx_sim_mode, child_stream); - g_stream_manager->push(op); - g_cuda_device_launch_map.erase(parameter_buffer); + g_cuda_device_launch_op.push_back(device_launch_op); + g_cuda_device_launch_param_map.erase(parameter_buffer); //set retval0 const operand_info &actual_return_op = pI->operand_lookup(0); //retval0 const symbol *formal_return = target_func->get_return_var(); //cudaError_t - unsigned int return_size = formal_return->get_size_in_bytes(); - DEV_RUNTIME_REPORT("cudaLaunchDeviceV2 return value has size of " << return_size); - assert(actual_return_op.is_param_local()); - assert(actual_return_op.get_symbol()->get_size_in_bytes() == return_size + unsigned int return_size = formal_return->get_size_in_bytes(); + DEV_RUNTIME_REPORT("cudaLaunchDeviceV2 return value has size of " << return_size); + assert(actual_return_op.is_param_local()); + assert(actual_return_op.get_symbol()->get_size_in_bytes() == return_size && return_size == sizeof(cudaError_t)); cudaError_t error = cudaSuccess; addr_t ret_param_addr = actual_return_op.get_symbol()->get_address(); - thread->m_local_mem->write(ret_param_addr, return_size, &error, NULL, NULL); + thread->m_local_mem->write(ret_param_addr, return_size, &error, NULL, NULL); } @@ -208,7 +258,7 @@ void gpgpusim_cuda_streamCreateWithFlags(const ptx_instruction * pI, ptx_thread_ addr_t from_addr = actual_param_op.get_symbol()->get_address(); if(arg == 0) {//cudaStream_t * pStream, address of cudaStream_t - assert(size == sizeof(cudaStream_t *)); + assert(size == sizeof(cudaStream_t *)); thread->m_local_mem->read(from_addr, size, &generic_pStream_addr); //pStream should be non-zero address in local memory @@ -217,7 +267,7 @@ void gpgpusim_cuda_streamCreateWithFlags(const ptx_instruction * pI, ptx_thread_ DEV_RUNTIME_REPORT("pStream locating at local memory " << pStream_addr); } else if(arg == 1) { //unsigned int flags, should be cudaStreamNonBlocking - assert(size == sizeof(unsigned int)); + assert(size == sizeof(unsigned int)); thread->m_local_mem->read(from_addr, size, &flags); assert(flags == cudaStreamNonBlocking); } @@ -231,13 +281,31 @@ void gpgpusim_cuda_streamCreateWithFlags(const ptx_instruction * pI, ptx_thread_ //set retval0 const operand_info &actual_return_op = pI->operand_lookup(0); //retval0 const symbol *formal_return = target_func->get_return_var(); //cudaError_t - unsigned int return_size = formal_return->get_size_in_bytes(); - DEV_RUNTIME_REPORT("cudaStreamCreateWithFlags return value has size of " << return_size); - assert(actual_return_op.is_param_local()); - assert(actual_return_op.get_symbol()->get_size_in_bytes() == return_size + unsigned int return_size = formal_return->get_size_in_bytes(); + DEV_RUNTIME_REPORT("cudaStreamCreateWithFlags return value has size of " << return_size); + assert(actual_return_op.is_param_local()); + assert(actual_return_op.get_symbol()->get_size_in_bytes() == return_size && return_size == sizeof(cudaError_t)); cudaError_t error = cudaSuccess; addr_t ret_param_addr = actual_return_op.get_symbol()->get_address(); - thread->m_local_mem->write(ret_param_addr, return_size, &error, NULL, NULL); + thread->m_local_mem->write(ret_param_addr, return_size, &error, NULL, NULL); } + + +void launch_one_device_kernel() { + if(!g_cuda_device_launch_op.empty()) { + device_launch_operation_t &op = g_cuda_device_launch_op.front(); + + stream_operation stream_op = stream_operation(op.grid, g_ptx_sim_mode, op.stream); + g_stream_manager->push(stream_op); + g_cuda_device_launch_op.pop_front(); + } +} + +void launch_all_device_kernels() { + while(!g_cuda_device_launch_op.empty()) { + launch_one_device_kernel(); + } +} + diff --git a/src/cuda-sim/cuda_device_runtime.h b/src/cuda-sim/cuda_device_runtime.h index 7447d5a..385d605 100644 --- a/src/cuda-sim/cuda_device_runtime.h +++ b/src/cuda-sim/cuda_device_runtime.h @@ -6,3 +6,5 @@ void gpgpusim_cuda_getParameterBufferV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func); void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func); void gpgpusim_cuda_streamCreateWithFlags(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func); +void launch_all_device_kernels(); +void launch_one_device_kernel(); diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 47dbc89..126e007 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -61,6 +61,7 @@ #include "power_stat.h" #include "visualizer.h" #include "stats.h" +#include "../cuda-sim/cuda_device_runtime.h" #ifdef GPGPUSIM_POWER_MODEL #include "power_interface.h" @@ -1370,6 +1371,9 @@ void gpgpu_sim::cycle() } try_snap_shot(gpu_sim_cycle); spill_log_to_file (stdout, 0, gpu_sim_cycle); + + //launch device kernel + launch_one_device_kernel(); } } diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 546ab3b..f90d9be 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -217,8 +217,8 @@ stream_manager::stream_manager( gpgpu_sim *gpu, bool cuda_launch_blocking ) bool stream_manager::operation( bool * sim) { - pthread_mutex_lock(&m_lock); bool check=check_finished_kernel(); + pthread_mutex_lock(&m_lock); if(check)m_gpu->print_stats(); stream_operation op =front(); if(!op.do_operation( m_gpu )) //not ready to execute -- cgit v1.3 From dafeb411265dbc0228889fe97d85b00f71363f10 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Fri, 1 Jul 2016 06:54:46 -0400 Subject: MOD: compute child parameter size --- src/cuda-sim/cuda-sim.cc | 9 +++++++-- src/cuda-sim/ptx_ir.cc | 1 + src/cuda-sim/ptx_ir.h | 3 +++ 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 980afc8..f5d8a88 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1066,7 +1066,10 @@ void function_info::add_param_data( unsigned argn, struct gpgpu_ptx_sim_arg *arg } unsigned function_info::get_args_aligned_size() { - + + if(m_args_aligned_size >= 0) + return m_args_aligned_size; + unsigned param_address = 0; unsigned int total_size = 0; for( std::map::iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { @@ -1081,7 +1084,9 @@ unsigned function_info::get_args_aligned_size() { total_size += arg_size; } - return (total_size + 3) / 4 * 4; //final size aligned to word + m_args_aligned_size = (total_size + 3) / 4 * 4; //final size aligned to word + + return m_args_aligned_size; } diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index bdc8381..176eb14 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1292,6 +1292,7 @@ function_info::function_info(int entry_point ) m_kernel_info.regs = 0; m_kernel_info.smem = 0; m_local_mem_framesize = 0; + m_args_aligned_size = -1; } unsigned function_info::print_insn( unsigned pc, FILE * fp ) const diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index a7ca27e..a54ae41 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -291,6 +291,9 @@ private: std::list m_initializer; static unsigned sm_next_uid; + + //parameter size for device kernels + int m_args_aligned_size; }; class symbol_table { -- cgit v1.3 From 0b37da2434beb66713754869a1de775b82a72283 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Fri, 1 Jul 2016 07:00:20 -0400 Subject: ADD: launch all device kernels at once in functional simulator --- src/cuda-sim/cuda-sim.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index f5d8a88..276cb9d 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -48,6 +48,7 @@ #include "../gpgpusim_entrypoint.h" #include "decuda_pred_table/decuda_pred_table.h" #include "../stream_manager.h" +#include "cuda_device_runtime.h" int gpgpu_ptx_instruction_classification; void ** g_inst_classification_stat = NULL; @@ -1776,13 +1777,15 @@ void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL ) g_the_gpu->getShaderCoreConfig()->warp_size ); cta.execute(); + + launch_all_device_kernels(); } //registering this kernel as done - extern stream_manager *g_stream_manager; //openCL kernel simulation calls don't register the kernel so we don't register its exit if(!openCL) { + extern stream_manager *g_stream_manager; g_stream_manager->register_finished_kernel(kernel.get_uid()); } -- cgit v1.3 From fa63d925c3d73d4c1dd7b27799d501c90917aa84 Mon Sep 17 00:00:00 2001 From: sspenst Date: Tue, 5 Jul 2016 11:58:39 -0700 Subject: Slight addition to the parser for CPTX aesthetics. You now begin and end your custom inserted PTX with CPTX_BEGIN and CPTX_END, respectively. --- src/cuda-sim/ptx.l | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 1ac047c..49fd790 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -148,6 +148,8 @@ nop TC; ptx_lval.int_value = NOP_OP; return OPCODE; break TC; ptx_lval.int_value = BREAK_OP; return OPCODE; breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; +"CPTX_END" printf("ENDING CUSTOM PTX.\n"); BEGIN(IN_COMMENT); + { \.align TC; return ALIGN_DIRECTIVE; @@ -393,9 +395,9 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; { "*/" BEGIN(INITIAL); "CPTX_BEGIN" printf("BEGINNING CUSTOM PTX.\n"); BEGIN(INITIAL); -[^C*\n]+ // eat comment in chunks -"C" -"*" // eat the lone star +[^C*\n]+ // eat comment in chunks +"C" // eat the lone C +"*" // eat the lone star \n TC; } -- cgit v1.3 From 3321626d5e858df8e2154bf4e7a1bacda76658e7 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Thu, 13 Nov 2014 17:16:44 -0500 Subject: ADD: support concurrent kernels on one shader --- src/gpgpu-sim/gpu-sim.cc | 113 ++++++++++++++++++++++++++++++++++++++++++++--- src/gpgpu-sim/shader.cc | 79 ++++++++++++++++++++++++--------- src/gpgpu-sim/shader.h | 23 +++++++++- 3 files changed, 186 insertions(+), 29 deletions(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 126e007..8a5d581 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -367,6 +367,10 @@ void shader_core_config::reg_options(class OptionParser * opp) "For complete list of prioritization values see shader.h enum scheduler_prioritization_type" "Default: gto", "gto"); + + option_parser_register(opp, "-gpgpu_concurrent_kernel_sm", OPT_BOOL, &gpgpu_concurrent_kernel_sm, + "Support concurrent kernels on a SM (default = enabled)", + "1"); } void gpgpu_sim_config::reg_options(option_parser_t opp) @@ -1075,7 +1079,98 @@ void shader_core_ctx::mem_instruction_stats(const warp_inst_t &inst) abort(); } } +//Jin: concurrent kernels on one SM +bool shader_core_ctx::can_issue_1block(kernel_info_t & kernel) { + + if(m_config->max_cta(kernel) < 1) + return false; + + return occupy_shader_resource_1block(kernel, false); +} + +int shader_core_ctx::find_available_hwtid(unsigned int cta_size) { + + unsigned int step; + for(step = 0; step < m_config->n_thread_per_shader; + step += cta_size) { + + unsigned int hw_tid; + for(hw_tid = step; hw_tid < step + cta_size; + hw_tid++) { + if(m_active_threads.test(hw_tid)) + break; + } + if(hw_tid == step + cta_size) //consecutive non-active + break; + } + if(step >= m_config->n_thread_per_shader) //didn't find + return -1; + else + return step; +} + +bool shader_core_ctx::occupy_shader_resource_1block(kernel_info_t & k, bool occupy) { + unsigned threads_per_cta = k.threads_per_cta(); + const class function_info *kernel = k.entry(); + unsigned int padded_cta_size = threads_per_cta; + unsigned int warp_size = m_config->warp_size; + if (padded_cta_size%warp_size) + padded_cta_size = ((padded_cta_size/warp_size)+1)*(warp_size); + + if(m_occupied_n_threads + padded_cta_size > m_config->n_thread_per_shader) + return false; + + if(find_available_hwtid(padded_cta_size) == -1) + return false; + + const struct gpgpu_ptx_sim_kernel_info *kernel_info = ptx_sim_kernel_info(kernel); + + if(m_occupied_shmem + kernel_info->smem > m_config->gpgpu_shmem_size) + return false; + + unsigned int used_regs = padded_cta_size * ((kernel_info->regs+3)&~3); + if(m_occupied_regs + used_regs > m_config->gpgpu_shader_registers) + return false; + + if(m_occupied_ctas +1 > m_config->max_cta_per_core) + return false; + + if(occupy) { + m_occupied_n_threads += padded_cta_size; + m_occupied_shmem += kernel_info->smem; + m_occupied_regs += (padded_cta_size * ((kernel_info->regs+3)&~3)); + m_occupied_ctas++; + + printf("GPGPU-Sim uArch: Shader %d occupied %d threads, %d shared mem, %d registers, %d ctas\n", + m_sid, m_occupied_n_threads, m_occupied_shmem, m_occupied_regs, m_occupied_ctas); + } + + return true; +} +void shader_core_ctx::release_shader_resource_1block(kernel_info_t & k) { + unsigned threads_per_cta = k.threads_per_cta(); + const class function_info *kernel = k.entry(); + unsigned int padded_cta_size = threads_per_cta; + unsigned int warp_size = m_config->warp_size; + if (padded_cta_size%warp_size) + padded_cta_size = ((padded_cta_size/warp_size)+1)*(warp_size); + + assert(m_occupied_n_threads >= padded_cta_size); + m_occupied_n_threads -= padded_cta_size; + + const struct gpgpu_ptx_sim_kernel_info *kernel_info = ptx_sim_kernel_info(kernel); + + assert(m_occupied_shmem >= (unsigned int)kernel_info->smem); + m_occupied_shmem -= kernel_info->smem; + + unsigned int used_regs = padded_cta_size * ((kernel_info->regs+3)&~3); + assert(m_occupied_regs >= used_regs); + m_occupied_regs -= used_regs; + + assert(m_occupied_ctas >= 1); + m_occupied_ctas--; +} //////////////////////////////////////////////////////////////////////////////////////////////// @@ -1088,11 +1183,14 @@ void shader_core_ctx::mem_instruction_stats(const warp_inst_t &inst) void shader_core_ctx::issue_block2core( kernel_info_t &kernel ) { - set_max_cta(kernel); +// set_max_cta(kernel); + kernel.inc_running(); + assert(occupy_shader_resource_1block(kernel, true)); // find a free CTA context unsigned free_cta_hw_id=(unsigned)-1; - for (unsigned i=0;imax_cta_per_core;i++ ) { if( m_cta_status[i]==0 ) { free_cta_hw_id=i; break; @@ -1109,8 +1207,11 @@ void shader_core_ctx::issue_block2core( kernel_info_t &kernel ) int padded_cta_size = cta_size; if (cta_size%m_config->warp_size) padded_cta_size = ((cta_size/m_config->warp_size)+1)*(m_config->warp_size); - unsigned start_thread = free_cta_hw_id * padded_cta_size; - unsigned end_thread = start_thread + cta_size; + unsigned int start_thread = find_available_hwtid(padded_cta_size); + assert((int)start_thread != -1); + unsigned int end_thread = start_thread + cta_size; +// unsigned start_thread = free_cta_hw_id * padded_cta_size; +// unsigned end_thread = start_thread + cta_size; // reset the microarchitecture state of the selected hardware thread and warp contexts reinit(start_thread, end_thread,false); @@ -1138,7 +1239,9 @@ void shader_core_ctx::issue_block2core( kernel_info_t &kernel ) m_n_active_cta++; shader_CTA_count_log(m_sid, 1); - printf("GPGPU-Sim uArch: core:%3d, cta:%2u initialized @(%lld,%lld)\n", m_sid, free_cta_hw_id, gpu_sim_cycle, gpu_tot_sim_cycle ); + printf("GPGPU-Sim uArch: core:%3d, cta:%2u, start_tid:%4u, end_tid:%4u, initialized @(%lld,%lld)\n", + m_sid, free_cta_hw_id, start_thread, end_thread, gpu_sim_cycle, gpu_tot_sim_cycle ); + } /////////////////////////////////////////////////////////////////////////////////////////// diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index de5bcf6..8cba31e 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -296,6 +296,12 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_last_inst_gpu_sim_cycle = 0; m_last_inst_gpu_tot_sim_cycle = 0; + + //Jin: for concurrent kernels on a SM + m_occupied_n_threads = 0; + m_occupied_shmem = 0; + m_occupied_regs = 0; + m_occupied_ctas = 0; } void shader_core_ctx::reinit(unsigned start_thread, unsigned end_thread, bool reset_not_completed ) @@ -303,6 +309,13 @@ void shader_core_ctx::reinit(unsigned start_thread, unsigned end_thread, bool re if( reset_not_completed ) { m_not_completed = 0; m_active_threads.reset(); + + //Jin: for concurrent kernels on a SM + m_occupied_n_threads = 0; + m_occupied_shmem = 0; + m_occupied_regs = 0; + m_occupied_ctas = 0; + } for (unsigned i = start_thread; iget_kernel())); m_not_completed -= 1; m_active_threads.reset(tid); assert( m_thread[tid]!= NULL ); @@ -1917,7 +1930,7 @@ void ldst_unit::cycle() } } -void shader_core_ctx::register_cta_thread_exit( unsigned cta_num ) +void shader_core_ctx::register_cta_thread_exit( unsigned cta_num, kernel_info_t * kernel) { assert( m_cta_status[cta_num] > 0 ); m_cta_status[cta_num]--; @@ -1925,23 +1938,33 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num ) m_n_active_cta--; m_barriers.deallocate_barrier(cta_num); shader_CTA_count_unlog(m_sid, 1); + printf("GPGPU-Sim uArch: Shader %d finished CTA #%d (%lld,%lld), %u CTAs running\n", m_sid, cta_num, gpu_sim_cycle, gpu_tot_sim_cycle, m_n_active_cta ); + if( m_n_active_cta == 0 ) { - assert( m_kernel != NULL ); - m_kernel->dec_running(); - printf("GPGPU-Sim uArch: Shader %u empty (release kernel %u \'%s\').\n", m_sid, m_kernel->get_uid(), - m_kernel->name().c_str() ); - if( !m_gpu->kernel_more_cta_left(m_kernel) ) { - if( !m_kernel->running() ) { - printf("GPGPU-Sim uArch: GPU detected kernel %u \'%s\' finished on shader %u.\n", m_kernel->get_uid(), - m_kernel->name().c_str(), m_sid ); - m_gpu->set_kernel_done( m_kernel ); - } - } - m_kernel=NULL; + printf("GPGPU-Sim uArch: Shader %u empty (last released kernel %u \'%s\').\n", m_sid, kernel->get_uid(), + kernel->name().c_str() ); fflush(stdout); + + //Shader can only be empty when no more cta are dispatched + assert(m_kernel == NULL || !m_gpu->kernel_more_cta_left(m_kernel)); + m_kernel = NULL; } + + //Jin: for concurrent kernels on sm + release_shader_resource_1block(*kernel); + kernel->dec_running(); + if( !m_gpu->kernel_more_cta_left(kernel) ) { + if( !kernel->running() ) { + printf("GPGPU-Sim uArch: GPU detected kernel %u \'%s\' finished on shader %u.\n", kernel->get_uid(), + kernel->name().c_str(), m_sid ); + if(m_kernel == kernel) + m_kernel = NULL; + m_gpu->set_kernel_done( kernel ); + } + } + } } @@ -3239,15 +3262,27 @@ unsigned simt_core_cluster::issue_block2core() unsigned num_blocks_issued=0; for( unsigned i=0; i < m_config->n_simt_cores_per_cluster; i++ ) { unsigned core = (i+m_cta_issue_next_core+1)%m_config->n_simt_cores_per_cluster; - if( m_core[core]->get_not_completed() == 0 ) { - if( m_core[core]->get_kernel() == NULL ) { - kernel_info_t *k = m_gpu->select_kernel(); - if( k ) - m_core[core]->set_kernel(k); - } - } + kernel_info_t *kernel = m_core[core]->get_kernel(); - if( m_gpu->kernel_more_cta_left(kernel) && (m_core[core]->get_n_active_cta() < m_config->max_cta(*kernel)) ) { + + //Jin: check if to fetch the next kernel + if( !m_gpu->kernel_more_cta_left(kernel) ) { + if(m_config->gpgpu_concurrent_kernel_sm || //concurrent kernel on sm + + //otherwise wait till current kernel finishes + (!m_config->gpgpu_concurrent_kernel_sm && + m_core[core]->get_not_completed() == 0) ) + { + kernel_info_t *k = m_gpu->select_kernel(); + if( k ) + m_core[core]->set_kernel(k); + } + } + + kernel = m_core[core]->get_kernel(); + if( m_gpu->kernel_more_cta_left(kernel) && +// (m_core[core]->get_n_active_cta() < m_config->max_cta(*kernel)) ) { + m_core[core]->can_issue_1block(*kernel)) { m_core[core]->issue_block2core(*kernel); num_blocks_issued++; m_cta_issue_next_core=core; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 38d09e9..fcbc8aa 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1327,6 +1327,9 @@ struct shader_core_config : public core_config int simt_core_sim_order; unsigned mem2device(unsigned memid) const { return memid + n_simt_clusters; } + + //Jin: concurrent kernel on sm + bool gpgpu_concurrent_kernel_sm; }; struct shader_core_stats_pod { @@ -1574,6 +1577,7 @@ public: void cycle(); void reinit(unsigned start_thread, unsigned end_thread, bool reset_not_completed ); void issue_block2core( class kernel_info_t &kernel ); + void cache_flush(); void accept_fetch_response( mem_fetch *mf ); void accept_ldst_unit_response( class mem_fetch * mf ); @@ -1582,7 +1586,7 @@ public: { assert(k); m_kernel=k; - k->inc_running(); +// k->inc_running(); printf("GPGPU-Sim uArch: Shader %d bind to kernel %u \'%s\'\n", m_sid, m_kernel->get_uid(), m_kernel->name().c_str() ); } @@ -1749,7 +1753,7 @@ public: virtual void checkExecutionStatusAndUpdate(warp_inst_t &inst, unsigned t, unsigned tid); address_type next_pc( int tid ) const; void fetch(); - void register_cta_thread_exit( unsigned cta_num ); + void register_cta_thread_exit( unsigned cta_num, kernel_info_t * kernel ); void decode(); @@ -1831,6 +1835,20 @@ public: // is that the dynamic_warp_id is a running number unique to every warp // run on this shader, where the warp_id is the static warp slot. unsigned m_dynamic_warp_id; + + //Jin: concurrent kernels on a sm +public: + bool can_issue_1block(kernel_info_t & kernel); + bool occupy_shader_resource_1block(kernel_info_t & kernel, bool occupy); + void release_shader_resource_1block(kernel_info_t & kernel); + int find_available_hwtid(unsigned int cta_size); +private: + unsigned int m_occupied_n_threads; + unsigned int m_occupied_shmem; + unsigned int m_occupied_regs; + unsigned int m_occupied_ctas; + + }; class simt_core_cluster { @@ -1851,6 +1869,7 @@ public: bool icnt_injection_buffer_full(unsigned size, bool write); void icnt_inject_request_packet(class mem_fetch *mf); + // for perfect memory interface bool response_queue_full() { return ( m_response_fifo.size() >= m_config->n_simt_ejection_buffer_size ); -- cgit v1.3 From 69bb1082de9df29d1d7b40486301049767e607b0 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Thu, 13 Nov 2014 18:47:03 -0500 Subject: BUG: for concurrent kernels on same shader, should select kernel from the distributor directly --- src/gpgpu-sim/gpu-sim.cc | 4 ++++ src/gpgpu-sim/shader.cc | 36 +++++++++++++++++++++--------------- 2 files changed, 25 insertions(+), 15 deletions(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 8a5d581..10c4ccf 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -523,6 +523,10 @@ bool gpgpu_sim::get_more_cta_left() const kernel_info_t *gpgpu_sim::select_kernel() { + if(m_running_kernels[m_last_issued_kernel] && + !m_running_kernels[m_last_issued_kernel]->no_more_ctas_to_run()) + return m_running_kernels[m_last_issued_kernel]; + for(unsigned n=0; n < m_running_kernels.size(); n++ ) { unsigned idx = (n+m_last_issued_kernel+1)%m_config.max_concurrent_kernel; if( kernel_more_cta_left(m_running_kernels[idx]) ){ diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 8cba31e..cd38cb7 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3263,23 +3263,29 @@ unsigned simt_core_cluster::issue_block2core() for( unsigned i=0; i < m_config->n_simt_cores_per_cluster; i++ ) { unsigned core = (i+m_cta_issue_next_core+1)%m_config->n_simt_cores_per_cluster; - kernel_info_t *kernel = m_core[core]->get_kernel(); - - //Jin: check if to fetch the next kernel - if( !m_gpu->kernel_more_cta_left(kernel) ) { - if(m_config->gpgpu_concurrent_kernel_sm || //concurrent kernel on sm - - //otherwise wait till current kernel finishes - (!m_config->gpgpu_concurrent_kernel_sm && - m_core[core]->get_not_completed() == 0) ) - { - kernel_info_t *k = m_gpu->select_kernel(); - if( k ) - m_core[core]->set_kernel(k); - } + kernel_info_t * kernel; + //Jin: fetch kernel according to concurrent kernel setting + if(m_config->gpgpu_concurrent_kernel_sm) {//concurrent kernel on sm + //always select latest issued kernel + kernel_info_t *k = m_gpu->select_kernel(); + kernel = k; + } + else { + //first select core kernel, if no more cta, get a new kernel + //only when core completes + kernel = m_core[core]->get_kernel(); + if( !m_gpu->kernel_more_cta_left(kernel) ) { + //wait till current kernel finishes + if(m_core[core]->get_not_completed() == 0) + { + kernel_info_t *k = m_gpu->select_kernel(); + if( k ) + m_core[core]->set_kernel(k); + kernel = k; + } + } } - kernel = m_core[core]->get_kernel(); if( m_gpu->kernel_more_cta_left(kernel) && // (m_core[core]->get_n_active_cta() < m_config->max_cta(*kernel)) ) { m_core[core]->can_issue_1block(*kernel)) { -- cgit v1.3 From 8ef2e4eb13093c59190439800fdd0cc552a3779e Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Fri, 14 Nov 2014 18:45:46 -0500 Subject: ADD: add cdp latency --- src/abstract_hardware_model.h | 8 ++++++-- src/cuda-sim/cuda-sim.cc | 21 ++++++++++++++++----- src/cuda-sim/ptx_ir.cc | 10 ++++++---- src/gpgpu-sim/shader.cc | 26 ++++++++++++++++++++++++++ src/gpgpu-sim/shader.h | 13 +++++++++++++ 5 files changed, 67 insertions(+), 11 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 3a268ad..45334b6 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -867,7 +867,7 @@ public: m_mem_accesses_created=false; m_cache_hit=false; m_is_printf=false; - m_is_cdp = false; + m_is_cdp = 0; } virtual ~warp_inst_t(){ } @@ -1020,7 +1020,6 @@ protected: unsigned cycles; // used for implementing initiation interval delay bool m_isatomic; bool m_is_printf; - bool m_is_cdp; unsigned m_warp_id; unsigned m_dynamic_warp_id; const core_config *m_config; @@ -1041,6 +1040,11 @@ protected: std::list m_accessq; static unsigned sm_next_uid; + + //Jin: cdp support +public: + int m_is_cdp; + }; void move_warp( warp_inst_t *&dst, warp_inst_t *&src ); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 276cb9d..9ecd92b 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -64,6 +64,8 @@ unsigned gpgpu_param_num_shaders = 0; char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp; char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp; +char *cdp_latency_str; +unsigned cdp_latency[4]; void ptx_opcocde_latency_options (option_parser_t opp) { option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, @@ -90,6 +92,11 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Opcode initiation intervals for double precision floating points " "Default 8,8,8,8,130", "8,8,8,8,130"); + option_parser_register(opp, "-cdp_latency", OPT_CSTR, &cdp_latency_str, + "CDP API latency " + "Default 1,7200,19320,1680", + "1,7200,19320,1680"); } static address_type get_converge_point(address_type pc); @@ -609,6 +616,8 @@ void ptx_instruction::set_opcode_and_latency() sscanf(opcode_initiation_dp, "%u,%u,%u,%u,%u", &dp_init[0],&dp_init[1],&dp_init[2], &dp_init[3],&dp_init[4]); + sscanf(cdp_latency_str, "%u,%u,%u,%u", + &cdp_latency[0],&cdp_latency[1],&cdp_latency[2], &cdp_latency[3]); if(!m_operands.empty()){ std::vector::iterator it; @@ -639,19 +648,21 @@ void ptx_instruction::set_opcode_and_latency() case MEMBAR_OP: op = MEMORY_BARRIER_OP; break; case CALL_OP: { - if(m_is_printf || m_is_cdp) + if(m_is_printf || m_is_cdp) { op = ALU_OP; + } else op = CALL_OPS; break; } case CALLP_OP: { - if(m_is_printf || m_is_cdp) + if(m_is_printf || m_is_cdp) { op = ALU_OP; - else - op = CALL_OPS; - break; + } + else + op = CALL_OPS; + break; } case RET_OP: case RETP_OP: op = RET_OPS;break; case ADD_OP: case ADDP_OP: case ADDC_OP: case SUB_OP: case SUBC_OP: diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 176eb14..4931213 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1241,10 +1241,12 @@ ptx_instruction::ptx_instruction( int opcode, if (fname =="vprintf"){ m_is_printf = true; } - if (fname == "cudaGetParameterBufferV2" - || fname == "cudaLaunchDeviceV2" - || fname == "cudaStreamCreateWithFlags") - m_is_cdp = true; + if(fname == "cudaGetParameterBufferV2") + m_is_cdp = 1; + if(fname == "cudaStreamCreateWithFlags") + m_is_cdp = 2; + if(fname == "cudaLaunchDeviceV2") + m_is_cdp = 3; } } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index cd38cb7..e85c4a8 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -841,6 +841,13 @@ void scheduler_unit::cycle() unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp; while( !warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue) ) { const warp_inst_t *pI = warp(warp_id).ibuffer_next_inst(); + //Jin: handle cdp latency; + if(pI->m_is_cdp && warp(warp_id).m_cdp_latency > 0) { + assert(warp(warp_id).m_cdp_dummy); + warp(warp_id).m_cdp_latency--; + break; + } + bool valid = warp(warp_id).ibuffer_next_valid(); bool warp_inst_issued = false; unsigned pc,rpc; @@ -875,6 +882,25 @@ void scheduler_unit::cycle() bool sp_pipe_avail = m_sp_out->has_free(); bool sfu_pipe_avail = m_sfu_out->has_free(); if( sp_pipe_avail && (pI->op != SFU_OP) ) { + + //Jin: special for CDP api + if(pI->m_is_cdp && !warp(warp_id).m_cdp_dummy) { + assert(warp(warp_id).m_cdp_latency == 0); + + extern unsigned cdp_latency[3]; + if(pI->m_is_cdp != 3) + warp(warp_id).m_cdp_latency = cdp_latency[pI->m_is_cdp - 1]; + else //cudaLaunchDeviceV2 + warp(warp_id).m_cdp_latency = cdp_latency[pI->m_is_cdp - 1] + + cdp_latency[pI->m_is_cdp] * active_mask.count(); + warp(warp_id).m_cdp_dummy = true; + break; + } + else if(pI->m_is_cdp && warp(warp_id).m_cdp_dummy) { + assert(warp(warp_id).m_cdp_latency == 0); + warp(warp_id).m_cdp_dummy = false; + } + // always prefer SP pipe for operations that can use both SP and SFU pipelines m_shader->issue_warp(*m_sp_out,pI,active_mask,warp_id); issued++; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index fcbc8aa..882868e 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -108,6 +108,10 @@ public: m_last_fetch=0; m_next=0; m_inst_at_barrier=NULL; + + //Jin: cdp support + m_cdp_latency = 0; + m_cdp_dummy = false; } void init( address_type start_pc, unsigned cta_id, @@ -124,6 +128,10 @@ public: n_completed -= active.count(); // active threads are not yet completed m_active_threads = active; m_done_exit=false; + + //Jin: cdp support + m_cdp_latency = 0; + m_cdp_dummy = false; } bool functional_done() const; @@ -260,6 +268,11 @@ private: unsigned m_stores_outstanding; // number of store requests sent but not yet acknowledged unsigned m_inst_in_pipeline; + + //Jin: cdp support +public: + unsigned int m_cdp_latency; + bool m_cdp_dummy; }; -- cgit v1.3 From bbcb492c0f6d887c4034bd15adf57420dd735c5e Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Fri, 14 Nov 2014 20:01:10 -0500 Subject: ADD: add separate cdp latency --- src/cuda-sim/cuda-sim.cc | 16 +++++++++------- src/cuda-sim/ptx_ir.cc | 6 +++--- src/gpgpu-sim/shader.cc | 7 ++++--- 3 files changed, 16 insertions(+), 13 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 9ecd92b..c87e3e4 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -65,7 +65,7 @@ unsigned gpgpu_param_num_shaders = 0; char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp; char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp; char *cdp_latency_str; -unsigned cdp_latency[4]; +unsigned cdp_latency[5]; void ptx_opcocde_latency_options (option_parser_t opp) { option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, @@ -93,10 +93,11 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Default 8,8,8,8,130", "8,8,8,8,130"); option_parser_register(opp, "-cdp_latency", OPT_CSTR, &cdp_latency_str, - "CDP API latency " - "Default 1,7200,19320,1680", - "1,7200,19320,1680"); + "CDP API latency " + "Default 7200,8000,100,12000,1600", + "7200,8000,100,12000,1600"); } static address_type get_converge_point(address_type pc); @@ -616,8 +617,9 @@ void ptx_instruction::set_opcode_and_latency() sscanf(opcode_initiation_dp, "%u,%u,%u,%u,%u", &dp_init[0],&dp_init[1],&dp_init[2], &dp_init[3],&dp_init[4]); - sscanf(cdp_latency_str, "%u,%u,%u,%u", - &cdp_latency[0],&cdp_latency[1],&cdp_latency[2], &cdp_latency[3]); + sscanf(cdp_latency_str, "%u,%u,%u,%u,%u", + &cdp_latency[0],&cdp_latency[1],&cdp_latency[2], + &cdp_latency[3],&cdp_latency[4]); if(!m_operands.empty()){ std::vector::iterator it; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 4931213..783c885 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1241,12 +1241,12 @@ ptx_instruction::ptx_instruction( int opcode, if (fname =="vprintf"){ m_is_printf = true; } - if(fname == "cudaGetParameterBufferV2") - m_is_cdp = 1; if(fname == "cudaStreamCreateWithFlags") + m_is_cdp = 1; + if(fname == "cudaGetParameterBufferV2") m_is_cdp = 2; if(fname == "cudaLaunchDeviceV2") - m_is_cdp = 3; + m_is_cdp = 4; } } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index e85c4a8..8ce2146 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -887,12 +887,13 @@ void scheduler_unit::cycle() if(pI->m_is_cdp && !warp(warp_id).m_cdp_dummy) { assert(warp(warp_id).m_cdp_latency == 0); - extern unsigned cdp_latency[3]; - if(pI->m_is_cdp != 3) + extern unsigned cdp_latency[5]; + if(pI->m_is_cdp == 1) warp(warp_id).m_cdp_latency = cdp_latency[pI->m_is_cdp - 1]; - else //cudaLaunchDeviceV2 + else //cudaLaunchDeviceV2 and cudaGetParameterBufferV2 warp(warp_id).m_cdp_latency = cdp_latency[pI->m_is_cdp - 1] + cdp_latency[pI->m_is_cdp] * active_mask.count(); + printf("set latency %d\n", warp(warp_id).m_cdp_latency); warp(warp_id).m_cdp_dummy = true; break; } -- cgit v1.3 From 9c0384c1626205b4a9ed97f998b3d4d8e7758198 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Fri, 14 Nov 2014 22:11:52 -0500 Subject: BUG: concurrent kernels on same SM may occupy warps from running CTAs --- src/gpgpu-sim/gpu-sim.cc | 27 +++++++++++++++++++++------ src/gpgpu-sim/shader.cc | 7 +++++-- src/gpgpu-sim/shader.h | 8 +++++--- 3 files changed, 31 insertions(+), 11 deletions(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 10c4ccf..81c9c9a 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1092,7 +1092,7 @@ bool shader_core_ctx::can_issue_1block(kernel_info_t & kernel) { return occupy_shader_resource_1block(kernel, false); } -int shader_core_ctx::find_available_hwtid(unsigned int cta_size) { +int shader_core_ctx::find_available_hwtid(unsigned int cta_size, bool occupy) { unsigned int step; for(step = 0; step < m_config->n_thread_per_shader; @@ -1101,7 +1101,7 @@ int shader_core_ctx::find_available_hwtid(unsigned int cta_size) { unsigned int hw_tid; for(hw_tid = step; hw_tid < step + cta_size; hw_tid++) { - if(m_active_threads.test(hw_tid)) + if(m_occupied_hwtid.test(hw_tid)) break; } if(hw_tid == step + cta_size) //consecutive non-active @@ -1109,8 +1109,14 @@ int shader_core_ctx::find_available_hwtid(unsigned int cta_size) { } if(step >= m_config->n_thread_per_shader) //didn't find return -1; - else + else { + if(occupy) { + for(unsigned hw_tid = step; hw_tid < step + cta_size; + hw_tid++) + m_occupied_hwtid.set(hw_tid); + } return step; + } } bool shader_core_ctx::occupy_shader_resource_1block(kernel_info_t & k, bool occupy) { @@ -1124,7 +1130,7 @@ bool shader_core_ctx::occupy_shader_resource_1block(kernel_info_t & k, bool occu if(m_occupied_n_threads + padded_cta_size > m_config->n_thread_per_shader) return false; - if(find_available_hwtid(padded_cta_size) == -1) + if(find_available_hwtid(padded_cta_size, false) == -1) return false; const struct gpgpu_ptx_sim_kernel_info *kernel_info = ptx_sim_kernel_info(kernel); @@ -1152,7 +1158,7 @@ bool shader_core_ctx::occupy_shader_resource_1block(kernel_info_t & k, bool occu return true; } -void shader_core_ctx::release_shader_resource_1block(kernel_info_t & k) { +void shader_core_ctx::release_shader_resource_1block(unsigned hw_ctaid, kernel_info_t & k) { unsigned threads_per_cta = k.threads_per_cta(); const class function_info *kernel = k.entry(); unsigned int padded_cta_size = threads_per_cta; @@ -1163,6 +1169,13 @@ void shader_core_ctx::release_shader_resource_1block(kernel_info_t & k) { assert(m_occupied_n_threads >= padded_cta_size); m_occupied_n_threads -= padded_cta_size; + int start_thread = m_occupied_cta_to_hwtid[hw_ctaid]; + + for(unsigned hwtid = start_thread; hwtid < start_thread + padded_cta_size; + hwtid++) + m_occupied_hwtid.reset(hwtid); + m_occupied_cta_to_hwtid.erase(hw_ctaid); + const struct gpgpu_ptx_sim_kernel_info *kernel_info = ptx_sim_kernel_info(kernel); assert(m_occupied_shmem >= (unsigned int)kernel_info->smem); @@ -1211,9 +1224,11 @@ void shader_core_ctx::issue_block2core( kernel_info_t &kernel ) int padded_cta_size = cta_size; if (cta_size%m_config->warp_size) padded_cta_size = ((cta_size/m_config->warp_size)+1)*(m_config->warp_size); - unsigned int start_thread = find_available_hwtid(padded_cta_size); + unsigned int start_thread = find_available_hwtid(padded_cta_size, true); assert((int)start_thread != -1); unsigned int end_thread = start_thread + cta_size; + assert(m_occupied_cta_to_hwtid.find(free_cta_hw_id) == m_occupied_cta_to_hwtid.end()); + m_occupied_cta_to_hwtid[free_cta_hw_id]= start_thread; // unsigned start_thread = free_cta_hw_id * padded_cta_size; // unsigned end_thread = start_thread + cta_size; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 8ce2146..b9caf18 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -302,6 +302,8 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_occupied_shmem = 0; m_occupied_regs = 0; m_occupied_ctas = 0; + m_occupied_hwtid.reset(); + m_occupied_cta_to_hwtid.clear(); } void shader_core_ctx::reinit(unsigned start_thread, unsigned end_thread, bool reset_not_completed ) @@ -315,6 +317,8 @@ void shader_core_ctx::reinit(unsigned start_thread, unsigned end_thread, bool re m_occupied_shmem = 0; m_occupied_regs = 0; m_occupied_ctas = 0; + m_occupied_hwtid.reset(); + m_occupied_cta_to_hwtid.clear(); } for (unsigned i = start_thread; im_is_cdp - 1] + cdp_latency[pI->m_is_cdp] * active_mask.count(); - printf("set latency %d\n", warp(warp_id).m_cdp_latency); warp(warp_id).m_cdp_dummy = true; break; } @@ -1980,7 +1983,7 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num, kernel_info_t } //Jin: for concurrent kernels on sm - release_shader_resource_1block(*kernel); + release_shader_resource_1block(cta_num, *kernel); kernel->dec_running(); if( !m_gpu->kernel_more_cta_left(kernel) ) { if( !kernel->running() ) { diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 882868e..bdd8dbe 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1766,7 +1766,7 @@ public: virtual void checkExecutionStatusAndUpdate(warp_inst_t &inst, unsigned t, unsigned tid); address_type next_pc( int tid ) const; void fetch(); - void register_cta_thread_exit( unsigned cta_num, kernel_info_t * kernel ); + void register_cta_thread_exit(unsigned cta_num, kernel_info_t * kernel ); void decode(); @@ -1853,13 +1853,15 @@ public: public: bool can_issue_1block(kernel_info_t & kernel); bool occupy_shader_resource_1block(kernel_info_t & kernel, bool occupy); - void release_shader_resource_1block(kernel_info_t & kernel); - int find_available_hwtid(unsigned int cta_size); + void release_shader_resource_1block(unsigned hw_ctaid, kernel_info_t & kernel); + int find_available_hwtid(unsigned int cta_size, bool occupy); private: unsigned int m_occupied_n_threads; unsigned int m_occupied_shmem; unsigned int m_occupied_regs; unsigned int m_occupied_ctas; + std::bitset m_occupied_hwtid; + std::map m_occupied_cta_to_hwtid; }; -- cgit v1.3 From a31392370bc7b23e115160b170e95b117597ebc4 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Sat, 15 Nov 2014 02:09:24 -0500 Subject: ADD: add stats for kernel launching and complete cycle --- src/abstract_hardware_model.h | 6 ++++++ src/cuda-sim/cuda_device_runtime.cc | 2 +- src/gpgpu-sim/gpu-sim.cc | 2 ++ src/stream_manager.cc | 9 ++++++++- 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 45334b6..e6ef521 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -284,6 +284,7 @@ public: bool cta_has_stream(dim3 ctaid, CUstream_st* stream); void destroy_cta_streams(); void print_parent_info(); + kernel_info_t * get_parent() { return m_parent_kernel; } private: kernel_info_t * m_parent_kernel; @@ -292,6 +293,11 @@ private: std::list m_child_kernels; //child kernel launched std::map< dim3, std::list, dim3comp > m_cta_streams; //streams created in each CTA +//Jin: kernel timing +public: + unsigned long long launch_cycle; + unsigned long long start_cycle; + unsigned long long end_cycle; }; struct core_config { diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc index df2653e..1b8c8d9 100644 --- a/src/cuda-sim/cuda_device_runtime.cc +++ b/src/cuda-sim/cuda_device_runtime.cc @@ -176,6 +176,7 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * //create child kernel_info_t and index it with parameter_buffer address device_grid = new kernel_info_t(config.grid_dim, config.block_dim, device_kernel_entry); + device_grid->launch_cycle = gpu_sim_cycle; kernel_info_t & parent_grid = thread->get_kernel(); DEV_RUNTIME_REPORT("child kernel launched by " << parent_grid.name() << ", cta (" << thread->get_ctaid().x << ", " << thread->get_ctaid().y << ", " << thread->get_ctaid().z << @@ -184,7 +185,6 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * device_grid->set_parent(&parent_grid, thread->get_ctaid(), thread->get_tid()); device_launch_op = device_launch_operation_t(device_grid, NULL); device_kernel_param_mem = device_grid->get_param_memory(); //kernel param - size_t param_start_address = 0; //copy in word for(unsigned n = 0; n < device_kernel_arg_size; n += 4) { diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 81c9c9a..27362cf 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -531,6 +531,7 @@ kernel_info_t *gpgpu_sim::select_kernel() unsigned idx = (n+m_last_issued_kernel+1)%m_config.max_concurrent_kernel; if( kernel_more_cta_left(m_running_kernels[idx]) ){ m_last_issued_kernel=idx; + m_running_kernels[idx]->start_cycle = gpu_sim_cycle; // record this kernel for stat print if it is the first time this kernel is selected for execution unsigned launch_uid = m_running_kernels[idx]->get_uid(); if (std::find(m_executed_kernel_uids.begin(), m_executed_kernel_uids.end(), launch_uid) == m_executed_kernel_uids.end()) { @@ -560,6 +561,7 @@ void gpgpu_sim::set_kernel_done( kernel_info_t *kernel ) std::vector::iterator k; for( k=m_running_kernels.begin(); k!=m_running_kernels.end(); k++ ) { if( *k == kernel ) { + kernel->end_cycle = gpu_sim_cycle; *k = NULL; break; } diff --git a/src/stream_manager.cc b/src/stream_manager.cc index f90d9be..5bd7737 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -254,7 +254,14 @@ bool stream_manager::register_finished_kernel(unsigned grid_uid) //Jin: should check children kernels for CDP if(kernel->is_finished()) { - printf("kernel %d finishes, retires from stream %d\n", grid_uid, stream->get_uid()); +// std::ofstream kernel_stat("kernel_stat.txt", std::ofstream::out | std::ofstream::app); +// kernel_stat<< " kernel " << grid_uid; +// if(kernel->get_parent()) +// kernel_stat << ", parent " << kernel->get_parent()->get_uid() << +// ", launch " << kernel->launch_cycle; +// kernel_stat<< ", start " << kernel->start_cycle << +// ", end " << kernel->end_cycle << ", retire " << gpu_sim_cycle << "\n"; +// printf("kernel %d finishes, retires from stream %d\n", grid_uid, stream->get_uid()); stream->record_next_done(); m_grid_id_to_stream.erase(grid_uid); kernel->notify_parent_finished(); -- cgit v1.3 From b70a5a69fa14cc01f707b910f8f021e36067922f Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Sat, 15 Nov 2014 05:44:03 -0500 Subject: ADD: print kernel parameter size footprint. BUG: concurrent kernels on same shader, should use hw_cta_id to store shared mem info --- src/abstract_hardware_model.cc | 2 ++ src/cuda-sim/cuda-sim.cc | 3 ++- src/cuda-sim/cuda_device_runtime.cc | 7 ++++++- src/gpgpu-sim/gpu-sim.cc | 23 +++++++++++++++-------- src/stream_manager.cc | 6 ++++-- 5 files changed, 29 insertions(+), 12 deletions(-) diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index 4db5f2f..be5c5b9 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -618,6 +618,8 @@ bool kernel_info_t::children_all_finished() { void kernel_info_t::notify_parent_finished() { if(m_parent_kernel) { + extern unsigned long long g_total_param_size; + g_total_param_size -= ((m_kernel_entry->get_args_aligned_size() + 255)/256*256); m_parent_kernel->remove_child(this); g_stream_manager->register_finished_kernel(m_parent_kernel->get_uid()); } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index c87e3e4..3f5af7e 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1499,7 +1499,8 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, unsigned max_cta_per_sm = num_threads/cta_size; // e.g., 256 / 48 = 5 assert( max_cta_per_sm > 0 ); - unsigned sm_idx = (tid/cta_size)*gpgpu_param_num_shaders + sid; + //unsigned sm_idx = (tid/cta_size)*gpgpu_param_num_shaders + sid; + unsigned sm_idx = hw_cta_id*gpgpu_param_num_shaders + sid; if ( shared_memory_lookup.find(sm_idx) == shared_memory_lookup.end() ) { if ( g_debug_execution >= 1 ) { diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc index 1b8c8d9..66cd063 100644 --- a/src/cuda-sim/cuda_device_runtime.cc +++ b/src/cuda-sim/cuda_device_runtime.cc @@ -59,6 +59,8 @@ public: std::map g_cuda_device_launch_param_map; std::list g_cuda_device_launch_op; extern stream_manager *g_stream_manager; +unsigned long long g_total_param_size = 0; +unsigned long long g_max_total_param_size = 0; //Handling device runtime api: //void * cudaGetParameterBufferV2(void *func, dim3 gridDimension, dim3 blockDimension, unsigned int sharedMemSize) @@ -111,7 +113,10 @@ void gpgpusim_cuda_getParameterBufferV2(const ptx_instruction * pI, ptx_thread_i //get total child kernel argument size and malloc buffer in global memory unsigned child_kernel_arg_size = child_kernel_entry->get_args_aligned_size(); void * param_buffer = thread->get_gpu()->gpu_malloc(child_kernel_arg_size); + g_total_param_size += ((child_kernel_arg_size + 255) / 256 * 256); DEV_RUNTIME_REPORT("child kernel arg size total " << child_kernel_arg_size << ", parameter buffer allocated at " << param_buffer); + if(g_total_param_size > g_max_total_param_size) + g_max_total_param_size = g_total_param_size; //store param buffer address and launch config device_launch_config_t device_launch_config(grid_dim, block_dim, shared_mem, child_kernel_entry); @@ -176,7 +181,7 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * //create child kernel_info_t and index it with parameter_buffer address device_grid = new kernel_info_t(config.grid_dim, config.block_dim, device_kernel_entry); - device_grid->launch_cycle = gpu_sim_cycle; + device_grid->launch_cycle = gpu_sim_cycle + gpu_tot_sim_cycle; kernel_info_t & parent_grid = thread->get_kernel(); DEV_RUNTIME_REPORT("child kernel launched by " << parent_grid.name() << ", cta (" << thread->get_ctaid().x << ", " << thread->get_ctaid().y << ", " << thread->get_ctaid().z << diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 27362cf..a9da1c9 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -524,20 +524,26 @@ bool gpgpu_sim::get_more_cta_left() const kernel_info_t *gpgpu_sim::select_kernel() { if(m_running_kernels[m_last_issued_kernel] && - !m_running_kernels[m_last_issued_kernel]->no_more_ctas_to_run()) + !m_running_kernels[m_last_issued_kernel]->no_more_ctas_to_run()) { + unsigned launch_uid = m_running_kernels[m_last_issued_kernel]->get_uid(); + if(std::find(m_executed_kernel_uids.begin(), m_executed_kernel_uids.end(), launch_uid) == m_executed_kernel_uids.end()) { + m_running_kernels[m_last_issued_kernel]->start_cycle = gpu_sim_cycle + gpu_tot_sim_cycle; + m_executed_kernel_uids.push_back(launch_uid); + m_executed_kernel_names.push_back(m_running_kernels[m_last_issued_kernel]->name()); + } return m_running_kernels[m_last_issued_kernel]; + } for(unsigned n=0; n < m_running_kernels.size(); n++ ) { unsigned idx = (n+m_last_issued_kernel+1)%m_config.max_concurrent_kernel; if( kernel_more_cta_left(m_running_kernels[idx]) ){ m_last_issued_kernel=idx; - m_running_kernels[idx]->start_cycle = gpu_sim_cycle; + m_running_kernels[idx]->start_cycle = gpu_sim_cycle + gpu_tot_sim_cycle; // record this kernel for stat print if it is the first time this kernel is selected for execution unsigned launch_uid = m_running_kernels[idx]->get_uid(); - if (std::find(m_executed_kernel_uids.begin(), m_executed_kernel_uids.end(), launch_uid) == m_executed_kernel_uids.end()) { - m_executed_kernel_uids.push_back(launch_uid); - m_executed_kernel_names.push_back(m_running_kernels[idx]->name()); - } + assert(std::find(m_executed_kernel_uids.begin(), m_executed_kernel_uids.end(), launch_uid) == m_executed_kernel_uids.end()); + m_executed_kernel_uids.push_back(launch_uid); + m_executed_kernel_names.push_back(m_running_kernels[idx]->name()); return m_running_kernels[idx]; } @@ -561,7 +567,7 @@ void gpgpu_sim::set_kernel_done( kernel_info_t *kernel ) std::vector::iterator k; for( k=m_running_kernels.begin(); k!=m_running_kernels.end(); k++ ) { if( *k == kernel ) { - kernel->end_cycle = gpu_sim_cycle; + kernel->end_cycle = gpu_sim_cycle + gpu_tot_sim_cycle; *k = NULL; break; } @@ -942,7 +948,8 @@ void gpgpu_sim::gpu_print_stat() printf("gpu_tot_ipc = %12.4f\n", (float)(gpu_tot_sim_insn+gpu_sim_insn) / (gpu_tot_sim_cycle+gpu_sim_cycle)); printf("gpu_tot_issued_cta = %lld\n", gpu_tot_issued_cta + m_total_cta_launched); - + extern unsigned long long g_max_total_param_size; + fprintf(statfout, "max_total_param_size = %llu\n", g_max_total_param_size); // performance counter for stalls due to congestion. printf("gpu_stall_dramfull = %d\n", gpu_stall_dramfull); diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 5bd7737..3459c6d 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -219,7 +219,7 @@ bool stream_manager::operation( bool * sim) { bool check=check_finished_kernel(); pthread_mutex_lock(&m_lock); - if(check)m_gpu->print_stats(); +// if(check)m_gpu->print_stats(); stream_operation op =front(); if(!op.do_operation( m_gpu )) //not ready to execute { @@ -260,8 +260,10 @@ bool stream_manager::register_finished_kernel(unsigned grid_uid) // kernel_stat << ", parent " << kernel->get_parent()->get_uid() << // ", launch " << kernel->launch_cycle; // kernel_stat<< ", start " << kernel->start_cycle << -// ", end " << kernel->end_cycle << ", retire " << gpu_sim_cycle << "\n"; +// ", end " << kernel->end_cycle << ", retire " << gpu_sim_cycle + gpu_tot_sim_cycle << "\n"; // printf("kernel %d finishes, retires from stream %d\n", grid_uid, stream->get_uid()); +// kernel_stat.flush(); +// kernel_stat.close(); stream->record_next_done(); m_grid_id_to_stream.erase(grid_uid); kernel->notify_parent_finished(); -- cgit v1.3 From 60fa05d4de0f3c926f9ab4f687b5d0748ec19285 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Sun, 16 Nov 2014 01:27:47 -0500 Subject: ADD: add kernel launching latency from stream to distributor --- src/abstract_hardware_model.cc | 4 ++++ src/abstract_hardware_model.h | 1 + src/gpgpu-sim/gpu-sim.cc | 6 ++++++ src/gpgpusim_entrypoint.cc | 1 + src/stream_manager.cc | 39 +++++++++++++++++++++++++-------------- 5 files changed, 37 insertions(+), 14 deletions(-) diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index be5c5b9..819ad35 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -550,6 +550,8 @@ void warp_inst_t::completed( unsigned long long cycle ) const ptx_file_line_stats_add_latency(pc, latency * active_count()); } +//Jin: kernel launch latency +unsigned g_kernel_launch_latency; unsigned kernel_info_t::m_next_uid = 1; @@ -569,6 +571,8 @@ kernel_info_t::kernel_info_t( dim3 gridDim, dim3 blockDim, class function_info * //Jin: parent and child kernel management for CDP m_parent_kernel = NULL; + //Jin: launch latency management + m_launch_latency = g_kernel_launch_latency; } kernel_info_t::~kernel_info_t() diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index e6ef521..ab77d63 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -298,6 +298,7 @@ public: unsigned long long launch_cycle; unsigned long long start_cycle; unsigned long long end_cycle; + unsigned m_launch_latency; }; struct core_config { diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index a9da1c9..7fb9ab3 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -443,6 +443,12 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) &Trace::sampling_memory_partition, "The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all)", "-1"); ptx_file_line_stats_options(opp); + + //Jin: kernel launch latency + extern unsigned g_kernel_launch_latency; + option_parser_register(opp, "-gpgpu_kernel_launch_latency", OPT_INT32, + &g_kernel_launch_latency, "Kernel launch latency in cycles. Default: 0", + "0"); } ///////////////////////////////////////////////////////////////////////////// diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index fb17eed..04845e7 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -153,6 +153,7 @@ void *gpgpu_sim_thread_concurrent(void*) printf("GPGPU-Sim: ** STOP simulation thread (no work) **\n"); fflush(stdout); } + g_the_gpu->print_stats(); if(sim_cycles) { g_the_gpu->update_stats(); print_simulation_time(); diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 3459c6d..3b6cbd5 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -160,20 +160,31 @@ bool stream_operation::do_operation( gpgpu_sim *gpu ) m_stream->record_next_done(); break; case stream_kernel_launch: - if( gpu->can_start_kernel() ) { - gpu->set_cache_config(m_kernel->name()); - if(g_debug_execution >= 3) - printf("kernel %d: \'%s\' transfer to GPU hardware scheduler\n", m_kernel->get_uid(), m_kernel->name().c_str() ); - m_kernel->print_parent_info(); - if( m_sim_mode ) - gpu->functional_launch( m_kernel ); - else - gpu->launch( m_kernel ); + if( m_sim_mode ) { //Functional Sim + if(g_debug_execution >= 3) { + printf("kernel %d: \'%s\' transfer to GPU hardware scheduler\n", m_kernel->get_uid(), m_kernel->name().c_str() ); + m_kernel->print_parent_info(); + } + gpu->set_cache_config(m_kernel->name()); + gpu->functional_launch( m_kernel ); } - else { - if(g_debug_execution >= 3) - printf("kernel %d: \'%s\' not ready to transfer to GPU hardware scheduler\n", m_kernel->get_uid(), m_kernel->name().c_str() ); - return false; + else { //Performance Sim + if( gpu->can_start_kernel() && m_kernel->m_launch_latency == 0) { + if(g_debug_execution >= 3) { + printf("kernel %d: \'%s\' transfer to GPU hardware scheduler\n", m_kernel->get_uid(), m_kernel->name().c_str() ); + m_kernel->print_parent_info(); + } + gpu->set_cache_config(m_kernel->name()); + gpu->launch( m_kernel ); + } + else { + if(m_kernel->m_launch_latency) + m_kernel->m_launch_latency--; + if(g_debug_execution >= 3) + printf("kernel %d: \'%s\', latency %u not ready to transfer to GPU hardware scheduler\n", + m_kernel->get_uid(), m_kernel->name().c_str(), m_kernel->m_launch_latency); + return false; + } } break; case stream_event: { @@ -255,7 +266,7 @@ bool stream_manager::register_finished_kernel(unsigned grid_uid) //Jin: should check children kernels for CDP if(kernel->is_finished()) { // std::ofstream kernel_stat("kernel_stat.txt", std::ofstream::out | std::ofstream::app); -// kernel_stat<< " kernel " << grid_uid; +// kernel_stat<< " kernel " << grid_uid << ": " << kernel->name(); // if(kernel->get_parent()) // kernel_stat << ", parent " << kernel->get_parent()->get_uid() << // ", launch " << kernel->launch_cycle; -- cgit v1.3 From 06c5a3ddc979a78dd38bf0f74170e4919cd32fab Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Sun, 3 Jul 2016 06:46:15 -0400 Subject: BUG: wrong declaration for m_args_aligned_size --- src/cuda-sim/ptx_ir.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index a54ae41..55b01fd 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -292,8 +292,6 @@ private: std::list m_initializer; static unsigned sm_next_uid; - //parameter size for device kernels - int m_args_aligned_size; }; class symbol_table { @@ -1302,6 +1300,9 @@ private: static std::vector s_g_pc_to_insn; // a direct mapping from PC to instruction static unsigned sm_next_uid; + + //parameter size for device kernels + int m_args_aligned_size; }; class arg_buffer_t { -- cgit v1.3 From b64b0f41e217db350637aff6de0ddb18c8e7ad49 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Sun, 3 Jul 2016 07:10:38 -0400 Subject: BUG: extra bracket --- src/cuda-sim/cuda_device_runtime.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc index 66cd063..12c83d2 100644 --- a/src/cuda-sim/cuda_device_runtime.cc +++ b/src/cuda-sim/cuda_device_runtime.cc @@ -215,9 +215,9 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * " to stream " << child_stream->get_uid() << ": " << child_stream); } - device_launch_op.stream = child_stream; - } + device_launch_op.stream = child_stream; } + } -- cgit v1.3 From 9f958e424f2fc952970794efc7647ceae1674d97 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Wed, 6 Jul 2016 02:40:10 -0400 Subject: MOD: modify to new structure name gpgpu_ptx_sim_info --- src/gpgpu-sim/gpu-sim.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 7fb9ab3..02c9c09 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1148,7 +1148,7 @@ bool shader_core_ctx::occupy_shader_resource_1block(kernel_info_t & k, bool occu if(find_available_hwtid(padded_cta_size, false) == -1) return false; - const struct gpgpu_ptx_sim_kernel_info *kernel_info = ptx_sim_kernel_info(kernel); + const struct gpgpu_ptx_sim_info *kernel_info = ptx_sim_kernel_info(kernel); if(m_occupied_shmem + kernel_info->smem > m_config->gpgpu_shmem_size) return false; @@ -1191,7 +1191,7 @@ void shader_core_ctx::release_shader_resource_1block(unsigned hw_ctaid, kernel_i m_occupied_hwtid.reset(hwtid); m_occupied_cta_to_hwtid.erase(hw_ctaid); - const struct gpgpu_ptx_sim_kernel_info *kernel_info = ptx_sim_kernel_info(kernel); + const struct gpgpu_ptx_sim_info *kernel_info = ptx_sim_kernel_info(kernel); assert(m_occupied_shmem >= (unsigned int)kernel_info->smem); m_occupied_shmem -= kernel_info->smem; -- cgit v1.3 From 2af85e353bccad8c8536c1d5f039361884b96872 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Wed, 6 Jul 2016 05:18:44 -0400 Subject: ADD: add knob to enable CDP in gpgpusim config --- libcuda/cuda_runtime_api.cc | 14 +++++++++++++- src/abstract_hardware_model.cc | 3 ++- src/cuda-sim/ptx_loader.cc | 6 +++++- src/gpgpu-sim/gpu-sim.cc | 4 ++++ 4 files changed, 24 insertions(+), 3 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 30bf823..aa9a3eb 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1336,7 +1336,11 @@ void extract_code_using_cuobjdump(){ system(command); // Running cuobjdump using dynamic link to current process // Needs the option '-all' to extract PTX from CDP-enabled binary - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); + extern bool g_cdp_enabled; + if(!g_cdp_enabled) + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass %s > %s", app_binary.c_str(), fname); + else + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); bool parse_output = true; int result = system(command); if(result) { @@ -1545,6 +1549,14 @@ cuobjdumpPTXSection* findPTXSectionInList(std::list sectionli if((ptxsection=dynamic_cast(*iter)) != NULL){ if(ptxsection->getIdentifier() == identifier) return ptxsection; + else { + extern bool g_cdp_enabled; + if(g_cdp_enabled) { + printf("Warning: __cudaRegisterFatBinary needs %s, but find PTX section with %s\n", + identifier.c_str(), ptxsection->getIdentifier().c_str()); + return ptxsection; + } + } } } return NULL; diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index 819ad35..fe6f8ab 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -550,7 +550,8 @@ void warp_inst_t::completed( unsigned long long cycle ) const ptx_file_line_stats_add_latency(pc, latency * active_count()); } -//Jin: kernel launch latency +//Jin: CDP support +bool g_cdp_enabled; unsigned g_kernel_launch_latency; unsigned kernel_info_t::m_next_uid = 1; diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index f7bf70e..a646408 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -217,7 +217,11 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num #if CUDART_VERSION >= 3000 if (sm_version == 0) sm_version = 20; - snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); + extern bool g_cdp_enabled; + if(!g_cdp_enabled) + snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); + else + snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version); #endif snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 02c9c09..0b4b2f6 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -449,6 +449,10 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) option_parser_register(opp, "-gpgpu_kernel_launch_latency", OPT_INT32, &g_kernel_launch_latency, "Kernel launch latency in cycles. Default: 0", "0"); + extern bool g_cdp_enabled; + option_parser_register(opp, "-gpgpu_cdp_enabled", OPT_BOOL, + &g_cdp_enabled, "Turn on CDP", + "0"); } ///////////////////////////////////////////////////////////////////////////// -- cgit v1.3 From 35cf76f383ec8de6de901bbbcd8fb478f69e46e4 Mon Sep 17 00:00:00 2001 From: sspenst Date: Wed, 6 Jul 2016 13:56:52 -0700 Subject: Added sstarr memory, which works the same as shared memory --- cuobjdump_to_ptxplus/ptx_parser.h | 1 + src/abstract_hardware_model.h | 1 + src/cuda-sim/cuda-sim.cc | 8 +++++ src/cuda-sim/instructions.cc | 65 +++++++++++++++++++++++++++++++++++++++ src/cuda-sim/ptx.l | 1 + src/cuda-sim/ptx.y | 2 ++ src/cuda-sim/ptx_ir.h | 6 ++++ src/cuda-sim/ptx_parser.cc | 14 +++++++++ src/cuda-sim/ptx_sim.cc | 1 + src/cuda-sim/ptx_sim.h | 1 + 10 files changed, 100 insertions(+) diff --git a/cuobjdump_to_ptxplus/ptx_parser.h b/cuobjdump_to_ptxplus/ptx_parser.h index 1c96b46..22377b2 100644 --- a/cuobjdump_to_ptxplus/ptx_parser.h +++ b/cuobjdump_to_ptxplus/ptx_parser.h @@ -58,6 +58,7 @@ enum _memory_space_t { reg_space, local_space, shared_space, + sstarr_space, param_space_unclassified, param_space_kernel, /* global to all threads in a kernel : read-only */ param_space_local, /* local to a thread : read-writable */ diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index b29f918..750eb6a 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -41,6 +41,7 @@ enum _memory_space_t { reg_space, local_space, shared_space, + sstarr_space, param_space_unclassified, param_space_kernel, /* global to all threads in a kernel : read-only */ param_space_local, /* local to a thread : read-writable */ diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 09e9a81..57da23f 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1407,6 +1407,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, std::list &active_threads = kernel.active_threads(); static std::map shared_memory_lookup; + static std::map sstarr_memory_lookup; static std::map ptx_cta_lookup; static std::map > local_memory_lookup; @@ -1450,6 +1451,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, //initializing new CTA ptx_cta_info *cta_info = NULL; memory_space *shared_mem = NULL; + memory_space *sstarr_mem = NULL; unsigned cta_size = kernel.threads_per_cta(); unsigned max_cta_per_sm = num_threads/cta_size; // e.g., 256 / 48 = 5 @@ -1466,6 +1468,9 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, snprintf(buf,512,"shared_%u", sid); shared_mem = new memory_space_impl<16*1024>(buf,4); shared_memory_lookup[sm_idx] = shared_mem; + snprintf(buf,512,"sstarr_%u", sid); + sstarr_mem = new memory_space_impl<16*1024>(buf,4); + sstarr_memory_lookup[sm_idx] = sstarr_mem; cta_info = new ptx_cta_info(sm_idx); ptx_cta_lookup[sm_idx] = cta_info; } else { @@ -1474,6 +1479,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, sm_idx, sid, max_cta_per_sm ); } shared_mem = shared_memory_lookup[sm_idx]; + sstarr_mem = sstarr_memory_lookup[sm_idx]; cta_info = ptx_cta_lookup[sm_idx]; cta_info->check_cta_thread_status_and_reset(); } @@ -1506,9 +1512,11 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, thd->cpy_tid_to_reg(tid3d); thd->set_valid(); thd->m_shared_mem = shared_mem; + thd->m_sstarr_mem = sstarr_mem; function_info *finfo = thd->func_info(); symbol_table *st = finfo->get_symtab(); thd->func_info()->param_to_shared(thd->m_shared_mem,st); + thd->func_info()->param_to_shared(thd->m_sstarr_mem,st); thd->m_cta_info = cta_info; cta_info->add_thread(thd); thd->m_local_mem = local_mem; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 36aa29f..4eb5ce3 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -130,6 +130,8 @@ ptx_reg_t ptx_thread_info::get_operand_value( const operand_info &op, operand_in result.u64 = sym->get_address() + op.get_addr_offset(); } else if ( op.is_shared() ) { result.u64 = op.get_symbol()->get_address() + op.get_addr_offset(); + } else if ( op.is_sstarr() ) { + result.u64 = op.get_symbol()->get_address() + op.get_addr_offset(); } else { const char *name = op.name().c_str(); printf("GPGPU-Sim PTX: ERROR ** get_operand_value : unknown memory operand type for %s\n", name ); @@ -142,6 +144,8 @@ ptx_reg_t ptx_thread_info::get_operand_value( const operand_info &op, operand_in result.u64 = op.get_symbol()->get_address(); } else if ( op.is_shared() ) { result.u64 = op.get_symbol()->get_address(); + } else if ( op.is_sstarr() ) { + result.u64 = op.get_symbol()->get_address(); } else if ( op.is_const() ) { result.u64 = op.get_symbol()->get_address(); } else if ( op.is_global() ) { @@ -2347,6 +2351,7 @@ void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand case surf_space: mem = thread->get_surf_memory(); break; case param_space_kernel: mem = thread->get_param_memory(); break; case shared_space: mem = thread->m_shared_mem; break; + case sstarr_space: mem = thread->m_sstarr_mem; break; case const_space: mem = thread->get_global_memory(); break; case generic_space: if( thread->get_ptx_version().ver() >= 2.0 ) { @@ -3736,7 +3741,67 @@ void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { + const operand_info &src1 = pI->src1(); + const operand_info &src3 = pI->src3(); //may be scalar or vector of regs + unsigned type = pI->get_type(); + ptx_reg_t addr_reg = thread->get_operand_value(src1, src1, type, thread, 1); + ptx_reg_t src3_data; + memory_space_t space = pI->get_space(); + + memory_space *mem = NULL; + addr_t addr = addr_reg.u32; + + decode_space(space,thread,src1,mem,addr); + + size_t size; + int t; + type_info_key::type_decode(type,size,t); + + src3_data = thread->get_operand_value(src3, src1, type, thread, 1); + mem->write(addr,size/8,&src3_data.s64,thread,pI); + thread->m_last_effective_address = addr; + thread->m_last_memory_space = space; + + printf("SST instruction found.\n"); + + /*const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + + unsigned type = pI->get_type(); + ptx_reg_t addr_reg = thread->get_operand_value(src1, src1, type, thread, 1); + memory_space_t space = pI->get_space(); + + memory_space *mem = NULL; + addr_t addr = addr_reg.u32; + + decode_space(space,thread,src1,mem,addr); + + size_t size; + int t; + type_info_key::type_decode(type,size,t); + + ptx_reg_t src2_data = thread->get_operand_value(src2, src1, type, thread, 1); + ptx_reg_t src3_data = thread->get_operand_value(src3, src1, type, thread, 1); + mem->write(addr,size/8,&src3_data.s64,thread,pI);*/ + + /* + switch ( i_type ) { + case U32_TYPE: + data.u64 = (src1_data.u64 & 0xFFFFFFFF) + (src2_data.u64 & 0xFFFFFFFF); + carry = (data.u64 & 0x100000000)>>32; + break; + case U64_TYPE: + data.u64 = src1_data.u64 + src2_data.u64; + break; + default: assert(0); break; + }*/ + + //thread->set_operand_value(dst, data, i_type, thread, pI, overflow, carry ); + //thread->m_last_effective_address = addr; + //thread->m_last_memory_space = space; } void ssy_impl( const ptx_instruction *pI, ptx_thread_info *thread ) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 49fd790..69349a0 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -177,6 +177,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.section TC; return SECTION_DIRECTIVE; \.shared TC; return SHARED_DIRECTIVE; \.sreg TC; return SREG_DIRECTIVE; +\.sstarr TC; return SSTARR_DIRECTIVE; \.struct TC; return STRUCT_DIRECTIVE; \.surf TC; return SURF_DIRECTIVE; /* not in PTX 2.1 */ \.target TC; return TARGET_DIRECTIVE; diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 4de39d1..97f4ff2 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -64,6 +64,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token SECTION_DIRECTIVE %token SHARED_DIRECTIVE %token SREG_DIRECTIVE +%token SSTARR_DIRECTIVE %token STRUCT_DIRECTIVE %token SURF_DIRECTIVE %token TARGET_DIRECTIVE @@ -339,6 +340,7 @@ addressable_spec: CONST_DIRECTIVE { add_space_spec(const_space,$1); } | LOCAL_DIRECTIVE { add_space_spec(local_space,0); } | PARAM_DIRECTIVE { add_space_spec(param_space_unclassified,0); } | SHARED_DIRECTIVE { add_space_spec(shared_space,0); } + | SSTARR_DIRECTIVE { add_space_spec(sstarr_space,0); } | SURF_DIRECTIVE { add_space_spec(surf_space,0); } | TEX_DIRECTIVE { add_space_spec(tex_space,0); } ; diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 601a13d..7724443 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -222,6 +222,7 @@ public: bool is_label() const { return m_is_label;} bool is_shared() const { return m_is_shared;} + bool is_sstarr() const { return m_is_sstarr;} bool is_const() const { return m_is_const;} bool is_global() const { return m_is_global;} bool is_local() const { return m_is_local;} @@ -279,6 +280,7 @@ private: bool m_address_valid; bool m_is_label; bool m_is_shared; + bool m_is_sstarr; bool m_is_const; bool m_is_global; bool m_is_local; @@ -313,10 +315,12 @@ public: void set_label_address( const symbol *label, unsigned addr ); unsigned next_reg_num() { return ++m_reg_allocator;} addr_t get_shared_next() { return m_shared_next;} + addr_t get_sstarr_next() { return m_sstarr_next;} addr_t get_global_next() { return m_global_next;} addr_t get_local_next() { return m_local_next;} addr_t get_tex_next() { return m_tex_next;} void alloc_shared( unsigned num_bytes ) { m_shared_next += num_bytes;} + void alloc_sstarr( unsigned num_bytes ) { m_sstarr_next += num_bytes;} void alloc_global( unsigned num_bytes ) { m_global_next += num_bytes;} void alloc_local( unsigned num_bytes ) { m_local_next += num_bytes;} void alloc_tex( unsigned num_bytes ) { m_tex_next += num_bytes;} @@ -333,6 +337,7 @@ public: private: unsigned m_reg_allocator; unsigned m_shared_next; + unsigned m_sstarr_next; unsigned m_const_next; unsigned m_global_next; unsigned m_local_next; @@ -703,6 +708,7 @@ public: } return m_value.m_symbolic->is_shared(); } + bool is_sstarr() const { return m_value.m_symbolic->is_sstarr();} bool is_const() const { return m_value.m_symbolic->is_const();} bool is_global() const { return m_value.m_symbolic->is_global();} bool is_local() const { return m_value.m_symbolic->is_local();} diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index 824714a..a53a8fe 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -415,6 +415,20 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident g_last_symbol->set_address( addr+addr_pad ); g_current_symbol_table->alloc_shared( num_bits/8 + addr_pad ); break; + case sstarr_space: + printf("GPGPU-Sim PTX: allocating sstarr region for \"%s\" ", + identifier); + fflush(stdout); + assert( (num_bits%8) == 0 ); + addr = g_current_symbol_table->get_sstarr_next(); + addr_pad = pad_address(addr, num_bits/8, 128); + printf("from 0x%x to 0x%lx (sstarr memory space)\n", + addr+addr_pad, + addr+addr_pad + num_bits/8); + fflush(stdout); + g_last_symbol->set_address( addr+addr_pad ); + g_current_symbol_table->alloc_sstarr( num_bits/8 + addr_pad ); + break; case const_space: if( array_ident == ARRAY_IDENTIFIER_NO_DIM ) { printf("GPGPU-Sim PTX: deferring allocation of constant region for \"%s\" (need size information)\n", identifier ); diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc index 09844ae..511e8d6 100644 --- a/src/cuda-sim/ptx_sim.cc +++ b/src/cuda-sim/ptx_sim.cc @@ -153,6 +153,7 @@ ptx_thread_info::ptx_thread_info( kernel_info_t &kernel ) m_last_memory_space = undefined_space; m_branch_taken = 0; m_shared_mem = NULL; + m_sstarr_mem = NULL; m_cta_info = NULL; m_local_mem = NULL; m_symbol_table = NULL; diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index f926e6d..c66b68c 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -424,6 +424,7 @@ public: memory_space_t m_last_memory_space; dram_callback_t m_last_dram_callback; memory_space *m_shared_mem; + memory_space *m_sstarr_mem; memory_space *m_local_mem; ptx_cta_info *m_cta_info; ptx_reg_t m_last_set_operand_value; -- cgit v1.3 From e841e5f21b9d86910a6cc10de3af016912c43ce0 Mon Sep 17 00:00:00 2001 From: sspenst Date: Wed, 6 Jul 2016 15:08:11 -0700 Subject: Added the ability to load from sstarr memory after data has been stored in it --- src/abstract_hardware_model.cc | 4 +++- src/gpgpu-sim/gpu-sim.cc | 3 +++ src/gpgpu-sim/shader.cc | 1 + src/gpgpu-sim/shader.h | 1 + 4 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index 84d165c..ab83ba4 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -213,6 +213,7 @@ void warp_inst_t::generate_mem_accesses() access_type = is_write? LOCAL_ACC_W: LOCAL_ACC_R; break; case shared_space: break; + case sstarr_space: break; default: assert(0); break; } @@ -220,7 +221,8 @@ void warp_inst_t::generate_mem_accesses() new_addr_type cache_block_size = 0; // in bytes switch( space.get_type() ) { - case shared_space: { + case shared_space: + case sstarr_space: { unsigned subwarp_size = m_config->warp_size / m_config->mem_warp_parts; unsigned total_accesses=0; for( unsigned subwarp=0; subwarp < m_config->mem_warp_parts; subwarp++ ) { diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index eafb909..e7ba8e5 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1049,6 +1049,9 @@ void shader_core_ctx::mem_instruction_stats(const warp_inst_t &inst) case shared_space: m_stats->gpgpu_n_shmem_insn += active_count; break; + case sstarr_space: + m_stats->gpgpu_n_sstarr_insn += active_count; + break; case const_space: m_stats->gpgpu_n_const_insn += active_count; break; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index ff2fac7..9c3f816 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -386,6 +386,7 @@ void shader_core_stats::print( FILE* fout ) const fprintf(fout, "gpgpu_n_load_insn = %d\n", gpgpu_n_load_insn); fprintf(fout, "gpgpu_n_store_insn = %d\n", gpgpu_n_store_insn); fprintf(fout, "gpgpu_n_shmem_insn = %d\n", gpgpu_n_shmem_insn); + fprintf(fout, "gpgpu_n_shmem_insn = %d\n", gpgpu_n_sstarr_insn); fprintf(fout, "gpgpu_n_tex_insn = %d\n", gpgpu_n_tex_insn); fprintf(fout, "gpgpu_n_const_mem_insn = %d\n", gpgpu_n_const_insn); fprintf(fout, "gpgpu_n_param_mem_insn = %d\n", gpgpu_n_param_insn); diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 38d09e9..3b9859f 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1372,6 +1372,7 @@ struct shader_core_stats_pod { unsigned gpgpu_n_load_insn; unsigned gpgpu_n_store_insn; unsigned gpgpu_n_shmem_insn; + unsigned gpgpu_n_sstarr_insn; unsigned gpgpu_n_tex_insn; unsigned gpgpu_n_const_insn; unsigned gpgpu_n_param_insn; -- cgit v1.3 From 7ce3005d27cfa68d6ed1fea001eb22cf0da628c2 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Wed, 6 Jul 2016 16:52:35 -0700 Subject: pull torque queue manger setup for github/travis --- .travis.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.travis.yml b/.travis.yml index 18fcd7a..525fa4a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,5 +1,7 @@ dist: trusty before_install: + - git clone https://github.com/gpgpu-sim/setup_torque_on_ubuntu_14.04.git + - ./setup_torque_on_ubuntu_14.04/install_torque.sh - wget http://developer.download.nvidia.com/compute/cuda/repos/ubuntu1404/x86_64/cuda-repo-ubuntu1404_7.5-18_amd64.deb - sudo dpkg -i cuda-repo-ubuntu1404_7.5-18_amd64.deb - sudo apt-get -qq update -- cgit v1.3 From 7758943c96d22cd65f3de30b36c71b27370de5ce Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Wed, 6 Jul 2016 17:03:58 -0700 Subject: dependencies and directory --- .travis.yml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/.travis.yml b/.travis.yml index 525fa4a..0564709 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,7 +1,8 @@ dist: trusty -before_install: +before_install: + - sudo apt-get install -y libssl-dev libxml2-dev libboost-all-dev - git clone https://github.com/gpgpu-sim/setup_torque_on_ubuntu_14.04.git - - ./setup_torque_on_ubuntu_14.04/install_torque.sh + - cd ./setup_torque_on_ubuntu_14.04; ./install_torque.sh; cd - - wget http://developer.download.nvidia.com/compute/cuda/repos/ubuntu1404/x86_64/cuda-repo-ubuntu1404_7.5-18_amd64.deb - sudo dpkg -i cuda-repo-ubuntu1404_7.5-18_amd64.deb - sudo apt-get -qq update -- cgit v1.3 From 320631e64d6d9e4ccdac175621858642b7b12265 Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 7 Jul 2016 09:35:49 -0700 Subject: Rough implementation of the SST instruction. It squeezes out the zeros that are in the sstarr memory and writes the data back into sstarr memory. --- src/cuda-sim/instructions.cc | 91 ++++++++++++++++++++++++-------------------- 1 file changed, 49 insertions(+), 42 deletions(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 4eb5ce3..47f7075 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3741,15 +3741,16 @@ void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { + // Step 1: store data in sstarr memory const operand_info &src1 = pI->src1(); - const operand_info &src3 = pI->src3(); //may be scalar or vector of regs + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); unsigned type = pI->get_type(); - ptx_reg_t addr_reg = thread->get_operand_value(src1, src1, type, thread, 1); - ptx_reg_t src3_data; + ptx_reg_t src1_data = thread->get_operand_value(src1, src1, type, thread, 1); + ptx_reg_t src2_data, src3_data; memory_space_t space = pI->get_space(); - memory_space *mem = NULL; - addr_t addr = addr_reg.u32; + addr_t addr = src1_data.u32; decode_space(space,thread,src1,mem,addr); @@ -3757,51 +3758,57 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) int t; type_info_key::type_decode(type,size,t); + src2_data = thread->get_operand_value(src2, src1, type, thread, 1); src3_data = thread->get_operand_value(src3, src1, type, thread, 1); mem->write(addr,size/8,&src3_data.s64,thread,pI); + thread->m_last_effective_address = addr; thread->m_last_memory_space = space; + // Step 2: __syncthreads() to make sure all data is stored in sstarr memory + // (function must be called with dst = 0 so that all threads execute bar.sync 0) + ptx_instruction * cpI = const_cast(pI); + const operand_info &dst = cpI->dst(); + ptx_reg_t dst_data; + dst_data = thread->get_operand_value(dst, dst, U32_TYPE, thread, 1); + cpI->set_bar_id(dst_data.u32); + + thread->m_last_dram_callback.function = bar_callback; + thread->m_last_dram_callback.instruction = pI; + + // Step 3: pick only one thread to load all of the data back from sstarr memory + // rearrange the data so that zeros are at the end of the array + // store this data back in the original array (each thread can maybe do this after another sync?) + int NUM_THREADS = 8; + if (src2_data.s64 == NUM_THREADS-1) { + addr -= (NUM_THREADS-1)*4; + unsigned offset = 0; + ptx_reg_t data; + // loop through all of the threads (how do you do this dynamically?) + for (int tid = 0; tid < NUM_THREADS; tid++) { + data.u64=0; + mem->read(addr+(tid*4),size/8,&data.s64); + + // store nonzero entries + if (data.s64 != 0) { + mem->write(addr+(offset*4),size/8,&data.s64,thread,pI); + thread->m_last_effective_address = addr+(offset*4); + offset++; + } + } + // fill the rest of the array with zeros + while (offset < NUM_THREADS) { + mem->write(addr+(offset*4),size/8,&src2_data.s64,thread,pI); + thread->m_last_effective_address = addr+(offset*4); + offset++; + } - printf("SST instruction found.\n"); - - /*const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - - unsigned type = pI->get_type(); - ptx_reg_t addr_reg = thread->get_operand_value(src1, src1, type, thread, 1); - memory_space_t space = pI->get_space(); - - memory_space *mem = NULL; - addr_t addr = addr_reg.u32; - - decode_space(space,thread,src1,mem,addr); + // Step 4: load from sstarr memory and store data back into original array - size_t size; - int t; - type_info_key::type_decode(type,size,t); + } - ptx_reg_t src2_data = thread->get_operand_value(src2, src1, type, thread, 1); - ptx_reg_t src3_data = thread->get_operand_value(src3, src1, type, thread, 1); - mem->write(addr,size/8,&src3_data.s64,thread,pI);*/ - - /* - switch ( i_type ) { - case U32_TYPE: - data.u64 = (src1_data.u64 & 0xFFFFFFFF) + (src2_data.u64 & 0xFFFFFFFF); - carry = (data.u64 & 0x100000000)>>32; - break; - case U64_TYPE: - data.u64 = src1_data.u64 + src2_data.u64; - break; - default: assert(0); break; - }*/ - - //thread->set_operand_value(dst, data, i_type, thread, pI, overflow, carry ); - //thread->m_last_effective_address = addr; - //thread->m_last_memory_space = space; + //if( type == S16_TYPE || type == S32_TYPE ) sign_extend(data,size,dst); + //thread->set_operand_value(dst,data, type, thread, pI); } void ssy_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -- cgit v1.3 From 19595382f05235b8887955c76794a976fad04833 Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 7 Jul 2016 11:53:56 -0700 Subject: SST instruction now updates the original array instead of storing the result in sstarr memory --- src/abstract_hardware_model.h | 1 + src/cuda-sim/instructions.cc | 49 ++++++++++++++++++++++++------------------- 2 files changed, 28 insertions(+), 22 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 750eb6a..6ed9b8e 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -554,6 +554,7 @@ public: return false; } enum _memory_space_t get_type() const { return m_type; } + void set_type( enum _memory_space_t t ) { m_type = t; } unsigned get_bank() const { return m_bank; } void set_bank( unsigned b ) { m_bank = b; } bool is_const() const { return (m_type == const_space) || (m_type == param_space_kernel); } diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 47f7075..d4b74fa 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3747,10 +3747,11 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) const operand_info &src3 = pI->src3(); unsigned type = pI->get_type(); ptx_reg_t src1_data = thread->get_operand_value(src1, src1, type, thread, 1); - ptx_reg_t src2_data, src3_data; + ptx_reg_t src2_data = thread->get_operand_value(src2, src1, type, thread, 1); + ptx_reg_t src3_data = thread->get_operand_value(src3, src1, type, thread, 1); memory_space_t space = pI->get_space(); memory_space *mem = NULL; - addr_t addr = src1_data.u32; + addr_t addr = src2_data.u32 * 4; // this assumes sstarr memory starts at address 0 decode_space(space,thread,src1,mem,addr); @@ -3758,13 +3759,8 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) int t; type_info_key::type_decode(type,size,t); - src2_data = thread->get_operand_value(src2, src1, type, thread, 1); - src3_data = thread->get_operand_value(src3, src1, type, thread, 1); mem->write(addr,size/8,&src3_data.s64,thread,pI); - thread->m_last_effective_address = addr; - thread->m_last_memory_space = space; - // Step 2: __syncthreads() to make sure all data is stored in sstarr memory // (function must be called with dst = 0 so that all threads execute bar.sync 0) ptx_instruction * cpI = const_cast(pI); @@ -3776,35 +3772,44 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) thread->m_last_dram_callback.function = bar_callback; thread->m_last_dram_callback.instruction = pI; - // Step 3: pick only one thread to load all of the data back from sstarr memory - // rearrange the data so that zeros are at the end of the array - // store this data back in the original array (each thread can maybe do this after another sync?) - int NUM_THREADS = 8; + + int NUM_THREADS = 8; // (how do you get this dynamically?) if (src2_data.s64 == NUM_THREADS-1) { - addr -= (NUM_THREADS-1)*4; + // Step 3: pick only one thread to load all of the data back from sstarr memory unsigned offset = 0; + addr -= (NUM_THREADS-1)*4; ptx_reg_t data; - // loop through all of the threads (how do you do this dynamically?) + float sstarr_fdata[NUM_THREADS]; + signed long long sstarr_ldata[NUM_THREADS]; + // loop through all of the threads for (int tid = 0; tid < NUM_THREADS; tid++) { data.u64=0; mem->read(addr+(tid*4),size/8,&data.s64); + sstarr_fdata[tid] = data.f32; + sstarr_ldata[tid] = data.s64; + } - // store nonzero entries - if (data.s64 != 0) { - mem->write(addr+(offset*4),size/8,&data.s64,thread,pI); - thread->m_last_effective_address = addr+(offset*4); + // Step 4: squeeze the zeros out of the array and store data back into original array + mem = NULL; + addr = src1_data.u32; + space.set_type(global_space); + decode_space(space,thread,src1,mem,addr); + // store nonzero entries + for (int tid = 0; tid < NUM_THREADS; tid++) { + if (sstarr_fdata[tid] != 0) { + mem->write(addr+(offset*4),size/8,&sstarr_ldata[tid],thread,pI); offset++; } } - // fill the rest of the array with zeros + + // fill the rest of the array with zeros (dst should always have a 0 in it) while (offset < NUM_THREADS) { - mem->write(addr+(offset*4),size/8,&src2_data.s64,thread,pI); - thread->m_last_effective_address = addr+(offset*4); + mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI); offset++; } - // Step 4: load from sstarr memory and store data back into original array - + thread->m_last_effective_address = addr+(NUM_THREADS-1)*4; + thread->m_last_memory_space = space; } //if( type == S16_TYPE || type == S32_TYPE ) sign_extend(data,size,dst); -- cgit v1.3 From e61a68f28a887fae5ed49533597349dfd074ebf9 Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 7 Jul 2016 12:43:10 -0700 Subject: SST instruction now returns the end address of the new sparse array --- src/cuda-sim/instructions.cc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index d4b74fa..9e2dfbb 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3802,6 +3802,11 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) } } + // store the return address + data = thread->get_operand_value(src1, dst, type, thread, 1); + data.s64 += 4*(offset-1); // set address to the last spot in the sparse array + thread->set_operand_value(dst, data, type, thread, pI); + // fill the rest of the array with zeros (dst should always have a 0 in it) while (offset < NUM_THREADS) { mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI); @@ -3811,9 +3816,6 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) thread->m_last_effective_address = addr+(NUM_THREADS-1)*4; thread->m_last_memory_space = space; } - - //if( type == S16_TYPE || type == S32_TYPE ) sign_extend(data,size,dst); - //thread->set_operand_value(dst,data, type, thread, pI); } void ssy_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -- cgit v1.3 From 64ad6d76929403d5d4de4e5f0a218cf4ea8cbfbf Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 7 Jul 2016 14:39:45 -0700 Subject: Indices are now stored corresponding to values. SST now returns the number of elements instead of the device memory address --- src/cuda-sim/instructions.cc | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 9e2dfbb..5a7382a 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3776,13 +3776,13 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) int NUM_THREADS = 8; // (how do you get this dynamically?) if (src2_data.s64 == NUM_THREADS-1) { // Step 3: pick only one thread to load all of the data back from sstarr memory - unsigned offset = 0; + long long offset = 0; addr -= (NUM_THREADS-1)*4; ptx_reg_t data; float sstarr_fdata[NUM_THREADS]; signed long long sstarr_ldata[NUM_THREADS]; // loop through all of the threads - for (int tid = 0; tid < NUM_THREADS; tid++) { + for (short tid = 0; tid < NUM_THREADS; tid++) { data.u64=0; mem->read(addr+(tid*4),size/8,&data.s64); sstarr_fdata[tid] = data.f32; @@ -3794,22 +3794,26 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) addr = src1_data.u32; space.set_type(global_space); decode_space(space,thread,src1,mem,addr); - // store nonzero entries + // store nonzero entries and indices for (int tid = 0; tid < NUM_THREADS; tid++) { if (sstarr_fdata[tid] != 0) { + float ftid = (float)tid; mem->write(addr+(offset*4),size/8,&sstarr_ldata[tid],thread,pI); + mem->write(addr+((NUM_THREADS+offset)*4),size/8,&ftid,thread,pI); offset++; } } // store the return address - data = thread->get_operand_value(src1, dst, type, thread, 1); - data.s64 += 4*(offset-1); // set address to the last spot in the sparse array + //data = thread->get_operand_value(src1, dst, type, thread, 1); + //data.s64 += 4*(offset-1); // set address to the last spot in the sparse array + data.s64 = offset-1; thread->set_operand_value(dst, data, type, thread, pI); // fill the rest of the array with zeros (dst should always have a 0 in it) while (offset < NUM_THREADS) { mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI); + mem->write(addr+((NUM_THREADS+offset)*4),size/8,&dst_data.s64,thread,pI); offset++; } -- cgit v1.3 From 1cb439dad25261b0b9617a8fb3e943cf0e0beac1 Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 7 Jul 2016 14:56:16 -0700 Subject: sst_impl cleanup --- src/cuda-sim/instructions.cc | 30 ++++++++++-------------------- 1 file changed, 10 insertions(+), 20 deletions(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 5a7382a..aeaf9e6 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3741,11 +3741,12 @@ void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { - // Step 1: store data in sstarr memory + const operand_info &dst = pI->dst(); const operand_info &src1 = pI->src1(); const operand_info &src2 = pI->src2(); const operand_info &src3 = pI->src3(); unsigned type = pI->get_type(); + ptx_reg_t dst_data = thread->get_operand_value(dst, dst, type, thread, 1); ptx_reg_t src1_data = thread->get_operand_value(src1, src1, type, thread, 1); ptx_reg_t src2_data = thread->get_operand_value(src2, src1, type, thread, 1); ptx_reg_t src3_data = thread->get_operand_value(src3, src1, type, thread, 1); @@ -3759,37 +3760,29 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) int t; type_info_key::type_decode(type,size,t); + // store data in sstarr memory mem->write(addr,size/8,&src3_data.s64,thread,pI); - // Step 2: __syncthreads() to make sure all data is stored in sstarr memory - // (function must be called with dst = 0 so that all threads execute bar.sync 0) - ptx_instruction * cpI = const_cast(pI); - const operand_info &dst = cpI->dst(); - ptx_reg_t dst_data; - dst_data = thread->get_operand_value(dst, dst, U32_TYPE, thread, 1); - cpI->set_bar_id(dst_data.u32); - - thread->m_last_dram_callback.function = bar_callback; - thread->m_last_dram_callback.instruction = pI; - + thread->m_last_effective_address = addr; + thread->m_last_memory_space = space; int NUM_THREADS = 8; // (how do you get this dynamically?) if (src2_data.s64 == NUM_THREADS-1) { - // Step 3: pick only one thread to load all of the data back from sstarr memory - long long offset = 0; + // pick only one thread to load all of the data back from sstarr memory + unsigned offset = 0; addr -= (NUM_THREADS-1)*4; ptx_reg_t data; float sstarr_fdata[NUM_THREADS]; signed long long sstarr_ldata[NUM_THREADS]; // loop through all of the threads - for (short tid = 0; tid < NUM_THREADS; tid++) { + for (int tid = 0; tid < NUM_THREADS; tid++) { data.u64=0; mem->read(addr+(tid*4),size/8,&data.s64); sstarr_fdata[tid] = data.f32; sstarr_ldata[tid] = data.s64; } - // Step 4: squeeze the zeros out of the array and store data back into original array + // squeeze the zeros out of the array and store data back into original array mem = NULL; addr = src1_data.u32; space.set_type(global_space); @@ -3803,10 +3796,7 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) offset++; } } - - // store the return address - //data = thread->get_operand_value(src1, dst, type, thread, 1); - //data.s64 += 4*(offset-1); // set address to the last spot in the sparse array + // store the number of nonzero elements in the array data.s64 = offset-1; thread->set_operand_value(dst, data, type, thread, pI); -- cgit v1.3 From 877cbd077ffaf112b68973fdb7db8f10505303ee Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 8 Jul 2016 12:57:56 -0700 Subject: SST should now properly simulate the barrier operation --- src/cuda-sim/cuda-sim.cc | 4 ++++ src/cuda-sim/instructions.cc | 8 +++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 57da23f..e194a2a 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -572,6 +572,9 @@ void ptx_instruction::set_bar_type() abort(); } } + else if(m_opcode==SST_OP) { + bar_type = SYNC; + } } @@ -635,6 +638,7 @@ void ptx_instruction::set_opcode_and_latency() case TEX_OP: op = LOAD_OP; mem_op=TEX; break; case ATOM_OP: op = LOAD_OP; break; case BAR_OP: op = BARRIER_OP; break; + case SST_OP: op = BARRIER_OP; break; case MEMBAR_OP: op = MEMORY_BARRIER_OP; break; case CALL_OP: { diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index aeaf9e6..8bdb94f 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3741,7 +3741,8 @@ void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { - const operand_info &dst = pI->dst(); + ptx_instruction * cpI = const_cast(pI); // constant + const operand_info &dst = cpI->dst(); const operand_info &src1 = pI->src1(); const operand_info &src2 = pI->src2(); const operand_info &src3 = pI->src3(); @@ -3763,8 +3764,13 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) // store data in sstarr memory mem->write(addr,size/8,&src3_data.s64,thread,pI); + // sync threads + cpI->set_bar_id(dst_data.u32); + thread->m_last_effective_address = addr; thread->m_last_memory_space = space; + thread->m_last_dram_callback.function = bar_callback; + thread->m_last_dram_callback.instruction = cpI; int NUM_THREADS = 8; // (how do you get this dynamically?) if (src2_data.s64 == NUM_THREADS-1) { -- cgit v1.3 From 6c1fb702e17b00fd7de72ac7dd4a31584d5978b9 Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 8 Jul 2016 14:51:44 -0700 Subject: Made gridDim and blockDim global variables so that they can be accessed from sst_impl --- libcuda/cuda_runtime_api.cc | 7 +++++-- src/abstract_hardware_model.h | 3 +++ src/cuda-sim/instructions.cc | 3 +-- src/cuda-sim/opcodes.def | 2 +- 4 files changed, 10 insertions(+), 5 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index e8a0e91..3eff4af 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -180,6 +180,9 @@ cudaError_t g_last_cudaError = cudaSuccess; extern stream_manager *g_stream_manager; +dim3 gridDim = (dim3){1,1,1}; +dim3 blockDim = (dim3){1,1,1}; + void register_ptx_function( const char *name, function_info *impl ) { // no longer need this @@ -959,8 +962,8 @@ __host__ cudaError_t CUDARTAPI cudaLaunch( const char *hostFun ) g_ptx_sim_mode?"functional simulation":"performance simulation", stream?stream->get_uid():0 ); kernel_info_t *grid = gpgpu_cuda_ptx_sim_init_grid(hostFun,config.get_args(),config.grid_dim(),config.block_dim(),context); std::string kname = grid->name(); - dim3 gridDim = config.grid_dim(); - dim3 blockDim = config.block_dim(); + gridDim = config.grid_dim(); + blockDim = config.block_dim(); printf("GPGPU-Sim PTX: pushing kernel \'%s\' to stream %u, gridDim= (%u,%u,%u) blockDim = (%u,%u,%u) \n", kname.c_str(), stream?stream->get_uid():0, gridDim.x,gridDim.y,gridDim.z,blockDim.x,blockDim.y,blockDim.z ); stream_operation op(grid,g_ptx_sim_mode,stream); diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 6ed9b8e..46c3279 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -162,6 +162,9 @@ struct dim3 { }; #endif +extern dim3 gridDim; +extern dim3 blockDim; + void increment_x_then_y_then_z( dim3 &i, const dim3 &bound); class kernel_info_t { diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 8bdb94f..fd3b1fa 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3772,7 +3772,7 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) thread->m_last_dram_callback.function = bar_callback; thread->m_last_dram_callback.instruction = cpI; - int NUM_THREADS = 8; // (how do you get this dynamically?) + int NUM_THREADS = blockDim.x * blockDim.y * blockDim.z; if (src2_data.s64 == NUM_THREADS-1) { // pick only one thread to load all of the data back from sstarr memory unsigned offset = 0; @@ -3809,7 +3809,6 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) // fill the rest of the array with zeros (dst should always have a 0 in it) while (offset < NUM_THREADS) { mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI); - mem->write(addr+((NUM_THREADS+offset)*4),size/8,&dst_data.s64,thread,pI); offset++; } diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 0c0eda9..1af04ea 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -103,7 +103,7 @@ OP_DEF(SHR_OP,shr_impl,"shr",1,1) OP_DEF(SIN_OP,sin_impl,"sin",1,4) OP_DEF(SLCT_OP,slct_impl,"slct",1,1) OP_DEF(SQRT_OP,sqrt_impl,"sqrt",1,4) -OP_DEF(SST_OP,sst_impl,"sst",1,1) +OP_DEF(SST_OP,sst_impl,"sst",1,5) OP_DEF(SSY_OP,ssy_impl,"ssy",0,3) OP_DEF(ST_OP,st_impl,"st",0,5) OP_DEF(SUB_OP,sub_impl,"sub",1,1) -- cgit v1.3 From adc311951d67b0685ebf2fab4ce6410f96f0039a Mon Sep 17 00:00:00 2001 From: sspenst Date: Mon, 11 Jul 2016 11:16:46 -0700 Subject: Reverted the previous commit to add a cleaner way of getting NUM_THREADS. Now, sst_impl doesn't functionally execute on the last indexed element of an array, but instead on the actual last thread that executes --- libcuda/cuda_runtime_api.cc | 7 ++----- src/abstract_hardware_model.h | 3 --- src/cuda-sim/instructions.cc | 13 ++++++++----- src/cuda-sim/ptx_sim.cc | 16 ++++++++++++++++ src/cuda-sim/ptx_sim.h | 4 ++++ 5 files changed, 30 insertions(+), 13 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 3eff4af..e8a0e91 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -180,9 +180,6 @@ cudaError_t g_last_cudaError = cudaSuccess; extern stream_manager *g_stream_manager; -dim3 gridDim = (dim3){1,1,1}; -dim3 blockDim = (dim3){1,1,1}; - void register_ptx_function( const char *name, function_info *impl ) { // no longer need this @@ -962,8 +959,8 @@ __host__ cudaError_t CUDARTAPI cudaLaunch( const char *hostFun ) g_ptx_sim_mode?"functional simulation":"performance simulation", stream?stream->get_uid():0 ); kernel_info_t *grid = gpgpu_cuda_ptx_sim_init_grid(hostFun,config.get_args(),config.grid_dim(),config.block_dim(),context); std::string kname = grid->name(); - gridDim = config.grid_dim(); - blockDim = config.block_dim(); + dim3 gridDim = config.grid_dim(); + dim3 blockDim = config.block_dim(); printf("GPGPU-Sim PTX: pushing kernel \'%s\' to stream %u, gridDim= (%u,%u,%u) blockDim = (%u,%u,%u) \n", kname.c_str(), stream?stream->get_uid():0, gridDim.x,gridDim.y,gridDim.z,blockDim.x,blockDim.y,blockDim.z ); stream_operation op(grid,g_ptx_sim_mode,stream); diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 46c3279..6ed9b8e 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -162,9 +162,6 @@ struct dim3 { }; #endif -extern dim3 gridDim; -extern dim3 blockDim; - void increment_x_then_y_then_z( dim3 &i, const dim3 &bound); class kernel_info_t { diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index fd3b1fa..b5a3db4 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3754,6 +3754,7 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) memory_space_t space = pI->get_space(); memory_space *mem = NULL; addr_t addr = src2_data.u32 * 4; // this assumes sstarr memory starts at address 0 + ptx_cta_info *cta_info = thread->m_cta_info; decode_space(space,thread,src1,mem,addr); @@ -3765,18 +3766,19 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) mem->write(addr,size/8,&src3_data.s64,thread,pI); // sync threads - cpI->set_bar_id(dst_data.u32); + cpI->set_bar_id(16); // use 16 for sst because bar uses an int from 0-15 thread->m_last_effective_address = addr; thread->m_last_memory_space = space; thread->m_last_dram_callback.function = bar_callback; thread->m_last_dram_callback.instruction = cpI; - int NUM_THREADS = blockDim.x * blockDim.y * blockDim.z; - if (src2_data.s64 == NUM_THREADS-1) { - // pick only one thread to load all of the data back from sstarr memory + // the last thread that executes loads all of the data back from sstarr memory + int NUM_THREADS = cta_info->num_threads(); + cta_info->inc_bar_threads(); + if (NUM_THREADS == cta_info->get_bar_threads()) { unsigned offset = 0; - addr -= (NUM_THREADS-1)*4; + addr = 0; ptx_reg_t data; float sstarr_fdata[NUM_THREADS]; signed long long sstarr_ldata[NUM_THREADS]; @@ -3812,6 +3814,7 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) offset++; } + cta_info->reset_bar_threads(); thread->m_last_effective_address = addr+(NUM_THREADS-1)*4; thread->m_last_memory_space = space; } diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc index 511e8d6..f48115b 100644 --- a/src/cuda-sim/ptx_sim.cc +++ b/src/cuda-sim/ptx_sim.cc @@ -44,6 +44,7 @@ ptx_cta_info::ptx_cta_info( unsigned sm_idx ) m_sm_idx = sm_idx; m_uid = g_ptx_cta_info_uid++; + m_bar_threads = 0; } void ptx_cta_info::add_thread( ptx_thread_info *thd ) @@ -128,6 +129,21 @@ unsigned ptx_cta_info::get_sm_idx() const return m_sm_idx; } +unsigned ptx_cta_info::get_bar_threads() const +{ + return m_bar_threads; +} + +void ptx_cta_info::inc_bar_threads() +{ + m_bar_threads++; +} + +void ptx_cta_info::reset_bar_threads() +{ + m_bar_threads = 0; +} + unsigned g_ptx_thread_info_uid_next=1; unsigned g_ptx_thread_info_delete_count=0; diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index c66b68c..4e748e9 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -158,8 +158,12 @@ public: void register_thread_exit( ptx_thread_info *thd ); void register_deleted_thread( ptx_thread_info *thd ); unsigned get_sm_idx() const; + unsigned get_bar_threads() const; + void inc_bar_threads(); + void reset_bar_threads(); private: + unsigned m_bar_threads; unsigned long long m_uid; unsigned m_sm_idx; std::set m_threads_in_cta; -- cgit v1.3 From e08fc0294fe919a198477b771a414c5102430188 Mon Sep 17 00:00:00 2001 From: sspenst Date: Mon, 11 Jul 2016 11:40:23 -0700 Subject: Changed sst return value to be the address instead of index offset --- src/cuda-sim/instructions.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index b5a3db4..b401bef 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3805,7 +3805,8 @@ void sst_impl( const ptx_instruction *pI, ptx_thread_info *thread ) } } // store the number of nonzero elements in the array - data.s64 = offset-1; + data = thread->get_operand_value(src1, dst, type, thread, 1); + data.s64 += 4*(offset-1); thread->set_operand_value(dst, data, type, thread, pI); // fill the rest of the array with zeros (dst should always have a 0 in it) -- cgit v1.3 From feda07a5e0053ef2f2bfa382f5ba9a7a0b6c6bf5 Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 4 Aug 2016 13:09:41 -0700 Subject: A thread executing BSMAD is now able to access information from all threads in its warp --- src/abstract_hardware_model.h | 1 + src/cuda-sim/cuda-sim.cc | 14 ++++ src/cuda-sim/instructions.cc | 158 ++++++++++++++++++++++++++++++++++++++++++ src/cuda-sim/opcodes.def | 3 + src/cuda-sim/opcodes.h | 4 +- src/cuda-sim/ptx.l | 3 + 6 files changed, 182 insertions(+), 1 deletion(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 6ed9b8e..13dfce3 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1053,6 +1053,7 @@ class core_t { warp_inst_t getExecuteWarp(unsigned warpId); void get_pdom_stack_top_info( unsigned warpId, unsigned *pc, unsigned *rpc ) const; kernel_info_t * get_kernel_info(){ return m_kernel;} + class ptx_thread_info ** get_thread_info() { return m_thread; } unsigned get_warp_size() const { return m_warp_size; } void and_reduction(unsigned ctaid, unsigned barid, bool value) { reduction_storage[ctaid][barid] &= value; } void or_reduction(unsigned ctaid, unsigned barid, bool value) { reduction_storage[ctaid][barid] |= value; } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index e194a2a..059fbe2 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -849,8 +849,10 @@ void ptx_instruction::pre_decode() switch ( get_opcode() ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; #include "opcodes.def" #undef OP_DEF +#undef OP_W_DEF default: printf( "Execution error: Invalid opcode (0x%x)\n", get_opcode() ); break; @@ -1242,10 +1244,22 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) *((warp_inst_t*)pJ) = inst; // copy active mask information pI = pJ; } + /*const ptx_instruction **pA; + if( pI->get_opcode() == BSMAD_OP ) { + //pA = (const ptx_instruction**)malloc(get_core()->get_warp_size()*(sizeof(ptx_instruction*))); + pA = (const ptx_instruction**)malloc(8*(sizeof(ptx_instruction*))); + for (int i = 0; i < get_core()->get_warp_size() && inst.active(i); i++) { + //pA[i] = get_core()->get_thread_info()[inst.warp_id() * get_core()->get_warp_size() + i]->func_info()->get_instruction(pc+(i-lane_id)*(pI->inst_size())); + int tid = inst.warp_id() * get_core()->get_warp_size() + i; + pA[i] = get_core()->get_thread_info()[tid]->func_info()->get_instruction(pc); + } + }*/ switch ( pI->get_opcode() ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; #include "opcodes.def" #undef OP_DEF +#undef OP_W_DEF default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break; } delete pJ; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index b401bef..618add1 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -47,8 +47,10 @@ unsigned ptx_instruction::g_num_ptx_inst_uid=0; const char *g_opcode_string[NUM_OPCODES] = { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, #include "opcodes.def" #undef OP_DEF +#undef OP_W_DEF }; void inst_not_implemented( const ptx_instruction * pI ) ; @@ -1456,6 +1458,162 @@ void breakaddr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void brev_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) +{ + for (int i = 0; i < core->get_warp_size() && inst.active(i); i++) { + const operand_info &dst = pI->dst(); + unsigned type = pI->get_type(); + + int tid = inst.warp_id() * core->get_warp_size() + i; + ptx_thread_info *thread = core->get_thread_info()[tid]; + ptx_reg_t data = thread->get_operand_value(dst, dst, type, thread, 1); + printf("BSMAD - DATA FROM THREAD %d: %d\n", i, data.u32); + } + printf("\n"); + /*const unsigned OPERANDS = 9; + // 0 = output + // 1 = input precision + // 2 = output precision + // 3 = buffer0 + // 4 = buffer1 + // 5 = buffer2 + // 6 = buffer3 + // 7 = synapse value + // 8 = output value + // as a temporary solution, let 0 be the base address of output, which is an array of shared memory + // that will be filled when the last thread completes the bsmad instruction + // maybe you can store the addresses of other ptx_instruction in sstarr memory and then update dst later? + // not sure if that works + + //ptx_instruction * cpI = const_cast(pI); + const operand_info &src[OPERANDS]; + ptx_reg_t src_data[OPERANDS]; + unsigned type = pI->get_type(); + + for (int i = 0; i < OPERANDS; i++) { + src[i] = pI->operand_lookup(i); + src_data[i] = thread->get_operand_value(src[i], src[0], type, thread, 1); + } + + memory_space_t space = pI->get_space(); + memory_space *mem = NULL; + addr_t addr = thread->get_tid().x * 24; // 4 bytes per register * 6 registers per thread = 24 bytes + + decode_space(space,thread,src[0],mem,addr); + + size_t size; + int t; + type_info_key::type_decode(type,size,t); + + // store src_data[1:4] in sstarr memory + for (int i = 0; i < 6; i++) { + mem->write(addr + i*4,size/8,&src_data[i+3].s64,thread,pI); + } + + // sync threads + //cpI->set_bar_id(16); // use 16 for sst because bar uses an int from 0-15 + + thread->m_last_effective_address = addr; + thread->m_last_memory_space = space; + thread->m_last_dram_callback.function = bar_callback; + thread->m_last_dram_callback.instruction = cpI; + + // the last thread that executes loads all of the data back from sstarr memory + ptx_cta_info *cta_info = thread->m_cta_info;((32/ip)*4)/(32/op) + const int NUM_THREADS = cta_info->num_threads(); + cta_info->inc_bar_threads(); + if (NUM_THREADS == cta_info->get_bar_threads()) { + // load all things from sstarr memory + addr = 0; + ptx_reg_t data; + unsigned sstarr_data[NUM_THREADS*6]; + for (int i = 0; i < NUM_THREADS*6; i++) { + data.u64 = 0; + mem->read(addr+(i*4),size/8,&data.s64); + sstarr_data[i] = data.u32; + } + + // unpack registers, add data from across threads + unsigned ip = src_data[1].u32; + unsigned op = src_data[2].u32; + unsigned unpacked_output[(32/ip)*4]; + + for (unsigned i = 0; i < (32/ip)*4; i++) { + unsigned buf = i/(32/ip); + unsigned pos = i%(32/ip); + + unsigned mask = 0; + for (int b = 0; b < ip; b++) { + mask |= (1 << b); + } + mask <<= (pos*ip); + + int sum = 0; + for (int j = 0; j < NUM_THREADS; j++) { + sum += mask & sstarr_data[j*6 + buf]; + } + unpacked_output[i] = sum; + } + + // truncate result, repack, store in shared mem + unsigned output_regs[((32/ip)*4)/(32/op) + (((32/ip)*4)%(32/op) != 0)]; + + + + unsigned offset = 0; + addr = 0; + ptx_reg_t data; + float sstarr_fdata[NUM_THREADS]; + signed long long sstarr_ldata[NUM_THREADS]; + // loop through all of the threads + for (int tid = 0; tid < NUM_THREADS; tid++) { + data.u64=0; + mem->read(addr+(tid*4),size/8,&data.s64); + sstarr_fdata[tid] = data.f32; + sstarr_ldata[tid] = data.s64; + } + + // squeeze the zeros out of the array and store data back into original array + mem = NULL; + addr = src1_data.u32; + space.set_type(global_space); + decode_space(space,thread,src1,mem,addr); + // store nonzero entries and indices + for (int tid = 0; tid < NUM_THREADS; tid++) { + if (sstarr_fdata[tid] != 0) { + float ftid = (float)tid; + mem->write(addr+(offset*4),size/8,&sstarr_ldata[tid],thread,pI); + mem->write(addr+((NUM_THREADS+offset)*4),size/8,&ftid,thread,pI); + offset++; + } + } + // store the number of nonzero elements in the array + data = thread->get_op((32/ip)*4)/(32/op)erand_value(src1, dst, type, thread, 1); + data.s64 += 4*(offset-1); + thread->set_operand_value(dst, data, type, thread, pI); + + // fill the rest of the array with zeros (dst should always have a 0 in it) + while (offset < NUM_THREADS) { + mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI); + offset++; + } + + cta_info->reset_bar_threads(); + thread->m_last_effective_address = addr+(NUM_THREADS-1)*4; + thread->m_last_memory_space = space; + }*/ +} + +void bsmul_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + printf("BSMUL instruction found.\n"); +} + +void buf_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + printf("BUF instruction found.\n"); +} + void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { static unsigned call_uid_next = 1; diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 1af04ea..d0e6f25 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -52,6 +52,9 @@ OP_DEF(BRA_OP,bra_impl,"bra",0,3) OP_DEF(BRX_OP,brx_impl,"brx",0,3) OP_DEF(BREV_OP,brev_impl,"brev",1,1) OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9) +OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",0,1) +OP_DEF(BSMUL_OP,bsmul_impl,"bsmul",1,1) +OP_DEF(BUF_OP,buf_impl,"buf",0,5) OP_DEF(CALL_OP,call_impl,"call",1,3) OP_DEF(CALLP_OP,callp_impl,"callp",1,3) OP_DEF(CLZ_OP,clz_impl,"clz",1,1) diff --git a/src/cuda-sim/opcodes.h b/src/cuda-sim/opcodes.h index 871091c..aa133da 100644 --- a/src/cuda-sim/opcodes.h +++ b/src/cuda-sim/opcodes.h @@ -30,9 +30,11 @@ enum opcode_t { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) OP, +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) OP, #include "opcodes.def" - NUM_OPCODES + NUM_OPCODES #undef OP_DEF +#undef OP_W_DEF }; enum special_regs { diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 69349a0..e0d7b9d 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -68,6 +68,9 @@ bra TC; ptx_lval.int_value = BRA_OP; return OPCODE; brx TC; ptx_lval.int_value = BRX_OP; return OPCODE; brev TC; ptx_lval.int_value = BREV_OP; return OPCODE; brkpt TC; ptx_lval.int_value = BRKPT_OP; return OPCODE; +bsmad TC; ptx_lval.int_value = BSMAD_OP; return OPCODE; +bsmul TC; ptx_lval.int_value = BSMUL_OP; return OPCODE; +buf TC; ptx_lval.int_value = BUF_OP; return OPCODE; call TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode callp TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE; clz TC; ptx_lval.int_value = CLZ_OP; return OPCODE; -- cgit v1.3 From 9a6b68c5b11fbdb239d25afe60e5135bc2afa88d Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 5 Aug 2016 10:16:29 -0700 Subject: bsmad gives the correct output in the small cases I have tried, still need to complete the TODOs noted in bsmad_impl --- src/cuda-sim/cuda-sim.cc | 10 -- src/cuda-sim/instructions.cc | 211 +++++++++++++++++++------------------------ src/cuda-sim/opcodes.def | 2 - src/cuda-sim/ptx.l | 2 - 4 files changed, 95 insertions(+), 130 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 059fbe2..337463b 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1244,16 +1244,6 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) *((warp_inst_t*)pJ) = inst; // copy active mask information pI = pJ; } - /*const ptx_instruction **pA; - if( pI->get_opcode() == BSMAD_OP ) { - //pA = (const ptx_instruction**)malloc(get_core()->get_warp_size()*(sizeof(ptx_instruction*))); - pA = (const ptx_instruction**)malloc(8*(sizeof(ptx_instruction*))); - for (int i = 0; i < get_core()->get_warp_size() && inst.active(i); i++) { - //pA[i] = get_core()->get_thread_info()[inst.warp_id() * get_core()->get_warp_size() + i]->func_info()->get_instruction(pc+(i-lane_id)*(pI->inst_size())); - int tid = inst.warp_id() * get_core()->get_warp_size() + i; - pA[i] = get_core()->get_thread_info()[tid]->func_info()->get_instruction(pc); - } - }*/ switch ( pI->get_opcode() ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; #define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 618add1..f58c4f5 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1460,17 +1460,7 @@ void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { - for (int i = 0; i < core->get_warp_size() && inst.active(i); i++) { - const operand_info &dst = pI->dst(); - unsigned type = pI->get_type(); - - int tid = inst.warp_id() * core->get_warp_size() + i; - ptx_thread_info *thread = core->get_thread_info()[tid]; - ptx_reg_t data = thread->get_operand_value(dst, dst, type, thread, 1); - printf("BSMAD - DATA FROM THREAD %d: %d\n", i, data.u32); - } - printf("\n"); - /*const unsigned OPERANDS = 9; + // operands: // 0 = output // 1 = input precision // 2 = output precision @@ -1480,65 +1470,61 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) // 6 = buffer3 // 7 = synapse value // 8 = output value - // as a temporary solution, let 0 be the base address of output, which is an array of shared memory - // that will be filled when the last thread completes the bsmad instruction - // maybe you can store the addresses of other ptx_instruction in sstarr memory and then update dst later? - // not sure if that works - - //ptx_instruction * cpI = const_cast(pI); - const operand_info &src[OPERANDS]; - ptx_reg_t src_data[OPERANDS]; - unsigned type = pI->get_type(); - - for (int i = 0; i < OPERANDS; i++) { - src[i] = pI->operand_lookup(i); - src_data[i] = thread->get_operand_value(src[i], src[0], type, thread, 1); - } - - memory_space_t space = pI->get_space(); - memory_space *mem = NULL; - addr_t addr = thread->get_tid().x * 24; // 4 bytes per register * 6 registers per thread = 24 bytes - - decode_space(space,thread,src[0],mem,addr); - - size_t size; - int t; - type_info_key::type_decode(type,size,t); - - // store src_data[1:4] in sstarr memory - for (int i = 0; i < 6; i++) { - mem->write(addr + i*4,size/8,&src_data[i+3].s64,thread,pI); - } - - // sync threads - //cpI->set_bar_id(16); // use 16 for sst because bar uses an int from 0-15 - - thread->m_last_effective_address = addr; - thread->m_last_memory_space = space; - thread->m_last_dram_callback.function = bar_callback; - thread->m_last_dram_callback.instruction = cpI; - // the last thread that executes loads all of the data back from sstarr memory - ptx_cta_info *cta_info = thread->m_cta_info;((32/ip)*4)/(32/op) + // TODO: what should happen when the output precision is larger than the input precision? + // TODO: create a ptx_warp_info that can do the same thing that ptx_cta_info does here + ptx_cta_info *cta_info = core->get_thread_info()[inst.warp_id() * core->get_warp_size()]->m_cta_info; const int NUM_THREADS = cta_info->num_threads(); + const int NUM_BUFFERS = 4; cta_info->inc_bar_threads(); - if (NUM_THREADS == cta_info->get_bar_threads()) { - // load all things from sstarr memory - addr = 0; - ptx_reg_t data; - unsigned sstarr_data[NUM_THREADS*6]; - for (int i = 0; i < NUM_THREADS*6; i++) { - data.u64 = 0; - mem->read(addr+(i*4),size/8,&data.s64); - sstarr_data[i] = data.u32; - } - // unpack registers, add data from across threads - unsigned ip = src_data[1].u32; - unsigned op = src_data[2].u32; - unsigned unpacked_output[(32/ip)*4]; + // threads within the warp are executed sequentially by the simulator, store output in first four registers + if (cta_info->get_bar_threads() <= NUM_BUFFERS) { + unsigned ip, op; // only get these when i = 0 + unsigned buffer[inst.active_count()][NUM_BUFFERS]; + unsigned synapse[inst.active_count()]; + unsigned output[NUM_BUFFERS]; + + // loop through all threads in the warp and get all data + for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { + if (inst.active(i)) { + const operand_info dst = pI->dst(); + const operand_info src1 = pI->operand_lookup(1); + const operand_info src2 = pI->operand_lookup(2); + const operand_info src3 = pI->operand_lookup(3); + const operand_info src4 = pI->operand_lookup(4); + const operand_info src5 = pI->operand_lookup(5); + const operand_info src6 = pI->operand_lookup(6); + const operand_info src7 = pI->operand_lookup(7); + const operand_info src8 = pI->operand_lookup(8); + unsigned type = pI->get_type(); + + int tid = inst.warp_id() * core->get_warp_size() + i; + ptx_thread_info *thread = core->get_thread_info()[tid]; + + // only get precision data once + if (j == 0) { + ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; + op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; + } + // get buffer data and synapse data from each thread + buffer[j][0] = (thread->get_operand_value(src3, dst, type, thread, 1)).u32; + buffer[j][1] = (thread->get_operand_value(src4, dst, type, thread, 1)).u32; + buffer[j][2] = (thread->get_operand_value(src5, dst, type, thread, 1)).u32; + buffer[j][3] = (thread->get_operand_value(src6, dst, type, thread, 1)).u32; + synapse[j] = (thread->get_operand_value(src7, dst, type, thread, 1)).u32; + // get output data from the first 4 threads + if (j < NUM_BUFFERS) { + output[j] = (thread->get_operand_value(src8, dst, type, thread, 1)).u32; + } + j++; + } + } - for (unsigned i = 0; i < (32/ip)*4; i++) { + // unpack registers, compute enough outputs to fill an output register + unsigned *unpacked_output = (unsigned*)calloc(32/op,sizeof(unsigned)); + unsigned buffer_data_start = (32/op)*(cta_info->get_bar_threads()-1); + for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*NUM_BUFFERS; i++) { unsigned buf = i/(32/ip); unsigned pos = i%(32/ip); @@ -1550,68 +1536,61 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) int sum = 0; for (int j = 0; j < NUM_THREADS; j++) { - sum += mask & sstarr_data[j*6 + buf]; + sum += (mask & buffer[j][buf]) >> (pos*ip); } - unpacked_output[i] = sum; + unpacked_output[i - buffer_data_start] = sum; } - // truncate result, repack, store in shared mem - unsigned output_regs[((32/ip)*4)/(32/op) + (((32/ip)*4)%(32/op) != 0)]; - - + // truncate output + for (unsigned i = 0; i < 32/op; i++) { + int mask = 1, latest_one = -1; + unsigned data = unpacked_output[i]; + for (unsigned j = 0; j < sizeof(unsigned)*8; j++) { + int bit = data & mask; + if (bit == 1) latest_one = j; + data >>= 1; + } + if (latest_one >= op) { + // round_up is 1 if the most significant truncated digit is a 1, otherwise it is 0 + int round_up = (unpacked_output[i] & (1 << (latest_one-op))) >> (latest_one-op); + unsigned shifted_output = unpacked_output[i] >> (latest_one-op+1); + // if shifted_output is a number like 1111, don't round up + if (shifted_output == (pow(2,op)-1)) round_up = 0; + unpacked_output[i] = shifted_output + round_up; + } + } - unsigned offset = 0; - addr = 0; - ptx_reg_t data; - float sstarr_fdata[NUM_THREADS]; - signed long long sstarr_ldata[NUM_THREADS]; - // loop through all of the threads - for (int tid = 0; tid < NUM_THREADS; tid++) { - data.u64=0; - mem->read(addr+(tid*4),size/8,&data.s64); - sstarr_fdata[tid] = data.f32; - sstarr_ldata[tid] = data.s64; + // create mask of 1s + unsigned mask = 0; + for (int b = 0; b < op; b++) { + mask |= (1 << b); } - // squeeze the zeros out of the array and store data back into original array - mem = NULL; - addr = src1_data.u32; - space.set_type(global_space); - decode_space(space,thread,src1,mem,addr); - // store nonzero entries and indices - for (int tid = 0; tid < NUM_THREADS; tid++) { - if (sstarr_fdata[tid] != 0) { - float ftid = (float)tid; - mem->write(addr+(offset*4),size/8,&sstarr_ldata[tid],thread,pI); - mem->write(addr+((NUM_THREADS+offset)*4),size/8,&ftid,thread,pI); - offset++; - } + // pack the outputs into one register + unsigned output_data = 0; + for (int i = 0; i < 32/op; i++) { + output_data |= (unpacked_output[i] & mask) << (op*i); } - // store the number of nonzero elements in the array - data = thread->get_op((32/ip)*4)/(32/op)erand_value(src1, dst, type, thread, 1); - data.s64 += 4*(offset-1); - thread->set_operand_value(dst, data, type, thread, pI); - // fill the rest of the array with zeros (dst should always have a 0 in it) - while (offset < NUM_THREADS) { - mem->write(addr+(offset*4),size/8,&dst_data.s64,thread,pI); - offset++; + // store the result in the correct thread's output register + for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { + if (inst.active(i)) j++; + if (j == cta_info->get_bar_threads()) { + const operand_info &dst = pI->dst(); + unsigned type = pI->get_type(); + int tid = inst.warp_id() * core->get_warp_size() + i; + ptx_thread_info *thread = core->get_thread_info()[tid]; + ptx_reg_t data; + data.u32 = output_data; + thread->set_operand_value(dst, data, type, thread, pI); + break; + } } + } + if (cta_info->get_bar_threads() == NUM_THREADS) { cta_info->reset_bar_threads(); - thread->m_last_effective_address = addr+(NUM_THREADS-1)*4; - thread->m_last_memory_space = space; - }*/ -} - -void bsmul_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - printf("BSMUL instruction found.\n"); -} - -void buf_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - printf("BUF instruction found.\n"); + } } void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index d0e6f25..021eed8 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -53,8 +53,6 @@ OP_DEF(BRX_OP,brx_impl,"brx",0,3) OP_DEF(BREV_OP,brev_impl,"brev",1,1) OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9) OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",0,1) -OP_DEF(BSMUL_OP,bsmul_impl,"bsmul",1,1) -OP_DEF(BUF_OP,buf_impl,"buf",0,5) OP_DEF(CALL_OP,call_impl,"call",1,3) OP_DEF(CALLP_OP,callp_impl,"callp",1,3) OP_DEF(CLZ_OP,clz_impl,"clz",1,1) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index e0d7b9d..001ec04 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -69,8 +69,6 @@ brx TC; ptx_lval.int_value = BRX_OP; return OPCODE; brev TC; ptx_lval.int_value = BREV_OP; return OPCODE; brkpt TC; ptx_lval.int_value = BRKPT_OP; return OPCODE; bsmad TC; ptx_lval.int_value = BSMAD_OP; return OPCODE; -bsmul TC; ptx_lval.int_value = BSMUL_OP; return OPCODE; -buf TC; ptx_lval.int_value = BUF_OP; return OPCODE; call TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode callp TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE; clz TC; ptx_lval.int_value = CLZ_OP; return OPCODE; -- cgit v1.3 From d1b45cf53a39261663a3eff0d409d6c1220d923d Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 5 Aug 2016 14:45:56 -0700 Subject: Added ptx_warp_info to know how many threads within a warp have executed --- src/abstract_hardware_model.h | 2 + src/cuda-sim/cuda-sim.cc | 10 +++++ src/cuda-sim/instructions.cc | 95 +++++++++++++++++++++++-------------------- src/cuda-sim/ptx_sim.cc | 21 ++++++++++ src/cuda-sim/ptx_sim.h | 12 ++++++ 5 files changed, 95 insertions(+), 45 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 13dfce3..cfa8c9f 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1028,6 +1028,7 @@ class core_t { m_warp_count += 1; } assert( m_warp_count * m_warp_size > 0 ); + //m_warp = ( ptx_warp_info** )calloc( m_warp_count, sizeof( ptx_warp_info* ) ); m_thread = ( ptx_thread_info** ) calloc( m_warp_count * m_warp_size, sizeof( ptx_thread_info* ) ); @@ -1063,6 +1064,7 @@ class core_t { class gpgpu_sim *m_gpu; kernel_info_t *m_kernel; simt_stack **m_simt_stack; // pdom based reconvergence context for each warp + //class ptx_warp_info ** m_warp; class ptx_thread_info ** m_thread; unsigned m_warp_size; unsigned m_warp_count; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 337463b..ba0d00b 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1417,6 +1417,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, static std::map shared_memory_lookup; static std::map sstarr_memory_lookup; static std::map ptx_cta_lookup; + static std::map ptx_warp_lookup; static std::map > local_memory_lookup; if ( *thread_info != NULL ) { @@ -1501,6 +1502,15 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, new_tid += tid; ptx_thread_info *thd = new ptx_thread_info(kernel); + ptx_warp_info *warp_info = NULL; + if ( ptx_warp_lookup.find(hw_warp_id) == ptx_warp_lookup.end() ) { + warp_info = new ptx_warp_info(); // num_threads should be threads in the warp + ptx_warp_lookup[hw_warp_id] = warp_info; + } else { + warp_info = ptx_warp_lookup[hw_warp_id]; + } + thd->m_warp_info = warp_info; + memory_space *local_mem = NULL; std::map::iterator l = local_mem_lookup.find(new_tid); if ( l != local_mem_lookup.end() ) { diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index f58c4f5..9dcc25c 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1471,74 +1471,81 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) // 7 = synapse value // 8 = output value - // TODO: what should happen when the output precision is larger than the input precision? - // TODO: create a ptx_warp_info that can do the same thing that ptx_cta_info does here - ptx_cta_info *cta_info = core->get_thread_info()[inst.warp_id() * core->get_warp_size()]->m_cta_info; - const int NUM_THREADS = cta_info->num_threads(); - const int NUM_BUFFERS = 4; - cta_info->inc_bar_threads(); + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + unsigned type = pI->get_type(); + int tid = inst.warp_id() * core->get_warp_size(); + ptx_thread_info *thread = core->get_thread_info()[tid]; + const int ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; + const int op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; + const int THREADS = inst.active_count(); + const int INBUFFERS = 4; + const int OUTBUFFERS = (((32/ip)*INBUFFERS) / (32/op)) + ((((32/ip)*INBUFFERS) % (32/op)) != 0); + if (OUTBUFFERS > THREADS) { + printf("GPGPU-Sim PTX: BSMAD ERROR - Number of output registers required (%d) is greater than the number available (%d)\n", OUTBUFFERS, THREADS); + abort(); + } + ptx_warp_info *warp_info = core->get_thread_info()[inst.warp_id() * core->get_warp_size()]->m_warp_info; + warp_info->inc_done_threads(); // threads within the warp are executed sequentially by the simulator, store output in first four registers - if (cta_info->get_bar_threads() <= NUM_BUFFERS) { - unsigned ip, op; // only get these when i = 0 - unsigned buffer[inst.active_count()][NUM_BUFFERS]; + if (warp_info->get_done_threads() <= OUTBUFFERS) { + unsigned buffer[inst.active_count()][INBUFFERS]; unsigned synapse[inst.active_count()]; - unsigned output[NUM_BUFFERS]; + unsigned output; // loop through all threads in the warp and get all data for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { if (inst.active(i)) { - const operand_info dst = pI->dst(); - const operand_info src1 = pI->operand_lookup(1); - const operand_info src2 = pI->operand_lookup(2); - const operand_info src3 = pI->operand_lookup(3); - const operand_info src4 = pI->operand_lookup(4); - const operand_info src5 = pI->operand_lookup(5); - const operand_info src6 = pI->operand_lookup(6); - const operand_info src7 = pI->operand_lookup(7); - const operand_info src8 = pI->operand_lookup(8); - unsigned type = pI->get_type(); - - int tid = inst.warp_id() * core->get_warp_size() + i; - ptx_thread_info *thread = core->get_thread_info()[tid]; - - // only get precision data once - if (j == 0) { - ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; - op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; - } + const operand_info &src3 = pI->operand_lookup(3); + const operand_info &src4 = pI->operand_lookup(4); + const operand_info &src5 = pI->operand_lookup(5); + const operand_info &src6 = pI->operand_lookup(6); + const operand_info &src7 = pI->operand_lookup(7); + const operand_info &src8 = pI->operand_lookup(8); + + thread = core->get_thread_info()[tid+i]; // get buffer data and synapse data from each thread buffer[j][0] = (thread->get_operand_value(src3, dst, type, thread, 1)).u32; buffer[j][1] = (thread->get_operand_value(src4, dst, type, thread, 1)).u32; buffer[j][2] = (thread->get_operand_value(src5, dst, type, thread, 1)).u32; buffer[j][3] = (thread->get_operand_value(src6, dst, type, thread, 1)).u32; synapse[j] = (thread->get_operand_value(src7, dst, type, thread, 1)).u32; + j++; // get output data from the first 4 threads - if (j < NUM_BUFFERS) { - output[j] = (thread->get_operand_value(src8, dst, type, thread, 1)).u32; + if (j == warp_info->get_done_threads()) { + output = (thread->get_operand_value(src8, dst, type, thread, 1)).u32; } - j++; } } // unpack registers, compute enough outputs to fill an output register unsigned *unpacked_output = (unsigned*)calloc(32/op,sizeof(unsigned)); - unsigned buffer_data_start = (32/op)*(cta_info->get_bar_threads()-1); - for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*NUM_BUFFERS; i++) { + unsigned buffer_data_start = (32/op)*(warp_info->get_done_threads()-1); + for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*INBUFFERS; i++) { unsigned buf = i/(32/ip); unsigned pos = i%(32/ip); - unsigned mask = 0; + int sum = 0; + // sum values from the buffers for (int b = 0; b < ip; b++) { mask |= (1 << b); } mask <<= (pos*ip); - int sum = 0; - for (int j = 0; j < NUM_THREADS; j++) { + for (int j = 0; j < THREADS; j++) { sum += (mask & buffer[j][buf]) >> (pos*ip); } - unpacked_output[i - buffer_data_start] = sum; + // get the previous output + mask = 0; + for (int b = 0; b < op; b++) { + mask |= (1 << b); + } + mask <<= (op*(i-buffer_data_start)); + int past_output = (mask & output) >> (op*(i-buffer_data_start)); + + unpacked_output[i-buffer_data_start] = sum + past_output; } // truncate output @@ -1575,11 +1582,8 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) // store the result in the correct thread's output register for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { if (inst.active(i)) j++; - if (j == cta_info->get_bar_threads()) { - const operand_info &dst = pI->dst(); - unsigned type = pI->get_type(); - int tid = inst.warp_id() * core->get_warp_size() + i; - ptx_thread_info *thread = core->get_thread_info()[tid]; + if (j == warp_info->get_done_threads()) { + thread = core->get_thread_info()[tid+i]; ptx_reg_t data; data.u32 = output_data; thread->set_operand_value(dst, data, type, thread, pI); @@ -1588,8 +1592,9 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) } } - if (cta_info->get_bar_threads() == NUM_THREADS) { - cta_info->reset_bar_threads(); + // once the warp has finished, set the number of completed threads back to 0 for the next warp + if (warp_info->get_done_threads() == THREADS) { + warp_info->reset_done_threads(); } } diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc index f48115b..820287d 100644 --- a/src/cuda-sim/ptx_sim.cc +++ b/src/cuda-sim/ptx_sim.cc @@ -144,6 +144,26 @@ void ptx_cta_info::reset_bar_threads() m_bar_threads = 0; } +ptx_warp_info::ptx_warp_info() +{ + reset_done_threads(); +} + +unsigned ptx_warp_info::get_done_threads() const +{ + return m_done_threads; +} + +void ptx_warp_info::inc_done_threads() +{ + m_done_threads++; +} + +void ptx_warp_info::reset_done_threads() +{ + m_done_threads = 0; +} + unsigned g_ptx_thread_info_uid_next=1; unsigned g_ptx_thread_info_delete_count=0; @@ -170,6 +190,7 @@ ptx_thread_info::ptx_thread_info( kernel_info_t &kernel ) m_branch_taken = 0; m_shared_mem = NULL; m_sstarr_mem = NULL; + m_warp_info = NULL; m_cta_info = NULL; m_local_mem = NULL; m_symbol_table = NULL; diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index 4e748e9..c62fa57 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -171,6 +171,17 @@ private: std::set m_dangling_pointers; }; +class ptx_warp_info { +public: + ptx_warp_info(); // add get_core or something, or threads? + unsigned get_done_threads() const; + void inc_done_threads(); + void reset_done_threads(); + +private: + unsigned m_done_threads; +}; + class symbol; struct stack_entry { @@ -430,6 +441,7 @@ public: memory_space *m_shared_mem; memory_space *m_sstarr_mem; memory_space *m_local_mem; + ptx_warp_info *m_warp_info; ptx_cta_info *m_cta_info; ptx_reg_t m_last_set_operand_value; -- cgit v1.3 From de21c009ca25fbbfd460047c3ae8a3cf59c31454 Mon Sep 17 00:00:00 2001 From: sspenst Date: Fri, 5 Aug 2016 14:50:37 -0700 Subject: Deleted useless comments --- src/abstract_hardware_model.h | 2 -- src/cuda-sim/cuda-sim.cc | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index cfa8c9f..13dfce3 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1028,7 +1028,6 @@ class core_t { m_warp_count += 1; } assert( m_warp_count * m_warp_size > 0 ); - //m_warp = ( ptx_warp_info** )calloc( m_warp_count, sizeof( ptx_warp_info* ) ); m_thread = ( ptx_thread_info** ) calloc( m_warp_count * m_warp_size, sizeof( ptx_thread_info* ) ); @@ -1064,7 +1063,6 @@ class core_t { class gpgpu_sim *m_gpu; kernel_info_t *m_kernel; simt_stack **m_simt_stack; // pdom based reconvergence context for each warp - //class ptx_warp_info ** m_warp; class ptx_thread_info ** m_thread; unsigned m_warp_size; unsigned m_warp_count; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index ba0d00b..53ee25b 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1504,7 +1504,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, ptx_warp_info *warp_info = NULL; if ( ptx_warp_lookup.find(hw_warp_id) == ptx_warp_lookup.end() ) { - warp_info = new ptx_warp_info(); // num_threads should be threads in the warp + warp_info = new ptx_warp_info(); ptx_warp_lookup[hw_warp_id] = warp_info; } else { warp_info = ptx_warp_lookup[hw_warp_id]; -- cgit v1.3 From 8c264f2e77fe628987416269a925bb9930a1b813 Mon Sep 17 00:00:00 2001 From: sspenst Date: Mon, 8 Aug 2016 16:10:43 -0700 Subject: Forgot to multiply by the synapse --- src/abstract_hardware_model.h | 2 +- src/cuda-sim/instructions.cc | 35 ++++++++++++----------------------- 2 files changed, 13 insertions(+), 24 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 13dfce3..c009276 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -788,7 +788,7 @@ public: int src[MAX_REG_OPERANDS]; } arch_reg; //int arch_reg[MAX_REG_OPERANDS]; // register number for bank conflict evaluation - unsigned latency; // operation latency + unsigned latency; // operation latency unsigned initiation_interval; unsigned data_size; // what is the size of the word being operated on? diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 9dcc25c..3b938bb 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1486,13 +1486,13 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) printf("GPGPU-Sim PTX: BSMAD ERROR - Number of output registers required (%d) is greater than the number available (%d)\n", OUTBUFFERS, THREADS); abort(); } - ptx_warp_info *warp_info = core->get_thread_info()[inst.warp_id() * core->get_warp_size()]->m_warp_info; + ptx_warp_info *warp_info = thread->m_warp_info; warp_info->inc_done_threads(); // threads within the warp are executed sequentially by the simulator, store output in first four registers if (warp_info->get_done_threads() <= OUTBUFFERS) { - unsigned buffer[inst.active_count()][INBUFFERS]; - unsigned synapse[inst.active_count()]; + unsigned buffer[THREADS][INBUFFERS]; + unsigned synapse[THREADS]; unsigned output; // loop through all threads in the warp and get all data @@ -1526,25 +1526,15 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*INBUFFERS; i++) { unsigned buf = i/(32/ip); unsigned pos = i%(32/ip); - unsigned mask = 0; - int sum = 0; // sum values from the buffers - for (int b = 0; b < ip; b++) { - mask |= (1 << b); - } - mask <<= (pos*ip); - + int sum = 0; + unsigned mask = (unsigned)(pow(2,ip)-1) << (pos*ip); for (int j = 0; j < THREADS; j++) { - sum += (mask & buffer[j][buf]) >> (pos*ip); + sum += ((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j]; } // get the previous output - mask = 0; - for (int b = 0; b < op; b++) { - mask |= (1 << b); - } - mask <<= (op*(i-buffer_data_start)); + mask = (unsigned)(pow(2,op)-1) << (op*(i-buffer_data_start)); int past_output = (mask & output) >> (op*(i-buffer_data_start)); - unpacked_output[i-buffer_data_start] = sum + past_output; } @@ -1567,13 +1557,8 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) } } - // create mask of 1s - unsigned mask = 0; - for (int b = 0; b < op; b++) { - mask |= (1 << b); - } - // pack the outputs into one register + unsigned mask = pow(2,op)-1; unsigned output_data = 0; for (int i = 0; i < 32/op; i++) { output_data |= (unpacked_output[i] & mask) << (op*i); @@ -1596,6 +1581,10 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) if (warp_info->get_done_threads() == THREADS) { warp_info->reset_done_threads(); } + + // set the latency assuming 4 bits of each input get processed every cycle + // mutable latency variable??? + //pI->latency = (ip+3)/4; } void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -- cgit v1.3 From 45f95f05a11e916933480422b9075767a4cfdf90 Mon Sep 17 00:00:00 2001 From: sspenst Date: Tue, 9 Aug 2016 19:20:02 -0700 Subject: Changed bsmad_impl to match Ahmed's output. Added latency and initiation_interval numbers for bsmad --- src/cuda-sim/cuda-sim.cc | 29 +++++++++++++++++------------ src/cuda-sim/instructions.cc | 30 ++++++++++++++++++++++++++---- src/cuda-sim/opcodes.def | 2 +- 3 files changed, 44 insertions(+), 17 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 53ee25b..4bae236 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -66,9 +66,9 @@ char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp; void ptx_opcocde_latency_options (option_parser_t opp) { option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, - "Opcode latencies for integers " - "Default 1,1,19,25,145", - "1,1,19,25,145"); + "Opcode latencies for integers " + "Default 1,1,19,25,145,1", + "1,1,19,25,145,1"); option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp, "Opcode latencies for single precision floating points " "Default 1,1,1,1,30", @@ -78,9 +78,9 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Default 8,8,8,8,335", "8,8,8,8,335"); option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, - "Opcode initiation intervals for integers " - "Default 1,1,4,4,32", - "1,1,4,4,32"); + "Opcode initiation intervals for integers " + "Default 1,1,4,4,32,1", + "1,1,4,4,32,1"); option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp, "Opcode initiation intervals for single precision floating points " "Default 1,1,1,1,5", @@ -580,10 +580,10 @@ void ptx_instruction::set_bar_type() void ptx_instruction::set_opcode_and_latency() { - unsigned int_latency[5]; + unsigned int_latency[6]; unsigned fp_latency[5]; unsigned dp_latency[5]; - unsigned int_init[5]; + unsigned int_init[6]; unsigned fp_init[5]; unsigned dp_init[5]; /* @@ -592,19 +592,20 @@ void ptx_instruction::set_opcode_and_latency() * [2] MUL * [3] MAD * [4] DIV + * [5] BSMAD */ - sscanf(opcode_latency_int, "%u,%u,%u,%u,%u", + sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u", &int_latency[0],&int_latency[1],&int_latency[2], - &int_latency[3],&int_latency[4]); + &int_latency[3],&int_latency[4],&int_latency[5]); sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u", &fp_latency[0],&fp_latency[1],&fp_latency[2], &fp_latency[3],&fp_latency[4]); sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u", &dp_latency[0],&dp_latency[1],&dp_latency[2], &dp_latency[3],&dp_latency[4]); - sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u", + sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u", &int_init[0],&int_init[1],&int_init[2], - &int_init[3],&int_init[4]); + &int_init[3],&int_init[4],&int_init[5]); sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u", &fp_init[0],&fp_init[1],&fp_init[2], &fp_init[3],&fp_init[4]); @@ -773,6 +774,10 @@ void ptx_instruction::set_opcode_and_latency() initiation_interval = dp_init[2]; op = SFU_OP; break; + case BSMAD_OP: + latency = int_latency[5]; + initiation_interval = int_init[5]; + break; default: break; } diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 3b938bb..bb15621 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1458,6 +1458,26 @@ void breakaddr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void brev_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +unsigned trunc(unsigned num, unsigned precision) { + int mask = 1, latest_one = -1; + unsigned data = num; + for (unsigned j = 0; j < sizeof(unsigned)*8; j++) { + int bit = data & mask; + if (bit == 1) latest_one = j; + data >>= 1; + } + if (latest_one >= precision) { + // round_up is 1 if the most significant truncated digit is a 1, otherwise it is 0 + //int round_up = (num & (1 << (latest_one-precision))) >> (latest_one-precision); + //unsigned shifted_output = num >> (latest_one-precision+1); + // if shifted_output is a number like 1111, don't round up + //if (shifted_output == (pow(2,precision)-1)) round_up = 0; + //num = shifted_output + round_up; + num >>= (latest_one-precision+1); + } + return num; +} + void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { // operands: @@ -1530,16 +1550,18 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) int sum = 0; unsigned mask = (unsigned)(pow(2,ip)-1) << (pos*ip); for (int j = 0; j < THREADS; j++) { - sum += ((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j]; + //sum += ((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j]; + sum += trunc(((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j], op); } // get the previous output mask = (unsigned)(pow(2,op)-1) << (op*(i-buffer_data_start)); int past_output = (mask & output) >> (op*(i-buffer_data_start)); - unpacked_output[i-buffer_data_start] = sum + past_output; + unpacked_output[i-buffer_data_start] = trunc(trunc(sum,op) + past_output,op); + // truncate sum, truncate (truncated sum + past_output) } // truncate output - for (unsigned i = 0; i < 32/op; i++) { + /*for (unsigned i = 0; i < 32/op; i++) { int mask = 1, latest_one = -1; unsigned data = unpacked_output[i]; for (unsigned j = 0; j < sizeof(unsigned)*8; j++) { @@ -1555,7 +1577,7 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) if (shifted_output == (pow(2,op)-1)) round_up = 0; unpacked_output[i] = shifted_output + round_up; } - } + }*/ // pack the outputs into one register unsigned mask = pow(2,op)-1; diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 021eed8..b363dca 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -52,7 +52,7 @@ OP_DEF(BRA_OP,bra_impl,"bra",0,3) OP_DEF(BRX_OP,brx_impl,"brx",0,3) OP_DEF(BREV_OP,brev_impl,"brev",1,1) OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9) -OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",0,1) +OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",1,1) OP_DEF(CALL_OP,call_impl,"call",1,3) OP_DEF(CALLP_OP,callp_impl,"callp",1,3) OP_DEF(CLZ_OP,clz_impl,"clz",1,1) -- cgit v1.3 From 68336f112117bcef5b943650819a6764e9ebf4ce Mon Sep 17 00:00:00 2001 From: sspenst Date: Wed, 24 Aug 2016 15:24:19 -0700 Subject: Added shfl instruction --- src/abstract_hardware_model.h | 1 + src/cuda-sim/cuda-sim.cc | 20 +++++++++++- src/cuda-sim/instructions.cc | 75 +++++++++++++++++++++++++++++++++++++++++++ src/cuda-sim/opcodes.def | 1 + src/cuda-sim/opcodes.h | 4 ++- src/cuda-sim/ptx.l | 6 ++++ src/cuda-sim/ptx.y | 8 +++++ src/cuda-sim/ptx_ir.cc | 6 ++++ src/cuda-sim/ptx_ir.h | 2 ++ src/cuda-sim/ptx_sim.cc | 21 ++++++++++++ src/cuda-sim/ptx_sim.h | 12 +++++++ 11 files changed, 154 insertions(+), 2 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index b29f918..d0c807d 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1051,6 +1051,7 @@ class core_t { warp_inst_t getExecuteWarp(unsigned warpId); void get_pdom_stack_top_info( unsigned warpId, unsigned *pc, unsigned *rpc ) const; kernel_info_t * get_kernel_info(){ return m_kernel;} + class ptx_thread_info ** get_thread_info() { return m_thread; } unsigned get_warp_size() const { return m_warp_size; } void and_reduction(unsigned ctaid, unsigned barid, bool value) { reduction_storage[ctaid][barid] &= value; } void or_reduction(unsigned ctaid, unsigned barid, bool value) { reduction_storage[ctaid][barid] |= value; } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 09e9a81..8bf4ec8 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -769,6 +769,10 @@ void ptx_instruction::set_opcode_and_latency() initiation_interval = dp_init[2]; op = SFU_OP; break; + case SHFL_OP: + latency = 32; + initiation_interval = 15; + break; default: break; } @@ -845,8 +849,10 @@ void ptx_instruction::pre_decode() switch ( get_opcode() ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; #include "opcodes.def" #undef OP_DEF +#undef OP_W_DEF default: printf( "Execution error: Invalid opcode (0x%x)\n", get_opcode() ); break; @@ -1240,8 +1246,10 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) } switch ( pI->get_opcode() ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; #include "opcodes.def" #undef OP_DEF +#undef OP_W_DEF default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break; } delete pJ; @@ -1408,6 +1416,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, static std::map shared_memory_lookup; static std::map ptx_cta_lookup; + static std::map ptx_warp_lookup; static std::map > local_memory_lookup; if ( *thread_info != NULL ) { @@ -1486,7 +1495,16 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, kernel.increment_thread_id(); new_tid += tid; ptx_thread_info *thd = new ptx_thread_info(kernel); - + + ptx_warp_info *warp_info = NULL; + if ( ptx_warp_lookup.find(hw_warp_id) == ptx_warp_lookup.end() ) { + warp_info = new ptx_warp_info(); // num_threads should be threads in the warp + ptx_warp_lookup[hw_warp_id] = warp_info; + } else { + warp_info = ptx_warp_lookup[hw_warp_id]; + } + thd->m_warp_info = warp_info; + memory_space *local_mem = NULL; std::map::iterator l = local_mem_lookup.find(new_tid); if ( l != local_mem_lookup.end() ) { diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 7b0f4fa..05ba78f 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -47,8 +47,10 @@ unsigned ptx_instruction::g_num_ptx_inst_uid=0; const char *g_opcode_string[NUM_OPCODES] = { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, #include "opcodes.def" #undef OP_DEF +#undef OP_W_DEF }; void inst_not_implemented( const ptx_instruction * pI ) ; @@ -3516,6 +3518,79 @@ void set_impl( const ptx_instruction *pI, ptx_thread_info *thread ) } +void shfl_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) +{ + unsigned i_type = pI->get_type(); + int tid = inst.warp_id() * core->get_warp_size(); + ptx_thread_info *thread = core->get_thread_info()[tid]; + ptx_warp_info *warp_info = thread->m_warp_info; + int lane = warp_info->get_done_threads(); + thread = core->get_thread_info()[tid + lane]; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + int bval = (thread->get_operand_value(src2, dst, i_type, thread, 1)).u32; + int cval = (thread->get_operand_value(src3, dst, i_type, thread, 1)).u32; + int mask = cval >> 8; + cval &= 0x1F; + + int maxLane = (lane & mask) | (cval & ~mask); + int minLane = lane & mask; + + int src_idx; + int p; + switch(pI->shfl_op()) { + case UP_OPTION: + src_idx = lane - bval; + p = (src_idx >= maxLane); + break; + case DOWN_OPTION: + src_idx = lane + bval; + p = (src_idx <= maxLane); + break; + case BFLY_OPTION: + src_idx = lane ^ bval; + p = (src_idx <= maxLane); + break; + case IDX_OPTION: + src_idx = minLane | (bval & ~mask); + p = (src_idx <= maxLane); + break; + default: + printf("GPGPU-Sim PTX: ERROR: Unrecognized shfl option\n"); + assert(0); + break; + } + // copy from own lane + if (!p) src_idx = lane; + // copy input from lane src_idx + ptx_reg_t data; + /*if (inst.active(src_idx) && i_type == PRED_TYPE) { + ptx_thread_info *source = core->get_thread_info()[tid + src_idx]; + data = source->get_operand_value(src1, dst, i_type, source, 1); + data.pred = p; + } else { + printf("GPGPU-Sim PTX: WARNING: shfl input value unpredictable for inactive/predicated-off threads in a warp\n"); + data.u32 = 0; + }*/ + if (inst.active(src_idx)) { + ptx_thread_info *source = core->get_thread_info()[tid + src_idx]; + data = source->get_operand_value(src1, dst, i_type, source, 1); + } + if (i_type == PRED_TYPE) { + data.pred = p; + } + thread->set_operand_value(dst, data, i_type, thread, pI); + + // keep track of the number of threads that have executed in the warp + warp_info->inc_done_threads(); + if (warp_info->get_done_threads() == inst.active_count()) { + warp_info->reset_done_threads(); + } +} + void shl_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { ptx_reg_t a, b, d; diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 2ee6976..e1b1422 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -98,6 +98,7 @@ OP_DEF(SAD_OP,sad_impl,"sad",1,1) OP_DEF(SELP_OP,selp_impl,"selp",1,1) OP_DEF(SETP_OP,setp_impl,"setp",1,1) OP_DEF(SET_OP,set_impl,"set",1,1) +OP_W_DEF(SHFL_OP,shfl_impl,"shfl",1,10) OP_DEF(SHL_OP,shl_impl,"shl",1,1) OP_DEF(SHR_OP,shr_impl,"shr",1,1) OP_DEF(SIN_OP,sin_impl,"sin",1,4) diff --git a/src/cuda-sim/opcodes.h b/src/cuda-sim/opcodes.h index 871091c..aa133da 100644 --- a/src/cuda-sim/opcodes.h +++ b/src/cuda-sim/opcodes.h @@ -30,9 +30,11 @@ enum opcode_t { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) OP, +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) OP, #include "opcodes.def" - NUM_OPCODES + NUM_OPCODES #undef OP_DEF +#undef OP_W_DEF }; enum special_regs { diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 88ccf6a..8fac4ac 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -115,6 +115,7 @@ sad TC; ptx_lval.int_value = SAD_OP; return OPCODE; selp TC; ptx_lval.int_value = SELP_OP; return OPCODE; setp TC; ptx_lval.int_value = SETP_OP; return OPCODE; set TC; ptx_lval.int_value = SET_OP; return OPCODE; +shfl TC; ptx_lval.int_value = SHFL_OP; return OPCODE; shl TC; ptx_lval.int_value = SHL_OP; return OPCODE; shr TC; ptx_lval.int_value = SHR_OP; return OPCODE; sin TC; ptx_lval.int_value = SIN_OP; return OPCODE; @@ -329,6 +330,11 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.nc TC; return NC_OPTION; +\.up TC; return UP_OPTION; +\.down TC; return DOWN_OPTION; +\.bfly TC; return BFLY_OPTION; +\.idx TC; return IDX_OPTION; + \.popc TC; return ATOMIC_POPC; \.and TC; return ATOMIC_AND; \.or TC; return ATOMIC_OR; diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 4de39d1..166b15d 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -194,6 +194,10 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token WB_OPTION; %token WT_OPTION; %token NC_OPTION; +%token UP_OPTION; +%token DOWN_OPTION; +%token BFLY_OPTION; +%token IDX_OPTION; %type function_decl_header %type function_decl @@ -451,6 +455,10 @@ option: type_spec | WB_OPTION { add_option(WB_OPTION); } | WT_OPTION { add_option(WT_OPTION); } | NC_OPTION { add_option(NC_OPTION); } + | UP_OPTION { add_option(UP_OPTION); } + | DOWN_OPTION { add_option(DOWN_OPTION); } + | BFLY_OPTION { add_option(BFLY_OPTION); } + | IDX_OPTION { add_option(IDX_OPTION); } ; atomic_operation_spec: ATOMIC_AND { add_option(ATOMIC_AND); } diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 2eccabc..4cfe1b9 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1171,6 +1171,12 @@ ptx_instruction::ptx_instruction( int opcode, break; case NC_OPTION: break; + case UP_OPTION: + case DOWN_OPTION: + case BFLY_OPTION: + case IDX_OPTION: + m_shfl_op = last_ptx_inst_option; + break; default: assert(0); break; diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 601a13d..0abbc83 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -993,6 +993,7 @@ public: unsigned saturation_mode() const { return m_saturation_mode;} unsigned dimension() const { return m_geom_spec;} unsigned barrier_op() const {return m_barrier_op;} + unsigned shfl_op() const {return m_shfl_op;} enum vote_mode_t { vote_any, vote_all, vote_uni, vote_ballot }; enum vote_mode_t vote_mode() const { return m_vote_mode; } @@ -1058,6 +1059,7 @@ private: unsigned m_compare_op; unsigned m_saturation_mode; unsigned m_barrier_op; + unsigned m_shfl_op; std::list m_scalar_type; memory_space_t m_space_spec; diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc index 09844ae..a3e43aa 100644 --- a/src/cuda-sim/ptx_sim.cc +++ b/src/cuda-sim/ptx_sim.cc @@ -128,6 +128,26 @@ unsigned ptx_cta_info::get_sm_idx() const return m_sm_idx; } +ptx_warp_info::ptx_warp_info() +{ + reset_done_threads(); +} + +unsigned ptx_warp_info::get_done_threads() const +{ + return m_done_threads; +} + +void ptx_warp_info::inc_done_threads() +{ + m_done_threads++; +} + +void ptx_warp_info::reset_done_threads() +{ + m_done_threads = 0; +} + unsigned g_ptx_thread_info_uid_next=1; unsigned g_ptx_thread_info_delete_count=0; @@ -153,6 +173,7 @@ ptx_thread_info::ptx_thread_info( kernel_info_t &kernel ) m_last_memory_space = undefined_space; m_branch_taken = 0; m_shared_mem = NULL; + m_warp_info = NULL; m_cta_info = NULL; m_local_mem = NULL; m_symbol_table = NULL; diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index f926e6d..449511f 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -167,6 +167,17 @@ private: std::set m_dangling_pointers; }; +class ptx_warp_info { +public: + ptx_warp_info(); + unsigned get_done_threads() const; + void inc_done_threads(); + void reset_done_threads(); + +private: + unsigned m_done_threads; +}; + class symbol; struct stack_entry { @@ -425,6 +436,7 @@ public: dram_callback_t m_last_dram_callback; memory_space *m_shared_mem; memory_space *m_local_mem; + ptx_warp_info *m_warp_info; ptx_cta_info *m_cta_info; ptx_reg_t m_last_set_operand_value; -- cgit v1.3 From bffac032402b35acb81200540f6f808bd6f851d8 Mon Sep 17 00:00:00 2001 From: sspenst Date: Wed, 24 Aug 2016 15:30:16 -0700 Subject: Cleanup --- src/cuda-sim/cuda-sim.cc | 2 +- src/cuda-sim/instructions.cc | 8 -------- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 8bf4ec8..d3c928d 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1498,7 +1498,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel, ptx_warp_info *warp_info = NULL; if ( ptx_warp_lookup.find(hw_warp_id) == ptx_warp_lookup.end() ) { - warp_info = new ptx_warp_info(); // num_threads should be threads in the warp + warp_info = new ptx_warp_info(); ptx_warp_lookup[hw_warp_id] = warp_info; } else { warp_info = ptx_warp_lookup[hw_warp_id]; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 05ba78f..4c9392b 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3567,14 +3567,6 @@ void shfl_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) if (!p) src_idx = lane; // copy input from lane src_idx ptx_reg_t data; - /*if (inst.active(src_idx) && i_type == PRED_TYPE) { - ptx_thread_info *source = core->get_thread_info()[tid + src_idx]; - data = source->get_operand_value(src1, dst, i_type, source, 1); - data.pred = p; - } else { - printf("GPGPU-Sim PTX: WARNING: shfl input value unpredictable for inactive/predicated-off threads in a warp\n"); - data.u32 = 0; - }*/ if (inst.active(src_idx)) { ptx_thread_info *source = core->get_thread_info()[tid + src_idx]; data = source->get_operand_value(src1, dst, i_type, source, 1); -- cgit v1.3 From 6a88a8fb947f6256dcf5dd9f315834f12322ad38 Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 25 Aug 2016 15:54:38 -0700 Subject: Fixed minor shfl bugs --- src/cuda-sim/instructions.cc | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 4c9392b..78d6450 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3534,13 +3534,14 @@ void shfl_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) int bval = (thread->get_operand_value(src2, dst, i_type, thread, 1)).u32; int cval = (thread->get_operand_value(src3, dst, i_type, thread, 1)).u32; int mask = cval >> 8; + bval &= 0x1F; cval &= 0x1F; int maxLane = (lane & mask) | (cval & ~mask); int minLane = lane & mask; int src_idx; - int p; + unsigned p; switch(pI->shfl_op()) { case UP_OPTION: src_idx = lane - bval; @@ -3559,23 +3560,32 @@ void shfl_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) p = (src_idx <= maxLane); break; default: - printf("GPGPU-Sim PTX: ERROR: Unrecognized shfl option\n"); + printf("GPGPU-Sim PTX: ERROR: Invalid shfl option\n"); assert(0); break; } // copy from own lane if (!p) src_idx = lane; + // copy input from lane src_idx + ptx_thread_info *source = core->get_thread_info()[tid + src_idx]; ptx_reg_t data; if (inst.active(src_idx)) { - ptx_thread_info *source = core->get_thread_info()[tid + src_idx]; data = source->get_operand_value(src1, dst, i_type, source, 1); - } - if (i_type == PRED_TYPE) { - data.pred = p; + } else { + printf("GPGPU-Sim PTX: WARNING: shfl input value unpredictable for inactive threads in a warp\n"); + data.u32 = 0; } thread->set_operand_value(dst, data, i_type, thread, pI); + /* + TODO: deal with predicates appropriately using the following pseudocode: + if (!isGuardPredicateTrue(src_idx)) { + printf("GPGPU-Sim PTX: WARNING: shfl input value unpredictable for predicated-off threads in a warp\n"); + } + if (dest predicate selected) data.pred = p; + */ + // keep track of the number of threads that have executed in the warp warp_info->inc_done_threads(); if (warp_info->get_done_threads() == inst.active_count()) { -- cgit v1.3 From 0afe825c212560c3b473366d005a50c2568cad1a Mon Sep 17 00:00:00 2001 From: sspenst Date: Thu, 25 Aug 2016 15:56:02 -0700 Subject: OCD --- src/cuda-sim/instructions.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 78d6450..26d6285 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -3568,9 +3568,9 @@ void shfl_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) if (!p) src_idx = lane; // copy input from lane src_idx - ptx_thread_info *source = core->get_thread_info()[tid + src_idx]; ptx_reg_t data; if (inst.active(src_idx)) { + ptx_thread_info *source = core->get_thread_info()[tid + src_idx]; data = source->get_operand_value(src1, dst, i_type, source, 1); } else { printf("GPGPU-Sim PTX: WARNING: shfl input value unpredictable for inactive threads in a warp\n"); -- cgit v1.3 From 623a88e5d5c6c3edb94404ef6e5ea100caec9deb Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Mon, 29 Aug 2016 18:10:00 -0700 Subject: MOD: Add macros to turn off cuda_device_runtime for CUDA < 5.0 --- src/cuda-sim/cuda-sim.cc | 2 ++ src/cuda-sim/cuda_device_runtime.cc | 10 +++++++--- src/cuda-sim/cuda_device_runtime.h | 3 ++- src/cuda-sim/instructions.cc | 2 ++ src/gpgpu-sim/gpu-sim.cc | 2 ++ src/gpgpu-sim/shader.cc | 2 +- 6 files changed, 16 insertions(+), 5 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 3f5af7e..ec51779 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1792,7 +1792,9 @@ void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL ) ); cta.execute(); +#if (CUDART_VERSION >= 5000) launch_all_device_kernels(); +#endif } //registering this kernel as done diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc index 12c83d2..4a8ffe5 100644 --- a/src/cuda-sim/cuda_device_runtime.cc +++ b/src/cuda-sim/cuda_device_runtime.cc @@ -1,9 +1,15 @@ //Jin: cuda_device_runtime.cc //Defines CUDA device runtime APIs for CDP support + #include #include +unsigned long long g_total_param_size = 0; +unsigned long long g_max_total_param_size = 0; + + +#if (CUDART_VERSION >= 5000) #define __CUDA_RUNTIME_API_H__ #include @@ -59,8 +65,6 @@ public: std::map g_cuda_device_launch_param_map; std::list g_cuda_device_launch_op; extern stream_manager *g_stream_manager; -unsigned long long g_total_param_size = 0; -unsigned long long g_max_total_param_size = 0; //Handling device runtime api: //void * cudaGetParameterBufferV2(void *func, dim3 gridDimension, dim3 blockDimension, unsigned int sharedMemSize) @@ -313,4 +317,4 @@ void launch_all_device_kernels() { launch_one_device_kernel(); } } - +#endif diff --git a/src/cuda-sim/cuda_device_runtime.h b/src/cuda-sim/cuda_device_runtime.h index 385d605..6dbcd71 100644 --- a/src/cuda-sim/cuda_device_runtime.h +++ b/src/cuda-sim/cuda_device_runtime.h @@ -1,6 +1,6 @@ //Jin: cuda_device_runtime.h //Defines CUDA device runtime APIs for CDP support - +#if (CUDART_VERSION >= 5000) #pragma once void gpgpusim_cuda_getParameterBufferV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func); @@ -8,3 +8,4 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * void gpgpusim_cuda_streamCreateWithFlags(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func); void launch_all_device_kernels(); void launch_one_device_kernel(); +#endif diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 5d909d3..e68f9fd 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1414,6 +1414,7 @@ void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) return; } +#if (CUDART_VERSION >= 5000) //Jin: handle device runtime apis for CDP else if(fname == "cudaGetParameterBufferV2") { gpgpusim_cuda_getParameterBufferV2(pI, thread, target_func); @@ -1427,6 +1428,7 @@ void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) gpgpusim_cuda_streamCreateWithFlags(pI, thread, target_func); return; } +#endif // read source arguements into register specified in declaration of function arg_buffer_list_t arg_values; diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 0b4b2f6..363fe5a 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1513,8 +1513,10 @@ void gpgpu_sim::cycle() try_snap_shot(gpu_sim_cycle); spill_log_to_file (stdout, 0, gpu_sim_cycle); +#if (CUDART_VERSION >= 5000) //launch device kernel launch_one_device_kernel(); +#endif } } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index b9caf18..59a2d8b 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -846,7 +846,7 @@ void scheduler_unit::cycle() while( !warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue) ) { const warp_inst_t *pI = warp(warp_id).ibuffer_next_inst(); //Jin: handle cdp latency; - if(pI->m_is_cdp && warp(warp_id).m_cdp_latency > 0) { + if(pI && pI->m_is_cdp && warp(warp_id).m_cdp_latency > 0) { assert(warp(warp_id).m_cdp_dummy); warp(warp_id).m_cdp_latency--; break; -- cgit v1.3 From ad4b448e846b1cd3ac244f02fc1e21ab37eaec55 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Tue, 30 Aug 2016 20:30:17 -0700 Subject: BUG: concurrent kernel on the same SMX does not work with non-legacy local memory mapping, turn off by default --- src/gpgpu-sim/gpu-sim.cc | 114 ++++++++++++++++++++++++++++------------------- src/gpgpu-sim/shader.cc | 4 +- 2 files changed, 72 insertions(+), 46 deletions(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 363fe5a..58a5d16 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -369,8 +369,8 @@ void shader_core_config::reg_options(class OptionParser * opp) "gto"); option_parser_register(opp, "-gpgpu_concurrent_kernel_sm", OPT_BOOL, &gpgpu_concurrent_kernel_sm, - "Support concurrent kernels on a SM (default = enabled)", - "1"); + "Support concurrent kernels on a SM (default = disabled)", + "0"); } void gpgpu_sim_config::reg_options(option_parser_t opp) @@ -1102,13 +1102,18 @@ void shader_core_ctx::mem_instruction_stats(const warp_inst_t &inst) abort(); } } -//Jin: concurrent kernels on one SM bool shader_core_ctx::can_issue_1block(kernel_info_t & kernel) { - - if(m_config->max_cta(kernel) < 1) - return false; - return occupy_shader_resource_1block(kernel, false); + //Jin: concurrent kernels on one SM + if(m_config->gpgpu_concurrent_kernel_sm) { + if(m_config->max_cta(kernel) < 1) + return false; + + return occupy_shader_resource_1block(kernel, false); + } + else { + return (get_n_active_cta() < m_config->max_cta(kernel)); + } } int shader_core_ctx::find_available_hwtid(unsigned int cta_size, bool occupy) { @@ -1178,34 +1183,37 @@ bool shader_core_ctx::occupy_shader_resource_1block(kernel_info_t & k, bool occu } void shader_core_ctx::release_shader_resource_1block(unsigned hw_ctaid, kernel_info_t & k) { - unsigned threads_per_cta = k.threads_per_cta(); - const class function_info *kernel = k.entry(); - unsigned int padded_cta_size = threads_per_cta; - unsigned int warp_size = m_config->warp_size; - if (padded_cta_size%warp_size) - padded_cta_size = ((padded_cta_size/warp_size)+1)*(warp_size); - - assert(m_occupied_n_threads >= padded_cta_size); - m_occupied_n_threads -= padded_cta_size; - - int start_thread = m_occupied_cta_to_hwtid[hw_ctaid]; - - for(unsigned hwtid = start_thread; hwtid < start_thread + padded_cta_size; - hwtid++) - m_occupied_hwtid.reset(hwtid); - m_occupied_cta_to_hwtid.erase(hw_ctaid); - - const struct gpgpu_ptx_sim_info *kernel_info = ptx_sim_kernel_info(kernel); - - assert(m_occupied_shmem >= (unsigned int)kernel_info->smem); - m_occupied_shmem -= kernel_info->smem; - unsigned int used_regs = padded_cta_size * ((kernel_info->regs+3)&~3); - assert(m_occupied_regs >= used_regs); - m_occupied_regs -= used_regs; - - assert(m_occupied_ctas >= 1); - m_occupied_ctas--; + if(m_config->gpgpu_concurrent_kernel_sm) { + unsigned threads_per_cta = k.threads_per_cta(); + const class function_info *kernel = k.entry(); + unsigned int padded_cta_size = threads_per_cta; + unsigned int warp_size = m_config->warp_size; + if (padded_cta_size%warp_size) + padded_cta_size = ((padded_cta_size/warp_size)+1)*(warp_size); + + assert(m_occupied_n_threads >= padded_cta_size); + m_occupied_n_threads -= padded_cta_size; + + int start_thread = m_occupied_cta_to_hwtid[hw_ctaid]; + + for(unsigned hwtid = start_thread; hwtid < start_thread + padded_cta_size; + hwtid++) + m_occupied_hwtid.reset(hwtid); + m_occupied_cta_to_hwtid.erase(hw_ctaid); + + const struct gpgpu_ptx_sim_info *kernel_info = ptx_sim_kernel_info(kernel); + + assert(m_occupied_shmem >= (unsigned int)kernel_info->smem); + m_occupied_shmem -= kernel_info->smem; + + unsigned int used_regs = padded_cta_size * ((kernel_info->regs+3)&~3); + assert(m_occupied_regs >= used_regs); + m_occupied_regs -= used_regs; + + assert(m_occupied_ctas >= 1); + m_occupied_ctas--; + } } //////////////////////////////////////////////////////////////////////////////////////////////// @@ -1219,14 +1227,23 @@ void shader_core_ctx::release_shader_resource_1block(unsigned hw_ctaid, kernel_i void shader_core_ctx::issue_block2core( kernel_info_t &kernel ) { -// set_max_cta(kernel); + + if(!m_config->gpgpu_concurrent_kernel_sm) + set_max_cta(kernel); + else + assert(occupy_shader_resource_1block(kernel, true)); + kernel.inc_running(); - assert(occupy_shader_resource_1block(kernel, true)); // find a free CTA context unsigned free_cta_hw_id=(unsigned)-1; -// for (unsigned i=0;imax_cta_per_core;i++ ) { + + unsigned max_cta_per_core; + if(!m_config->gpgpu_concurrent_kernel_sm) + max_cta_per_core = kernel_max_cta_per_shader; + else + max_cta_per_core = m_config->max_cta_per_core; + for (unsigned i=0;iwarp_size) padded_cta_size = ((cta_size/m_config->warp_size)+1)*(m_config->warp_size); - unsigned int start_thread = find_available_hwtid(padded_cta_size, true); - assert((int)start_thread != -1); - unsigned int end_thread = start_thread + cta_size; - assert(m_occupied_cta_to_hwtid.find(free_cta_hw_id) == m_occupied_cta_to_hwtid.end()); - m_occupied_cta_to_hwtid[free_cta_hw_id]= start_thread; -// unsigned start_thread = free_cta_hw_id * padded_cta_size; -// unsigned end_thread = start_thread + cta_size; + + unsigned int start_thread, end_thread; + + if(!m_config->gpgpu_concurrent_kernel_sm) { + start_thread = free_cta_hw_id * padded_cta_size; + end_thread = start_thread + cta_size; + } + else { + start_thread = find_available_hwtid(padded_cta_size, true); + assert((int)start_thread != -1); + end_thread = start_thread + cta_size; + assert(m_occupied_cta_to_hwtid.find(free_cta_hw_id) == m_occupied_cta_to_hwtid.end()); + m_occupied_cta_to_hwtid[free_cta_hw_id]= start_thread; + } // reset the microarchitecture state of the selected hardware thread and warp contexts reinit(start_thread, end_thread,false); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 59a2d8b..d17e51d 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1978,7 +1978,9 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num, kernel_info_t fflush(stdout); //Shader can only be empty when no more cta are dispatched - assert(m_kernel == NULL || !m_gpu->kernel_more_cta_left(m_kernel)); + if(kernel != m_kernel) { + assert(m_kernel == NULL || !m_gpu->kernel_more_cta_left(m_kernel)); + } m_kernel = NULL; } -- cgit v1.3 From 0421e45d3f8796bc9bf1ff3b62c05173f7862463 Mon Sep 17 00:00:00 2001 From: Jin Wang Date: Mon, 5 Sep 2016 18:09:12 -0400 Subject: MOD: modify Makefile to make CUDART_VERSION available to gpu-sim.cc --- src/gpgpu-sim/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gpgpu-sim/Makefile b/src/gpgpu-sim/Makefile index bead38a..f10a8a4 100644 --- a/src/gpgpu-sim/Makefile +++ b/src/gpgpu-sim/Makefile @@ -59,6 +59,7 @@ ifneq ($(GPGPUSIM_POWER_MODEL),) endif OPTFLAGS += -g3 -fPIC +OPTFLAGS += -DCUDART_VERSION=$(CUDART_VERSION) CPP = g++ $(SNOW) OEXT = o -- cgit v1.3 From 96d528311239d6ff82d7bec807a2509b344c9a60 Mon Sep 17 00:00:00 2001 From: gpgpu-sim Date: Sat, 10 Sep 2016 11:44:16 -0400 Subject: Paper to cite for CDP support --- README | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/README b/README index 4883e93..4eb0651 100644 --- a/README +++ b/README @@ -24,6 +24,12 @@ Tor M. Aamodt, Vijay Janapa Reddi, GPUWattch: Enabling Energy Optimizations in GPGPUs, In proceedings of the ACM/IEEE International Symposium on Computer Architecture (ISCA 2013), Tel-Aviv, Israel, June 23-27, 2013. +If you use the support for CUDA dynamic parallelism in your research, please cite: + +Jin Wang and Sudhakar Yalamanchili, Characterization and Analysis of Dynamic +Parallelism in Unstructured GPU Applications, 2014 IEEE International Symposium +on Workload Characterization (IISWC), November 2014. + If you use figures plotted using AerialVision in your publications, please cite: Aaron Ariel, Wilson W. L. Fung, Andrew Turner, Tor M. Aamodt, Visualizing -- cgit v1.3 From 7b7f9050424f21a6da17f6765add0c6cd244b2a3 Mon Sep 17 00:00:00 2001 From: Ahmed ElTantawy Date: Fri, 28 Oct 2016 10:49:19 -0700 Subject: support for CUDA 8.0 PTX --- Makefile | 2 ++ libcuda/cuda_runtime_api.cc | 7 ++++++- setup_environment | 2 +- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 9e2c576..3b6e40d 100644 --- a/Makefile +++ b/Makefile @@ -156,6 +156,8 @@ $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib if [ ! -f $(SIM_LIB_DIR)/libcudart.so.5.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.5.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.6.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.6.0; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.7.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.7.5; fi + if [ ! -f $(SIM_LIB_DIR)/libcudart.so.8.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.8.0; fi + $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib g++ -dynamiclib -Wl,-headerpad_max_install_names,-undefined,dynamic_lookup,-compatibility_version,1.1,-current_version,1.1\ $(SIM_OBJ_FILES_DIR)/libcuda/*.o \ diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 910bebd..75a2f31 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -125,7 +125,9 @@ #include "host_defines.h" #include "builtin_types.h" #include "driver_types.h" +#if (CUDART_VERSION < 8000) #include "__cudaFatFormat.h" +#endif #include "../src/gpgpu-sim/gpu-sim.h" #include "../src/cuda-sim/ptx_loader.h" #include "../src/cuda-sim/cuda-sim.h" @@ -1667,7 +1669,9 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) cuobjdumpRegisterFatBinary(fat_cubin_handle, filename); return (void**)fat_cubin_handle; - } else { + } + #if (CUDART_VERSION < 8000) + else { static unsigned source_num=1; unsigned long long fat_cubin_handle = next_fat_bin_handle++; __cudaFatCudaBinary *info = (__cudaFatCudaBinary *)fatCubin; @@ -1724,6 +1728,7 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) } return (void**)fat_cubin_handle; } + #endif } void __cudaUnregisterFatBinary(void **fatCubinHandle) diff --git a/setup_environment b/setup_environment index 2684514..854a335 100644 --- a/setup_environment +++ b/setup_environment @@ -43,7 +43,7 @@ CC_VERSION=`gcc --version | head -1 | awk '{for(i=1;i<=NF;i++){ if(match($i,/^[0 CUDA_VERSION_STRING=`$CUDA_INSTALL_PATH/bin/nvcc --version | awk '/release/ {print $5;}' | sed 's/,//'`; CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("%02u%02u", 10*int($1), 10*$2);}'` -if [ $CUDA_VERSION_NUMBER -gt 7500 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then +if [ $CUDA_VERSION_NUMBER -gt 8000 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then echo "ERROR ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; return elif [ $CUDA_VERSION_NUMBER -gt 4020 ]; then -- cgit v1.3 From 54529f8b3556427526fd416118c444ce0eb10a21 Mon Sep 17 00:00:00 2001 From: Ahmed ElTantawy Date: Mon, 31 Oct 2016 12:54:29 -0700 Subject: update opencl_runtime similar to cuda_runtime --- libopencl/opencl_runtime_api.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libopencl/opencl_runtime_api.cc b/libopencl/opencl_runtime_api.cc index 020384f..63f7c81 100644 --- a/libopencl/opencl_runtime_api.cc +++ b/libopencl/opencl_runtime_api.cc @@ -74,7 +74,9 @@ #define __CUDA_RUNTIME_API_H__ #include "host_defines.h" #include "builtin_types.h" +#if (CUDART_VERSION < 8000) #include "__cudaFatFormat.h" +#endif #include "../src/abstract_hardware_model.h" #include "../src/cuda-sim/cuda-sim.h" #include "../src/cuda-sim/ptx_loader.h" -- cgit v1.3 From 7fe0d9214ba42be543862d8e40849d38f9b818bb Mon Sep 17 00:00:00 2001 From: Tim Rogers Date: Tue, 9 May 2017 14:00:19 -0400 Subject: Updating for Travis --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 18fcd7a..2ffdb12 100644 --- a/.travis.yml +++ b/.travis.yml @@ -6,6 +6,6 @@ before_install: - sudo apt-get install -y cuda - sudo apt-get install -y build-essential xutils-dev bison zlib1g-dev flex libglu1-mesa-dev env: - - CUDA_INSTALL_PATH=/usr/local/cuda-7.5/ + - CUDA_INSTALL_PATH=/usr/local/cuda-8.0/ language: cpp script: source ./setup_environment && make -- cgit v1.3 From a0de8a0a75f3640e10a27cb91822a11089f22b99 Mon Sep 17 00:00:00 2001 From: Mengchi Zhang Date: Tue, 9 May 2017 16:52:24 -0400 Subject: Fix next block addr to link predicate ret block to consecutive block The block containing predicate ret instruction should add the consecutive block to its successor_ids set. next_addr should be assigned with current instruction address add instruction size instead of 1. Signed-off-by: Mengchi Zhang --- src/cuda-sim/ptx_ir.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 1805ce9..8ebdcf8 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -498,7 +498,7 @@ void function_info::connect_basic_blocks( ) //iterate across m_basic_blocks of f if( pI->has_pred() ) { printf("GPGPU-Sim PTX: Warning detected predicated return/exit.\n"); // if predicated, add link to next block - unsigned next_addr = pI->get_m_instr_mem_index() + 1; + unsigned next_addr = pI->get_m_instr_mem_index() + pI->inst_size(); if( next_addr < m_instr_mem_size && m_instr_mem[next_addr] ) { basic_block_t *next_bb = m_instr_mem[next_addr]->get_bb(); (*bb_itr)->successor_ids.insert(next_bb->bb_id); -- cgit v1.3 From 196703487e33ec383dab2a0cededb2289e342083 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 16 May 2017 13:37:29 -0400 Subject: Changing the version detection to be much more detailed. Now the git commit # and branch will be embedded in the built executable and print out when gpgpu-sim runs --- src/cuda-sim/Makefile | 2 +- src/cuda-sim/cuda-sim.cc | 5 ++--- version | 1 - version_detection.mk | 9 +++++++-- 4 files changed, 10 insertions(+), 7 deletions(-) diff --git a/src/cuda-sim/Makefile b/src/cuda-sim/Makefile index f479294..5132bcc 100644 --- a/src/cuda-sim/Makefile +++ b/src/cuda-sim/Makefile @@ -46,7 +46,7 @@ OPT := -O3 -g3 -Wall -Wno-unused-function -Wno-sign-compare ifeq ($(DEBUG),1) OPT := -g3 -Wall -Wno-unused-function -Wno-sign-compare endif -OPT += -I$(CUDA_INSTALL_PATH)/include -I$(OUTPUT_DIR)/ -I. +OPT += -I$(CUDA_INSTALL_PATH)/include -I$(OUTPUT_DIR)/ -I. -I$(SIM_OBJ_FILES_DIR) OPT += -fPIC ifeq ($(TRACE),1) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 7ec3ce9..d4ace76 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1623,14 +1623,13 @@ kernel_info_t *gpgpu_opencl_ptx_sim_init_grid(class function_info *entry, } #include "../../version" +#include "detailed_version" void print_splash() { static int splash_printed=0; if ( !splash_printed ) { - unsigned build=0; - sscanf(g_gpgpusim_build_string, "$Change"": %u $", &build); - fprintf(stdout, "\n\n *** %s [build %u] ***\n\n\n", g_gpgpusim_version_string, build ); + fprintf(stdout, "\n\n *** %s [build %s] ***\n\n\n", g_gpgpusim_version_string, g_gpgpusim_build_string ); splash_printed=1; } } diff --git a/version b/version index e565a98..c70c6ac 100644 --- a/version +++ b/version @@ -1,2 +1 @@ const char *g_gpgpusim_version_string = "GPGPU-Sim Simulator Version 3.2.2 "; -const char *g_gpgpusim_build_string = "$Change$"; diff --git a/version_detection.mk b/version_detection.mk index 8796d5c..00a8b1f 100644 --- a/version_detection.mk +++ b/version_detection.mk @@ -30,7 +30,13 @@ ifeq ($(GPGPUSIM_ROOT),) else GPGPUSIM_VERSION=$(shell cat $(GPGPUSIM_ROOT)/version | awk '/Version/ {print $$8}' ) -GPGPUSIM_BUILD=$(shell cat $(GPGPUSIM_ROOT)/version | awk '/Change/ {print $$6}' ) + +#Detect Git branch and commit # +GIT_BRANCH := $(shell git branch | grep "\*" | sed -re 's/\*\s+(.*)/\1/') +GIT_COMMIT := $(shell git log -n 1 | head -1 | sed -re 's/commit (.*)/\1/') +GIT_FILES_CHANGED := $(shell git diff --numstat --cached && git diff --numstat | wc | sed -re 's/^\s+([0-9]+).*/\1/') +GPGPUSIM_BUILD := "gpgpu-sim_$(GIT_BRANCH)_$(GIT_COMMIT)_modified_$(GIT_FILES_CHANGED)" +$(shell mkdir -p $(SIM_OBJ_FILES_DIR)/libcuda && echo "const char *g_gpgpusim_build_string=\"$(GPGPUSIM_BUILD)\";" > $(SIM_OBJ_FILES_DIR)/detailed_version) endif # Detect CUDA Runtime Version @@ -42,4 +48,3 @@ CC_VERSION := $(shell gcc --version | head -1 | awk '{for(i=1;i<=NF;i++){ if(mat # Detect Support for C++11 (C++0x) from GCC Version GNUC_CPP0X := $(shell gcc --version | perl -ne 'if (/gcc\s+\(.*\)\s+([0-9.]+)/){ if($$1 >= 4.3) {$$n=1} else {$$n=0;} } END { print $$n; }') - -- cgit v1.3 From 8b44f564221b9a0503ca04ccdb463bd60ae8c33c Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 16 May 2017 16:56:54 -0400 Subject: Fixing a bug with where the build version is made. Moveing it after the right directories ect are defined --- Makefile | 3 +++ version_detection.mk | 1 - 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 78ef892..7a7b187 100644 --- a/Makefile +++ b/Makefile @@ -54,6 +54,9 @@ ifneq ($(shell which nvcc), "") endif endif + +$(shell mkdir -p $(SIM_OBJ_FILES_DIR)/libcuda && echo "const char *g_gpgpusim_build_string=\"$(GPGPUSIM_BUILD)\";" > $(SIM_OBJ_FILES_DIR)/detailed_version) + LIBS = cuda-sim gpgpu-sim_uarch $(INTERSIM) gpgpusimlib diff --git a/version_detection.mk b/version_detection.mk index 00a8b1f..f9c333f 100644 --- a/version_detection.mk +++ b/version_detection.mk @@ -36,7 +36,6 @@ GIT_BRANCH := $(shell git branch | grep "\*" | sed -re 's/\*\s+(.*)/\1/') GIT_COMMIT := $(shell git log -n 1 | head -1 | sed -re 's/commit (.*)/\1/') GIT_FILES_CHANGED := $(shell git diff --numstat --cached && git diff --numstat | wc | sed -re 's/^\s+([0-9]+).*/\1/') GPGPUSIM_BUILD := "gpgpu-sim_$(GIT_BRANCH)_$(GIT_COMMIT)_modified_$(GIT_FILES_CHANGED)" -$(shell mkdir -p $(SIM_OBJ_FILES_DIR)/libcuda && echo "const char *g_gpgpusim_build_string=\"$(GPGPUSIM_BUILD)\";" > $(SIM_OBJ_FILES_DIR)/detailed_version) endif # Detect CUDA Runtime Version -- cgit v1.3 From 1e7f2f0d857666ee7edd7bd0d6b0e52a6588522e Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 16 May 2017 23:03:47 -0400 Subject: Getting rid of the branch since it gets weird, espeically in travis --- version_detection.mk | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/version_detection.mk b/version_detection.mk index f9c333f..00a86c0 100644 --- a/version_detection.mk +++ b/version_detection.mk @@ -32,10 +32,9 @@ else GPGPUSIM_VERSION=$(shell cat $(GPGPUSIM_ROOT)/version | awk '/Version/ {print $$8}' ) #Detect Git branch and commit # -GIT_BRANCH := $(shell git branch | grep "\*" | sed -re 's/\*\s+(.*)/\1/') GIT_COMMIT := $(shell git log -n 1 | head -1 | sed -re 's/commit (.*)/\1/') GIT_FILES_CHANGED := $(shell git diff --numstat --cached && git diff --numstat | wc | sed -re 's/^\s+([0-9]+).*/\1/') -GPGPUSIM_BUILD := "gpgpu-sim_$(GIT_BRANCH)_$(GIT_COMMIT)_modified_$(GIT_FILES_CHANGED)" +GPGPUSIM_BUILD := "gpgpu-sim_git-commit-$(GIT_COMMIT)_modified_$(GIT_FILES_CHANGED)" endif # Detect CUDA Runtime Version -- cgit v1.3 From 959808f483a43dc2371f04e18c34fcebb0425b48 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 17 May 2017 10:15:48 -0400 Subject: Adding in the embedded .so bit --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 7a7b187..e83de9a 100644 --- a/Makefile +++ b/Makefile @@ -143,7 +143,7 @@ no_opencl_support: @echo "Warning: gpgpu-sim is building without opencl support. Make sure NVOPENCL_LIBDIR and NVOPENCL_INCDIR are set" $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib - g++ -shared -Wl,-soname,libcudart.so \ + g++ -shared -Wl,-soname,libcudart_$(GPGPUSIM_BUILD).so \ $(SIM_OBJ_FILES_DIR)/libcuda/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/decuda_pred_table/*.o \ @@ -174,7 +174,7 @@ $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib -o $(SIM_LIB_DIR)/libcudart.dylib $(SIM_LIB_DIR)/libOpenCL.so: makedirs $(LIBS) opencllib - g++ -shared -Wl,-soname,libOpenCL.so \ + g++ -shared -Wl,-soname,libOpenCL_$(GPGPUSIM_BUILD).so \ $(SIM_OBJ_FILES_DIR)/libopencl/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/decuda_pred_table/*.o \ -- cgit v1.3 From f17b0d38c7654bf3a83e0bd93fcf87c6ab233b6b Mon Sep 17 00:00:00 2001 From: tgrogers Date: Thu, 6 Jul 2017 00:40:01 -0400 Subject: Adding the correct dependency for the detailed_version file. In order to updatet the built number output when we run gpgpu-sim we need to recompile cuda-sim everytime the detailed_version has changed --- src/cuda-sim/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cuda-sim/Makefile b/src/cuda-sim/Makefile index 5132bcc..999dad7 100644 --- a/src/cuda-sim/Makefile +++ b/src/cuda-sim/Makefile @@ -142,7 +142,7 @@ $(OUTPUT_DIR)/ptx_parser.o: $(OUTPUT_DIR)/ptx.tab.c $(OUTPUT_DIR)/ptx_parser_dec $(OUTPUT_DIR)/ptxinfo.tab.o: $(OUTPUT_DIR)/ptx.tab.c $(OUTPUT_DIR)/ptx-stats.o: $(OUTPUT_DIR)/ptx.tab.c $(OUTPUT_DIR)/ptx_sim.o: $(OUTPUT_DIR)/ptx.tab.c -$(OUTPUT_DIR)/cuda-sim.o: $(OUTPUT_DIR)/ptx.tab.c +$(OUTPUT_DIR)/cuda-sim.o: $(OUTPUT_DIR)/ptx.tab.c $(SIM_OBJ_FILES_DIR)/detailed_version $(OUTPUT_DIR)/lex.ptxinfo_.o: $(OUTPUT_DIR)/ptx.tab.c $(OUTPUT_DIR)/lex.ptx_.o: $(OUTPUT_DIR)/ptx.tab.c $(OUTPUT_DIR)/cuda_device_runtime.o: $(OUTPUT_DIR)/ptx.tab.c -- cgit v1.3 From 7f770a887b9a5f1bb0098230098765227ed4bbb2 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 8 Jul 2017 23:53:35 -0400 Subject: Adding in a test to see what happens when travis tries to build with docker. --- .travis.yml | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/.travis.yml b/.travis.yml index 2ffdb12..2c8b942 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,11 +1,10 @@ -dist: trusty +sudo: required + +services: + - docker + before_install: - - wget http://developer.download.nvidia.com/compute/cuda/repos/ubuntu1404/x86_64/cuda-repo-ubuntu1404_7.5-18_amd64.deb - - sudo dpkg -i cuda-repo-ubuntu1404_7.5-18_amd64.deb - - sudo apt-get -qq update - - sudo apt-get install -y cuda - - sudo apt-get install -y build-essential xutils-dev bison zlib1g-dev flex libglu1-mesa-dev -env: - - CUDA_INSTALL_PATH=/usr/local/cuda-8.0/ + - docker pull tgrogers/gpgpu-sim_regress + language: cpp -script: source ./setup_environment && make +script: ls && pwd && ls / -- cgit v1.3 From 54f463b872460ea729544d9c33ce28693498fa8f Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 00:05:20 -0400 Subject: Commit to wake travis up? --- .travis.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis.yml b/.travis.yml index 2c8b942..e635dcb 100644 --- a/.travis.yml +++ b/.travis.yml @@ -6,5 +6,6 @@ services: before_install: - docker pull tgrogers/gpgpu-sim_regress + language: cpp script: ls && pwd && ls / -- cgit v1.3 From 7b281b27317c372684ff9080a5ca9af962f25531 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 00:14:50 -0400 Subject: Adding in some mroe stuff to debug travis --- .travis.yml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/.travis.yml b/.travis.yml index e635dcb..c7282bd 100644 --- a/.travis.yml +++ b/.travis.yml @@ -5,7 +5,9 @@ services: before_install: - docker pull tgrogers/gpgpu-sim_regress - + - docker run tgrogers/gpgpu-sim_regress /bin/bash -c "pwd; ls" language: cpp -script: ls && pwd && ls / + +script: + ls && pwd && ls / -- cgit v1.3 From 7e0b657d86770c8226186c2d3f2d6c79595c1b84 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 00:18:00 -0400 Subject: What is going on? --- .travis.yml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/.travis.yml b/.travis.yml index c7282bd..78b10b2 100644 --- a/.travis.yml +++ b/.travis.yml @@ -3,9 +3,10 @@ sudo: required services: - docker -before_install: - - docker pull tgrogers/gpgpu-sim_regress - - docker run tgrogers/gpgpu-sim_regress /bin/bash -c "pwd; ls" +before_install: + ls +# - docker pull tgrogers/gpgpu-sim_regress +# - docker run tgrogers/gpgpu-sim_regress /bin/bash -c "pwd; ls" language: cpp -- cgit v1.3 From e04d36bb2555fd063182de6e3cc8b0742ec6b996 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 00:21:51 -0400 Subject: wrong docker tag --- .travis.yml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/.travis.yml b/.travis.yml index 78b10b2..34147e4 100644 --- a/.travis.yml +++ b/.travis.yml @@ -4,9 +4,8 @@ services: - docker before_install: - ls -# - docker pull tgrogers/gpgpu-sim_regress -# - docker run tgrogers/gpgpu-sim_regress /bin/bash -c "pwd; ls" + - docker pull tgrogers/gpgpu-sim_regress:firsttry + - docker run tgrogers/gpgpu-sim_regress /bin/bash -c "pwd; ls" language: cpp -- cgit v1.3 From b3e2060b8e69dcdc6e923857261296ae51eec3c4 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 00:26:48 -0400 Subject: wrong docker tag --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 34147e4..33dc82e 100644 --- a/.travis.yml +++ b/.travis.yml @@ -5,7 +5,7 @@ services: before_install: - docker pull tgrogers/gpgpu-sim_regress:firsttry - - docker run tgrogers/gpgpu-sim_regress /bin/bash -c "pwd; ls" + - docker run tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "pwd; ls" language: cpp -- cgit v1.3 From 53ab60f7864d976b492f6f9d082373cf715c6e63 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 00:40:24 -0400 Subject: Adding in the first pass at the actual regression commands --- .travis.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/.travis.yml b/.travis.yml index 33dc82e..a9f992d 100644 --- a/.travis.yml +++ b/.travis.yml @@ -5,9 +5,8 @@ services: before_install: - docker pull tgrogers/gpgpu-sim_regress:firsttry - - docker run tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "pwd; ls" language: cpp script: - ls && pwd && ls / + - docker run -v .:/home/runner/gpgpu-sim_distribution tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; su - runner; cd gpgpu-sim_distribution; source setup_environment; make -j; cd ../gpgpu-sim_simulations/util/job_launching; ./run_simulations -N regress; ./monitor_fucn_test.py -N regress" -- cgit v1.3 From f37488e37cfa3ea75b3a91a33e740c9c5c06d97a Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 00:45:34 -0400 Subject: trying pwd --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index a9f992d..570337f 100644 --- a/.travis.yml +++ b/.travis.yml @@ -9,4 +9,4 @@ before_install: language: cpp script: - - docker run -v .:/home/runner/gpgpu-sim_distribution tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; su - runner; cd gpgpu-sim_distribution; source setup_environment; make -j; cd ../gpgpu-sim_simulations/util/job_launching; ./run_simulations -N regress; ./monitor_fucn_test.py -N regress" + - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; su - runner; cd gpgpu-sim_distribution; source setup_environment; make -j; cd ../gpgpu-sim_simulations/util/job_launching; ./run_simulations -N regress; ./monitor_fucn_test.py -N regress" -- cgit v1.3 From fa0af93b6a7f45a46d66944e33519cac0e1549cf Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 01:19:25 -0400 Subject: Magic line --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 570337f..7689880 100644 --- a/.travis.yml +++ b/.travis.yml @@ -9,4 +9,4 @@ before_install: language: cpp script: - - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; su - runner; cd gpgpu-sim_distribution; source setup_environment; make -j; cd ../gpgpu-sim_simulations/util/job_launching; ./run_simulations -N regress; ./monitor_fucn_test.py -N regress" + - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -N regress'" -- cgit v1.3 From f75c725f9ea358a203f3a9726f62acc237d31be9 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 01:30:47 -0400 Subject: specify rw for the mapped directory --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 7689880..0ad2c8f 100644 --- a/.travis.yml +++ b/.travis.yml @@ -9,4 +9,4 @@ before_install: language: cpp script: - - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -N regress'" + - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -N regress'" -- cgit v1.3 From cd226998437ed95c9dbf15df33356aec1528a084 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 01:50:22 -0400 Subject: giving runner permissions to the distributions directory --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 0ad2c8f..f4f4712 100644 --- a/.travis.yml +++ b/.travis.yml @@ -9,4 +9,4 @@ before_install: language: cpp script: - - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -N regress'" + - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -N regress'" -- cgit v1.3 From 26680b9e80967d17cec7b1434e7e64deb7d2aff0 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 02:26:59 -0400 Subject: Call the monitor in verbose mode? --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index f4f4712..b4b1c62 100644 --- a/.travis.yml +++ b/.travis.yml @@ -9,4 +9,4 @@ before_install: language: cpp script: - - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -N regress'" + - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" -- cgit v1.3 From d7087c3ebf839a9a3d78f89ed56cd83046834b41 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 02:50:47 -0400 Subject: trying out parallel builds --- .travis.yml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/.travis.yml b/.travis.yml index b4b1c62..4fe2fce 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,5 +8,11 @@ before_install: language: cpp -script: - - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" +jobs: + include: + - stage: GTX480 + script: + docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" + - + script: + docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" -- cgit v1.3 From fbb85eacd1ac806cc3e2d97e612d7aa7253ea8a0 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 02:53:42 -0400 Subject: again with the parallel --- .travis.yml | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/.travis.yml b/.travis.yml index 4fe2fce..c92f845 100644 --- a/.travis.yml +++ b/.travis.yml @@ -10,9 +10,8 @@ language: cpp jobs: include: - - stage: GTX480 - script: + - stage: Parallel-regressions + - script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" - - - script: + - script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" -- cgit v1.3 From 748a5b0a4a2a709c05ba597d69b4fee137b716aa Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 02:57:31 -0400 Subject: What works, sort of... --- .travis.yml | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/.travis.yml b/.travis.yml index c92f845..13dddb6 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,10 +8,5 @@ before_install: language: cpp -jobs: - include: - - stage: Parallel-regressions - - script: - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" - - script: +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" -- cgit v1.3 From b94d3a5beab0e9a2ceca3af8c0820819a315555e Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 10:31:12 -0400 Subject: A test for what is wrong with torque --- .travis.yml | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/.travis.yml b/.travis.yml index 13dddb6..656ab40 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,5 +8,13 @@ before_install: language: cpp -script: - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; \ + chown -R runner /home/runner/gpgpu-sim_distribution; \ + su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment \ + && make -j -C /home/runner/gpgpu-sim_distribution \ + && cd /home/runner/gpgpu-sim_simulations/ \ + && git pull \ + && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress \ + && while [ 0 -lt 1 ] cat `ls /var/spool/torque/server_logs/` && ps -aux | grep -i pbs && lscpu done'" + +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" -- cgit v1.3 From a48c829bc6171079d1860e89cfbc5afa4d9372f5 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 10:54:21 -0400 Subject: new debugging commandline --- .travis.yml | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/.travis.yml b/.travis.yml index 656ab40..49f8660 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,13 +8,4 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; \ - chown -R runner /home/runner/gpgpu-sim_distribution; \ - su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment \ - && make -j -C /home/runner/gpgpu-sim_distribution \ - && cd /home/runner/gpgpu-sim_simulations/ \ - && git pull \ - && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress \ - && while [ 0 -lt 1 ] cat `ls /var/spool/torque/server_logs/` && ps -aux | grep -i pbs && lscpu done'" - -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From 42b8dbc3e2d602e32d27d6640025fd195ddbfa13 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 11:31:56 -0400 Subject: Debugging non-running mom --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 49f8660..f906cfe 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,4 +8,4 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; ps -aux | grep -i pbs; done'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From d14e714107ed0f5d2444bb56b71441d12dd86cb2 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 11:44:55 -0400 Subject: Adding another check for the pbs_mom --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index f906cfe..f2a4aa4 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,4 +8,4 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; ps -aux | grep -i pbs; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From b80d1b148e9b8abf559f9448ec6a4bae2922e2e7 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 12:05:24 -0400 Subject: again, try to restart --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index f2a4aa4..6be2268 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,4 +8,4 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; ps -aux | grep -i pbs; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; ps -aux | grep -i pbs; chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From 092b8b4bf35f8cb739ac3b87eb291a264b075d30 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 14:16:56 -0400 Subject: increasing mom lovel to see why it is continously failing --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 6be2268..f83ed8a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,4 +8,4 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "./start_torque.sh; ps -aux | grep -i pbs; chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From 985de25068ed722e4d20580b95f1b6d034b19fbd Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 14:30:19 -0400 Subject: Adding an extra slash for the loglevel --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index f83ed8a..8731265 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,4 +8,4 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From 8ecd03733b890559ac86395bc332c9400e035e68 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 14:34:09 -0400 Subject: Adding another slash for the logvel 0 this time maybe... --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 8731265..9ec7017 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,4 +8,4 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From 9ca55c4871597e12a161bedb607308c28ed434e2 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Sun, 9 Jul 2017 22:53:28 -0400 Subject: Fixing backgroup index bug --- src/gpgpu-sim/gpu-sim.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index a2d1b9b..7d92c66 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -195,7 +195,7 @@ struct memory_config { for (i=0; nbkt>0; i++) { nbkt = nbkt>>1; } - bk_tag_length = i; + bk_tag_length = i-1; assert(nbkgrp>0 && "Number of bank groups cannot be zero"); tRCDWR = tRCD-(WL+1); tRTW = (CL+(BL/data_command_freq_ratio)+2-WL); -- cgit v1.3 From 745b65579bb13e1005bae89b0cdea11c96c670bc Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 23:07:27 -0400 Subject: lookimg at messages --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 9ec7017..148bb75 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,4 +8,4 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; cat /var/log/messages ;chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From 0860cd6580d281a580952e9d486eec7b98bf324d Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 9 Jul 2017 23:43:30 -0400 Subject: is it hosts? --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 148bb75..e847a2b 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,4 +8,4 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; cat /var/log/messages ;chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; cat /etc/hosts ;chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From bdf410b45f44f31a405f9aa8397a14aa1e459da7 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 10 Jul 2017 09:55:52 -0400 Subject: Let's test mom by lunching it over and over --- .travis.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index e847a2b..61de53d 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,4 +8,5 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; cat /etc/hosts ;chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; while true; do /etc/init.d/torque-mom restart; ps -aux | grep -i pbs; sleep 5s ; ps -aux | grep -i pbs; cat /var/spool/torque/mom_logs/\`ls -tr /var/spool/torque/mom_logs | tail -1\` ;done" +#script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; cat /etc/hosts ;chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From 01cbaf4b9186ba24ae116ccd58429ee90bf8aefc Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 10 Jul 2017 16:52:29 -0400 Subject: More info in logs? --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 61de53d..4fd5321 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,5 +8,5 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; while true; do /etc/init.d/torque-mom restart; ps -aux | grep -i pbs; sleep 5s ; ps -aux | grep -i pbs; cat /var/spool/torque/mom_logs/\`ls -tr /var/spool/torque/mom_logs | tail -1\` ;done" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; while true; do /etc/init.d/torque-mom restart; ps -aux | grep -i pbs; sleep 5s ; ps -aux | grep -i pbs; cat /var/spool/torque/mom_logs/\`ls -tr /var/spool/torque/mom_logs | tail -1\` ;cat /var/log/\`ls -rt /var/log | tail -1\` ;done" #script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; cat /etc/hosts ;chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From bba836f5c98cb6aa89a951bc82829f85ed3884b9 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 10 Jul 2017 17:47:21 -0400 Subject: another test of pbs_mom --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 4fd5321..ac878bc 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,5 +8,5 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; while true; do /etc/init.d/torque-mom restart; ps -aux | grep -i pbs; sleep 5s ; ps -aux | grep -i pbs; cat /var/spool/torque/mom_logs/\`ls -tr /var/spool/torque/mom_logs | tail -1\` ;cat /var/log/\`ls -rt /var/log | tail -1\` ;done" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; while true; do /usr/sbin/pbs_mom ;ps -aux | grep -i pbs; sleep 5s ; ps -aux | grep -i pbs; cat /var/spool/torque/mom_logs/\`ls -tr /var/spool/torque/mom_logs | tail -1\`;done" #script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; cat /etc/hosts ;chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From a262269ea4b1322a19af80cc1be557da5cd0169e Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 10 Jul 2017 18:08:21 -0400 Subject: a short in the dark... --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index ac878bc..97ee0e8 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,5 +8,5 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; while true; do /usr/sbin/pbs_mom ;ps -aux | grep -i pbs; sleep 5s ; ps -aux | grep -i pbs; cat /var/spool/torque/mom_logs/\`ls -tr /var/spool/torque/mom_logs | tail -1\`;done" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"pbs_server = 127.0.0.1\" > /var/spool/torque/mom_priv/config && echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; while true; do /usr/sbin/pbs_mom ;ps -aux | grep -i pbs; sleep 5s ; ps -aux | grep -i pbs; cat /var/spool/torque/mom_logs/\`ls -tr /var/spool/torque/mom_logs | tail -1\`;done" #script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; cat /etc/hosts ;chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From 441bc18259620c03a6f1267d5be949b5eeba3c3e Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 10 Jul 2017 22:32:18 -0400 Subject: After diggin in the torque source code, it looks like it might be this posix memlock stuff that is killing the travis install. I guess it is possible that the server disables this feature on whatever infrastructure they are using. I am trying to rebuild pbs_mom without the memlock and see how much further we get. --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 97ee0e8..dc1ed92 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,5 +8,5 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"pbs_server = 127.0.0.1\" > /var/spool/torque/mom_priv/config && echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; while true; do /usr/sbin/pbs_mom ;ps -aux | grep -i pbs; sleep 5s ; ps -aux | grep -i pbs; cat /var/spool/torque/mom_logs/\`ls -tr /var/spool/torque/mom_logs | tail -1\`;done" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "wget http://archive.ubuntu.com/ubuntu/pool/universe/t/torque/torque_2.4.16+dfsg.orig.tar.gz && tar xzvf torque_2.4.16+dfsg.orig.tar.gz && cd torque-2.4.16/ && ./configure --disable-posixmemlock && make && cp ./src/resmom/.libs/pbs_mom /usr/sbin/ echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && while true; do cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done" #script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; cat /etc/hosts ;chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From 9722a8ce2a3254821104156bfef6308abefdfaea Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 10 Jul 2017 22:46:39 -0400 Subject: new build got us past that fail - now lets see if it can stay up... --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index dc1ed92..1ee71ca 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,5 +8,5 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "wget http://archive.ubuntu.com/ubuntu/pool/universe/t/torque/torque_2.4.16+dfsg.orig.tar.gz && tar xzvf torque_2.4.16+dfsg.orig.tar.gz && cd torque-2.4.16/ && ./configure --disable-posixmemlock && make && cp ./src/resmom/.libs/pbs_mom /usr/sbin/ echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && while true; do cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "wget http://archive.ubuntu.com/ubuntu/pool/universe/t/torque/torque_2.4.16+dfsg.orig.tar.gz && tar xzvf torque_2.4.16+dfsg.orig.tar.gz && cd torque-2.4.16/ && ./configure --disable-posixmemlock && make && cp ./src/resmom/.libs/pbs_mom /usr/sbin/ && echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; while true; do cat /var/spool/torque/mom_logs/\`ls -rt /var/spool/torque/mom_logs | tail -1\`; ps -aux | grep -i pbs; done" #script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; cat /etc/hosts ;chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From 70f358a5946dcf3c05d245f5a9ea48c42dd2823b Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 10 Jul 2017 22:56:13 -0400 Subject: forgot to change dirs --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 1ee71ca..dc1a4f4 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,5 +8,5 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "wget http://archive.ubuntu.com/ubuntu/pool/universe/t/torque/torque_2.4.16+dfsg.orig.tar.gz && tar xzvf torque_2.4.16+dfsg.orig.tar.gz && cd torque-2.4.16/ && ./configure --disable-posixmemlock && make && cp ./src/resmom/.libs/pbs_mom /usr/sbin/ && echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; while true; do cat /var/spool/torque/mom_logs/\`ls -rt /var/spool/torque/mom_logs | tail -1\`; ps -aux | grep -i pbs; done" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "wget http://archive.ubuntu.com/ubuntu/pool/universe/t/torque/torque_2.4.16+dfsg.orig.tar.gz && tar xzvf torque_2.4.16+dfsg.orig.tar.gz && cd torque-2.4.16/ && ./configure --disable-posixmemlock && make && cp ./src/resmom/.libs/pbs_mom /usr/sbin/ && echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; cd /gpgpu-sim/ && ./start_torque.sh; ps -aux | grep -i pbs; while true; do cat /var/spool/torque/mom_logs/\`ls -rt /var/spool/torque/mom_logs | tail -1\`; ps -aux | grep -i pbs; done" #script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; cat /etc/hosts ;chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -- cgit v1.3 From 6f995f6312bef87bf7310d475ff1eb92d58e0b23 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 10 Jul 2017 23:08:02 -0400 Subject: Now that mom stays up, lets try this again... --- .travis.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index dc1a4f4..254ff4e 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,5 +8,6 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "wget http://archive.ubuntu.com/ubuntu/pool/universe/t/torque/torque_2.4.16+dfsg.orig.tar.gz && tar xzvf torque_2.4.16+dfsg.orig.tar.gz && cd torque-2.4.16/ && ./configure --disable-posixmemlock && make && cp ./src/resmom/.libs/pbs_mom /usr/sbin/ && echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; cd /gpgpu-sim/ && ./start_torque.sh; ps -aux | grep -i pbs; while true; do cat /var/spool/torque/mom_logs/\`ls -rt /var/spool/torque/mom_logs | tail -1\`; ps -aux | grep -i pbs; done" +#script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "wget http://archive.ubuntu.com/ubuntu/pool/universe/t/torque/torque_2.4.16+dfsg.orig.tar.gz && tar xzvf torque_2.4.16+dfsg.orig.tar.gz && cd torque-2.4.16/ && ./configure --disable-posixmemlock && make && cp ./src/resmom/.libs/pbs_mom /usr/sbin/ && echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; cd /gpgpu-sim/ && ./start_torque.sh; ps -aux | grep -i pbs; while true; do cat /var/spool/torque/mom_logs/\`ls -rt /var/spool/torque/mom_logs | tail -1\`; ps -aux | grep -i pbs; done" #script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; cat /etc/hosts ;chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "wget http://archive.ubuntu.com/ubuntu/pool/universe/t/torque/torque_2.4.16+dfsg.orig.tar.gz && tar xzvf torque_2.4.16+dfsg.orig.tar.gz && cd torque-2.4.16/ && ./configure --disable-posixmemlock && make && cp ./src/resmom/.libs/pbs_mom /usr/sbin/; cd /gpgpu-sim/ && ./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -N regress'" -- cgit v1.3 From a3307c29871f46342b0cd59eab375f2af24d9a37 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 10 Jul 2017 23:30:54 -0400 Subject: pointing a the latest version of the docker image that already has the new pbs_mom built in it. --- .travis.yml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/.travis.yml b/.travis.yml index 254ff4e..b919ba6 100644 --- a/.travis.yml +++ b/.travis.yml @@ -4,10 +4,8 @@ services: - docker before_install: - - docker pull tgrogers/gpgpu-sim_regress:firsttry + - docker pull tgrogers/gpgpu-sim_regress:latest language: cpp -#script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "wget http://archive.ubuntu.com/ubuntu/pool/universe/t/torque/torque_2.4.16+dfsg.orig.tar.gz && tar xzvf torque_2.4.16+dfsg.orig.tar.gz && cd torque-2.4.16/ && ./configure --disable-posixmemlock && make && cp ./src/resmom/.libs/pbs_mom /usr/sbin/ && echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; cd /gpgpu-sim/ && ./start_torque.sh; ps -aux | grep -i pbs; while true; do cat /var/spool/torque/mom_logs/\`ls -rt /var/spool/torque/mom_logs | tail -1\`; ps -aux | grep -i pbs; done" -#script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "echo \"\\\$loglevel 7\" >> /var/spool/torque/mom_priv/config; ./start_torque.sh; ps -aux | grep -i pbs; cat /etc/hosts ;chown -R runner /home/runner/gpgpu-sim_distribution; echo \"mom_2\" && /etc/init.d/torque-mom restart && ps -aux | grep -i pbs && su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && while true; do lscpu; cat /var/spool/torque/server_logs/\`ls /var/spool/torque/server_logs\`; echo \"mom_logs\"; cat /var/spool/torque/mom_logs/\`ls /var/spool/torque/mom_logs\`; ps -aux | grep -i pbs; done'" -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:firsttry /bin/bash -c "wget http://archive.ubuntu.com/ubuntu/pool/universe/t/torque/torque_2.4.16+dfsg.orig.tar.gz && tar xzvf torque_2.4.16+dfsg.orig.tar.gz && cd torque-2.4.16/ && ./configure --disable-posixmemlock && make && cp ./src/resmom/.libs/pbs_mom /usr/sbin/; cd /gpgpu-sim/ && ./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -N regress'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" -- cgit v1.3 From 0616aff48a53613fc0cc774a0cbcd7f597ae61ad Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 10 Jul 2017 23:59:50 -0400 Subject: Attempting to parallelize the build across all the configs at once --- .travis.yml | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index b919ba6..0682625 100644 --- a/.travis.yml +++ b/.travis.yml @@ -8,4 +8,12 @@ before_install: language: cpp -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" +matrix: + include: + - env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.gtx480.yml + - env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.gtx750ti.yml + - env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.quadro5600.yml + - env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.quadro5800.yml + - env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.teslac2050.yml + +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c $CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" -- cgit v1.3 From 1a440b7b2b155636b33009591e086ec16c712470 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 11 Jul 2017 00:05:37 -0400 Subject: looks like i need to explicitly include docker?? --- .travis.yml | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/.travis.yml b/.travis.yml index 0682625..a0d0bb6 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,8 +1,5 @@ sudo: required -services: - - docker - before_install: - docker pull tgrogers/gpgpu-sim_regress:latest @@ -10,10 +7,15 @@ language: cpp matrix: include: - - env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.gtx480.yml - - env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.gtx750ti.yml - - env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.quadro5600.yml - - env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.quadro5800.yml - - env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.teslac2050.yml + - services: docker + env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.gtx480.yml + - services: docker + env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.gtx750ti.yml + - services: docker + env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.quadro5600.yml + - services: docker + env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.quadro5800.yml + - services: docker + env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.teslac2050.yml script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c $CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" -- cgit v1.3 From a3041c986c1673a00871bede67d5002e2ac26203 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 11 Jul 2017 00:10:59 -0400 Subject: trvis tick? --- .travis.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.travis.yml b/.travis.yml index a0d0bb6..24ccb95 100644 --- a/.travis.yml +++ b/.travis.yml @@ -5,6 +5,7 @@ before_install: language: cpp + matrix: include: - services: docker -- cgit v1.3 From 700db957a1135c13131083c53966c40e82925cff Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 11 Jul 2017 00:47:57 -0400 Subject: reducing the reundant text in the config defintions --- .travis.yml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/.travis.yml b/.travis.yml index 24ccb95..dfedae7 100644 --- a/.travis.yml +++ b/.travis.yml @@ -9,14 +9,14 @@ language: cpp matrix: include: - services: docker - env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.gtx480.yml + env: CONFIG=configs.gtx480.yml - services: docker - env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.gtx750ti.yml + env: CONFIG=configs.gtx750ti.yml - services: docker - env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.quadro5600.yml + env: CONFIG=configs.quadro5600.yml - services: docker - env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.quadro5800.yml + env: CONFIG=configs.quadro5800.yml - services: docker - env: CONFIG=/home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.teslac2050.yml + env: CONFIG=configs.teslac2050.yml -script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c $CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" +script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" -- cgit v1.3 From a227a35814e4feb6cfa23a9c32acf94d020087c0 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 11 Jul 2017 14:57:54 -0400 Subject: Disbaling the maxwell config --- .travis.yml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/.travis.yml b/.travis.yml index dfedae7..fabfc5b 100644 --- a/.travis.yml +++ b/.travis.yml @@ -10,8 +10,9 @@ matrix: include: - services: docker env: CONFIG=configs.gtx480.yml - - services: docker - env: CONFIG=configs.gtx750ti.yml +# This config is just taking far too long... +# - services: docker +# env: CONFIG=configs.gtx750ti.yml - services: docker env: CONFIG=configs.quadro5600.yml - services: docker -- cgit v1.3 From 9f60e00962127ded3b52d970d11073f24c894705 Mon Sep 17 00:00:00 2001 From: gpgpu-sim Date: Tue, 11 Jul 2017 15:20:59 -0700 Subject: Update CHANGES added mention of a couple of recent changes --- CHANGES | 2 ++ 1 file changed, 2 insertions(+) diff --git a/CHANGES b/CHANGES index e3b3177..dbf5b39 100644 --- a/CHANGES +++ b/CHANGES @@ -1,5 +1,7 @@ LOG: Version 3.2.3+edits (development branch) versus 3.2.3 +- Support for running regression tests using Travis +- Support added for CUDA dynamic parallelism (courtesy of Jin Wang from Georgia Tech) - Added a parameter to the cache configuration to configure the set index function. Added a hash set index function to the Fermi L1 data cache for the two default cache sizes, 16KB/48KB with 32/64 sets. -- cgit v1.3 From be451de4abf4fac2ea4b8bd2a79c6037ac635990 Mon Sep 17 00:00:00 2001 From: gpgpu-sim Date: Tue, 11 Jul 2017 15:23:17 -0700 Subject: Update README updating description of CUDA versions --- README | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/README b/README index 4eb0651..6e2d734 100644 --- a/README +++ b/README @@ -5,7 +5,8 @@ AerialVision and a configurable and extensible energy model called GPUWattch. GPGPU-Sim and GPUWattch have been rigorously validated with performance and power measurements of real hardware GPUs. -This version of GPGPU-Sim has been tested with CUDA version 2.3, 3.1 and 4.0. +This version of GPGPU-Sim has been tested with CUDA version 2.3, 3.1, 4.0, +5.0, 5.5, 6.0 and 7.5. Please see the copyright notice in the file COPYRIGHT distributed with this release in the same directory as this file. -- cgit v1.3 From e9736f3b054062744c4bb81d38b7402944eb5480 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 12 Jul 2017 15:14:48 -0400 Subject: Adding in the jenkinsfile that can be used for automatic regression on Purdue's end --- Jenkinsfile | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 Jenkinsfile diff --git a/Jenkinsfile b/Jenkinsfile new file mode 100644 index 0000000..86ca78f --- /dev/null +++ b/Jenkinsfile @@ -0,0 +1,13 @@ +pipeline { + agent { + label "purdue-cluster" + } + + stages { + stage('4.2-regress') { + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh && source `pwd`/setup_environment && make -j && git clone https://github.com/tgrogers/gpgpu-sim_simulations.git && cd gpgpu-sim_simulations && git checkout purdue-cluster && make -j -C ./benchmarks/src all && ./util/job_launching/run_simulations.py -N regress &&./util/job_launching/monitor_func_test.py -v -N regress' + } + } + } +} -- cgit v1.3 From a3120435ca0e2d51bc06278ee242e9fb850b7076 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 12 Jul 2017 15:29:16 -0400 Subject: Fixing BankGroup Indexing Bug --- src/gpgpu-sim/gpu-sim.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index a2d1b9b..7d92c66 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -195,7 +195,7 @@ struct memory_config { for (i=0; nbkt>0; i++) { nbkt = nbkt>>1; } - bk_tag_length = i; + bk_tag_length = i-1; assert(nbkgrp>0 && "Number of bank groups cannot be zero"); tRCDWR = tRCD-(WL+1); tRTW = (CL+(BL/data_command_freq_ratio)+2-WL); -- cgit v1.3 From f8e84eefc92d7d63554472e0bb88fe691f40701d Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 12 Jul 2017 17:03:30 -0400 Subject: Getting jenkins to work by changing the error on shell type to a warning. The way we detect the shell is not fool-proof and fails for jenkins, although we are using bash --- setup_environment | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup_environment b/setup_environment index 854a335..0895d44 100644 --- a/setup_environment +++ b/setup_environment @@ -1,6 +1,6 @@ # see README before running this -ps -p $$ | awk '/bash/ || / sh/ || /zsh/ {exit 1;}' && echo "ERROR ** source setup_environment must be run in a bash, zsh or sh shell; see README" && exit +ps -p $$ | awk '/bash/ || / sh/ || /zsh/ {exit 1;}' && echo "WARNING ** source setup_environment must be run in a bash, zsh or sh shell; see README" export GPGPUSIM_SETUP_ENVIRONMENT_WAS_RUN= export GPGPUSIM_ROOT="$( cd "$( dirname "$BASH_SOURCE" )" && pwd )" -- cgit v1.3 From 2f231086c67432cd4d9aabb2261e4f3515763851 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 12 Jul 2017 17:45:00 -0400 Subject: Removing the simulations directory before we sync --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 86ca78f..6063245 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -6,7 +6,7 @@ pipeline { stages { stage('4.2-regress') { steps { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh && source `pwd`/setup_environment && make -j && git clone https://github.com/tgrogers/gpgpu-sim_simulations.git && cd gpgpu-sim_simulations && git checkout purdue-cluster && make -j -C ./benchmarks/src all && ./util/job_launching/run_simulations.py -N regress &&./util/job_launching/monitor_func_test.py -v -N regress' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh && source `pwd`/setup_environment && make -j && rm -rf gpgpu-sim_simulations && git clone https://github.com/tgrogers/gpgpu-sim_simulations.git && cd gpgpu-sim_simulations && git checkout purdue-cluster && make -j -C ./benchmarks/src all && ./util/job_launching/run_simulations.py -N regress &&./util/job_launching/monitor_func_test.py -v -N regress' } } } -- cgit v1.3 From dcf7e6a8445a5d8e4383add44ca6f5d0d198ab02 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 17 Jul 2017 22:32:30 -0400 Subject: Improving GPU core model. This commits contains: 1- round robin inst issue for warp multiple schedulers 2- add sector mask in the memory request (to bused later for L2 sector cache) 3- Adding Fermi coalescer 4- Ensure different exen units are used in dual_issue mode 5- Report how many dual_issue happened 6- Adding oldest_first scheduler --- src/abstract_hardware_model.cc | 54 +++++++++++++++++++++++-------- src/abstract_hardware_model.h | 18 ++++++++--- src/gpgpu-sim/gpu-cache.cc | 3 +- src/gpgpu-sim/gpu-sim.cc | 20 +++++++++--- src/gpgpu-sim/gpu-sim.h | 2 ++ src/gpgpu-sim/mem_fetch.h | 1 + src/gpgpu-sim/shader.cc | 73 +++++++++++++++++++++++++++++++++++++----- src/gpgpu-sim/shader.h | 36 +++++++++++++++++++-- 8 files changed, 173 insertions(+), 34 deletions(-) diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index fe6f8ab..f75c525 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -314,12 +314,12 @@ void warp_inst_t::generate_mem_accesses() break; case global_space: case local_space: case param_space_local: - if( m_config->gpgpu_coalesce_arch == 13 ) { - if(isatomic()) - memory_coalescing_arch_13_atomic(is_write, access_type); - else - memory_coalescing_arch_13(is_write, access_type); - } else abort(); + if( m_config->gpgpu_coalesce_arch == 13 || m_config->gpgpu_coalesce_arch == 20) { + if(isatomic()) + memory_coalescing_arch_atomic(is_write, access_type); + else + memory_coalescing_arch(is_write, access_type); + } else abort(); break; @@ -343,7 +343,7 @@ void warp_inst_t::generate_mem_accesses() byte_mask.set(idx+i); } for( a=accesses.begin(); a != accesses.end(); ++a ) - m_accessq.push_back( mem_access_t(access_type,a->first,cache_block_size,is_write,a->second,byte_mask) ); + m_accessq.push_back( mem_access_t(access_type,a->first,cache_block_size,is_write,a->second, byte_mask, mem_access_sector_mask_t())); } if ( space.get_type() == global_space ) { @@ -352,11 +352,37 @@ void warp_inst_t::generate_mem_accesses() m_mem_accesses_created=true; } -void warp_inst_t::memory_coalescing_arch_13( bool is_write, mem_access_type access_type ) +void warp_inst_t::memory_coalescing_arch( bool is_write, mem_access_type access_type ) { // see the CUDA manual where it discusses coalescing rules before reading this unsigned segment_size = 0; - unsigned warp_parts = m_config->mem_warp_parts; + unsigned warp_parts; + + //TO DO: need to double check how double number are coalesced! + if(data_size == 1) + { + //If it is byte data, then coalesce on the whole 32 threads, regardless the arch version + warp_parts = 1; + } + else if(m_config->gpgpu_coalesce_arch == 13) + { + //mem_warp_parts should equal 2 for arch=13 + //we still use the parameter mem_warp_parts for arch=13 to ensure it is backward compatibility with older gpgpu config files + warp_parts = m_config->mem_warp_parts; + } + else if(m_config->gpgpu_coalesce_arch == 20) + { + //It is expected that L1_warp_parts_non_cached = 4 and L1_warp_parts_cached = 1 for arch=20 + //non cached, coalesce on 8 threads to generate 32 bytes accesses + //cached, coalesce on 32 threads to generate 128 bytes accesses + if(m_config->gmem_skip_L1D || cache_op == CACHE_GLOBAL) + warp_parts = m_config->L1_warp_parts_non_cached; + else + warp_parts = m_config->L1_warp_parts_cached; + } + else + abort(); + switch( data_size ) { case 1: segment_size = 32; break; case 2: segment_size = 64; break; @@ -410,13 +436,13 @@ void warp_inst_t::memory_coalescing_arch_13( bool is_write, mem_access_type acce new_addr_type addr = t->first; const transaction_info &info = t->second; - memory_coalescing_arch_13_reduce_and_send(is_write, access_type, info, addr, segment_size); + memory_coalescing_arch_reduce_and_send(is_write, access_type, info, addr, segment_size); } } } -void warp_inst_t::memory_coalescing_arch_13_atomic( bool is_write, mem_access_type access_type ) +void warp_inst_t::memory_coalescing_arch_atomic( bool is_write, mem_access_type access_type ) { assert(space.get_type() == global_space); // Atomics allowed only for global memory @@ -485,13 +511,13 @@ void warp_inst_t::memory_coalescing_arch_13_atomic( bool is_write, mem_access_ty for(t=transaction_list.begin(); t!=transaction_list.end(); t++) { // For each transaction const transaction_info &info = *t; - memory_coalescing_arch_13_reduce_and_send(is_write, access_type, info, addr, segment_size); + memory_coalescing_arch_reduce_and_send(is_write, access_type, info, addr, segment_size); } } } } -void warp_inst_t::memory_coalescing_arch_13_reduce_and_send( bool is_write, mem_access_type access_type, const transaction_info &info, new_addr_type addr, unsigned segment_size ) +void warp_inst_t::memory_coalescing_arch_reduce_and_send( bool is_write, mem_access_type access_type, const transaction_info &info, new_addr_type addr, unsigned segment_size ) { assert( (addr & (segment_size-1)) == 0 ); @@ -540,7 +566,7 @@ void warp_inst_t::memory_coalescing_arch_13_reduce_and_send( bool is_write, mem_ assert(lower_half_used && upper_half_used); } } - m_accessq.push_back( mem_access_t(access_type,addr,size,is_write,info.active,info.bytes) ); + m_accessq.push_back( mem_access_t(access_type,addr,size,is_write,info.active,info.bytes, info.chunks) ); } void warp_inst_t::completed( unsigned long long cycle ) const diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index aaa4b00..cd185a1 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -332,12 +332,15 @@ struct core_config { unsigned gpgpu_shmem_sizeDefault; unsigned gpgpu_shmem_sizePrefL1; unsigned gpgpu_shmem_sizePrefShared; + unsigned L1_warp_parts_cached; + unsigned L1_warp_parts_non_cached; // texture and constant cache line sizes (used to determine number of memory accesses) unsigned gpgpu_cache_texl1_linesize; unsigned gpgpu_cache_constl1_linesize; unsigned gpgpu_max_insn_issue_per_warp; + bool gmem_skip_L1D; // on = global memory access always skip the L1 cache }; // bounded stack that implements simt reconvergence using pdom mechanism from MICRO'07 paper @@ -615,6 +618,8 @@ private: const unsigned MAX_MEMORY_ACCESS_SIZE = 128; typedef std::bitset mem_access_byte_mask_t; +const unsigned SECTOR_CHUNCK_SIZE = 4; +typedef std::bitset mem_access_sector_mask_t; #define NO_PARTIAL_WRITE (mem_access_byte_mask_t()) #define MEM_ACCESS_TYPE_TUP_DEF \ @@ -679,8 +684,9 @@ public: unsigned size, bool wr, const active_mask_t &active_mask, - const mem_access_byte_mask_t &byte_mask ) - : m_warp_mask(active_mask), m_byte_mask(byte_mask) + const mem_access_byte_mask_t &byte_mask, + const mem_access_sector_mask_t §or_mask) + : m_warp_mask(active_mask), m_byte_mask(byte_mask), m_sector_mask(sector_mask) { init(); m_type = type; @@ -696,6 +702,7 @@ public: bool is_write() const { return m_write; } enum mem_access_type get_type() const { return m_type; } mem_access_byte_mask_t get_byte_mask() const { return m_byte_mask; } + mem_access_sector_mask_t get_sector_mask() const { return m_sector_mask; } void print(FILE *fp) const { @@ -729,6 +736,7 @@ private: mem_access_type m_type; active_mask_t m_warp_mask; mem_access_byte_mask_t m_byte_mask; + mem_access_sector_mask_t m_sector_mask; static unsigned sm_next_access_uid; }; @@ -938,9 +946,9 @@ public: }; void generate_mem_accesses(); - void memory_coalescing_arch_13( bool is_write, mem_access_type access_type ); - void memory_coalescing_arch_13_atomic( bool is_write, mem_access_type access_type ); - void memory_coalescing_arch_13_reduce_and_send( bool is_write, mem_access_type access_type, const transaction_info &info, new_addr_type addr, unsigned segment_size ); + void memory_coalescing_arch( bool is_write, mem_access_type access_type ); + void memory_coalescing_arch_atomic( bool is_write, mem_access_type access_type ); + void memory_coalescing_arch_reduce_and_send( bool is_write, mem_access_type access_type, const transaction_info &info, new_addr_type addr, unsigned segment_size ); void add_callback( unsigned lane_id, void (*function)(const class inst_t*, class ptx_thread_info*), diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 5ea4190..cfd0dc8 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -867,7 +867,8 @@ data_cache::wr_miss_wa( new_addr_type addr, mf->get_data_size(), false, // Now performing a read mf->get_access_warp_mask(), - mf->get_access_byte_mask() ); + mf->get_access_byte_mask(), + mf->get_access_sector_mask()); mem_fetch *n_mf = new mem_fetch( *ma, NULL, diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 58a5d16..26432c4 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -285,6 +285,15 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &mem_warp_parts, "Number of portions a warp is divided into for shared memory bank conflict check ", "2"); + option_parser_register(opp, "-gpgpu_L1_warp_parts_cached", OPT_INT32, &L1_warp_parts_cached, + "Number of portions a warp is divided into when the request is cached", + "2"); + option_parser_register(opp, "-gpgpu_L1_warp_parts_cached", OPT_INT32, &L1_warp_parts_non_cached, + "Number of portions a warp is divided into when the request is not cached", + "4"); + option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &mem_warp_parts, + "Number of portions a warp is divided into for shared memory bank conflict check ", + "2"); option_parser_register(opp, "-gpgpu_warpdistro_shader", OPT_INT32, &gpgpu_warpdistro_shader, "Specify which shader core to collect the warp size distribution from", "-1"); @@ -293,7 +302,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "0"); option_parser_register(opp, "-gpgpu_local_mem_map", OPT_BOOL, &gpgpu_local_mem_map, "Mapping from local memory space address to simulated GPU physical address space (default = enabled)", - "1"); + "1"); option_parser_register(opp, "-gpgpu_num_reg_banks", OPT_INT32, &gpgpu_num_reg_banks, "Number of register banks (default = 8)", "8"); @@ -337,14 +346,17 @@ void shader_core_config::reg_options(class OptionParser * opp) "number of collector unit in ports (default = 0)", "0"); option_parser_register(opp, "-gpgpu_coalesce_arch", OPT_INT32, &gpgpu_coalesce_arch, - "Coalescing arch (default = 13, anything else is off for now)", + "Coalescing arch (GT200 = 13, Fermi = 20)", "13"); option_parser_register(opp, "-gpgpu_num_sched_per_core", OPT_INT32, &gpgpu_num_sched_per_core, "Number of warp schedulers per core", "1"); option_parser_register(opp, "-gpgpu_max_insn_issue_per_warp", OPT_INT32, &gpgpu_max_insn_issue_per_warp, - "Max number of instructions that can be issued per warp in one cycle by scheduler", - "2"); + "Max number of instructions that can be issued per warp in one cycle by scheduler (either 1 or 2)", + "2"); + option_parser_register(opp, "-gpgpu_dual_issue_diff_exec_units", OPT_BOOL, &gpgpu_dual_issue_diff_exec_units, + "should dual issue use two different execution unit resources", + "1"); option_parser_register(opp, "-gpgpu_simt_core_sim_order", OPT_INT32, &simt_core_sim_order, "Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)", "1"); diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 7d92c66..23e6144 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -314,6 +314,8 @@ public: unsigned num_shader() const { return m_shader_config.num_shader(); } unsigned num_cluster() const { return m_shader_config.n_simt_clusters; } unsigned get_max_concurrent_kernel() const { return max_concurrent_kernel; } + unsigned get_gpu_max_cycle_opt() const { return gpu_max_cycle_opt; } + unsigned get_gpu_max_insn_opt() const { return gpu_max_insn_opt; } private: void init_clock_domains(void ); diff --git a/src/gpgpu-sim/mem_fetch.h b/src/gpgpu-sim/mem_fetch.h index c89edbb..db4a8e9 100644 --- a/src/gpgpu-sim/mem_fetch.h +++ b/src/gpgpu-sim/mem_fetch.h @@ -104,6 +104,7 @@ public: enum mem_access_type get_access_type() const { return m_access.get_type(); } const active_mask_t& get_access_warp_mask() const { return m_access.get_warp_mask(); } mem_access_byte_mask_t get_access_byte_mask() const { return m_access.get_byte_mask(); } + mem_access_sector_mask_t get_access_sector_mask() const { return m_access.get_sector_mask(); } address_type get_pc() const { return m_inst.empty()?-1:m_inst.pc; } const warp_inst_t &get_inst() { return m_inst; } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index d17e51d..015995e 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -81,6 +81,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_memory_config = mem_config; m_stats = stats; unsigned warp_size=config->warp_size; + Issue_Prio = 0; m_sid = shader_id; m_tpc = tpc_id; @@ -131,6 +132,8 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE : sched_config.find("gto") != std::string::npos ? CONCRETE_SCHEDULER_GTO : + sched_config.find("old") != std::string::npos ? + CONCRETE_SCHEDULER_OLDEST_FIRST : sched_config.find("warp_limiting") != std::string::npos ? CONCRETE_SCHEDULER_WARP_LIMITING: NUM_CONCRETE_SCHEDULERS; @@ -182,6 +185,20 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, ) ); break; + case CONCRETE_SCHEDULER_OLDEST_FIRST: + schedulers.push_back( + new oldest_scheduler( m_stats, + this, + m_scoreboard, + m_simt_stack, + &m_warp, + &m_pipeline_reg[ID_OC_SP], + &m_pipeline_reg[ID_OC_SFU], + &m_pipeline_reg[ID_OC_MEM], + i + ) + ); + break; case CONCRETE_SCHEDULER_WARP_LIMITING: schedulers.push_back( new swl_scheduler( m_stats, @@ -465,6 +482,14 @@ void shader_core_stats::print( FILE* fout ) const for (unsigned i = 3; i < m_config->warp_size + 3; i++) fprintf(fout, "\tW%d:%d", i-2, shader_cycle_distro[i]); fprintf(fout, "\n"); + fprintf(fout, "single_issue_nums:"); + for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; i++) + fprintf(fout, "WS%d:%d\t", i, single_issue_nums[i]); + fprintf(fout, "\n"); + fprintf(fout, "dual_issue_nums:"); + for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; i++) + fprintf(fout, "WS%d:%d\t", i, dual_issue_nums[i]); + fprintf(fout, "\n"); m_outgoing_traffic_stats->print(fout); m_incoming_traffic_stats->print(fout); @@ -724,10 +749,18 @@ void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* } void shader_core_ctx::issue(){ + + unsigned j; + for (unsigned i = 0; i < schedulers.size(); i++) { + j = (Issue_Prio + i) % schedulers.size(); + schedulers[j]->cycle(); + } + Issue_Prio = (Issue_Prio+1)% schedulers.size(); + //really is issue; - for (unsigned i = 0; i < schedulers.size(); i++) { - schedulers[i]->cycle(); - } + //for (unsigned i = 0; i < schedulers.size(); i++) { + // schedulers[i]->cycle(); + //} } shd_warp_t& scheduler_unit::warp(int i){ @@ -842,7 +875,9 @@ void scheduler_unit::cycle() unsigned warp_id = (*iter)->get_warp_id(); unsigned checked=0; unsigned issued=0; - unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp; + exec_unit_type_t previous_issued_inst_exec_type = exec_unit_type_t::NONE; + unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp; + bool diff_exec_units = m_shader->m_config->gpgpu_dual_issue_diff_exec_units; while( !warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue) ) { const warp_inst_t *pI = warp(warp_id).ibuffer_next_inst(); //Jin: handle cdp latency; @@ -875,17 +910,18 @@ void scheduler_unit::cycle() ready_inst = true; const active_mask_t &active_mask = m_simt_stack[warp_id]->get_active_mask(); assert( warp(warp_id).inst_in_pipeline() ); - if ( (pI->op == LOAD_OP) || (pI->op == STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) { + if( m_mem_out->has_free() && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::MEM)) { if( m_mem_out->has_free() ) { m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id); issued++; issued_inst=true; warp_inst_issued = true; + previous_issued_inst_exec_type = exec_unit_type_t::MEM; } } else { bool sp_pipe_avail = m_sp_out->has_free(); bool sfu_pipe_avail = m_sfu_out->has_free(); - if( sp_pipe_avail && (pI->op != SFU_OP) ) { + if( sp_pipe_avail && (pI->op != SFU_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SP)) { //Jin: special for CDP api if(pI->m_is_cdp && !warp(warp_id).m_cdp_dummy) { @@ -910,14 +946,17 @@ void scheduler_unit::cycle() issued++; issued_inst=true; warp_inst_issued = true; - } else if ( (pI->op == SFU_OP) || (pI->op == ALU_SFU_OP) ) { + previous_issued_inst_exec_type = exec_unit_type_t::SP; + } else if ( (pI->op == SFU_OP) || (pI->op == ALU_SFU_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SFU)) { if( sfu_pipe_avail ) { m_shader->issue_warp(*m_sfu_out,pI,active_mask,warp_id); issued++; issued_inst=true; warp_inst_issued = true; + previous_issued_inst_exec_type = exec_unit_type_t::SFU; } - } } + } + } } else { SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) fails scoreboard\n", (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id() ); @@ -952,6 +991,14 @@ void scheduler_unit::cycle() m_last_supervised_issued = supervised_iter; } } + + if(issued == 1) + m_stats->single_issue_nums[m_id]++; + else if(issued > 1) + m_stats->dual_issue_nums[m_id]++; + else + abort(); //issued should be > 0 + break; } } @@ -1009,6 +1056,16 @@ void gto_scheduler::order_warps() scheduler_unit::sort_warps_by_oldest_dynamic_id ); } +void oldest_scheduler::order_warps() +{ + order_by_priority( m_next_cycle_prioritized_warps, + m_supervised_warps, + m_last_supervised_issued, + m_supervised_warps.size(), + ORDERED_PRIORITY_FUNC_ONLY, + scheduler_unit::sort_warps_by_oldest_dynamic_id ); +} + void two_level_active_scheduler::do_on_warp_issued( unsigned warp_id, unsigned num_issued, diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index bdd8dbe..395c1ed 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -70,6 +70,14 @@ #define WRITE_MASK_SIZE 8 +enum exec_unit_type_t +{ + NONE = 0, + SP = 1, + SFU = 2, + MEM = 3, + DP = 4 +}; class thread_ctx_t { public: @@ -308,6 +316,7 @@ enum concrete_scheduler CONCRETE_SCHEDULER_GTO, CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE, CONCRETE_SCHEDULER_WARP_LIMITING, + CONCRETE_SCHEDULER_OLDEST_FIRST, NUM_CONCRETE_SCHEDULERS }; @@ -435,6 +444,23 @@ public: }; +class oldest_scheduler : public scheduler_unit { +public: + oldest_scheduler ( shader_core_stats* stats, shader_core_ctx* shader, + Scoreboard* scoreboard, simt_stack** simt, + std::vector* warp, + register_set* sp_out, + register_set* sfu_out, + register_set* mem_out, + int id ) + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, mem_out, id ){} + virtual ~oldest_scheduler () {} + virtual void order_warps (); + virtual void done_adding_supervised_warps() { + m_last_supervised_issued = m_supervised_warps.begin(); + } + +}; class two_level_active_scheduler : public scheduler_unit { public: @@ -1294,12 +1320,11 @@ struct shader_core_config : public core_config mutable cache_config m_L1C_config; mutable l1d_cache_config m_L1D_config; - bool gmem_skip_L1D; // on = global memory access always skip the L1 cache - bool gpgpu_dwf_reg_bankconflict; int gpgpu_num_sched_per_core; int gpgpu_max_insn_issue_per_warp; + bool gpgpu_dual_issue_diff_exec_units; //op collector int gpgpu_operand_collector_num_units_sp; @@ -1401,6 +1426,8 @@ struct shader_core_stats_pod { unsigned *last_shader_cycle_distro; unsigned *num_warps_issuable; unsigned gpgpu_n_stall_shd_mem; + unsigned* single_issue_nums; + unsigned* dual_issue_nums; //memory access classification int gpgpu_n_mem_read_local; @@ -1469,6 +1496,8 @@ public: m_n_diverge = (unsigned*) calloc(config->num_shader(),sizeof(unsigned)); shader_cycle_distro = (unsigned*) calloc(config->warp_size+3, sizeof(unsigned)); last_shader_cycle_distro = (unsigned*) calloc(m_config->warp_size+3, sizeof(unsigned)); + single_issue_nums = (unsigned*) calloc(config->gpgpu_num_sched_per_core,sizeof(unsigned)); + dual_issue_nums = (unsigned*) calloc(config->gpgpu_num_sched_per_core, sizeof(unsigned)); n_simt_to_mem = (long *)calloc(config->num_shader(), sizeof(long)); n_mem_to_simt = (long *)calloc(config->num_shader(), sizeof(long)); @@ -1830,6 +1859,9 @@ public: //schedule std::vector schedulers; + //issue + unsigned int Issue_Prio; + // execute unsigned m_num_function_units; std::vector m_dispatch_port; -- cgit v1.3 From b806d3a4021a12638e1e67fcd67012dca4b1689e Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 17 Jul 2017 23:20:42 -0400 Subject: Fixing some typos and adding comments --- src/abstract_hardware_model.cc | 14 +++++++------- src/abstract_hardware_model.h | 2 +- src/gpgpu-sim/gpu-cache.cc | 2 +- src/gpgpu-sim/gpu-sim.cc | 12 ++++++------ src/gpgpu-sim/gpu-sim.h | 2 -- src/gpgpu-sim/shader.cc | 43 +++++++++++++++++++++--------------------- src/gpgpu-sim/shader.h | 4 ++-- 7 files changed, 39 insertions(+), 40 deletions(-) diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index f75c525..64eb43c 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -315,11 +315,11 @@ void warp_inst_t::generate_mem_accesses() case global_space: case local_space: case param_space_local: if( m_config->gpgpu_coalesce_arch == 13 || m_config->gpgpu_coalesce_arch == 20) { - if(isatomic()) - memory_coalescing_arch_atomic(is_write, access_type); - else - memory_coalescing_arch(is_write, access_type); - } else abort(); + if(isatomic()) + memory_coalescing_arch_atomic(is_write, access_type); + else + memory_coalescing_arch(is_write, access_type); + } else abort(); break; @@ -358,7 +358,7 @@ void warp_inst_t::memory_coalescing_arch( bool is_write, mem_access_type access_ unsigned segment_size = 0; unsigned warp_parts; - //TO DO: need to double check how double number are coalesced! + //TO DO: need to double check how doubles are coalesced! if(data_size == 1) { //If it is byte data, then coalesce on the whole 32 threads, regardless the arch version @@ -367,7 +367,7 @@ void warp_inst_t::memory_coalescing_arch( bool is_write, mem_access_type access_ else if(m_config->gpgpu_coalesce_arch == 13) { //mem_warp_parts should equal 2 for arch=13 - //we still use the parameter mem_warp_parts for arch=13 to ensure it is backward compatibility with older gpgpu config files + //use the parameter mem_warp_parts for arch=13 to ensure it is backward compatibility with older gpgpu config files warp_parts = m_config->mem_warp_parts; } else if(m_config->gpgpu_coalesce_arch == 20) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index cd185a1..910a9ed 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -685,7 +685,7 @@ public: bool wr, const active_mask_t &active_mask, const mem_access_byte_mask_t &byte_mask, - const mem_access_sector_mask_t §or_mask) + const mem_access_sector_mask_t §or_mask) : m_warp_mask(active_mask), m_byte_mask(byte_mask), m_sector_mask(sector_mask) { init(); diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index cfd0dc8..7af7db0 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -868,7 +868,7 @@ data_cache::wr_miss_wa( new_addr_type addr, false, // Now performing a read mf->get_access_warp_mask(), mf->get_access_byte_mask(), - mf->get_access_sector_mask()); + mf->get_access_sector_mask()); mem_fetch *n_mf = new mem_fetch( *ma, NULL, diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 26432c4..483a7b6 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -302,7 +302,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "0"); option_parser_register(opp, "-gpgpu_local_mem_map", OPT_BOOL, &gpgpu_local_mem_map, "Mapping from local memory space address to simulated GPU physical address space (default = enabled)", - "1"); + "1"); option_parser_register(opp, "-gpgpu_num_reg_banks", OPT_INT32, &gpgpu_num_reg_banks, "Number of register banks (default = 8)", "8"); @@ -346,17 +346,17 @@ void shader_core_config::reg_options(class OptionParser * opp) "number of collector unit in ports (default = 0)", "0"); option_parser_register(opp, "-gpgpu_coalesce_arch", OPT_INT32, &gpgpu_coalesce_arch, - "Coalescing arch (GT200 = 13, Fermi = 20)", + "Coalescing arch (GT200 = 13, Fermi = 20)", "13"); option_parser_register(opp, "-gpgpu_num_sched_per_core", OPT_INT32, &gpgpu_num_sched_per_core, "Number of warp schedulers per core", "1"); option_parser_register(opp, "-gpgpu_max_insn_issue_per_warp", OPT_INT32, &gpgpu_max_insn_issue_per_warp, - "Max number of instructions that can be issued per warp in one cycle by scheduler (either 1 or 2)", - "2"); + "Max number of instructions that can be issued per warp in one cycle by scheduler (either 1 or 2)", + "2"); option_parser_register(opp, "-gpgpu_dual_issue_diff_exec_units", OPT_BOOL, &gpgpu_dual_issue_diff_exec_units, - "should dual issue use two different execution unit resources", - "1"); + "should dual issue use two different execution unit resources", + "1"); option_parser_register(opp, "-gpgpu_simt_core_sim_order", OPT_INT32, &simt_core_sim_order, "Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)", "1"); diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 23e6144..7d92c66 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -314,8 +314,6 @@ public: unsigned num_shader() const { return m_shader_config.num_shader(); } unsigned num_cluster() const { return m_shader_config.n_simt_clusters; } unsigned get_max_concurrent_kernel() const { return max_concurrent_kernel; } - unsigned get_gpu_max_cycle_opt() const { return gpu_max_cycle_opt; } - unsigned get_gpu_max_insn_opt() const { return gpu_max_insn_opt; } private: void init_clock_domains(void ); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 015995e..d826b69 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -132,8 +132,8 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE : sched_config.find("gto") != std::string::npos ? CONCRETE_SCHEDULER_GTO : - sched_config.find("old") != std::string::npos ? - CONCRETE_SCHEDULER_OLDEST_FIRST : + sched_config.find("old") != std::string::npos ? + CONCRETE_SCHEDULER_OLDEST_FIRST : sched_config.find("warp_limiting") != std::string::npos ? CONCRETE_SCHEDULER_WARP_LIMITING: NUM_CONCRETE_SCHEDULERS; @@ -187,16 +187,16 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, break; case CONCRETE_SCHEDULER_OLDEST_FIRST: schedulers.push_back( - new oldest_scheduler( m_stats, - this, - m_scoreboard, - m_simt_stack, - &m_warp, - &m_pipeline_reg[ID_OC_SP], - &m_pipeline_reg[ID_OC_SFU], - &m_pipeline_reg[ID_OC_MEM], - i - ) + new oldest_scheduler( m_stats, + this, + m_scoreboard, + m_simt_stack, + &m_warp, + &m_pipeline_reg[ID_OC_SP], + &m_pipeline_reg[ID_OC_SFU], + &m_pipeline_reg[ID_OC_MEM], + i + ) ); break; case CONCRETE_SCHEDULER_WARP_LIMITING: @@ -750,12 +750,13 @@ void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* void shader_core_ctx::issue(){ - unsigned j; - for (unsigned i = 0; i < schedulers.size(); i++) { - j = (Issue_Prio + i) % schedulers.size(); - schedulers[j]->cycle(); - } - Issue_Prio = (Issue_Prio+1)% schedulers.size(); + //Ensure fair round robin issu between schedulers + unsigned j; + for (unsigned i = 0; i < schedulers.size(); i++) { + j = (Issue_Prio + i) % schedulers.size(); + schedulers[j]->cycle(); + } + Issue_Prio = (Issue_Prio+1)% schedulers.size(); //really is issue; //for (unsigned i = 0; i < schedulers.size(); i++) { @@ -876,8 +877,8 @@ void scheduler_unit::cycle() unsigned checked=0; unsigned issued=0; exec_unit_type_t previous_issued_inst_exec_type = exec_unit_type_t::NONE; - unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp; - bool diff_exec_units = m_shader->m_config->gpgpu_dual_issue_diff_exec_units; + unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp; + bool diff_exec_units = m_shader->m_config->gpgpu_dual_issue_diff_exec_units; while( !warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue) ) { const warp_inst_t *pI = warp(warp_id).ibuffer_next_inst(); //Jin: handle cdp latency; @@ -1062,7 +1063,7 @@ void oldest_scheduler::order_warps() m_supervised_warps, m_last_supervised_issued, m_supervised_warps.size(), - ORDERED_PRIORITY_FUNC_ONLY, + ORDERED_PRIORITY_FUNC_ONLY, scheduler_unit::sort_warps_by_oldest_dynamic_id ); } diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 395c1ed..2fed420 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -316,7 +316,7 @@ enum concrete_scheduler CONCRETE_SCHEDULER_GTO, CONCRETE_SCHEDULER_TWO_LEVEL_ACTIVE, CONCRETE_SCHEDULER_WARP_LIMITING, - CONCRETE_SCHEDULER_OLDEST_FIRST, + CONCRETE_SCHEDULER_OLDEST_FIRST, NUM_CONCRETE_SCHEDULERS }; @@ -456,7 +456,7 @@ public: : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, mem_out, id ){} virtual ~oldest_scheduler () {} virtual void order_warps (); - virtual void done_adding_supervised_warps() { + virtual void done_adding_supervised_warps() { m_last_supervised_issued = m_supervised_warps.begin(); } -- cgit v1.3 From bc69b31897d6e11dc98d4d75bd7b902a42b146bc Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Tue, 18 Jul 2017 12:59:52 -0400 Subject: Fixing deadlock bug --- src/gpgpu-sim/shader.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index d826b69..bb2cf0e 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -482,11 +482,11 @@ void shader_core_stats::print( FILE* fout ) const for (unsigned i = 3; i < m_config->warp_size + 3; i++) fprintf(fout, "\tW%d:%d", i-2, shader_cycle_distro[i]); fprintf(fout, "\n"); - fprintf(fout, "single_issue_nums:"); + fprintf(fout, "single_issue_nums: "); for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; i++) fprintf(fout, "WS%d:%d\t", i, single_issue_nums[i]); fprintf(fout, "\n"); - fprintf(fout, "dual_issue_nums:"); + fprintf(fout, "dual_issue_nums: "); for (unsigned i = 0; i < m_config->gpgpu_num_sched_per_core; i++) fprintf(fout, "WS%d:%d\t", i, dual_issue_nums[i]); fprintf(fout, "\n"); @@ -911,8 +911,8 @@ void scheduler_unit::cycle() ready_inst = true; const active_mask_t &active_mask = m_simt_stack[warp_id]->get_active_mask(); assert( warp(warp_id).inst_in_pipeline() ); - if( m_mem_out->has_free() && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::MEM)) { - if( m_mem_out->has_free() ) { + if ( (pI->op == LOAD_OP) || (pI->op == STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) { + if( m_mem_out->has_free() && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::MEM)) { m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id); issued++; issued_inst=true; -- cgit v1.3 From 86a344a721b3215da894794675bd709da79e44db Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Tue, 18 Jul 2017 16:56:08 -0400 Subject: Free buffer interconnection assertion --- src/intersim2/interconnect_interface.cpp | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/intersim2/interconnect_interface.cpp b/src/intersim2/interconnect_interface.cpp index 4386821..456b757 100644 --- a/src/intersim2/interconnect_interface.cpp +++ b/src/intersim2/interconnect_interface.cpp @@ -146,7 +146,16 @@ void InterconnectInterface::Init() void InterconnectInterface::Push(unsigned input_deviceID, unsigned output_deviceID, void *data, unsigned int size) { // it should have free buffer - assert(HasBuffer(input_deviceID, size)); + bool hasBuffer = HasBuffer(input_deviceID, size); +#if 0 + if(!hasBuffer) + { + cout<<"No free buffer for input_deviceID: "< Date: Tue, 18 Jul 2017 17:35:20 -0400 Subject: Interconnection assertion failing demysstifying --- src/intersim2/interconnect_interface.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/intersim2/interconnect_interface.cpp b/src/intersim2/interconnect_interface.cpp index 456b757..b397aad 100644 --- a/src/intersim2/interconnect_interface.cpp +++ b/src/intersim2/interconnect_interface.cpp @@ -187,7 +187,11 @@ void InterconnectInterface::Push(unsigned input_deviceID, unsigned output_device case WRITE_REQUEST: packet_type = Flit::WRITE_REQUEST ;break; case READ_REPLY: packet_type = Flit::READ_REPLY ;break; case WRITE_ACK: packet_type = Flit::WRITE_REPLY ;break; - default: assert (0); + default: + { + cout<<"Type "<get_type()<<" is undefined!"< Date: Wed, 19 Jul 2017 12:04:54 -0400 Subject: Adding some interconnection traces --- src/intersim2/Makefile | 2 +- src/intersim2/interconnect_interface.cpp | 14 ++++---------- src/trace_streams.tup | 1 + 3 files changed, 6 insertions(+), 11 deletions(-) diff --git a/src/intersim2/Makefile b/src/intersim2/Makefile index ef948d6..4c7d8cc 100644 --- a/src/intersim2/Makefile +++ b/src/intersim2/Makefile @@ -36,7 +36,7 @@ DEBUG ?= 0 LEX = flex YACC = bison -y DEFINE = #-DTRACK_STALLS -DTRACK_BUFFERS -DTRACK_FLOWS -DTRACK_CREDITS -INCPATH = -I. -Iarbiters -Iallocators -Irouters -Inetworks -Ipower +INCPATH = -I. -Iarbiters -Iallocators -Irouters -Inetworks -Ipower -I$(GPGPUSIM_ROOT)/src ifeq ($(CREATE_LIBRARY),1) INCPATH += -I$(GPGPUSIM_ROOT)/src/gpgpu-sim/ diff --git a/src/intersim2/interconnect_interface.cpp b/src/intersim2/interconnect_interface.cpp index b397aad..1e1a2d7 100644 --- a/src/intersim2/interconnect_interface.cpp +++ b/src/intersim2/interconnect_interface.cpp @@ -44,6 +44,7 @@ #include "booksim.hpp" #include "intersim_config.hpp" #include "network.hpp" +#include "trace.h" InterconnectInterface* InterconnectInterface::New(const char* const config_file) { @@ -146,16 +147,9 @@ void InterconnectInterface::Init() void InterconnectInterface::Push(unsigned input_deviceID, unsigned output_deviceID, void *data, unsigned int size) { // it should have free buffer - bool hasBuffer = HasBuffer(input_deviceID, size); -#if 0 - if(!hasBuffer) - { - cout<<"No free buffer for input_deviceID: "< Date: Wed, 19 Jul 2017 12:11:12 -0400 Subject: trying to refomat the Jenkinsfile to be more reader friendly --- Jenkinsfile | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 6063245..453cce4 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -6,7 +6,16 @@ pipeline { stages { stage('4.2-regress') { steps { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh && source `pwd`/setup_environment && make -j && rm -rf gpgpu-sim_simulations && git clone https://github.com/tgrogers/gpgpu-sim_simulations.git && cd gpgpu-sim_simulations && git checkout purdue-cluster && make -j -C ./benchmarks/src all && ./util/job_launching/run_simulations.py -N regress &&./util/job_launching/monitor_func_test.py -v -N regress' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment && \ + make -j && \ + rm -rf gpgpu-sim_simulations && \ + git clone https://github.com/tgrogers/gpgpu-sim_simulations.git && \ + cd gpgpu-sim_simulations && \ + git checkout purdue-cluster && \ + make -j -C ./benchmarks/src all && \ + ./util/job_launching/run_simulations.py -N regress && \ + ./util/job_launching/monitor_func_test.py -v -N regress' } } } -- cgit v1.3 From e71aaaba5201e48790aa63df4dc2aa1de2fffda1 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 19 Jul 2017 13:46:35 -0400 Subject: Updaing the interconnect simulator to properly check for dependencies --- src/intersim2/Makefile | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/intersim2/Makefile b/src/intersim2/Makefile index ef948d6..bd42000 100644 --- a/src/intersim2/Makefile +++ b/src/intersim2/Makefile @@ -125,6 +125,14 @@ endif # rules to compile simulator +$(OBJDIR)/Makefile.makedepend: depend + +ALL_SRCS = $(CPP_SRCS) +ALL_SRCS += $(shell ls **/*.cpp) + +depend: + touch $(OBJDIR)/Makefile.makedepend + makedepend -f$(OBJDIR)/Makefile.makedepend -I$(INCPATH) -p$(OBJDIR)/ $(ALL_SRCS) 2> /dev/null ${LEX_OBJS}: $(OBJDIR)/lex.yy.c $(OBJDIR)/y.tab.h $(CC) $(CPPFLAGS) -c $< -o $@ @@ -173,3 +181,5 @@ $(OBJDIR)/y.tab.c $(OBJDIR)/y.tab.h: config.y $(OBJDIR)/lex.yy.c: config.l $(LEX) -o$@ $< + +include $(OBJDIR)/Makefile.makedepend -- cgit v1.3 From 6726b3fc7a10be5ed3af4d99110634638e4ca61c Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 19 Jul 2017 14:04:35 -0400 Subject: Adding in auto-email stuff --- Jenkinsfile | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Jenkinsfile b/Jenkinsfile index 453cce4..7075601 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -16,7 +16,19 @@ pipeline { make -j -C ./benchmarks/src all && \ ./util/job_launching/run_simulations.py -N regress && \ ./util/job_launching/monitor_func_test.py -v -N regress' + + emailex + body: '''$PROJECT_NAME - Build # $BUILD_NUMBER - $BUILD_STATUS: + Check console output at $BUILD_URL to view the results.''', + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + replyTo: 'tgrogers@purdue.edu', + subject: '[AALP Jenkins]: $PROJECT_NAME - Build # $BUILD_NUMBER - $BUILD_STATUS!', + to: 'tgrogers@purdue.edu' } } } + + + } -- cgit v1.3 From b41e86008dbf6bc5b5e07dbe72ba08779a9b7d6e Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 19 Jul 2017 14:44:33 -0400 Subject: changing the varnames - not sure if this is valid yet... --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 7075601..54fe4d5 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -18,12 +18,12 @@ pipeline { ./util/job_launching/monitor_func_test.py -v -N regress' emailex - body: '''$PROJECT_NAME - Build # $BUILD_NUMBER - $BUILD_STATUS: + body: '''$JOB_NAME - $BRANCH_NAME - Build # currentBuild.number - currentBuild.result: Check console output at $BUILD_URL to view the results.''', recipientProviders: [[$class: 'CulpritsRecipientProvider'], [$class: 'RequesterRecipientProvider']], replyTo: 'tgrogers@purdue.edu', - subject: '[AALP Jenkins]: $PROJECT_NAME - Build # $BUILD_NUMBER - $BUILD_STATUS!', + subject: '[AALP Jenkins]: $JOB_NAME - Build # currentBuild.number - currentBuild.result!', to: 'tgrogers@purdue.edu' } } -- cgit v1.3 From 4caffa019eb99713ad580259f944952056b65223 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 19 Jul 2017 14:50:50 -0400 Subject: quotes? --- Jenkinsfile | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 54fe4d5..fad7bb0 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -18,12 +18,12 @@ pipeline { ./util/job_launching/monitor_func_test.py -v -N regress' emailex - body: '''$JOB_NAME - $BRANCH_NAME - Build # currentBuild.number - currentBuild.result: - Check console output at $BUILD_URL to view the results.''', - recipientProviders: [[$class: 'CulpritsRecipientProvider'], - [$class: 'RequesterRecipientProvider']], - replyTo: 'tgrogers@purdue.edu', - subject: '[AALP Jenkins]: $JOB_NAME - Build # currentBuild.number - currentBuild.result!', + body: "$JOB_NAME - $BRANCH_NAME - Build # currentBuild.number - currentBuild.result: + Check console output at $BUILD_URL to view the results.", + recipientProviders: [[$class: "CulpritsRecipientProvider"], + [$class: "RequesterRecipientProvider"]], + replyTo: "tgrogers@purdue.edu", + subject: "[AALP Jenkins]: $JOB_NAME - Build # currentBuild.number - currentBuild.result!", to: 'tgrogers@purdue.edu' } } -- cgit v1.3 From 9100087555584013c735d6cddc0a8069567d564b Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 19 Jul 2017 15:13:37 -0400 Subject: does not like the space --- Jenkinsfile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index fad7bb0..8c05427 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -18,8 +18,7 @@ pipeline { ./util/job_launching/monitor_func_test.py -v -N regress' emailex - body: "$JOB_NAME - $BRANCH_NAME - Build # currentBuild.number - currentBuild.result: - Check console output at $BUILD_URL to view the results.", + body: "$JOB_NAME - $BRANCH_NAME - Build # currentBuild.number - currentBuild.result: Check console output at $BUILD_URL to view the results.", recipientProviders: [[$class: "CulpritsRecipientProvider"], [$class: "RequesterRecipientProvider"]], replyTo: "tgrogers@purdue.edu", -- cgit v1.3 From 2fc555094a7ba90540de7d02543a66909d84d126 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 19 Jul 2017 16:01:30 -0400 Subject: Trying a different auto-email --- Jenkinsfile | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 8c05427..a510f40 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -17,13 +17,17 @@ pipeline { ./util/job_launching/run_simulations.py -N regress && \ ./util/job_launching/monitor_func_test.py -v -N regress' - emailex - body: "$JOB_NAME - $BRANCH_NAME - Build # currentBuild.number - currentBuild.result: Check console output at $BUILD_URL to view the results.", - recipientProviders: [[$class: "CulpritsRecipientProvider"], - [$class: "RequesterRecipientProvider"]], - replyTo: "tgrogers@purdue.edu", - subject: "[AALP Jenkins]: $JOB_NAME - Build # currentBuild.number - currentBuild.result!", - to: 'tgrogers@purdue.edu' + + def to = emailextrecipients([ + [$class: 'CulpritsRecipientProvider'], + [$class: 'DevelopersRecipientProvider'], + [$class: 'RequesterRecipientProvider'] + ]) + + if(to != null && !to.isEmpty()) { + mail to: to, subject: "[AALP Jenkins] Build ${currentBuild.result}!", + body: "See ${env.BUILD_URL}" + } } } } -- cgit v1.3 From 744b2f50c86d1149d887645af1b4a2e16360a270 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 19 Jul 2017 16:07:45 -0400 Subject: inside step? --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index a510f40..1f6ed5f 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -18,7 +18,7 @@ pipeline { ./util/job_launching/monitor_func_test.py -v -N regress' - def to = emailextrecipients([ + step(def to = emailextrecipients([ [$class: 'CulpritsRecipientProvider'], [$class: 'DevelopersRecipientProvider'], [$class: 'RequesterRecipientProvider'] @@ -27,7 +27,7 @@ pipeline { if(to != null && !to.isEmpty()) { mail to: to, subject: "[AALP Jenkins] Build ${currentBuild.result}!", body: "See ${env.BUILD_URL}" - } + }) } } } -- cgit v1.3 From 96df59010db946696455bcc341a97198c1b0778f Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 19 Jul 2017 16:12:26 -0400 Subject: another example? --- Jenkinsfile | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 1f6ed5f..8a63478 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -17,17 +17,7 @@ pipeline { ./util/job_launching/run_simulations.py -N regress && \ ./util/job_launching/monitor_func_test.py -v -N regress' - - step(def to = emailextrecipients([ - [$class: 'CulpritsRecipientProvider'], - [$class: 'DevelopersRecipientProvider'], - [$class: 'RequesterRecipientProvider'] - ]) - - if(to != null && !to.isEmpty()) { - mail to: to, subject: "[AALP Jenkins] Build ${currentBuild.result}!", - body: "See ${env.BUILD_URL}" - }) + step([$class: 'Mailer', notifyEveryUnstableBuild: true, recipients: emailextrecipients([[$class: 'CulpritsRecipientProvider'], [$class: 'RequesterRecipientProvider']])]) } } } -- cgit v1.3 From 02544fc70c6f62ed1df8c8b2922cb6444db341a8 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 19 Jul 2017 16:21:01 -0400 Subject: another try at the email to make i more like I want --- Jenkinsfile | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 8a63478..24c676b 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -17,7 +17,11 @@ pipeline { ./util/job_launching/run_simulations.py -N regress && \ ./util/job_launching/monitor_func_test.py -v -N regress' - step([$class: 'Mailer', notifyEveryUnstableBuild: true, recipients: emailextrecipients([[$class: 'CulpritsRecipientProvider'], [$class: 'RequesterRecipientProvider']])]) + emailext body: 'See ${env.BUILD_URL}', + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: '[AALP Jenkins] Build #${currentBuild.number} - ${currentBuild.result}', + to: 'tgrogers@purdue.edu' } } } -- cgit v1.3 From a0fc0b6d5e561aabdb579149dc421e38ffba796e Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 19 Jul 2017 16:49:53 -0400 Subject: changing the mail again --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 24c676b..b342c77 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -17,10 +17,10 @@ pipeline { ./util/job_launching/run_simulations.py -N regress && \ ./util/job_launching/monitor_func_test.py -v -N regress' - emailext body: 'See ${env.BUILD_URL}', + emailext body: 'See ${BUILD_URL}', recipientProviders: [[$class: 'CulpritsRecipientProvider'], [$class: 'RequesterRecipientProvider']], - subject: '[AALP Jenkins] Build #${currentBuild.number} - ${currentBuild.result}', + subject: '[AALP Jenkins] Build #${BUILD_NUMBER} - $currentBuild.result', to: 'tgrogers@purdue.edu' } } -- cgit v1.3 From b3625f9f09d91538d4168004e2a4ce30836861cb Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 19 Jul 2017 17:45:11 -0400 Subject: Cleaning up the Jenkinsile to be more sane and have emails properly work --- Jenkinsfile | 39 ++++++++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index b342c77..19fbae4 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -4,28 +4,41 @@ pipeline { } stages { - stage('4.2-regress') { + stage('4.2-simulator-build'){ steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment && \ - make -j && \ + make -j' + } + } + stage('4.2-simulations-build'){ + steps{ + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment && \ rm -rf gpgpu-sim_simulations && \ git clone https://github.com/tgrogers/gpgpu-sim_simulations.git && \ cd gpgpu-sim_simulations && \ git checkout purdue-cluster && \ - make -j -C ./benchmarks/src all && \ - ./util/job_launching/run_simulations.py -N regress && \ - ./util/job_launching/monitor_func_test.py -v -N regress' - - emailext body: 'See ${BUILD_URL}', - recipientProviders: [[$class: 'CulpritsRecipientProvider'], - [$class: 'RequesterRecipientProvider']], - subject: '[AALP Jenkins] Build #${BUILD_NUMBER} - $currentBuild.result', - to: 'tgrogers@purdue.edu' + make -j -C ./benchmarks/src all' + } + } + stage('4.2-rodinia-regress'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress' } } } + post { + always{ + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - ${currentBuild.result}", + to: 'tgrogers@purdue.edu' - - + } + } } -- cgit v1.3 From 28a0a22a65d9c1ebe1558c838ff92bf17a22073b Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 12 Jul 2017 15:29:16 -0400 Subject: Fixing BankGroup Indexing Bug --- src/gpgpu-sim/gpu-sim.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index a2d1b9b..7d92c66 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -195,7 +195,7 @@ struct memory_config { for (i=0; nbkt>0; i++) { nbkt = nbkt>>1; } - bk_tag_length = i; + bk_tag_length = i-1; assert(nbkgrp>0 && "Number of bank groups cannot be zero"); tRCDWR = tRCD-(WL+1); tRTW = (CL+(BL/data_command_freq_ratio)+2-WL); -- cgit v1.3 From f5abe6f9573bfc1ccbdf52b4dc960599c974884f Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 19 Jul 2017 13:46:35 -0400 Subject: Updaing the interconnect simulator to properly check for dependencies --- src/intersim2/Makefile | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/intersim2/Makefile b/src/intersim2/Makefile index ef948d6..bd42000 100644 --- a/src/intersim2/Makefile +++ b/src/intersim2/Makefile @@ -125,6 +125,14 @@ endif # rules to compile simulator +$(OBJDIR)/Makefile.makedepend: depend + +ALL_SRCS = $(CPP_SRCS) +ALL_SRCS += $(shell ls **/*.cpp) + +depend: + touch $(OBJDIR)/Makefile.makedepend + makedepend -f$(OBJDIR)/Makefile.makedepend -I$(INCPATH) -p$(OBJDIR)/ $(ALL_SRCS) 2> /dev/null ${LEX_OBJS}: $(OBJDIR)/lex.yy.c $(OBJDIR)/y.tab.h $(CC) $(CPPFLAGS) -c $< -o $@ @@ -173,3 +181,5 @@ $(OBJDIR)/y.tab.c $(OBJDIR)/y.tab.h: config.y $(OBJDIR)/lex.yy.c: config.l $(LEX) -o$@ $< + +include $(OBJDIR)/Makefile.makedepend -- cgit v1.3 From 724fb1a44353df595bf03cad9553c7e34491e5c8 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 30 Jul 2017 15:14:05 -0400 Subject: ignore tags --- .gitignore | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 53fadb5..e78b216 100644 --- a/.gitignore +++ b/.gitignore @@ -26,4 +26,6 @@ cuobjdump_to_ptxplus/sass_parser.cc cuobjdump_to_ptxplus/sass_parser.hh cuobjdump_to_ptxplus/sass_parser.output -build/* \ No newline at end of file +build/* + +tags -- cgit v1.3 From fdf4ffb5b1dc213d1d775f3048567eaf36f6df66 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 14 Aug 2017 11:06:56 -0400 Subject: Changing the simulations directory to our local repo --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 19fbae4..0821837 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -16,7 +16,7 @@ pipeline { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment && \ rm -rf gpgpu-sim_simulations && \ - git clone https://github.com/tgrogers/gpgpu-sim_simulations.git && \ + git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ cd gpgpu-sim_simulations && \ git checkout purdue-cluster && \ make -j -C ./benchmarks/src all' -- cgit v1.3 From d553eefc40084fbe9abcc7eae6ef3801f25bedc8 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 14 Aug 2017 11:23:00 -0400 Subject: Adding in the setup_environment call --- Jenkinsfile | 1 + 1 file changed, 1 insertion(+) diff --git a/Jenkinsfile b/Jenkinsfile index 0821837..ef08b07 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -19,6 +19,7 @@ pipeline { git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ cd gpgpu-sim_simulations && \ git checkout purdue-cluster && \ + source `pwd`/setup_environment && \ make -j -C ./benchmarks/src all' } } -- cgit v1.3 From 2430287d5dc646d8ecc5ac4ea46d4ebccbd9b641 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 14 Aug 2017 11:25:56 -0400 Subject: Another Issue with the setup_enviro --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index ef08b07..3073022 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -19,7 +19,7 @@ pipeline { git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ cd gpgpu-sim_simulations && \ git checkout purdue-cluster && \ - source `pwd`/setup_environment && \ + source ./benchmarks/src/setup_environment && \ make -j -C ./benchmarks/src all' } } -- cgit v1.3 From 90ba89e6569b9727ac158efc768dd72229637018 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 14 Aug 2017 11:42:59 -0400 Subject: Adding in a test for CUDA 8.0 --- Jenkinsfile | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/Jenkinsfile b/Jenkinsfile index 3073022..5708add 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -4,6 +4,8 @@ pipeline { } stages { + parallel ( + "4.2 Tests" : { stage('4.2-simulator-build'){ steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ @@ -31,6 +33,39 @@ pipeline { ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress' } } + } + + "8.0 Tests" : { + stage('8.0-simulator-build'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ + source `pwd`/setup_environment && \ + make -j' + } + } + stage('8.0-simulations-build'){ + steps{ + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ + source `pwd`/setup_environment && \ + rm -rf gpgpu-sim_simulations && \ + git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ + cd gpgpu-sim_simulations && \ + git checkout purdue-cluster && \ + source ./benchmarks/src/setup_environment && \ + make -j -C ./benchmarks/src all' + } + } + stage('8.0-rodinia-regress'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ + source `pwd`/setup_environment && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress' + } + } + } + + ) } post { always{ -- cgit v1.3 From 15d071a76c34587f82b18b8354cfc75e923f6030 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 14 Aug 2017 12:31:53 -0400 Subject: No quotes? --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 5708add..8096eed 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -5,7 +5,7 @@ pipeline { stages { parallel ( - "4.2 Tests" : { + 4.2-Tests: { stage('4.2-simulator-build'){ steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ @@ -35,7 +35,7 @@ pipeline { } } - "8.0 Tests" : { + 8.0-Tests : { stage('8.0-simulator-build'){ steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ -- cgit v1.3 From a4cfe2a85499d23f4947695f9bf7e703029a2462 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 14 Aug 2017 12:39:52 -0400 Subject: Does this work for parallel? --- Jenkinsfile | 42 +++++++----------------------------------- 1 file changed, 7 insertions(+), 35 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 8096eed..c19b4de 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -4,48 +4,23 @@ pipeline { } stages { - parallel ( - 4.2-Tests: { - stage('4.2-simulator-build'){ + stage('4.2-simulator-build') + parallel 4.2: { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment && \ make -j' } - } - stage('4.2-simulations-build'){ - steps{ - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - source `pwd`/setup_environment && \ - rm -rf gpgpu-sim_simulations && \ - git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ - cd gpgpu-sim_simulations && \ - git checkout purdue-cluster && \ - source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src all' - } - } - stage('4.2-rodinia-regress'){ - steps { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - source `pwd`/setup_environment && \ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress' - } - } - } - - 8.0-Tests : { - stage('8.0-simulator-build'){ + }, 8.0: { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment && \ make -j' } } - stage('8.0-simulations-build'){ + stage('4.2-simulations-build'){ steps{ - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment && \ rm -rf gpgpu-sim_simulations && \ git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ @@ -55,18 +30,15 @@ pipeline { make -j -C ./benchmarks/src all' } } - stage('8.0-rodinia-regress'){ + stage('4.2-rodinia-regress'){ steps { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment && \ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress' } } } - - ) - } post { always{ emailext body: "See ${BUILD_URL}", -- cgit v1.3 From 502f3673df8df64bae84fbb0551d0447bd71a490 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 14 Aug 2017 12:58:20 -0400 Subject: Missed Bracket --- Jenkinsfile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index c19b4de..010c866 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -4,7 +4,7 @@ pipeline { } stages { - stage('4.2-simulator-build') + stage('4.2-simulator-build') { parallel 4.2: { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ @@ -18,6 +18,7 @@ pipeline { make -j' } } + } stage('4.2-simulations-build'){ steps{ sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ -- cgit v1.3 From 06e21dda283bc3a1a9939f8b59bf2729438ec4fa Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 14 Aug 2017 13:06:36 -0400 Subject: Trying a different arrangement of parallel and the stahes --- Jenkinsfile | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 010c866..bc8127d 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -4,20 +4,18 @@ pipeline { } stages { - stage('4.2-simulator-build') { - parallel 4.2: { - steps { + stage('simulator-build') { + steps { + parallel 4.2: { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment && \ make -j' - } - }, 8.0: { - steps { + }, 8.0: { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment && \ make -j' } - } + } } stage('4.2-simulations-build'){ steps{ -- cgit v1.3 From f53e6f0c2417383f08ab313e3ad124d6dc6345db Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 14 Aug 2017 13:09:51 -0400 Subject: It wants a string literal --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index bc8127d..c7f6ac1 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -6,11 +6,11 @@ pipeline { stages { stage('simulator-build') { steps { - parallel 4.2: { + parallel "4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment && \ make -j' - }, 8.0: { + }, "8.0": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment && \ make -j' -- cgit v1.3 From ccff37780d7b1a0781ff370b2a93a94acdf1147b Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 14 Aug 2017 13:19:27 -0400 Subject: can I do stages in parallel? --- Jenkinsfile | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index c7f6ac1..139fd31 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -4,18 +4,16 @@ pipeline { } stages { - stage('simulator-build') { - steps { - parallel "4.2": { + parallel stage('4.2 simulator-build') { + steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment && \ make -j' - }, "8.0": { + } + }, stage('8..0 simulator-build') { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment && \ make -j' - } - } } stage('4.2-simulations-build'){ steps{ -- cgit v1.3 From 933330c51bb46efdb472fe7b7aa5d7ed4467bb56 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 14 Aug 2017 13:30:59 -0400 Subject: lets for get parallel - can we fix the env variables? --- Jenkinsfile | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 139fd31..43f44d9 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -1,25 +1,22 @@ pipeline { agent { label "purdue-cluster" - } + } stages { - parallel stage('4.2 simulator-build') { + stage('set-env') { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment + } + + stage('4.2 simulator-build') { steps { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - source `pwd`/setup_environment && \ - make -j' + sh 'make -j' } - }, stage('8..0 simulator-build') { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ - source `pwd`/setup_environment && \ - make -j' } stage('4.2-simulations-build'){ steps{ - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - source `pwd`/setup_environment && \ - rm -rf gpgpu-sim_simulations && \ + sh 'rm -rf gpgpu-sim_simulations && \ git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ cd gpgpu-sim_simulations && \ git checkout purdue-cluster && \ @@ -29,13 +26,11 @@ pipeline { } stage('4.2-rodinia-regress'){ steps { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - source `pwd`/setup_environment && \ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && \ + sh './gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress' } } - } + } post { always{ emailext body: "See ${BUILD_URL}", -- cgit v1.3 From 15e4cfc8f65baac21cb6dc8650e37869398724d3 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 14 Aug 2017 13:32:53 -0400 Subject: missing quote --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 43f44d9..cbaa086 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -6,7 +6,7 @@ pipeline { stages { stage('set-env') { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - source `pwd`/setup_environment + source `pwd`/setup_environment' } stage('4.2 simulator-build') { -- cgit v1.3 From c90e11408b5e4e06ef3b329d1868e0523047ae6a Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 14 Aug 2017 13:35:26 -0400 Subject: forgot steps --- Jenkinsfile | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index cbaa086..38d8edd 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -5,8 +5,10 @@ pipeline { stages { stage('set-env') { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - source `pwd`/setup_environment' + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment' + } } stage('4.2 simulator-build') { -- cgit v1.3 From 366bab391e09ff137a0fadba09be8b823c8db57f Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 15 Aug 2017 22:41:35 -0400 Subject: Getting the Jenkinsfile to work with 4.5, 8.0 and do them in parallel. --- Jenkinsfile | 68 ++++++++++++++++++++++++++++++++++++++++++------------------- 1 file changed, 47 insertions(+), 21 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 38d8edd..dfe2d1c 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -4,43 +4,69 @@ pipeline { } stages { - stage('set-env') { + stage('simulator-build') { steps { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - source `pwd`/setup_environment' + + parallel "4.2": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + make -j' + }, "8.0" : { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + make -j' + } } } - - stage('4.2 simulator-build') { - steps { - sh 'make -j' - } - } - stage('4.2-simulations-build'){ + stage('simulations-build'){ steps{ - sh 'rm -rf gpgpu-sim_simulations && \ - git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ - cd gpgpu-sim_simulations && \ - git checkout purdue-cluster && \ - source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src all' + sh 'rm -rf gpgpu-sim_simulations' + sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ + cd gpgpu-sim_simulations && \ + git checkout purdue-cluster' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + cd gpgpu-sim_simulations && \ + source ./benchmarks/src/setup_environment && \ + make -j -C ./benchmarks/src all' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + cd gpgpu-sim_simulations && \ + source ./benchmarks/src/setup_environment && \ + make -j -C ./benchmarks/src all' } } - stage('4.2-rodinia-regress'){ + stage('rodinia-regress'){ steps { - sh './gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress' + parallel "4.2-rodinia": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' + }, "8.0-rodinia": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/benchmarks-8.0.yml -c ./gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs-fermi-plus-only.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' + } } } } post { - always{ + success { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - Success!", + to: 'tgrogers@purdue.edu' + } + failure { emailext body: "See ${BUILD_URL}", recipientProviders: [[$class: 'CulpritsRecipientProvider'], [$class: 'RequesterRecipientProvider']], subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - ${currentBuild.result}", to: 'tgrogers@purdue.edu' - } } } + -- cgit v1.3 From bff1764efb3e1dc91d61190ab61909ac345ec2f0 Mon Sep 17 00:00:00 2001 From: Timothy G Rogers Date: Tue, 15 Aug 2017 23:53:46 -0400 Subject: Dev purdue integration (#5) * ignore tags * Getting the Jenkinsfile to work with 4.5, 8.0 and do them in parallel. --- .gitignore | 4 +++- Jenkinsfile | 67 +++++++++++++++++++++++++++++++++++++++++++------------------ 2 files changed, 50 insertions(+), 21 deletions(-) diff --git a/.gitignore b/.gitignore index 53fadb5..e78b216 100644 --- a/.gitignore +++ b/.gitignore @@ -26,4 +26,6 @@ cuobjdump_to_ptxplus/sass_parser.cc cuobjdump_to_ptxplus/sass_parser.hh cuobjdump_to_ptxplus/sass_parser.output -build/* \ No newline at end of file +build/* + +tags diff --git a/Jenkinsfile b/Jenkinsfile index 3073022..dfe2d1c 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -1,45 +1,72 @@ pipeline { agent { label "purdue-cluster" - } + } stages { - stage('4.2-simulator-build'){ + stage('simulator-build') { steps { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - source `pwd`/setup_environment && \ - make -j' + + parallel "4.2": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + make -j' + }, "8.0" : { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + make -j' + } } } - stage('4.2-simulations-build'){ + stage('simulations-build'){ steps{ + sh 'rm -rf gpgpu-sim_simulations' + sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ + cd gpgpu-sim_simulations && \ + git checkout purdue-cluster' sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - source `pwd`/setup_environment && \ - rm -rf gpgpu-sim_simulations && \ - git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ - cd gpgpu-sim_simulations && \ - git checkout purdue-cluster && \ - source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src all' + source `pwd`/setup_environment &&\ + cd gpgpu-sim_simulations && \ + source ./benchmarks/src/setup_environment && \ + make -j -C ./benchmarks/src all' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + cd gpgpu-sim_simulations && \ + source ./benchmarks/src/setup_environment && \ + make -j -C ./benchmarks/src all' } } - stage('4.2-rodinia-regress'){ + stage('rodinia-regress'){ steps { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - source `pwd`/setup_environment && \ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress' + parallel "4.2-rodinia": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' + }, "8.0-rodinia": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/benchmarks-8.0.yml -c ./gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs-fermi-plus-only.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' + } } } } post { - always{ + success { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - Success!", + to: 'tgrogers@purdue.edu' + } + failure { emailext body: "See ${BUILD_URL}", recipientProviders: [[$class: 'CulpritsRecipientProvider'], [$class: 'RequesterRecipientProvider']], subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - ${currentBuild.result}", to: 'tgrogers@purdue.edu' - } } } + -- cgit v1.3 From 3e718d76b0e6ab9691648a02672d44f5da98462e Mon Sep 17 00:00:00 2001 From: speverel Date: Fri, 18 Aug 2017 14:17:42 -0700 Subject: Added configuration for NVIDIA GeForce GTX1080Ti --- configs/GeForceGTX1080Ti/config_fermi_islip.icnt | 70 +++ configs/GeForceGTX1080Ti/gpgpusim.config | 149 +++++++ configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml | 538 +++++++++++++++++++++++ 3 files changed, 757 insertions(+) create mode 100644 configs/GeForceGTX1080Ti/config_fermi_islip.icnt create mode 100644 configs/GeForceGTX1080Ti/gpgpusim.config create mode 100755 configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml diff --git a/configs/GeForceGTX1080Ti/config_fermi_islip.icnt b/configs/GeForceGTX1080Ti/config_fermi_islip.icnt new file mode 100644 index 0000000..2a69ddd --- /dev/null +++ b/configs/GeForceGTX1080Ti/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 50; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/GeForceGTX1080Ti/gpgpusim.config b/configs/GeForceGTX1080Ti/gpgpusim.config new file mode 100644 index 0000000..47c2b6a --- /dev/null +++ b/configs/GeForceGTX1080Ti/gpgpusim.config @@ -0,0 +1,149 @@ +# This config models the Pascal GP102 (GeForceGTX 1080Ti) + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 20 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 11 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 1,2,1,1,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The default is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_shmem_size 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 +-gpgpu_cache:dl2_texture_only 0 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +# gpgpu_num_reg_banks should be increased to 32, but it gives an error! +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) +# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" + +# Pascal has four schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml b/configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml new file mode 100755 index 0000000..02619ff --- /dev/null +++ b/configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.3 From 97a37f639b25ffed12f7222ac45d1f17dff56c83 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 18 Aug 2017 21:06:04 -0400 Subject: Adding in a new travis test for the new config --- .travis.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.travis.yml b/.travis.yml index fabfc5b..6ef6730 100644 --- a/.travis.yml +++ b/.travis.yml @@ -19,5 +19,7 @@ matrix: env: CONFIG=configs.quadro5800.yml - services: docker env: CONFIG=configs.teslac2050.yml + - services: docker + env: CONFIG=configs.gtx1080ti.yml script: docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" -- cgit v1.3 From 2ec7cb00b1beb7854e0a4493dbeef130a996a19d Mon Sep 17 00:00:00 2001 From: Mengchi Zhang Date: Sat, 9 Sep 2017 02:09:27 -0400 Subject: Modify import to make matplotlib compatible with new python Signed-off-by: Mengchi Zhang --- aerialvision/guiclasses.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/aerialvision/guiclasses.py b/aerialvision/guiclasses.py index 0a7013b..45fed26 100644 --- a/aerialvision/guiclasses.py +++ b/aerialvision/guiclasses.py @@ -69,7 +69,7 @@ import matplotlib matplotlib.use('TkAgg') from matplotlib.backends.backend_tkagg import FigureCanvasTkAgg, NavigationToolbar2TkAgg from matplotlib.figure import Figure -from matplotlib import mpl +import matplotlib as mpl from matplotlib.colors import colorConverter from matplotlib import pyplot import Pmw -- cgit v1.3 From f678104dcc3e5c970b871244e18e38f97c0caaa5 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Tue, 12 Sep 2017 18:53:26 -0400 Subject: Adding HBM model --- src/gpgpu-sim/dram.cc | 597 +++++++++++++++++++++++++++++++++----------- src/gpgpu-sim/dram.h | 59 ++++- src/gpgpu-sim/dram_sched.cc | 11 +- src/gpgpu-sim/gpu-sim.cc | 9 + src/gpgpu-sim/gpu-sim.h | 4 + 5 files changed, 534 insertions(+), 146 deletions(-) diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index a0e024b..352bd58 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -49,11 +49,41 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m m_stats = stats; m_config = config; + //rowblp + access_num=0; + hits_num=0; + banks_1time=0; + banks_acess_total=0; + banks_acess_total_after=0; + banks_time_ready=0; + banks_access_ready_total=0; + issued_two=0; + issued_total=0; + issued_total_row=0; + issued_total_col=0; + CCDc = 0; RRDc = 0; RTWc = 0; WTRc = 0; + wasted_bw_row=0; + wasted_bw_col=0; + util_bw=0; + idle_bw=0; + RCDc_limit=0; + CCDLc_limit=0; + CCDLc_limit_alone=0; + CCDc_limit=0; + WTRc_limit=0; + WTRc_limit_alone=0; + RCDWRc_limit=0; + RTWc_limit=0; + RTWc_limit_alone=0; + rwq_limit=0; + write_to_read_ratio_blp_rw_average=0; + bkgrp_parallsim_rw=0; + rw = READ; //read mode is default bkgrp = (bankgrp_t**) calloc(sizeof(bankgrp_t*), m_config->nbkgrp); @@ -74,12 +104,13 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m bk[i]->state = BANK_IDLE; bk[i]->bkgrpindex = i/(m_config->nbk/m_config->nbkgrp); } - prio = 0; + prio = 0; + rwq = new fifo_pipeline("rwq",m_config->CL,m_config->CL+1); mrqq = new fifo_pipeline("mrqq",0,2); returnq = new fifo_pipeline("dramreturnq",0,m_config->gpgpu_dram_return_queue_size==0?1024:m_config->gpgpu_dram_return_queue_size); m_frfcfs_scheduler = NULL; - if ( m_config->scheduler_type == DRAM_FRFCFS ) + if ( m_config->scheduler_type == DRAM_FRFCFS) m_frfcfs_scheduler = new frfcfs_scheduler(m_config,this,stats); n_cmd = 0; n_activity = 0; @@ -88,6 +119,8 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m n_pre = 0; n_rd = 0; n_wr = 0; + n_wr_WB=0; + n_rd_L2_A=0; n_req = 0; max_mrqs_temp = 0; bwutil = 0; @@ -113,11 +146,12 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m mrqq_Dist = StatCreate("mrqq_length",1, queue_limit()); else //queue length is unlimited; mrqq_Dist = StatCreate("mrqq_length",1,64); //track up to 64 entries + } bool dram_t::full() const { - if(m_config->scheduler_type == DRAM_FRFCFS ){ + if(m_config->scheduler_type == DRAM_FRFCFS){ if(m_config->gpgpu_frfcfs_dram_sched_queue_size == 0 ) return false; return m_frfcfs_scheduler->num_pending() >= m_config->gpgpu_frfcfs_dram_sched_queue_size; } @@ -127,7 +161,7 @@ bool dram_t::full() const unsigned dram_t::que_length() const { unsigned nreqs = 0; - if (m_config->scheduler_type == DRAM_FRFCFS ) { + if (m_config->scheduler_type == DRAM_FRFCFS) { nreqs = m_frfcfs_scheduler->num_pending(); } else { nreqs = mrqq->get_length(); @@ -146,7 +180,7 @@ unsigned int dram_t::queue_limit() const } -dram_req_t::dram_req_t( class mem_fetch *mf ) +dram_req_t::dram_req_t( class mem_fetch *mf, unsigned banks, unsigned dram_bnk_indexing_policy) { txbytes = 0; dqbytes = 0; @@ -154,7 +188,15 @@ dram_req_t::dram_req_t( class mem_fetch *mf ) const addrdec_t &tlx = mf->get_tlx_addr(); - bk = tlx.bk; + if(dram_bnk_indexing_policy == 0) { + int lbank = log2(banks); + bk = tlx.bk ^ (((1<get_data_size(); @@ -169,14 +211,15 @@ void dram_t::push( class mem_fetch *data ) { assert(id == data->get_tlx_addr().chip); // Ensure request is in correct memory partition - dram_req_t *mrq = new dram_req_t(data); + dram_req_t *mrq = new dram_req_t(data,m_config->nbk,m_config->dram_bnk_indexing_policy); + data->set_status(IN_PARTITION_MC_INTERFACE_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); - mrqq->push(mrq); + mrqq->push(mrq); // stats... n_req += 1; n_req_partial += 1; - if ( m_config->scheduler_type == DRAM_FRFCFS ) { + if ( m_config->scheduler_type == DRAM_FRFCFS) { unsigned nreqs = m_frfcfs_scheduler->num_pending(); if ( nreqs > max_mrqs_temp) max_mrqs_temp = nreqs; @@ -212,6 +255,7 @@ void dram_t::cycle() printf("\tDQ: BK%d Row:%03x Col:%03x", cmd->bk, cmd->row, cmd->col + cmd->dqbytes); #endif cmd->dqbytes += m_config->dram_atom_size; + if (cmd->dqbytes >= cmd->nbytes) { mem_fetch *data = cmd->data; data->set_status(IN_PARTITION_MC_RETURNQ,gpu_sim_cycle+gpu_tot_sim_cycle); @@ -240,7 +284,7 @@ void dram_t::cycle() printf("Error: Unknown DRAM scheduler type\n"); assert(0); } - if ( m_config->scheduler_type == DRAM_FRFCFS ) { + if ( m_config->scheduler_type == DRAM_FRFCFS) { unsigned nreqs = m_frfcfs_scheduler->num_pending(); if ( nreqs > max_mrqs) { max_mrqs = nreqs; @@ -258,130 +302,123 @@ void dram_t::cycle() unsigned k=m_config->nbk; bool issued = false; - // check if any bank is ready to issue a new read + //collect row buffer locality, BLP and other statistics + ///////////////////////////////////////////////////////////////////////// + unsigned int memory_Pending=0; for (unsigned i=0;inbk;i++) { - unsigned j = (i + prio) % m_config->nbk; - unsigned grp = j>>m_config->bk_tag_length; - if (bk[j]->mrq) { //if currently servicing a memory request - bk[j]->mrq->data->set_status(IN_PARTITION_DRAM,gpu_sim_cycle+gpu_tot_sim_cycle); - // correct row activated for a READ - if ( !issued && !CCDc && !bk[j]->RCDc && - !(bkgrp[grp]->CCDLc) && - (bk[j]->curr_row == bk[j]->mrq->row) && - (bk[j]->mrq->rw == READ) && (WTRc == 0 ) && - (bk[j]->state == BANK_ACTIVE) && - !rwq->full() ) { - if (rw==WRITE) { - rw=READ; - rwq->set_min_length(m_config->CL); - } - rwq->push(bk[j]->mrq); - bk[j]->mrq->txbytes += m_config->dram_atom_size; - CCDc = m_config->tCCD; - bkgrp[grp]->CCDLc = m_config->tCCDL; - RTWc = m_config->tRTW; - bk[j]->RTPc = m_config->BL/m_config->data_command_freq_ratio; - bkgrp[grp]->RTPLc = m_config->tRTPL; - issued = true; - n_rd++; - bwutil += m_config->BL/m_config->data_command_freq_ratio; - bwutil_partial += m_config->BL/m_config->data_command_freq_ratio; - bk[j]->n_access++; -#ifdef DRAM_VERIFY - PRINT_CYCLE=1; - printf("\tRD Bk:%d Row:%03x Col:%03x \n", - j, bk[j]->curr_row, - bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size); -#endif - // transfer done - if ( !(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes) ) { - bk[j]->mrq = NULL; - } - } else - // correct row activated for a WRITE - if ( !issued && !CCDc && !bk[j]->RCDWRc && - !(bkgrp[grp]->CCDLc) && - (bk[j]->curr_row == bk[j]->mrq->row) && - (bk[j]->mrq->rw == WRITE) && (RTWc == 0 ) && - (bk[j]->state == BANK_ACTIVE) && - !rwq->full() ) { - if (rw==READ) { - rw=WRITE; - rwq->set_min_length(m_config->WL); - } - rwq->push(bk[j]->mrq); - - bk[j]->mrq->txbytes += m_config->dram_atom_size; - CCDc = m_config->tCCD; - bkgrp[grp]->CCDLc = m_config->tCCDL; - WTRc = m_config->tWTR; - bk[j]->WTPc = m_config->tWTP; - issued = true; - n_wr++; - bwutil += m_config->BL/m_config->data_command_freq_ratio; - bwutil_partial += m_config->BL/m_config->data_command_freq_ratio; -#ifdef DRAM_VERIFY - PRINT_CYCLE=1; - printf("\tWR Bk:%d Row:%03x Col:%03x \n", - j, bk[j]->curr_row, - bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size); -#endif - // transfer done - if ( !(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes) ) { - bk[j]->mrq = NULL; - } - } - - else - // bank is idle - if ( !issued && !RRDc && - (bk[j]->state == BANK_IDLE) && - !bk[j]->RPc && !bk[j]->RCc ) { -#ifdef DRAM_VERIFY - PRINT_CYCLE=1; - printf("\tACT BK:%d NewRow:%03x From:%03x \n", - j,bk[j]->mrq->row,bk[j]->curr_row); -#endif - // activate the row with current memory request - bk[j]->curr_row = bk[j]->mrq->row; - bk[j]->state = BANK_ACTIVE; - RRDc = m_config->tRRD; - bk[j]->RCDc = m_config->tRCD; - bk[j]->RCDWRc = m_config->tRCDWR; - bk[j]->RASc = m_config->tRAS; - bk[j]->RCc = m_config->tRC; - prio = (j + 1) % m_config->nbk; - issued = true; - n_act_partial++; - n_act++; - } - - else - // different row activated - if ( (!issued) && - (bk[j]->curr_row != bk[j]->mrq->row) && - (bk[j]->state == BANK_ACTIVE) && - (!bk[j]->RASc && !bk[j]->WTPc && - !bk[j]->RTPc && - !bkgrp[grp]->RTPLc) ) { - // make the bank idle again - bk[j]->state = BANK_IDLE; - bk[j]->RPc = m_config->tRP; - prio = (j + 1) % m_config->nbk; - issued = true; - n_pre++; - n_pre_partial++; -#ifdef DRAM_VERIFY - PRINT_CYCLE=1; - printf("\tPRE BK:%d Row:%03x \n", j,bk[j]->curr_row); -#endif - } - } else { - if (!CCDc && !RRDc && !RTWc && !WTRc && !bk[j]->RCDc && !bk[j]->RASc - && !bk[j]->RCc && !bk[j]->RPc && !bk[j]->RCDWRc) k--; - bk[j]->n_idle++; - } + if (bk[i]->mrq) + memory_Pending++; + } + banks_1time += memory_Pending; + if(memory_Pending >0) + banks_acess_total++; + + unsigned int memory_pending_rw=0; + unsigned read_BLP_RW=0; + unsigned write_BLP_RW=0; + std::bitset<8> bnkgrp_RW_found; + //bool memory_pending_rw_found=false; + for (unsigned j=0;jnbk;j++) { + unsigned grp = get_bankgrp_number(j); + if (bk[j]->mrq && (((bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == READ) && + (bk[j]->state == BANK_ACTIVE)))) + { + memory_pending_rw++; + read_BLP_RW++; + bnkgrp_RW_found.set(grp); + } + else if + (bk[j]->mrq && (((bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == WRITE) && + (bk[j]->state == BANK_ACTIVE)))) + { + memory_pending_rw++; + write_BLP_RW++; + bnkgrp_RW_found.set(grp); + } + } + banks_time_rw += memory_pending_rw; + bkgrp_parallsim_rw += bnkgrp_RW_found.count(); + if(memory_pending_rw >0) + { + write_to_read_ratio_blp_rw_average += (double)write_BLP_RW/(write_BLP_RW+read_BLP_RW); + banks_access_rw_total++; + } + + unsigned int memory_Pending_ready=0; + for (unsigned j=0;jnbk;j++) { + unsigned grp = get_bankgrp_number(j); + if (bk[j]->mrq && ((!CCDc && !bk[j]->RCDc && + !(bkgrp[grp]->CCDLc) && + (bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == READ) && (WTRc == 0 ) && + (bk[j]->state == BANK_ACTIVE) && + !rwq->full()) + || + (!CCDc && !bk[j]->RCDWRc && + !(bkgrp[grp]->CCDLc) && + (bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == WRITE) && (RTWc == 0 ) && + (bk[j]->state == BANK_ACTIVE) && + !rwq->full()))) + { + memory_Pending_ready++; + } + } + banks_time_ready += memory_Pending_ready; + if(memory_Pending_ready >0) + banks_access_ready_total++; + /////////////////////////////////////////////////////////////////////////////////// + + bool issued_col_cmd = false; + bool issued_row_cmd = false; + + if(m_config->dual_bus_interface) + { + //dual bus interface + //issue one row command and one column command + for (unsigned i=0;inbk;i++) { + unsigned j = (i + prio) % m_config->nbk; + issued_col_cmd = issue_col_command(j); + if(issued_col_cmd) break; + } + for (unsigned i=0;inbk;i++) { + unsigned j = (i + prio) % m_config->nbk; + issued_row_cmd = issue_row_command(j); + if(issued_row_cmd) break; + } + for (unsigned i=0;inbk;i++) { + unsigned j = (i + prio) % m_config->nbk; + if(!bk[j]->mrq) { + if (!CCDc && !RRDc && !RTWc && !WTRc && !bk[j]->RCDc && !bk[j]->RASc + && !bk[j]->RCc && !bk[j]->RPc && !bk[j]->RCDWRc) k--; + bk[j]->n_idle++; + } + } } + else + { + //single bus interface + //issue only one row/column command + for (unsigned i=0;inbk;i++) { + unsigned j = (i + prio) % m_config->nbk; + if(!issued_col_cmd) + issued_col_cmd = issue_col_command(j); + + if(!issued_col_cmd && !issued_row_cmd) + issued_row_cmd = issue_row_command(j); + + if(!bk[j]->mrq) { + if (!CCDc && !RRDc && !RTWc && !WTRc && !bk[j]->RCDc && !bk[j]->RASc + && !bk[j]->RCc && !bk[j]->RPc && !bk[j]->RCDWRc) k--; + bk[j]->n_idle++; + } + + } + } + + issued = issued_row_cmd || issued_col_cmd; if (!issued) { n_nop++; n_nop_partial++; @@ -395,6 +432,80 @@ void dram_t::cycle() } n_cmd++; n_cmd_partial++; + if(issued) + { + issued_total++; + if(issued_col_cmd && issued_row_cmd) + issued_two++; + } + if(issued_col_cmd) issued_total_col++; + if(issued_row_cmd) issued_total_row++; + + unsigned int memory_pending_found=0; + for (unsigned i=0;inbk;i++) { + if (bk[i]->mrq) + memory_pending_found++; + } + if(memory_pending_found>0) + banks_acess_total_after++; + + bool memory_pending_rw_found=false; + for (unsigned j=0;jnbk;j++) { + unsigned grp = get_bankgrp_number(j); + if (bk[j]->mrq && (((bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == READ) && + (bk[j]->state == BANK_ACTIVE)) + || + ( + (bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == WRITE) && + (bk[j]->state == BANK_ACTIVE)))) + memory_pending_rw_found=true; + } + + //Collect some statistics + //check the limitation, why BW is wasted? + if(issued_col_cmd || CCDc) + util_bw++; + else if (memory_pending_rw_found) + { + wasted_bw_col++; + for (unsigned j=0;jnbk;j++) { + unsigned grp = get_bankgrp_number(j); + //read + if (bk[j]->mrq && (((bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == READ) && + (bk[j]->state == BANK_ACTIVE)))) + { + if(bk[j]->RCDc) RCDc_limit++; + if(bkgrp[grp]->CCDLc) CCDLc_limit++; + if(WTRc) WTRc_limit++; + if(CCDc) CCDc_limit++; + if(rwq->full()) rwq_limit++; + if(bkgrp[grp]->CCDLc && !WTRc) CCDLc_limit_alone++; + if(!bkgrp[grp]->CCDLc && WTRc) WTRc_limit_alone++; + } + //write + else if (bk[j]->mrq && ((bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == WRITE) && + (bk[j]->state == BANK_ACTIVE))) + { + if(bk[j]->RCDWRc) RCDWRc_limit++; + if(bkgrp[grp]->CCDLc) CCDLc_limit++; + if(RTWc) RTWc_limit++; + if(CCDc) CCDc_limit++; + if(rwq->full()) rwq_limit++; + if(bkgrp[grp]->CCDLc && !RTWc) CCDLc_limit_alone++; + if(!bkgrp[grp]->CCDLc && RTWc) RTWc_limit_alone++; + } + } + } + else if (memory_pending_found) + wasted_bw_row++; + else if (!memory_pending_found) + idle_bw++; + else + assert(1); // decrements counters once for each time dram_issueCMD is called DEC2ZERO(RRDc); @@ -420,39 +531,231 @@ void dram_t::cycle() #endif } +bool dram_t::issue_col_command(int j) +{ + bool issued = false; + unsigned grp = get_bankgrp_number(j); + if (bk[j]->mrq) { //if currently servicing a memory request + bk[j]->mrq->data->set_status(IN_PARTITION_DRAM,gpu_sim_cycle+gpu_tot_sim_cycle); + // correct row activated for a READ + if ( !issued && !CCDc && !bk[j]->RCDc && + !(bkgrp[grp]->CCDLc) && + (bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == READ) && (WTRc == 0 ) && + (bk[j]->state == BANK_ACTIVE) && + !rwq->full() ) { + if (rw==WRITE) { + rw=READ; + rwq->set_min_length(m_config->CL); + } + rwq->push(bk[j]->mrq); + bk[j]->mrq->txbytes += m_config->dram_atom_size; + CCDc = m_config->tCCD; + bkgrp[grp]->CCDLc = m_config->tCCDL; + RTWc = m_config->tRTW; + bk[j]->RTPc = m_config->BL/m_config->data_command_freq_ratio; + bkgrp[grp]->RTPLc = m_config->tRTPL; + issued = true; + if(bk[j]->mrq->data->get_access_type() == L2_WR_ALLOC_R) + n_rd_L2_A++; + else + n_rd++; + bwutil += m_config->BL/m_config->data_command_freq_ratio; + bwutil_partial += m_config->BL/m_config->data_command_freq_ratio; + bk[j]->n_access++; + +#ifdef DRAM_VERIFY + PRINT_CYCLE=1; + printf("\tRD Bk:%d Row:%03x Col:%03x \n", + j, bk[j]->curr_row, + bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size); +#endif + // transfer done + if ( !(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes) ) { + bk[j]->mrq = NULL; + } + } else + // correct row activated for a WRITE + if ( !issued && !CCDc && !bk[j]->RCDWRc && + !(bkgrp[grp]->CCDLc) && + (bk[j]->curr_row == bk[j]->mrq->row) && + (bk[j]->mrq->rw == WRITE) && (RTWc == 0 ) && + (bk[j]->state == BANK_ACTIVE) && + !rwq->full() ) { + if (rw==READ) { + rw=WRITE; + rwq->set_min_length(m_config->WL); + } + rwq->push(bk[j]->mrq); + + bk[j]->mrq->txbytes += m_config->dram_atom_size; + CCDc = m_config->tCCD; + bkgrp[grp]->CCDLc = m_config->tCCDL; + WTRc = m_config->tWTR; + bk[j]->WTPc = m_config->tWTP; + issued = true; + + if(bk[j]->mrq->data->get_access_type() == L2_WRBK_ACC) + n_wr_WB++; + else + n_wr++; + bwutil += m_config->BL/m_config->data_command_freq_ratio; + bwutil_partial += m_config->BL/m_config->data_command_freq_ratio; +#ifdef DRAM_VERIFY + PRINT_CYCLE=1; + printf("\tWR Bk:%d Row:%03x Col:%03x \n", + j, bk[j]->curr_row, + bk[j]->mrq->col + bk[j]->mrq->txbytes - m_config->dram_atom_size); +#endif + // transfer done + if ( !(bk[j]->mrq->txbytes < bk[j]->mrq->nbytes) ) { + bk[j]->mrq = NULL; + } + } + + } + + return issued; +} + +bool dram_t::issue_row_command(int j) +{ + bool issued = false; + unsigned grp = get_bankgrp_number(j); + if (bk[j]->mrq) { //if currently servicing a memory request + bk[j]->mrq->data->set_status(IN_PARTITION_DRAM,gpu_sim_cycle+gpu_tot_sim_cycle); + // bank is idle + //else + if ( !issued && !RRDc && + (bk[j]->state == BANK_IDLE) && + !bk[j]->RPc && !bk[j]->RCc) { // +#ifdef DRAM_VERIFY + PRINT_CYCLE=1; + printf("\tACT BK:%d NewRow:%03x From:%03x \n", + j,bk[j]->mrq->row,bk[j]->curr_row); +#endif + // activate the row with current memory request + bk[j]->curr_row = bk[j]->mrq->row; + bk[j]->state = BANK_ACTIVE; + RRDc = m_config->tRRD; + bk[j]->RCDc = m_config->tRCD; + bk[j]->RCDWRc = m_config->tRCDWR; + bk[j]->RASc = m_config->tRAS; + bk[j]->RCc = m_config->tRC; + prio = (j + 1) % m_config->nbk; + issued = true; + n_act_partial++; + n_act++; + } + + else + // different row activated + if ( (!issued) && + (bk[j]->curr_row != bk[j]->mrq->row) && + (bk[j]->state == BANK_ACTIVE) && + (!bk[j]->RASc && !bk[j]->WTPc && + !bk[j]->RTPc && + !bkgrp[grp]->RTPLc) ) { + // make the bank idle again + bk[j]->state = BANK_IDLE; + bk[j]->RPc = m_config->tRP; + prio = (j + 1) % m_config->nbk; + issued = true; + n_pre++; + n_pre_partial++; +#ifdef DRAM_VERIFY + PRINT_CYCLE=1; + printf("\tPRE BK:%d Row:%03x \n", j,bk[j]->curr_row); +#endif + } + } + return issued; +} + + //if mrq is being serviced by dram, gets popped after CL latency fulfilled -class mem_fetch* dram_t::return_queue_pop() +class mem_fetch* dram_t::return_queue_pop() { return returnq->pop(); } -class mem_fetch* dram_t::return_queue_top() +class mem_fetch* dram_t::return_queue_top() { return returnq->top(); } + void dram_t::print( FILE* simFile) const { unsigned i; fprintf(simFile,"DRAM[%d]: %d bks, busW=%d BL=%d CL=%d, ", id, m_config->nbk, m_config->busW, m_config->BL, m_config->CL ); fprintf(simFile,"tRRD=%d tCCD=%d, tRCD=%d tRAS=%d tRP=%d tRC=%d\n", - m_config->tCCD, m_config->tRRD, m_config->tRCD, m_config->tRAS, m_config->tRP, m_config->tRC ); - fprintf(simFile,"n_cmd=%d n_nop=%d n_act=%d n_pre=%d n_req=%d n_rd=%d n_write=%d bw_util=%.4g\n", - n_cmd, n_nop, n_act, n_pre, n_req, n_rd, n_wr, + m_config->tRRD, m_config->tCCD, m_config->tRCD, m_config->tRAS, m_config->tRP, m_config->tRC ); + fprintf(simFile,"n_cmd=%d n_nop=%d n_act=%d n_pre=%d n_ref_event=%d n_req=%d n_rd=%d n_rd_L2_A=%d n_write=%d n_wr_bk=%d bw_util=%.4g\n", + n_cmd, n_nop, n_act, n_pre, n_ref, n_req, n_rd, n_rd_L2_A, n_wr, n_wr_WB, (float)bwutil/n_cmd); fprintf(simFile,"n_activity=%d dram_eff=%.4g\n", n_activity, (float)bwutil/n_activity); for (i=0;inbk;i++) { fprintf(simFile, "bk%d: %da %di ",i,bk[i]->n_access,bk[i]->n_idle); } + fprintf(simFile, "\n"); + fprintf(simFile, "\n------------------------------------------------------------------------\n"); + + printf("\nRow_Buffer_Locality = %.6f", (float)hits_num / access_num); + printf("\nBank_Level_Parallism = %.6f", (float)banks_1time / banks_acess_total); + printf("\nBank_Level_Parallism_Col = %.6f", (float)banks_time_rw / banks_access_rw_total); + printf("\nBank_Level_Parallism_Ready = %.6f", (float)banks_time_ready /banks_access_ready_total); + printf("\nwrite_to_read_ratio_blp_rw_average = %.6f", write_to_read_ratio_blp_rw_average /banks_access_rw_total); + printf("\nGrpLevelPara = %.6f \n", (float)bkgrp_parallsim_rw /banks_access_rw_total); + + printf("\nbwutil = %.6f \n", (float)bwutil/n_cmd); + printf("total_CMD = %d \n", n_cmd); + printf("util_bw = %d \n", util_bw); + printf("Wasted_Col = %d \n", wasted_bw_col); + printf("Wasted_Row %d \n", wasted_bw_row); + printf("Idle = %d \n\n", idle_bw); + + printf("RCDc_limit = %d \n", RCDc_limit); + printf("RCDWRc_limit = %d \n", RCDWRc_limit); + printf("WTRc_limit = %d \n", WTRc_limit); + printf("RTWc_limit = %d \n", RTWc_limit); + printf("CCDLc_limit %d \n", CCDLc_limit); + printf("rwq = %d \n", rwq_limit); + printf("CCDLc_limit_alone = %d \n", CCDLc_limit_alone); + printf("WTRc_limit_alone = %d \n", WTRc_limit_alone); + printf("RTWc_limit_alone = %d \n", RTWc_limit_alone); + + printf("total_CMD = %d \n", n_cmd); + printf("n_nop = %d \n", n_nop); + printf("Read = %d \n", n_rd); + printf("Write = %d \n",n_wr); + printf("L2_Alloc = %d \n", n_rd_L2_A); + printf("L2_WB = %d \n", n_wr_WB); + printf("n_act = %d \n", n_act); + printf("n_pre = %d \n", n_pre); + printf("n_ref = %d \n", n_ref); + printf("n_req = %d \n", n_req ); + printf("n_req4 = %d \n", n_req*4 ); + printf("total_req = %d \n\n", n_rd+n_wr+n_rd_L2_A+n_wr_WB); + + printf("issued_total_row = %lu \n", issued_total_row); + printf("issued_total_col = %lu \n", issued_total_col); + printf("Row_Bus_Util = %.6f \n", (float)issued_total_row / n_cmd); + printf("CoL_Bus_Util = %.6f \n", (float)issued_total_col / n_cmd); + printf("Either_Row_CoL_Bus_Util %.6f \n", (float)issued_total / n_cmd); + printf("Issued_on_Two_Bus_Simul_Util %.6f \n", (float)issued_two /n_cmd); + printf("issued_two_Eff = %.6f \n", (float)issued_two /issued_total); + printf("queue_avg = %.6f \n\n", (float)ave_mrqs/n_cmd ); + fprintf(simFile, "\n"); fprintf(simFile, "dram_util_bins:"); for (i=0;i<10;i++) fprintf(simFile, " %d", dram_util_bins[i]); fprintf(simFile, "\ndram_eff_bins:"); for (i=0;i<10;i++) fprintf(simFile, " %d", dram_eff_bins[i]); fprintf(simFile, "\n"); - if(m_config->scheduler_type== DRAM_FRFCFS) + if(m_config->scheduler_type== DRAM_FRFCFS) fprintf(simFile, "mrqq: max=%d avg=%g\n", max_mrqs, (float)ave_mrqs/n_cmd); } @@ -476,8 +779,8 @@ void dram_t::visualize() const void dram_t::print_stat( FILE* simFile ) { - fprintf(simFile,"DRAM (%d): n_cmd=%d n_nop=%d n_act=%d n_pre=%d n_req=%d n_rd=%d n_write=%d bw_util=%.4g ", - id, n_cmd, n_nop, n_act, n_pre, n_req, n_rd, n_wr, + fprintf(simFile,"DRAM (%d): n_cmd=%d n_nop=%d n_act=%d n_pre=%d n_ref=%d n_req=%d n_rd=%d n_write=%d bw_util=%.4g ", + id, n_cmd, n_nop, n_act, n_pre, n_ref, n_req, n_rd, n_wr, (float)bwutil/n_cmd); fprintf(simFile, "mrqq: %d %.4g mrqsmax=%d ", max_mrqs, (float)ave_mrqs/n_cmd, max_mrqs_temp); fprintf(simFile, "\n"); @@ -516,6 +819,7 @@ void dram_t::visualizer_print( gzFile visualizer_file ) n_pre_partial = 0; n_req_partial = 0; + // dram access type classification for (unsigned j = 0; j < m_config->nbk; j++) { gzprintf(visualizer_file,"dramglobal_acc_r: %u %u %u\n", id, j, @@ -553,3 +857,16 @@ void dram_t::set_dram_power_stats( unsigned &cmd, wr = n_wr; req = n_req; } + +unsigned dram_t::get_bankgrp_number(unsigned i) +{ + if(m_config->dram_bnkgrp_indexing_policy == 0) { //higher bits + return i>>m_config->bk_tag_length; + } + else if (m_config->dram_bnkgrp_indexing_policy == 1) { //lower bits + return i&((m_config->nbkgrp-1)); + } + else { + assert(1); + } +} diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index a8bff14..0ec5166 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -31,9 +31,15 @@ #include "delayqueue.h" #include +#include +#include +#include +#include +#include #include #include #include +#include #define READ 'R' //define read and write states #define WRITE 'W' @@ -42,7 +48,7 @@ class dram_req_t { public: - dram_req_t( class mem_fetch *data ); + dram_req_t( class mem_fetch *data , unsigned banks, unsigned dram_bnk_indexing_policy); unsigned int row; unsigned int col; @@ -106,6 +112,7 @@ public: class mem_fetch* return_queue_pop(); class mem_fetch* return_queue_top(); + void push( class mem_fetch *data ); void cycle(); void dram_log (int task); @@ -123,17 +130,24 @@ public: unsigned &wr, unsigned &req) const; -private: - void scheduler_fifo(); - void scheduler_frfcfs(); + const struct memory_config *m_config; +private: bankgrp_t **bkgrp; bank_t **bk; unsigned int prio; + unsigned get_bankgrp_number(unsigned i); + + void scheduler_fifo(); + void scheduler_frfcfs(); + + bool issue_col_command(int j); + bool issue_row_command(int j); + unsigned int RRDc; unsigned int CCDc; unsigned int RTWc; //read to write penalty applies across banks @@ -146,7 +160,7 @@ private: fifo_pipeline *rwq; fifo_pipeline *mrqq; //buffer to hold packets when DRAM processing is over - //should be filled with dram clock and popped with l2or icnt clock + //should be filled with dram clock and popped with l2or icnt clock fifo_pipeline *returnq; unsigned int dram_util_bins[10]; @@ -158,11 +172,46 @@ private: unsigned int n_nop; unsigned int n_act; unsigned int n_pre; + unsigned int n_ref; unsigned int n_rd; + unsigned int n_rd_L2_A; unsigned int n_wr; + unsigned int n_wr_WB; unsigned int n_req; unsigned int max_mrqs_temp; + unsigned wasted_bw_row; + unsigned wasted_bw_col; + unsigned util_bw; + unsigned idle_bw; + unsigned RCDc_limit; + unsigned CCDLc_limit; + unsigned CCDLc_limit_alone; + unsigned CCDc_limit; + unsigned WTRc_limit; + unsigned WTRc_limit_alone; + unsigned RCDWRc_limit; + unsigned RTWc_limit; + unsigned RTWc_limit_alone; + unsigned rwq_limit; + + //row locality, BLP and other statistics + unsigned long access_num; + unsigned long long hits_num; + unsigned long long banks_1time; + unsigned long long banks_acess_total; + unsigned long long banks_acess_total_after; + unsigned long long banks_time_rw; + unsigned long long banks_access_rw_total; + unsigned long long banks_time_ready; + unsigned long long banks_access_ready_total; + unsigned long long issued_two; + unsigned long long issued_total; + unsigned long long issued_total_row; + unsigned long long issued_total_col; + double write_to_read_ratio_blp_rw_average; + unsigned long long bkgrp_parallsim_rw; + unsigned int bwutil; unsigned int max_mrqs; unsigned int ave_mrqs; diff --git a/src/gpgpu-sim/dram_sched.cc b/src/gpgpu-sim/dram_sched.cc index 8303e86..008b5bb 100644 --- a/src/gpgpu-sim/dram_sched.cc +++ b/src/gpgpu-sim/dram_sched.cc @@ -78,6 +78,9 @@ void frfcfs_scheduler::data_collection(unsigned int bank) dram_req_t *frfcfs_scheduler::schedule( unsigned bank, unsigned curr_row ) { + //row + bool rowhit = true; + if ( m_last_row[bank] == NULL ) { if ( m_queue[bank].empty() ) return NULL; @@ -89,11 +92,17 @@ dram_req_t *frfcfs_scheduler::schedule( unsigned bank, unsigned curr_row ) assert( bin_ptr != m_bins[bank].end() ); // where did the request go??? m_last_row[bank] = &(bin_ptr->second); data_collection(bank); + rowhit = false; } else { m_last_row[bank] = &(bin_ptr->second); - + rowhit = true; } } + //rowblp + m_dram->access_num++; + if(rowhit) + m_dram->hits_num++; + std::list::iterator next = m_last_row[bank]->back(); dram_req_t *req = (*next); diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 483a7b6..8a69847 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -192,6 +192,15 @@ void memory_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-dram_latency", OPT_UINT32, &dram_latency, "DRAM latency (default 30)", "30"); + option_parser_register(opp, "-dual_bus_interface", OPT_UINT32, &dual_bus_interface, + "dual_bus_interface", + "0"); + option_parser_register(opp, "-dram_bnk_indexing_policy", OPT_UINT32, &dram_bnk_indexing_policy, + "dram_bnk_indexing_policy", + "0"); + option_parser_register(opp, "-dram_bnkgrp_indexing_policy", OPT_UINT32, &dram_bnkgrp_indexing_policy, + "dram_bnkgrp_indexing_policy", + "0"); m_address_mapping.addrdec_setoption(opp); } diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 7d92c66..f379a17 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -270,6 +270,10 @@ struct memory_config { linear_to_raw_address_translation m_address_mapping; unsigned icnt_flit_size; + + unsigned dram_bnk_indexing_policy; + unsigned dram_bnkgrp_indexing_policy; + bool dual_bus_interface; }; // global counters and flags (please try not to add to this list!!!) -- cgit v1.3 From bd45b8f49f35827dfaa7b5273dda85f0c442fe13 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 13 Sep 2017 09:47:38 -0400 Subject: Fixing some typos --- src/gpgpu-sim/dram.cc | 39 ++++++++++++++++++++++----------------- src/gpgpu-sim/dram.h | 1 + 2 files changed, 23 insertions(+), 17 deletions(-) diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index 352bd58..dcc0a7d 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -304,29 +304,29 @@ void dram_t::cycle() //collect row buffer locality, BLP and other statistics ///////////////////////////////////////////////////////////////////////// - unsigned int memory_Pending=0; + unsigned int memory_pending=0; for (unsigned i=0;inbk;i++) { if (bk[i]->mrq) - memory_Pending++; + memory_pending++; } - banks_1time += memory_Pending; - if(memory_Pending >0) + banks_1time += memory_pending; + if(memory_pending >0) banks_acess_total++; unsigned int memory_pending_rw=0; - unsigned read_BLP_RW=0; - unsigned write_BLP_RW=0; - std::bitset<8> bnkgrp_RW_found; - //bool memory_pending_rw_found=false; - for (unsigned j=0;jnbk;j++) { + unsigned read_blp_rw=0; + unsigned write_blp_rw=0; + std::bitset<8> bnkgrp_rw_found; //assume max we have 8 bank groups + + for (unsigned j=0;jnbk;j++) { unsigned grp = get_bankgrp_number(j); if (bk[j]->mrq && (((bk[j]->curr_row == bk[j]->mrq->row) && (bk[j]->mrq->rw == READ) && (bk[j]->state == BANK_ACTIVE)))) { memory_pending_rw++; - read_BLP_RW++; - bnkgrp_RW_found.set(grp); + read_blp_rw++; + bnkgrp_rw_found.set(grp); } else if (bk[j]->mrq && (((bk[j]->curr_row == bk[j]->mrq->row) && @@ -334,15 +334,15 @@ void dram_t::cycle() (bk[j]->state == BANK_ACTIVE)))) { memory_pending_rw++; - write_BLP_RW++; - bnkgrp_RW_found.set(grp); + write_blp_rw++; + bnkgrp_rw_found.set(grp); } } banks_time_rw += memory_pending_rw; - bkgrp_parallsim_rw += bnkgrp_RW_found.count(); + bkgrp_parallsim_rw += bnkgrp_rw_found.count(); if(memory_pending_rw >0) { - write_to_read_ratio_blp_rw_average += (double)write_BLP_RW/(write_BLP_RW+read_BLP_RW); + write_to_read_ratio_blp_rw_average += (double)write_blp_rw/(write_blp_rw+read_blp_rw); banks_access_rw_total++; } @@ -441,6 +441,10 @@ void dram_t::cycle() if(issued_col_cmd) issued_total_col++; if(issued_row_cmd) issued_total_row++; + + //Collect some statistics + //check the limitation, see where BW is wasted? + ///////////////////////////////////////////////////////// unsigned int memory_pending_found=0; for (unsigned i=0;inbk;i++) { if (bk[i]->mrq) @@ -463,8 +467,7 @@ void dram_t::cycle() memory_pending_rw_found=true; } - //Collect some statistics - //check the limitation, why BW is wasted? + if(issued_col_cmd || CCDc) util_bw++; else if (memory_pending_rw_found) @@ -507,6 +510,8 @@ void dram_t::cycle() else assert(1); + ///////////////////////////////////////////////////////// + // decrements counters once for each time dram_issueCMD is called DEC2ZERO(RRDc); DEC2ZERO(CCDc); diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index 0ec5166..331b4f1 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -180,6 +180,7 @@ private: unsigned int n_req; unsigned int max_mrqs_temp; + //some statistics to collect to see where BW is wasted? unsigned wasted_bw_row; unsigned wasted_bw_col; unsigned util_bw; -- cgit v1.3 From 355de7f8d033a4b5082cb0816650d880f05d81c8 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 13 Sep 2017 16:03:39 -0400 Subject: Adding sperate dp_unit --- configs/GTX480/gpgpusim.config | 6 ++- configs/GeForceGTX750Ti/gpgpusim.config | 5 ++- configs/QuadroFX5600/gpgpusim.config | 5 ++- configs/QuadroFX5800/gpgpusim.config | 5 ++- configs/TeslaC2050/gpgpusim.config | 3 +- src/abstract_hardware_model.h | 2 + src/cuda-sim/cuda-sim.cc | 5 ++- src/gpgpu-sim/gpu-sim.cc | 12 ++++++ src/gpgpu-sim/shader.cc | 70 +++++++++++++++++++++++++++++---- src/gpgpu-sim/shader.h | 41 ++++++++++++++++--- 10 files changed, 132 insertions(+), 22 deletions(-) diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config index 436cb41..7d8d91e 100644 --- a/configs/GTX480/gpgpusim.config +++ b/configs/GTX480/gpgpusim.config @@ -29,10 +29,12 @@ -gpgpu_simd_model 1 # Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 2,1,1,2,1,1,2 +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +#For Fermi, DP unit =0, DP inst is executed on SFU unit instead +-gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 -gpgpu_num_sp_units 2 -gpgpu_num_sfu_units 1 +-gpgpu_num_dp_units 0 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index 8b030b6..bd6412c 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -28,10 +28,11 @@ -gpgpu_simd_model 1 # Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 2,1,1,2,1,1,2 +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 -gpgpu_num_sp_units 8 -gpgpu_num_sfu_units 32 +-gpgpu_num_dp_units 0 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" diff --git a/configs/QuadroFX5600/gpgpusim.config b/configs/QuadroFX5600/gpgpusim.config index cb87b65..82dc64a 100644 --- a/configs/QuadroFX5600/gpgpusim.config +++ b/configs/QuadroFX5600/gpgpusim.config @@ -17,10 +17,11 @@ -gpgpu_simd_model 1 # Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 1,1,1,1,1,1,1 +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 1,0,1,1,1,0,1,1,1 -gpgpu_num_sp_units 1 -gpgpu_num_sfu_units 1 +-gpgpu_num_dp_units 0 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index 82243c2..fdd87e0 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -16,10 +16,11 @@ -gpgpu_simd_model 1 # Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 1,1,1,1,1,1,1 +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 1,0,1,1,1,0,1,1,1 -gpgpu_num_sp_units 1 -gpgpu_num_sfu_units 1 +-gpgpu_num_dp_units 0 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config index 442ab8b..4febbe5 100644 --- a/configs/TeslaC2050/gpgpusim.config +++ b/configs/TeslaC2050/gpgpusim.config @@ -33,9 +33,10 @@ # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 2,1,1,2,1,1,2 +-gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 -gpgpu_num_sp_units 2 -gpgpu_num_sfu_units 1 +-gpgpu_num_sfu_units 0 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 910a9ed..7d7773c 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -76,6 +76,7 @@ enum uarch_op_t { NO_OP=-1, ALU_OP=1, SFU_OP, + DP_OP, ALU_SFU_OP, LOAD_OP, STORE_OP, @@ -131,6 +132,7 @@ typedef enum special_operations_t special_ops; // Required to identify for the p enum operation_pipeline_t { UNKOWN_OP, SP__OP, + DP__OP, SFU__OP, MEM__OP }; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index d4ace76..c7c32fa 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -678,6 +678,7 @@ void ptx_instruction::set_opcode_and_latency() case FF64_TYPE: latency = dp_latency[0]; initiation_interval = dp_init[0]; + op = DP_OP; break; case B32_TYPE: case U32_TYPE: @@ -699,6 +700,7 @@ void ptx_instruction::set_opcode_and_latency() case FF64_TYPE: latency = dp_latency[1]; initiation_interval = dp_init[1]; + op = DP_OP; break; case B32_TYPE: case U32_TYPE: @@ -721,7 +723,7 @@ void ptx_instruction::set_opcode_and_latency() case FF64_TYPE: latency = dp_latency[2]; initiation_interval = dp_init[2]; - op = ALU_SFU_OP; + op = DP_OP; break; case B32_TYPE: case U32_TYPE: @@ -744,6 +746,7 @@ void ptx_instruction::set_opcode_and_latency() case FF64_TYPE: latency = dp_latency[3]; initiation_interval = dp_init[3]; + op = DP_OP; break; case B32_TYPE: case U32_TYPE: diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 8a69847..c5930fc 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -321,6 +321,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_operand_collector_num_units_sp", OPT_INT32, &gpgpu_operand_collector_num_units_sp, "number of collector units (default = 4)", "4"); + option_parser_register(opp, "-gpgpu_operand_collector_num_units_dp", OPT_INT32, &gpgpu_operand_collector_num_units_dp, + "number of collector units (default = 0)", + "0"); option_parser_register(opp, "-gpgpu_operand_collector_num_units_sfu", OPT_INT32, &gpgpu_operand_collector_num_units_sfu, "number of collector units (default = 4)", "4"); @@ -333,6 +336,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_sp", OPT_INT32, &gpgpu_operand_collector_num_in_ports_sp, "number of collector unit in ports (default = 1)", "1"); + option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_dp", OPT_INT32, &gpgpu_operand_collector_num_in_ports_dp, + "number of collector unit in ports (default = 0)", + "0"); option_parser_register(opp, "-gpgpu_operand_collector_num_in_ports_sfu", OPT_INT32, &gpgpu_operand_collector_num_in_ports_sfu, "number of collector unit in ports (default = 1)", "1"); @@ -345,6 +351,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_sp", OPT_INT32, &gpgpu_operand_collector_num_out_ports_sp, "number of collector unit in ports (default = 1)", "1"); + option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_dp", OPT_INT32, &gpgpu_operand_collector_num_out_ports_dp, + "number of collector unit in ports (default = 0)", + "0"); option_parser_register(opp, "-gpgpu_operand_collector_num_out_ports_sfu", OPT_INT32, &gpgpu_operand_collector_num_out_ports_sfu, "number of collector unit in ports (default = 1)", "1"); @@ -376,6 +385,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32, &gpgpu_num_sp_units, "Number of SP units (default=1)", "1"); + option_parser_register(opp, "-gpgpu_num_dp_units", OPT_INT32, &gpgpu_num_dp_units, + "Number of DP units (default=0)", + "0"); option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_INT32, &gpgpu_num_sfu_units, "Number of SF units (default=1)", "1"); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index bb2cf0e..5547a18 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -150,6 +150,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], + &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_MEM], i @@ -164,6 +165,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], + &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_MEM], i, @@ -179,6 +181,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], + &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_MEM], i @@ -193,6 +196,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], + &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_MEM], i @@ -207,6 +211,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_simt_stack, &m_warp, &m_pipeline_reg[ID_OC_SP], + &m_pipeline_reg[ID_OC_DP], &m_pipeline_reg[ID_OC_SFU], &m_pipeline_reg[ID_OC_MEM], i, @@ -228,8 +233,9 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, } //op collector configuration - enum { SP_CUS, SFU_CUS, MEM_CUS, GEN_CUS }; + enum { SP_CUS, DP_CUS, SFU_CUS, MEM_CUS, GEN_CUS }; m_operand_collector.add_cu_set(SP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_sp); + m_operand_collector.add_cu_set(DP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_dp); m_operand_collector.add_cu_set(SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu, m_config->gpgpu_operand_collector_num_out_ports_sfu); m_operand_collector.add_cu_set(MEM_CUS, m_config->gpgpu_operand_collector_num_units_mem, m_config->gpgpu_operand_collector_num_out_ports_mem); m_operand_collector.add_cu_set(GEN_CUS, m_config->gpgpu_operand_collector_num_units_gen, m_config->gpgpu_operand_collector_num_out_ports_gen); @@ -246,6 +252,15 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, in_ports.clear(),out_ports.clear(),cu_sets.clear(); } + for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_dp; i++) { + in_ports.push_back(&m_pipeline_reg[ID_OC_DP]); + out_ports.push_back(&m_pipeline_reg[OC_EX_DP]); + cu_sets.push_back((unsigned)DP_CUS); + cu_sets.push_back((unsigned)GEN_CUS); + m_operand_collector.add_port(in_ports,out_ports,cu_sets); + in_ports.clear(),out_ports.clear(),cu_sets.clear(); + } + for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_sfu; i++) { in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]); out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]); @@ -280,7 +295,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_operand_collector.init( m_config->gpgpu_num_reg_banks, this ); // execute - m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_sfu_units + 1; // sp_unit, sfu, ldst_unit + m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_dp_units + m_config->gpgpu_num_sfu_units + 1; // sp_unit, sfu, ldst_unit //m_dispatch_port = new enum pipeline_stage_name_t[ m_num_function_units ]; //m_issue_port = new enum pipeline_stage_name_t[ m_num_function_units ]; @@ -292,12 +307,18 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, m_issue_port.push_back(OC_EX_SP); } + for (int k = 0; k < m_config->gpgpu_num_dp_units; k++) { + m_fu.push_back(new dp_unit( &m_pipeline_reg[EX_WB], m_config, this )); + m_dispatch_port.push_back(ID_OC_DP); + m_issue_port.push_back(OC_EX_DP); + } + for (int k = 0; k < m_config->gpgpu_num_sfu_units; k++) { m_fu.push_back(new sfu( &m_pipeline_reg[EX_WB], m_config, this )); m_dispatch_port.push_back(ID_OC_SFU); m_issue_port.push_back(OC_EX_SFU); } - + m_ldst_unit = new ldst_unit( m_icnt, m_mem_fetch_allocator, this, &m_operand_collector, m_scoreboard, config, mem_config, stats, shader_id, tpc_id ); m_fu.push_back(m_ldst_unit); m_dispatch_port.push_back(ID_OC_MEM); @@ -754,7 +775,7 @@ void shader_core_ctx::issue(){ unsigned j; for (unsigned i = 0; i < schedulers.size(); i++) { j = (Issue_Prio + i) % schedulers.size(); - schedulers[j]->cycle(); + schedulers[j]->cycle(); } Issue_Prio = (Issue_Prio+1)% schedulers.size(); @@ -879,6 +900,7 @@ void scheduler_unit::cycle() exec_unit_type_t previous_issued_inst_exec_type = exec_unit_type_t::NONE; unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp; bool diff_exec_units = m_shader->m_config->gpgpu_dual_issue_diff_exec_units; + while( !warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue) ) { const warp_inst_t *pI = warp(warp_id).ibuffer_next_inst(); //Jin: handle cdp latency; @@ -920,9 +942,11 @@ void scheduler_unit::cycle() previous_issued_inst_exec_type = exec_unit_type_t::MEM; } } else { + bool sp_pipe_avail = m_sp_out->has_free(); bool sfu_pipe_avail = m_sfu_out->has_free(); - if( sp_pipe_avail && (pI->op != SFU_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SP)) { + bool dp_pipe_avail = m_dp_out->has_free(); + if( sp_pipe_avail && (pI->op != SFU_OP && pI->op != DP_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SP)) { //Jin: special for CDP api if(pI->m_is_cdp && !warp(warp_id).m_cdp_dummy) { @@ -948,7 +972,17 @@ void scheduler_unit::cycle() issued_inst=true; warp_inst_issued = true; previous_issued_inst_exec_type = exec_unit_type_t::SP; - } else if ( (pI->op == SFU_OP) || (pI->op == ALU_SFU_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SFU)) { + } else if ( (m_shader->m_config->gpgpu_num_dp_units != 0) && (pI->op == DP_OP) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::DP)) { + if( dp_pipe_avail ) { + m_shader->issue_warp(*m_dp_out,pI,active_mask,warp_id); + issued++; + issued_inst=true; + warp_inst_issued = true; + previous_issued_inst_exec_type = exec_unit_type_t::DP; + std::cout<<"DP inst is issued"<m_config->gpgpu_num_dp_units == 0 && pI->op == DP_OP) || (pI->op == SFU_OP) || (pI->op == ALU_SFU_OP)) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SFU)) { if( sfu_pipe_avail ) { m_shader->issue_warp(*m_sfu_out,pI,active_mask,warp_id); issued++; @@ -1139,11 +1173,12 @@ swl_scheduler::swl_scheduler ( shader_core_stats* stats, shader_core_ctx* shader Scoreboard* scoreboard, simt_stack** simt, std::vector* warp, register_set* sp_out, + register_set* dp_out, register_set* sfu_out, register_set* mem_out, int id, char* config_string ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, mem_out, id ) + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, mem_out, id ) { unsigned m_prioritization_readin; int ret = sscanf( config_string, @@ -1588,6 +1623,13 @@ void sp_unit::active_lanes_in_pipeline(){ m_core->incfuactivelanes_stat(active_count); m_core->incfumemactivelanes_stat(active_count); } +void dp_unit::active_lanes_in_pipeline(){ + unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline(); + assert(active_count<=m_core->get_config()->warp_size); + m_core->incspactivelanes_stat(active_count); + m_core->incfuactivelanes_stat(active_count); + m_core->incfumemactivelanes_stat(active_count); +} void sfu::active_lanes_in_pipeline(){ unsigned active_count=pipelined_simd_unit::get_active_lanes_in_pipeline(); @@ -1603,6 +1645,12 @@ sp_unit::sp_unit( register_set* result_port, const shader_core_config *config,sh m_name = "SP "; } +dp_unit::dp_unit( register_set* result_port, const shader_core_config *config,shader_core_ctx *core) + : pipelined_simd_unit(result_port,config,config->max_sfu_latency,core) +{ + m_name = "DP "; +} + void sp_unit :: issue(register_set& source_reg) { warp_inst_t** ready_reg = source_reg.get_ready(); @@ -1612,6 +1660,14 @@ void sp_unit :: issue(register_set& source_reg) pipelined_simd_unit::issue(source_reg); } +void dp_unit :: issue(register_set& source_reg) +{ + warp_inst_t** ready_reg = source_reg.get_ready(); + //m_core->incexecstat((*ready_reg)); + (*ready_reg)->op_pipe=DP__OP; + m_core->incsp_stat(m_core->get_config()->warp_size,(*ready_reg)->latency); + pipelined_simd_unit::issue(source_reg); +} pipelined_simd_unit::pipelined_simd_unit( register_set* result_port, const shader_core_config *config, unsigned max_latency,shader_core_ctx *core ) : simd_function_unit(config) diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 2fed420..544d8d8 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -326,12 +326,13 @@ public: Scoreboard* scoreboard, simt_stack** simt, std::vector* warp, register_set* sp_out, + register_set* dp_out, register_set* sfu_out, register_set* mem_out, int id) : m_supervised_warps(), m_stats(stats), m_shader(shader), m_scoreboard(scoreboard), m_simt_stack(simt), /*m_pipeline_reg(pipe_regs),*/ m_warp(warp), - m_sp_out(sp_out),m_sfu_out(sfu_out),m_mem_out(mem_out), m_id(id){} + m_sp_out(sp_out),m_dp_out(dp_out),m_sfu_out(sfu_out),m_mem_out(mem_out), m_id(id){} virtual ~scheduler_unit(){} virtual void add_supervised_warp_id(int i) { m_supervised_warps.push_back(&warp(i)); @@ -403,6 +404,7 @@ protected: //warp_inst_t** m_pipeline_reg; std::vector* m_warp; register_set* m_sp_out; + register_set* m_dp_out; register_set* m_sfu_out; register_set* m_mem_out; @@ -415,10 +417,11 @@ public: Scoreboard* scoreboard, simt_stack** simt, std::vector* warp, register_set* sp_out, + register_set* dp_out, register_set* sfu_out, register_set* mem_out, int id ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, mem_out, id ){} + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, mem_out, id ){} virtual ~lrr_scheduler () {} virtual void order_warps (); virtual void done_adding_supervised_warps() { @@ -432,10 +435,11 @@ public: Scoreboard* scoreboard, simt_stack** simt, std::vector* warp, register_set* sp_out, + register_set* dp_out, register_set* sfu_out, register_set* mem_out, int id ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, mem_out, id ){} + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, mem_out, id ){} virtual ~gto_scheduler () {} virtual void order_warps (); virtual void done_adding_supervised_warps() { @@ -450,10 +454,11 @@ public: Scoreboard* scoreboard, simt_stack** simt, std::vector* warp, register_set* sp_out, + register_set* dp_out, register_set* sfu_out, register_set* mem_out, int id ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, mem_out, id ){} + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, mem_out, id ){} virtual ~oldest_scheduler () {} virtual void order_warps (); virtual void done_adding_supervised_warps() { @@ -468,11 +473,12 @@ public: Scoreboard* scoreboard, simt_stack** simt, std::vector* warp, register_set* sp_out, + register_set* dp_out, register_set* sfu_out, register_set* mem_out, int id, char* config_str ) - : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, sfu_out, mem_out, id ), + : scheduler_unit ( stats, shader, scoreboard, simt, warp, sp_out, dp_out, sfu_out, mem_out, id ), m_pending_warps() { unsigned inner_level_readin; @@ -518,6 +524,7 @@ public: Scoreboard* scoreboard, simt_stack** simt, std::vector* warp, register_set* sp_out, + register_set* dp_out, register_set* sfu_out, register_set* mem_out, int id, @@ -1088,6 +1095,22 @@ public: virtual void issue( register_set& source_reg ); }; +class dp_unit : public pipelined_simd_unit +{ +public: + dp_unit( register_set* result_port, const shader_core_config *config, shader_core_ctx *core ); + virtual bool can_issue( const warp_inst_t &inst ) const + { + switch(inst.op) { + case DP_OP: break; + default: return false; + } + return pipelined_simd_unit::can_issue(inst); + } + virtual void active_lanes_in_pipeline(); + virtual void issue( register_set& source_reg ); +}; + class sp_unit : public pipelined_simd_unit { public: @@ -1226,9 +1249,11 @@ protected: enum pipeline_stage_name_t { ID_OC_SP=0, + ID_OC_DP, ID_OC_SFU, ID_OC_MEM, OC_EX_SP, + OC_EX_DP, OC_EX_SFU, OC_EX_MEM, EX_WB, @@ -1237,9 +1262,11 @@ enum pipeline_stage_name_t { const char* const pipeline_stage_name_decode[] = { "ID_OC_SP", + "ID_OC_DP", "ID_OC_SFU", "ID_OC_MEM", "OC_EX_SP", + "OC_EX_DP", "OC_EX_SFU", "OC_EX_MEM", "EX_WB", @@ -1328,21 +1355,25 @@ struct shader_core_config : public core_config //op collector int gpgpu_operand_collector_num_units_sp; + int gpgpu_operand_collector_num_units_dp; int gpgpu_operand_collector_num_units_sfu; int gpgpu_operand_collector_num_units_mem; int gpgpu_operand_collector_num_units_gen; unsigned int gpgpu_operand_collector_num_in_ports_sp; + unsigned int gpgpu_operand_collector_num_in_ports_dp; unsigned int gpgpu_operand_collector_num_in_ports_sfu; unsigned int gpgpu_operand_collector_num_in_ports_mem; unsigned int gpgpu_operand_collector_num_in_ports_gen; unsigned int gpgpu_operand_collector_num_out_ports_sp; + unsigned int gpgpu_operand_collector_num_out_ports_dp; unsigned int gpgpu_operand_collector_num_out_ports_sfu; unsigned int gpgpu_operand_collector_num_out_ports_mem; unsigned int gpgpu_operand_collector_num_out_ports_gen; int gpgpu_num_sp_units; + int gpgpu_num_dp_units; int gpgpu_num_sfu_units; int gpgpu_num_mem_units; -- cgit v1.3 From 1623ca1036356a8a50fa7e0b504f0f67df054e5c Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 14 Sep 2017 10:28:40 -0400 Subject: adding seperate sfu latency and init variables --- src/cuda-sim/cuda-sim.cc | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index c7c32fa..48d1219 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -62,8 +62,8 @@ addr_t g_debug_pc = 0xBEEF1518; unsigned g_ptx_sim_num_insn = 0; unsigned gpgpu_param_num_shaders = 0; -char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp; -char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp; +char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp,*opcode_latency_sfu; +char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp,*opcode_initiation_sfu; char *cdp_latency_str; unsigned cdp_latency[5]; @@ -80,6 +80,10 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Opcode latencies for double precision floating points " "Default 8,8,8,8,335", "8,8,8,8,335"); + option_parser_register(opp, "-opcode_latency_sfu", OPT_CSTR, &opcode_latency_sfu, + "Opcode latencies for SFU instructions" + "Default 8", + "8"); option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, "Opcode initiation intervals for integers " "Default 1,1,4,4,32", @@ -92,6 +96,10 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Opcode initiation intervals for double precision floating points " "Default 8,8,8,8,130", "8,8,8,8,130"); + option_parser_register(opp, "-ptx_opcode_initiation_sfu", OPT_CSTR, &opcode_initiation_sfu, + "Opcode initiation intervals for sfu instructions" + "Default 8", + "8"); option_parser_register(opp, "-cdp_latency", OPT_CSTR, &cdp_latency_str, "CDP API latency Date: Thu, 14 Sep 2017 10:53:43 -0400 Subject: fixing jenkins file --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index dfe2d1c..d6d3618 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -14,7 +14,7 @@ pipeline { }, "8.0" : { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment &&\ - make -j' + make -j -C -f Makefile.PTX5' } } } @@ -33,7 +33,7 @@ pipeline { source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src all' + make -j -f Makefile.PTX5 ./benchmarks/src all' } } stage('rodinia-regress'){ -- cgit v1.3 From 4d299b2fe8a2511cc6fba9e2d883249de9e0da74 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 14 Sep 2017 10:56:21 -0400 Subject: fixing jenkinsfile 2 --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index d6d3618..526c45f 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -14,7 +14,7 @@ pipeline { }, "8.0" : { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment &&\ - make -j -C -f Makefile.PTX5' + make -j -f Makefile.PTX5' } } } -- cgit v1.3 From 375533963bef3d528ba3c8527ae786bc12f024cd Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 14 Sep 2017 11:45:21 -0400 Subject: fixing jenkinsfile 3 --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 526c45f..6e180a2 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -14,7 +14,7 @@ pipeline { }, "8.0" : { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment &&\ - make -j -f Makefile.PTX5' + make -j' } } } @@ -33,7 +33,7 @@ pipeline { source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -f Makefile.PTX5 ./benchmarks/src all' + make -j -f Makefile.PTX./benchmarks/src all' } } stage('rodinia-regress'){ -- cgit v1.3 From 466bf0037b79a4ad4e1ce12aba011143b820eb81 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Thu, 14 Sep 2017 11:47:24 -0400 Subject: Update Jenkinsfile --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 6e180a2..3a716b4 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -33,7 +33,7 @@ pipeline { source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -f Makefile.PTX./benchmarks/src all' + make -j -f Makefile.PTX5 ./benchmarks/src all' } } stage('rodinia-regress'){ -- cgit v1.3 From cc8ee38f16569846c344e1ad511bb8de57506f8b Mon Sep 17 00:00:00 2001 From: tgrogers Date: Thu, 14 Sep 2017 13:32:50 -0400 Subject: Adding Mahmoud's Jenkisfile changes --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index dfe2d1c..3a716b4 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -33,7 +33,7 @@ pipeline { source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src all' + make -j -f Makefile.PTX5 ./benchmarks/src all' } } stage('rodinia-regress'){ -- cgit v1.3 From f9ffcb4a6932eb8484d8f9be81ba5653429c3f63 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Thu, 14 Sep 2017 13:45:34 -0400 Subject: Fixing the make command --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 3a716b4..de37bb4 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -33,7 +33,7 @@ pipeline { source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -f Makefile.PTX5 ./benchmarks/src all' + make -j -f Makefile.PTX5 -C ./benchmarks/src/ all' } } stage('rodinia-regress'){ -- cgit v1.3 From a4d5a911660629713f8fa87272f7abadcf6676d2 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Thu, 14 Sep 2017 13:54:42 -0400 Subject: Getting rid of -j since it is making the build output harder to read --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index de37bb4..289fef4 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -28,12 +28,12 @@ pipeline { source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src all' + make -C ./benchmarks/src all' sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -f Makefile.PTX5 -C ./benchmarks/src/ all' + make -f Makefile.PTX5 -C ./benchmarks/src/ all' } } stage('rodinia-regress'){ -- cgit v1.3 From a60c4f9f35850195ec353b3a95d9215288996b8b Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 14 Sep 2017 20:15:27 -0400 Subject: changing the DRAM bank indexing policy --- src/gpgpu-sim/dram.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index dcc0a7d..5c1ddab 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -189,11 +189,12 @@ dram_req_t::dram_req_t( class mem_fetch *mf, unsigned banks, unsigned dram_bnk_i const addrdec_t &tlx = mf->get_tlx_addr(); if(dram_bnk_indexing_policy == 0) { - int lbank = log2(banks); - bk = tlx.bk ^ (((1< Date: Thu, 14 Sep 2017 20:18:59 -0400 Subject: adding some condig comments --- src/gpgpu-sim/gpu-sim.cc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index c5930fc..b424d2c 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -193,13 +193,13 @@ void memory_config::reg_options(class OptionParser * opp) "DRAM latency (default 30)", "30"); option_parser_register(opp, "-dual_bus_interface", OPT_UINT32, &dual_bus_interface, - "dual_bus_interface", + "dual_bus_interface (default = 0) ", "0"); option_parser_register(opp, "-dram_bnk_indexing_policy", OPT_UINT32, &dram_bnk_indexing_policy, - "dram_bnk_indexing_policy", + "dram_bnk_indexing_policy (0 = normal indexing, 1 = Xoring with the higher bits) (Default = 0)", "0"); option_parser_register(opp, "-dram_bnkgrp_indexing_policy", OPT_UINT32, &dram_bnkgrp_indexing_policy, - "dram_bnkgrp_indexing_policy", + "dram_bnkgrp_indexing_policy (0 = take higher bits, 1 = take lower bits) (Default = 0)", "0"); m_address_mapping.addrdec_setoption(opp); @@ -373,15 +373,15 @@ void shader_core_config::reg_options(class OptionParser * opp) "Max number of instructions that can be issued per warp in one cycle by scheduler (either 1 or 2)", "2"); option_parser_register(opp, "-gpgpu_dual_issue_diff_exec_units", OPT_BOOL, &gpgpu_dual_issue_diff_exec_units, - "should dual issue use two different execution unit resources", + "should dual issue use two different execution unit resources (Default = 1)", "1"); option_parser_register(opp, "-gpgpu_simt_core_sim_order", OPT_INT32, &simt_core_sim_order, "Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin)", "1"); option_parser_register(opp, "-gpgpu_pipeline_widths", OPT_CSTR, &pipeline_widths_string, "Pipeline widths " - "ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB", - "1,1,1,1,1,1,1" ); + "ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB", + "1,1,1,1,1,1,1,1,1" ); option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32, &gpgpu_num_sp_units, "Number of SP units (default=1)", "1"); -- cgit v1.3 From 5b9e91d9b2b5d017a196eb4e02cc7215ec48f692 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 14 Sep 2017 20:19:49 -0400 Subject: Adding Pascal config files --- configs/Pascal-P100-HBM/config_fermi_islip.icnt | 70 +++++++++ configs/Pascal-P100-HBM/gpgpusim.config | 168 +++++++++++++++++++++ configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt | 70 +++++++++ configs/Pascal-P102-GDDR5X/gpgpusim.config | 162 ++++++++++++++++++++ 4 files changed, 470 insertions(+) create mode 100644 configs/Pascal-P100-HBM/config_fermi_islip.icnt create mode 100644 configs/Pascal-P100-HBM/gpgpusim.config create mode 100644 configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt create mode 100644 configs/Pascal-P102-GDDR5X/gpgpusim.config diff --git a/configs/Pascal-P100-HBM/config_fermi_islip.icnt b/configs/Pascal-P100-HBM/config_fermi_islip.icnt new file mode 100644 index 0000000..a788090 --- /dev/null +++ b/configs/Pascal-P100-HBM/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 62; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config new file mode 100644 index 0000000..18aa82a --- /dev/null +++ b/configs/Pascal-P100-HBM/gpgpusim.config @@ -0,0 +1,168 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 60 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 32 +-gpgpu_n_sub_partition_per_mchannel 1 + +# Pscal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA GP100 clock domains are adopted from +# https://en.wikipedia.org/wiki/Nvidia_Tesla +-gpgpu_clock_domains 1480.0:2960.0:1480.0:715.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 2,2,2,1,2,2,2,1,6 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 2 +-gpgpu_num_dp_units 2 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 2,2,2,2,130 +-ptx_opcode_latency_sfu 8 +-ptx_opcode_initiation_sfu 4 + + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP100 has 64KB Shared memory +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_shmem_size 65536 +-gmem_skip_L1D 0 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 4MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 +# gpgpu_num_reg_banks should be increased to 32 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +# Use Fermi Coalsce arhitetecture which is the same as Pascal +-gpgpu_coalesce_arch 20 + +## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units +-gpgpu_max_insn_issue_per_warp 2 +-gpgpu_dual_issue_diff_exec_units 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +# DRAM latency should be lower compared to other configs, due to high-speed interposer connection +-dram_latency 60 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for HBM, 32 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS + +# GDDR5 timing +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=6:RCD=12:RAS=28:RP=12:RC=40: +# CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: + CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" + +# HBM has dual bus interface, in which it can issue two col and row commands at a time +-dual_bus_interface 1 +# select lower bits for bnkgrp to increase bnkgrp parallelism +-dram_bnkgrp_indexing_policy 1 + +# Pascal has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Pascal 100 +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt new file mode 100644 index 0000000..602daee --- /dev/null +++ b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 52; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config new file mode 100644 index 0000000..4400454 --- /dev/null +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -0,0 +1,162 @@ +# This config models the Pascal GP102 (NVIDIA TITAN X) +# For more info about this card, see Nvidia White paper +# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 61 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 12 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1417.0:2834.0:1417.0:2500.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,1,1,1,4,1,1,1,6 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 +-gpgpu_num_dp_units 1 + + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,8,8,8,130 +-ptx_opcode_latency_sfu 8 +-ptx_opcode_initiation_sfu 4 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The defulat is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_shmem_size 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 +# gpgpu_num_reg_banks should be increased to 32 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +# Use Fermi Coalsce arhitetecture which is the same as Pascal +-gpgpu_coalesce_arch 20 + +## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units +-gpgpu_max_insn_issue_per_warp 2 +-gpgpu_dual_issue_diff_exec_units 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) +# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# Pascal 102 has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Pascal 102 +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + -- cgit v1.3 From 0751c1489add70d7494521c7f9d65f462e4391c6 Mon Sep 17 00:00:00 2001 From: speverel Date: Sun, 24 Sep 2017 21:12:40 -0700 Subject: Changed how warp level instructions are handled to avoid an assert that is guaranteed to fail in functional simulation only mode. Hopefully this shouldn't introduce any new issues. --- src/abstract_hardware_model.h | 4 ++++ src/cuda-sim/instructions.cc | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 607eda7..cdd9cf3 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -980,6 +980,10 @@ public: assert( !m_empty ); return m_warp_id; } + unsigned warp_id_func() const // to be used in functional simulations only + { + return m_warp_id; + } unsigned dynamic_warp_id() const { assert( !m_empty ); diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 159fd4c..493e307 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1500,7 +1500,7 @@ void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) const operand_info &src1 = pI->src1(); const operand_info &src2 = pI->src2(); unsigned type = pI->get_type(); - int tid = inst.warp_id() * core->get_warp_size(); + int tid = inst.warp_id_func() * core->get_warp_size(); ptx_thread_info *thread = core->get_thread_info()[tid]; const int ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; const int op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; @@ -3698,7 +3698,7 @@ void set_impl( const ptx_instruction *pI, ptx_thread_info *thread ) void shfl_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { unsigned i_type = pI->get_type(); - int tid = inst.warp_id() * core->get_warp_size(); + int tid = inst.warp_id_func() * core->get_warp_size(); ptx_thread_info *thread = core->get_thread_info()[tid]; ptx_warp_info *warp_info = thread->m_warp_info; int lane = warp_info->get_done_threads(); -- cgit v1.3 From eb85a913d5f6d3ef152cd3024ea0e59f3b177423 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 1 Oct 2017 14:22:42 -0400 Subject: properly pulling the latest changes to the simulations dir to get updated results. --- Jenkinsfile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 289fef4..387aaa8 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -23,7 +23,8 @@ pipeline { sh 'rm -rf gpgpu-sim_simulations' sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ cd gpgpu-sim_simulations && \ - git checkout purdue-cluster' + git checkout purdue-cluster && \ + git pull' sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ -- cgit v1.3 From cd7ae9179812d114dc1ad5383482a6dd6a5c7479 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 1 Oct 2017 15:24:33 -0400 Subject: calling out the running of rodinia --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 387aaa8..a670e18 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -42,7 +42,7 @@ pipeline { parallel "4.2-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/benchmarks.yml -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "8.0-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ -- cgit v1.3 From e85478986a2df02ece9d8d0e6faa44ba9f8ca3e8 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 1 Oct 2017 22:04:46 -0400 Subject: Making sure we are using the right config yaml --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index a670e18..3ea1bcd 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -42,7 +42,7 @@ pipeline { parallel "4.2-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/benchmarks.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/benchmarks.yml -c ./gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.yml -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "8.0-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ -- cgit v1.3 From 472878e74255acf1c44fc1a50d886cc754078b53 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Wed, 11 Oct 2017 18:58:51 -0400 Subject: Fixing deadlock because of dp_unit --- src/gpgpu-sim/shader.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 5547a18..a654a06 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -235,7 +235,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, //op collector configuration enum { SP_CUS, DP_CUS, SFU_CUS, MEM_CUS, GEN_CUS }; m_operand_collector.add_cu_set(SP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_sp); - m_operand_collector.add_cu_set(DP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_dp); + m_operand_collector.add_cu_set(DP_CUS, m_config->gpgpu_operand_collector_num_units_dp, m_config->gpgpu_operand_collector_num_out_ports_dp); m_operand_collector.add_cu_set(SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu, m_config->gpgpu_operand_collector_num_out_ports_sfu); m_operand_collector.add_cu_set(MEM_CUS, m_config->gpgpu_operand_collector_num_units_mem, m_config->gpgpu_operand_collector_num_out_ports_mem); m_operand_collector.add_cu_set(GEN_CUS, m_config->gpgpu_operand_collector_num_units_gen, m_config->gpgpu_operand_collector_num_out_ports_gen); -- cgit v1.3 From e643e2e56344db6264b17d7ffce28f22c8fbabe8 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Wed, 11 Oct 2017 19:00:47 -0400 Subject: Fixing deadlock because of dp_unit (2) --- src/gpgpu-sim/shader.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 544d8d8..2c54332 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1087,6 +1087,7 @@ public: switch(inst.op) { case SFU_OP: break; case ALU_SFU_OP: break; + case DP_OP: break; //for compute <= 29 (i..e Fermi and GT200) default: return false; } return pipelined_simd_unit::can_issue(inst); -- cgit v1.3 From 57b0578fcf9f38fdf6ef2828f2ff71e30c7d7098 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 11 Oct 2017 20:03:23 -0400 Subject: Sector Cache - first commit --- src/gpgpu-sim/shader.cc | 19 ++++++++++++------- src/gpgpu-sim/shader.h | 1 + 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 5547a18..c14e19f 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -235,7 +235,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu, //op collector configuration enum { SP_CUS, DP_CUS, SFU_CUS, MEM_CUS, GEN_CUS }; m_operand_collector.add_cu_set(SP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_sp); - m_operand_collector.add_cu_set(DP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_dp); + m_operand_collector.add_cu_set(DP_CUS, m_config->gpgpu_operand_collector_num_units_dp, m_config->gpgpu_operand_collector_num_out_ports_dp); m_operand_collector.add_cu_set(SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu, m_config->gpgpu_operand_collector_num_out_ports_sfu); m_operand_collector.add_cu_set(MEM_CUS, m_config->gpgpu_operand_collector_num_units_mem, m_config->gpgpu_operand_collector_num_out_ports_mem); m_operand_collector.add_cu_set(GEN_CUS, m_config->gpgpu_operand_collector_num_units_gen, m_config->gpgpu_operand_collector_num_out_ports_gen); @@ -698,7 +698,7 @@ void shader_core_ctx::fetch() if( !m_warp[warp_id].functional_done() && !m_warp[warp_id].imiss_pending() && m_warp[warp_id].ibuffer_empty() ) { address_type pc = m_warp[warp_id].get_pc(); address_type ppc = pc + PROGRAM_MEM_START; - unsigned nbytes=16; + unsigned nbytes=16; unsigned offset_in_block = pc & (m_config->m_L1I_config.get_line_sz()-1); if( (offset_in_block+nbytes) > m_config->m_L1I_config.get_line_sz() ) nbytes = (m_config->m_L1I_config.get_line_sz()-offset_in_block); @@ -979,7 +979,6 @@ void scheduler_unit::cycle() issued_inst=true; warp_inst_issued = true; previous_issued_inst_exec_type = exec_unit_type_t::DP; - std::cout<<"DP inst is issued"<m_config->gpgpu_num_dp_units == 0 && pI->op == DP_OP) || (pI->op == SFU_OP) || (pI->op == ALU_SFU_OP)) && (!diff_exec_units || previous_issued_inst_exec_type != exec_unit_type_t::SFU)) { @@ -1440,8 +1439,14 @@ ldst_unit::process_cache_access( cache_t* cache, mem_stage_stall_type result = NO_RC_FAIL; bool write_sent = was_write_sent(events); bool read_sent = was_read_sent(events); - if( write_sent ) - m_core->inc_store_req( inst.warp_id() ); + if( write_sent ) { + unsigned inc_ack = (m_config->m_L1D_config.get_mshr_type() == SECTOR_ASSOC)? + (mf->get_data_size()/SECTOR_SIZE) : 1; + + for(unsigned i=0; i< inc_ack; ++i) + m_core->inc_store_req( inst.warp_id() ); + + } if ( status == HIT ) { assert( !read_sent ); inst.accessq_pop_back(); @@ -1965,12 +1970,12 @@ void ldst_unit::cycle() if( !m_response_fifo.empty() ) { mem_fetch *mf = m_response_fifo.front(); - if (mf->istexture()) { + if (mf->get_access_type() == TEXTURE_ACC_R) { if (m_L1T->fill_port_free()) { m_L1T->fill(mf,gpu_sim_cycle+gpu_tot_sim_cycle); m_response_fifo.pop_front(); } - } else if (mf->isconst()) { + } else if (mf->get_access_type() == CONST_ACC_R) { if (m_L1C->fill_port_free()) { mf->set_status(IN_SHADER_FETCHED,gpu_sim_cycle+gpu_tot_sim_cycle); m_L1C->fill(mf,gpu_sim_cycle+gpu_tot_sim_cycle); diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 544d8d8..c93e0ee 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1087,6 +1087,7 @@ public: switch(inst.op) { case SFU_OP: break; case ALU_SFU_OP: break; + case DP_OP: break; //for compute <= 29 (i..e Fermi and GT200) default: return false; } return pipelined_simd_unit::can_issue(inst); -- cgit v1.3 From c62dab6704fe8c249f8093afb2bf4287b1d3c8a4 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Wed, 11 Oct 2017 20:07:00 -0400 Subject: Update gpgpusim.config --- configs/TeslaC2050/gpgpusim.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config index 4febbe5..ad64679 100644 --- a/configs/TeslaC2050/gpgpusim.config +++ b/configs/TeslaC2050/gpgpusim.config @@ -36,7 +36,7 @@ -gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 -gpgpu_num_sp_units 2 -gpgpu_num_sfu_units 1 --gpgpu_num_sfu_units 0 +-gpgpu_num_dp_units 0 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" -- cgit v1.3 From 6e60441e5724f3d9dd974c17ca67e7bf3e1f990b Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 12 Oct 2017 17:57:23 -0400 Subject: remove Tex cache assertion and prevent spunit to execute DP insts --- src/gpgpu-sim/gpu-cache.cc | 2 +- src/gpgpu-sim/shader.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 9633874..eadc094 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -1483,7 +1483,7 @@ void tex_cache::cycle(){ unsigned rob_index = m_rob.next_pop_index(); const rob_entry &r = m_rob.peek(rob_index); assert( r.m_request == e.m_request ); - assert( r.m_block_addr == m_config.block_addr(e.m_request->get_addr()) ); + //assert( r.m_block_addr == m_config.block_addr(e.m_request->get_addr()) ); if ( r.m_ready ) { assert( r.m_index == e.m_cache_index ); m_cache[r.m_index].m_valid = true; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index c93e0ee..5b41c06 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1123,6 +1123,7 @@ public: case LOAD_OP: return false; case STORE_OP: return false; case MEMORY_BARRIER_OP: return false; + case DP_OP: return false; default: break; } return pipelined_simd_unit::can_issue(inst); -- cgit v1.3 From 07b375cc0c0da2b8a8ca7263f11ecca8ebaf8fe9 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Fri, 13 Oct 2017 22:20:57 -0400 Subject: ensure that first launch uses simt cluster 0 --- src/gpgpu-sim/gpu-sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index eac92b4..470fcf4 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -671,7 +671,7 @@ gpgpu_sim::gpgpu_sim( const gpgpu_sim_config &config ) m_running_kernels.resize( config.max_concurrent_kernel, NULL ); m_last_issued_kernel = 0; - m_last_cluster_issue = 0; + m_last_cluster_issue = m_shader_config->n_simt_clusters-1; // this causes first launch to use simt cluster 0 *average_pipeline_duty_cycle=0; *active_sms=0; -- cgit v1.3 From 50b7ac49a78948f61fa685d717de90feaa277b9b Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 25 Oct 2017 13:15:44 -0400 Subject: The commits includes: 1- REEAD/WERITE buffer for DRAM 2- Fixing FETCH_ON_WRITE cahce policy bug --- src/gpgpu-sim/dram.cc | 11 +++++- src/gpgpu-sim/dram.h | 2 +- src/gpgpu-sim/dram_sched.cc | 95 ++++++++++++++++++++++++++++++++++----------- src/gpgpu-sim/dram_sched.h | 12 ++++++ src/gpgpu-sim/gpu-cache.cc | 34 ++++++++++++---- src/gpgpu-sim/gpu-sim.cc | 7 +++- src/gpgpu-sim/gpu-sim.h | 9 +++++ src/gpgpu-sim/l2cache.cc | 29 ++++++++------ src/gpgpu-sim/mem_fetch.cc | 4 +- src/gpgpu-sim/mem_fetch.h | 4 +- 10 files changed, 160 insertions(+), 47 deletions(-) diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index 5c1ddab..7ed7b6f 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -149,11 +149,18 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m } -bool dram_t::full() const +bool dram_t::full(bool is_write) const { if(m_config->scheduler_type == DRAM_FRFCFS){ if(m_config->gpgpu_frfcfs_dram_sched_queue_size == 0 ) return false; - return m_frfcfs_scheduler->num_pending() >= m_config->gpgpu_frfcfs_dram_sched_queue_size; + if(m_config->seperate_write_queue_enabled){ + if(is_write) + return m_frfcfs_scheduler->num_write_pending() >= m_config->gpgpu_frfcfs_dram_write_queue_size; + else + return m_frfcfs_scheduler->num_pending() >= m_config->gpgpu_frfcfs_dram_sched_queue_size; + } + else + return m_frfcfs_scheduler->num_pending() >= m_config->gpgpu_frfcfs_dram_sched_queue_size; } else return mrqq->full(); } diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index 331b4f1..29731a7 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -101,7 +101,7 @@ public: dram_t( unsigned int parition_id, const struct memory_config *config, class memory_stats_t *stats, class memory_partition_unit *mp ); - bool full() const; + bool full(bool is_write) const; void print( FILE* simFile ) const; void visualize() const; void print_stat( FILE* simFile ); diff --git a/src/gpgpu-sim/dram_sched.cc b/src/gpgpu-sim/dram_sched.cc index 008b5bb..7a140c5 100644 --- a/src/gpgpu-sim/dram_sched.cc +++ b/src/gpgpu-sim/dram_sched.cc @@ -36,6 +36,7 @@ frfcfs_scheduler::frfcfs_scheduler( const memory_config *config, dram_t *dm, mem m_config = config; m_stats = stats; m_num_pending = 0; + m_num_write_pending = 0; m_dram = dm; m_queue = new std::list[m_config->nbk]; m_bins = new std::map::iterator> >[ m_config->nbk ]; @@ -49,15 +50,36 @@ frfcfs_scheduler::frfcfs_scheduler( const memory_config *config, dram_t *dm, mem curr_row_service_time[i] = 0; row_service_timestamp[i] = 0; } + if(m_config->seperate_write_queue_enabled) { + m_write_queue = new std::list[m_config->nbk]; + m_write_bins = new std::map::iterator> >[ m_config->nbk ]; + m_last_write_row = new std::list::iterator>*[ m_config->nbk ]; + + for ( unsigned i=0; i < m_config->nbk; i++ ) { + m_write_queue[i].clear(); + m_write_bins[i].clear(); + m_last_write_row[i] = NULL; + } + } + m_mode = READ_MODE; } void frfcfs_scheduler::add_req( dram_req_t *req ) { - m_num_pending++; - m_queue[req->bk].push_front(req); - std::list::iterator ptr = m_queue[req->bk].begin(); - m_bins[req->bk][req->row].push_front( ptr ); //newest reqs to the front + if(m_config->seperate_write_queue_enabled && req->data->is_write()) { + assert(m_num_write_pending < m_config->gpgpu_frfcfs_dram_write_queue_size); + m_num_write_pending++; + m_write_queue[req->bk].push_front(req); + std::list::iterator ptr = m_write_queue[req->bk].begin(); + m_write_bins[req->bk][req->row].push_front( ptr ); //newest reqs to the front + } else { + assert(m_num_pending < m_config->gpgpu_frfcfs_dram_sched_queue_size); + m_num_pending++; + m_queue[req->bk].push_front(req); + std::list::iterator ptr = m_queue[req->bk].begin(); + m_bins[req->bk][req->row].push_front( ptr ); //newest reqs to the front + } } void frfcfs_scheduler::data_collection(unsigned int bank) @@ -80,21 +102,43 @@ dram_req_t *frfcfs_scheduler::schedule( unsigned bank, unsigned curr_row ) { //row bool rowhit = true; + std::list *m_current_queue = m_queue; + std::map::iterator> > *m_current_bins = m_bins ; + std::list::iterator> **m_current_last_row = m_last_row; + + if(m_config->seperate_write_queue_enabled) { + if(m_mode == READ_MODE && + ((m_num_write_pending >= m_config->write_high_watermark ) + || (m_queue[bank].empty() && !m_write_queue[bank].empty()))) { + m_mode = WRITE_MODE; + } + else if(m_mode == WRITE_MODE && + (( m_num_write_pending < m_config->write_low_watermark ) + || (!m_queue[bank].empty() && m_write_queue[bank].empty()))){ + m_mode = READ_MODE; + } + } + + if(m_mode == WRITE_MODE) { + m_current_queue = m_write_queue; + m_current_bins = m_write_bins ; + m_current_last_row = m_last_write_row; + } - if ( m_last_row[bank] == NULL ) { - if ( m_queue[bank].empty() ) + if ( m_current_last_row[bank] == NULL ) { + if ( m_current_queue[bank].empty() ) return NULL; - std::map::iterator> >::iterator bin_ptr = m_bins[bank].find( curr_row ); - if ( bin_ptr == m_bins[bank].end()) { - dram_req_t *req = m_queue[bank].back(); - bin_ptr = m_bins[bank].find( req->row ); - assert( bin_ptr != m_bins[bank].end() ); // where did the request go??? - m_last_row[bank] = &(bin_ptr->second); + std::map::iterator> >::iterator bin_ptr = m_current_bins[bank].find( curr_row ); + if ( bin_ptr == m_current_bins[bank].end()) { + dram_req_t *req = m_current_queue[bank].back(); + bin_ptr = m_current_bins[bank].find( req->row ); + assert( bin_ptr != m_current_bins[bank].end() ); // where did the request go??? + m_current_last_row[bank] = &(bin_ptr->second); data_collection(bank); rowhit = false; } else { - m_last_row[bank] = &(bin_ptr->second); + m_current_last_row[bank] = &(bin_ptr->second); rowhit = true; } } @@ -103,25 +147,32 @@ dram_req_t *frfcfs_scheduler::schedule( unsigned bank, unsigned curr_row ) if(rowhit) m_dram->hits_num++; - std::list::iterator next = m_last_row[bank]->back(); + std::list::iterator next = m_current_last_row[bank]->back(); dram_req_t *req = (*next); m_stats->concurrent_row_access[m_dram->id][bank]++; m_stats->row_access[m_dram->id][bank]++; - m_last_row[bank]->pop_back(); + m_current_last_row[bank]->pop_back(); - m_queue[bank].erase(next); - if ( m_last_row[bank]->empty() ) { - m_bins[bank].erase( req->row ); - m_last_row[bank] = NULL; + m_current_queue[bank].erase(next); + if ( m_current_last_row[bank]->empty() ) { + m_current_bins[bank].erase( req->row ); + m_current_last_row[bank] = NULL; } #ifdef DEBUG_FAST_IDEAL_SCHED if ( req ) printf("%08u : DRAM(%u) scheduling memory request to bank=%u, row=%u\n", (unsigned)gpu_sim_cycle, m_dram->id, req->bk, req->row ); #endif - assert( req != NULL && m_num_pending != 0 ); - m_num_pending--; + + if(m_config->seperate_write_queue_enabled && req->data->is_write()) { + assert( req != NULL && m_num_write_pending != 0 ); + m_num_write_pending--; + } + else { + assert( req != NULL && m_num_pending != 0 ); + m_num_pending--; + } return req; } @@ -138,7 +189,7 @@ void dram_t::scheduler_frfcfs() { unsigned mrq_latency; frfcfs_scheduler *sched = m_frfcfs_scheduler; - while ( !mrqq->empty() && (!m_config->gpgpu_frfcfs_dram_sched_queue_size || sched->num_pending() < m_config->gpgpu_frfcfs_dram_sched_queue_size)) { + while ( !mrqq->empty() ) { dram_req_t *req = mrqq->pop(); // Power stats diff --git a/src/gpgpu-sim/dram_sched.h b/src/gpgpu-sim/dram_sched.h index 3860f5b..63f5831 100644 --- a/src/gpgpu-sim/dram_sched.h +++ b/src/gpgpu-sim/dram_sched.h @@ -35,6 +35,11 @@ #include #include +enum memory_mode { + READ_MODE = 0, + WRITE_MODE +}; + class frfcfs_scheduler { public: frfcfs_scheduler( const memory_config *config, dram_t *dm, memory_stats_t *stats ); @@ -43,17 +48,24 @@ public: dram_req_t *schedule( unsigned bank, unsigned curr_row ); void print( FILE *fp ); unsigned num_pending() const { return m_num_pending;} + unsigned num_write_pending() const { return m_num_write_pending;} private: const memory_config *m_config; dram_t *m_dram; unsigned m_num_pending; + unsigned m_num_write_pending; std::list *m_queue; std::map::iterator> > *m_bins; std::list::iterator> **m_last_row; unsigned *curr_row_service_time; //one set of variables for each bank. unsigned *row_service_timestamp; //tracks when scheduler began servicing current row + std::list *m_write_queue; + std::map::iterator> > *m_write_bins; + std::list::iterator> **m_last_write_row; + + enum memory_mode m_mode; memory_stats_t *m_stats; }; diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index eadc094..d199cca 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -945,10 +945,9 @@ void baseline_cache::send_read_request(new_addr_type addr, new_addr_type block_a mf->set_addr( block_addr ); m_miss_queue.push_back(mf); mf->set_status(m_miss_queue_status,time); - if(wa) - events.push_back(cache_event(WRITE_ALLOCATE_SENT)); - else + if(!wa) events.push_back(cache_event(READ_REQUEST_SENT)); + do_miss = true; } else if(mshr_hit && !mshr_avail) @@ -1087,6 +1086,8 @@ data_cache::wr_miss_wa_naive( new_addr_type addr, send_read_request(addr, block_addr, cache_index, n_mf, time, do_miss, wb, evicted, events, false, true); + events.push_back(cache_event(WRITE_ALLOCATE_SENT)); + if( do_miss ){ // If evicted block is modified and not a write-through // (already modified lower level) @@ -1111,7 +1112,7 @@ data_cache::wr_miss_wa_fetch_on_write( new_addr_type addr, { new_addr_type block_addr = m_config.block_addr(addr); - new_addr_type mshr_addr = m_config.block_addr(mf->get_addr()); + new_addr_type mshr_addr = m_config.mshr_addr(mf->get_addr()); if(mf->get_access_byte_mask().count() == m_config.get_atom_sz()) { @@ -1147,10 +1148,23 @@ data_cache::wr_miss_wa_fetch_on_write( new_addr_type addr, } else { - if(miss_queue_full(1)) { - m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL); - return RESERVATION_FAIL; - } + bool mshr_hit = m_mshrs.probe(mshr_addr); + bool mshr_avail = !m_mshrs.full(mshr_addr); + if(miss_queue_full(1) + || (!(mshr_hit && mshr_avail) + && !(!mshr_hit && mshr_avail && (m_miss_queue.size() < m_config.m_miss_queue_size)))) { + //check what is the exactly the failure reason + if(miss_queue_full(1) ) + m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL); + else if(mshr_hit && !mshr_avail) + m_stats.inc_fail_stats(mf->get_access_type(), MSHR_MERGE_ENRTY_FAIL); + else if (!mshr_hit && !mshr_avail) + m_stats.inc_fail_stats(mf->get_access_type(), MSHR_ENRTY_FAIL); + else + assert(0); + + return RESERVATION_FAIL; + } //prevent Write - Read - Write in pending mshr @@ -1177,8 +1191,10 @@ data_cache::wr_miss_wa_fetch_on_write( new_addr_type addr, mf->get_sid(), mf->get_tpc(), mf->get_mem_config(), + NULL, mf); + new_addr_type block_addr = m_config.block_addr(addr); bool do_miss = false; bool wb = false; @@ -1191,6 +1207,8 @@ data_cache::wr_miss_wa_fetch_on_write( new_addr_type addr, cache_block_t* block = m_tag_array->get_block(cache_index); block->set_modified_on_fill(true, mf->get_access_sector_mask()); + events.push_back(cache_event(WRITE_ALLOCATE_SENT)); + if( do_miss ){ // If evicted block is modified and not a write-through // (already modified lower level) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 470fcf4..7838875 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -201,7 +201,12 @@ void memory_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-dram_bnkgrp_indexing_policy", OPT_UINT32, &dram_bnkgrp_indexing_policy, "dram_bnkgrp_indexing_policy (0 = take higher bits, 1 = take lower bits) (Default = 0)", "0"); - + option_parser_register(opp, "-Seperate_Write_Queue_Enable", OPT_BOOL, &seperate_write_queue_enabled, + "Seperate_Write_Queue_Enable", + "0"); + option_parser_register(opp, "-Write_Queue_Size", OPT_CSTR, &write_queue_size_opt, + "Write_Queue_Size", + "32:28:16"); m_address_mapping.addrdec_setoption(opp); } diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index f379a17..197350b 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -214,6 +214,9 @@ struct memory_config { m_valid = true; icnt_flit_size = 32; // Default 32 + + sscanf(write_queue_size_opt,"%d:%d:%d", + &gpgpu_frfcfs_dram_write_queue_size,&write_high_watermark,&write_low_watermark); } void reg_options(class OptionParser * opp); @@ -274,6 +277,12 @@ struct memory_config { unsigned dram_bnk_indexing_policy; unsigned dram_bnkgrp_indexing_policy; bool dual_bus_interface; + + bool seperate_write_queue_enabled; + char *write_queue_size_opt; + unsigned gpgpu_frfcfs_dram_write_queue_size; + unsigned write_high_watermark; + unsigned write_low_watermark; }; // global counters and flags (please try not to add to this list!!!) diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index f7323c5..cac59f1 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -93,7 +93,9 @@ memory_partition_unit::arbitration_metadata::arbitration_metadata(const struct m m_private_credit_limit = 1; m_shared_credit_limit = config->gpgpu_frfcfs_dram_sched_queue_size + config->gpgpu_dram_return_queue_size - - (config->m_n_sub_partition_per_memory_channel - 1); + - (config->m_n_sub_partition_per_memory_channel - 1); + if(config->seperate_write_queue_enabled ) + m_shared_credit_limit += config->gpgpu_frfcfs_dram_write_queue_size; if (config->gpgpu_frfcfs_dram_sched_queue_size == 0 or config->gpgpu_dram_return_queue_size == 0) { @@ -220,7 +222,8 @@ void memory_partition_unit::dram_cycle() m_dram->cycle(); m_dram->dram_log(SAMPLELOG); - if( !m_dram->full() ) { + // mem_fetch *mf = m_sub_partition[spid]->L2_dram_queue_top(); + //if( !m_dram->full(mf->is_write()) ) { // L2->DRAM queue to DRAM latency queue // Arbitrate among multiple L2 subpartitions int last_issued_partition = m_arbitration_metadata.last_borrower(); @@ -228,6 +231,9 @@ void memory_partition_unit::dram_cycle() int spid = (p + last_issued_partition + 1) % m_config->m_n_sub_partition_per_memory_channel; if (!m_sub_partition[spid]->L2_dram_queue_empty() && can_issue_to_dram(spid)) { mem_fetch *mf = m_sub_partition[spid]->L2_dram_queue_top(); + if(m_dram->full(mf->is_write()) ) + break; + m_sub_partition[spid]->L2_dram_queue_pop(); MEMPART_DPRINTF("Issue mem_fetch request %p from sub partition %d to dram\n", mf, spid); dram_delay_t d; @@ -239,12 +245,13 @@ void memory_partition_unit::dram_cycle() break; // the DRAM should only accept one request per cycle } } - } + //} // DRAM latency queue - if( !m_dram_latency_queue.empty() && ( (gpu_sim_cycle+gpu_tot_sim_cycle) >= m_dram_latency_queue.front().ready_cycle ) && !m_dram->full() ) { - mem_fetch* mf = m_dram_latency_queue.front().req; - m_dram_latency_queue.pop_front(); + + if( !m_dram_latency_queue.empty() && ( (gpu_sim_cycle+gpu_tot_sim_cycle) >= m_dram_latency_queue.front().ready_cycle ) && !m_dram->full(m_dram_latency_queue.front().req->is_write()) ) { + mem_fetch* mf = m_dram_latency_queue.front().req; + m_dram_latency_queue.pop_front(); m_dram->push(mf); } } @@ -343,12 +350,12 @@ void memory_sub_partition::cache_cycle( unsigned cycle ) mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); m_L2_icnt_queue->push(mf); }else{ - if(m_config->m_L2_config.m_write_alloc_policy == FETCH_ON_WRITE && mf->original_mf) + if(m_config->m_L2_config.m_write_alloc_policy == FETCH_ON_WRITE) { - assert(mf->original_mf); - mf->original_mf->set_reply(); - mf->original_mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); - m_L2_icnt_queue->push(mf->original_mf); + assert(mf->original_wr_mf); + mf->original_wr_mf->set_reply(); + mf->original_wr_mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); + m_L2_icnt_queue->push(mf->original_wr_mf); } m_request_tracker.erase(mf); delete mf; diff --git a/src/gpgpu-sim/mem_fetch.cc b/src/gpgpu-sim/mem_fetch.cc index b8e918f..c05a693 100644 --- a/src/gpgpu-sim/mem_fetch.cc +++ b/src/gpgpu-sim/mem_fetch.cc @@ -40,7 +40,8 @@ mem_fetch::mem_fetch( const mem_access_t &access, unsigned sid, unsigned tpc, const class memory_config *config, - mem_fetch *m_original_mf) + mem_fetch *m_original_mf, + mem_fetch *m_original_wr_mf) { m_request_uid = sm_next_mf_request_uid++; m_access = access; @@ -63,6 +64,7 @@ mem_fetch::mem_fetch( const mem_access_t &access, m_mem_config = config; icnt_flit_size = config->icnt_flit_size; original_mf = m_original_mf; + original_wr_mf = m_original_wr_mf; } mem_fetch::~mem_fetch() diff --git a/src/gpgpu-sim/mem_fetch.h b/src/gpgpu-sim/mem_fetch.h index 76e7419..278cf32 100644 --- a/src/gpgpu-sim/mem_fetch.h +++ b/src/gpgpu-sim/mem_fetch.h @@ -56,7 +56,8 @@ public: unsigned sid, unsigned tpc, const class memory_config *config, - mem_fetch *original_mf = NULL); + mem_fetch *original_mf = NULL, + mem_fetch *original_wr_mf = NULL); ~mem_fetch(); void set_status( enum mem_fetch_status status, unsigned long long cycle ); @@ -115,6 +116,7 @@ public: unsigned get_num_flits(bool simt_to_mem); mem_fetch* original_mf; + mem_fetch* original_wr_mf; private: // request source information unsigned m_request_uid; -- cgit v1.3 From 161f9cefeaf216f48f93e1192c817997cf875cac Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 26 Oct 2017 11:19:52 -0400 Subject: Changing the Titan X config file to use the last modifications --- configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt | 4 +- configs/Pascal-P102-GDDR5X/gpgpusim.config | 46 +++++++++++++--------- src/gpgpu-sim/gpu-sim.cc | 3 ++ src/gpgpu-sim/gpu-sim.h | 1 - 4 files changed, 32 insertions(+), 22 deletions(-) diff --git a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt index 602daee..58e596d 100644 --- a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt +++ b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt @@ -1,6 +1,6 @@ //21*1 fly with 32 flits per packet under gpgpusim injection mode use_map = 0; -flit_size = 32; +flit_size = 40; // currently we do not use this, see subnets below network_count = 2; @@ -17,7 +17,7 @@ routing_function = dest_tag; // Flow control num_vcs = 1; -vc_buf_size = 8; +vc_buf_size = 32; wait_for_tail_credit = 0; diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index 8b02680..36d13af 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -12,8 +12,9 @@ -gpgpu_ptx_save_converted_ptxplus 0 # high level architecture configuration +# P102 has two semi-indp scheds per core, and two cores per cluster -gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 1 +-gpgpu_n_cores_per_cluster 2 -gpgpu_n_mem 12 -gpgpu_n_sub_partition_per_mchannel 2 @@ -24,20 +25,20 @@ -gpgpu_clock_domains 1417.0:2834.0:1417.0:2500.0 # shader core pipeline config --gpgpu_shader_registers 65536 +-gpgpu_shader_registers 32768 -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 +# This implies a maximum of 32 warps/SM +-gpgpu_shader_core_pipeline 1024:32 +-gpgpu_shader_cta 16 -gpgpu_simd_model 1 # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB ## Pascal GP102 has 4 SP SIMD units and 4 SFU units ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,1,4,1,4,1,4,1,9 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 4 +-gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 2 -gpgpu_num_dp_units 1 @@ -51,7 +52,6 @@ -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,8,8,8,130 --ptx_opcode_latency_sfu 8 -ptx_opcode_initiation_sfu 4 # ::,::::,::,:** @@ -60,13 +60,16 @@ # Pascal GP102 has 96KB Shared memory # Pascal GP102 has 64KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,S:128:8,8 --gpgpu_shmem_size 98304 +-gpgpu_cache:dl1 S:64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_shmem_size 49152 -gmem_skip_L1D 1 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:128:4,4:0,32 +-gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:256:4,4:0,32 -gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 @@ -76,15 +79,14 @@ -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 # enable operand collector -## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units -gpgpu_operand_collector_num_units_sp 12 -gpgpu_operand_collector_num_units_sfu 6 -gpgpu_operand_collector_num_units_mem 8 -gpgpu_operand_collector_num_units_dp 6 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 4 --gpgpu_operand_collector_num_out_ports_sfu 4 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_operand_collector_num_in_ports_sfu 2 +-gpgpu_operand_collector_num_out_ports_sfu 2 -gpgpu_operand_collector_num_in_ports_mem 1 -gpgpu_operand_collector_num_out_ports_mem 1 -gpgpu_operand_collector_num_in_ports_dp 1 @@ -119,7 +121,7 @@ # the minimum DRAM latency (100 core cycles). I.e. # Total buffer space required = 100 x 924MHz / 700MHz = 132 -gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 116 +-gpgpu_dram_return_queue_size 192 # for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) # 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition @@ -136,8 +138,14 @@ -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 32:28:16 + # Pascal 102 has four schedulers per core --gpgpu_num_sched_per_core 4 +-gpgpu_num_sched_per_core 2 # Two Level Scheduler with active and pending pools #-gpgpu_scheduler two_level_active:6:0:1 # Loose round robbin scheduler diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 7838875..6179d46 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -207,6 +207,9 @@ void memory_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-Write_Queue_Size", OPT_CSTR, &write_queue_size_opt, "Write_Queue_Size", "32:28:16"); + option_parser_register(opp, "-icnt_flit_size", OPT_UINT32, &icnt_flit_size, + "icnt_flit_size", + "32"); m_address_mapping.addrdec_setoption(opp); } diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 197350b..52c4643 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -213,7 +213,6 @@ struct memory_config { m_L2_config.init(&m_address_mapping); m_valid = true; - icnt_flit_size = 32; // Default 32 sscanf(write_queue_size_opt,"%d:%d:%d", &gpgpu_frfcfs_dram_write_queue_size,&write_high_watermark,&write_low_watermark); -- cgit v1.3 From d55bf349e018597199839d1397f9609e015d924d Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 26 Oct 2017 11:27:19 -0400 Subject: fixing a typo in config file --- src/cuda-sim/cuda-sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 48d1219..a668db1 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -80,7 +80,7 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Opcode latencies for double precision floating points " "Default 8,8,8,8,335", "8,8,8,8,335"); - option_parser_register(opp, "-opcode_latency_sfu", OPT_CSTR, &opcode_latency_sfu, + option_parser_register(opp, "-ptx_opcode_latency_sfu", OPT_CSTR, &opcode_latency_sfu, "Opcode latencies for SFU instructions" "Default 8", "8"); -- cgit v1.3 From c1bb3638d2c3a8f1b86e0e952e12bb2ed7f1c0dc Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 26 Oct 2017 11:29:45 -0400 Subject: adding sfu latency to config file --- configs/Pascal-P102-GDDR5X/gpgpusim.config | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index 36d13af..5419c51 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -53,6 +53,7 @@ -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,8,8,8,130 -ptx_opcode_initiation_sfu 4 +-ptx_opcode_latency_sfu 8 # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo -- cgit v1.3 From f23021ad8663636e1103bd75a742480cb6238435 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Fri, 27 Oct 2017 22:35:52 -0400 Subject: add more statistics and chaging Pascal config --- configs/Pascal-P102-GDDR5X/gpgpusim.config | 12 +++++++----- src/abstract_hardware_model.cc | 2 +- src/gpgpu-sim/dram.cc | 3 ++- src/gpgpu-sim/dram_sched.cc | 2 ++ src/gpgpu-sim/gpu-cache.cc | 2 ++ src/gpgpu-sim/gpu-sim.cc | 2 +- src/gpgpu-sim/gpu-sim.h | 2 +- src/gpgpu-sim/l2cache.cc | 2 +- src/gpgpu-sim/mem_latency_stat.cc | 17 +++++++++++++---- src/gpgpu-sim/mem_latency_stat.h | 4 ++++ src/gpgpu-sim/shader.cc | 8 ++++---- 11 files changed, 38 insertions(+), 18 deletions(-) diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index 5419c51..e830023 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -59,22 +59,24 @@ # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. # Pascal GP102 has 96KB Shared memory -# Pascal GP102 has 64KB L1 cache +# Pascal GP102 has 24KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 S:64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_cache:dl1 N:32:128:6,L:L:m:N:H,S:128:8,16 -gpgpu_shmem_size 49152 -gmem_skip_L1D 1 -icnt_flit_size 40 -gpgpu_n_cluster_ejection_buffer_size 32 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:256:4,4:0,32 +-gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:128:4,16:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 +#-gpgpu_flush_l2_cache 1 # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 # 48 KB Tex +# this is unused -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 # 12 KB Const -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 @@ -100,7 +102,7 @@ -gpgpu_shmem_limited_broadcast 0 -gpgpu_shmem_warp_parts 1 # Use Fermi Coalsce arhitetecture which is the same as Pascal --gpgpu_coalesce_arch 20 +-gpgpu_coalesce_arch 61 ## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units -gpgpu_max_insn_issue_per_warp 2 @@ -143,7 +145,7 @@ -dram_bnkgrp_indexing_policy 1 #-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 32:28:16 +#-Write_Queue_Size 64:56:32 # Pascal 102 has four schedulers per core -gpgpu_num_sched_per_core 2 diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc index 51265fd..d2a155c 100644 --- a/src/abstract_hardware_model.cc +++ b/src/abstract_hardware_model.cc @@ -314,7 +314,7 @@ void warp_inst_t::generate_mem_accesses() break; case global_space: case local_space: case param_space_local: - if( m_config->gpgpu_coalesce_arch == 13 || m_config->gpgpu_coalesce_arch == 20) { + if( m_config->gpgpu_coalesce_arch >= 13 && m_config->gpgpu_coalesce_arch <= 62) { if(isatomic()) memory_coalescing_arch_atomic(is_write, access_type); else diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index 7ed7b6f..de37f64 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -570,9 +570,10 @@ bool dram_t::issue_col_command(int j) bkgrp[grp]->RTPLc = m_config->tRTPL; issued = true; if(bk[j]->mrq->data->get_access_type() == L2_WR_ALLOC_R) - n_rd_L2_A++; + n_rd_L2_A++; else n_rd++; + bwutil += m_config->BL/m_config->data_command_freq_ratio; bwutil_partial += m_config->BL/m_config->data_command_freq_ratio; bk[j]->n_access++; diff --git a/src/gpgpu-sim/dram_sched.cc b/src/gpgpu-sim/dram_sched.cc index 7a140c5..ac4c827 100644 --- a/src/gpgpu-sim/dram_sched.cc +++ b/src/gpgpu-sim/dram_sched.cc @@ -220,6 +220,8 @@ void dram_t::scheduler_frfcfs() bk[b]->mrq = req; if (m_config->gpgpu_memlatency_stat) { mrq_latency = gpu_sim_cycle + gpu_tot_sim_cycle - bk[b]->mrq->timestamp; + m_stats->tot_mrq_latency += mrq_latency; + m_stats->tot_mrq_num++; bk[b]->mrq->timestamp = gpu_tot_sim_cycle + gpu_sim_cycle; m_stats->mrq_lat_table[LOGB2(mrq_latency)]++; if (mrq_latency > m_stats->max_mrq_latency) { diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index d199cca..32c2bb1 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -333,8 +333,10 @@ void tag_array::fill( unsigned index, unsigned time, mem_fetch* mf) void tag_array::flush() { for (unsigned i=0; i < m_config.get_num_lines(); i++) + if(m_lines[i]->is_modified_line()) { for(unsigned j=0; j < SECTOR_CHUNCK_SIZE; j++) m_lines[i]->set_status(INVALID, mem_access_sector_mask_t().set(j)) ; + } } float tag_array::windowed_miss_rate( ) const diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 6179d46..0e06c5c 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1412,7 +1412,7 @@ void gpgpu_sim::cycle() if (mf) { unsigned response_size = mf->get_is_write()?mf->get_ctrl_size():mf->size(); if ( ::icnt_has_buffer( m_shader_config->mem2device(i), response_size ) ) { - if (!mf->get_is_write()) + //if (!mf->get_is_write()) mf->set_return_timestamp(gpu_sim_cycle+gpu_tot_sim_cycle); mf->set_status(IN_ICNT_TO_SHADER,gpu_sim_cycle+gpu_tot_sim_cycle); ::icnt_push( m_shader_config->mem2device(i), mf->get_tpc(), mf, response_size ); diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 52c4643..043fcee 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -199,7 +199,7 @@ struct memory_config { assert(nbkgrp>0 && "Number of bank groups cannot be zero"); tRCDWR = tRCD-(WL+1); tRTW = (CL+(BL/data_command_freq_ratio)+2-WL); - tWTR = (WL+(BL/data_command_freq_ratio)+tCDLR); + tWTR = (WL+(BL/data_command_freq_ratio)+tCDLR); tWTP = (WL+(BL/data_command_freq_ratio)+tWR); dram_atom_size = BL * busW * gpu_n_mem_per_ctrlr; // burst length x bus width x # chips per partition diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index cac59f1..8fbf448 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -628,6 +628,7 @@ std::vector memory_sub_partition::breakdown_request_to_sector_reques void memory_sub_partition::push( mem_fetch* m_req, unsigned long long cycle ) { if (m_req) { + m_stats->memlatstat_icnt2mem_pop(m_req); std::vector reqs; if(m_config->m_L2_config.m_cache_type == SECTOR) reqs = breakdown_request_to_sector_requests(m_req); @@ -637,7 +638,6 @@ void memory_sub_partition::push( mem_fetch* m_req, unsigned long long cycle ) for(unsigned i=0; imemlatstat_icnt2mem_pop(req); if( req->istexture() ) { m_icnt_L2_queue->push(req); req->set_status(IN_PARTITION_ICNT_TO_L2_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc index fde0eff..35d6d84 100644 --- a/src/gpgpu-sim/mem_latency_stat.cc +++ b/src/gpgpu-sim/mem_latency_stat.cc @@ -75,6 +75,10 @@ memory_stats_t::memory_stats_t( unsigned n_shader, const struct shader_core_conf max_mf_latency = 0; max_icnt2mem_latency = 0; max_icnt2sh_latency = 0; + tot_icnt2mem_latency = 0; + tot_icnt2sh_latency = 0; + tot_mrq_num = 0; + tot_mrq_latency = 0; memset(mrq_lat_table, 0, sizeof(unsigned)*32); memset(dq_lat_table, 0, sizeof(unsigned)*32); memset(mf_lat_table, 0, sizeof(unsigned)*32); @@ -158,6 +162,7 @@ void memory_stats_t::memlatstat_read_done(mem_fetch *mf) mf_max_lat_table[mf->get_tlx_addr().chip][mf->get_tlx_addr().bk] = mf_latency; unsigned icnt2sh_latency; icnt2sh_latency = (gpu_tot_sim_cycle+gpu_sim_cycle) - mf->get_return_timestamp(); + tot_icnt2sh_latency += icnt2sh_latency; icnt2sh_lat_table[LOGB2(icnt2sh_latency)]++; if (icnt2sh_latency > max_icnt2sh_latency) max_icnt2sh_latency = icnt2sh_latency; @@ -191,6 +196,7 @@ void memory_stats_t::memlatstat_icnt2mem_pop(mem_fetch *mf) if (m_memory_config->gpgpu_memlatency_stat) { unsigned icnt2mem_latency; icnt2mem_latency = (gpu_tot_sim_cycle+gpu_sim_cycle) - mf->get_timestamp(); + tot_icnt2mem_latency += icnt2mem_latency; icnt2mem_lat_table[LOGB2(icnt2mem_latency)]++; if (icnt2mem_latency > max_icnt2mem_latency) max_icnt2mem_latency = icnt2mem_latency; @@ -216,14 +222,17 @@ void memory_stats_t::memlatstat_print( unsigned n_mem, unsigned gpu_mem_n_bk ) unsigned max_bank_accesses, min_bank_accesses, max_chip_accesses, min_chip_accesses; if (m_memory_config->gpgpu_memlatency_stat) { + printf("maxmflatency = %d \n", max_mf_latency); + printf("max_icnt2mem_latency = %d \n", max_icnt2mem_latency); printf("maxmrqlatency = %d \n", max_mrq_latency); - printf("maxdqlatency = %d \n", max_dq_latency); - printf("maxmflatency = %d \n", max_mf_latency); + //printf("maxdqlatency = %d \n", max_dq_latency); + printf("max_icnt2sh_latency = %d \n", max_icnt2sh_latency); if (num_mfs) { printf("averagemflatency = %lld \n", mf_total_lat/num_mfs); + printf("avg_icnt2mem_latency = %lld \n", tot_icnt2mem_latency/num_mfs); + printf("avg_mrq_latency = %lld \n", tot_mrq_latency/tot_mrq_num); + printf("avg_icnt2sh_latency = %lld \n", tot_icnt2sh_latency/num_mfs); } - printf("max_icnt2mem_latency = %d \n", max_icnt2mem_latency); - printf("max_icnt2sh_latency = %d \n", max_icnt2sh_latency); printf("mrq_lat_table:"); for (i=0; i< 32; i++) { printf("%d \t", mrq_lat_table[i]); diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h index 4968a3b..5b89202 100644 --- a/src/gpgpu-sim/mem_latency_stat.h +++ b/src/gpgpu-sim/mem_latency_stat.h @@ -56,6 +56,10 @@ public: unsigned max_dq_latency; unsigned max_mf_latency; unsigned max_icnt2mem_latency; + unsigned long long int tot_icnt2mem_latency; + unsigned long long int tot_icnt2sh_latency; + unsigned long long int tot_mrq_latency; + unsigned long long int tot_mrq_num; unsigned max_icnt2sh_latency; unsigned mrq_lat_table[32]; unsigned dq_lat_table[32]; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index c14e19f..bf482fb 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1458,7 +1458,7 @@ ldst_unit::process_cache_access( cache_t* cache, if( !write_sent ) delete mf; } else if ( status == RESERVATION_FAIL ) { - result = COAL_STALL; + result = BK_CONF; assert( !read_sent ); assert( !write_sent ); delete mf; @@ -1467,8 +1467,8 @@ ldst_unit::process_cache_access( cache_t* cache, //inst.clear_active( access.get_warp_mask() ); // threads in mf writeback when mf returns inst.accessq_pop_back(); } - if( !inst.accessq_empty() ) - result = BK_CONF; + if( !inst.accessq_empty() && result == NO_RC_FAIL) + result = COAL_STALL; return result; } @@ -1563,7 +1563,7 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea assert( CACHE_UNDEFINED != inst.cache_op ); stall_cond = process_memory_access_queue(m_L1D,inst); } - if( !inst.accessq_empty() ) + if( !inst.accessq_empty() && stall_cond == NO_RC_FAIL) stall_cond = COAL_STALL; if (stall_cond != NO_RC_FAIL) { stall_reason = stall_cond; -- cgit v1.3 From be9d240c3f8b0c1c4083dc2b6173a50f55cbe52e Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 27 Oct 2017 23:27:11 -0400 Subject: Adding the sdk into the regression mix --- Jenkinsfile | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 3ea1bcd..63d14d2 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -6,7 +6,6 @@ pipeline { stages { stage('simulator-build') { steps { - parallel "4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ @@ -37,7 +36,7 @@ pipeline { make -f Makefile.PTX5 -C ./benchmarks/src/ all' } } - stage('rodinia-regress'){ + stage('regress'){ steps { parallel "4.2-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ @@ -49,9 +48,20 @@ pipeline { source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/benchmarks-8.0.yml -c ./gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs-fermi-plus-only.yml -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' + }, "4.2-sdk-4.2": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/apps/sdk-4.2.yml -c ./gpgpu-sim_simulations/util/job_launching/configs/all-ptx-cfgs-post-fermi.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' + }, "8.0-sdk-4.2": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/apps/sdk-4.2.yml -c ./gpgpu-sim_simulations/util/job_launching/configs/all-ptx-cfgs-post-fermi.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' } } } + } post { success { -- cgit v1.3 From 6852a6f17d31b7caea48255f1a00778d986a72fa Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 27 Oct 2017 23:32:42 -0400 Subject: parallelizing the benchmark build --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 63d14d2..474bc45 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -28,12 +28,12 @@ pipeline { source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -C ./benchmarks/src all' + make -j -C ./benchmarks/src all' sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -f Makefile.PTX5 -C ./benchmarks/src/ all' + make -j -f Makefile.PTX5 -C ./benchmarks/src/ all' } } stage('regress'){ -- cgit v1.3 From dbf8020709ff5f016cb79f4cfa24ff421fe7cdf7 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 27 Oct 2017 23:44:24 -0400 Subject: oop - wrong name for sdk app yml --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 474bc45..065fb90 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -51,12 +51,12 @@ pipeline { }, "4.2-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/apps/sdk-4.2.yml -c ./gpgpu-sim_simulations/util/job_launching/configs/all-ptx-cfgs-post-fermi.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/apps/sdk.yml -c ./gpgpu-sim_simulations/util/job_launching/configs/all-ptx-cfgs-post-fermi.yml -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "8.0-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/apps/sdk-4.2.yml -c ./gpgpu-sim_simulations/util/job_launching/configs/all-ptx-cfgs-post-fermi.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/apps/sdk.yml -c ./gpgpu-sim_simulations/util/job_launching/configs/all-ptx-cfgs-post-fermi.yml -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' } } -- cgit v1.3 From 075625b451b3ca9ba053e8d81d034aa046216b91 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 28 Oct 2017 00:56:54 -0400 Subject: another misnaming of configs --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 065fb90..0feba14 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -51,12 +51,12 @@ pipeline { }, "4.2-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/apps/sdk.yml -c ./gpgpu-sim_simulations/util/job_launching/configs/all-ptx-cfgs-post-fermi.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/apps/sdk.yml -c ./gpgpu-sim_simulations/util/job_launching/configs/all-ptx-only-post-fermi.yml -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "8.0-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/apps/sdk.yml -c ./gpgpu-sim_simulations/util/job_launching/configs/all-ptx-cfgs-post-fermi.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/apps/sdk.yml -c ./gpgpu-sim_simulations/util/job_launching/configs/all-ptx-only-post-fermi.yml -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' } } -- cgit v1.3 From 20d4e11b87a6cafb2ece48a22a16dd02f270b6a3 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 28 Oct 2017 01:01:49 -0400 Subject: Using SDK 4.2 with 8.0 is causing way too much trouble. --- Jenkinsfile | 5 ----- 1 file changed, 5 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 0feba14..0a7bdf0 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -53,11 +53,6 @@ pipeline { source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/apps/sdk.yml -c ./gpgpu-sim_simulations/util/job_launching/configs/all-ptx-only-post-fermi.yml -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' - }, "8.0-sdk-4.2": { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ - source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/apps/sdk.yml -c ./gpgpu-sim_simulations/util/job_launching/configs/all-ptx-only-post-fermi.yml -N regress-$$ && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' } } } -- cgit v1.3 From 110b88d9273d16f5eab1193402cb45557fa23a69 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 28 Oct 2017 10:18:42 -0400 Subject: Adding in the config Mahmoud made that requires no code changes to GPGPU-Sim --- .../gpgpu-sim-3.x/config_fermi_islip.icnt | 70 +++ configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 151 ++++++ .../gpgpu-sim-3.x/gpuwattch_gtx480.xml | 538 +++++++++++++++++++++ 3 files changed, 759 insertions(+) create mode 100644 configs/PascalTitanX/gpgpu-sim-3.x/config_fermi_islip.icnt create mode 100644 configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config create mode 100755 configs/PascalTitanX/gpgpu-sim-3.x/gpuwattch_gtx480.xml diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/config_fermi_islip.icnt b/configs/PascalTitanX/gpgpu-sim-3.x/config_fermi_islip.icnt new file mode 100644 index 0000000..602daee --- /dev/null +++ b/configs/PascalTitanX/gpgpu-sim-3.x/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 52; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config new file mode 100644 index 0000000..782edf6 --- /dev/null +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -0,0 +1,151 @@ +# This config models the Pascal GP102 (NVIDIA TITAN X) +# For more info about this card, see Nvidia White paper +# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 61 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 12 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1417.0:2834.0:1417.0:2500.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 4 SFU units +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,4,1,4,4,1,8 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,8,4,4,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The defulat is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_shmem_size 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +# gpgpu_num_reg_banks should be increased to 32 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) +# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" + +# Pascal GP102 has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpuwattch_gtx480.xml b/configs/PascalTitanX/gpgpu-sim-3.x/gpuwattch_gtx480.xml new file mode 100755 index 0000000..304e0fd --- /dev/null +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpuwattch_gtx480.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.3 From 9fad92bb8305b7cc6dd99f68c82721f4f4e09e5c Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 29 Oct 2017 00:30:35 -0400 Subject: changing the commandline for launching to reflect simplifications in the simulations repo --- Jenkinsfile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 0a7bdf0..f927471 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -33,7 +33,7 @@ pipeline { source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -f Makefile.PTX5 -C ./benchmarks/src/ all' + make -j -C ./benchmarks/src/ all' } } stage('regress'){ @@ -41,17 +41,17 @@ pipeline { parallel "4.2-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/benchmarks.yml -c ./gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b rodinia_2.0-ft -c ./gpgpu-sim_simulations/util/job_launching/configs/run-fermi-and-up.yml -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "8.0-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/benchmarks-8.0.yml -c ./gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs-fermi-plus-only.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b rodinia_2.0-ft -c ./gpgpu-sim_simulations/util/job_launching/configs/run-fermi-and-up-noplus.yml -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "4.2-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b ./gpgpu-sim_simulations/util/job_launching/apps/sdk.yml -c ./gpgpu-sim_simulations/util/job_launching/configs/all-ptx-only-post-fermi.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b sdk-4.2 -c ./gpgpu-sim_simulations/util/job_launching/configs/run-fermi-and-up-noplus.yml -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' } } -- cgit v1.3 From b32909cf0a4faa282a5cbb0cee30af20ba129032 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 29 Oct 2017 00:35:25 -0400 Subject: oops... big B --- Jenkinsfile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index f927471..5d43e4c 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -41,17 +41,17 @@ pipeline { parallel "4.2-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b rodinia_2.0-ft -c ./gpgpu-sim_simulations/util/job_launching/configs/run-fermi-and-up.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -c ./gpgpu-sim_simulations/util/job_launching/configs/run-fermi-and-up.yml -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "8.0-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b rodinia_2.0-ft -c ./gpgpu-sim_simulations/util/job_launching/configs/run-fermi-and-up-noplus.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -c ./gpgpu-sim_simulations/util/job_launching/configs/run-fermi-and-up-noplus.yml -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "4.2-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -b sdk-4.2 -c ./gpgpu-sim_simulations/util/job_launching/configs/run-fermi-and-up-noplus.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -c ./gpgpu-sim_simulations/util/job_launching/configs/run-fermi-and-up-noplus.yml -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' } } -- cgit v1.3 From 88724dc5bcbf66f678d935d81b972767cd913e79 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 29 Oct 2017 01:19:21 -0400 Subject: reworking the config spec to be much simpler as well --- Jenkinsfile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 5d43e4c..4e9a74b 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -41,17 +41,17 @@ pipeline { parallel "4.2-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -c ./gpgpu-sim_simulations/util/job_launching/configs/run-fermi-and-up.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS,GTX750Ti,GTX750Ti-PTXPLUS,PASCALTITANX -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "8.0-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -c ./gpgpu-sim_simulations/util/job_launching/configs/run-fermi-and-up-noplus.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX750Ti,PASCALTITANX -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "4.2-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -c ./gpgpu-sim_simulations/util/job_launching/configs/run-fermi-and-up-noplus.yml -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480,GTX750Ti,PASCALTITANX -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' } } -- cgit v1.3 From 275e5813f4ef3ef92851d1a3752d1bffaabcdb50 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 29 Oct 2017 02:09:56 -0400 Subject: dumping the slow-ass maxwell card nobody cares about --- Jenkinsfile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 4e9a74b..bdf8294 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -41,17 +41,17 @@ pipeline { parallel "4.2-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS,GTX750Ti,GTX750Ti-PTXPLUS,PASCALTITANX -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS,PASCALTITANX,PASCALTITANX-PTXPLUS -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "8.0-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX750Ti,PASCALTITANX -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,PASCALTITANX -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "4.2-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480,GTX750Ti,PASCALTITANX -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480,PASCALTITANX -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' } } -- cgit v1.3 From c56115c9df274708ada5964f4f46e2d08b1acd03 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Sun, 29 Oct 2017 20:53:30 -0400 Subject: Update gpgpusim.config --- configs/Pascal-P100-HBM/gpgpusim.config | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config index 5b038de..0f6761d 100644 --- a/configs/Pascal-P100-HBM/gpgpusim.config +++ b/configs/Pascal-P100-HBM/gpgpusim.config @@ -58,8 +58,8 @@ -gpgpu_shmem_size 65536 -gmem_skip_L1D 0 -# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 4MB L2 cache --gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:128:4,4:0,32 +# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 4MB L2 cache +-gpgpu_cache:dl2 S:32:128:16,L:B:m:W:L,A:128:4,4:0,32 -gpgpu_cache:dl2_texture_only 0 # 4 KB Inst. -- cgit v1.3 From ff6c395da7b70d9cdbb72a8cfc3721a7f27a2a25 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Mon, 30 Oct 2017 17:08:07 -0400 Subject: Update gpgpusim.config --- configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 23 +++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 782edf6..2f09ab6 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -35,18 +35,23 @@ # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB ## Pascal GP102 has 4 SP SIMD units and 4 SFU units ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,1,4,4,1,8 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 4 +-gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 2 +-gpgpu_num_dp_units 1 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 -ptx_opcode_latency_int 4,13,4,5,145 -ptx_opcode_initiation_int 1,1,1,1,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 4,8,4,4,130 +-ptx_opcode_initiation_dp 8,8,8,8,130 +-ptx_opcode_initiation_sfu 4 +-ptx_opcode_latency_sfu 8 # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo @@ -54,21 +59,21 @@ # Pascal GP102 has 96KB Shared memory # Pascal GP102 has 64KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 98304 -gmem_skip_L1D 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 +-gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:128:8,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 # 4 KB Inst. --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 # 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 # 12 KB Const --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 +-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 # enable operand collector ## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units -- cgit v1.3 From 4aa3b5158f0e70e83cfe44dae79cd75110c52eb7 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Mon, 30 Oct 2017 17:08:45 -0400 Subject: Update gpgpusim.config --- configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 2f09ab6..7dfd6d5 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -36,8 +36,8 @@ ## Pascal GP102 has 4 SP SIMD units and 4 SFU units ## we need to scale the number of pipeline registers to be equal to the number of SP units -gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 2 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 -gpgpu_num_dp_units 1 # Instruction latencies and initiation intervals -- cgit v1.3 From c31a833b3fee9b2e618a2869b41b5cf00d856bc8 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Mon, 30 Oct 2017 17:29:24 -0400 Subject: Update Jenkinsfile --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index bdf8294..85fc8f8 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -41,7 +41,7 @@ pipeline { parallel "4.2-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS,PASCALTITANX,PASCALTITANX-PTXPLUS -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS,PASCALTITANX,PASCALTITANX-PTXPLUS,TITANX-P102 -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "8.0-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ -- cgit v1.3 From 178abb228229332c4717c5fd565a83875c3d5c9e Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Mon, 30 Oct 2017 18:51:10 -0400 Subject: Update gpgpusim.config --- configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 7dfd6d5..82dfa9a 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -32,10 +32,10 @@ -gpgpu_simd_model 1 # Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB ## Pascal GP102 has 4 SP SIMD units and 4 SFU units ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5 +-gpgpu_pipeline_widths 4,1,4,1,4,1,4,1,9 -gpgpu_num_sp_units 4 -gpgpu_num_sfu_units 4 -gpgpu_num_dp_units 1 @@ -77,15 +77,18 @@ # enable operand collector ## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units --gpgpu_operand_collector_num_units_sp 20 --gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 -gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 -gpgpu_operand_collector_num_in_ports_sp 4 -gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_sfu 4 +-gpgpu_operand_collector_num_out_ports_sfu 4 -gpgpu_operand_collector_num_in_ports_mem 1 -gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 # gpgpu_num_reg_banks should be increased to 32 -gpgpu_num_reg_banks 32 -- cgit v1.3 From 0b1a646c0ddf5d4db64a2b6fe9dfa30789cf1cd4 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 30 Oct 2017 20:23:51 -0400 Subject: adding new stats and change the PascalP100-HBM config --- configs/Pascal-P100-HBM/config_fermi_islip.icnt | 9 +++++--- configs/Pascal-P100-HBM/gpgpusim.config | 25 ++++++++++++---------- configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt | 3 +++ src/gpgpu-sim/dram.cc | 13 +++++++---- src/gpgpu-sim/dram.h | 4 ++++ src/gpgpu-sim/dram_sched.cc | 21 +++++++++++++----- src/gpgpu-sim/gpu-sim.cc | 4 +++- src/gpgpu-sim/gpu-sim.h | 8 +++++++ 8 files changed, 63 insertions(+), 24 deletions(-) diff --git a/configs/Pascal-P100-HBM/config_fermi_islip.icnt b/configs/Pascal-P100-HBM/config_fermi_islip.icnt index a788090..0a73c81 100644 --- a/configs/Pascal-P100-HBM/config_fermi_islip.icnt +++ b/configs/Pascal-P100-HBM/config_fermi_islip.icnt @@ -1,13 +1,13 @@ //21*1 fly with 32 flits per packet under gpgpusim injection mode use_map = 0; -flit_size = 32; +flit_size = 40; // currently we do not use this, see subnets below network_count = 2; // Topology topology = fly; -k = 62; +k = 60; n = 1; // Routing @@ -17,7 +17,10 @@ routing_function = dest_tag; // Flow control num_vcs = 1; -vc_buf_size = 8; +vc_buf_size = 64; +input_buffer_size = 64; +ejection_buffer_size = 64; +boundary_buffer_size = 64; wait_for_tail_credit = 0; diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config index 5b038de..1029194 100644 --- a/configs/Pascal-P100-HBM/gpgpusim.config +++ b/configs/Pascal-P100-HBM/gpgpusim.config @@ -54,13 +54,17 @@ # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. # Pascal GP100 has 64KB Shared memory --gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,S:128:8,8 +-gpgpu_cache:dl1 S:64:128:6,L:L:m:N:H,A:128:8,32:0,32 -gpgpu_shmem_size 65536 --gmem_skip_L1D 0 +-gmem_skip_L1D 1 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 -# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 4MB L2 cache --gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:128:4,4:0,32 +# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 4MB L2 cache +-gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:256:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 +#-gpgpu_flush_l2_cache 1 # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 @@ -89,8 +93,7 @@ -gpgpu_shmem_num_banks 32 -gpgpu_shmem_limited_broadcast 0 -gpgpu_shmem_warp_parts 1 -# Use Fermi Coalscer arhitetecture for now! Need to be canged to pascal Coalscer --gpgpu_coalesce_arch 20 +-gpgpu_coalesce_arch 60 ## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units -gpgpu_max_insn_issue_per_warp 2 @@ -123,10 +126,6 @@ -gpgpu_mem_address_mask 1 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS -# GDDR5 timing -#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=6:RCD=12:RAS=28:RP=12:RC=40: -# CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" - # HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) # Timing for 1 GHZ # tRRDl and tWTR are missing, need to be added @@ -140,8 +139,12 @@ # HBM has dual bus interface, in which it can issue two col and row commands at a time -dual_bus_interface 1 # select lower bits for bnkgrp to increase bnkgrp parallelism +-dram_bnk_indexing_policy 0 -dram_bnkgrp_indexing_policy 1 +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + # Pascal has two schedulers per core -gpgpu_num_sched_per_core 2 # Two Level Scheduler with active and pending pools @@ -158,7 +161,7 @@ -visualizer_enabled 0 # power model configs, disable it untill we create a real energy model for Pascal 100 --power_simulation_enabled 1 +-power_simulation_enabled 0 -gpuwattch_xml_file gpuwattch_gtx480.xml # tracing functionality diff --git a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt index 58e596d..94b2378 100644 --- a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt +++ b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt @@ -18,6 +18,9 @@ routing_function = dest_tag; num_vcs = 1; vc_buf_size = 32; +input_buffer_size = 32; +ejection_buffer_size = 32; +boundary_buffer_size = 32; wait_for_tail_credit = 0; diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc index de37f64..a57508c 100644 --- a/src/gpgpu-sim/dram.cc +++ b/src/gpgpu-sim/dram.cc @@ -52,6 +52,10 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m //rowblp access_num=0; hits_num=0; + read_num=0; + write_num=0; + hits_read_num=0; + hits_write_num=0; banks_1time=0; banks_acess_total=0; banks_acess_total_after=0; @@ -718,6 +722,8 @@ void dram_t::print( FILE* simFile) const fprintf(simFile, "\n------------------------------------------------------------------------\n"); printf("\nRow_Buffer_Locality = %.6f", (float)hits_num / access_num); + printf("\nRow_Buffer_Locality_read = %.6f", (float)hits_read_num / read_num); + printf("\nRow_Buffer_Locality_write = %.6f", (float)hits_write_num / write_num); printf("\nBank_Level_Parallism = %.6f", (float)banks_1time / banks_acess_total); printf("\nBank_Level_Parallism_Col = %.6f", (float)banks_time_rw / banks_access_rw_total); printf("\nBank_Level_Parallism_Ready = %.6f", (float)banks_time_ready /banks_access_ready_total); @@ -735,7 +741,7 @@ void dram_t::print( FILE* simFile) const printf("RCDWRc_limit = %d \n", RCDWRc_limit); printf("WTRc_limit = %d \n", WTRc_limit); printf("RTWc_limit = %d \n", RTWc_limit); - printf("CCDLc_limit %d \n", CCDLc_limit); + printf("CCDLc_limit = %d \n", CCDLc_limit); printf("rwq = %d \n", rwq_limit); printf("CCDLc_limit_alone = %d \n", CCDLc_limit_alone); printf("WTRc_limit_alone = %d \n", WTRc_limit_alone); @@ -751,15 +757,14 @@ void dram_t::print( FILE* simFile) const printf("n_pre = %d \n", n_pre); printf("n_ref = %d \n", n_ref); printf("n_req = %d \n", n_req ); - printf("n_req4 = %d \n", n_req*4 ); printf("total_req = %d \n\n", n_rd+n_wr+n_rd_L2_A+n_wr_WB); printf("issued_total_row = %lu \n", issued_total_row); printf("issued_total_col = %lu \n", issued_total_col); printf("Row_Bus_Util = %.6f \n", (float)issued_total_row / n_cmd); printf("CoL_Bus_Util = %.6f \n", (float)issued_total_col / n_cmd); - printf("Either_Row_CoL_Bus_Util %.6f \n", (float)issued_total / n_cmd); - printf("Issued_on_Two_Bus_Simul_Util %.6f \n", (float)issued_two /n_cmd); + printf("Either_Row_CoL_Bus_Util = %.6f \n", (float)issued_total / n_cmd); + printf("Issued_on_Two_Bus_Simul_Util = %.6f \n", (float)issued_two /n_cmd); printf("issued_two_Eff = %.6f \n", (float)issued_two /issued_total); printf("queue_avg = %.6f \n\n", (float)ave_mrqs/n_cmd ); diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index 29731a7..0d4c0e7 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -198,7 +198,11 @@ private: //row locality, BLP and other statistics unsigned long access_num; + unsigned long read_num; + unsigned long write_num; unsigned long long hits_num; + unsigned long long hits_read_num; + unsigned long long hits_write_num; unsigned long long banks_1time; unsigned long long banks_acess_total; unsigned long long banks_acess_total_after; diff --git a/src/gpgpu-sim/dram_sched.cc b/src/gpgpu-sim/dram_sched.cc index ac4c827..f754d36 100644 --- a/src/gpgpu-sim/dram_sched.cc +++ b/src/gpgpu-sim/dram_sched.cc @@ -142,14 +142,25 @@ dram_req_t *frfcfs_scheduler::schedule( unsigned bank, unsigned curr_row ) rowhit = true; } } - //rowblp - m_dram->access_num++; - if(rowhit) - m_dram->hits_num++; - std::list::iterator next = m_current_last_row[bank]->back(); dram_req_t *req = (*next); + //rowblp stats + m_dram->access_num++; + bool is_write = req->data->is_write(); + if(is_write) + m_dram->write_num++; + else + m_dram->read_num++; + + if(rowhit) { + m_dram->hits_num++; + if(is_write) + m_dram->hits_write_num++; + else + m_dram->hits_read_num++; + } + m_stats->concurrent_row_access[m_dram->id][bank]++; m_stats->row_access[m_dram->id][bank]++; m_current_last_row[bank]->pop_back(); diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 0e06c5c..11ac5df 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -207,6 +207,9 @@ void memory_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-Write_Queue_Size", OPT_CSTR, &write_queue_size_opt, "Write_Queue_Size", "32:28:16"); + option_parser_register(opp, "-Elimnate_rw_turnaround", OPT_BOOL, &elimnate_rw_turnaround, + "elimnate_rw_turnaround i.e set tWTR and tRTW = 0", + "0"); option_parser_register(opp, "-icnt_flit_size", OPT_UINT32, &icnt_flit_size, "icnt_flit_size", "32"); @@ -435,7 +438,6 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) option_parser_register(opp, "-gpgpu_flush_l2_cache", OPT_BOOL, &gpgpu_flush_l2_cache, "Flush L2 cache at the end of each kernel call", "0"); - option_parser_register(opp, "-gpgpu_deadlock_detect", OPT_BOOL, &gpu_deadlock_detect, "Stop the simulation at deadlock (1=on (default), 0=off)", "1"); diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 043fcee..c04648c 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -198,8 +198,14 @@ struct memory_config { bk_tag_length = i-1; assert(nbkgrp>0 && "Number of bank groups cannot be zero"); tRCDWR = tRCD-(WL+1); + if(elimnate_rw_turnaround) + { + tRTW = 0; + tWTR = 0; + } else { tRTW = (CL+(BL/data_command_freq_ratio)+2-WL); tWTR = (WL+(BL/data_command_freq_ratio)+tCDLR); + } tWTP = (WL+(BL/data_command_freq_ratio)+tWR); dram_atom_size = BL * busW * gpu_n_mem_per_ctrlr; // burst length x bus width x # chips per partition @@ -266,6 +272,8 @@ struct memory_config { unsigned nbk; + bool elimnate_rw_turnaround; + unsigned data_command_freq_ratio; // frequency ratio between DRAM data bus and command bus (2 for GDDR3, 4 for GDDR5) unsigned dram_atom_size; // number of bytes transferred per read or write command -- cgit v1.3 From 4df2f7d2499600fa0f0c5642c07fed6576aa5713 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Mon, 30 Oct 2017 22:36:16 -0400 Subject: fixing TITANX config --- configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 82dfa9a..4191eb0 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -64,16 +64,16 @@ -gmem_skip_L1D 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:128:8,4:0,32 +-gpgpu_cache:dl2 N:64:128:16,L:B:m:W:L,A:128:8,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 # 4 KB Inst. --gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 +-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,A:2:48,4 # 48 KB Tex -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 # 12 KB Const --gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 +-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,A:2:64,4 # enable operand collector ## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units -- cgit v1.3 From 8735428754d1bb944400922982f41f867f2f9b9c Mon Sep 17 00:00:00 2001 From: speverel Date: Sat, 4 Nov 2017 10:42:32 -0700 Subject: Added basic support for CUDA 9.0. --- Makefile | 1 + setup_environment | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index e83de9a..f0c3da9 100644 --- a/Makefile +++ b/Makefile @@ -161,6 +161,7 @@ $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib if [ ! -f $(SIM_LIB_DIR)/libcudart.so.6.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.6.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.7.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.7.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.8.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.8.0; fi + if [ ! -f $(SIM_LIB_DIR)/libcudart.so.9.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.9.0; fi $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib g++ -dynamiclib -Wl,-headerpad_max_install_names,-undefined,dynamic_lookup,-compatibility_version,1.1,-current_version,1.1\ diff --git a/setup_environment b/setup_environment index 854a335..0b0a6ff 100644 --- a/setup_environment +++ b/setup_environment @@ -43,7 +43,7 @@ CC_VERSION=`gcc --version | head -1 | awk '{for(i=1;i<=NF;i++){ if(match($i,/^[0 CUDA_VERSION_STRING=`$CUDA_INSTALL_PATH/bin/nvcc --version | awk '/release/ {print $5;}' | sed 's/,//'`; CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("%02u%02u", 10*int($1), 10*$2);}'` -if [ $CUDA_VERSION_NUMBER -gt 8000 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then +if [ $CUDA_VERSION_NUMBER -gt 9000 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then echo "ERROR ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; return elif [ $CUDA_VERSION_NUMBER -gt 4020 ]; then -- cgit v1.3 From 32babbbda9c589e918ac1a2436eae0fd64c70bae Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 8 Nov 2017 20:13:28 -0500 Subject: Fixing the break limit bug --- src/gpgpusim_entrypoint.cc | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index 04845e7..ad4587a 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -91,6 +91,7 @@ void *gpgpu_sim_thread_sequential(void*) pthread_mutex_t g_sim_lock = PTHREAD_MUTEX_INITIALIZER; bool g_sim_active = false; bool g_sim_done = true; +bool break_limit = false; void *gpgpu_sim_thread_concurrent(void*) { @@ -144,11 +145,13 @@ void *gpgpu_sim_thread_concurrent(void*) if(g_the_gpu->cycle_insn_cta_max_hit()){ g_stream_manager->stop_all_running_kernels(); g_sim_done = true; + break_limit = true; } } active=g_the_gpu->active() || !g_stream_manager->empty_protected(); - } while( active ); + + } while( active && !g_sim_done); if(g_debug_execution >= 3) { printf("GPGPU-Sim: ** STOP simulation thread (no work) **\n"); fflush(stdout); @@ -166,6 +169,11 @@ void *gpgpu_sim_thread_concurrent(void*) printf("GPGPU-Sim: *** simulation thread exiting ***\n"); fflush(stdout); } + if(break_limit) { + printf("GPGPU-Sim: ** break due to reaching the maximum cycles (or instructions) **\n"); + exit(1); + } + sem_post(&g_sim_signal_exit); return NULL; } @@ -179,7 +187,7 @@ void synchronize() bool done = false; do { pthread_mutex_lock(&g_sim_lock); - done = g_stream_manager->empty() && !g_sim_active; + done = ( g_stream_manager->empty() && !g_sim_active ) || g_sim_done; pthread_mutex_unlock(&g_sim_lock); } while (!done); printf("GPGPU-Sim: detected inactive GPU simulation thread\n"); -- cgit v1.3 From 7c9b838bca837a3ccea5ea30f53c1cbd8e35252c Mon Sep 17 00:00:00 2001 From: Negar Date: Sun, 12 Nov 2017 19:03:27 -0800 Subject: Fix latency bug --- bsmad_test/.gdbinit | 97 ++ bsmad_test/Makefile | 6 + bsmad_test/bsmad | Bin 0 -> 2660316 bytes bsmad_test/bsmad_result.txt | 333 ++++ bsmad_test/bsmad_test.cu | 76 + bsmad_test/bsmadoutput.txt | 3004 +++++++++++++++++++++++++++++++++++ bsmad_test/config_fermi_islip.icnt | 70 + bsmad_test/d.log | 3049 ++++++++++++++++++++++++++++++++++++ bsmad_test/gpgpu_inst_stats.txt | 26 + bsmad_test/gpgpusim.config | 149 ++ bsmad_test/gpuwattch_gtx1080Ti.xml | 538 +++++++ bsmad_test/out.txt | 1837 ++++++++++++++++++++++ bsmad_test/output | 2338 +++++++++++++++++++++++++++ bsmad_test/output.txt | 2338 +++++++++++++++++++++++++++ bsmad_test/result | 2338 +++++++++++++++++++++++++++ src/cuda-sim/cuda-sim.cc | 30 +- 16 files changed, 16216 insertions(+), 13 deletions(-) create mode 100644 bsmad_test/.gdbinit create mode 100644 bsmad_test/Makefile create mode 100755 bsmad_test/bsmad create mode 100644 bsmad_test/bsmad_result.txt create mode 100644 bsmad_test/bsmad_test.cu create mode 100644 bsmad_test/bsmadoutput.txt create mode 100644 bsmad_test/config_fermi_islip.icnt create mode 100644 bsmad_test/d.log create mode 100644 bsmad_test/gpgpu_inst_stats.txt create mode 100644 bsmad_test/gpgpusim.config create mode 100755 bsmad_test/gpuwattch_gtx1080Ti.xml create mode 100644 bsmad_test/out.txt create mode 100644 bsmad_test/output create mode 100644 bsmad_test/output.txt create mode 100644 bsmad_test/result diff --git a/bsmad_test/.gdbinit b/bsmad_test/.gdbinit new file mode 100644 index 0000000..b456895 --- /dev/null +++ b/bsmad_test/.gdbinit @@ -0,0 +1,97 @@ +# Provides some useful debugging macros. To use this file, copy to your home +# directory or to your simulation directory then run GPGPU-Sim in gdb. + +printf "\n ** loading GPGPU-Sim debugging macros... ** \n\n" + +set print pretty +set print array-indexes +set unwindonsignal on + +define dp + call g_the_gpu->dump_pipeline((0x40|0x4|0x1),$arg0,0) +end + +document dp +Usage: dp +Display pipeline state. +: index of shader core you would like to see the pipeline state of + +This function displays the state of the pipeline on a single shader core +(setting different values for the first argument of the call to +dump_pipeline will cause different information to be displayed-- +see the source code for more details) +end + +define dpc + call g_the_gpu->dump_pipeline((0x40|0x4|0x1),$arg0,0) + continue +end + +document dpc +Usage: dpc +Display pipeline state, then continue to next breakpoint. +: index of shader core you would like to see the pipeline state of + +This version is useful if you set a breakpoint where gpu_sim_cycle is +incremented in gpu_sim_loop() in src/gpgpu-sim/gpu-sim.c +repeatly hitting enter will advance to show the pipeline contents on +the next cycle. +end + +define dm + call g_the_gpu->dump_pipeline(0x10000|0x10000000,0,$arg0) +end + +define ptxdis + set $addr=$arg0 + printf "disassemble instructions from 0x%x to 0x%x\n", $arg0, $arg1 + call fflush(stdout) + while ( $addr <= $arg1 ) + printf "0x%04x (%4u) : ", $addr, $addr + call ptx_print_insn( $addr, stdout ) + call fflush(stdout) + set $addr = $addr + ptx_print_insn::size + end +end + +document ptxdis +Usage: ptxdis +Disassemble PTX instructions between and (PCs). +end + +define ptxdis_func + set $sid = $arg0 + set $cluster = g_the_gpu_config.m_shader_config.sid_to_cluster($sid) + set $cid = g_the_gpu_config.m_shader_config.sid_to_cid($sid) + set $ptx_tinfo = g_the_gpu->m_cluster[$cluster]->m_core[$cid]->m_thread[$arg1] + set $finfo = $ptx_tinfo->m_func_info + set $minpc = $finfo->m_start_PC + set $maxpc = $minpc + $finfo->m_instr_mem_size + printf "disassembly of function %s (min pc = %u, max pc = %u):\n", $finfo->m_name.c_str(), $minpc, $maxpc + ptxdis $minpc $maxpc +end + +document ptxdis_func +Usage: ptxdis_func (requires debug build) +: shader core number +: thread ID +end + +define ptx_tids2pcs + set $i = 0 + while ( $i < $arg1 ) + set $tid = $arg0[$i] + set $cluster = g_the_gpu_config.m_shader_config.sid_to_cluster($sid); + set $cid = g_the_gpu_config.m_shader_config.sid_to_cid($sid); + set $addr = g_the_gpu->m_cluster[$cluster]->m_core[$cid]->m_thread[$tid]->m_PC + printf "%2u : tid = %3u => pc = %d\n", $i, $tid, $addr + set $i = $i + 1 + end +end + +document ptx_tids2pcs +Usage: ptx_tids2pcs +: array of tids +: length of array +: shader core number +end diff --git a/bsmad_test/Makefile b/bsmad_test/Makefile new file mode 100644 index 0000000..b841c6b --- /dev/null +++ b/bsmad_test/Makefile @@ -0,0 +1,6 @@ +all: bsmad_test.cu + nvcc --gpu-architecture=compute_50 --gpu-code=compute_50 -lcudart -g -o bsmad bsmad_test.cu + +.PHONY: +clean: + rm bsmad diff --git a/bsmad_test/bsmad b/bsmad_test/bsmad new file mode 100755 index 0000000..56020ff Binary files /dev/null and b/bsmad_test/bsmad differ diff --git a/bsmad_test/bsmad_result.txt b/bsmad_test/bsmad_result.txt new file mode 100644 index 0000000..968a990 --- /dev/null +++ b/bsmad_test/bsmad_result.txt @@ -0,0 +1,333 @@ +GNU gdb (GDB) SUSE (7.5.1-2.5.1) +Copyright (C) 2012 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. Type "show copying" +and "show warranty" for details. +This GDB was configured as "x86_64-suse-linux". +For bug reporting instructions, please see: +... +Reading symbols from /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad...done. +To enable execution of this file add + add-auto-load-safe-path /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/.gdbinit +line to your configuration file "/home/negargoli93/.gdbinit". +To completely disable this security protection add + set auto-load safe-path / +line to your configuration file "/home/negargoli93/.gdbinit". +For more information about this security protection see the +"Auto-loading safe path" section in the GDB manual. E.g., run from the shell: + info "(gdb)Auto-loading safe path" +(gdb) r^C(gdb) r +Starting program: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +[Thread debugging using libthread_db enabled] +Using host libthread_db library "/lib64/libthread_db.so.1". + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-0751c1489add70d7494521c7f9d65f462e4391c6_modified_0] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace[New Thread 0x7ffff4512700 (LWP 5117)] +[Thread 0x7ffff4512700 (LWP 5117) exited] +[New Thread 0x7ffff4512700 (LWP 5120)] + +Program received signal SIGINT, Interrupt. +0x00007ffff6f78fef in pthread_join () from /lib64/libpthread.so.0 +Missing separate debuginfos, use: zypper install Mesa-libGL1-debuginfo-8.0.4-20.27.1.x86_64 Mesa-libglapi0-debuginfo-8.0.4-20.27.1.x86_64 glibc-debuginfo-2.15-22.17.1.x86_64 libX11-6-debuginfo-1.5.0-2.7.1.x86_64 libX11-xcb1-debuginfo-1.5.0-2.7.1.x86_64 libXau6-debuginfo-1.0.7-2.1.2.x86_64 libXdamage1-debuginfo-1.1.3-2.1.2.x86_64 libXext6-debuginfo-1.3.1-2.4.1.x86_64 libXfixes3-debuginfo-5.0-2.4.1.x86_64 libXxf86vm1-debuginfo-1.1.2-2.7.1.x86_64 libdrm2-debuginfo-2.4.33-2.3.2.x86_64 libgcc47-debuginfo-4.7.1_20120723-1.1.1.x86_64 libstdc++47-debuginfo-4.7.1_20120723-1.1.1.x86_64 libxcb-glx0-debuginfo-1.8.1-2.8.1.x86_64 libxcb1-debuginfo-1.8.1-2.8.1.x86_64 zlib-debuginfo-1.2.7-2.1.2.x86_64 +(gdb) +(gdb) quit +A debugging session is active. + + Inferior 1 [process 5113] will be killed. + +Quit anyway? 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(y or n) EOF [assumed Y] diff --git a/bsmad_test/bsmad_test.cu b/bsmad_test/bsmad_test.cu new file mode 100644 index 0000000..9be6e74 --- /dev/null +++ b/bsmad_test/bsmad_test.cu @@ -0,0 +1,76 @@ +#include +#define SIZE 1024 +#define THREADS_PER_BLOCK 32 +#define PART_THREADS 1 +#define NUM_BLOCKS 1 +#define I_PREC 4 +#define O_PREC 4 + +__global__ void vector_add(int* A, int* B, int* res) +{ + int tid = threadIdx.x + blockIdx.x * blockDim.x; + res[tid] = A[tid] + B[tid]; +} + +__global__ void digit_serial_mad(unsigned* i_buffer, unsigned* i_synapse, unsigned* result, unsigned* accum) +{ + unsigned tid = threadIdx.x + blockIdx.x * blockDim.x; + unsigned buffer; + unsigned synapse; + if (tid < PART_THREADS) + { + buffer = i_buffer[tid]; + synapse = i_synapse[tid]; + } + + asm("/*"); + asm("CPTX_BEGIN"); + asm("bsmad.s32 %0, %1, %2, %3, %4, %5, %6, %7, %8;" : "=r"(result[tid]) : + "r"(I_PREC), "r"(O_PREC), "r"(buffer), "r"(0), "r"(0), "r"(0), "r"(synapse), "r"(accum[tid])); + asm("CPTX_END"); + asm("*/"); +} + +int main() +{ + // host values + unsigned *buffer = (unsigned*)malloc(sizeof(unsigned)); + unsigned *synapse = (unsigned*)malloc(sizeof(unsigned)); + unsigned *result = (unsigned*)calloc(THREADS_PER_BLOCK, sizeof(unsigned)); + unsigned *accum = (unsigned*)calloc(THREADS_PER_BLOCK, sizeof(unsigned)); + // assign host values + *buffer = 0x5000003F; + *synapse = 0x00000002; + *accum = 0; + // device pointers + unsigned *d_buffer; + unsigned *d_synapse; + unsigned *d_result; + unsigned *d_accum; + // allocate device memory + cudaMalloc(&d_buffer, sizeof(unsigned)); + cudaMalloc(&d_synapse, sizeof(unsigned)); + cudaMalloc(&d_result, sizeof(unsigned)); + cudaMalloc(&d_accum, sizeof(unsigned)); + // copy data to device + cudaMemcpy(d_buffer, buffer, sizeof(unsigned), cudaMemcpyHostToDevice); + cudaMemcpy(d_synapse, synapse, sizeof(unsigned), cudaMemcpyHostToDevice); + cudaMemcpy(d_result, result, sizeof(unsigned) * THREADS_PER_BLOCK, cudaMemcpyHostToDevice); + cudaMemcpy(d_accum, accum, sizeof(unsigned) * THREADS_PER_BLOCK, cudaMemcpyHostToDevice); + // call kernel + digit_serial_mad<<>>(d_buffer, d_synapse, d_result, d_accum); + // copy data back to host + cudaMemcpy(result, d_result, sizeof(unsigned) * THREADS_PER_BLOCK, cudaMemcpyDeviceToHost); + // read out result + printf("Result: %#X\n", result[0]); + // clean up device memory + cudaFree(d_buffer); + cudaFree(d_synapse); + cudaFree(d_result); + cudaFree(d_accum); + // clean up host memory + free(buffer); + free(synapse); + free(result); + free(accum); +} diff --git a/bsmad_test/bsmadoutput.txt b/bsmad_test/bsmadoutput.txt new file mode 100644 index 0000000..7c5f9d5 --- /dev/null +++ b/bsmad_test/bsmadoutput.txt @@ -0,0 +1,3004 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4 # Opcode latencies for integers Default 1,1,19,25,145,1 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +057a78a8e028f9794c162a7c4e45415d /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_A4Dkbu +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_3lcy4c" +Running: cat _ptx_3lcy4c | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_6DnMXV +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_6DnMXV --output-file /dev/null 2> _ptx_3lcy4cinfo" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_3lcy4c _ptx2_6DnMXV _ptx_3lcy4cinfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 + 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) +bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 17:28:53 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA +GPGPU-Sim uArch: Shader 1 finished CTA #0 (1081,0), 0 CTAs running +GPGPU-Sim uArch: Shader 1 empty (last released kernel 1 '_Z16digit_serial_madPjS_S_S_'). +GPGPU-Sim uArch: GPU detected kernel 1 '_Z16digit_serial_madPjS_S_S_' finished on shader 1. +Destroy streams for kernel 1: size 0 +kernel_name = _Z16digit_serial_madPjS_S_S_ +kernel_launch_uid = 1 +gpu_sim_cycle = 1082 +gpu_sim_insn = 675 +gpu_ipc = 0.6238 +gpu_tot_sim_cycle = 1082 +gpu_tot_sim_insn = 675 +gpu_tot_ipc = 0.6238 +gpu_tot_issued_cta = 1 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=675 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 13 + L1I_total_cache_misses = 2 + L1I_total_cache_miss_rate = 0.1538 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 4 + L1C_total_cache_misses = 4 + L1C_total_cache_miss_rate = 1.0000 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 800 +gpgpu_n_tot_w_icount = 25 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 3 +gpgpu_n_mem_write_global = 1 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 1 +gpgpu_n_load_insn = 34 +gpgpu_n_store_insn = 32 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 128 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:1902 W0_Scoreboard:294 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 +traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} +traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} +traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} +traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} +maxmrqlatency = 7 +maxdqlatency = 0 +maxmflatency = 252 +averagemflatency = 250 +max_icnt2mem_latency = 6 +max_icnt2sh_latency = 1081 +mrq_lat_table:7 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 4 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 750 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 759 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1066 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1038 0 0 0 0 228 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 2.000000 -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan 1.000000 +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 8/6 = 1.333333 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 7 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 1 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 252 none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none 250 none none none none none +dram[2]: none none none none none none none none none none 250 none none none none none +dram[3]: none none none none none none none none none none 122 none none none none none +dram[4]: none none none none none none none none none none 252 none none none none 0 +dram[5]: none none none none none none none none none none none none none none 0 none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 244 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 252 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 +n_activity=40 dram_eff=0.2 +bk0: 4a 1989i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 +n_activity=40 dram_eff=0.2 +bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 4a 1989i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 0a 2007i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 +n_activity=40 dram_eff=0.2 +bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 4a 1989i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 0a 2007i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents +MSHR: tag=0x3e20200, atomic=0 1 entries : 0x7f51d804c750 : mf: uid= 22, sid01:w00, part=3, addr=0x3e20200, load , size=128, unknown status = IN_PARTITION_DRAM (1081), + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2000 n_act=1 n_pre=0 n_req=2 n_rd=3 n_write=4 bw_util=0.006972 +n_activity=29 dram_eff=0.4828 +bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 3a 1979i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 0a 2007i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=1 avg=0.0059761 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=1998 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007968 +n_activity=80 dram_eff=0.2 +bk0: 0a 2006i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2009i bk6: 0a 2009i bk7: 0a 2009i bk8: 0a 2009i bk9: 0a 2009i bk10: 4a 1989i bk11: 0a 2007i bk12: 0a 2007i bk13: 0a 2007i bk14: 0a 2007i bk15: 4a 1988i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2003 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003984 +n_activity=40 dram_eff=0.2 +bk0: 0a 2007i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2009i bk14: 4a 1989i bk15: 0a 2007i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2008 n_nop=2008 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2008i bk1: 0a 2008i bk2: 0a 2008i bk3: 0a 2008i bk4: 0a 2008i bk5: 0a 2008i bk6: 0a 2008i bk7: 0a 2008i bk8: 0a 2008i bk9: 0a 2008i bk10: 0a 2008i bk11: 0a 2008i bk12: 0a 2008i bk13: 0a 2008i bk14: 0a 2008i bk15: 0a 2008i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 7 +L2_total_cache_misses = 7 +L2_total_cache_miss_rate = 1.0000 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 3 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 1 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.001 + +icnt_total_pkts_mem_to_simt=23 +icnt_total_pkts_simt_to_mem=11 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = 7.42857 + minimum = 6 + maximum = 10 +Network latency average = 7.42857 + minimum = 6 + maximum = 10 +Slowest packet = 1 +Flit latency average = 6 + minimum = 6 + maximum = 6 +Slowest flit = 0 +Fragmentation average = 0 + minimum = 0 + maximum = 0 +Injected packet rate average = 0.00012951 + minimum = 0 (at node 0) + maximum = 0.00323774 (at node 1) +Accepted packet rate average = 0.00012951 + minimum = 0 (at node 0) + maximum = 0.00323774 (at node 1) +Injected flit rate average = 0.000314524 + minimum = 0 (at node 0) + maximum = 0.00508788 (at node 1) +Accepted flit rate average= 0.000314524 + minimum = 0 (at node 0) + maximum = 0.0106383 (at node 1) +Injected packet length average = 2.42857 +Accepted packet length average = 2.42857 +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Network latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Flit latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Fragmentation average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Injected packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected packet size average = -nan (5 samples) +Accepted packet size average = -nan (5 samples) +Hops average = -nan (5 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- + + +gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 1 sec (1 sec) +gpgpu_simulation_rate = 675 (inst/sec) +gpgpu_simulation_rate = 1082 (cycle/sec) +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 1082 +gpu_tot_sim_insn = 675 +gpu_tot_ipc = 0.6238 +gpu_tot_issued_cta = 1 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=675 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 13 + L1I_total_cache_misses = 2 + L1I_total_cache_miss_rate = 0.1538 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 4 + L1C_total_cache_misses = 4 + L1C_total_cache_miss_rate = 1.0000 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 800 +gpgpu_n_tot_w_icount = 25 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 3 +gpgpu_n_mem_write_global = 1 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 1 +gpgpu_n_load_insn = 34 +gpgpu_n_store_insn = 32 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 128 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:1902 W0_Scoreboard:294 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 +traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} +traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} +traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} +traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} +Result: 0XA000006F diff --git a/bsmad_test/config_fermi_islip.icnt b/bsmad_test/config_fermi_islip.icnt new file mode 100644 index 0000000..2a69ddd --- /dev/null +++ b/bsmad_test/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 50; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/bsmad_test/d.log b/bsmad_test/d.log new file mode 100644 index 0000000..50ba43f --- /dev/null +++ b/bsmad_test/d.log @@ -0,0 +1,3049 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers Default 1,1,19,25,145,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +e1ffbb239b1e632822e743b7e0c60b46 /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_8Ypfya +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_CMkVsP" +Running: cat _ptx_CMkVsP | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_bVrCnu +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_bVrCnu --output-file /dev/null 2> _ptx_CMkVsPinfo" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_CMkVsP _ptx2_bVrCnu _ptx_CMkVsPinfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +Number of Memory Banks Accessed per Memory Operation per Warp (from 0): +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Average # of Memory Banks Accessed per Memory Operation per Warp=-nan + +position of mrq chosen +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +average position of mrq chosen = -nan +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +Number of Memory Banks Accessed per Memory Operation per Warp (from 0): +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Average # of Memory Banks Accessed per Memory Operation per Warp=-nan + +position of mrq chosen +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +average position of mrq chosen = -nan +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +Number of Memory Banks Accessed per Memory Operation per Warp (from 0): +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Average # of Memory Banks Accessed per Memory Operation per Warp=-nan + +position of mrq chosen +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +average position of mrq chosen = -nan +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 + +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) + -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +Number of Memory Banks Accessed per Memory Operation per Warp (from 0): +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Average # of Memory Banks Accessed per Memory Operation per Warp=-nan + +position of mrq chosen +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +average position of mrq chosen = -nan +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 18:22:19 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA +GPGPU-Sim uArch: Shader 1 finished CTA #0 (1079,0), 0 CTAs running +GPGPU-Sim uArch: Shader 1 empty (last released kernel 1 '_Z16digit_serial_madPjS_S_S_'). +GPGPU-Sim uArch: GPU detected kernel 1 '_Z16digit_serial_madPjS_S_S_' finished on shader 1. +Destroy streams for kernel 1: size 0 +kernel_name = _Z16digit_serial_madPjS_S_S_ +kernel_launch_uid = 1 +gpu_sim_cycle = 1080 +gpu_sim_insn = 675 +gpu_ipc = 0.6250 +gpu_tot_sim_cycle = 1080 +gpu_tot_sim_insn = 675 +gpu_tot_ipc = 0.6250 +gpu_tot_issued_cta = 1 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=675 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 13 + L1I_total_cache_misses = 2 + L1I_total_cache_miss_rate = 0.1538 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 4 + L1C_total_cache_misses = 4 + L1C_total_cache_miss_rate = 1.0000 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 800 +gpgpu_n_tot_w_icount = 25 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 3 +gpgpu_n_mem_write_global = 1 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 1 +gpgpu_n_load_insn = 34 +gpgpu_n_store_insn = 32 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 128 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:1900 W0_Scoreboard:292 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 +traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} +traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} +traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} +traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} +maxmrqlatency = 7 +maxdqlatency = 0 +maxmflatency = 252 +averagemflatency = 250 +max_icnt2mem_latency = 6 +max_icnt2sh_latency = 1079 +mrq_lat_table:7 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 4 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 750 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 759 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1064 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1038 0 0 0 0 228 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: inf -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 2.000000 -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan -nan -nan -nan 1.000000 +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan 1.000000 -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 8/6 = 1.333333 +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 7 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 1 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: 252 none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none 250 none none none none none +dram[2]: none none none none none none none none none none 250 none none none none none +dram[3]: none none none none none none none none none none 122 none none none none none +dram[4]: none none none none none none none none none none 252 none none none none 0 +dram[5]: none none none none none none none none none none none none none none 0 none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 250 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 244 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 252 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +Number of Memory Banks Accessed per Memory Operation per Warp (from 0): +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Average # of Memory Banks Accessed per Memory Operation per Warp=-nan + +position of mrq chosen +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + +average position of mrq chosen = -nan +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 +n_activity=40 dram_eff=0.2 +bk0: 4a 1985i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 +n_activity=40 dram_eff=0.2 +bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 +n_activity=40 dram_eff=0.2 +bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 3: +Cache L2_bank_006: +MSHR contents +MSHR: tag=0x3e20200, atomic=0 1 entries : 0x7f6d3018f8f0 : mf: uid= 22, sid01:w00, part=3, addr=0x3e20200, load , size=128, unknown status = IN_PARTITION_DRAM (1079), + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1996 n_act=1 n_pre=0 n_req=2 n_rd=3 n_write=4 bw_util=0.006986 +n_activity=29 dram_eff=0.4828 +bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 3a 1975i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 0a 2003i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=1 avg=0.00598802 +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1994 n_act=2 n_pre=0 n_req=2 n_rd=8 n_write=0 bw_util=0.007984 +n_activity=80 dram_eff=0.2 +bk0: 0a 2002i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2005i bk6: 0a 2005i bk7: 0a 2005i bk8: 0a 2005i bk9: 0a 2005i bk10: 4a 1985i bk11: 0a 2003i bk12: 0a 2003i bk13: 0a 2003i bk14: 0a 2003i bk15: 4a 1984i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=1999 n_act=1 n_pre=0 n_req=1 n_rd=4 n_write=0 bw_util=0.003992 +n_activity=40 dram_eff=0.2 +bk0: 0a 2003i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2005i bk14: 4a 1985i bk15: 0a 2003i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=2004 n_nop=2004 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=0 +n_activity=0 dram_eff=-nan +bk0: 0a 2004i bk1: 0a 2004i bk2: 0a 2004i bk3: 0a 2004i bk4: 0a 2004i bk5: 0a 2004i bk6: 0a 2004i bk7: 0a 2004i bk8: 0a 2004i bk9: 0a 2004i bk10: 0a 2004i bk11: 0a 2004i bk12: 0a 2004i bk13: 0a 2004i bk14: 0a 2004i bk15: 0a 2004i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=0 + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 1, Miss = 1, Miss_rate = 1.000, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 7 +L2_total_cache_misses = 7 +L2_total_cache_miss_rate = 1.0000 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: + L2_cache_stats_breakdown[GLOBAL_ACC_R][MISS] = 3 + L2_cache_stats_breakdown[CONST_ACC_R][MISS] = 1 + L2_cache_stats_breakdown[GLOBAL_ACC_W][MISS] = 1 + L2_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.001 + +icnt_total_pkts_mem_to_simt=23 +icnt_total_pkts_simt_to_mem=11 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = 7.42857 + minimum = 6 + maximum = 10 +Network latency average = 7.42857 + minimum = 6 + maximum = 10 +Slowest packet = 1 +Flit latency average = 6 + minimum = 6 + maximum = 6 +Slowest flit = 0 +Fragmentation average = 0 + minimum = 0 + maximum = 0 +Injected packet rate average = 0.00012975 + minimum = 0 (at node 0) + maximum = 0.00324374 (at node 1) +Accepted packet rate average = 0.00012975 + minimum = 0 (at node 0) + maximum = 0.00324374 (at node 1) +Injected flit rate average = 0.000315107 + minimum = 0 (at node 0) + maximum = 0.00509731 (at node 1) +Accepted flit rate average= 0.000315107 + minimum = 0 (at node 0) + maximum = 0.010658 (at node 1) +Injected packet length average = 2.42857 +Accepted packet length average = 2.42857 +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Network latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Flit latency average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Fragmentation average = -nan (5 samples) + minimum = nan (5 samples) + maximum = -nan (5 samples) +Injected packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted packet rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Accepted flit rate average = -nan (5 samples) + minimum = -nan (5 samples) + maximum = -nan (5 samples) +Injected packet size average = -nan (5 samples) +Accepted packet size average = -nan (5 samples) +Hops average = -nan (5 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- + + +gpgpu_simulation_time = 0 days, 0 hrs, 0 min, 1 sec (1 sec) +gpgpu_simulation_rate = 675 (inst/sec) +gpgpu_simulation_rate = 1080 (cycle/sec) +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 1080 +gpu_tot_sim_insn = 675 +gpu_tot_ipc = 0.6250 +gpu_tot_issued_cta = 1 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=675 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 13 + L1I_total_cache_misses = 2 + L1I_total_cache_miss_rate = 0.1538 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +Result: 0XA000006F + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 4 + L1C_total_cache_misses = 4 + L1C_total_cache_miss_rate = 1.0000 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: + Total_core_cache_stats_breakdown[CONST_ACC_R][MISS] = 4 + Total_core_cache_stats_breakdown[INST_ACC_R][HIT] = 11 + Total_core_cache_stats_breakdown[INST_ACC_R][MISS] = 2 +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 800 +gpgpu_n_tot_w_icount = 25 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 3 +gpgpu_n_mem_write_global = 1 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 1 +gpgpu_n_load_insn = 34 +gpgpu_n_store_insn = 32 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 128 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:1900 W0_Scoreboard:292 W1:4 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:21 +traffic_breakdown_coretomem[CONST_ACC_R] = 8 {8:1,} +traffic_breakdown_coretomem[GLOBAL_ACC_R] = 24 {8:3,} +traffic_breakdown_coretomem[GLOBAL_ACC_W] = 136 {136:1,} +traffic_breakdown_coretomem[INST_ACC_R] = 16 {8:2,} +traffic_breakdown_memtocore[CONST_ACC_R] = 72 {72:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_R] = 216 {40:2,136:1,} +traffic_breakdown_memtocore[GLOBAL_ACC_W] = 8 {8:1,} +traffic_breakdown_memtocore[INST_ACC_R] = 272 {136:2,} diff --git a/bsmad_test/gpgpu_inst_stats.txt b/bsmad_test/gpgpu_inst_stats.txt new file mode 100644 index 0000000..96fa69d --- /dev/null +++ b/bsmad_test/gpgpu_inst_stats.txt @@ -0,0 +1,26 @@ +kernel line : count latency dram_traffic smem_bk_conflicts smem_warp gmem_access_generated gmem_warp exposed_latency warp_divergence +_1.ptx 92 : 32 160 128 0 0 1 1 0 0 +_1.ptx 90 : 32 448 0 0 0 0 0 0 0 +_1.ptx 67 : 32 186 0 0 0 0 0 0 1 +_1.ptx 66 : 32 224 0 0 0 0 0 0 0 +_1.ptx 65 : 32 416 0 0 0 0 0 0 0 +_1.ptx 88 : 32 192 0 0 0 0 0 0 0 +_1.ptx 64 : 32 192 0 0 0 0 0 0 0 +_1.ptx 87 : 32 192 0 0 0 0 0 0 0 +_1.ptx 63 : 32 192 0 0 0 0 0 0 0 +_1.ptx 86 : 32 8256 128 0 0 1 1 0 0 +_1.ptx 99 : 32 192 0 0 0 0 0 0 0 +_1.ptx 62 : 32 192 0 0 0 0 0 0 0 +_1.ptx 85 : 32 352 0 0 0 0 0 0 0 +_1.ptx 61 : 32 8192 0 0 0 0 0 0 0 +_1.ptx 84 : 32 352 0 0 0 0 0 0 0 +_1.ptx 60 : 32 8192 0 0 0 0 0 0 0 +_1.ptx 83 : 32 320 0 0 0 0 0 0 0 +_1.ptx 59 : 32 8224 0 0 0 0 0 0 0 +_1.ptx 58 : 32 8224 128 0 0 0 0 0 0 +_1.ptx 69 : 1 7 0 0 0 0 0 0 0 +_1.ptx 70 : 1 256 128 0 0 1 1 0 0 +_1.ptx 71 : 1 7 0 0 0 0 0 0 0 +_1.ptx 72 : 1 256 128 0 0 1 1 0 0 +_1.ptx 75 : 32 224 0 0 0 0 0 0 0 +_1.ptx 76 : 32 224 0 0 0 0 0 0 0 diff --git a/bsmad_test/gpgpusim.config b/bsmad_test/gpgpusim.config new file mode 100644 index 0000000..6b512ba --- /dev/null +++ b/bsmad_test/gpgpusim.config @@ -0,0 +1,149 @@ +# This config models the Pascal GP102 (GeForceGTX 1080Ti) + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 60 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 11 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145,4,4 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 1,2,1,1,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The default is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_shmem_size 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 +-gpgpu_cache:dl2_texture_only 0 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +# gpgpu_num_reg_banks should be increased to 32, but it gives an error! +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) +# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" + +# Pascal has four schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/bsmad_test/gpuwattch_gtx1080Ti.xml b/bsmad_test/gpuwattch_gtx1080Ti.xml new file mode 100755 index 0000000..02619ff --- /dev/null +++ b/bsmad_test/gpuwattch_gtx1080Ti.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsmad_test/out.txt b/bsmad_test/out.txt new file mode 100644 index 0000000..4e95cb1 --- /dev/null +++ b/bsmad_test/out.txt @@ -0,0 +1,1837 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers Default 1,1,19,25,145,1 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +1739ba94823ccfb8e12f742738e8e16e /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_leydyg +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_8pgp00" +Running: cat _ptx_8pgp00 | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_ZhKBsL +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_ZhKBsL --output-file /dev/null 2> _ptx_8pgp00info" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_8pgp00 _ptx2_ZhKBsL _ptx_8pgp00info" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 +bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 16:03:17 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/bsmad_test/output b/bsmad_test/output new file mode 100644 index 0000000..db0d524 --- /dev/null +++ b/bsmad_test/output @@ -0,0 +1,2338 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers Default 1,1,19,25,145,1 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +733602e7cd2fc7896e7fece60068330a /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_Fvj0UD +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_qiCCrA" +Running: cat _ptx_qiCCrA | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_zIGfYw +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_zIGfYw --output-file /dev/null 2> _ptx_qiCCrAinfo" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_qiCCrA _ptx2_zIGfYw _ptx_qiCCrAinfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 13:33:51 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/bsmad_test/output.txt b/bsmad_test/output.txt new file mode 100644 index 0000000..7414f61 --- /dev/null +++ b/bsmad_test/output.txt @@ -0,0 +1,2338 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers Default 1,1,19,25,145,1 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +1739ba94823ccfb8e12f742738e8e16e /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_r35nHZ +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_hSOoDH" +Running: cat _ptx_hSOoDH | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_FSgqzp +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_FSgqzp --output-file /dev/null 2> _ptx_hSOoDHinfo" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_hSOoDH _ptx2_FSgqzp _ptx_hSOoDHinfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 + +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) + 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 16:02:01 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/bsmad_test/result b/bsmad_test/result new file mode 100644 index 0000000..210fed9 --- /dev/null +++ b/bsmad_test/result @@ -0,0 +1,2338 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-8735428754d1bb944400922982f41f867f2f9b9c_modified_1] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 60 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 28 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,4,4 # Opcode latencies for integers Default 1,1,19,25,145,1 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,4,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 28 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 +1739ba94823ccfb8e12f742738e8e16e /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad +Running md5sum using "md5sum /home/negargoli93/Perforce/gpgpu_sim_research/GPU-ML/gpgpu-sim_samples/scott_samples/bsmad " +Parsing file _cuobjdump_complete_output_ppZXax +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_50 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z16digit_serial_madPjS_S_S_ : hostFun 0x0x401372, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 50 +GPGPU-Sim PTX: instruction assembly for function '_Z10vector_addPiS_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z10vector_addPiS_S_'... +GPGPU-Sim PTX: reconvergence points for _Z10vector_addPiS_S_... +GPGPU-Sim PTX: ... end of reconvergence points for _Z10vector_addPiS_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z10vector_addPiS_S_'. +BEGINNING CUSTOM PTX. +ENDING CUSTOM PTX. +GPGPU-Sim PTX: instruction assembly for function '_Z16digit_serial_madPjS_S_S_'... done. +GPGPU-Sim PTX: finding reconvergence points for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate dominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: Finding immediate postdominators for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'... +GPGPU-Sim PTX: reconvergence points for _Z16digit_serial_madPjS_S_S_... +GPGPU-Sim PTX: 1 (potential) branch divergence @ PC=0x0e0 (_1.ptx:67) @%p1 bra BB1_2; +GPGPU-Sim PTX: immediate post dominator @ PC=0x108 (_1.ptx:75) cvta.to.global.u64 %rd7, %rd3; +GPGPU-Sim PTX: ... end of reconvergence points for _Z16digit_serial_madPjS_S_S_ +GPGPU-Sim PTX: ... done pre-decoding instructions for '_Z16digit_serial_madPjS_S_S_'. +GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file _1.ptx +Adding _cuobjdump_1.ptx with cubin handle 1 +GPGPU-Sim PTX: extracting embedded .ptx to temporary file "_ptx_D0f3bm" +Running: cat _ptx_D0f3bm | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\(\.extern \.const\[1\] .b8 \w\+\)\[\]/\1\[1\]/' | sed 's/const\[.\]/const\[0\]/g' > _ptx2_ctl9cb +GPGPU-Sim PTX: generating ptxinfo using "$CUDA_INSTALL_PATH/bin/ptxas --gpu-name=sm_50 -v _ptx2_ctl9cb --output-file /dev/null 2> _ptx_D0f3bminfo" +GPGPU-Sim PTX: Kernel '_Z16digit_serial_madPjS_S_S_' : regs=4, lmem=0, smem=0, cmem=352 +GPGPU-Sim PTX: Kernel '_Z10vector_addPiS_S_' : regs=8, lmem=0, smem=0, cmem=344 +GPGPU-Sim PTX: removing ptxinfo using "rm -f _ptx_D0f3bm _ptx2_ctl9cb _ptx_D0f3bminfo" +GPGPU-Sim PTX: loading globals with explicit initializers... +GPGPU-Sim PTX: finished loading globals (0 bytes total). +GPGPU-Sim PTX: loading constants with explicit initializers... done. +GPGPU-Sim PTX: __cudaRegisterFunction _Z10vector_addPiS_S_ : hostFun 0x0x40128e, fat_cubin_handle = 1 +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 2, filename=default +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4022b0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402540, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4027d0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402a60, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402cf0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x402f80, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403210, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4034a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceImLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403720, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4039a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403c20, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x403ea0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi1ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4043a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi1ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x404620, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi1EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ : hostFun 0x0x4048a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memcpy_3d_deviceIjLi0ELi0ELi0EEvPKhPhT_S3_S3_S3_S3_S3_S3_jjjjjjjjS3_S1_S2_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ac0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404ce0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x404f00, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405120, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405340, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405560, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405780, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x4059a0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceImLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405bc0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x405de0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406000, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406220, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi1ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406440, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406660, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi1ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406880, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi1EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterFunction __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ : hostFun 0x0x406aa0, fat_cubin_handle = 2 +Warning: cannot find deviceFun __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37__Z16memset_3d_deviceIjLi0ELi0ELi0EEvPhhjT_S1_S1_S1_S1_jjjjjjjS1_S0_ +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680180; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x6801c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_set_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680200; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel32 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680240; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 64 bytes +GPGPU-Sim PTX registering constant __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cpy_kernel64 (64 bytes) to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x67f5c0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 1944 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorTableArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680160; deviceAddress = cudartErrorTable; deviceName = cudartErrorTable +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorTable hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a80; deviceAddress = cudartErrorTableEntryCount; deviceName = cudartErrorTableEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorTableEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409aa0; deviceAddress = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr; deviceName = __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 104 bytes +GPGPU-Sim PTX registering global __nv_static_79__66_tmpxft_00001a84_00000000_17_cuda_device_runtime_compute_61_cpp1_ii_8b1a5d37_cudartErrorCnpMapArr hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680168; deviceAddress = cudartErrorCnpMap; deviceName = cudartErrorCnpMap +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 8 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMap hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x409a84; deviceAddress = cudartErrorCnpMapEntryCount; deviceName = cudartErrorCnpMapEntryCount +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global cudartErrorCnpMapEntryCount hostVar to name mapping +GPGPU-Sim PTX: __cudaRegisterVar: hostVar = 0x680170; deviceAddress = __CNPRT_VERSION_NUMBER__; deviceName = __CNPRT_VERSION_NUMBER__ +GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of 4 bytes +GPGPU-Sim PTX registering global __CNPRT_VERSION_NUMBER__ hostVar to name mapping +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Network latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Flit latency average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Fragmentation average = -nan (1 samples) + minimum = nan (1 samples) + maximum = -nan (1 samples) +Injected packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted packet rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Accepted flit rate average = -nan (1 samples) + minimum = -nan (1 samples) + maximum = -nan (1 samples) +Injected packet size average = -nan (1 samples) +Accepted packet size average = -nan (1 samples) +Hops average = -nan (1 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Network latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Flit latency average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Fragmentation average = -nan (2 samples) + minimum = nan (2 samples) + maximum = -nan (2 samples) +Injected packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted packet rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Accepted flit rate average = -nan (2 samples) + minimum = -nan (2 samples) + maximum = -nan (2 samples) +Injected packet size average = -nan (2 samples) +Accepted packet size average = -nan (2 samples) +Hops average = -nan (2 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Network latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Flit latency average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Fragmentation average = -nan (3 samples) + minimum = nan (3 samples) + maximum = -nan (3 samples) +Injected packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted packet rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Accepted flit rate average = -nan (3 samples) + minimum = -nan (3 samples) + maximum = -nan (3 samples) +Injected packet size average = -nan (3 samples) +Accepted packet size average = -nan (3 samples) +Hops average = -nan (3 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +kernel_name = +kernel_launch_uid = +gpu_sim_cycle = 0 +gpu_sim_insn = 0 +gpu_ipc = -nan +gpu_tot_sim_cycle = 0 +gpu_tot_sim_insn = 0 +gpu_tot_ipc = -nan +gpu_tot_issued_cta = 0 +max_total_param_size = 0 +gpu_stall_dramfull = 0 +gpu_stall_icnt2sh = 0 +gpu_total_sim_rate=0 + +========= Core cache stats ========= +L1I_cache: + +GPGPU-Sim PTX: cudaLaunch for 0x0x401372 (mode=performance simulation) on stream 0 + L1I_total_cache_accesses = 0 + L1I_total_cache_misses = 0 + L1I_total_cache_pending_hits = 0 + L1I_total_cache_reservation_fails = 0 +L1D_cache: + L1D_cache_core[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[22]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[23]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[24]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[25]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[26]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_cache_core[27]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 + L1D_total_cache_accesses = 0 + L1D_total_cache_misses = 0 + L1D_total_cache_pending_hits = 0 + L1D_total_cache_reservation_fails = 0 + L1D_cache_data_port_util = 0.000 + L1D_cache_fill_port_util = 0.000 +L1C_cache: + L1C_total_cache_accesses = 0 + L1C_total_cache_misses = 0 + L1C_total_cache_pending_hits = 0 + L1C_total_cache_reservation_fails = 0 +L1T_cache: + L1T_total_cache_accesses = 0 + L1T_total_cache_misses = 0 + L1T_total_cache_pending_hits = 0 + L1T_total_cache_reservation_fails = 0 + +Total_core_cache_stats: +Shader 0 warp_id issue ditsribution: +warp_id: + +distro: + +gpgpu_n_tot_thrd_icount = 0 +gpgpu_n_tot_w_icount = 0 +gpgpu_n_stall_shd_mem = 0 +gpgpu_n_mem_read_local = 0 +gpgpu_n_mem_write_local = 0 +gpgpu_n_mem_read_global = 0 +gpgpu_n_mem_write_global = 0 +gpgpu_n_mem_texture = 0 +gpgpu_n_mem_const = 0 +gpgpu_n_load_insn = 0 +gpgpu_n_store_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_shmem_insn = 0 +gpgpu_n_tex_insn = 0 +gpgpu_n_const_mem_insn = 0 +gpgpu_n_param_mem_insn = 0 +gpgpu_n_shmem_bkconflict = 0 +gpgpu_n_cache_bkconflict = 0 +gpgpu_n_intrawarp_mshr_merge = 0 +gpgpu_n_cmem_portconflict = 0 +gpgpu_stall_shd_mem[c_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[c_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[c_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[c_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[t_mem][mshr_rc] = 0 +gpgpu_stall_shd_mem[t_mem][icnt_rc] = 0 +gpgpu_stall_shd_mem[t_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[s_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][bk_conf] = 0 +gpgpu_stall_shd_mem[gl_mem][coal_stall] = 0 +gpgpu_stall_shd_mem[gl_mem][data_port_stall] = 0 +gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = 0 +gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = 0 +gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = 0 +gpu_reg_bank_conflict_stalls = 0 +Warp Occupancy Distribution: +Stall:0 W0_Idle:0 W0_Scoreboard:0 W1:0 W2:0 W3:0 W4:0 W5:0 W6:0 W7:0 W8:0 W9:0 W10:0 W11:0 W12:0 W13:0 W14:0 W15:0 W16:0 W17:0 W18:0 W19:0 W20:0 W21:0 W22:0 W23:0 W24:0 W25:0 W26:0 W27:0 W28:0 W29:0 W30:0 W31:0 W32:0 +GPGPU-Sim PTX: pushing kernel '_Z16digit_serial_madPjS_S_S_' to stream 0, gridDim= (1,1,1) blockDim = (32,1,1) +maxmrqlatency = 0 +maxdqlatency = 0 +maxmflatency = 0 +max_icnt2mem_latency = 0 +max_icnt2sh_latency = 0 +mrq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dq_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2mem_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +icnt2sh_lat_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +mf_lat_pw_table:0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum concurrent accesses to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +maximum service time to same row: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +average row accesses per activate: +dram[0]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[1]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[2]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[3]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[4]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[5]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[6]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[7]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[8]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[9]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +dram[10]: -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan -nan +average row locality = 0/0 = -nan +number of total memory accesses made: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total accesses: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total read accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +number of total write accesses: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +total reads: 0 +min_bank_accesses = 0! +min_chip_accesses = 0! +average mf latency per bank: +dram[0]: none none none none none none none none none none none none none none none none +dram[1]: none none none none none none none none none none none none none none none none +dram[2]: none none none none none none none none none none none none none none none none +dram[3]: none none none none none none none none none none none none none none none none +dram[4]: none none none none none none none none none none none none none none none none +dram[5]: none none none none none none none none none none none none none none none none +dram[6]: none none none none none none none none none none none none none none none none +dram[7]: none none none none none none none none none none none none none none none none +dram[8]: none none none none none none none none none none none none none none none none +dram[9]: none none none none none none none none none none none none none none none none +dram[10]: none none none none none none none none none none none none none none none none +maximum mf latency per bank: +dram[0]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[1]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[2]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[3]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[4]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[5]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[6]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[7]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[8]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[9]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +dram[10]: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +Memory Partition 0: +Cache L2_bank_000: +MSHR contents + +Cache L2_bank_001: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[0]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 1: +Cache L2_bank_002: +MSHR contents + +Cache L2_bank_003: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[1]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 2: +Cache L2_bank_004: +MSHR contents + +Cache L2_bank_005: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[2]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 3: +Cache L2_bank_006: +MSHR contents + +Cache L2_bank_007: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[3]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 4: +Cache L2_bank_008: +MSHR contents + +Cache L2_bank_009: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[4]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 5: +Cache L2_bank_010: +MSHR contents + +Cache L2_bank_011: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[5]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 6: +Cache L2_bank_012: +MSHR contents + +Cache L2_bank_013: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[6]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 7: +Cache L2_bank_014: +MSHR contents + +Cache L2_bank_015: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[7]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 8: +Cache L2_bank_016: +MSHR contents + +Cache L2_bank_017: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[8]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 9: +Cache L2_bank_018: +MSHR contents + +Cache L2_bank_019: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[9]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan +Memory Partition 10: +Cache L2_bank_020: +MSHR contents + +Cache L2_bank_021: +MSHR contents + +In Dram Latency Queue (total = 0): +DRAM[10]: 16 bks, busW=4 BL=8 CL=12, tRRD=2 tCCD=6, tRCD=12 tRAS=28 tRP=12 tRC=40 +n_cmd=0 n_nop=0 n_act=0 n_pre=0 n_req=0 n_rd=0 n_write=0 bw_util=-nan +n_activity=0 dram_eff=-nan +bk0: 0a 0i bk1: 0a 0i bk2: 0a 0i bk3: 0a 0i bk4: 0a 0i bk5: 0a 0i bk6: 0a 0i bk7: 0a 0i bk8: 0a 0i bk9: 0a 0i bk10: 0a 0i bk11: 0a 0i bk12: 0a 0i bk13: 0a 0i bk14: 0a 0i bk15: 0a 0i +dram_util_bins: 0 0 0 0 0 0 0 0 0 0 +dram_eff_bins: 0 0 0 0 0 0 0 0 0 0 +mrqq: max=0 avg=-nan + +========= L2 cache stats ========= +L2_cache_bank[0]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[1]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[2]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[3]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[4]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[5]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[6]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[7]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[8]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[9]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[10]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[11]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[12]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[13]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[14]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[15]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[16]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[17]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[18]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[19]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[20]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_cache_bank[21]: Access = 0, Miss = 0, Miss_rate = -nan, Pending_hits = 0, Reservation_fails = 0 +L2_total_cache_accesses = 0 +L2_total_cache_misses = 0 +L2_total_cache_pending_hits = 0 +L2_total_cache_reservation_fails = 0 +L2_total_cache_breakdown: +L2_cache_data_port_util = 0.000 +L2_cache_fill_port_util = 0.000 + +icnt_total_pkts_mem_to_simt=0 +icnt_total_pkts_simt_to_mem=0 +LD_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +ST_mem_lat_dist 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +----------------------------Interconnect-DETAILS-------------------------------- +Class 0: +Packet latency average = -nan + minimum = nan + maximum = -nan +Network latency average = -nan + minimum = nan + maximum = -nan +Slowest packet = -1 +Flit latency average = -nan + minimum = nan + maximum = -nan +Slowest flit = -1 +Fragmentation average = -nan + minimum = nan + maximum = -nan +Injected packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted packet rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected flit rate average = -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Accepted flit rate average= -nan + minimum = -nan (at node 0) + maximum = -nan (at node 0) +Injected packet length average = -nan +Accepted packet length average = -nan +Total in-flight flits = 0 (0 measured) +====== Overall Traffic Statistics ====== +====== Traffic class 0 ====== +Packet latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Network latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Flit latency average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Fragmentation average = -nan (4 samples) + minimum = nan (4 samples) + maximum = -nan (4 samples) +Injected packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted packet rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Accepted flit rate average = -nan (4 samples) + minimum = -nan (4 samples) + maximum = -nan (4 samples) +Injected packet size average = -nan (4 samples) +Accepted packet size average = -nan (4 samples) +Hops average = -nan (4 samples) +----------------------------END-of-Interconnect-DETAILS------------------------- +GPGPU-Sim uArch: Shader 1 bind to kernel 1 '_Z16digit_serial_madPjS_S_S_' +GPGPU-Sim uArch: CTA/core = 32, limited by: cta_limit +GPGPU-Sim uArch: core: 1, cta: 0, start_tid: 0, end_tid: 32, initialized @(1,0) +GPGPU-Sim uArch: cycles simulated: 500 inst.: 191 (ipc= 0.4) sim_rate=191 (inst/sec) elapsed = 0:0:00:01 / Sun Nov 12 16:27:07 2017 +GPGPU-Sim PTX: WARNING (_1.ptx:90) ** reading undefined register '%r19' (cuid:0). Setting to 0X00000000. This is okay if you are simulating the native ISA diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index b5b79e7..54d8796 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -69,9 +69,9 @@ unsigned cdp_latency[5]; void ptx_opcocde_latency_options (option_parser_t opp) { option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, - "Opcode latencies for integers " - "Default 1,1,19,25,145,1", - "1,1,19,25,145,1"); + "Opcode latencies for integers " + "Default 1,1,19,25,145,1,4", + "1,1,19,25,145,1,4"); option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp, "Opcode latencies for single precision floating points " "Default 1,1,1,1,30", @@ -81,8 +81,8 @@ void ptx_opcocde_latency_options (option_parser_t opp) { "Default 8,8,8,8,335", "8,8,8,8,335"); option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, - "Opcode initiation intervals for integers " - "Default 1,1,4,4,32,1", + "Opcode initiation intervals for integers " + "Default 1,1,4,4,32,1,1", "1,1,4,4,32,1"); option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp, "Opcode initiation intervals for single precision floating points " @@ -589,10 +589,14 @@ void ptx_instruction::set_bar_type() void ptx_instruction::set_opcode_and_latency() { - unsigned int_latency[6]; + unsigned int_latency[5]; + unsigned int_precision; + unsigned int_lane_width; unsigned fp_latency[5]; unsigned dp_latency[5]; - unsigned int_init[6]; + unsigned int_init[5]; + unsigned int_init_precision; + unsigned int_init_lane_width; unsigned fp_init[5]; unsigned dp_init[5]; /* @@ -603,18 +607,18 @@ void ptx_instruction::set_opcode_and_latency() * [4] DIV * [5] BSMAD */ - sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u", + sscanf(opcode_latency_int, "%u,%u,%u,%u,%u,%u,%u", &int_latency[0],&int_latency[1],&int_latency[2], - &int_latency[3],&int_latency[4],&int_latency[5]); + &int_latency[3],&int_latency[4],&int_precision,&int_lane_width); sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u", &fp_latency[0],&fp_latency[1],&fp_latency[2], &fp_latency[3],&fp_latency[4]); sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u", &dp_latency[0],&dp_latency[1],&dp_latency[2], &dp_latency[3],&dp_latency[4]); - sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u", + sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u,%u, %u", &int_init[0],&int_init[1],&int_init[2], - &int_init[3],&int_init[4],&int_init[5]); + &int_init[3],&int_init[4],&int_init_precision,&int_init_lane_width); sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u", &fp_init[0],&fp_init[1],&fp_init[2], &fp_init[3],&fp_init[4]); @@ -789,8 +793,8 @@ void ptx_instruction::set_opcode_and_latency() op = SFU_OP; break; case BSMAD_OP: - latency = int_latency[5]; - initiation_interval = int_init[5]; + latency = int_precision/int_lane_width; + initiation_interval = int_init_precision/int_init_lane_width; break; case SHFL_OP: latency = 32; -- cgit v1.3 From dccac457bb2263602a6a244297168cae8fda8e47 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Wed, 15 Nov 2017 20:58:22 -0500 Subject: Update gpgpusim.config --- configs/Pascal-P102-GDDR5X/gpgpusim.config | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index e830023..257560e 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -22,7 +22,7 @@ #-gpgpu_clock_domains ::: # Pascal NVIDIA TITAN X clock domains are adopted from # https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1417.0:2834.0:1417.0:2500.0 +-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 # shader core pipeline config -gpgpu_shader_registers 32768 @@ -113,7 +113,7 @@ -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 120 +-rop_latency 0 -dram_latency 100 # dram model config @@ -123,8 +123,8 @@ # To allow 100% DRAM utility, there should at least be enough buffer to sustain # the minimum DRAM latency (100 core cycles). I.e. # Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 192 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 240 # for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) # 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition -- cgit v1.3 From 9233f6f9eeea537187deb64add77a320442aa621 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 18 Nov 2017 15:48:26 -0500 Subject: vectoradd is successfully filling the l2 --- src/cuda-sim/cuda-sim.cc | 4 ++++ src/gpgpu-sim/gpu-cache.cc | 23 +++++++++++++++++------ src/gpgpu-sim/gpu-cache.h | 11 +++++++++++ src/gpgpu-sim/gpu-sim.cc | 17 +++++++++++++++++ src/gpgpu-sim/gpu-sim.h | 2 ++ src/gpgpu-sim/l2cache.cc | 9 +++++++++ src/gpgpu-sim/l2cache.h | 6 ++++++ 7 files changed, 66 insertions(+), 6 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index a668db1..685ae53 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -401,6 +401,10 @@ void gpgpu_t::memcpy_to_gpu( size_t dst_start_addr, const void *src, size_t coun char *src_data = (char*)src; for (unsigned n=0; n < count; n ++ ) m_global_mem->write(dst_start_addr+n,1, src_data+n,NULL,NULL); + + // Copy into the performance model. + extern gpgpu_sim* g_the_gpu; + g_the_gpu->memcpy_to_gpu(dst_start_addr, src, count); if(g_debug_execution >= 3) { printf( " done.\n"); fflush(stdout); diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 32c2bb1..37fc5ea 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -190,11 +190,17 @@ void tag_array::init( int core_id, int type_id ) m_type_id = type_id; } + enum cache_request_status tag_array::probe( new_addr_type addr, unsigned &idx, mem_fetch* mf) const { + mem_access_sector_mask_t mask = mf->get_access_sector_mask(); + return probe(addr, idx, mask); +} + + +enum cache_request_status tag_array::probe( new_addr_type addr, unsigned &idx, mem_access_sector_mask_t mask) const { //assert( m_config.m_write_policy == READ_ONLY ); unsigned set_index = m_config.set_index(addr); new_addr_type tag = m_config.tag(addr); - mem_access_sector_mask_t mask = mf->get_access_sector_mask(); unsigned invalid_line = (unsigned)-1; unsigned valid_line = (unsigned)-1; @@ -310,18 +316,23 @@ enum cache_request_status tag_array::access( new_addr_type addr, unsigned time, void tag_array::fill( new_addr_type addr, unsigned time, mem_fetch* mf) { - assert( m_config.m_alloc_policy == ON_FILL ); + fill(addr, time, mf->get_access_sector_mask()); +} + +void tag_array::fill( new_addr_type addr, unsigned time, mem_access_sector_mask_t mask ) +{ + //assert( m_config.m_alloc_policy == ON_FILL ); unsigned idx; - enum cache_request_status status = probe(addr,idx,mf); + enum cache_request_status status = probe(addr,idx,mask); assert(status==MISS||status==SECTOR_MISS); // MSHR should have prevented redundant memory request if(status==MISS) - m_lines[idx]->allocate( m_config.tag(addr), m_config.block_addr(addr), time, mf->get_access_sector_mask() ); + m_lines[idx]->allocate( m_config.tag(addr), m_config.block_addr(addr), time, mask ); else if (status==SECTOR_MISS) { assert(m_config.m_cache_type == SECTOR); - ((sector_cache_block*)m_lines[idx])->allocate_sector( time, mf->get_access_sector_mask() ); + ((sector_cache_block*)m_lines[idx])->allocate_sector( time, mask ); } - m_lines[idx]->fill(time, mf->get_access_sector_mask()); + m_lines[idx]->fill(time, mask); } void tag_array::fill( unsigned index, unsigned time, mem_fetch* mf) diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 3e1691a..3713126 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -690,11 +690,13 @@ public: ~tag_array(); enum cache_request_status probe( new_addr_type addr, unsigned &idx, mem_fetch* mf ) const; + enum cache_request_status probe( new_addr_type addr, unsigned &idx, mem_access_sector_mask_t mask ) const; enum cache_request_status access( new_addr_type addr, unsigned time, unsigned &idx, mem_fetch* mf ); enum cache_request_status access( new_addr_type addr, unsigned time, unsigned &idx, bool &wb, evicted_block_info &evicted, mem_fetch* mf ); void fill( new_addr_type addr, unsigned time, mem_fetch* mf ); void fill( unsigned idx, unsigned time, mem_fetch* mf ); + void fill( new_addr_type addr, unsigned time, mem_access_sector_mask_t mask ); unsigned size() const { return m_config.get_num_lines();} cache_block_t* get_block(unsigned idx) { return m_lines[idx];} @@ -969,6 +971,15 @@ public: bool data_port_free() const { return m_bandwidth_management.data_port_free(); } bool fill_port_free() const { return m_bandwidth_management.fill_port_free(); } + // This is a gapping hole we are poking in the system to quickly handle + // filling the cache on cudamemcopies. We don't care about anything other than + // L2 state after the memcopy - so just force the tag array to act as though + // something is read or written without doing anything else. + void force_tag_access( new_addr_type addr, unsigned time, mem_access_sector_mask_t mask ) + { + m_tag_array->fill( addr, time, mask ); + } + protected: // Constructor that can be used by derived classes with custom tag arrays baseline_cache( const char *name, diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 11ac5df..263cbad 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1595,6 +1595,23 @@ void shader_core_ctx::dump_warp_state( FILE *fout ) const m_warp[w].print(fout); } + +void gpgpu_sim::memcpy_to_gpu( size_t dst_start_addr, const void *src, size_t count ) +{ + assert (dst_start_addr % 32 == 0); + // Right now - I am just going to assume you write the whole last cache line... +// assert (count % 128 == 0); + for ( unsigned counter = 0; counter < count; counter += 32 ) { + const size_t wr_addr = dst_start_addr + counter; + addrdec_t raw_addr; + mem_access_sector_mask_t mask; + mask.set(wr_addr % 128 / 32); + m_memory_config->m_address_mapping.addrdec_tlx( wr_addr, &raw_addr ); + const unsigned partition_id = raw_addr.sub_partition / m_memory_config->m_n_sub_partition_per_memory_channel; + m_memory_partition_unit[ partition_id ]->handle_memcpy_to_gpu( wr_addr, raw_addr.sub_partition, mask ); + } +} + void gpgpu_sim::dump_pipeline( int mask, int s, int m ) const { /* diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index c04648c..6382adf 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -425,6 +425,8 @@ public: void gpu_print_stat(); void dump_pipeline( int mask, int s, int m ) const; + void memcpy_to_gpu( size_t dst_start_addr, const void *src, size_t count ); + //The next three functions added to be used by the functional simulation function //! Get shader core configuration diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index 8fbf448..1df7858 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -74,6 +74,15 @@ memory_partition_unit::memory_partition_unit( unsigned partition_id, } } +void memory_partition_unit::handle_memcpy_to_gpu( size_t addr, unsigned global_subpart_id, mem_access_sector_mask_t mask ) +{ + unsigned p = global_sub_partition_id_to_local_id(global_subpart_id); + std::string mystring = + mask.to_string(); + MEMPART_DPRINTF("Copy Engine Request Received For Address=%zu, local_subpart=%u, sector_mask=%s \n", addr, p, mystring.c_str()); + m_sub_partition[p]->force_l2_tag_update(addr,gpu_sim_cycle+gpu_tot_sim_cycle, mask); +} + memory_partition_unit::~memory_partition_unit() { delete m_dram; diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index 2cc0e76..b613a94 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -72,6 +72,7 @@ public: void print_stat( FILE *fp ) { m_dram->print_stat(fp); } void visualize() const { m_dram->visualize(); } void print( FILE *fp ) const; + void handle_memcpy_to_gpu( size_t dst_start_addr, unsigned subpart_id, mem_access_sector_mask_t mask ); class memory_sub_partition * get_sub_partition(int sub_partition_id) { @@ -178,6 +179,11 @@ public: void accumulate_L2cache_stats(class cache_stats &l2_stats) const; void get_L2cache_sub_stats(struct cache_sub_stats &css) const; + void force_l2_tag_update(new_addr_type addr, unsigned time, mem_access_sector_mask_t mask) + { + m_L2cache->force_tag_access( addr, time, mask ); + } + private: // data unsigned m_id; //< the global sub partition ID -- cgit v1.3 From d8766e4eb7551afcc8c9ca168449bcd20974af60 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 18 Nov 2017 16:24:58 -0500 Subject: Making the perf sim copy optional, getting rid of an assert that will happen with the new hack and incrementing the cycle so that cudamemcopies take some time (if we don't do this the LRU in the cache does not work) --- src/gpgpu-sim/gpu-cache.cc | 2 +- src/gpgpu-sim/gpu-sim.cc | 27 ++++++++++++++++----------- src/gpgpu-sim/gpu-sim.h | 1 + 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 37fc5ea..e1e41a5 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -324,7 +324,7 @@ void tag_array::fill( new_addr_type addr, unsigned time, mem_access_sector_mask_ //assert( m_config.m_alloc_policy == ON_FILL ); unsigned idx; enum cache_request_status status = probe(addr,idx,mask); - assert(status==MISS||status==SECTOR_MISS); // MSHR should have prevented redundant memory request + //assert(status==MISS||status==SECTOR_MISS); // MSHR should have prevented redundant memory request if(status==MISS) m_lines[idx]->allocate( m_config.tag(addr), m_config.block_addr(addr), time, mask ); else if (status==SECTOR_MISS) { diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 263cbad..438769f 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -140,6 +140,8 @@ void power_config::reg_options(class OptionParser * opp) void memory_config::reg_options(class OptionParser * opp) { + option_parser_register(opp, "-perf_sim_memcpy", OPT_BOOL, &m_perf_sim_memcpy, + "Fill the L2 cache on memcpy", "0"); option_parser_register(opp, "-gpgpu_dram_scheduler", OPT_INT32, &scheduler_type, "0 = fifo, 1 = FR-FCFS (defaul)", "1"); option_parser_register(opp, "-gpgpu_dram_partition_queues", OPT_CSTR, &gpgpu_L2_queue_config, @@ -1598,17 +1600,20 @@ void shader_core_ctx::dump_warp_state( FILE *fout ) const void gpgpu_sim::memcpy_to_gpu( size_t dst_start_addr, const void *src, size_t count ) { - assert (dst_start_addr % 32 == 0); - // Right now - I am just going to assume you write the whole last cache line... -// assert (count % 128 == 0); - for ( unsigned counter = 0; counter < count; counter += 32 ) { - const size_t wr_addr = dst_start_addr + counter; - addrdec_t raw_addr; - mem_access_sector_mask_t mask; - mask.set(wr_addr % 128 / 32); - m_memory_config->m_address_mapping.addrdec_tlx( wr_addr, &raw_addr ); - const unsigned partition_id = raw_addr.sub_partition / m_memory_config->m_n_sub_partition_per_memory_channel; - m_memory_partition_unit[ partition_id ]->handle_memcpy_to_gpu( wr_addr, raw_addr.sub_partition, mask ); + if (m_memory_config->m_perf_sim_memcpy) { + assert (dst_start_addr % 32 == 0); + // Right now - I am just going to assume you write the whole last cache line... + // assert (count % 128 == 0); + for ( unsigned counter = 0; counter < count; counter += 32 ) { + const size_t wr_addr = dst_start_addr + counter; + addrdec_t raw_addr; + mem_access_sector_mask_t mask; + mask.set(wr_addr % 128 / 32); + m_memory_config->m_address_mapping.addrdec_tlx( wr_addr, &raw_addr ); + const unsigned partition_id = raw_addr.sub_partition / m_memory_config->m_n_sub_partition_per_memory_channel; + m_memory_partition_unit[ partition_id ]->handle_memcpy_to_gpu( wr_addr, raw_addr.sub_partition, mask ); + gpu_sim_cycle += 1; + } } } diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 6382adf..81f13cb 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -290,6 +290,7 @@ struct memory_config { unsigned gpgpu_frfcfs_dram_write_queue_size; unsigned write_high_watermark; unsigned write_low_watermark; + bool m_perf_sim_memcpy; }; // global counters and flags (please try not to add to this list!!!) -- cgit v1.3 From b9420953855042566ea3371882aef89f66a3f055 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 18 Nov 2017 17:38:24 -0500 Subject: fixing a stupid inheritance bug --- src/cuda-sim/cuda-sim.cc | 2 +- src/gpgpu-sim/gpu-sim.cc | 2 +- src/gpgpu-sim/gpu-sim.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 685ae53..5516b1e 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -404,7 +404,7 @@ void gpgpu_t::memcpy_to_gpu( size_t dst_start_addr, const void *src, size_t coun // Copy into the performance model. extern gpgpu_sim* g_the_gpu; - g_the_gpu->memcpy_to_gpu(dst_start_addr, src, count); + g_the_gpu->perf_memcpy_to_gpu(dst_start_addr, count); if(g_debug_execution >= 3) { printf( " done.\n"); fflush(stdout); diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 438769f..0c2ea1c 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1598,7 +1598,7 @@ void shader_core_ctx::dump_warp_state( FILE *fout ) const } -void gpgpu_sim::memcpy_to_gpu( size_t dst_start_addr, const void *src, size_t count ) +void gpgpu_sim::perf_memcpy_to_gpu( size_t dst_start_addr, size_t count ) { if (m_memory_config->m_perf_sim_memcpy) { assert (dst_start_addr % 32 == 0); diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 81f13cb..1778008 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -426,7 +426,7 @@ public: void gpu_print_stat(); void dump_pipeline( int mask, int s, int m ) const; - void memcpy_to_gpu( size_t dst_start_addr, const void *src, size_t count ); + void perf_memcpy_to_gpu( size_t dst_start_addr, size_t count ); //The next three functions added to be used by the functional simulation function -- cgit v1.3 From 05182e14ea348b9d57fc14aeae1ff3f684512262 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 18 Nov 2017 19:30:53 -0500 Subject: 64-address used on the CPU side, but GPGPU-Sim Truncates it to 32-bit.... truncating the address here fixes the issue and we start propoerly hitting in the L2 --- src/gpgpu-sim/gpu-sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 0c2ea1c..0267c31 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1605,7 +1605,7 @@ void gpgpu_sim::perf_memcpy_to_gpu( size_t dst_start_addr, size_t count ) // Right now - I am just going to assume you write the whole last cache line... // assert (count % 128 == 0); for ( unsigned counter = 0; counter < count; counter += 32 ) { - const size_t wr_addr = dst_start_addr + counter; + const unsigned wr_addr = dst_start_addr + counter; addrdec_t raw_addr; mem_access_sector_mask_t mask; mask.set(wr_addr % 128 / 32); -- cgit v1.3 From 14fdd4d3d250a33760b4cb04b8b5858531781d08 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 18 Nov 2017 19:31:28 -0500 Subject: Adding a subpartion trace to help in figuring out what the hell is going on --- src/gpgpu-sim/l2cache.cc | 3 ++- src/gpgpu-sim/l2cache_trace.h | 16 ++++++++++++++++ src/trace_streams.tup | 1 + 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index 1df7858..fb0d588 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -79,7 +79,7 @@ void memory_partition_unit::handle_memcpy_to_gpu( size_t addr, unsigned global_s unsigned p = global_sub_partition_id_to_local_id(global_subpart_id); std::string mystring = mask.to_string(); - MEMPART_DPRINTF("Copy Engine Request Received For Address=%zu, local_subpart=%u, sector_mask=%s \n", addr, p, mystring.c_str()); + MEMPART_DPRINTF("Copy Engine Request Received For Address=%llx, local_subpart=%u, global_subpart=%u, sector_mask=%s \n", addr, p, global_subpart_id, mystring.c_str()); m_sub_partition[p]->force_l2_tag_update(addr,gpu_sim_cycle+gpu_tot_sim_cycle, mask); } @@ -407,6 +407,7 @@ void memory_sub_partition::cache_cycle( unsigned cycle ) enum cache_request_status status = m_L2cache->access(mf->get_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle,events); bool write_sent = was_write_sent(events); bool read_sent = was_read_sent(events); + MEM_SUBPART_DPRINTF("Probing L2 cache Address=%llx, status=%u\n", mf->get_addr(), status); if ( status == HIT ) { if( !write_sent ) { diff --git a/src/gpgpu-sim/l2cache_trace.h b/src/gpgpu-sim/l2cache_trace.h index 3dac87d..2235cdc 100644 --- a/src/gpgpu-sim/l2cache_trace.h +++ b/src/gpgpu-sim/l2cache_trace.h @@ -34,6 +34,9 @@ #define MEMPART_PRINT_STR SIM_PRINT_STR " %d - " #define MEMPART_DTRACE(x) ( DTRACE(x) && (Trace::sampling_memory_partition == -1 || Trace::sampling_memory_partition == (int)get_mpid()) ) +#define MEM_SUBPART_PRINT_STR SIM_PRINT_STR " %d - " +#define MEM_SUBPART_DTRACE(x) ( DTRACE(x) && (Trace::sampling_memory_partition == -1 || Trace::sampling_memory_partition == (int)m_id) ) + // Intended to be called from inside components of a memory partition // Depends on a get_mpid() function #define MEMPART_DPRINTF(...) do {\ @@ -46,10 +49,23 @@ }\ } while (0) +#define MEM_SUBPART_DPRINTF(...) do {\ + if (MEM_SUBPART_DTRACE(MEMORY_PARTITION_UNIT)) {\ + printf( MEM_SUBPART_PRINT_STR,\ + gpu_sim_cycle + gpu_tot_sim_cycle,\ + Trace::trace_streams_str[Trace::MEMORY_SUBPARTITION_UNIT],\ + m_id );\ + printf(__VA_ARGS__);\ + }\ +} while (0) + #else #define MEMPART_DTRACE(x) (false) #define MEMPART_DPRINTF(x, ...) do {} while (0) +#define MEM_SUBPART_DTRACE(x) (false) +#define MEM_SUBPART_DPRINTF(x, ...) do {} while (0) + #endif diff --git a/src/trace_streams.tup b/src/trace_streams.tup index bbc9bb3..3455a00 100644 --- a/src/trace_streams.tup +++ b/src/trace_streams.tup @@ -29,6 +29,7 @@ TS_TUP_BEGIN( trace_streams_type ) TS_TUP( WARP_SCHEDULER ), TS_TUP( SCOREBOARD ), TS_TUP( MEMORY_PARTITION_UNIT ), + TS_TUP( MEMORY_SUBPARTITION_UNIT ), TS_TUP( INTERCONNECT ), TS_TUP( NUM_TRACE_STREAMS ) TS_TUP_END( trace_streams_type ) -- cgit v1.3 From 21528f301886ffdba5e921091658446d23c9c377 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 18 Nov 2017 21:00:17 -0500 Subject: fixing the cycle issues with using the cudamemcpies --- src/gpgpu-sim/gpu-sim.cc | 4 +--- src/gpgpu-sim/l2cache.cc | 5 +++-- src/gpgpu-sim/l2cache.h | 10 +++++++++- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 0267c31..8dc80d2 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1602,8 +1602,7 @@ void gpgpu_sim::perf_memcpy_to_gpu( size_t dst_start_addr, size_t count ) { if (m_memory_config->m_perf_sim_memcpy) { assert (dst_start_addr % 32 == 0); - // Right now - I am just going to assume you write the whole last cache line... - // assert (count % 128 == 0); + for ( unsigned counter = 0; counter < count; counter += 32 ) { const unsigned wr_addr = dst_start_addr + counter; addrdec_t raw_addr; @@ -1612,7 +1611,6 @@ void gpgpu_sim::perf_memcpy_to_gpu( size_t dst_start_addr, size_t count ) m_memory_config->m_address_mapping.addrdec_tlx( wr_addr, &raw_addr ); const unsigned partition_id = raw_addr.sub_partition / m_memory_config->m_n_sub_partition_per_memory_channel; m_memory_partition_unit[ partition_id ]->handle_memcpy_to_gpu( wr_addr, raw_addr.sub_partition, mask ); - gpu_sim_cycle += 1; } } } diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index fb0d588..b1465a8 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -315,6 +315,7 @@ memory_sub_partition::memory_sub_partition( unsigned sub_partition_id, m_id = sub_partition_id; m_config=config; m_stats=stats; + m_memcpy_cycle_offset = 0; assert(m_id < m_config->m_n_mem_sub_partition); @@ -378,7 +379,7 @@ void memory_sub_partition::cache_cycle( unsigned cycle ) if ( !m_config->m_L2_config.disabled() && m_L2cache->waiting_for_fill(mf) ) { if (m_L2cache->fill_port_free()) { mf->set_status(IN_PARTITION_L2_FILL_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); - m_L2cache->fill(mf,gpu_sim_cycle+gpu_tot_sim_cycle); + m_L2cache->fill(mf,gpu_sim_cycle+gpu_tot_sim_cycle+m_memcpy_cycle_offset); m_dram_L2_queue->pop(); } } else if ( !m_L2_icnt_queue->full() ) { @@ -404,7 +405,7 @@ void memory_sub_partition::cache_cycle( unsigned cycle ) bool port_free = m_L2cache->data_port_free(); if ( !output_full && port_free ) { std::list events; - enum cache_request_status status = m_L2cache->access(mf->get_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle,events); + enum cache_request_status status = m_L2cache->access(mf->get_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle+m_memcpy_cycle_offset,events); bool write_sent = was_write_sent(events); bool read_sent = was_read_sent(events); MEM_SUBPART_DPRINTF("Probing L2 cache Address=%llx, status=%u\n", mf->get_addr(), status); diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index b613a94..2d13918 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -181,7 +181,8 @@ public: void force_l2_tag_update(new_addr_type addr, unsigned time, mem_access_sector_mask_t mask) { - m_L2cache->force_tag_access( addr, time, mask ); + m_L2cache->force_tag_access( addr, m_memcpy_cycle_offset + time, mask ); + m_memcpy_cycle_offset += 1; } private: @@ -216,6 +217,13 @@ private: friend class L2interface; std::vector breakdown_request_to_sector_requests(mem_fetch* mf); + + // This is a cycle offset that has to be applied to the l2 accesses to account for + // the cudamemcpy read/writes. We want GPGPU-Sim to only count cycles for kernel execution + // but we want cudamemcpy to go through the L2. Everytime an access is made from cudamemcpy + // this counter is incremented, and when the l2 is accessed (in both cudamemcpyies and otherwise) + // this value is added to the gpgpu-sim cycle counters. + unsigned m_memcpy_cycle_offset; }; class L2interface : public mem_fetch_interface { -- cgit v1.3 From db4011bce0d88b44584eccf3854f3d82876cdc77 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 18 Nov 2017 21:03:48 -0500 Subject: copy to the L2 by default --- src/gpgpu-sim/gpu-sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 8dc80d2..17f1714 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -141,7 +141,7 @@ void power_config::reg_options(class OptionParser * opp) void memory_config::reg_options(class OptionParser * opp) { option_parser_register(opp, "-perf_sim_memcpy", OPT_BOOL, &m_perf_sim_memcpy, - "Fill the L2 cache on memcpy", "0"); + "Fill the L2 cache on memcpy", "1"); option_parser_register(opp, "-gpgpu_dram_scheduler", OPT_INT32, &scheduler_type, "0 = fifo, 1 = FR-FCFS (defaul)", "1"); option_parser_register(opp, "-gpgpu_dram_partition_queues", OPT_CSTR, &gpgpu_L2_queue_config, -- cgit v1.3 From b2c4c3e23530799e6e24eb83b2a6b82cf7891cf4 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 18 Nov 2017 21:50:10 -0500 Subject: Getting rid of another assert that crops up cause of our memcpy and L2 interaction --- src/gpgpu-sim/gpu-cache.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 3713126..b649135 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -292,8 +292,8 @@ struct sector_cache_block : public cache_block_t { { unsigned sidx = get_sector_index(sector_mask); - if(!m_ignore_on_fill_status[sidx]) - assert( m_status[sidx] == RESERVED ); + // if(!m_ignore_on_fill_status[sidx]) + // assert( m_status[sidx] == RESERVED ); m_status[sidx] = m_set_modified_on_fill[sidx]? MODIFIED : VALID; -- cgit v1.3 From 8386d194b8a239ed0c36852c8a6efff142712801 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 18 Nov 2017 22:25:13 -0500 Subject: removing another assert --- src/gpgpu-sim/gpu-cache.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index b649135..6a84a3a 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -153,8 +153,8 @@ struct line_cache_block: public cache_block_t { } void fill( unsigned time, mem_access_sector_mask_t sector_mask ) { - if(!m_ignore_on_fill_status) - assert( m_status == RESERVED ); + //if(!m_ignore_on_fill_status) + // assert( m_status == RESERVED ); m_status = m_set_modified_on_fill? MODIFIED : VALID; -- cgit v1.3 From f125fecc85fdbb29ed846a2acfdb5e8c6cf20e41 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 18 Nov 2017 22:40:27 -0500 Subject: Also initiate our L2 accesses on copies back to the CPU --- src/cuda-sim/cuda-sim.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 5516b1e..2f166aa 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -420,6 +420,10 @@ void gpgpu_t::memcpy_from_gpu( void *dst, size_t src_start_addr, size_t count ) unsigned char *dst_data = (unsigned char*)dst; for (unsigned n=0; n < count; n ++ ) m_global_mem->read(src_start_addr+n,1,dst_data+n); + + // Copy into the performance model. + extern gpgpu_sim* g_the_gpu; + g_the_gpu->perf_memcpy_to_gpu(src_start_addr, count); if(g_debug_execution >= 3) { printf( " done.\n"); fflush(stdout); -- cgit v1.3 From 3fe52ab24a75493ad201ef82837dced36272b8f5 Mon Sep 17 00:00:00 2001 From: Mahmoud Abdallah Date: Sat, 18 Nov 2017 23:56:06 -0500 Subject: improving P102 accuracy --- configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt | 8 ++++---- configs/Pascal-P102-GDDR5X/gpgpusim.config | 10 +++++----- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt index 94b2378..714d933 100644 --- a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt +++ b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt @@ -17,10 +17,10 @@ routing_function = dest_tag; // Flow control num_vcs = 1; -vc_buf_size = 32; -input_buffer_size = 32; -ejection_buffer_size = 32; -boundary_buffer_size = 32; +vc_buf_size = 64; +input_buffer_size = 256; +ejection_buffer_size = 64; +boundary_buffer_size = 64; wait_for_tail_credit = 0; diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index 257560e..cb69767 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -61,7 +61,7 @@ # Pascal GP102 has 96KB Shared memory # Pascal GP102 has 24KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 N:32:128:6,L:L:m:N:H,S:128:8,16 +-gpgpu_cache:dl1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 -gpgpu_shmem_size 49152 -gmem_skip_L1D 1 -icnt_flit_size 40 @@ -71,7 +71,7 @@ -gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:128:4,16:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 -#-gpgpu_flush_l2_cache 1 +-perf_sim_memcpy 1 # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 @@ -113,7 +113,7 @@ -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 0 +-rop_latency 100 -dram_latency 100 # dram model config @@ -138,8 +138,8 @@ # Use the same GDDR5 timing from hynix H5GQ1H24AFR # disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: + CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" -dram_bnk_indexing_policy 0 -dram_bnkgrp_indexing_policy 1 -- cgit v1.3 From 68cc9491f40e41d6421a2e6b068b4302cedf80ec Mon Sep 17 00:00:00 2001 From: Mahmoud Abdallah Date: Sun, 19 Nov 2017 00:01:30 -0500 Subject: improving P100 accuracy --- configs/Pascal-P100-HBM/config_fermi_islip.icnt | 8 ++++---- configs/Pascal-P100-HBM/gpgpusim.config | 8 ++++---- configs/Pascal-P102-GDDR5X/gpgpusim.config | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/configs/Pascal-P100-HBM/config_fermi_islip.icnt b/configs/Pascal-P100-HBM/config_fermi_islip.icnt index 0a73c81..e7c2c3b 100644 --- a/configs/Pascal-P100-HBM/config_fermi_islip.icnt +++ b/configs/Pascal-P100-HBM/config_fermi_islip.icnt @@ -17,10 +17,10 @@ routing_function = dest_tag; // Flow control num_vcs = 1; -vc_buf_size = 64; -input_buffer_size = 64; -ejection_buffer_size = 64; -boundary_buffer_size = 64; +vc_buf_size = 128; +input_buffer_size = 256; +ejection_buffer_size = 128; +boundary_buffer_size = 128; wait_for_tail_credit = 0; diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config index 1029194..533a865 100644 --- a/configs/Pascal-P100-HBM/gpgpusim.config +++ b/configs/Pascal-P100-HBM/gpgpusim.config @@ -17,7 +17,7 @@ #-gpgpu_clock_domains ::: # Pascal NVIDIA GP100 clock domains are adopted from # https://en.wikipedia.org/wiki/Nvidia_Tesla --gpgpu_clock_domains 1480.0:2960.0:1480.0:715.0 +-gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0 # shader core pipeline config -gpgpu_shader_registers 65536 @@ -54,7 +54,7 @@ # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. # Pascal GP100 has 64KB Shared memory --gpgpu_cache:dl1 S:64:128:6,L:L:m:N:H,A:128:8,32:0,32 +-gpgpu_cache:dl1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 -gpgpu_shmem_size 65536 -gmem_skip_L1D 1 -icnt_flit_size 40 @@ -64,7 +64,7 @@ -gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:256:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 -#-gpgpu_flush_l2_cache 1 +-perf_sim_memcpy 0 # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 @@ -116,7 +116,7 @@ # the minimum DRAM latency (100 core cycles). I.e. # Total buffer space required = 100 x 924MHz / 700MHz = 132 -gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 116 +-gpgpu_dram_return_queue_size 192 # for HBM, 32 channles, each (128 bits) 16 bytes width -gpgpu_n_mem_per_ctrlr 1 diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index cb69767..0c6c126 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -71,7 +71,7 @@ -gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:128:4,16:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 --perf_sim_memcpy 1 +-perf_sim_memcpy 0 # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 -- cgit v1.3 From 8719ea402730f6f429e32d63304f9af79bb83df0 Mon Sep 17 00:00:00 2001 From: Mahmoud Abdallah Date: Sun, 19 Nov 2017 00:29:29 -0500 Subject: improving the accuracy of titanX --- configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 4191eb0..4407870 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -21,7 +21,7 @@ #-gpgpu_clock_domains ::: # Pascal NVIDIA TITAN X clock domains are adopted from # https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1417.0:2834.0:1417.0:2500.0 +-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 # shader core pipeline config -gpgpu_shader_registers 65536 @@ -105,7 +105,7 @@ -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 120 +-rop_latency 100 -dram_latency 100 # dram model config @@ -130,8 +130,8 @@ # Use the same GDDR5 timing from hynix H5GQ1H24AFR # disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: + CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" # Pascal GP102 has four schedulers per core -gpgpu_num_sched_per_core 4 -- cgit v1.3 From 6a2f9978b9325fb78e8af1be5d5aaf90814e08d7 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Sun, 19 Nov 2017 20:05:53 -0500 Subject: Doing lazy fetch-on-read policy --- src/gpgpu-sim/gpu-cache.cc | 59 ++++++++++++++++++++++++++++++++++++++++++---- src/gpgpu-sim/gpu-cache.h | 31 +++++++++++++++++++++++- 2 files changed, 85 insertions(+), 5 deletions(-) diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index e1e41a5..0602e20 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -219,9 +219,16 @@ enum cache_request_status tag_array::probe( new_addr_type addr, unsigned &idx, m } else if ( line->get_status(mask) == VALID ) { idx = index; return HIT; - } else if ( line->get_status(mask) == MODIFIED ) { - idx = index; - return HIT; + } else if ( line->get_status(mask) == MODIFIED) { + if(line->is_readable(mask)) { + idx = index; + return HIT; + } + else { + idx = index; + return SECTOR_MISS; + } + } else if ( line->is_valid_line() && line->get_status(mask) == INVALID ) { idx = index; return SECTOR_MISS; @@ -1125,6 +1132,50 @@ data_cache::wr_miss_wa_fetch_on_write( new_addr_type addr, { new_addr_type block_addr = m_config.block_addr(addr); + new_addr_type mshr_addr = m_config.mshr_addr(mf->get_addr()); + + + //if the request writes to the whole cache line/sector, then, write and set cache line Modified. + //and no need to send read request to memory or reserve mshr + + if(miss_queue_full(0)) { + m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL); + return RESERVATION_FAIL; // cannot handle request this cycle + } + + bool wb = false; + evicted_block_info evicted; + + cache_request_status m_status = m_tag_array->access(block_addr,time,cache_index,wb,evicted,mf); + assert(m_status != HIT); + cache_block_t* block = m_tag_array->get_block(cache_index); + block->set_status(MODIFIED, mf->get_access_sector_mask()); + if(m_status == HIT_RESERVED) { + block->set_ignore_on_fill(true, mf->get_access_sector_mask()); + block->set_modified_on_fill(true, mf->get_access_sector_mask()); + } + + if(mf->get_access_byte_mask().count() == m_config.get_atom_sz()) + { + block->set_m_readable(true, mf->get_access_sector_mask()); + } else + { + block->set_m_readable(false, mf->get_access_sector_mask()); + } + + if( m_status != RESERVATION_FAIL ){ + // If evicted block is modified and not a write-through + // (already modified lower level) + if( wb && (m_config.m_write_policy != WRITE_THROUGH) ) { + mem_fetch *wb = m_memfetch_creator->alloc(evicted.m_block_addr, + m_wrbk_type,evicted.m_modified_size,true); + send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); + } + return MISS; + } + return RESERVATION_FAIL; + + /*new_addr_type block_addr = m_config.block_addr(addr); new_addr_type mshr_addr = m_config.mshr_addr(mf->get_addr()); if(mf->get_access_byte_mask().count() == m_config.get_atom_sz()) @@ -1233,7 +1284,7 @@ data_cache::wr_miss_wa_fetch_on_write( new_addr_type addr, return MISS; } return RESERVATION_FAIL; - } + }*/ } /// No write-allocate miss: Simply send write request to lower level memory diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 6a84a3a..0d07878 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -123,8 +123,11 @@ struct cache_block_t { virtual void set_ignore_on_fill(bool m_ignore, mem_access_sector_mask_t sector_mask) = 0; virtual void set_modified_on_fill(bool m_modified, mem_access_sector_mask_t sector_mask) = 0; virtual unsigned get_modified_size() = 0; + virtual void set_m_readable(bool readable, mem_access_sector_mask_t sector_mask)=0; + virtual bool is_readable(mem_access_sector_mask_t sector_mask)=0; virtual ~cache_block_t() {} + new_addr_type m_tag; new_addr_type m_block_addr; @@ -139,6 +142,7 @@ struct line_cache_block: public cache_block_t { m_status=INVALID; m_ignore_on_fill_status = false; m_set_modified_on_fill = false; + m_readable = true; } void allocate( new_addr_type tag, new_addr_type block_addr, unsigned time, mem_access_sector_mask_t sector_mask ) { @@ -209,6 +213,13 @@ struct line_cache_block: public cache_block_t { { return SECTOR_CHUNCK_SIZE * SECTOR_SIZE; //i.e. cache line size } + virtual void set_m_readable(bool readable, mem_access_sector_mask_t sector_mask) + { + m_readable = readable; + } + virtual bool is_readable(mem_access_sector_mask_t sector_mask) { + return m_readable; + } private: @@ -218,6 +229,7 @@ private: cache_block_state m_status; bool m_ignore_on_fill_status; bool m_set_modified_on_fill; + bool m_readable; }; struct sector_cache_block : public cache_block_t { @@ -234,6 +246,7 @@ struct sector_cache_block : public cache_block_t { m_status[i]= INVALID; m_ignore_on_fill_status[i] = false; m_set_modified_on_fill[i] = false; + m_readable[i] = true; } m_line_alloc_time=0; m_line_last_access_time=0; @@ -279,9 +292,15 @@ struct sector_cache_block : public cache_block_t { m_sector_alloc_time[sidx]=time; m_last_sector_access_time[sidx]=time; m_sector_fill_time[sidx]=0; + if(m_status[sidx]==MODIFIED) //this should be the case only for fetch-on-write policy //TO DO + m_set_modified_on_fill[sidx] = true; + else + m_set_modified_on_fill[sidx] = false; + m_status[sidx]=RESERVED; m_ignore_on_fill_status[sidx] = false; - m_set_modified_on_fill[sidx] = false; + //m_set_modified_on_fill[sidx] = false; + m_readable[sidx] = true; //set line stats m_line_last_access_time=time; @@ -362,6 +381,15 @@ struct sector_cache_block : public cache_block_t { unsigned sidx = get_sector_index(sector_mask); m_set_modified_on_fill[sidx] = m_modified; } + virtual void set_m_readable(bool readable, mem_access_sector_mask_t sector_mask) + { + unsigned sidx = get_sector_index(sector_mask); + m_readable[sidx] = readable; + } + virtual bool is_readable(mem_access_sector_mask_t sector_mask) { + unsigned sidx = get_sector_index(sector_mask); + return m_readable[sidx]; + } virtual unsigned get_modified_size() { @@ -383,6 +411,7 @@ private: cache_block_state m_status[SECTOR_CHUNCK_SIZE]; bool m_ignore_on_fill_status[SECTOR_CHUNCK_SIZE]; bool m_set_modified_on_fill[SECTOR_CHUNCK_SIZE]; + bool m_readable[SECTOR_CHUNCK_SIZE]; unsigned get_sector_index(mem_access_sector_mask_t sector_mask) { -- cgit v1.3 From 6347147dbd059410648aaf1045cfc73a7294b4e6 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 12 Dec 2017 21:46:54 -0500 Subject: support for 9.1 --- Makefile | 1 + setup_environment | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index e83de9a..95e4432 100644 --- a/Makefile +++ b/Makefile @@ -161,6 +161,7 @@ $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib if [ ! -f $(SIM_LIB_DIR)/libcudart.so.6.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.6.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.7.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.7.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.8.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.8.0; fi + if [ ! -f $(SIM_LIB_DIR)/libcudart.so.9.1 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.9.1; fi $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib g++ -dynamiclib -Wl,-headerpad_max_install_names,-undefined,dynamic_lookup,-compatibility_version,1.1,-current_version,1.1\ diff --git a/setup_environment b/setup_environment index 0895d44..8a529c3 100644 --- a/setup_environment +++ b/setup_environment @@ -43,7 +43,7 @@ CC_VERSION=`gcc --version | head -1 | awk '{for(i=1;i<=NF;i++){ if(match($i,/^[0 CUDA_VERSION_STRING=`$CUDA_INSTALL_PATH/bin/nvcc --version | awk '/release/ {print $5;}' | sed 's/,//'`; CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("%02u%02u", 10*int($1), 10*$2);}'` -if [ $CUDA_VERSION_NUMBER -gt 8000 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then +if [ $CUDA_VERSION_NUMBER -gt 9100 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then echo "ERROR ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; return elif [ $CUDA_VERSION_NUMBER -gt 4020 ]; then -- cgit v1.3 From bbdb4b29c89751846e48238bdd7b1751636d3dd0 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 13 Dec 2017 11:12:47 -0500 Subject: Replacing the 8.0 regressions with 9.1 --- Jenkinsfile | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index bdf8294..c9fbc30 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -10,8 +10,8 @@ pipeline { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ make -j' - }, "8.0" : { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ + }, "9.1" : { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ make -j' } @@ -29,7 +29,7 @@ pipeline { cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ make -j -C ./benchmarks/src all' - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ @@ -43,8 +43,8 @@ pipeline { source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS,PASCALTITANX,PASCALTITANX-PTXPLUS -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' - }, "8.0-rodinia": { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ + }, "9.1-rodinia": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,PASCALTITANX -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' -- cgit v1.3 From dd3b1fa1bda98de0d1c97cde46413043bcdbc8c2 Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Tue, 20 Feb 2018 19:38:14 -0600 Subject: Added cudaDeviceGetAttribute --- libcuda/cuda_runtime_api.cc | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index cbe8a11..79cca04 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -816,6 +816,50 @@ __host__ cudaError_t CUDARTAPI cudaGetDeviceProperties(struct cudaDeviceProp *pr } } +__host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDeviceAttr attr, int device) +{ + const struct cudaDeviceProp *prop; + _cuda_device_id *dev = GPGPUSim_Init(); + if (device <= dev->num_devices() ) { + prop = dev->get_prop(); + switch (attr) { + case 5: + *value= prop->maxGridSize[0]; + break; + case 6: + *value= prop->maxGridSize[1]; + break; + case 7: + *value= prop->maxGridSize[2]; + break; + case 10: + *value= prop->warpSize; + break; + case 12: + *value= prop->regsPerBlock; + break; + case 14: + *value= prop->textureAlignment ; + break; + case 16: + *value= prop->multiProcessorCount ; + break; + case 39: + *value= dev->get_gpgpu()->threads_per_core(); + break; + case 75: + *value= 8 ; + break; + case 76: + *value= 3 ; + break; + } + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorInvalidDevice; + } +} + __host__ cudaError_t CUDARTAPI cudaChooseDevice(int *device, const struct cudaDeviceProp *prop) { _cuda_device_id *dev = GPGPUSim_Init(); -- cgit v1.3 From 7796a731c2a7d14a58d1369af62c8ad589c63921 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 21 Feb 2018 17:44:35 -0500 Subject: Cannot do GTX480 in CUDA 9.1 -- since sm_20 is now dead --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index c9fbc30..831e7d8 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -46,7 +46,7 @@ pipeline { }, "9.1-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,PASCALTITANX -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C PASCALTITANX -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "4.2-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ -- cgit v1.3 From 25dcce6d91d088eb91d26fe0b6aa255090f24a4b Mon Sep 17 00:00:00 2001 From: tgrogers Date: Thu, 22 Feb 2018 15:59:37 -0500 Subject: run all the configs, do 9.1 on the sdk and stop the setup environment from complaining about cuda version --- Jenkinsfile | 9 +++++++-- setup_environment | 2 +- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index cf9d71e..0f6314f 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -46,12 +46,17 @@ pipeline { }, "9.1-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C PASCALTITANX -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C PASCALTITANX,TITANX-P102 -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "4.2-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480,PASCALTITANX -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480,PASCALTITANX,TITANX-P102 -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' + }, "9.1-sdk-4.2": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C PASCALTITANX,TITANX-P102 -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' } } diff --git a/setup_environment b/setup_environment index 8a529c3..cd6452e 100644 --- a/setup_environment +++ b/setup_environment @@ -46,7 +46,7 @@ CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("% if [ $CUDA_VERSION_NUMBER -gt 9100 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then echo "ERROR ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; return -elif [ $CUDA_VERSION_NUMBER -gt 4020 ]; then +elif [ $CUDA_VERSION_NUMBER -gt 9100 ]; then echo "WARNING ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not fully tested with CUDA version $CUDA_VERSION_STRING (please see README)"; fi -- cgit v1.3 From 423dc13a99e5e23d48569a8d9fa844ff5de06ca0 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Fri, 23 Feb 2018 10:46:13 -0500 Subject: fixing the libcardt link issue --- Makefile | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index e83de9a..1f043fa 100644 --- a/Makefile +++ b/Makefile @@ -62,7 +62,7 @@ LIBS = cuda-sim gpgpu-sim_uarch $(INTERSIM) gpgpusimlib TARGETS = ifeq ($(shell uname),Linux) - TARGETS += $(SIM_LIB_DIR)/libcudart.so + TARGETS += $(SIM_LIB_DIR)/libcudart.so else # MAC TARGETS += $(SIM_LIB_DIR)/libcudart.dylib endif @@ -75,6 +75,7 @@ else TARGETS += $(SIM_LIB_DIR)/libOpenCL.so endif TARGETS += cuobjdump_to_ptxplus/cuobjdump_to_ptxplus + TARGETS += $(SIM_LIB_DIR)/gpgpusim.out MCPAT= MCPAT_OBJ_DIR= @@ -143,7 +144,7 @@ no_opencl_support: @echo "Warning: gpgpu-sim is building without opencl support. Make sure NVOPENCL_LIBDIR and NVOPENCL_INCDIR are set" $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib - g++ -shared -Wl,-soname,libcudart_$(GPGPUSIM_BUILD).so \ + g++ -shared -Wl \ $(SIM_OBJ_FILES_DIR)/libcuda/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/decuda_pred_table/*.o \ @@ -162,6 +163,9 @@ $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib if [ ! -f $(SIM_LIB_DIR)/libcudart.so.7.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.7.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.8.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.8.0; fi +$(SIM_LIB_DIR)/gpgpusim.out: makedirs $(LIBS) cudalib $(SIM_LIB_DIR)/libcudart.so + g++ -std=c++0x -L$(SIM_LIB_DIR) -lcudart -o $(SIM_LIB_DIR)/gpgpusim.out src/trace-driven/gpgpusim_trace_driven_main.cc + $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib g++ -dynamiclib -Wl,-headerpad_max_install_names,-undefined,dynamic_lookup,-compatibility_version,1.1,-current_version,1.1\ $(SIM_OBJ_FILES_DIR)/libcuda/*.o \ -- cgit v1.3 From baba81bd9bd5ec5fd07e70b307ccbfeac2d90e0e Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 12 Mar 2018 16:52:26 -0400 Subject: fixibg sectir l1 deadlock bug --- src/gpgpu-sim/gpu-cache.cc | 4 ++-- src/gpgpu-sim/gpu-cache.h | 15 ++++++++++++--- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 0602e20..8191f62 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -962,7 +962,7 @@ void baseline_cache::send_read_request(new_addr_type addr, new_addr_type block_a m_mshrs.add(mshr_addr,mf); m_extra_mf_fields[mf] = extra_mf_fields(mshr_addr,mf->get_addr(),cache_index, mf->get_data_size(), m_config); mf->set_data_size( m_config.get_atom_sz() ); - mf->set_addr( block_addr ); + mf->set_addr( mshr_addr ); m_miss_queue.push_back(mf); mf->set_status(m_miss_queue_status,time); if(!wa) @@ -1432,7 +1432,7 @@ data_cache::process_tag_probe( bool wr, access_status = (this->*m_wr_hit)( addr, cache_index, mf, time, events, probe_status ); - }else if ( probe_status != RESERVATION_FAIL ) { + }else if ( (probe_status != RESERVATION_FAIL) || (probe_status == RESERVATION_FAIL && m_config.m_write_alloc_policy == NO_WRITE_ALLOCATE) ) { access_status = (this->*m_wr_miss)( addr, cache_index, mf, time, events, probe_status ); diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 0d07878..76b07a2 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -39,7 +39,7 @@ #include enum cache_block_state { - INVALID, + INVALID=0, RESERVED, VALID, MODIFIED @@ -125,6 +125,7 @@ struct cache_block_t { virtual unsigned get_modified_size() = 0; virtual void set_m_readable(bool readable, mem_access_sector_mask_t sector_mask)=0; virtual bool is_readable(mem_access_sector_mask_t sector_mask)=0; + virtual void print_status()=0; virtual ~cache_block_t() {} @@ -144,7 +145,7 @@ struct line_cache_block: public cache_block_t { m_set_modified_on_fill = false; m_readable = true; } - void allocate( new_addr_type tag, new_addr_type block_addr, unsigned time, mem_access_sector_mask_t sector_mask ) + void allocate( new_addr_type tag, new_addr_type block_addr, unsigned time, mem_access_sector_mask_t sector_mask) { m_tag=tag; m_block_addr=block_addr; @@ -220,6 +221,9 @@ struct line_cache_block: public cache_block_t { virtual bool is_readable(mem_access_sector_mask_t sector_mask) { return m_readable; } + virtual void print_status() { + printf("m_block_addr is %u, status = %u\n", m_block_addr, m_status); + } private: @@ -401,6 +405,11 @@ struct sector_cache_block : public cache_block_t { return modified * SECTOR_SIZE; } + virtual void print_status() { + printf("m_block_addr is %u, status = %u %u %u %u\n", m_block_addr, m_status[0], m_status[1], m_status[2], m_status[3]); + } + + private: unsigned m_sector_alloc_time[SECTOR_CHUNCK_SIZE]; unsigned m_last_sector_access_time[SECTOR_CHUNCK_SIZE]; @@ -1030,7 +1039,7 @@ protected: std::string m_name; cache_config &m_config; tag_array* m_tag_array; - mshr_table m_mshrs; + mshr_table m_mshrs; std::list m_miss_queue; enum mem_fetch_status m_miss_queue_status; mem_fetch_interface *m_memport; -- cgit v1.3 From d4db0d28cca5fb9ce6496aa7a18859a97e1bd56d Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 13 Mar 2018 10:56:12 -0400 Subject: Regressing all the new titan configs --- Jenkinsfile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index bdf8294..b35a502 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -41,17 +41,17 @@ pipeline { parallel "4.2-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS,PASCALTITANX,PASCALTITANX-PTXPLUS -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS,TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "8.0-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/8.0_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,PASCALTITANX -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "4.2-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480,PASCALTITANX -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480,PASCALTITANX,TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' } } -- cgit v1.3 From d907266173d129c0e5f1fd7902a77ab30c43ad73 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 13 Mar 2018 11:18:54 -0400 Subject: CUDA 9.1 cannot run GTX480 - support for sm_20 is dead --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 7b103df..00f760e 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -46,7 +46,7 @@ pipeline { }, "9.1-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' }, "4.2-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ -- cgit v1.3 From 8ea96cfef19bb5dd91756c1d20e4aae93f0cfa36 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Tue, 13 Mar 2018 11:31:11 -0400 Subject: Update gpgpusim.config --- configs/Pascal-P100-HBM/gpgpusim.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config index 533a865..bd868ac 100644 --- a/configs/Pascal-P100-HBM/gpgpusim.config +++ b/configs/Pascal-P100-HBM/gpgpusim.config @@ -56,7 +56,7 @@ # Pascal GP100 has 64KB Shared memory -gpgpu_cache:dl1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 -gpgpu_shmem_size 65536 --gmem_skip_L1D 1 +-gmem_skip_L1D 0 -icnt_flit_size 40 -gpgpu_n_cluster_ejection_buffer_size 32 -- cgit v1.3 From edb99bbfb39ddd09fc7124cd481dca484a60c5b8 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Tue, 13 Mar 2018 12:31:49 -0400 Subject: adding the config file for P102 for gpgpu-sim 3.x --- configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 43 +++++++++------------- 1 file changed, 18 insertions(+), 25 deletions(-) diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 4407870..28689ce 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -33,25 +33,21 @@ # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 4 SFU units +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,1,4,1,4,1,4,1,9 +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 -gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 4 --gpgpu_num_dp_units 1 +-gpgpu_num_sfu_units 1 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 +# SFU is 32-width in pascal, then dp units initiation is 1 cycle -ptx_opcode_latency_int 4,13,4,5,145 -ptx_opcode_initiation_int 1,1,1,1,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 8,8,8,8,130 --ptx_opcode_initiation_sfu 4 --ptx_opcode_latency_sfu 8 +-ptx_opcode_initiation_dp 4,8,4,4,130 # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo @@ -59,36 +55,33 @@ # Pascal GP102 has 96KB Shared memory # Pascal GP102 has 64KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 98304 -gmem_skip_L1D 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 N:64:128:16,L:B:m:W:L,A:128:8,4:0,32 +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 # 4 KB Inst. --gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,A:2:48,4 +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # 48 KB Tex --gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # 12 KB Const --gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,A:2:64,4 +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # enable operand collector ## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units --gpgpu_operand_collector_num_units_sp 12 --gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 -gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_units_dp 6 -gpgpu_operand_collector_num_in_ports_sp 4 -gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 4 --gpgpu_operand_collector_num_out_ports_sfu 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 -gpgpu_operand_collector_num_in_ports_mem 1 -gpgpu_operand_collector_num_out_ports_mem 1 --gpgpu_operand_collector_num_in_ports_dp 1 --gpgpu_operand_collector_num_out_ports_dp 1 # gpgpu_num_reg_banks should be increased to 32 -gpgpu_num_reg_banks 32 @@ -105,7 +98,7 @@ -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 100 +-rop_latency 120 -dram_latency 100 # dram model config @@ -130,10 +123,10 @@ # Use the same GDDR5 timing from hynix H5GQ1H24AFR # disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: - CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" -# Pascal GP102 has four schedulers per core +# Fermi has two schedulers per core -gpgpu_num_sched_per_core 4 # Two Level Scheduler with active and pending pools #-gpgpu_scheduler two_level_active:6:0:1 -- cgit v1.3 From f35ae9d24fa14f838352a95bc2c1445821f53449 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Tue, 13 Mar 2018 15:04:03 -0400 Subject: adding config file for P100 of gpgpsim3.x --- configs/Pascal-P100-HBM/gpgpusim.config | 6 +- .../gpgpu-sim-3.x/config_fermi_islip.icnt | 70 +++ configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config | 152 ++++++ .../PascalP100X/gpgpu-sim-3.x/gpuwattch_gtx480.xml | 538 +++++++++++++++++++++ 4 files changed, 762 insertions(+), 4 deletions(-) create mode 100644 configs/PascalP100X/gpgpu-sim-3.x/config_fermi_islip.icnt create mode 100644 configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config create mode 100755 configs/PascalP100X/gpgpu-sim-3.x/gpuwattch_gtx480.xml diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config index 533a865..0c4744a 100644 --- a/configs/Pascal-P100-HBM/gpgpusim.config +++ b/configs/Pascal-P100-HBM/gpgpusim.config @@ -56,7 +56,7 @@ # Pascal GP100 has 64KB Shared memory -gpgpu_cache:dl1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 -gpgpu_shmem_size 65536 --gmem_skip_L1D 1 +-gmem_skip_L1D 0 -icnt_flit_size 40 -gpgpu_n_cluster_ejection_buffer_size 32 @@ -86,7 +86,6 @@ -gpgpu_operand_collector_num_out_ports_mem 1 -gpgpu_operand_collector_num_in_ports_dp 1 -gpgpu_operand_collector_num_out_ports_dp 1 -# gpgpu_num_reg_banks should be increased to 32 -gpgpu_num_reg_banks 32 # shared memory bankconflict detection @@ -105,8 +104,7 @@ # memory partition latency config -rop_latency 120 -# DRAM latency should be lower compared to other configs, due to high-speed interposer connection --dram_latency 60 +-dram_latency 100 # dram model config -gpgpu_dram_scheduler 1 diff --git a/configs/PascalP100X/gpgpu-sim-3.x/config_fermi_islip.icnt b/configs/PascalP100X/gpgpu-sim-3.x/config_fermi_islip.icnt new file mode 100644 index 0000000..602daee --- /dev/null +++ b/configs/PascalP100X/gpgpu-sim-3.x/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 52; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config new file mode 100644 index 0000000..8afdd7f --- /dev/null +++ b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config @@ -0,0 +1,152 @@ +# This config models the Pascal GP100 +# For more info about this card, see Nvidia White paper +# https://images.nvidia.com/content/pdf/tesla/whitepaper/pascal-architecture-whitepaper.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 60 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 32 +-gpgpu_n_sub_partition_per_mchannel 1 + +# Pscal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA GP100 clock domains are adopted from +# https://en.wikipedia.org/wiki/Nvidia_Tesla +-gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 2,2,1,2,2,1,4 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 2,2,2,2,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP100 has 64KB Shared memory +# Pascal GP100 has 48KB L1 cache +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_shmem_size 65536 +-gmem_skip_L1D 0 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 14 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_units_mem 10 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for HBM, 32 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: + CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/PascalP100X/gpgpu-sim-3.x/gpuwattch_gtx480.xml b/configs/PascalP100X/gpgpu-sim-3.x/gpuwattch_gtx480.xml new file mode 100755 index 0000000..304e0fd --- /dev/null +++ b/configs/PascalP100X/gpgpu-sim-3.x/gpuwattch_gtx480.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.3 From a43bb3a68074f4b4be9b50b307dfddfb20386745 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Tue, 13 Mar 2018 15:38:55 -0400 Subject: fixing the inter nodes in P102 gpgpusim3.x --- configs/PascalP100X/gpgpu-sim-3.x/config_fermi_islip.icnt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/PascalP100X/gpgpu-sim-3.x/config_fermi_islip.icnt b/configs/PascalP100X/gpgpu-sim-3.x/config_fermi_islip.icnt index 602daee..d26c8d9 100644 --- a/configs/PascalP100X/gpgpu-sim-3.x/config_fermi_islip.icnt +++ b/configs/PascalP100X/gpgpu-sim-3.x/config_fermi_islip.icnt @@ -7,7 +7,7 @@ network_count = 2; // Topology topology = fly; -k = 52; +k = 60; n = 1; // Routing -- cgit v1.3 From dafe4afd3e4a8a53fc0294b8769787ebf895cb9d Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 13 Mar 2018 16:04:07 -0400 Subject: explicitly get the data here --- Jenkinsfile | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 00f760e..55bfaf8 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -28,12 +28,14 @@ pipeline { source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src all' + make -j -C ./benchmarks/src all' && \ + make -C ./benchmarks/src data' sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src/ all' + make -j -C ./benchmarks/src/ all' && \ + make -C ./benchmarks/src data' } } stage('regress'){ -- cgit v1.3 From c78085c7cf885ea311896df5c2e7df662e0b0dea Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 13 Mar 2018 17:04:49 -0400 Subject: fixing jenkinsfile error --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 55bfaf8..2d4bf18 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -28,13 +28,13 @@ pipeline { source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src all' && \ + make -j -C ./benchmarks/src all && \ make -C ./benchmarks/src data' sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src/ all' && \ + make -j -C ./benchmarks/src/ all && \ make -C ./benchmarks/src data' } } -- cgit v1.3 From 7abcf1cf783cd26912d250492e858ebbc1c04d2c Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 13 Mar 2018 17:17:00 -0400 Subject: Just make the relevant apps - don't waste time making stuff you don't use --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 2d4bf18..8e0fc40 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -28,13 +28,13 @@ pipeline { source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src all && \ + make -j -C ./benchmarks/src rodinia-2.0-ft sdk-4.2 && \ make -C ./benchmarks/src data' sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src/ all && \ + make -j -C ./benchmarks/src/ rodinia-2.0-ft sdk-4.2 && \ make -C ./benchmarks/src data' } } -- cgit v1.3 From 47573c62a1f0eb2746e71a386499b2ad4a7e8cb6 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 13 Mar 2018 17:19:14 -0400 Subject: Just make the relevant apps - don't waste time making stuff you don't use --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 8e0fc40..1aea232 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -28,13 +28,13 @@ pipeline { source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src rodinia-2.0-ft sdk-4.2 && \ + make -j -C ./benchmarks/src rodinia_2.0-ft sdk-4.2 && \ make -C ./benchmarks/src data' sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src/ rodinia-2.0-ft sdk-4.2 && \ + make -j -C ./benchmarks/src/ rodinia_2.0-ft sdk-4.2 && \ make -C ./benchmarks/src data' } } -- cgit v1.3 From 35ba74f137e7d3eae292882442a358bff37f72f1 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 14 Mar 2018 17:48:27 -0400 Subject: Adding the ability to plot all the runs automatically --- Jenkinsfile | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 1aea232..157f865 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -40,26 +40,35 @@ pipeline { } stage('regress'){ steps { + parallel "4.2-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS,TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS -N regress-$$ && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$ && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$ -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' }, "9.1-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$ -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' }, "4.2-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480,TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$ -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' }, "9.1-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$' + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$ -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' } } } -- cgit v1.3 From f6b87662a042934d3d2dd0229eb47e9788d8911f Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 14 Mar 2018 17:56:41 -0400 Subject: link the data to vut build times --- Jenkinsfile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 157f865..c9b4ee4 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -23,7 +23,8 @@ pipeline { sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ cd gpgpu-sim_simulations && \ git checkout purdue-cluster && \ - git pull' + git pull && \ + ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ -- cgit v1.3 From ae834f285afa1a628b8ab9ed01869ac864de5ff7 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 14 Mar 2018 17:59:47 -0400 Subject: delete the dir, then link it --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index c9b4ee4..73644d5 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -24,7 +24,7 @@ pipeline { cd gpgpu-sim_simulations && \ git checkout purdue-cluster && \ git pull && \ - ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' + rm -r ./benchmarks/data_dirs && ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ -- cgit v1.3 From 2c97d0c4214baab4497bbdd28c627b67a8c73dc1 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 14 Mar 2018 19:11:38 -0400 Subject: forgot stats file on others --- Jenkinsfile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 73644d5..a8d6302 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -54,21 +54,21 @@ pipeline { source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$ -N regress-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$ -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' }, "4.2-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480,TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$ -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' }, "9.1-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$ -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' } } -- cgit v1.3 From 8334534f1a31fa86b37054389715a50b5d8308b3 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 14 Mar 2018 20:56:06 -0400 Subject: Adding in a .csv extension --- Jenkinsfile | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index a8d6302..7836dc4 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -47,29 +47,29 @@ pipeline { source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$ && \ - ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$ -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' }, "9.1-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$ -N regress-$$ && \ - ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$ -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N regress-$$ && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' }, "4.2-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480,TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$ && \ - ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$ -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' }, "9.1-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$ && \ - ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$ -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' } } } -- cgit v1.3 From 2ac6898a8dc70592f016ef5f3a12b67135f9b8d1 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 18 Mar 2018 02:26:47 -0400 Subject: Adding in auto-correlation plots --- Jenkinsfile | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 7836dc4..2cff7b2 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -73,7 +73,28 @@ pipeline { } } } - + stage('4.2-correlate'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C TITANX-P102,P100-HBM > stats-4.2.csv && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ + ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-4.2.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ + scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' + } + } + stage('9.1-correlate'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C TITANX-P102,P100-HBM > stats-9.1.csv && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ + ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ + scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' + } + } } post { success { -- cgit v1.3 From 325c8951b18b257acefd62f5c25873a33fdcc59c Mon Sep 17 00:00:00 2001 From: letr63jd56 Date: Mon, 19 Mar 2018 12:38:09 -0700 Subject: temporary fixes to parsing issues --- src/cuda-sim/ptx.l | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 5471d6f..ea1e9da 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -162,6 +162,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.file TC; BEGIN(INITIAL); return FILE_DIRECTIVE; \.func TC; BEGIN(IN_FUNC_DECL); return FUNC_DIRECTIVE; // blocking opcode parsing in case the function has the same name as an opcode (e.g. sin(), cos()) \.global TC; return GLOBAL_DIRECTIVE; +\.global.volatile TC; return GLOBAL_DIRECTIVE; //AMRUTH: TODO: fix this! \.local TC; return LOCAL_DIRECTIVE; \.loc TC; return LOC_DIRECTIVE; \.maxnctapersm TC; return MAXNCTAPERSM_DIRECTIVE; @@ -233,6 +234,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.u32 TC; return U32_TYPE; \.u64 TC; return U64_TYPE; \.f16 TC; return F16_TYPE; +\.f16x2 TC; return F16_TYPE; /* AMRUTH: TODO: figure out what this should really be */ \.f32 TC; return F32_TYPE; \.f64 TC; return F64_TYPE; \.ff64 TC; return FF64_TYPE; -- cgit v1.3 From c6fcfc7e9509b087f932057f18fc4fe71b955382 Mon Sep 17 00:00:00 2001 From: letr63jd56 Date: Tue, 20 Mar 2018 11:33:18 -0700 Subject: code to load the embedded ptx directly and prevent cuobjdump to dump everytime we execute the code --- libcuda/cuda_runtime_api.cc | 34 ++++++++++++++++++++++++---------- src/cuda-sim/cuda-sim.cc | 4 +++- src/cuda-sim/ptx.l | 4 ++-- 3 files changed, 29 insertions(+), 13 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 79cca04..e7952e2 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1393,13 +1393,17 @@ std::string get_app_binary(){ * It is also responsible for extracting the libraries linked to the binary if the option is * enabled * */ + void extract_code_using_cuobjdump(){ - CUctx_st *context = GPGPUSim_Context(); + CUctx_st *context = GPGPUSim_Context(); + //prevent the dumping by cuobjdump everytime we execute the code! + const char *override_cuobjdump = getenv("CUOBJDUMP_SIM_FILE"); + + char fname[1024]; + if (override_cuobjdump == NULL) { char command[1000]; + std::string app_binary = get_app_binary(); - std::string app_binary = get_app_binary(); - - char fname[1024]; snprintf(fname,1024,"_cuobjdump_complete_output_XXXXXX"); int fd=mkstemp(fname); close(fd); @@ -1410,10 +1414,11 @@ void extract_code_using_cuobjdump(){ // Running cuobjdump using dynamic link to current process // Needs the option '-all' to extract PTX from CDP-enabled binary extern bool g_cdp_enabled; + //dump only for specific arch - TODO: will it save memory? if(!g_cdp_enabled) - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass %s > %s", app_binary.c_str(), fname); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_60 %s > %s", app_binary.c_str(), fname); else - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_60 -all %s > %s", app_binary.c_str(), fname); bool parse_output = true; int result = system(command); if(result) { @@ -1493,6 +1498,10 @@ void extract_code_using_cuobjdump(){ //Restore the original section list cuobjdumpSectionList = tmpsl; } + } else { + printf("GPGPU-Sim PTX: overriding cuobjdump with '%s' (CUOBJDUMP_SIM_FILE is set)\n", override_cuobjdump); + snprintf(fname,1024,override_cuobjdump); + } } //! Read file into char* @@ -1724,8 +1733,10 @@ cuobjdumpPTXSection* findPTXSection(const std::string identifier){ void cuobjdumpInit(){ CUctx_st *context = GPGPUSim_Context(); extract_code_using_cuobjdump(); //extract all the output of cuobjdump to _cuobjdump_*.* - cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); - cuobjdumpSectionList = mergeSections(cuobjdumpSectionList); + if (getenv("CUOBJDUMP_SIM_FILE")==NULL){ + cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); + cuobjdumpSectionList = mergeSections(cuobjdumpSectionList); + } } std::map fatbinmap; @@ -1760,7 +1771,9 @@ void cuobjdumpParseBinary(unsigned int handle){ } if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); - cuobjdumpPTXSection* ptx = findPTXSection(fname); + cuobjdumpPTXSection* ptx = NULL; + if(getenv("CUOBJDUMP_SIM_FILE")==NULL) + ptx = findPTXSection(fname); symbol_table *symtab; char *ptxcode; const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); @@ -1784,7 +1797,8 @@ void cuobjdumpParseBinary(unsigned int handle){ delete[] ptxplus_str; } else { symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxcode, handle); - printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); + //if CUOBJDUMP_SIM_FILE is not set, ptx is NULL. So comment below. + //printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); context->add_binary(symtab, handle); gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability ); } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index d4ace76..f51f57d 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -212,7 +212,9 @@ void function_info::ptx_assemble() m_start_PC = PC; addr_t n=0; // offset in m_instr_mem - s_g_pc_to_insn.reserve(s_g_pc_to_insn.size() + MAX_INST_SIZE*m_instructions.size()); + //Why s_g_pc_to_insn.size() is needed to reserve additional memory for insts? reserve is cumulative. + //s_g_pc_to_insn.reserve(s_g_pc_to_insn.size() + MAX_INST_SIZE*m_instructions.size()); + s_g_pc_to_insn.reserve(MAX_INST_SIZE*m_instructions.size()); for ( i=m_instructions.begin(); i != m_instructions.end(); i++ ) { ptx_instruction *pI = *i; if ( pI->is_label() ) { diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index ea1e9da..1b5d7f6 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -162,7 +162,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.file TC; BEGIN(INITIAL); return FILE_DIRECTIVE; \.func TC; BEGIN(IN_FUNC_DECL); return FUNC_DIRECTIVE; // blocking opcode parsing in case the function has the same name as an opcode (e.g. sin(), cos()) \.global TC; return GLOBAL_DIRECTIVE; -\.global.volatile TC; return GLOBAL_DIRECTIVE; //AMRUTH: TODO: fix this! +\.global.volatile TC; return GLOBAL_DIRECTIVE; //TODO: fix this! \.local TC; return LOCAL_DIRECTIVE; \.loc TC; return LOC_DIRECTIVE; \.maxnctapersm TC; return MAXNCTAPERSM_DIRECTIVE; @@ -234,7 +234,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.u32 TC; return U32_TYPE; \.u64 TC; return U64_TYPE; \.f16 TC; return F16_TYPE; -\.f16x2 TC; return F16_TYPE; /* AMRUTH: TODO: figure out what this should really be */ +\.f16x2 TC; return F16_TYPE; /* TODO: figure out what this should really be */ \.f32 TC; return F32_TYPE; \.f64 TC; return F64_TYPE; \.ff64 TC; return FF64_TYPE; -- cgit v1.3 From c3977ebf0549c2fd2d82d761008c172c74fcd113 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 20 Mar 2018 14:47:54 -0400 Subject: Adding in some setupscript stuff to properly print the build version and get rid of this not fully tested warning --- setup_environment | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/setup_environment b/setup_environment index 854a335..96cc362 100644 --- a/setup_environment +++ b/setup_environment @@ -6,7 +6,11 @@ export GPGPUSIM_SETUP_ENVIRONMENT_WAS_RUN= export GPGPUSIM_ROOT="$( cd "$( dirname "$BASH_SOURCE" )" && pwd )" GPGPUSIM_VERSION_STRING=`cat $GPGPUSIM_ROOT/version | awk '/Version/ {print $8}'` -GPGPUSIM_BUILD_STRING=`cat $GPGPUSIM_ROOT/version | awk '/Change/ {print $6}'` +#Detect Git branch and commit # +GIT_COMMIT=`git log -n 1 | head -1 | sed -re 's/commit (.*)/\1/'` +GIT_FILES_CHANGED=`git diff --numstat --cached && git diff --numstat | wc | sed -re 's/^\s+([0-9]+).*/\1/'` +GPGPUSIM_BUILD_STRING="gpgpu-sim_git-commit-$GIT_COMMIT-modified_$GIT_FILES_CHANGED" + echo -n "GPGPU-Sim version $GPGPUSIM_VERSION_STRING (build $GPGPUSIM_BUILD_STRING) "; if [ ! -n "$CUDA_INSTALL_PATH" ]; then @@ -43,11 +47,9 @@ CC_VERSION=`gcc --version | head -1 | awk '{for(i=1;i<=NF;i++){ if(match($i,/^[0 CUDA_VERSION_STRING=`$CUDA_INSTALL_PATH/bin/nvcc --version | awk '/release/ {print $5;}' | sed 's/,//'`; CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("%02u%02u", 10*int($1), 10*$2);}'` -if [ $CUDA_VERSION_NUMBER -gt 8000 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then +if [ $CUDA_VERSION_NUMBER -gt 9100 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then echo "ERROR ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; return -elif [ $CUDA_VERSION_NUMBER -gt 4020 ]; then - echo "WARNING ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not fully tested with CUDA version $CUDA_VERSION_STRING (please see README)"; fi if [ $# = '1' ] ; -- cgit v1.3 From e87f15a76c5b3225911850fcdb4074c16682ae50 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Wed, 21 Mar 2018 13:40:06 -0400 Subject: Change 124 by jain156@akshayj-lt1 on 2016/12/08 20:17:53 Added Memory divergence stats Data shows same divergence characteristics across PTX and PTX+ --- src/gpgpu-sim/shader.cc | 9 +++++++++ src/gpgpu-sim/shader.h | 4 ++++ 2 files changed, 13 insertions(+) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index bf482fb..72e0266 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -438,6 +438,9 @@ void shader_core_stats::print( FILE* fout ) const fprintf(fout,"gpgpu_n_mem_texture = %d\n", gpgpu_n_mem_texture); fprintf(fout,"gpgpu_n_mem_const = %d\n", gpgpu_n_mem_const); + fprintf(fout,"gpgpu_n_times_gmem_accesses_by_warps = %lld\n", gpgpu_n_times_gmem_accesses_by_warps); + fprintf(fout,"gpgpu_n_total_gmem_accesses_by_warps = %lld\n", gpgpu_n_total_gmem_accesses_by_warps); + fprintf(fout, "gpgpu_n_load_insn = %d\n", gpgpu_n_load_insn); fprintf(fout, "gpgpu_n_store_insn = %d\n", gpgpu_n_store_insn); fprintf(fout, "gpgpu_n_shmem_insn = %d\n", gpgpu_n_shmem_insn); @@ -740,9 +743,15 @@ void shader_core_ctx::fetch() void shader_core_ctx::func_exec_inst( warp_inst_t &inst ) { + unsigned starting_queue_size; execute_warp_inst_t(inst); if( inst.is_load() || inst.is_store() ) + starting_queue_size = inst.accessq_count(); inst.generate_mem_accesses(); + if ( inst.space.get_type() == global_space ) { + m_stats->gpgpu_n_times_gmem_accesses_by_warps++; + m_stats->gpgpu_n_total_gmem_accesses_by_warps += inst.accessq_count() - starting_queue_size; + } } void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* next_inst, const active_mask_t &active_mask, unsigned warp_id ) diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 5b41c06..2475677 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1470,6 +1470,10 @@ struct shader_core_stats_pod { int gpgpu_n_mem_read_global; int gpgpu_n_mem_write_global; int gpgpu_n_mem_read_inst; + + //warps memory divergence count + unsigned long long gpgpu_n_times_gmem_accesses_by_warps; + unsigned long long gpgpu_n_total_gmem_accesses_by_warps; int gpgpu_n_mem_l2_writeback; int gpgpu_n_mem_l1_write_allocate; -- cgit v1.3 From 2d8d4455aa710914e87c5611cbb71f9330cdbc73 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Thu, 22 Mar 2018 03:53:50 -0400 Subject: Change 180 by jain156@akshayj-lt1 on 2017/03/30 11:48:07 Added Memory Access breakdown statistics. Divided INST stats into INST type and INST Mem accesses. --- src/cuda-sim/cuda-sim.cc | 44 ++++++++++++++++++++------------------------ src/cuda-sim/cuda-sim.h | 2 ++ src/cuda-sim/opcodes.def | 2 ++ src/gpgpu-sim/gpu-sim.cc | 7 ++++--- 4 files changed, 28 insertions(+), 27 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 2f166aa..17a7798 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -52,8 +52,10 @@ int gpgpu_ptx_instruction_classification; void ** g_inst_classification_stat = NULL; +void ** g_inst_mem_classification_stat = NULL; void ** g_inst_op_classification_stat= NULL; int g_ptx_kernel_count = -1; // used for classification stat collection purposes +int g_ptx_kernel_count_prev = -1; // used for classification stat collection purposes int g_debug_execution = 0; int g_debug_thread_uid = 0; addr_t g_debug_pc = 0xBEEF1518; @@ -1240,12 +1242,16 @@ void init_inst_classification_stat() #define MAX_CLASS_KER 1024 char kernelname[MAX_CLASS_KER] =""; if (!g_inst_classification_stat) g_inst_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); - snprintf(kernelname, MAX_CLASS_KER, "Kernel %d Classification\n",g_ptx_kernel_count ); + snprintf(kernelname, MAX_CLASS_KER, "Kernel %d INST Classification",g_ptx_kernel_count ); assert( g_ptx_kernel_count < MAX_CLASS_KER ) ; // a static limit on number of kernels increase it if it fails! g_inst_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,20); + if (!g_inst_mem_classification_stat) g_inst_mem_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); + snprintf(kernelname, MAX_CLASS_KER, "Kernel %d MEM Classification",g_ptx_kernel_count ); + g_inst_mem_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,20); if (!g_inst_op_classification_stat) g_inst_op_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); - snprintf(kernelname, MAX_CLASS_KER, "Kernel %d OP Classification\n",g_ptx_kernel_count ); + snprintf(kernelname, MAX_CLASS_KER, "Kernel %d OP Classification",g_ptx_kernel_count ); g_inst_op_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,100); + g_ptx_kernel_count_prev++; } static unsigned get_tex_datasize( const ptx_instruction *pI, ptx_thread_info *thread ) @@ -1323,6 +1329,15 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) delete pJ; pI = pI_saved; + if ( gpgpu_ptx_instruction_classification ) { + init_inst_classification_stat(); + if (op_classification) + StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], op_classification); + if (pI->get_space().get_type()) + StatAddSample( g_inst_mem_classification_stat[g_ptx_kernel_count], ( int )pI->get_space().get_type()); + StatAddSample( g_inst_op_classification_stat[g_ptx_kernel_count], (int) pI->get_opcode() ); + } + // Run exit instruction if exit option included if(pI->is_exit()) exit_impl(pI,this); @@ -1408,27 +1423,6 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) if(!(this->m_functionalSimulationMode)) ptx_file_line_stats_add_exec_count(pI); - if ( gpgpu_ptx_instruction_classification ) { - init_inst_classification_stat(); - unsigned space_type=0; - switch ( pI->get_space().get_type() ) { - case global_space: space_type = 10; break; - case local_space: space_type = 11; break; - case tex_space: space_type = 12; break; - case surf_space: space_type = 13; break; - case param_space_kernel: - case param_space_local: - space_type = 14; break; - case shared_space: space_type = 15; break; - case const_space: space_type = 16; break; - default: - space_type = 0 ; - break; - } - StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], op_classification); - if (space_type) StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], ( int )space_type); - StatAddSample( g_inst_op_classification_stat[g_ptx_kernel_count], (int) pI->get_opcode() ); - } if ( (g_ptx_sim_num_insn % 100000) == 0 ) { dim3 ctaid = get_ctaid(); dim3 tid = get_tid(); @@ -1848,8 +1842,10 @@ void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL ) //******PRINTING******* printf( "GPGPU-Sim: Done functional simulation (%u instructions simulated).\n", g_ptx_sim_num_insn ); + fflush(stdout); if ( gpgpu_ptx_instruction_classification ) { - StatDisp( g_inst_classification_stat[g_ptx_kernel_count]); + StatDisp ( g_inst_classification_stat[g_ptx_kernel_count]); + StatDisp ( g_inst_mem_classification_stat[g_ptx_kernel_count]); StatDisp ( g_inst_op_classification_stat[g_ptx_kernel_count]); } diff --git a/src/cuda-sim/cuda-sim.h b/src/cuda-sim/cuda-sim.h index 958daba..ef9549f 100644 --- a/src/cuda-sim/cuda-sim.h +++ b/src/cuda-sim/cuda-sim.h @@ -44,8 +44,10 @@ extern int g_ptx_sim_mode; extern int g_debug_execution; extern int g_debug_thread_uid; extern void ** g_inst_classification_stat; +extern void ** g_inst_mem_classification_stat; extern void ** g_inst_op_classification_stat; extern int g_ptx_kernel_count; // used for classification stat collection purposes +extern int g_ptx_kernel_count_prev; // used for classification stat collection purposes void ptx_opcocde_latency_options (option_parser_t opp); extern class kernel_info_t *gpgpu_opencl_ptx_sim_init_grid(class function_info *entry, diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index e1b1422..ccf64d8 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -35,7 +35,9 @@ SFU 4 Mem(except Tex) 5 Tex 6 Nop 7 +Breakpoint 9 Other 10 +Scalar video 11 */ OP_DEF(ABS_OP,abs_impl,"abs",1,1) OP_DEF(ADD_OP,add_impl,"add",1,1) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 17f1714..121e079 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -445,7 +445,7 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) "1"); option_parser_register(opp, "-gpgpu_ptx_instruction_classification", OPT_INT32, &gpgpu_ptx_instruction_classification, - "if enabled will classify ptx instruction types per kernel (Max 255 kernels now)", + "if enabled will classify ptx instruction types per kernel (Max 1024 kernels now)", "0"); option_parser_register(opp, "-gpgpu_ptx_sim_mode", OPT_INT32, &g_ptx_sim_mode, "Select between Performance (default) or Functional simulation (1)", @@ -1076,8 +1076,9 @@ void gpgpu_sim::gpu_print_stat() insn_warp_occ_print(stdout); } if ( gpgpu_ptx_instruction_classification ) { - StatDisp( g_inst_classification_stat[g_ptx_kernel_count]); - StatDisp( g_inst_op_classification_stat[g_ptx_kernel_count]); + StatDisp( g_inst_classification_stat[g_ptx_kernel_count_prev]); + StatDisp( g_inst_mem_classification_stat[g_ptx_kernel_count_prev]); + StatDisp( g_inst_op_classification_stat[g_ptx_kernel_count_prev]); } #ifdef GPGPUSIM_POWER_MODEL -- cgit v1.3 From 777ab7fd6761a6250bc8e4f37994125a3f8d331b Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Thu, 22 Mar 2018 04:20:13 -0400 Subject: Change 252 by jain156@akshayj-lt1 on 2017/05/29 10:51:32 Checking in the data footprint stats as reported in the micro paper. The implementation uses gpgpu pointer, due to which I don't feel fine pushing to mainline. May be I can do the stats check and increment in l2cache.cc through a public function to avoid exposing gpgpu pointer to public --- src/gpgpu-sim/gpu-sim.cc | 2 +- src/gpgpu-sim/gpu-sim.h | 3 +++ src/gpgpu-sim/l2cache.cc | 20 ++++++++++++++++---- src/gpgpu-sim/l2cache.h | 8 ++++++-- src/gpgpusim_entrypoint.cc | 1 + 5 files changed, 27 insertions(+), 7 deletions(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 121e079..9a28b55 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -668,7 +668,7 @@ gpgpu_sim::gpgpu_sim( const gpgpu_sim_config &config ) m_memory_partition_unit = new memory_partition_unit*[m_memory_config->m_n_mem]; m_memory_sub_partition = new memory_sub_partition*[m_memory_config->m_n_mem_sub_partition]; for (unsigned i=0;im_n_mem;i++) { - m_memory_partition_unit[i] = new memory_partition_unit(i, m_memory_config, m_memory_stats); + m_memory_partition_unit[i] = new memory_partition_unit(i, m_memory_config, m_memory_stats, this); for (unsigned p = 0; p < m_memory_config->m_n_sub_partition_per_memory_channel; p++) { unsigned submpid = i * m_memory_config->m_n_sub_partition_per_memory_channel + p; m_memory_sub_partition[submpid] = m_memory_partition_unit[i]->get_sub_partition(p); diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 1778008..f9b5dad 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -36,6 +36,7 @@ #include #include #include +#include #include @@ -428,6 +429,8 @@ public: void perf_memcpy_to_gpu( size_t dst_start_addr, size_t count ); + std::unordered_set data_footprint_stats; + //The next three functions added to be used by the functional simulation function //! Get shader core configuration diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index b1465a8..a4aaf28 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -62,15 +62,16 @@ mem_fetch * partition_mf_allocator::alloc(new_addr_type addr, mem_access_type ty memory_partition_unit::memory_partition_unit( unsigned partition_id, const struct memory_config *config, - class memory_stats_t *stats ) -: m_id(partition_id), m_config(config), m_stats(stats), m_arbitration_metadata(config) + class memory_stats_t *stats, + class gpgpu_sim *gpu) +: m_id(partition_id), m_config(config), m_stats(stats), m_arbitration_metadata(config), m_gpu(gpu) { m_dram = new dram_t(m_id,m_config,m_stats,this); m_sub_partition = new memory_sub_partition*[m_config->m_n_sub_partition_per_memory_channel]; for (unsigned p = 0; p < m_config->m_n_sub_partition_per_memory_channel; p++) { unsigned sub_partition_id = m_id * m_config->m_n_sub_partition_per_memory_channel + p; - m_sub_partition[p] = new memory_sub_partition(sub_partition_id, m_config, stats); + m_sub_partition[p] = new memory_sub_partition(sub_partition_id, m_config, stats, m_gpu); } } @@ -310,11 +311,13 @@ void memory_partition_unit::print( FILE *fp ) const memory_sub_partition::memory_sub_partition( unsigned sub_partition_id, const struct memory_config *config, - class memory_stats_t *stats ) + class memory_stats_t *stats , + class gpgpu_sim *gpu) { m_id = sub_partition_id; m_config=config; m_stats=stats; + m_gpu=gpu; m_memcpy_cycle_offset = 0; assert(m_id < m_config->m_n_mem_sub_partition); @@ -410,6 +413,15 @@ void memory_sub_partition::cache_cycle( unsigned cycle ) bool read_sent = was_read_sent(events); MEM_SUBPART_DPRINTF("Probing L2 cache Address=%llx, status=%u\n", mf->get_addr(), status); + if ( (mf->get_access_type() == GLOBAL_ACC_R) || + (mf->get_access_type() == GLOBAL_ACC_W) || + (mf->get_access_type() == LOCAL_ACC_R) || + (mf->get_access_type() == LOCAL_ACC_W) || + (mf->get_access_type() == CONST_ACC_R) ) { + if (!m_gpu->data_footprint_stats.count(mf->get_addr())) + m_gpu->data_footprint_stats.insert(mf->get_addr()); + } + if ( status == HIT ) { if( !write_sent ) { // L2 cache replies diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index 2d13918..6aa7505 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -58,7 +58,7 @@ private: class memory_partition_unit { public: - memory_partition_unit( unsigned partition_id, const struct memory_config *config, class memory_stats_t *stats ); + memory_partition_unit( unsigned partition_id, const struct memory_config *config, class memory_stats_t *stats , class gpgpu_sim *gpu); ~memory_partition_unit(); bool busy() const; @@ -93,6 +93,8 @@ public: unsigned get_mpid() const { return m_id; } + gpgpu_sim *m_gpu; + private: unsigned m_id; @@ -145,7 +147,7 @@ private: class memory_sub_partition { public: - memory_sub_partition( unsigned sub_partition_id, const struct memory_config *config, class memory_stats_t *stats ); + memory_sub_partition( unsigned sub_partition_id, const struct memory_config *config, class memory_stats_t *stats, class gpgpu_sim *gpu); ~memory_sub_partition(); unsigned get_id() const { return m_id; } @@ -185,6 +187,8 @@ public: m_memcpy_cycle_offset += 1; } + gpgpu_sim *m_gpu; + private: // data unsigned m_id; //< the global sub partition ID diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index ad4587a..1ee980a 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -263,6 +263,7 @@ void print_simulation_time() s = difference - 60*(m + 60*(h + 24*d)); fflush(stderr); + printf("gpgpu_data_footprint = %u requests at L2\n", g_the_gpu->data_footprint_stats.size()); printf("\n\ngpgpu_simulation_time = %u days, %u hrs, %u min, %u sec (%u sec)\n", (unsigned)d, (unsigned)h, (unsigned)m, (unsigned)s, (unsigned)difference ); printf("gpgpu_simulation_rate = %u (inst/sec)\n", (unsigned)(g_the_gpu->gpu_tot_sim_insn / difference) ); -- cgit v1.3 From 160db7d46af433d12288505005ebd8c41be59922 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Thu, 22 Mar 2018 04:34:40 -0400 Subject: Change 253 by jain156@akshayj-lt1 on 2017/05/30 00:40:03 Replaced the mem div stats with mem div histogram --- src/gpgpu-sim/shader.cc | 8 ++++---- src/gpgpu-sim/shader.h | 9 ++++++--- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 72e0266..e7204c8 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -438,8 +438,9 @@ void shader_core_stats::print( FILE* fout ) const fprintf(fout,"gpgpu_n_mem_texture = %d\n", gpgpu_n_mem_texture); fprintf(fout,"gpgpu_n_mem_const = %d\n", gpgpu_n_mem_const); - fprintf(fout,"gpgpu_n_times_gmem_accesses_by_warps = %lld\n", gpgpu_n_times_gmem_accesses_by_warps); - fprintf(fout,"gpgpu_n_total_gmem_accesses_by_warps = %lld\n", gpgpu_n_total_gmem_accesses_by_warps); + fprintf(fout,"gpgpu_mem_divergence_hist "); + gpgpu_mem_divergence_hist->fprint(fout); + fprintf(fout,"\n"); fprintf(fout, "gpgpu_n_load_insn = %d\n", gpgpu_n_load_insn); fprintf(fout, "gpgpu_n_store_insn = %d\n", gpgpu_n_store_insn); @@ -749,8 +750,7 @@ void shader_core_ctx::func_exec_inst( warp_inst_t &inst ) starting_queue_size = inst.accessq_count(); inst.generate_mem_accesses(); if ( inst.space.get_type() == global_space ) { - m_stats->gpgpu_n_times_gmem_accesses_by_warps++; - m_stats->gpgpu_n_total_gmem_accesses_by_warps += inst.accessq_count() - starting_queue_size; + m_stats->gpgpu_mem_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); } } diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 2475677..45658ac 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -53,6 +53,8 @@ #include "stats.h" #include "gpu-cache.h" #include "traffic_breakdown.h" +#include "histogram.h" + @@ -1471,9 +1473,8 @@ struct shader_core_stats_pod { int gpgpu_n_mem_write_global; int gpgpu_n_mem_read_inst; - //warps memory divergence count - unsigned long long gpgpu_n_times_gmem_accesses_by_warps; - unsigned long long gpgpu_n_total_gmem_accesses_by_warps; + //warps combined memory divergence histogram + linear_histogram* gpgpu_mem_divergence_hist; int gpgpu_n_mem_l2_writeback; int gpgpu_n_mem_l1_write_allocate; @@ -1543,6 +1544,7 @@ public: m_incoming_traffic_stats = new traffic_breakdown("memtocore"); gpgpu_n_shmem_bank_access = (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); + gpgpu_mem_divergence_hist = new linear_histogram(1, "", config->warp_size+1); m_shader_dynamic_warp_issue_distro.resize( config->num_shader() ); m_shader_warp_slot_issue_distro.resize( config->num_shader() ); @@ -1557,6 +1559,7 @@ public: free(m_n_diverge); free(shader_cycle_distro); free(last_shader_cycle_distro); + free(gpgpu_mem_divergence_hist); } void new_grid() -- cgit v1.3 From 0241bdee08d2bdf95b7f6f9518403c22f8f0bc53 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Thu, 22 Mar 2018 04:37:36 -0400 Subject: Change 257 by jain156@akshayj-lt1 on 2017/06/03 16:32:52 Adding gpuwattch power stats to the output. Enabled inst and mem breakdown stats in config file. --- configs/GTX480/gpgpusim.config | 2 +- src/gpgpu-sim/gpu-sim.cc | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config index 03fcda1..bff5d16 100644 --- a/configs/GTX480/gpgpusim.config +++ b/configs/GTX480/gpgpusim.config @@ -1,5 +1,5 @@ # functional simulator specification --gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_instruction_classification 1 -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 20 diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 9a28b55..fb57a1e 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1024,6 +1024,7 @@ void gpgpu_sim::gpu_print_stat() shader_print_scheduler_stat( stdout, false ); m_shader_stats->print(stdout); + m_power_stats->print(stdout); #ifdef GPGPUSIM_POWER_MODEL if(m_config.g_power_simulation_enabled){ m_gpgpusim_wrapper->print_power_kernel_stats(gpu_sim_cycle, gpu_tot_sim_cycle, gpu_tot_sim_insn + gpu_sim_insn, kernel_info_str, true ); -- cgit v1.3 From 525f177a1d4f1fc309d22197bc8af26ee8d4c454 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Thu, 22 Mar 2018 04:40:44 -0400 Subject: Change 283 by jain156@akshayj-lt1 on 2017/07/03 19:52:55 Adding the global load and store divergence statistics. The previous histogram has been modified to look at all memory requests, but that is not meaningful - so it can as well be removed. --- src/gpgpu-sim/shader.cc | 15 +++++++++++++-- src/gpgpu-sim/shader.h | 8 +++++++- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index e7204c8..db6a532 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -441,6 +441,12 @@ void shader_core_stats::print( FILE* fout ) const fprintf(fout,"gpgpu_mem_divergence_hist "); gpgpu_mem_divergence_hist->fprint(fout); fprintf(fout,"\n"); + fprintf(fout,"gpgpu_gmem_ld_divergence_hist "); + gpgpu_gmem_ld_divergence_hist->fprint(fout); + fprintf(fout,"\n"); + fprintf(fout,"gpgpu_gmem_st_divergence_hist "); + gpgpu_gmem_st_divergence_hist->fprint(fout); + fprintf(fout,"\n"); fprintf(fout, "gpgpu_n_load_insn = %d\n", gpgpu_n_load_insn); fprintf(fout, "gpgpu_n_store_insn = %d\n", gpgpu_n_store_insn); @@ -746,12 +752,17 @@ void shader_core_ctx::func_exec_inst( warp_inst_t &inst ) { unsigned starting_queue_size; execute_warp_inst_t(inst); - if( inst.is_load() || inst.is_store() ) + if( inst.is_load() || inst.is_store() ) { starting_queue_size = inst.accessq_count(); inst.generate_mem_accesses(); if ( inst.space.get_type() == global_space ) { - m_stats->gpgpu_mem_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); + if (inst.is_load()) + m_stats->gpgpu_gmem_ld_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); + else if (inst.is_store()) + m_stats->gpgpu_gmem_st_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); } + m_stats->gpgpu_mem_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); + } } void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* next_inst, const active_mask_t &active_mask, unsigned warp_id ) diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 45658ac..da7eb32 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1475,7 +1475,9 @@ struct shader_core_stats_pod { //warps combined memory divergence histogram linear_histogram* gpgpu_mem_divergence_hist; - + linear_histogram* gpgpu_gmem_ld_divergence_hist; + linear_histogram* gpgpu_gmem_st_divergence_hist; + int gpgpu_n_mem_l2_writeback; int gpgpu_n_mem_l1_write_allocate; int gpgpu_n_mem_l2_write_allocate; @@ -1545,6 +1547,8 @@ public: gpgpu_n_shmem_bank_access = (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); gpgpu_mem_divergence_hist = new linear_histogram(1, "", config->warp_size+1); + gpgpu_gmem_ld_divergence_hist = new linear_histogram(1, "", config->warp_size+1); + gpgpu_gmem_st_divergence_hist = new linear_histogram(1, "", config->warp_size+1); m_shader_dynamic_warp_issue_distro.resize( config->num_shader() ); m_shader_warp_slot_issue_distro.resize( config->num_shader() ); @@ -1560,6 +1564,8 @@ public: free(shader_cycle_distro); free(last_shader_cycle_distro); free(gpgpu_mem_divergence_hist); + free(gpgpu_gmem_ld_divergence_hist); + free(gpgpu_gmem_st_divergence_hist); } void new_grid() -- cgit v1.3 From b43b94569734d9f27b2e4bbb22272aa4243fbd56 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Thu, 22 Mar 2018 04:45:59 -0400 Subject: Change 332 by jain156@akshayj-lt1 on 2018/02/01 05:20:33 Added shmem_divergence_hist and warp_inst_classification --- src/abstract_hardware_model.h | 7 +++++++ src/cuda-sim/cuda-sim.cc | 4 +++- src/gpgpu-sim/shader.cc | 13 +++++++++++++ src/gpgpu-sim/shader.h | 7 +++++++ 4 files changed, 30 insertions(+), 1 deletion(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index cec75f9..9ba31d9 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -798,6 +798,7 @@ public: arch_reg.dst[i] = -1; } isize=0; + op_classification = 0; } bool valid() const { return m_decoded; } virtual void print_insn( FILE *fp ) const @@ -816,6 +817,7 @@ public: address_type pc; // program counter address of instruction unsigned isize; // size of instruction in bytes op_type op; // opcode (uarch visible) + int op_classification; // classification of opcode for statistics purpopses barrier_type bar_type; reduction_type red_type; @@ -1023,6 +1025,11 @@ public: return cycles > 0; } + unsigned get_cycles() + { + return cycles; + } + void print( FILE *fout ) const; unsigned get_uid() const { return m_uid; } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 17a7798..169c491 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1331,8 +1331,10 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) if ( gpgpu_ptx_instruction_classification ) { init_inst_classification_stat(); - if (op_classification) + if (op_classification) { StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], op_classification); + inst.op_classification = op_classification; + } if (pI->get_space().get_type()) StatAddSample( g_inst_mem_classification_stat[g_ptx_kernel_count], ( int )pI->get_space().get_type()); StatAddSample( g_inst_op_classification_stat[g_ptx_kernel_count], (int) pI->get_opcode() ); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index db6a532..905139c 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -447,6 +447,12 @@ void shader_core_stats::print( FILE* fout ) const fprintf(fout,"gpgpu_gmem_st_divergence_hist "); gpgpu_gmem_st_divergence_hist->fprint(fout); fprintf(fout,"\n"); + fprintf(fout,"gpgpu_shmem_divergence_hist "); + gpgpu_shmem_divergence_hist->fprint(fout); + fprintf(fout,"\n"); + fprintf(fout,"warp_inst_classification "); + warp_inst_classification->fprint(fout); + fprintf(fout,"\n"); fprintf(fout, "gpgpu_n_load_insn = %d\n", gpgpu_n_load_insn); fprintf(fout, "gpgpu_n_store_insn = %d\n", gpgpu_n_store_insn); @@ -752,6 +758,9 @@ void shader_core_ctx::func_exec_inst( warp_inst_t &inst ) { unsigned starting_queue_size; execute_warp_inst_t(inst); + if (inst.op_classification) { + m_stats->warp_inst_classification->add2bin(inst.op_classification); + } if( inst.is_load() || inst.is_store() ) { starting_queue_size = inst.accessq_count(); inst.generate_mem_accesses(); @@ -761,6 +770,10 @@ void shader_core_ctx::func_exec_inst( warp_inst_t &inst ) else if (inst.is_store()) m_stats->gpgpu_gmem_st_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); } + else if ( inst.space.get_type() == shared_space ) { + m_stats->gpgpu_shmem_divergence_hist->add2bin(inst.get_cycles()); + } + m_stats->gpgpu_mem_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); } } diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index da7eb32..9fd1ecb 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1477,6 +1477,9 @@ struct shader_core_stats_pod { linear_histogram* gpgpu_mem_divergence_hist; linear_histogram* gpgpu_gmem_ld_divergence_hist; linear_histogram* gpgpu_gmem_st_divergence_hist; + linear_histogram* gpgpu_shmem_divergence_hist; + + linear_histogram* warp_inst_classification; int gpgpu_n_mem_l2_writeback; int gpgpu_n_mem_l1_write_allocate; @@ -1549,6 +1552,9 @@ public: gpgpu_mem_divergence_hist = new linear_histogram(1, "", config->warp_size+1); gpgpu_gmem_ld_divergence_hist = new linear_histogram(1, "", config->warp_size+1); gpgpu_gmem_st_divergence_hist = new linear_histogram(1, "", config->warp_size+1); + gpgpu_shmem_divergence_hist = new linear_histogram(1, "", config->warp_size+1); + + warp_inst_classification = new linear_histogram(1, "", 12); m_shader_dynamic_warp_issue_distro.resize( config->num_shader() ); m_shader_warp_slot_issue_distro.resize( config->num_shader() ); @@ -1566,6 +1572,7 @@ public: free(gpgpu_mem_divergence_hist); free(gpgpu_gmem_ld_divergence_hist); free(gpgpu_gmem_st_divergence_hist); + free(warp_inst_classification); } void new_grid() -- cgit v1.3 From e97f396d5892d1c7549b18e95787fb635dff4851 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Thu, 22 Mar 2018 16:47:39 -0400 Subject: Adding support for CUDA 9.1 --- Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile b/Makefile index e83de9a..de6264c 100644 --- a/Makefile +++ b/Makefile @@ -161,6 +161,8 @@ $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib if [ ! -f $(SIM_LIB_DIR)/libcudart.so.6.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.6.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.7.5 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.7.5; fi if [ ! -f $(SIM_LIB_DIR)/libcudart.so.8.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.8.0; fi + if [ ! -f $(SIM_LIB_DIR)/libcudart.so.9.0 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.9.0; fi + if [ ! -f $(SIM_LIB_DIR)/libcudart.so.9.1 ]; then ln -s libcudart.so $(SIM_LIB_DIR)/libcudart.so.9.1; fi $(SIM_LIB_DIR)/libcudart.dylib: makedirs $(LIBS) cudalib g++ -dynamiclib -Wl,-headerpad_max_install_names,-undefined,dynamic_lookup,-compatibility_version,1.1,-current_version,1.1\ -- cgit v1.3 From 6dfb3ba656b09acafdb274d7ab04fb081ca06e57 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 8 Nov 2017 20:13:28 -0500 Subject: Fixing the break limit bug --- src/gpgpusim_entrypoint.cc | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index 04845e7..ad4587a 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -91,6 +91,7 @@ void *gpgpu_sim_thread_sequential(void*) pthread_mutex_t g_sim_lock = PTHREAD_MUTEX_INITIALIZER; bool g_sim_active = false; bool g_sim_done = true; +bool break_limit = false; void *gpgpu_sim_thread_concurrent(void*) { @@ -144,11 +145,13 @@ void *gpgpu_sim_thread_concurrent(void*) if(g_the_gpu->cycle_insn_cta_max_hit()){ g_stream_manager->stop_all_running_kernels(); g_sim_done = true; + break_limit = true; } } active=g_the_gpu->active() || !g_stream_manager->empty_protected(); - } while( active ); + + } while( active && !g_sim_done); if(g_debug_execution >= 3) { printf("GPGPU-Sim: ** STOP simulation thread (no work) **\n"); fflush(stdout); @@ -166,6 +169,11 @@ void *gpgpu_sim_thread_concurrent(void*) printf("GPGPU-Sim: *** simulation thread exiting ***\n"); fflush(stdout); } + if(break_limit) { + printf("GPGPU-Sim: ** break due to reaching the maximum cycles (or instructions) **\n"); + exit(1); + } + sem_post(&g_sim_signal_exit); return NULL; } @@ -179,7 +187,7 @@ void synchronize() bool done = false; do { pthread_mutex_lock(&g_sim_lock); - done = g_stream_manager->empty() && !g_sim_active; + done = ( g_stream_manager->empty() && !g_sim_active ) || g_sim_done; pthread_mutex_unlock(&g_sim_lock); } while (!done); printf("GPGPU-Sim: detected inactive GPU simulation thread\n"); -- cgit v1.3 From 742c4dc4c2c85329754043d38c60b2a37fefdaa1 Mon Sep 17 00:00:00 2001 From: Amruth Date: Fri, 23 Mar 2018 19:13:00 -0700 Subject: dynamic pdom analysis at runtime --- libcuda/cuda_runtime_api.cc | 19 +++++++++++++++---- src/cuda-sim/cuda-sim.cc | 12 ++++++++++++ src/cuda-sim/ptx_ir.cc | 26 ++++++++++++++++++++++++++ src/cuda-sim/ptx_ir.h | 5 ++++- 4 files changed, 57 insertions(+), 5 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index e7952e2..948d81d 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1013,7 +1013,16 @@ __host__ cudaError_t CUDARTAPI cudaLaunch( const char *hostFun ) printf("\nGPGPU-Sim PTX: cudaLaunch for 0x%p (mode=%s) on stream %u\n", hostFun, g_ptx_sim_mode?"functional simulation":"performance simulation", stream?stream->get_uid():0 ); kernel_info_t *grid = gpgpu_cuda_ptx_sim_init_grid(hostFun,config.get_args(),config.grid_dim(),config.block_dim(),context); + //do dynamic PDOM analysis for performance simulation scenario std::string kname = grid->name(); + function_info *kernel_func_info = grid->entry(); + if (kernel_func_info->is_pdom_set()) { + printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", kname.c_str() ); + } else { + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", kname.c_str() ); + kernel_func_info->do_pdom(); + kernel_func_info->set_pdom(); + } dim3 gridDim = config.grid_dim(); dim3 blockDim = config.block_dim(); printf("GPGPU-Sim PTX: pushing kernel \'%s\' to stream %u, gridDim= (%u,%u,%u) blockDim = (%u,%u,%u) \n", @@ -1400,7 +1409,7 @@ void extract_code_using_cuobjdump(){ const char *override_cuobjdump = getenv("CUOBJDUMP_SIM_FILE"); char fname[1024]; - if (override_cuobjdump == NULL) { + if ((override_cuobjdump == NULL) || (strlen(override_cuobjdump)==0)) { char command[1000]; std::string app_binary = get_app_binary(); @@ -1733,7 +1742,8 @@ cuobjdumpPTXSection* findPTXSection(const std::string identifier){ void cuobjdumpInit(){ CUctx_st *context = GPGPUSim_Context(); extract_code_using_cuobjdump(); //extract all the output of cuobjdump to _cuobjdump_*.* - if (getenv("CUOBJDUMP_SIM_FILE")==NULL){ + const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); + if (pre_load ==NULL || strlen(pre_load)==0){ cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); cuobjdumpSectionList = mergeSections(cuobjdumpSectionList); } @@ -1772,12 +1782,13 @@ void cuobjdumpParseBinary(unsigned int handle){ if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); cuobjdumpPTXSection* ptx = NULL; - if(getenv("CUOBJDUMP_SIM_FILE")==NULL) + const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); + if(pre_load==NULL || strlen(pre_load)==0) ptx = findPTXSection(fname); symbol_table *symtab; char *ptxcode; const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); - if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL) { + if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL or strlen(getenv("PTX_SIM_USE_PTX_FILE"))==0) { ptxcode = readfile(ptx->getPTXfilename()); } else { printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index f51f57d..39a04dd 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -257,6 +257,8 @@ void function_info::ptx_assemble() fflush(stdout); printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", m_name.c_str() ); + //disable pdom analysis here and do it at runtime +#if 0 create_basic_blocks(); connect_basic_blocks(); bool modified = false; @@ -280,6 +282,7 @@ void function_info::ptx_assemble() print_postdominators(); print_ipostdominators(); } +#endif printf("GPGPU-Sim PTX: pre-decoding instructions for \'%s\'...\n", m_name.c_str() ); for ( unsigned ii=0; ii < n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions @@ -1801,6 +1804,15 @@ void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL ) //using a shader core object for book keeping, it is not needed but as most function built for performance simulation need it we use it here extern gpgpu_sim *g_the_gpu; + //before we execute, we should do PDOM analysis for functional simulation scenario. + function_info *kernel_func_info = kernel.entry(); + if (kernel_func_info->is_pdom_set()) { + printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", kernel.name().c_str() ); + } else { + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", kernel.name().c_str() ); + kernel_func_info->do_pdom(); + kernel_func_info->set_pdom(); + } //we excute the kernel one CTA (Block) at the time, as synchronization functions work block wise while(!kernel.no_more_ctas_to_run()){ diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 8ebdcf8..6a17eaf 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -575,6 +575,31 @@ bool function_info::connect_break_targets() //connecting break instructions with return modified; } +void function_info::do_pdom() { + create_basic_blocks(); + connect_basic_blocks(); + bool modified = false; + do { + find_dominators(); + find_idominators(); + modified = connect_break_targets(); + } while (modified == true); + + if ( g_debug_execution>=50 ) { + print_basic_blocks(); + print_basic_block_links(); + print_basic_block_dot(); + } + if ( g_debug_execution>=2 ) { + print_dominators(); + } + find_postdominators(); + find_ipostdominators(); + if ( g_debug_execution>=50 ) { + print_postdominators(); + print_ipostdominators(); + } +} void intersect( std::set &A, const std::set &B ) { // return intersection of A and B in A @@ -1305,6 +1330,7 @@ function_info::function_info(int entry_point ) m_kernel_info.smem = 0; m_local_mem_framesize = 0; m_args_aligned_size = -1; + pdom_done = false; //initialize it to false } unsigned function_info::print_insn( unsigned pc, FILE * fp ) const diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 9ad1571..26a2839 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1178,7 +1178,7 @@ public: //Muchnick's Adv. Compiler Design & Implemmntation Fig 7.15 void find_ipostdominators( ); void print_ipostdominators(); - + void do_pdom(); //function to call pdom analysis unsigned get_num_reconvergence_pairs(); @@ -1274,6 +1274,8 @@ public: m_local_mem_framesize = sz; } bool is_entry_point() const { return m_entry_point; } + bool is_pdom_set() const { return pdom_done; } //return pdom flag + void set_pdom() { pdom_done = true; } //set pdom flag private: unsigned m_uid; @@ -1281,6 +1283,7 @@ private: bool m_entry_point; bool m_extern; bool m_assembled; + bool pdom_done; //flag to check whether pdom is completed or not std::string m_name; ptx_instruction **m_instr_mem; unsigned m_start_PC; -- cgit v1.3 From a368a6ef96620763848f38d924a7fe041bc5728b Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 24 Mar 2018 18:08:37 -0400 Subject: The new CUDAs complain about version info not being embedded into the so file. Having gpgpu-sim ebed some version info to stop the error complaints --- Makefile | 2 +- linux-so-version.txt | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) create mode 100644 linux-so-version.txt diff --git a/Makefile b/Makefile index 95e4432..1641833 100644 --- a/Makefile +++ b/Makefile @@ -143,7 +143,7 @@ no_opencl_support: @echo "Warning: gpgpu-sim is building without opencl support. Make sure NVOPENCL_LIBDIR and NVOPENCL_INCDIR are set" $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib - g++ -shared -Wl,-soname,libcudart_$(GPGPUSIM_BUILD).so \ + g++ -shared -Wl,-soname,libcudart_$(GPGPUSIM_BUILD).so -Wl,--version-script=linux-so-version.txt\ $(SIM_OBJ_FILES_DIR)/libcuda/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/decuda_pred_table/*.o \ diff --git a/linux-so-version.txt b/linux-so-version.txt new file mode 100644 index 0000000..40f775d --- /dev/null +++ b/linux-so-version.txt @@ -0,0 +1,2 @@ +libcudart.so.9.1{ +}; -- cgit v1.3 From d97022fa5fee348e15f2b07ab83ee7aba4f008e0 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 24 Mar 2018 18:08:37 -0400 Subject: The new CUDAs complain about version info not being embedded into the so file. Having gpgpu-sim ebed some version info to stop the error complaints --- Makefile | 2 +- linux-so-version.txt | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) create mode 100644 linux-so-version.txt diff --git a/Makefile b/Makefile index de6264c..2d0466e 100644 --- a/Makefile +++ b/Makefile @@ -143,7 +143,7 @@ no_opencl_support: @echo "Warning: gpgpu-sim is building without opencl support. Make sure NVOPENCL_LIBDIR and NVOPENCL_INCDIR are set" $(SIM_LIB_DIR)/libcudart.so: makedirs $(LIBS) cudalib - g++ -shared -Wl,-soname,libcudart_$(GPGPUSIM_BUILD).so \ + g++ -shared -Wl,-soname,libcudart_$(GPGPUSIM_BUILD).so -Wl,--version-script=linux-so-version.txt\ $(SIM_OBJ_FILES_DIR)/libcuda/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/*.o \ $(SIM_OBJ_FILES_DIR)/cuda-sim/decuda_pred_table/*.o \ diff --git a/linux-so-version.txt b/linux-so-version.txt new file mode 100644 index 0000000..40f775d --- /dev/null +++ b/linux-so-version.txt @@ -0,0 +1,2 @@ +libcudart.so.9.1{ +}; -- cgit v1.3 From 78fd9e7f9d9934036b2f43392258b559886f3314 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 24 Mar 2018 20:21:13 -0400 Subject: Adding in a patch to get lonestargpu to work --- libcuda/cuda_runtime_api.cc | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index cbe8a11..d8e7832 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -336,10 +336,23 @@ class _cuda_device_id *GPGPUSim_Init() prop->minor = 2; prop->totalGlobalMem = 0x80000000 /* 2 GB */; prop->memPitch = 0; - prop->maxThreadsPerBlock = 512; - prop->maxThreadsDim[0] = 512; - prop->maxThreadsDim[1] = 512; - prop->maxThreadsDim[2] = 512; + + if(prop->major >= 2) { + prop->maxThreadsPerBlock = 1024; + prop->maxThreadsDim[0] = 1024; + prop->maxThreadsDim[1] = 1024; + } + else + { + prop->maxThreadsPerBlock = 512; + prop->maxThreadsDim[0] = 512; + prop->maxThreadsDim[1] = 512; + } + + prop->maxThreadsDim[2] = 64; + prop->maxGridSize[0] = 0x40000000; + prop->maxGridSize[1] = 0x40000000; + prop->maxGridSize[2] = 0x40000000; prop->maxGridSize[0] = 0x40000000; prop->maxGridSize[1] = 0x40000000; prop->maxGridSize[2] = 0x40000000; @@ -351,6 +364,9 @@ class _cuda_device_id *GPGPUSim_Init() prop->clockRate = the_gpu->shader_clock(); #if (CUDART_VERSION >= 2010) prop->multiProcessorCount = the_gpu->get_config().num_shader(); +#endif +#if (CUDART_VERSION >= 4000) + prop->maxThreadsPerMultiProcessor = the_gpu->threads_per_core(); #endif the_gpu->set_prop(prop); the_device = new _cuda_device_id(the_gpu); -- cgit v1.3 From b4cf66026f66291293c6e11e9c07976f773732fa Mon Sep 17 00:00:00 2001 From: Mengchi Zhang Date: Tue, 3 Oct 2017 11:36:52 -0400 Subject: Add lonestar tick support Signed-off-by: Mengchi Zhang --- cuobjdump_to_ptxplus/ptx_parser.h | 4 ++++ libcuda/cuda_runtime_api.cc | 49 +++++++++++++++++++++++++-------------- src/abstract_hardware_model.h | 10 +++++++- src/cuda-sim/cuda-sim.cc | 5 ++-- src/cuda-sim/ptx.y | 3 ++- src/cuda-sim/ptx_ir.cc | 1 + src/cuda-sim/ptx_ir.h | 7 ++++++ src/cuda-sim/ptx_parser.cc | 4 ++++ src/cuda-sim/ptx_parser.h | 1 + 9 files changed, 62 insertions(+), 22 deletions(-) diff --git a/cuobjdump_to_ptxplus/ptx_parser.h b/cuobjdump_to_ptxplus/ptx_parser.h index 418a733..729eaec 100644 --- a/cuobjdump_to_ptxplus/ptx_parser.h +++ b/cuobjdump_to_ptxplus/ptx_parser.h @@ -373,4 +373,8 @@ void func_header_info_int(const char* s, int i) g_headerList->getListEnd().addOperand(buff); } } + +void maxnt_id(int x, int y, int z) { + +} #endif //_PTX_PARSER_H_ diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index d8e7832..4f5e0fb 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -336,23 +336,19 @@ class _cuda_device_id *GPGPUSim_Init() prop->minor = 2; prop->totalGlobalMem = 0x80000000 /* 2 GB */; prop->memPitch = 0; + if(prop->major >= 2) { + prop->maxThreadsPerBlock = 1024; + prop->maxThreadsDim[0] = 1024; + prop->maxThreadsDim[1] = 1024; + } + else + { + prop->maxThreadsPerBlock = 512; + prop->maxThreadsDim[0] = 512; + prop->maxThreadsDim[1] = 512; + } - if(prop->major >= 2) { - prop->maxThreadsPerBlock = 1024; - prop->maxThreadsDim[0] = 1024; - prop->maxThreadsDim[1] = 1024; - } - else - { - prop->maxThreadsPerBlock = 512; - prop->maxThreadsDim[0] = 512; - prop->maxThreadsDim[1] = 512; - } - - prop->maxThreadsDim[2] = 64; - prop->maxGridSize[0] = 0x40000000; - prop->maxGridSize[1] = 0x40000000; - prop->maxGridSize[2] = 0x40000000; + prop->maxThreadsDim[2] = 64; prop->maxGridSize[0] = 0x40000000; prop->maxGridSize[1] = 0x40000000; prop->maxGridSize[2] = 0x40000000; @@ -366,7 +362,7 @@ class _cuda_device_id *GPGPUSim_Init() prop->multiProcessorCount = the_gpu->get_config().num_shader(); #endif #if (CUDART_VERSION >= 4000) - prop->maxThreadsPerMultiProcessor = the_gpu->threads_per_core(); + prop->maxThreadsPerMultiProcessor = the_gpu->threads_per_core(); #endif the_gpu->set_prop(prop); the_device = new _cuda_device_id(the_gpu); @@ -2112,6 +2108,20 @@ cudaError_t CUDARTAPI cudaSetDeviceFlags( int flags ) return g_last_cudaError = cudaErrorUnknown; } +size_t getMaxThreadsPerBlock(struct cudaFuncAttributes *attr) { + _cuda_device_id *dev = GPGPUSim_Init(); + struct cudaDeviceProp prop; + + prop = *dev->get_prop(); + + size_t max = prop.maxThreadsPerBlock; + + if ((prop.regsPerBlock / attr->numRegs) < max) + max = prop.regsPerBlock / attr->numRegs; + + return max; +} + cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, const char *hostFun ) { CUctx_st *context = GPGPUSim_Context(); @@ -2122,7 +2132,10 @@ cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, con attr->constSizeBytes = kinfo->cmem; attr->localSizeBytes = kinfo->lmem; attr->numRegs = kinfo->regs; - attr->maxThreadsPerBlock = 0; // from pragmas? + if(kinfo->maxthreads > 0) + attr->maxThreadsPerBlock = kinfo->maxthreads; + else + attr->maxThreadsPerBlock = getMaxThreadsPerBlock(attr); #if CUDART_VERSION >= 3000 attr->ptxVersion = kinfo->ptx_version; attr->binaryVersion = kinfo->sm_target; diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index cec75f9..1b764e2 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -517,7 +517,14 @@ public: const struct textureReference* get_texref(const std::string &texname) const { std::map::const_iterator t=m_NameToTextureRef.find(texname); - assert( t != m_NameToTextureRef.end() ); + if( t == m_NameToTextureRef.end() ) { + // search for :: prefixed names + std::string temp("::" + texname); + t=m_NameToTextureRef.find(temp); + } + + assert(t != m_NameToTextureRef.end()); + return t->second; } const struct cudaArray* get_texarray( const struct textureReference *texref ) const @@ -568,6 +575,7 @@ struct gpgpu_ptx_sim_info int cmem; int gmem; int regs; + unsigned maxthreads; unsigned ptx_version; unsigned sm_target; }; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 2f166aa..f143d35 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1159,13 +1159,14 @@ void function_info::finalize( memory_space *param_mem ) // copy the parameter over word-by-word so that parameter that crosses a memory page can be copied over //Jin: copy parameter using aligned rules const size_t word_size = 4; - param_address = (param_address + size - 1) / size * size; //aligned with size + //param_address = (param_address + size - 1) / size * size; //aligned with size TODO: align not correct for (size_t idx = 0; idx < size; idx += word_size) { const char *pdata = reinterpret_cast(param_value.pdata) + idx; // cast to char * for ptr arithmetic param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); + param_mem->read(param_address + idx, word_size, &data); } unsigned offset = p.get_offset(); - assert(offset == param_address); + //assert(offset == param_address); param->set_address(param_address); param_address += size; } diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index e00aa4b..c0c58a6 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -228,7 +228,8 @@ function_defn: function_decl { set_symtab($1); func_header(".skip"); } statement block_spec: MAXNTID_DIRECTIVE INT_OPERAND COMMA INT_OPERAND COMMA INT_OPERAND {func_header_info_int(".maxntid", $2); func_header_info_int(",", $4); - func_header_info_int(",", $6); } + func_header_info_int(",", $6); + maxnt_id($2, $4, $6);} | MINNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".minnctapersm", $2); printf("GPGPU-Sim: Warning: .minnctapersm ignored. \n"); } | MAXNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".maxnctapersm", $2); printf("GPGPU-Sim: Warning: .maxnctapersm ignored. \n"); } ; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 8ebdcf8..ee36957 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -222,6 +222,7 @@ bool symbol_table::add_function_decl( const char *name, int entry_point, functio } else { *func_info = new function_info(entry_point); (*func_info)->set_name(name); + (*func_info)->set_maxnt_id(0); m_function_info_lookup[key] = *func_info; } diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 9ad1571..36ef3d5 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1245,6 +1245,7 @@ public: const struct gpgpu_ptx_sim_info* get_kernel_info () const { + assert (m_kernel_info.maxthreads == maxnt_id); return &m_kernel_info; } @@ -1252,6 +1253,8 @@ public: m_kernel_info = info; m_kernel_info.ptx_version = 10*get_ptx_version().ver(); m_kernel_info.sm_target = get_ptx_version().target(); + // THIS DEPENDS ON ptxas being called after the PTX is parsed. + m_kernel_info.maxthreads = maxnt_id; } symbol_table *get_symtab() { @@ -1275,7 +1278,11 @@ public: } bool is_entry_point() const { return m_entry_point; } + void set_maxnt_id(unsigned maxthreads) { maxnt_id = maxthreads;} + unsigned get_maxnt_id() { return maxnt_id;} + private: + unsigned maxnt_id; unsigned m_uid; unsigned m_local_mem_framesize; bool m_entry_point; diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index baa3bcd..e5731a8 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -969,6 +969,10 @@ void target_header3(char* a, char* b, char* c) g_global_symbol_table->set_sm_target(a,b,c); } +void maxnt_id(int x, int y, int z) { + g_func_info->set_maxnt_id(x * y * z); +} + void func_header(const char* a) {} //intentional dummy function void func_header_info(const char* a) {} //intentional dummy function void func_header_info_int(const char* a, int b) {} //intentional dummy function diff --git a/src/cuda-sim/ptx_parser.h b/src/cuda-sim/ptx_parser.h index 32f3903..13042e1 100644 --- a/src/cuda-sim/ptx_parser.h +++ b/src/cuda-sim/ptx_parser.h @@ -93,6 +93,7 @@ void change_double_operand_type( int addr_type ); void change_operand_neg( ); void set_immediate_operand_type( ); void version_header(double a); +void maxnt_id(int x, int y, int z); //Jin: handle instructino group for cdp void start_inst_group(); -- cgit v1.3 From 78a971019b7eac438521c9a77fdf9de30340f29e Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 25 Mar 2018 15:26:38 -0400 Subject: Fixing a bug in mengchi's commit --- src/cuda-sim/cuda-sim.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index f143d35..3d3a820 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1163,7 +1163,6 @@ void function_info::finalize( memory_space *param_mem ) for (size_t idx = 0; idx < size; idx += word_size) { const char *pdata = reinterpret_cast(param_value.pdata) + idx; // cast to char * for ptr arithmetic param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); - param_mem->read(param_address + idx, word_size, &data); } unsigned offset = p.get_offset(); //assert(offset == param_address); -- cgit v1.3 From db4bd85339caee6a6bd470da1c5f24bc4e8cbe45 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 25 Mar 2018 15:50:13 -0400 Subject: succeed if just remining the GPU that pinned memory can beused --- libcuda/cuda_runtime_api.cc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 4f5e0fb..7ee7dbe 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -2104,8 +2104,14 @@ cudaError_t CUDARTAPI cudaSetValidDevices(int *device_arr, int len) cudaError_t CUDARTAPI cudaSetDeviceFlags( int flags ) { - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; + // This flag is implicitly always on (unless you are using the driver API). It is safe for GPGPU-Sim to + // just ignore it. + if ( cudaDeviceMapHost == flags ) { + return g_last_cudaError = cudaSuccess; + } else { + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; + } } size_t getMaxThreadsPerBlock(struct cudaFuncAttributes *attr) { -- cgit v1.3 From bd2700c7a1b5be3e71ee2f0e9abab76719f2f462 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 25 Mar 2018 16:41:51 -0400 Subject: Need to explicity set this or the stupid GPGPU-Sim defaults of 16k kicks in. --- configs/Pascal-P100-HBM/gpgpusim.config | 2 ++ configs/Pascal-P102-GDDR5X/gpgpusim.config | 2 ++ configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config | 2 ++ configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 2 ++ 4 files changed, 8 insertions(+) diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config index 0c4744a..31fbecb 100644 --- a/configs/Pascal-P100-HBM/gpgpusim.config +++ b/configs/Pascal-P100-HBM/gpgpusim.config @@ -56,6 +56,8 @@ # Pascal GP100 has 64KB Shared memory -gpgpu_cache:dl1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 -gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 65536 +-gpgpu_shmem_size_PrefShared 65536 -gmem_skip_L1D 0 -icnt_flit_size 40 -gpgpu_n_cluster_ejection_buffer_size 32 diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index 0c6c126..8e1e56f 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -63,6 +63,8 @@ # The defulat is to disable the L1 cache, unless cache modifieres is used -gpgpu_cache:dl1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 -gpgpu_shmem_size 49152 +-gpgpu_shmem_size_PrefL1 49152 +-gpgpu_shmem_size_PrefShared 49152 -gmem_skip_L1D 1 -icnt_flit_size 40 -gpgpu_n_cluster_ejection_buffer_size 32 diff --git a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config index 8afdd7f..b87d958 100644 --- a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config @@ -56,6 +56,8 @@ # Pascal GP100 has 48KB L1 cache -gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 65536 +-gpgpu_shmem_size_PrefShared 65536 -gmem_skip_L1D 0 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 28689ce..2df24e1 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -57,6 +57,8 @@ # The defulat is to disable the L1 cache, unless cache modifieres is used -gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 98304 +-gpgpu_shmem_size_PrefL1 98304 +-gpgpu_shmem_size_PrefShared 98304 -gmem_skip_L1D 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache -- cgit v1.3 From 4e91a60a48b07f41f4bfb4d59fa2355024a3914b Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 25 Mar 2018 16:51:21 -0400 Subject: Need to make sure we don't kill the L1 too --- configs/Pascal-P100-HBM/gpgpusim.config | 2 ++ configs/Pascal-P102-GDDR5X/gpgpusim.config | 2 ++ configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config | 2 ++ configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 2 ++ src/gpgpu-sim/gpu-sim.cc | 2 +- 5 files changed, 9 insertions(+), 1 deletion(-) diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config index 31fbecb..857a0ff 100644 --- a/configs/Pascal-P100-HBM/gpgpusim.config +++ b/configs/Pascal-P100-HBM/gpgpusim.config @@ -55,6 +55,8 @@ # Note: Hashing set index function (H) only applies to a set size of 32 or 64. # Pascal GP100 has 64KB Shared memory -gpgpu_cache:dl1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 -gpgpu_shmem_size 65536 -gpgpu_shmem_size_PrefL1 65536 -gpgpu_shmem_size_PrefShared 65536 diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index 8e1e56f..feb8c0b 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -62,6 +62,8 @@ # Pascal GP102 has 24KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used -gpgpu_cache:dl1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 -gpgpu_shmem_size 49152 -gpgpu_shmem_size_PrefL1 49152 -gpgpu_shmem_size_PrefShared 49152 diff --git a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config index b87d958..a5e6736 100644 --- a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config @@ -55,6 +55,8 @@ # Pascal GP100 has 64KB Shared memory # Pascal GP100 has 48KB L1 cache -gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 65536 -gpgpu_shmem_size_PrefL1 65536 -gpgpu_shmem_size_PrefShared 65536 diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 2df24e1..f78bd02 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -56,6 +56,8 @@ # Pascal GP102 has 64KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used -gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 98304 -gpgpu_shmem_size_PrefL1 98304 -gpgpu_shmem_size_PrefShared 98304 diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 17f1714..bb448b3 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -245,7 +245,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "per-shader L1 data cache config " " {::,:::,::, | none}", "none" ); - option_parser_register(opp, "-gpgpu_cache:dl1PreShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, + option_parser_register(opp, "-gpgpu_cache:dl1PrefShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, "per-shader L1 data cache config " " {::,:::,::, | none}", "none" ); -- cgit v1.3 From 26b9853cc1f6a3b17de0e319b40f28a5703ad6bf Mon Sep 17 00:00:00 2001 From: Amruth Date: Sun, 25 Mar 2018 16:01:22 -0700 Subject: code for removing duplicates in embedded ptx --- libcuda/cuda_runtime_api.cc | 247 ++++++++++++++++++++++++++++---------------- src/cuda-sim/ptx_loader.cc | 155 +++++++++++++++++---------- src/cuda-sim/ptx_loader.h | 1 + 3 files changed, 255 insertions(+), 148 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 948d81d..f74c4eb 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -145,6 +145,8 @@ #include #endif +int no_of_ptx=0; + extern void synchronize(); extern void exit_simulation(); @@ -1394,6 +1396,26 @@ std::string get_app_binary(){ return self_exe_path; } +//above func gives abs path whereas this give just the name of application. +char* get_app_binary_name(std::string abs_path){ + char *self_exe_path; +#ifdef __APPLE__ + //TODO: get apple device and check the result. + printf("WARNING: not tested for Apple-mac devices \n"); + abort(); +#else + char* buf = strdup(abs_path.c_str()); + char *token = strtok(buf, "/"); + while(token !=NULL){ + self_exe_path = token; + token = strtok(NULL,"/"); + } +#endif + self_exe_path = strtok(self_exe_path, "."); + printf("self exe links to: %s\n", self_exe_path); + return self_exe_path; +} + //! Call cuobjdump to extract everything (-elf -sass -ptx) /*! * This Function extract the whole PTX (for all the files) using cuobjdump @@ -1402,114 +1424,152 @@ std::string get_app_binary(){ * It is also responsible for extracting the libraries linked to the binary if the option is * enabled * */ - void extract_code_using_cuobjdump(){ CUctx_st *context = GPGPUSim_Context(); + unsigned forced_max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); + //prevent the dumping by cuobjdump everytime we execute the code! const char *override_cuobjdump = getenv("CUOBJDUMP_SIM_FILE"); - + char command[1000], ptx_file[1000]; + std::string app_binary = get_app_binary(); + //Running cuobjdump using dynamic link to current process + snprintf(command,1000,"md5sum %s ", app_binary.c_str()); + printf("Running md5sum using \"%s\"\n", command); + system(command); + // Running cuobjdump using dynamic link to current process + // Needs the option '-all' to extract PTX from CDP-enabled binary + extern bool g_cdp_enabled; + + //dump ptx for all individial ptx files into sepearte files which is later used by ptxas. + char fname2[1024]; + snprintf(fname2,1024,"_cuobjdump_list_ptx_XXXXXX"); + int fd2=mkstemp(fname2); + close(fd2); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -lptx -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname2); + int result = system(command); + if( result != 0 ) { + printf("WARNING: Failed to execute cuobjdump to get list of ptx files \n"); + exit(0); + } else { + /* + as we got list of ptx files, we need to extract one by one into seperate files so that ptxas can understand it. + In this way, the duplicate definitions in a single embedded file can be prevented. + No of lines in the file is equal to no of ptx fileis available. + */ + FILE *fp = fopen(fname2,"r"); + if (fp==NULL) { + printf("WARNING: cuobjdump file error! Could not open file %s \n", fname2); + exit(0); + } else { + for (char c = getc(fp); c != EOF; c = getc(fp)) + if (c == '\n') + no_of_ptx = no_of_ptx + 1; + fclose(fp); + } + } + //based on the list above, dump ptx files individually. Format of dumped ptx file is prog_name.unique_no.sm_<>.ptx + for (int index=1; index<= no_of_ptx; index++){ + snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", get_app_binary_name(app_binary), index, forced_max_capability); + printf("Extracting specific PTX file named %s \n",ptx_file); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -arch=sm_%u -xptx %s %s", forced_max_capability, ptx_file, app_binary.c_str()); + if (system(command)!=0) { + printf("ERROR: command: %s failed \n",command); + exit(0); + } + } + //TODO: redundant to dump twice. how can it be prevented? + //dump only for specific arch char fname[1024]; if ((override_cuobjdump == NULL) || (strlen(override_cuobjdump)==0)) { - char command[1000]; - std::string app_binary = get_app_binary(); - snprintf(fname,1024,"_cuobjdump_complete_output_XXXXXX"); int fd=mkstemp(fname); close(fd); - // Running cuobjdump using dynamic link to current process - snprintf(command,1000,"md5sum %s ", app_binary.c_str()); - printf("Running md5sum using \"%s\"\n", command); - system(command); - // Running cuobjdump using dynamic link to current process - // Needs the option '-all' to extract PTX from CDP-enabled binary - extern bool g_cdp_enabled; - //dump only for specific arch - TODO: will it save memory? if(!g_cdp_enabled) - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_60 %s > %s", app_binary.c_str(), fname); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname); else - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_60 -all %s > %s", app_binary.c_str(), fname); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_%u -all %s > %s", forced_max_capability, app_binary.c_str(), fname); bool parse_output = true; - int result = system(command); + result = system(command); if(result) { - if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support() && (result == 65280)) { - // Some CUDA application may exclusively use kernels provided by CUDA - // libraries (e.g. CUBLAS). Skipping cuobjdump extraction from the - // executable for this case. - // 65280 is the return code from cuobjdump denoting the specific error (tested on CUDA 4.0/4.1/4.2) - printf("WARNING: Failed to execute: %s\n", command); - printf(" Executable binary does not contain any GPU kernel.\n"); - parse_output = false; - } else { - printf("ERROR: Failed to execute: %s\n", command); - exit(1); - } - } - - if (parse_output) { - printf("Parsing file %s\n", fname); - cuobjdump_in = fopen(fname, "r"); - - cuobjdump_parse(); - fclose(cuobjdump_in); - printf("Done parsing!!!\n"); - } else { - printf("Parsing skipped for %s\n", fname); - } + if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support() && (result == 65280)) { + // Some CUDA application may exclusively use kernels provided by CUDA + // libraries (e.g. CUBLAS). Skipping cuobjdump extraction from the + // executable for this case. + // 65280 is the return code from cuobjdump denoting the specific error (tested on CUDA 4.0/4.1/4.2) + printf("WARNING: Failed to execute: %s\n", command); + printf(" Executable binary does not contain any GPU kernel.\n"); + parse_output = false; + } else { + printf("ERROR: Failed to execute: %s\n", command); + exit(1); + } + } - if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ - //Experimental library support - //Currently only for cufft + if (parse_output) { + printf("Parsing file %s\n", fname); + cuobjdump_in = fopen(fname, "r"); - std::stringstream cmd; - cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; - int result = system(cmd.str().c_str()); - if(result){ - std::cout << "Failed to execute: " << cmd << std::endl; - exit(1); - } - std::ifstream libsf; - libsf.open("_tempfile_.txt"); - if(!libsf.is_open()) { - std::cout << "Failed to open: _tempfile_.txt" << std::endl; - exit(1); - } - - //Save the original section list - std::list tmpsl = cuobjdumpSectionList; - cuobjdumpSectionList.clear(); - - std::string line; - std::getline(libsf, line); - std::cout << "DOING: " << line << std::endl; - int cnt=1; - while(libsf.good()){ - std::stringstream libcodfn; - libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; - cmd.str(""); //resetting - cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; - cmd << line; - cmd << " > "; - cmd << libcodfn.str(); - std::cout << "Running cuobjdump on " << line << std::endl; - std::cout << "Using command: " << cmd.str() << std::endl; - result = system(cmd.str().c_str()); - if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} - std::cout << "Done" << std::endl; - - std::cout << "Trying to parse " << libcodfn << std::endl; - cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); - cuobjdump_parse(); - fclose(cuobjdump_in); - std::getline(libsf, line); - } - libSectionList = cuobjdumpSectionList; + cuobjdump_parse(); + fclose(cuobjdump_in); + printf("Done parsing!!!\n"); + } else { + printf("Parsing skipped for %s\n", fname); + } - //Restore the original section list - cuobjdumpSectionList = tmpsl; - } + if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ + //Experimental library support + //Currently only for cufft + + std::stringstream cmd; + cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; + int result = system(cmd.str().c_str()); + if(result){ + std::cout << "Failed to execute: " << cmd << std::endl; + exit(1); + } + std::ifstream libsf; + libsf.open("_tempfile_.txt"); + if(!libsf.is_open()) { + std::cout << "Failed to open: _tempfile_.txt" << std::endl; + exit(1); + } + + //Save the original section list + std::list tmpsl = cuobjdumpSectionList; + cuobjdumpSectionList.clear(); + + std::string line; + std::getline(libsf, line); + std::cout << "DOING: " << line << std::endl; + int cnt=1; + while(libsf.good()){ + std::stringstream libcodfn; + libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; + cmd.str(""); //resetting + cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; + cmd << line; + cmd << " > "; + cmd << libcodfn.str(); + std::cout << "Running cuobjdump on " << line << std::endl; + std::cout << "Using command: " << cmd.str() << std::endl; + result = system(cmd.str().c_str()); + if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} + std::cout << "Done" << std::endl; + + std::cout << "Trying to parse " << libcodfn << std::endl; + cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); + cuobjdump_parse(); + fclose(cuobjdump_in); + std::getline(libsf, line); + } + libSectionList = cuobjdumpSectionList; + + //Restore the original section list + cuobjdumpSectionList = tmpsl; + } } else { - printf("GPGPU-Sim PTX: overriding cuobjdump with '%s' (CUOBJDUMP_SIM_FILE is set)\n", override_cuobjdump); - snprintf(fname,1024,override_cuobjdump); + printf("GPGPU-Sim PTX: overriding cuobjdump with '%s' (CUOBJDUMP_SIM_FILE is set)\n", override_cuobjdump); + snprintf(fname,1024, "%s",override_cuobjdump); } } @@ -1772,6 +1832,8 @@ void cuobjdumpParseBinary(unsigned int handle){ return; } + //Why to search for capability value if we can directly find it in device info? + #if 0 unsigned max_capability = 0; for ( std::list::iterator iter = cuobjdumpSectionList.begin(); iter != cuobjdumpSectionList.end(); @@ -1780,6 +1842,8 @@ void cuobjdumpParseBinary(unsigned int handle){ if (capability > max_capability) max_capability = capability; } if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); + #endif + unsigned max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); @@ -1926,6 +1990,7 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) return (void**)fat_cubin_handle; } #endif + return 0; } void __cudaUnregisterFatBinary(void **fatCubinHandle) diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 6c1b595..d98ca07 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -32,6 +32,7 @@ #include #include #include +#include /// globals @@ -287,56 +288,87 @@ void fix_duplicate_errors(char fname2[1024]) { } } +//we need the application name here too. +char* get_app_binary_name(){ + char exe_path[1025]; + char *self_exe_path; +#ifdef __APPLE__ + //AMRUTH: get apple device and check the result. + printf("WARNING: not tested for Apple-mac devices \n"); + abort(); +#else + std::stringstream exec_link; + exec_link << "/proc/self/exe"; + ssize_t path_length = readlink(exec_link.str().c_str(), exe_path, 1024); + assert(path_length != -1); + exe_path[path_length] = '\0'; + + char *token = strtok(exe_path, "/"); + while(token !=NULL){ + self_exe_path = token; + token = strtok(NULL,"/"); + } +#endif + self_exe_path = strtok(self_exe_path, "."); + printf("self exe links to: %s\n", self_exe_path); + return self_exe_path; +} + void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version ) { - char fname[1024]; - snprintf(fname,1024,"_ptx_XXXXXX"); - int fd=mkstemp(fname); - close(fd); - - printf("GPGPU-Sim PTX: extracting embedded .ptx to temporary file \"%s\"\n", fname); - FILE *ptxfile = fopen(fname,"w"); - fprintf(ptxfile,"%s", p_for_info); - fclose(ptxfile); - - char fname2[1024]; - snprintf(fname2,1024,"_ptx2_XXXXXX"); - fd=mkstemp(fname2); - close(fd); - char commandline2[4096]; - snprintf(commandline2,4096,"cat %s | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\\(\\.extern \\.const\\[1\\] .b8 \\w\\+\\)\\[\\]/\\1\\[1\\]/' | sed 's/const\\[.\\]/const\\[0\\]/g' > %s", fname, fname2); - printf("Running: %s\n", commandline2); - int result = system(commandline2); - if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); - printf(" Ensure you have write access to simulation directory\n"); - printf(" and have \'cat\' and \'sed\' in your path.\n"); - exit(1); - } - - char tempfile_ptxinfo[1024]; - snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); - char commandline[1024]; - char extra_flags[1024]; - extra_flags[0]=0; - -#if CUDART_VERSION >= 3000 - if (sm_version == 0) sm_version = 20; - extern bool g_cdp_enabled; - if(!g_cdp_enabled) - snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); - else - snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version); -#endif + //do ptxas for individual files instead of one big embedded ptx. This prevents the duplicate defs and declarations. + char ptx_file[1000]; + char *name=get_app_binary_name(); + char commandline[4096], fname[1024], fname2[1024]; + for (int index=1; index <= no_of_ptx; index++){ + snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", name, index, sm_version); + snprintf(fname,1024,"_ptx_XXXXXX"); + int fd=mkstemp(fname); + close(fd); - snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", + printf("GPGPU-Sim PTX: extracting embedded .ptx to temporary file \"%s\"\n", fname); + snprintf(commandline,4096,"cat %s > %s",ptx_file, fname); + if (system(commandline) !=0) { + printf("ERROR: %s command failed\n", commandline); + exit(0); + } + + snprintf(fname2,1024,"_ptx2_XXXXXX"); + fd=mkstemp(fname2); + close(fd); + char commandline2[4096]; + snprintf(commandline2,4096,"cat %s | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\\(\\.extern \\.const\\[1\\] .b8 \\w\\+\\)\\[\\]/\\1\\[1\\]/' | sed 's/const\\[.\\]/const\\[0\\]/g' > %s", fname, fname2); + printf("Running: %s\n", commandline2); + int result = system(commandline2); + if( result != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); + printf(" Ensure you have write access to simulation directory\n"); + printf(" and have \'cat\' and \'sed\' in your path.\n"); + exit(1); + } + + char tempfile_ptxinfo[1024]; + snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); + char extra_flags[1024]; + extra_flags[0]=0; + + #if CUDART_VERSION >= 3000 + if (sm_version == 0) sm_version = 20; + extern bool g_cdp_enabled; + if(!g_cdp_enabled) + snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); + else + snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version); + #endif + + snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", extra_flags, fname2, tempfile_ptxinfo); - printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); - result = system(commandline); - if( result != 0 ) { - // 65280 = duplicate errors - if (result == 65280) { - ptxinfo_in = fopen(tempfile_ptxinfo,"r"); + printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); + result = system(commandline); + if( result != 0 ) { + // 65280 = duplicate errors + if (result == 65280) { + ptxinfo_in = fopen(tempfile_ptxinfo,"r"); g_ptxinfo_filename = tempfile_ptxinfo; ptxinfo_parse(); @@ -345,26 +377,35 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num extra_flags, fname2, tempfile_ptxinfo); printf("GPGPU-Sim PTX: regenerating ptxinfo using \"%s\"\n", commandline); result = system(commandline); - } - if (result != 0) { + } + if (result != 0) { printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); printf(" Ensure ptxas is in your path.\n"); exit(1); - } + } + } } - - ptxinfo_in = fopen(tempfile_ptxinfo,"r"); - g_ptxinfo_filename = tempfile_ptxinfo; + //Now that we got resource usage per kernel in a ptx file, we dump all into one file and pass it to rest of the code as usual. + char commandline3[4096]; + char final_tempfile_ptxinfo[1024]; + snprintf(final_tempfile_ptxinfo,1024,"f_tempfile_ptx"); + snprintf(commandline3,4096, "cat *info > %s", final_tempfile_ptxinfo); + if (system(commandline3)!=0) { + printf("ERROR: Either we dont have info files or cat is not working \n"); + printf("ERROR: %s command failed\n",commandline3); + exit(1); + } + + ptxinfo_in = fopen(final_tempfile_ptxinfo,"r"); + g_ptxinfo_filename = final_tempfile_ptxinfo; ptxinfo_parse(); if( ! g_save_embedded_ptx ) { - snprintf(commandline,1024,"rm -f %s %s %s", fname, fname2, tempfile_ptxinfo); + snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, final_tempfile_ptxinfo); printf("GPGPU-Sim PTX: removing ptxinfo using \"%s\"\n", commandline); - result = system(commandline); - if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (c) %d\n", result); + if( system(commandline) != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while removing temporary files\n"); exit(1); } } } - diff --git a/src/cuda-sim/ptx_loader.h b/src/cuda-sim/ptx_loader.h index d3d0c92..a8ecda3 100644 --- a/src/cuda-sim/ptx_loader.h +++ b/src/cuda-sim/ptx_loader.h @@ -30,6 +30,7 @@ #include extern bool g_override_embedded_ptx; +extern int no_of_ptx; //counter to track number of ptx files to be extracted in an application. class symbol_table *gpgpu_ptx_sim_load_ptx_from_string( const char *p, unsigned source_num ); void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version=20 ); -- cgit v1.3 From 1af82fbe97428654b06b7cd8d40c2d2ce4592aae Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 26 Mar 2018 11:35:25 -0400 Subject: Fixing resources limitation assertion for compute cab 61 --- configs/Pascal-P102-GDDR5X/gpgpusim.config | 1 + src/gpgpu-sim/gpu-sim.cc | 3 +++ src/gpgpu-sim/shader.cc | 4 ++++ src/gpgpu-sim/shader.h | 1 + 4 files changed, 9 insertions(+) diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config index 0c6c126..b7bcdaf 100644 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config @@ -6,6 +6,7 @@ -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 61 +-gpgpu_ignore_resources_limitation 1 # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 17f1714..48af41e 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -268,6 +268,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shader_registers", OPT_UINT32, &gpgpu_shader_registers, "Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)", "8192"); + option_parser_register(opp, "-gpgpu_ignore_resources_limitation", OPT_BOOL, &gpgpu_ignore_resources_limitation, + "gpgpu_ignore_resources_limitation (default 0)", + "0"); option_parser_register(opp, "-gpgpu_shader_cta", OPT_UINT32, &max_cta_per_core, "Maximum number of concurrent CTAs in shader (default 8)", "8"); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index bf482fb..8173191 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -2614,6 +2614,10 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const assert( result <= MAX_CTA_PER_SHADER ); if (result < 1) { printf ("GPGPU-Sim uArch: ERROR ** Kernel requires more resources than shader has.\n"); + if(gpgpu_ignore_resources_limitation) { + printf ("GPGPU-Sim uArch: gpgpu_ignore_resources_limitation is set, ignore the ERROR!\n"); + return 1; + } abort(); } diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 5b41c06..ae22eaa 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1386,6 +1386,7 @@ struct shader_core_config : public core_config unsigned gpgpu_num_reg_banks; bool gpgpu_reg_bank_use_warp_id; bool gpgpu_local_mem_map; + bool gpgpu_ignore_resources_limitation; unsigned max_sp_latency; unsigned max_sfu_latency; -- cgit v1.3 From 8b40edc95b301269f1c0f43fdb94b3adc6b21845 Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Mon, 26 Mar 2018 19:08:58 -0400 Subject: .call instruction may have an empty argument list --- src/cuda-sim/ptx.y | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index e00aa4b..a66f508 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -513,7 +513,8 @@ compare_spec:EQ_OPTION { add_option(EQ_OPTION); } | NAN_OPTION { add_option(NAN_OPTION); } ; -operand_list: operand +operand_list: /* empty*/ + | operand | operand COMMA operand_list; operand: IDENTIFIER { add_scalar_operand( $1 ); } -- cgit v1.3 From 7a47f490efb7e7e7e4b960107f9bae79c5ab4a3d Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Mon, 26 Mar 2018 19:09:59 -0400 Subject: Remove duplicate token in PTX parser --- src/cuda-sim/ptx.y | 1 - 1 file changed, 1 deletion(-) diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index a66f508..4edae5d 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -47,7 +47,6 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token PTR_DIRECTIVE %token ENTRY_DIRECTIVE %token EXTERN_DIRECTIVE -%token WEAK_DIRECTIVE %token FILE_DIRECTIVE %token FUNC_DIRECTIVE %token GLOBAL_DIRECTIVE -- cgit v1.3 From c7d21017fcec06ef9d0d87e0a94c38deab5e1e1c Mon Sep 17 00:00:00 2001 From: Nathan J Conrad Date: Sat, 24 Mar 2018 11:39:14 -0400 Subject: Add vim swap files to gitignore --- .gitignore | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 53fadb5..0d84ba2 100644 --- a/.gitignore +++ b/.gitignore @@ -26,4 +26,5 @@ cuobjdump_to_ptxplus/sass_parser.cc cuobjdump_to_ptxplus/sass_parser.hh cuobjdump_to_ptxplus/sass_parser.output -build/* \ No newline at end of file +build/* +*.swp -- cgit v1.3 From d82197eba40f13a08784e8d873f6737b93f5bc41 Mon Sep 17 00:00:00 2001 From: Nathan J Conrad Date: Sat, 24 Mar 2018 15:01:12 -0400 Subject: Ignore generated docs in gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 0d84ba2..887b605 100644 --- a/.gitignore +++ b/.gitignore @@ -8,6 +8,7 @@ libcuda/cuobjdump_parser.h libcuda/cuobjdump_parser.output lib/* +doc/doxygen/html cuobjdump_to_ptxplus/elf_lexer.cc cuobjdump_to_ptxplus/elf_parser.cc -- cgit v1.3 From 6b7d14e294d8cb73e2281b7e18a4083e3271a85e Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Mon, 26 Mar 2018 19:20:24 -0400 Subject: Provide portable (non-x86) breakpoint method which should work on all linuxes. Tested on PowerPC. --- src/gpgpu-sim/gpu-sim.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 58a5d16..3829861 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -32,6 +32,7 @@ #include #include #include +#include #include "zlib.h" @@ -1440,7 +1441,7 @@ void gpgpu_sim::cycle() if( g_single_step && ((gpu_sim_cycle+gpu_tot_sim_cycle) >= g_single_step) ) { - asm("int $03"); + raise(SIGTRAP); // Debug breakpoint } gpu_sim_cycle++; if( g_interactive_debugger_enabled ) -- cgit v1.3 From 17ff26759ca0fb41095d2d0afaaed3059e6360ad Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Mon, 26 Mar 2018 19:35:41 -0400 Subject: Don't directly pass strings to printf (beacuse they wouldn't be escapped). Clang gives warnings about this. --- libcuda/cuobjdump.l | 6 ++---- src/cuda-sim/ptx_parser.cc | 10 +++++----- 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/libcuda/cuobjdump.l b/libcuda/cuobjdump.l index f63ee73..0953ea1 100644 --- a/libcuda/cuobjdump.l +++ b/libcuda/cuobjdump.l @@ -159,8 +159,6 @@ newlines {newline}+ %% void cuobjdump_error(const char* message) { - printf(" "); printf(message); printf(" near \""); printf(yytext); printf("\""); - printf(" on line "); - char line[5]; sprintf(line, "%i", yylineno); printf(line); - printf("\n"); + printf(" %s near \"%s\"",message, yytext); + printf(" on line %i\n",yylineno); } diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index baa3bcd..a180da9 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -433,7 +433,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_shared_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (shared memory space)\n", + printf("from 0x%llx to 0x%llx (shared memory space)\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); @@ -450,7 +450,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_global_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (global memory space) %u\n", + printf("from 0x%llx to 0x%llx (global memory space) %u\n", addr+addr_pad, addr+addr_pad + num_bits/8, g_const_alloc++); @@ -471,7 +471,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_global_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (global memory space)\n", + printf("from 0x%llx to 0x%llx (global memory space)\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); @@ -488,7 +488,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_local_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx (local memory space)\n", + printf("from 0x%llx to 0x%llx (local memory space)\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); @@ -501,7 +501,7 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident assert( (num_bits%8) == 0 ); addr = g_current_symbol_table->get_local_next(); addr_pad = pad_address(addr, num_bits/8, 128); - printf("from 0x%x to 0x%lx\n", + printf("from 0x%llx to 0x%llx\n", addr+addr_pad, addr+addr_pad + num_bits/8); fflush(stdout); -- cgit v1.3 From a49e6999ee9c95748a306e1bbfe789930ad5c464 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 26 Mar 2018 22:51:07 -0400 Subject: Adding in a nightly build that runs the world --- Jenkinsfile.nightly | 77 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Jenkinsfile.nightly diff --git a/Jenkinsfile.nightly b/Jenkinsfile.nightly new file mode 100644 index 0000000..a8b5fc7 --- /dev/null +++ b/Jenkinsfile.nightly @@ -0,0 +1,77 @@ +pipeline { + agent { + label "purdue-cluster" + } + + triggers { + chron('H H * * *') + } + + stages { + stage('simulator-build') { + steps { + "9.1" : { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + make -j' + } + } + } + stage('simulations-build'){ + steps{ + sh 'rm -rf gpgpu-sim_simulations' + sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ + cd gpgpu-sim_simulations && \ + git checkout purdue-cluster && \ + git pull && \ + rm -r ./benchmarks/data_dirs && ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + cd gpgpu-sim_simulations && \ + source ./benchmarks/src/setup_environment && \ + make -j -C ./benchmarks/src/ rodinia_2.0-ft sdk-4.2 && \ + make -C ./benchmarks/src data' + } + } + stage('2B-insn'){ + steps { + "9.1-rodinia": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM -N nightly-$$ && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N nightly-$$ && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + } + } + } + stage('9.1-correlate'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B `cat apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM > stats-9.1.csv && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ + ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ + scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' + } + } + } + post { + success { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - Success!", + to: 'tgrogers@purdue.edu' + } + failure { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - ${currentBuild.result}", + to: 'tgrogers@purdue.edu' + } + } +} + -- cgit v1.3 From 28ac03ba1056718d9ec904f3b76319d8e9e2dfd0 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 26 Mar 2018 23:19:16 -0400 Subject: Diabling concurrent builds --- Jenkinsfile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Jenkinsfile b/Jenkinsfile index 2cff7b2..d03e7b9 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -3,6 +3,10 @@ pipeline { label "purdue-cluster" } + options { + disableConcurrentBuilds() + } + stages { stage('simulator-build') { steps { -- cgit v1.3 From 89c198ba1f271bfc12a6c7d9c471e62a8daa5634 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Tue, 27 Mar 2018 04:21:38 -0400 Subject: Correcting the segfault in stats print. It was because print_stats() was called before g_ptx_kernel_count was initialized --- src/gpgpusim_entrypoint.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index 1ee980a..fe9e419 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -156,7 +156,7 @@ void *gpgpu_sim_thread_concurrent(void*) printf("GPGPU-Sim: ** STOP simulation thread (no work) **\n"); fflush(stdout); } - g_the_gpu->print_stats(); + //g_the_gpu->print_stats(); if(sim_cycles) { g_the_gpu->update_stats(); print_simulation_time(); -- cgit v1.3 From a82bf4b57e8669226bef6e1b86ce654d5971e25b Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 27 Mar 2018 11:52:33 -0400 Subject: Removing some configs that don't have to be run anymore. --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index d03e7b9..84689a8 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -63,7 +63,7 @@ pipeline { }, "4.2-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480,TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480,GTX480-PTXPLUS -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' @@ -81,7 +81,7 @@ pipeline { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C TITANX-P102,P100-HBM > stats-4.2.csv && \ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS > stats-4.2.csv && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-4.2.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ -- cgit v1.3 From a5578ff87d0516310d799a8e88e3288c1b44a429 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Tue, 27 Mar 2018 11:59:59 -0400 Subject: Update the write policy in P100 --- configs/Pascal-P100-HBM/gpgpusim.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config index 857a0ff..9a7259e 100644 --- a/configs/Pascal-P100-HBM/gpgpusim.config +++ b/configs/Pascal-P100-HBM/gpgpusim.config @@ -65,7 +65,7 @@ -gpgpu_n_cluster_ejection_buffer_size 32 # 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 4MB L2 cache --gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:256:4,32:0,32 +-gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:256:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 -perf_sim_memcpy 0 -- cgit v1.3 From cb7d4e6e41b17d95f9007e0ddf27515abc5db25e Mon Sep 17 00:00:00 2001 From: tgrogers Date: Tue, 27 Mar 2018 12:45:41 -0400 Subject: sdk does not work with ptxplus --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 84689a8..a8bd7f7 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -63,7 +63,7 @@ pipeline { }, "4.2-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480,GTX480-PTXPLUS -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480 -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' @@ -81,7 +81,7 @@ pipeline { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS > stats-4.2.csv && \ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS > stats-4.2.csv && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-4.2.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ -- cgit v1.3 From 5e8b10d9a0ea518dcb6c3c88b0a9cfd143363bcd Mon Sep 17 00:00:00 2001 From: Amruth Date: Tue, 27 Mar 2018 14:12:05 -0700 Subject: support for pinned memories - temporary fix --- libcuda/cuda_runtime_api.cc | 53 +++++++++++++++++++++++++++++++++++++++++-- src/abstract_hardware_model.h | 3 +++ src/cuda-sim/ptx_ir.cc | 6 +++-- 3 files changed, 58 insertions(+), 4 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index f74c4eb..97d702c 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -145,6 +145,8 @@ #include #endif +std::map pinned_memory; //support for pinned memories added +std::map pinned_memory_size; int no_of_ptx=0; extern void synchronize(); @@ -476,6 +478,8 @@ __host__ cudaError_t CUDARTAPI cudaMallocHost(void **ptr, size_t size) GPGPUSim_Context(); *ptr = malloc(size); if ( *ptr ) { + //track pinned memory size allocated in the host so that same amount of memory is also allocated in GPU. + pinned_memory_size[*ptr]=size; return g_last_cudaError = cudaSuccess; } else { return g_last_cudaError = cudaErrorMemoryAllocation; @@ -766,6 +770,16 @@ __host__ cudaError_t CUDARTAPI cudaMemset(void *mem, int c, size_t count) return g_last_cudaError = cudaSuccess; } +//memset operation is done but i think its not async? +__host__ cudaError_t CUDARTAPI cudaMemsetAsync(void *mem, int c, size_t count, cudaStream_t stream=0) +{ + printf("GPGPU-Sim PTX: WARNING: Asynchronous memset not supported (%s)\n", __my_func__); + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + gpu->gpu_memset((size_t)mem, c, count); + return g_last_cudaError = cudaSuccess; +} + __host__ cudaError_t CUDARTAPI cudaMemset2D(void *mem, size_t pitch, int c, size_t width, size_t height) { cuda_not_implemented(__my_func__,__LINE__); @@ -855,6 +869,12 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 76: *value= 3 ; break; + case 78: + *value= 0 ; //TODO: as of now, we dont support stream priorities. + break; + default: + printf("ERROR: implement the attribute numbered %d \n",attr); + abort(); } return g_last_cudaError = cudaSuccess; } else { @@ -1054,6 +1074,15 @@ __host__ cudaError_t CUDARTAPI cudaStreamCreate(cudaStream_t *stream) return g_last_cudaError = cudaSuccess; } +//TODO: introduce priorities +__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithPriority(cudaStream_t *stream, unsigned int flags, int priority) { + return cudaStreamCreate(stream); +} + +__host__ __device__ cudaError_t CUDARTAPI cudaDeviceGetStreamPriorityRange(int* leastPriority, int* greatestPriority) { + return cudaSuccess; +} + __host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *stream, unsigned int flags) { return cudaStreamCreate(stream); } @@ -2206,6 +2235,9 @@ cudaError_t cudaGLUnregisterBufferObject(GLuint bufferObj) cudaError_t CUDARTAPI cudaHostAlloc(void **pHost, size_t bytes, unsigned int flags) { *pHost = malloc(bytes); + //need to track the size allocated so that cudaHostGetDevicePointer() can function properly. + //TODO: vary this function behavior based on flags value (following nvidia documentation) + pinned_memory_size[*pHost]=bytes; if( *pHost ) return g_last_cudaError = cudaSuccess; else @@ -2214,8 +2246,25 @@ cudaError_t CUDARTAPI cudaHostAlloc(void **pHost, size_t bytes, unsigned int fl cudaError_t CUDARTAPI cudaHostGetDevicePointer(void **pDevice, void *pHost, unsigned int flags) { - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; + //only cpu memory allocation happens in cudaHostAlloc. Linking with device pointer to pinned memory happens here. + //TODO: once kernel is executed, the contents in global pointer of GPU must be copied back to CPU host pointer! + flags=0; + CUctx_st* context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + std::map::const_iterator i = pinned_memory_size.find(pHost); + assert(i != pinned_memory_size.end()); + size_t size = i->second; + *pDevice = gpu->gpu_malloc(size); + if(g_debug_execution >= 3) + printf("GPGPU-Sim PTX: cudaMallocing %zu bytes starting at 0x%llx..\n",size, (unsigned long long) *pDevice); + if ( *pDevice ) { + pinned_memory[pHost]=pDevice; + //Copy contents in cpu to gpu + gpu->memcpy_to_gpu((size_t)*pDevice,pHost,size); + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorMemoryAllocation; + } } cudaError_t CUDARTAPI cudaSetValidDevices(int *device_arr, int len) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index aaa4b00..67b36c7 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -182,6 +182,9 @@ void increment_x_then_y_then_z( dim3 &i, const dim3 &bound); class stream_manager; struct CUstream_st; extern stream_manager * g_stream_manager; +//support for pinned memories added +extern std::map pinned_memory; +extern std::map pinned_memory_size; class kernel_info_t { public: diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 6a17eaf..17e91df 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -280,8 +280,10 @@ type_info *symbol_table::get_array_type( type_info *base_type, unsigned array_di { type_info_key t = base_type->get_key(); t.set_array_dim(array_dim); - type_info *pt; - pt = m_types[t] = new type_info(this,t); + type_info *pt = new type_info(this,t); + //Where else is m_types being used? As of now, I dont find any use of it and causing seg fault. So disabling m_types. + //TODO: find where m_types can be used in future and solve the seg fault. + //pt = m_types[t] = new type_info(this,t); return pt; } -- cgit v1.3 From 0d07b73b58224724cff0576d91878817ec3c01c1 Mon Sep 17 00:00:00 2001 From: Amruth Date: Tue, 27 Mar 2018 15:52:52 -0700 Subject: considered CDP scenario --- libcuda/cuda_runtime_api.cc | 24 +++++++------- src/cuda-sim/ptx_loader.cc | 77 +++++++++++++++++++++++++++++++++++++-------- 2 files changed, 77 insertions(+), 24 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 97d702c..57c5ea1 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1083,8 +1083,8 @@ __host__ __device__ cudaError_t CUDARTAPI cudaDeviceGetStreamPriorityRange(int* return cudaSuccess; } -__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *stream, unsigned int flags) { - return cudaStreamCreate(stream); +__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *pStream, unsigned int flags) { + return cudaStreamCreate(pStream); } __host__ cudaError_t CUDARTAPI cudaStreamDestroy(cudaStream_t stream) @@ -1496,14 +1496,16 @@ void extract_code_using_cuobjdump(){ fclose(fp); } } - //based on the list above, dump ptx files individually. Format of dumped ptx file is prog_name.unique_no.sm_<>.ptx - for (int index=1; index<= no_of_ptx; index++){ - snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", get_app_binary_name(app_binary), index, forced_max_capability); - printf("Extracting specific PTX file named %s \n",ptx_file); - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -arch=sm_%u -xptx %s %s", forced_max_capability, ptx_file, app_binary.c_str()); - if (system(command)!=0) { - printf("ERROR: command: %s failed \n",command); - exit(0); + if(!g_cdp_enabled) { + //based on the list above, dump ptx files individually. Format of dumped ptx file is prog_name.unique_no.sm_<>.ptx + for (int index=1; index<= no_of_ptx; index++){ + snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", get_app_binary_name(app_binary), index, forced_max_capability); + printf("Extracting specific PTX file named %s \n",ptx_file); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -arch=sm_%u -xptx %s %s", forced_max_capability, ptx_file, app_binary.c_str()); + if (system(command)!=0) { + printf("ERROR: command: %s failed \n",command); + exit(0); + } } } //TODO: redundant to dump twice. how can it be prevented? @@ -1516,7 +1518,7 @@ void extract_code_using_cuobjdump(){ if(!g_cdp_enabled) snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname); else - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_%u -all %s > %s", forced_max_capability, app_binary.c_str(), fname); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); bool parse_output = true; result = system(command); if(result) { diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index d98ca07..9ff0859 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -319,7 +319,7 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num //do ptxas for individual files instead of one big embedded ptx. This prevents the duplicate defs and declarations. char ptx_file[1000]; char *name=get_app_binary_name(); - char commandline[4096], fname[1024], fname2[1024]; + char commandline[4096], fname[1024], fname2[1024], final_tempfile_ptxinfo[1024], tempfile_ptxinfo[1024]; for (int index=1; index <= no_of_ptx; index++){ snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", name, index, sm_version); snprintf(fname,1024,"_ptx_XXXXXX"); @@ -347,7 +347,6 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num exit(1); } - char tempfile_ptxinfo[1024]; snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); char extra_flags[1024]; extra_flags[0]=0; @@ -385,23 +384,75 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num } } } + + //TODO: duplicate code! move it into a function so that it can be reused! + if(no_of_ptx==0) { + //For CDP, we dump everything. So no_of_ptx will be 0. + snprintf(fname,1024,"_ptx_XXXXXX"); + int fd=mkstemp(fname); + close(fd); + + printf("GPGPU-Sim PTX: extracting embedded .ptx to temporary file \"%s\"\n", fname); + FILE *ptxfile = fopen(fname,"w"); + fprintf(ptxfile,"%s", p_for_info); + fclose(ptxfile); + + snprintf(fname2,1024,"_ptx2_XXXXXX"); + fd=mkstemp(fname2); + close(fd); + char commandline2[4096]; + snprintf(commandline2,4096,"cat %s | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\\(\\.extern \\.const\\[1\\] .b8 \\w\\+\\)\\[\\]/\\1\\[1\\]/' | sed 's/const\\[.\\]/const\\[0\\]/g' > %s", fname, fname2); + printf("Running: %s\n", commandline2); + int result = system(commandline2); + if( result != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); + printf(" Ensure you have write access to simulation directory\n"); + printf(" and have \'cat\' and \'sed\' in your path.\n"); + exit(1); + } + char tempfile_ptxinfo[1024]; + snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); + char extra_flags[1024]; + extra_flags[0]=0; +#if CUDART_VERSION >= 3000 + snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); +#endif + + snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", + extra_flags, fname2, tempfile_ptxinfo); + printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); + result = system(commandline); + if( result != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); + printf(" Ensure ptxas is in your path.\n"); + exit(1); + } + } + //Now that we got resource usage per kernel in a ptx file, we dump all into one file and pass it to rest of the code as usual. - char commandline3[4096]; - char final_tempfile_ptxinfo[1024]; - snprintf(final_tempfile_ptxinfo,1024,"f_tempfile_ptx"); - snprintf(commandline3,4096, "cat *info > %s", final_tempfile_ptxinfo); - if (system(commandline3)!=0) { - printf("ERROR: Either we dont have info files or cat is not working \n"); - printf("ERROR: %s command failed\n",commandline3); - exit(1); - } + if(no_of_ptx>0){ + char commandline3[4096]; + snprintf(final_tempfile_ptxinfo,1024,"f_tempfile_ptx"); + snprintf(commandline3,4096, "cat *info > %s", final_tempfile_ptxinfo); + if (system(commandline3)!=0) { + printf("ERROR: Either we dont have info files or cat is not working \n"); + printf("ERROR: %s command failed\n",commandline3); + exit(1); + } + } ptxinfo_in = fopen(final_tempfile_ptxinfo,"r"); - g_ptxinfo_filename = final_tempfile_ptxinfo; + if(no_of_ptx>0) + g_ptxinfo_filename = final_tempfile_ptxinfo; + else + g_ptxinfo_filename = tempfile_ptxinfo; ptxinfo_parse(); if( ! g_save_embedded_ptx ) { - snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, final_tempfile_ptxinfo); + if(no_of_ptx>0) + snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, final_tempfile_ptxinfo); + else + snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, tempfile_ptxinfo); printf("GPGPU-Sim PTX: removing ptxinfo using \"%s\"\n", commandline); if( system(commandline) != 0 ) { printf("GPGPU-Sim PTX: ERROR ** while removing temporary files\n"); -- cgit v1.3 From 3d2a9cc1b4a32237eb8a6fa84e999962001c715e Mon Sep 17 00:00:00 2001 From: Amruth Date: Tue, 27 Mar 2018 16:48:51 -0700 Subject: small corrections --- libcuda/cuda_runtime_api.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 57c5ea1..c622720 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1075,11 +1075,11 @@ __host__ cudaError_t CUDARTAPI cudaStreamCreate(cudaStream_t *stream) } //TODO: introduce priorities -__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithPriority(cudaStream_t *stream, unsigned int flags, int priority) { +__host__ cudaError_t CUDARTAPI cudaStreamCreateWithPriority(cudaStream_t *stream, unsigned int flags, int priority) { return cudaStreamCreate(stream); } -__host__ __device__ cudaError_t CUDARTAPI cudaDeviceGetStreamPriorityRange(int* leastPriority, int* greatestPriority) { +__host__ cudaError_t CUDARTAPI cudaDeviceGetStreamPriorityRange(int* leastPriority, int* greatestPriority) { return cudaSuccess; } -- cgit v1.3 From 9cdab90a180aea4d063d7b75bc085c4e8285bc49 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 12:55:07 -0400 Subject: Our internal Jenkinsfile --- Jenkinsfile | 120 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 Jenkinsfile diff --git a/Jenkinsfile b/Jenkinsfile new file mode 100644 index 0000000..a8bd7f7 --- /dev/null +++ b/Jenkinsfile @@ -0,0 +1,120 @@ +pipeline { + agent { + label "purdue-cluster" + } + + options { + disableConcurrentBuilds() + } + + stages { + stage('simulator-build') { + steps { + parallel "4.2": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + make -j' + }, "9.1" : { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + make -j' + } + } + } + stage('simulations-build'){ + steps{ + sh 'rm -rf gpgpu-sim_simulations' + sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ + cd gpgpu-sim_simulations && \ + git checkout purdue-cluster && \ + git pull && \ + rm -r ./benchmarks/data_dirs && ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + cd gpgpu-sim_simulations && \ + source ./benchmarks/src/setup_environment && \ + make -j -C ./benchmarks/src rodinia_2.0-ft sdk-4.2 && \ + make -C ./benchmarks/src data' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + cd gpgpu-sim_simulations && \ + source ./benchmarks/src/setup_environment && \ + make -j -C ./benchmarks/src/ rodinia_2.0-ft sdk-4.2 && \ + make -C ./benchmarks/src data' + } + } + stage('regress'){ + steps { + + parallel "4.2-rodinia": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS -N regress-$$ && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + }, "9.1-rodinia": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N regress-$$ && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + }, "4.2-sdk-4.2": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480 -N regress-$$ && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + }, "9.1-sdk-4.2": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + } + } + } + stage('4.2-correlate'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS > stats-4.2.csv && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ + ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-4.2.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ + scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' + } + } + stage('9.1-correlate'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C TITANX-P102,P100-HBM > stats-9.1.csv && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ + ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ + scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' + } + } + } + post { + success { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - Success!", + to: 'tgrogers@purdue.edu' + } + failure { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - ${currentBuild.result}", + to: 'tgrogers@purdue.edu' + } + } +} + -- cgit v1.3 From 998ee2c94154f0fcd402fac1a05ca17bdd1482f6 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 13:03:10 -0400 Subject: Explicitly loggin in with Jenkins --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index a8bd7f7..f0a7935 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -24,7 +24,7 @@ pipeline { stage('simulations-build'){ steps{ sh 'rm -rf gpgpu-sim_simulations' - sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ + sh 'git clone jenkin99@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ cd gpgpu-sim_simulations && \ git checkout purdue-cluster && \ git pull && \ -- cgit v1.3 From b0ea6b829d1dc459c602e67818787ecbfd4be571 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 13:04:23 -0400 Subject: Mirroring the internal setup_env that enables Jenkins to work --- setup_environment | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/setup_environment b/setup_environment index 854a335..f6a16c5 100644 --- a/setup_environment +++ b/setup_environment @@ -1,12 +1,16 @@ # see README before running this -ps -p $$ | awk '/bash/ || / sh/ || /zsh/ {exit 1;}' && echo "ERROR ** source setup_environment must be run in a bash, zsh or sh shell; see README" && exit +ps -p $$ | awk '/bash/ || / sh/ || /zsh/ {exit 1;}' && echo "WARNING ** source setup_environment must be run in a bash, zsh or sh shell; see README" export GPGPUSIM_SETUP_ENVIRONMENT_WAS_RUN= export GPGPUSIM_ROOT="$( cd "$( dirname "$BASH_SOURCE" )" && pwd )" GPGPUSIM_VERSION_STRING=`cat $GPGPUSIM_ROOT/version | awk '/Version/ {print $8}'` -GPGPUSIM_BUILD_STRING=`cat $GPGPUSIM_ROOT/version | awk '/Change/ {print $6}'` +#Detect Git branch and commit # +GIT_COMMIT=`git log -n 1 | head -1 | sed -re 's/commit (.*)/\1/'` +GIT_FILES_CHANGED=`git diff --numstat --cached && git diff --numstat | wc | sed -re 's/^\s+([0-9]+).*/\1/'` +GPGPUSIM_BUILD_STRING="gpgpu-sim_git-commit-$GIT_COMMIT-modified_$GIT_FILES_CHANGED" + echo -n "GPGPU-Sim version $GPGPUSIM_VERSION_STRING (build $GPGPUSIM_BUILD_STRING) "; if [ ! -n "$CUDA_INSTALL_PATH" ]; then @@ -43,11 +47,9 @@ CC_VERSION=`gcc --version | head -1 | awk '{for(i=1;i<=NF;i++){ if(match($i,/^[0 CUDA_VERSION_STRING=`$CUDA_INSTALL_PATH/bin/nvcc --version | awk '/release/ {print $5;}' | sed 's/,//'`; CUDA_VERSION_NUMBER=`echo $CUDA_VERSION_STRING | sed 's/\./ /' | awk '{printf("%02u%02u", 10*int($1), 10*$2);}'` -if [ $CUDA_VERSION_NUMBER -gt 8000 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then +if [ $CUDA_VERSION_NUMBER -gt 9100 -o $CUDA_VERSION_NUMBER -lt 2030 ]; then echo "ERROR ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not tested with CUDA version $CUDA_VERSION_STRING (please see README)"; return -elif [ $CUDA_VERSION_NUMBER -gt 4020 ]; then - echo "WARNING ** GPGPU-Sim version $GPGPUSIM_VERSION_STRING not fully tested with CUDA version $CUDA_VERSION_STRING (please see README)"; fi if [ $# = '1' ] ; -- cgit v1.3 From 996ec14f61526ac2d50e338f874f37a180f6dfa0 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 13:14:52 -0400 Subject: This does not exist in older CUDAs - only compile it for >5. Not sure if 5 is appropraite - but we test 4.2 and it fails --- libcuda/cuda_runtime_api.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index c622720..eda8d8e 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -832,6 +832,7 @@ __host__ cudaError_t CUDARTAPI cudaGetDeviceProperties(struct cudaDeviceProp *pr } } +#if (CUDART_VERSION > 5000) __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDeviceAttr attr, int device) { const struct cudaDeviceProp *prop; @@ -881,6 +882,7 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic return g_last_cudaError = cudaErrorInvalidDevice; } } +#endif __host__ cudaError_t CUDARTAPI cudaChooseDevice(int *device, const struct cudaDeviceProp *prop) { -- cgit v1.3 From 9acbc174a4c54d3ffa3d78feede017deb45922ec Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 13:21:08 -0400 Subject: This was a useless commmit - there were other problems with pulling the simulation repos --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index f0a7935..a8bd7f7 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -24,7 +24,7 @@ pipeline { stage('simulations-build'){ steps{ sh 'rm -rf gpgpu-sim_simulations' - sh 'git clone jenkin99@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ + sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ cd gpgpu-sim_simulations && \ git checkout purdue-cluster && \ git pull && \ -- cgit v1.3 From a9fe78437c825116500e866799cd6fab04a1f9a5 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 13:31:01 -0400 Subject: Do not run our private configs - just the public configs --- Jenkinsfile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index a8bd7f7..806231e 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -56,7 +56,7 @@ pipeline { }, "9.1-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C GTX1080Ti -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N regress-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' @@ -70,7 +70,7 @@ pipeline { }, "9.1-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX1080Ti -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' @@ -92,7 +92,7 @@ pipeline { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C TITANX-P102,P100-HBM > stats-9.1.csv && \ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C GTX1080Ti > stats-9.1.csv && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ -- cgit v1.3 From 67a257442f46a9e8e02f63a9d71fcc7ca54f3f5e Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 28 Mar 2018 14:00:16 -0400 Subject: adding new counters for parition level para and L2 BW --- src/gpgpu-sim/gpu-sim.cc | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 48af41e..228d4be 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -87,6 +87,12 @@ unsigned long long gpu_tot_sim_cycle = 0; // performance counter for stalls due to congestion. unsigned int gpu_stall_dramfull = 0; unsigned int gpu_stall_icnt2sh = 0; +unsigned long long partiton_reqs_in_parallel = 0; +unsigned long long partiton_reqs_in_parallel_total = 0; +unsigned long long partiton_reqs_in_parallel_util = 0; +unsigned long long partiton_reqs_in_parallel_util_total = 0; +unsigned long long partiton_replys_in_parallel = 0; +unsigned long long partiton_replys_in_parallel_total = 0; /* Clock Domains */ @@ -786,6 +792,9 @@ void gpgpu_sim::init() gpu_sim_insn = 0; last_gpu_sim_insn = 0; m_total_cta_launched=0; + partiton_reqs_in_parallel = 0; + partiton_replys_in_parallel = 0; + partiton_reqs_in_parallel_util = 0; reinit_clock_domains(); set_param_gpgpu_num_shaders(m_config.num_shader()); @@ -822,8 +831,14 @@ void gpgpu_sim::update_stats() { gpu_tot_sim_cycle += gpu_sim_cycle; gpu_tot_sim_insn += gpu_sim_insn; gpu_tot_issued_cta += m_total_cta_launched; + partiton_reqs_in_parallel_total += partiton_reqs_in_parallel; + partiton_replys_in_parallel_total += partiton_replys_in_parallel; + partiton_reqs_in_parallel_util_total += partiton_reqs_in_parallel_util; gpu_sim_cycle = 0; + partiton_reqs_in_parallel = 0; + partiton_replys_in_parallel = 0; + partiton_reqs_in_parallel_util = 0; gpu_sim_insn = 0; m_total_cta_launched = 0; } @@ -1007,6 +1022,19 @@ void gpgpu_sim::gpu_print_stat() printf("gpu_stall_dramfull = %d\n", gpu_stall_dramfull); printf("gpu_stall_icnt2sh = %d\n", gpu_stall_icnt2sh ); + printf("partiton_reqs_in_parallel = %lld\n", partiton_reqs_in_parallel); + printf("partiton_reqs_in_parallel_total = %lld\n", partiton_reqs_in_parallel_total ); + printf("partiton_level_parallism = %12.4f\n", (float)partiton_reqs_in_parallel / gpu_sim_cycle); + printf("partiton_level_parallism_total = %12.4f\n", (float)(partiton_reqs_in_parallel+partiton_reqs_in_parallel_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); + printf("partiton_reqs_in_parallel_util = %lld\n", partiton_reqs_in_parallel_util); + printf("partiton_reqs_in_parallel_util_total = %lld\n", partiton_reqs_in_parallel_util_total ); + printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle); + printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); + printf("partiton_replys_in_parallel = %lld\n", partiton_replys_in_parallel); + printf("partiton_replys_in_parallel_total = %lld\n", partiton_replys_in_parallel_total ); + printf("L2_BW = %12.4f GB/Sec\n", ((float)(partiton_replys_in_parallel * 32) / (gpu_sim_cycle * m_config.icnt_period)) / 1000000000); + printf("L2_BW_total = %12.4f GB/Sec\n", ((float)((partiton_replys_in_parallel+partiton_replys_in_parallel_total) * 32) / ((gpu_tot_sim_cycle+gpu_sim_cycle) * m_config.icnt_period)) / 1000000000 ); + time_t curr_time; time(&curr_time); unsigned long long elapsed_time = MAX( curr_time - g_simulation_starttime, 1 ); @@ -1412,6 +1440,7 @@ void gpgpu_sim::cycle() for (unsigned i=0;in_simt_clusters;i++) m_cluster[i]->icnt_cycle(); } + unsigned partiton_replys_in_parallel_per_cycle = 0; if (clock_mask & ICNT) { // pop from memory controller to interconnect for (unsigned i=0;im_n_mem_sub_partition;i++) { @@ -1424,6 +1453,7 @@ void gpgpu_sim::cycle() mf->set_status(IN_ICNT_TO_SHADER,gpu_sim_cycle+gpu_tot_sim_cycle); ::icnt_push( m_shader_config->mem2device(i), mf->get_tpc(), mf, response_size ); m_memory_sub_partition[i]->pop(); + partiton_replys_in_parallel_per_cycle++; } else { gpu_stall_icnt2sh++; } @@ -1432,6 +1462,7 @@ void gpgpu_sim::cycle() } } } + partiton_replys_in_parallel += partiton_replys_in_parallel_per_cycle; if (clock_mask & DRAM) { for (unsigned i=0;im_n_mem;i++){ @@ -1444,6 +1475,7 @@ void gpgpu_sim::cycle() } // L2 operations follow L2 clock domain + unsigned partiton_reqs_in_parallel_per_cycle = 0; if (clock_mask & L2) { m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].clear(); for (unsigned i=0;im_n_mem_sub_partition;i++) { @@ -1455,11 +1487,15 @@ void gpgpu_sim::cycle() } else { mem_fetch* mf = (mem_fetch*) icnt_pop( m_shader_config->mem2device(i) ); m_memory_sub_partition[i]->push( mf, gpu_sim_cycle + gpu_tot_sim_cycle ); + partiton_reqs_in_parallel_per_cycle++; } m_memory_sub_partition[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle); m_memory_sub_partition[i]->accumulate_L2cache_stats(m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX]); } } + partiton_reqs_in_parallel += partiton_reqs_in_parallel_per_cycle; + if(partiton_reqs_in_parallel_per_cycle > 0) + partiton_reqs_in_parallel_util += partiton_reqs_in_parallel_per_cycle; if (clock_mask & ICNT) { icnt_transfer(); -- cgit v1.3 From 93cdd2e217d7903ccf715a00b6dae8265bb38fca Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 28 Mar 2018 15:22:33 -0400 Subject: adding new stats counter --- src/gpgpu-sim/gpu-sim.cc | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index f216e7c..006d243 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -91,6 +91,8 @@ unsigned long long partiton_reqs_in_parallel = 0; unsigned long long partiton_reqs_in_parallel_total = 0; unsigned long long partiton_reqs_in_parallel_util = 0; unsigned long long partiton_reqs_in_parallel_util_total = 0; +unsigned long long gpu_sim_cycle_parition_util = 0; +unsigned long long gpu_tot_sim_cycle_parition_util = 0; unsigned long long partiton_replys_in_parallel = 0; unsigned long long partiton_replys_in_parallel_total = 0; @@ -795,6 +797,7 @@ void gpgpu_sim::init() partiton_reqs_in_parallel = 0; partiton_replys_in_parallel = 0; partiton_reqs_in_parallel_util = 0; + gpu_sim_cycle_parition_util = 0; reinit_clock_domains(); set_param_gpgpu_num_shaders(m_config.num_shader()); @@ -834,11 +837,14 @@ void gpgpu_sim::update_stats() { partiton_reqs_in_parallel_total += partiton_reqs_in_parallel; partiton_replys_in_parallel_total += partiton_replys_in_parallel; partiton_reqs_in_parallel_util_total += partiton_reqs_in_parallel_util; + gpu_tot_sim_cycle_parition_util += gpu_sim_cycle_parition_util ; gpu_sim_cycle = 0; partiton_reqs_in_parallel = 0; partiton_replys_in_parallel = 0; partiton_reqs_in_parallel_util = 0; + gpu_sim_cycle_parition_util = 0; + gpu_tot_sim_cycle = 0; gpu_sim_insn = 0; m_total_cta_launched = 0; } @@ -1028,8 +1034,10 @@ void gpgpu_sim::gpu_print_stat() printf("partiton_level_parallism_total = %12.4f\n", (float)(partiton_reqs_in_parallel+partiton_reqs_in_parallel_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); printf("partiton_reqs_in_parallel_util = %lld\n", partiton_reqs_in_parallel_util); printf("partiton_reqs_in_parallel_util_total = %lld\n", partiton_reqs_in_parallel_util_total ); - printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle); - printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); + printf("gpu_sim_cycle_parition_util = %lld\n", gpu_sim_cycle_parition_util); + printf("gpu_tot_sim_cycle_parition_util = %lld\n", gpu_tot_sim_cycle_parition_util ); + printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle_parition_util); + printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_sim_cycle_parition_util+gpu_tot_sim_cycle_parition_util) ); printf("partiton_replys_in_parallel = %lld\n", partiton_replys_in_parallel); printf("partiton_replys_in_parallel_total = %lld\n", partiton_replys_in_parallel_total ); printf("L2_BW = %12.4f GB/Sec\n", ((float)(partiton_replys_in_parallel * 32) / (gpu_sim_cycle * m_config.icnt_period)) / 1000000000); @@ -1494,8 +1502,10 @@ void gpgpu_sim::cycle() } } partiton_reqs_in_parallel += partiton_reqs_in_parallel_per_cycle; - if(partiton_reqs_in_parallel_per_cycle > 0) + if(partiton_reqs_in_parallel_per_cycle > 0){ partiton_reqs_in_parallel_util += partiton_reqs_in_parallel_per_cycle; + gpu_sim_cycle_parition_util++; + } if (clock_mask & ICNT) { icnt_transfer(); -- cgit v1.3 From c22eb8a8f6e41921e4e1a5e705cca8d5bbed67e0 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 15:29:46 -0400 Subject: gpuwaatch build does not parallelize nicely without -p --- src/gpuwattch/makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gpuwattch/makefile b/src/gpuwattch/makefile index ab718cc..354c9ec 100644 --- a/src/gpuwattch/makefile +++ b/src/gpuwattch/makefile @@ -11,10 +11,10 @@ opt: $(TAR).mk obj_opt @$(MAKE) TAG=opt -C . -f $(TAR).mk obj_dbg: - mkdir $@ + mkdir -p $@ obj_opt: - mkdir $@ + mkdir -p $@ depend: @$(MAKE) TAG=opt -C . -f $(TAR).mk depend -- cgit v1.3 From bcb7b8f86f7b487ff0b106e3a2f37f95d989fd07 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 16:55:28 -0400 Subject: 20 makes no sense for this part --- configs/GeForceGTX1080Ti/gpgpusim.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/GeForceGTX1080Ti/gpgpusim.config b/configs/GeForceGTX1080Ti/gpgpusim.config index 47c2b6a..a5ada34 100644 --- a/configs/GeForceGTX1080Ti/gpgpusim.config +++ b/configs/GeForceGTX1080Ti/gpgpusim.config @@ -3,7 +3,7 @@ # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 20 +-gpgpu_ptx_force_max_capability 61 # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 -- cgit v1.3 From 635366fe3e9b596318647b9c5bcdd546c522d52a Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Wed, 28 Mar 2018 14:37:43 -0700 Subject: fix compile errors on Ubuntu LTS 16.04 --- libcuda/cuda_runtime_api.cc | 18 +++++++++++------- src/abstract_hardware_model.h | 2 +- src/cuda-sim/cuda-math.h | 2 +- src/cuda-sim/instructions.cc | 8 ++++---- 4 files changed, 17 insertions(+), 13 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index cbe8a11..b7f25bf 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1406,7 +1406,7 @@ void extract_code_using_cuobjdump(){ cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; int result = system(cmd.str().c_str()); if(result){ - std::cout << "Failed to execute: " << cmd << std::endl; + std::cout << "Failed to execute: " << cmd.str() << std::endl; exit(1); } std::ifstream libsf; @@ -1438,7 +1438,7 @@ void extract_code_using_cuobjdump(){ if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} std::cout << "Done" << std::endl; - std::cout << "Trying to parse " << libcodfn << std::endl; + std::cout << "Trying to parse " << libcodfn.str() << std::endl; cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); cuobjdump_parse(); fclose(cuobjdump_in); @@ -1540,7 +1540,7 @@ std::list pruneSectionList(std::list cuobj //! Merge all PTX sections that have a specific identifier into one file std::list mergeMatchingSections(std::list cuobjdumpSectionList, std::string identifier){ - char *ptxcode = ""; + const char *ptxcode = ""; std::list::iterator old_iter; cuobjdumpPTXSection* old_ptxsection = NULL; cuobjdumpPTXSection* ptxsection; @@ -1689,7 +1689,7 @@ std::mapfatbin_registered; std::map name_symtab; //! Keep track of the association between filename and cubin handle -void cuobjdumpRegisterFatBinary(unsigned int handle, char* filename){ +void cuobjdumpRegisterFatBinary(unsigned int handle, const char* filename){ fatbinmap[handle] = filename; } @@ -1764,6 +1764,7 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) if (sizeof(void*) == 4) printf("GPGPU-Sim PTX: FatBin file name extraction has not been tested on 32-bit system.\n"); + #if (CUDART_VERSION <= 6000) // FatBin handle from the .fatbin.c file (one of the intermediate files generated by NVCC) typedef struct {int m; int v; const unsigned long long* d; char* f;} __fatDeviceText __attribute__ ((aligned (8))); __fatDeviceText * fatDeviceText = (__fatDeviceText *) fatCubin; @@ -1772,12 +1773,11 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) // - Obtains the pointer to the actual fatbin structure from the FatBin handle (fatCubin). // - An integer inside the fatbin structure contains the relative offset to the source code file name. // - This offset differs among different CUDA and GCC versions. - #if (CUDART_VERSION <= 6000) char * pfatbin = (char*) fatDeviceText->d; int offset = *((int*)(pfatbin+48)); char * filename = (pfatbin+16+offset); #else - char * filename = "default"; + const char * filename = "default"; #endif // The extracted file name is associated with a fat_cubin_handle passed // into cudaLaunch(). Inside cudaLaunch(), the associated file name is @@ -1798,7 +1798,7 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) return (void**)fat_cubin_handle; } - #if (CUDART_VERSION < 8000) +#if (CUDART_VERSION < 8000) else { static unsigned source_num=1; unsigned long long fat_cubin_handle = next_fat_bin_handle++; @@ -1857,6 +1857,10 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) return (void**)fat_cubin_handle; } #endif + else { + printf("ERROR ** __cudaRegisterFatBinary() needs to be updated\n"); + abort(); + } } void __cudaUnregisterFatBinary(void **fatCubinHandle) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index aaa4b00..7125b6b 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -383,7 +383,7 @@ protected: std::deque m_stack; }; -#define GLOBAL_HEAP_START 0x703E20000 +#define GLOBAL_HEAP_START 0xC0000000 // start allocating from this address (lower values used for allocating globals in .ptx file) #define SHARED_MEM_SIZE_MAX (64*1024) #define LOCAL_MEM_SIZE_MAX (8*1024) diff --git a/src/cuda-sim/cuda-math.h b/src/cuda-sim/cuda-math.h index 4721e8a..a3db0df 100644 --- a/src/cuda-sim/cuda-math.h +++ b/src/cuda-sim/cuda-math.h @@ -321,7 +321,7 @@ float __internal_accurate_fdividef(float a, float b) float __saturatef(float a) { float b; - if (isnan(a)) b = 0.0f; + if (std::isnan(a)) b = 0.0f; else if (a >= 1.0f) b = 1.0f; else if (a <= 0.0f) b = 0.0f; else b = a; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 011c285..71286c9 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1961,7 +1961,7 @@ ptx_reg_t d2d( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, y.f64 = x.f64; break; } - if (isnan(y.f64)) { + if (std::isnan(y.f64)) { y.u64 = 0xfff8000000000000ull; } else if (saturation_mode) { y.f64 = cuda_math::__saturatef(y.f64); @@ -2086,7 +2086,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) } } if ((type == F64_TYPE)||(type == FF64_TYPE)) { - if (isnan(data.f64)) { + if (std::isnan(data.f64)) { data.u64 = 0xfff8000000000000ull; } } @@ -2648,12 +2648,12 @@ void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry bool isNaN(float x) { - return isnan(x); + return std::isnan(x); } bool isNaN(double x) { - return isnan(x); + return std::isnan(x); } void max_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -- cgit v1.3 From c9cc4281bf84ad6cff77d20389b59d14a534ad6b Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Wed, 28 Mar 2018 16:16:38 -0700 Subject: (attempt to) fix compile error in last checkin --- libcuda/cuda_runtime_api.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index b7f25bf..9bdb993 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1856,11 +1856,12 @@ void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) } return (void**)fat_cubin_handle; } - #endif +#else else { printf("ERROR ** __cudaRegisterFatBinary() needs to be updated\n"); abort(); } +#endif } void __cudaUnregisterFatBinary(void **fatCubinHandle) -- cgit v1.3 From 6b6002d8f8f2e23de4a7c5e9dbc45467e846993c Mon Sep 17 00:00:00 2001 From: tgrogers-purdue Date: Thu, 29 Mar 2018 00:44:43 +0000 Subject: Initial Bitbucket Pipelines configuration --- bitbucket-pipelines.yml | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 bitbucket-pipelines.yml diff --git a/bitbucket-pipelines.yml b/bitbucket-pipelines.yml new file mode 100644 index 0000000..b15cc7c --- /dev/null +++ b/bitbucket-pipelines.yml @@ -0,0 +1,13 @@ +# This is a sample build configuration for C++ – Make. +# Check our guides at https://confluence.atlassian.com/x/5Q4SMw for more examples. +# Only use spaces to indent your .yml configuration. +# ----- +# You can specify a custom docker image from Docker Hub as your build environment. +image: gcc:6.1 + +pipelines: + default: + - step: + script: # Modify the commands below to build your repository. + - source setup_environment + - make -j \ No newline at end of file -- cgit v1.3 From 206b46ab50b58a629412f16ff261749e71dcca55 Mon Sep 17 00:00:00 2001 From: tgrogers-purdue Date: Thu, 29 Mar 2018 00:50:47 +0000 Subject: bitbucket-pipelines.yml edited online with Bitbucket --- bitbucket-pipelines.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bitbucket-pipelines.yml b/bitbucket-pipelines.yml index b15cc7c..f03c52a 100644 --- a/bitbucket-pipelines.yml +++ b/bitbucket-pipelines.yml @@ -1,9 +1,9 @@ -# This is a sample build configuration for C++ – Make. +# This is a sample build configuration for C++ – Make. # Check our guides at https://confluence.atlassian.com/x/5Q4SMw for more examples. # Only use spaces to indent your .yml configuration. # ----- # You can specify a custom docker image from Docker Hub as your build environment. -image: gcc:6.1 +image: tgrogers/gpgpu-sim_regress:latest pipelines: default: -- cgit v1.3 From 2a451799316abe72571343c8c94f1f2934f57108 Mon Sep 17 00:00:00 2001 From: tgrogers-purdue Date: Thu, 29 Mar 2018 00:57:10 +0000 Subject: Can I just do the exact same thing as Travis? --- bitbucket-pipelines.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/bitbucket-pipelines.yml b/bitbucket-pipelines.yml index f03c52a..2c53081 100644 --- a/bitbucket-pipelines.yml +++ b/bitbucket-pipelines.yml @@ -9,5 +9,4 @@ pipelines: default: - step: script: # Modify the commands below to build your repository. - - source setup_environment - - make -j \ No newline at end of file + - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" \ No newline at end of file -- cgit v1.3 From 14a8d4ecf7d26e4cf516b788b7a9ff83976204df Mon Sep 17 00:00:00 2001 From: tgrogers-purdue Date: Thu, 29 Mar 2018 01:02:54 +0000 Subject: bitbucket-pipelines.yml edited online with Bitbucket --- bitbucket-pipelines.yml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/bitbucket-pipelines.yml b/bitbucket-pipelines.yml index 2c53081..4b2d7a0 100644 --- a/bitbucket-pipelines.yml +++ b/bitbucket-pipelines.yml @@ -9,4 +9,6 @@ pipelines: default: - step: script: # Modify the commands below to build your repository. - - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" \ No newline at end of file + - ./start_torque.sh + - chown -R runner /home/runner/gpgpu-sim_distribution + - su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" \ No newline at end of file -- cgit v1.3 From acad8ce81a1ea8b6ce516aa913238963136ad5f9 Mon Sep 17 00:00:00 2001 From: tgrogers-purdue Date: Thu, 29 Mar 2018 01:13:30 +0000 Subject: bitbucket-pipelines.yml edited online with Bitbucket --- bitbucket-pipelines.yml | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/bitbucket-pipelines.yml b/bitbucket-pipelines.yml index 4b2d7a0..e9c92db 100644 --- a/bitbucket-pipelines.yml +++ b/bitbucket-pipelines.yml @@ -9,6 +9,7 @@ pipelines: default: - step: script: # Modify the commands below to build your repository. - - ./start_torque.sh - - chown -R runner /home/runner/gpgpu-sim_distribution - - su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" \ No newline at end of file + - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "export CONFIG=configs.gtx1080ti.yml; ./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" + services: + - docker + \ No newline at end of file -- cgit v1.3 From e76a32ee85ef8a132a11cbce69a854084215e728 Mon Sep 17 00:00:00 2001 From: tgrogers-purdue Date: Thu, 29 Mar 2018 01:19:27 +0000 Subject: bitbucket-pipelines.yml edited online with Bitbucket --- bitbucket-pipelines.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bitbucket-pipelines.yml b/bitbucket-pipelines.yml index e9c92db..6e331d4 100644 --- a/bitbucket-pipelines.yml +++ b/bitbucket-pipelines.yml @@ -9,7 +9,7 @@ pipelines: default: - step: script: # Modify the commands below to build your repository. - - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "export CONFIG=configs.gtx1080ti.yml; ./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/$CONFIG -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" + - docker run -v `pwd`:/home/runner/gpgpu-sim_distribution:rw tgrogers/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.gtx1080ti.yml -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress'" services: - docker \ No newline at end of file -- cgit v1.3 From 21ac2041365dc8521a6926244b96e85fd19cc2d3 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 28 Mar 2018 22:52:12 -0400 Subject: Fixing a minor typo in an old config --- src/gpgpu-sim/gpu-sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 58a5d16..d452888 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -223,7 +223,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "per-shader L1 data cache config " " {::,:::,::, | none}", "none" ); - option_parser_register(opp, "-gpgpu_cache:dl1PreShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, + option_parser_register(opp, "-gpgpu_cache:dl1PrefShared", OPT_CSTR, &m_L1D_config.m_config_stringPrefShared, "per-shader L1 data cache config " " {::,:::,::, | none}", "none" ); -- cgit v1.3 From 638e18c04bc634fc510236a53d5aa8c22ef3e1ae Mon Sep 17 00:00:00 2001 From: Amruth Date: Thu, 29 Mar 2018 00:25:23 -0700 Subject: cuobjdump -lptx flag is not supported by cuda 5 and lower --- libcuda/cuda_runtime_api.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index eda8d8e..abe5337 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1472,6 +1472,7 @@ void extract_code_using_cuobjdump(){ extern bool g_cdp_enabled; //dump ptx for all individial ptx files into sepearte files which is later used by ptxas. +#if (CUDART_VERSION >= 6000) char fname2[1024]; snprintf(fname2,1024,"_cuobjdump_list_ptx_XXXXXX"); int fd2=mkstemp(fname2); @@ -1510,6 +1511,7 @@ void extract_code_using_cuobjdump(){ } } } +#endif //TODO: redundant to dump twice. how can it be prevented? //dump only for specific arch char fname[1024]; -- cgit v1.3 From 66107577251189900ba06cce0e8bce036d13079d Mon Sep 17 00:00:00 2001 From: Amruth Date: Thu, 29 Mar 2018 00:32:09 -0700 Subject: compilation fix --- libcuda/cuda_runtime_api.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index abe5337..8426b8e 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1472,13 +1472,14 @@ void extract_code_using_cuobjdump(){ extern bool g_cdp_enabled; //dump ptx for all individial ptx files into sepearte files which is later used by ptxas. + int result=0; #if (CUDART_VERSION >= 6000) char fname2[1024]; snprintf(fname2,1024,"_cuobjdump_list_ptx_XXXXXX"); int fd2=mkstemp(fname2); close(fd2); snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -lptx -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname2); - int result = system(command); + result = system(command); if( result != 0 ) { printf("WARNING: Failed to execute cuobjdump to get list of ptx files \n"); exit(0); -- cgit v1.3 From 24dc02cd1c46ff304fe7d8717c60c24c4b257785 Mon Sep 17 00:00:00 2001 From: Amruth Date: Thu, 29 Mar 2018 01:43:59 -0700 Subject: arch is also not supported for cuda 5 or lower --- libcuda/cuda_runtime_api.cc | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 8426b8e..5452ed0 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1520,10 +1520,15 @@ void extract_code_using_cuobjdump(){ snprintf(fname,1024,"_cuobjdump_complete_output_XXXXXX"); int fd=mkstemp(fname); close(fd); - if(!g_cdp_enabled) + if(!g_cdp_enabled) { +#if (CUDART_VERSION >= 6000) snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname); - else +#else + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass %s > %s", app_binary.c_str(), fname); +#endif + } else { snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); + } bool parse_output = true; result = system(command); if(result) { -- cgit v1.3 From 3b9cc9285b5394320873e42edee03d8f23d6d17e Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Fri, 30 Mar 2018 11:27:57 -0400 Subject: fixing gpu-tot-cycle bug --- src/gpgpu-sim/gpu-sim.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 006d243..7835496 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -844,7 +844,6 @@ void gpgpu_sim::update_stats() { partiton_replys_in_parallel = 0; partiton_reqs_in_parallel_util = 0; gpu_sim_cycle_parition_util = 0; - gpu_tot_sim_cycle = 0; gpu_sim_insn = 0; m_total_cta_launched = 0; } -- cgit v1.3 From 6aba79083ec47a78ad2a9572a03cd52f42141def Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 30 Mar 2018 16:10:27 -0400 Subject: When CDP was added - we started printing garbage stats after every memcpy. I am stopping this by gaurding against it in the same way we do for updating the stat counts (checking if we have executed any cycles before printing). I am not sure what this does to CDP stat prints - as I am not sure what CDP kernels so to sim_cycles.... However EVERY other app except CDP is spewing junk to the output and it really messes up any per-kernel stat collection scripts. --- src/gpgpusim_entrypoint.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index ad4587a..dac9fd8 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -156,8 +156,8 @@ void *gpgpu_sim_thread_concurrent(void*) printf("GPGPU-Sim: ** STOP simulation thread (no work) **\n"); fflush(stdout); } - g_the_gpu->print_stats(); if(sim_cycles) { + g_the_gpu->print_stats(); g_the_gpu->update_stats(); print_simulation_time(); } -- cgit v1.3 From 9b586f9a61cac16b147e6dfea62abecc0a2a8eb7 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 30 Mar 2018 16:20:36 -0400 Subject: Moving the print to avoid spurrious statistics --- src/gpgpusim_entrypoint.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index ad4587a..dac9fd8 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -156,8 +156,8 @@ void *gpgpu_sim_thread_concurrent(void*) printf("GPGPU-Sim: ** STOP simulation thread (no work) **\n"); fflush(stdout); } - g_the_gpu->print_stats(); if(sim_cycles) { + g_the_gpu->print_stats(); g_the_gpu->update_stats(); print_simulation_time(); } -- cgit v1.3 From 177d02254ae38b6331b17dd6cd139b570a03c589 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sat, 31 Mar 2018 06:01:23 +0000 Subject: restore code that selects ptx code that exists --- libcuda/cuda_runtime_api.cc | 4 ---- 1 file changed, 4 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index e4ae251..6cf21dd 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1873,8 +1873,6 @@ void cuobjdumpParseBinary(unsigned int handle){ return; } - //Why to search for capability value if we can directly find it in device info? - #if 0 unsigned max_capability = 0; for ( std::list::iterator iter = cuobjdumpSectionList.begin(); iter != cuobjdumpSectionList.end(); @@ -1883,8 +1881,6 @@ void cuobjdumpParseBinary(unsigned int handle){ if (capability > max_capability) max_capability = capability; } if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); - #endif - unsigned max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); -- cgit v1.3 From 6d36a6a20f6e0c7082243c0dabe1a6b734c5002b Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sat, 31 Mar 2018 08:48:47 -0700 Subject: masked declaration leading to using unitialized buffer as file name, leading to crash this still fails regressions --- src/cuda-sim/ptx_loader.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 9ff0859..34870c4 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -410,7 +410,7 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num printf(" and have \'cat\' and \'sed\' in your path.\n"); exit(1); } - char tempfile_ptxinfo[1024]; + //char tempfile_ptxinfo[1024]; snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); char extra_flags[1024]; extra_flags[0]=0; -- cgit v1.3 From 89db73061e043c26df22c7f18d9adb106d8078ac Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 31 Mar 2018 17:56:50 -0400 Subject: Getting rid of our constant, annoying prints. Running workloads of any size causes ridiculous output file sizes --- src/cuda-sim/cuda-sim.cc | 2 +- src/gpgpu-sim/gpu-sim.cc | 12 +++++++----- src/gpgpu-sim/shader.cc | 14 ++++++++------ src/trace_streams.tup | 1 + 4 files changed, 17 insertions(+), 12 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index d4ace76..a34b99b 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1408,7 +1408,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) if ( (g_ptx_sim_num_insn % 100000) == 0 ) { dim3 ctaid = get_ctaid(); dim3 tid = get_tid(); - printf("GPGPU-Sim PTX: %u instructions simulated : ctaid=(%u,%u,%u) tid=(%u,%u,%u)\n", + DPRINTF(LIVENESS, "GPGPU-Sim PTX: %u instructions simulated : ctaid=(%u,%u,%u) tid=(%u,%u,%u)\n", g_ptx_sim_num_insn, ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z ); fflush(stdout); } diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index d452888..0ef267d 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -36,6 +36,7 @@ #include "shader.h" +#include "shader_trace.h" #include "dram.h" #include "mem_fetch.h" @@ -1175,8 +1176,8 @@ bool shader_core_ctx::occupy_shader_resource_1block(kernel_info_t & k, bool occu m_occupied_regs += (padded_cta_size * ((kernel_info->regs+3)&~3)); m_occupied_ctas++; - printf("GPGPU-Sim uArch: Shader %d occupied %d threads, %d shared mem, %d registers, %d ctas\n", - m_sid, m_occupied_n_threads, m_occupied_shmem, m_occupied_regs, m_occupied_ctas); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: Occupied %d threads, %d shared mem, %d registers, %d ctas\n", + m_occupied_n_threads, m_occupied_shmem, m_occupied_regs, m_occupied_ctas); } return true; @@ -1301,8 +1302,8 @@ void shader_core_ctx::issue_block2core( kernel_info_t &kernel ) m_n_active_cta++; shader_CTA_count_log(m_sid, 1); - printf("GPGPU-Sim uArch: core:%3d, cta:%2u, start_tid:%4u, end_tid:%4u, initialized @(%lld,%lld)\n", - m_sid, free_cta_hw_id, start_thread, end_thread, gpu_sim_cycle, gpu_tot_sim_cycle ); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: cta:%2u, start_tid:%4u, end_tid:%4u, initialized @(%lld,%lld)\n", + free_cta_hw_id, start_thread, end_thread, gpu_sim_cycle, gpu_tot_sim_cycle ); } @@ -1499,7 +1500,8 @@ void gpgpu_sim::cycle() hrs = elapsed_time/3600 - 24*days; minutes = elapsed_time/60 - 60*(hrs + 24*days); sec = elapsed_time - 60*(minutes + 60*(hrs + 24*days)); - printf("GPGPU-Sim uArch: cycles simulated: %lld inst.: %lld (ipc=%4.1f) sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s", + + DPRINTF(LIVENESS, "GPGPU-Sim uArch: cycles simulated: %lld inst.: %lld (ipc=%4.1f) sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s", gpu_tot_sim_cycle + gpu_sim_cycle, gpu_tot_sim_insn + gpu_sim_insn, (double)gpu_sim_insn/(double)gpu_sim_cycle, (unsigned)((gpu_tot_sim_insn+gpu_sim_insn) / elapsed_time), diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index d17e51d..4640d65 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -1969,12 +1969,12 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num, kernel_info_t m_barriers.deallocate_barrier(cta_num); shader_CTA_count_unlog(m_sid, 1); - printf("GPGPU-Sim uArch: Shader %d finished CTA #%d (%lld,%lld), %u CTAs running\n", m_sid, cta_num, gpu_sim_cycle, gpu_tot_sim_cycle, - m_n_active_cta ); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: Finished CTA #%d (%lld,%lld), %u CTAs running\n", + cta_num, gpu_sim_cycle, gpu_tot_sim_cycle, m_n_active_cta); if( m_n_active_cta == 0 ) { - printf("GPGPU-Sim uArch: Shader %u empty (last released kernel %u \'%s\').\n", m_sid, kernel->get_uid(), - kernel->name().c_str() ); + SHADER_DPRINTF(LIVENESS, "GPGPU-Sim uArch: Empty (last released kernel %u \'%s\').\n", + kernel->get_uid(), kernel->name().c_str()); fflush(stdout); //Shader can only be empty when no more cta are dispatched @@ -1989,8 +1989,10 @@ void shader_core_ctx::register_cta_thread_exit( unsigned cta_num, kernel_info_t kernel->dec_running(); if( !m_gpu->kernel_more_cta_left(kernel) ) { if( !kernel->running() ) { - printf("GPGPU-Sim uArch: GPU detected kernel %u \'%s\' finished on shader %u.\n", kernel->get_uid(), - kernel->name().c_str(), m_sid ); + SHADER_DPRINTF(LIVENESS, + "GPGPU-Sim uArch: GPU detected kernel %u \'%s\' finished on shader %u.\n", kernel->get_uid(), + kernel->name().c_str(), m_sid); + if(m_kernel == kernel) m_kernel = NULL; m_gpu->set_kernel_done( kernel ); diff --git a/src/trace_streams.tup b/src/trace_streams.tup index c41690e..fd68a16 100644 --- a/src/trace_streams.tup +++ b/src/trace_streams.tup @@ -29,5 +29,6 @@ TS_TUP_BEGIN( trace_streams_type ) TS_TUP( WARP_SCHEDULER ), TS_TUP( SCOREBOARD ), TS_TUP( MEMORY_PARTITION_UNIT ), + TS_TUP( LIVENESS ), TS_TUP( NUM_TRACE_STREAMS ) TS_TUP_END( trace_streams_type ) -- cgit v1.3 From 0c6928caf8814bf9bd37602bffe6b7b0021f2585 Mon Sep 17 00:00:00 2001 From: Akshay Jain Date: Sun, 1 Apr 2018 12:48:14 -0400 Subject: Stats are now printing properly. Checked in bfs --- src/stream_manager.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 3b6cbd5..21115c6 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -230,7 +230,7 @@ bool stream_manager::operation( bool * sim) { bool check=check_finished_kernel(); pthread_mutex_lock(&m_lock); -// if(check)m_gpu->print_stats(); + if(check)m_gpu->print_stats(); stream_operation op =front(); if(!op.do_operation( m_gpu )) //not ready to execute { -- cgit v1.3 From 48c9d92e2be9a9fe264d3783b0b3ee7af8295b53 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sun, 1 Apr 2018 16:33:59 -0700 Subject: add pdom analysis for function calls -- doesn't fix regressions --- src/cuda-sim/cuda-sim.cc | 2 +- src/cuda-sim/instructions.cc | 9 ++++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 39a04dd..987e3f2 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -255,10 +255,10 @@ void function_info::ptx_assemble() printf(" done.\n"); fflush(stdout); - printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", m_name.c_str() ); //disable pdom analysis here and do it at runtime #if 0 + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", m_name.c_str() ); create_basic_blocks(); connect_basic_blocks(); bool modified = false; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 71286c9..5d97287 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1466,7 +1466,14 @@ void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) const operand_info &target = pI->func_addr(); assert( target.is_function_address() ); const symbol *func_addr = target.get_symbol(); - const function_info *target_func = func_addr->get_pc(); + function_info *target_func = func_addr->get_pc(); + if (target_func->is_pdom_set()) { + printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", target_func->get_name().c_str() ); + } else { + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", target_func->get_name().c_str() ); + target_func->do_pdom(); + target_func->set_pdom(); + } // check that number of args and return match function requirements if( pI->has_return() ^ target_func->has_return() ) { -- cgit v1.3 From deee9038d3d67e60f106776be3dd0a846dd11df9 Mon Sep 17 00:00:00 2001 From: Tor Aamodt Date: Sun, 1 Apr 2018 17:31:14 -0700 Subject: fix regressions -- move call to pre_decode into do_pdom --- src/cuda-sim/cuda-sim.cc | 4 ++-- src/cuda-sim/ptx_ir.cc | 57 ++++++++++++++++++++++++++++-------------------- src/cuda-sim/ptx_ir.h | 2 ++ 3 files changed, 37 insertions(+), 26 deletions(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 987e3f2..dce35ca 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -252,7 +252,7 @@ void function_info::ptx_assemble() target.set_type(label_t); } } - + m_n = n; printf(" done.\n"); fflush(stdout); @@ -282,7 +282,6 @@ void function_info::ptx_assemble() print_postdominators(); print_ipostdominators(); } -#endif printf("GPGPU-Sim PTX: pre-decoding instructions for \'%s\'...\n", m_name.c_str() ); for ( unsigned ii=0; ii < n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions @@ -293,6 +292,7 @@ void function_info::ptx_assemble() fflush(stdout); m_assembled = true; +#endif } addr_t shared_to_generic( unsigned smid, addr_t addr ) diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 17e91df..be25dbe 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -577,30 +577,39 @@ bool function_info::connect_break_targets() //connecting break instructions with return modified; } -void function_info::do_pdom() { - create_basic_blocks(); - connect_basic_blocks(); - bool modified = false; - do { - find_dominators(); - find_idominators(); - modified = connect_break_targets(); - } while (modified == true); - - if ( g_debug_execution>=50 ) { - print_basic_blocks(); - print_basic_block_links(); - print_basic_block_dot(); - } - if ( g_debug_execution>=2 ) { - print_dominators(); - } - find_postdominators(); - find_ipostdominators(); - if ( g_debug_execution>=50 ) { - print_postdominators(); - print_ipostdominators(); - } +void function_info::do_pdom() +{ + create_basic_blocks(); + connect_basic_blocks(); + bool modified = false; + do { + find_dominators(); + find_idominators(); + modified = connect_break_targets(); + } while (modified == true); + + if ( g_debug_execution>=50 ) { + print_basic_blocks(); + print_basic_block_links(); + print_basic_block_dot(); + } + if ( g_debug_execution>=2 ) { + print_dominators(); + } + find_postdominators(); + find_ipostdominators(); + if ( g_debug_execution>=50 ) { + print_postdominators(); + print_ipostdominators(); + } + printf("GPGPU-Sim PTX: pre-decoding instructions for \'%s\'...\n", m_name.c_str() ); + for ( unsigned ii=0; ii < m_n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions + ptx_instruction *pI = m_instr_mem[ii]; + pI->pre_decode(); + } + printf("GPGPU-Sim PTX: ... done pre-decoding instructions for \'%s\'.\n", m_name.c_str() ); + fflush(stdout); + m_assembled = true; } void intersect( std::set &A, const std::set &B ) { diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 26a2839..85b2a3b 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1308,6 +1308,8 @@ private: //parameter size for device kernels int m_args_aligned_size; + + addr_t m_n; // offset in m_instr_mem (used in do_pdom) }; class arg_buffer_t { -- cgit v1.3 From c5da0034dd329976c77e2951e2f879095ea8cdac Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 2 Apr 2018 15:23:44 -0400 Subject: Adding in Mahmoud's changes to the print cache stats --- src/gpgpu-sim/gpu-cache.cc | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 5ea4190..8886398 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -517,18 +517,28 @@ void cache_stats::print_stats(FILE *fout, const char *cache_name) const{ /// the provided name is used. /// The printed format is "[][] = " /// + std::vector< unsigned > total_access; + total_access.resize(NUM_MEM_ACCESS_TYPE, 0); std::string m_cache_name = cache_name; for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) { for (unsigned status = 0; status < NUM_CACHE_REQUEST_STATUS; ++status) { - if(m_stats[type][status] > 0){ - fprintf(fout, "\t%s[%s][%s] = %u\n", - m_cache_name.c_str(), - mem_access_type_str((enum mem_access_type)type), - cache_request_status_str((enum cache_request_status)status), - m_stats[type][status]); - } + fprintf(fout, "\t%s[%s][%s] = %u\n", + m_cache_name.c_str(), + mem_access_type_str((enum mem_access_type)type), + cache_request_status_str((enum cache_request_status)status), + m_stats[type][status]); + if(status != RESERVATION_FAIL) + total_access[type]+= m_stats[type][status]; } } + for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) { + if(total_access[type] > 0) + fprintf(fout, "\t%s[%s][%s] = %u\n", + m_cache_name.c_str(), + mem_access_type_str((enum mem_access_type)type), + "TOTAL_ACCESS", + total_access[type]); + } } void cache_sub_stats::print_port_stats(FILE *fout, const char *cache_name) const -- cgit v1.3 From 21dae0d20e12018f1a9283596cf79be85b25341c Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 2 Apr 2018 15:25:22 -0400 Subject: print out all the cache stats even if they are zero - makes collection more uniform --- src/gpgpu-sim/gpu-cache.cc | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 8191f62..26a1638 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -658,15 +658,13 @@ void cache_stats::print_stats(FILE *fout, const char *cache_name) const{ std::string m_cache_name = cache_name; for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) { for (unsigned status = 0; status < NUM_CACHE_REQUEST_STATUS; ++status) { - if(m_stats[type][status] > 0){ - fprintf(fout, "\t%s[%s][%s] = %u\n", - m_cache_name.c_str(), - mem_access_type_str((enum mem_access_type)type), - cache_request_status_str((enum cache_request_status)status), - m_stats[type][status]); - if(status != RESERVATION_FAIL) - total_access[type]+= m_stats[type][status]; - } + fprintf(fout, "\t%s[%s][%s] = %u\n", + m_cache_name.c_str(), + mem_access_type_str((enum mem_access_type)type), + cache_request_status_str((enum cache_request_status)status), + m_stats[type][status]); + if(status != RESERVATION_FAIL) + total_access[type]+= m_stats[type][status]; } } for (unsigned type = 0; type < NUM_MEM_ACCESS_TYPE; ++type) { -- cgit v1.3 From 26476592e3650e796b51c94dd1a25c162eb1aa64 Mon Sep 17 00:00:00 2001 From: Amruth Date: Tue, 3 Apr 2018 11:43:46 -0700 Subject: crash when print() is sent to pdom analysis --- libcuda/cuda_runtime_api.cc | 15 +- libcuda/cuda_runtime_api.cc~ | 2515 +++++++++++++++++++++++ src/cuda-sim/cuda-sim.cc~ | 2155 ++++++++++++++++++++ src/cuda-sim/instructions.cc | 7 +- src/cuda-sim/instructions.cc~ | 4517 +++++++++++++++++++++++++++++++++++++++++ src/cuda-sim/ptx_loader.cc~ | 462 +++++ 6 files changed, 9663 insertions(+), 8 deletions(-) create mode 100644 libcuda/cuda_runtime_api.cc~ create mode 100644 src/cuda-sim/cuda-sim.cc~ create mode 100644 src/cuda-sim/instructions.cc~ create mode 100644 src/cuda-sim/ptx_loader.cc~ diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 6cf21dd..ded1aee 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1499,6 +1499,12 @@ void extract_code_using_cuobjdump(){ no_of_ptx = no_of_ptx + 1; fclose(fp); } + if(no_of_ptx==0){ + printf("WARNING: Number of ptx in the executable file are 0. One of the reasons might be\n"); + printf("\t1. CDP is enabled\n"); + printf("\t2. cuobjdump -lptx doesnt recognize sm_%u\n",forced_max_capability); + printf("\t3. the application was not compiled with nvcc flag sm_%u\n",forced_max_capability); + } } if(!g_cdp_enabled) { //based on the list above, dump ptx files individually. Format of dumped ptx file is prog_name.unique_no.sm_<>.ptx @@ -1520,15 +1526,10 @@ void extract_code_using_cuobjdump(){ snprintf(fname,1024,"_cuobjdump_complete_output_XXXXXX"); int fd=mkstemp(fname); close(fd); - if(!g_cdp_enabled) { -#if (CUDART_VERSION >= 6000) - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname); -#else + if(!g_cdp_enabled) snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass %s > %s", app_binary.c_str(), fname); -#endif - } else { + else snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); - } bool parse_output = true; result = system(command); if(result) { diff --git a/libcuda/cuda_runtime_api.cc~ b/libcuda/cuda_runtime_api.cc~ new file mode 100644 index 0000000..de7f5e9 --- /dev/null +++ b/libcuda/cuda_runtime_api.cc~ @@ -0,0 +1,2515 @@ +// This file created from cuda_runtime_api.h distributed with CUDA 1.1 +// Changes Copyright 2009, Tor M. Aamodt, Ali Bakhoda and George L. Yuan +// University of British Columbia + +/* + * cuda_runtime_api.cc + * + * Copyright © 2009 by Tor M. Aamodt, Wilson W. L. Fung, Ali Bakhoda, + * George L. Yuan and the University of British Columbia, Vancouver, + * BC V6T 1Z4, All Rights Reserved. + * + * THIS IS A LEGAL DOCUMENT BY DOWNLOADING GPGPU-SIM, YOU ARE AGREEING TO THESE + * TERMS AND CONDITIONS. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNERS OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * NOTE: The files libcuda/cuda_runtime_api.c and src/cuda-sim/cuda-math.h + * are derived from the CUDA Toolset available from http://www.nvidia.com/cuda + * (property of NVIDIA). The files benchmarks/BlackScholes/ and + * benchmarks/template/ are derived from the CUDA SDK available from + * http://www.nvidia.com/cuda (also property of NVIDIA). The files from + * src/intersim/ are derived from Booksim (a simulator provided with the + * textbook "Principles and Practices of Interconnection Networks" available + * from http://cva.stanford.edu/books/ppin/). As such, those files are bound by + * the corresponding legal terms and conditions set forth separately (original + * copyright notices are left in files from these sources and where we have + * modified a file our copyright notice appears before the original copyright + * notice). + * + * Using this version of GPGPU-Sim requires a complete installation of CUDA + * which is distributed seperately by NVIDIA under separate terms and + * conditions. To use this version of GPGPU-Sim with OpenCL requires a + * recent version of NVIDIA's drivers which support OpenCL. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the University of British Columbia nor the names of + * its contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * 4. This version of GPGPU-SIM is distributed freely for non-commercial use only. + * + * 5. No nonprofit user may place any restrictions on the use of this software, + * including as modified by the user, by any other authorized user. + * + * 6. GPGPU-SIM was developed primarily by Tor M. Aamodt, Wilson W. L. Fung, + * Ali Bakhoda, George L. Yuan, at the University of British Columbia, + * Vancouver, BC V6T 1Z4 + */ + +/* + * Copyright 1993-2007 NVIDIA Corporation. All rights reserved. + * + * NOTICE TO USER: + * + * This source code is subject to NVIDIA ownership rights under U.S. and + * international Copyright laws. Users and possessors of this source code + * are hereby granted a nonexclusive, royalty-free license to use this code + * in individual and commercial software. + * + * NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE + * CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR + * IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE. + * IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS + * OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE + * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE + * OR PERFORMANCE OF THIS SOURCE CODE. + * + * U.S. Government End Users. This source code is a "commercial item" as + * that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of + * "commercial computer software" and "commercial computer software + * documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995) + * and is provided to the U.S. Government only as a commercial end item. + * Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through + * 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the + * source code with only those rights set forth herein. + * + * Any use of this source code in individual and commercial software must + * include, in the user documentation and internal comments to the code, + * the above Disclaimer and U.S. Government End Users Notice. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef OPENGL_SUPPORT +#define GL_GLEXT_PROTOTYPES +#ifdef __APPLE__ +#include // Apple's version of GLUT is here +#else +#include +#endif +#endif + +#define __CUDA_RUNTIME_API_H__ + +#include "host_defines.h" +#include "builtin_types.h" +#include "driver_types.h" +#if (CUDART_VERSION < 8000) +#include "__cudaFatFormat.h" +#endif +#include "../src/gpgpu-sim/gpu-sim.h" +#include "../src/cuda-sim/ptx_loader.h" +#include "../src/cuda-sim/cuda-sim.h" +#include "../src/cuda-sim/ptx_ir.h" +#include "../src/cuda-sim/ptx_parser.h" +#include "../src/gpgpusim_entrypoint.h" +#include "../src/stream_manager.h" +#include "../src/abstract_hardware_model.h" + +#include +#include + +#ifdef __APPLE__ +#include +#endif + +std::map pinned_memory; //support for pinned memories added +std::map pinned_memory_size; +int no_of_ptx=0; + +extern void synchronize(); +extern void exit_simulation(); + +static int load_static_globals( symbol_table *symtab, unsigned min_gaddr, unsigned max_gaddr, gpgpu_t *gpu ); +static int load_constants( symbol_table *symtab, addr_t min_gaddr, gpgpu_t *gpu ); + +static kernel_info_t *gpgpu_cuda_ptx_sim_init_grid( const char *kernel_key, + gpgpu_ptx_sim_arg_list_t args, + struct dim3 gridDim, + struct dim3 blockDim, + struct CUctx_st* context ); + +/*DEVICE_BUILTIN*/ +struct cudaArray +{ + void *devPtr; + int devPtr32; + struct cudaChannelFormatDesc desc; + int width; + int height; + int size; //in bytes + unsigned dimensions; +}; + +#if !defined(__dv) +#if defined(__cplusplus) +#define __dv(v) \ + = v +#else /* __cplusplus */ +#define __dv(v) +#endif /* __cplusplus */ +#endif /* !__dv */ + +cudaError_t g_last_cudaError = cudaSuccess; + +extern stream_manager *g_stream_manager; + +void register_ptx_function( const char *name, function_info *impl ) +{ + // no longer need this +} + +#if defined __APPLE__ +# define __my_func__ __PRETTY_FUNCTION__ +#else +# if defined __cplusplus ? __GNUC_PREREQ (2, 6) : __GNUC_PREREQ (2, 4) +# define __my_func__ __PRETTY_FUNCTION__ +# else +# if defined __STDC_VERSION__ && __STDC_VERSION__ >= 199901L +# define __my_func__ __func__ +# else +# define __my_func__ ((__const char *) 0) +# endif +# endif +#endif + +struct _cuda_device_id { + _cuda_device_id(gpgpu_sim* gpu) {m_id = 0; m_next = NULL; m_gpgpu=gpu;} + struct _cuda_device_id *next() { return m_next; } + unsigned num_shader() const { return m_gpgpu->get_config().num_shader(); } + int num_devices() const { + if( m_next == NULL ) return 1; + else return 1 + m_next->num_devices(); + } + struct _cuda_device_id *get_device( unsigned n ) + { + assert( n < (unsigned)num_devices() ); + struct _cuda_device_id *p=this; + for(unsigned i=0; im_next; + return p; + } + const struct cudaDeviceProp *get_prop() const + { + return m_gpgpu->get_prop(); + } + unsigned get_id() const { return m_id; } + + gpgpu_sim *get_gpgpu() { return m_gpgpu; } +private: + unsigned m_id; + class gpgpu_sim *m_gpgpu; + struct _cuda_device_id *m_next; +}; + +struct CUctx_st { + CUctx_st( _cuda_device_id *gpu ) + { + m_gpu = gpu; + m_binary_info.cmem = 0; + m_binary_info.gmem = 0; + } + + _cuda_device_id *get_device() { return m_gpu; } + + void add_binary( symbol_table *symtab, unsigned fat_cubin_handle ) + { + m_code[fat_cubin_handle] = symtab; + m_last_fat_cubin_handle = fat_cubin_handle; + } + + void add_ptxinfo( const char *deviceFun, const struct gpgpu_ptx_sim_info &info ) + { + symbol *s = m_code[m_last_fat_cubin_handle]->lookup(deviceFun); + assert( s != NULL ); + function_info *f = s->get_pc(); + assert( f != NULL ); + f->set_kernel_info(info); + } + + void add_ptxinfo( const struct gpgpu_ptx_sim_info &info ) + { + m_binary_info = info; + } + + void register_function( unsigned fat_cubin_handle, const char *hostFun, const char *deviceFun ) + { + if( m_code.find(fat_cubin_handle) != m_code.end() ) { + symbol *s = m_code[fat_cubin_handle]->lookup(deviceFun); + if(s != NULL) { + function_info *f = s->get_pc(); + assert( f != NULL ); + m_kernel_lookup[hostFun] = f; + } + else { + printf("Warning: cannot find deviceFun %s\n", deviceFun); + m_kernel_lookup[hostFun] = NULL; + } + // assert( s != NULL ); + // function_info *f = s->get_pc(); + // assert( f != NULL ); + // m_kernel_lookup[hostFun] = f; + } else { + m_kernel_lookup[hostFun] = NULL; + } + } + + function_info *get_kernel(const char *hostFun) + { + std::map::iterator i=m_kernel_lookup.find(hostFun); + assert( i != m_kernel_lookup.end() ); + return i->second; + } + +private: + _cuda_device_id *m_gpu; // selected gpu + std::map m_code; // fat binary handle => global symbol table + unsigned m_last_fat_cubin_handle; + std::map m_kernel_lookup; // unique id (CUDA app function address) => kernel entry point + struct gpgpu_ptx_sim_info m_binary_info; + +}; + +class kernel_config { +public: + kernel_config( dim3 GridDim, dim3 BlockDim, size_t sharedMem, struct CUstream_st *stream ) + { + m_GridDim=GridDim; + m_BlockDim=BlockDim; + m_sharedMem=sharedMem; + m_stream = stream; + } + void set_arg( const void *arg, size_t size, size_t offset ) + { + m_args.push_front( gpgpu_ptx_sim_arg(arg,size,offset) ); + } + dim3 grid_dim() const { return m_GridDim; } + dim3 block_dim() const { return m_BlockDim; } + gpgpu_ptx_sim_arg_list_t get_args() { return m_args; } + struct CUstream_st *get_stream() { return m_stream; } + +private: + dim3 m_GridDim; + dim3 m_BlockDim; + size_t m_sharedMem; + struct CUstream_st *m_stream; + gpgpu_ptx_sim_arg_list_t m_args; +}; + +class _cuda_device_id *GPGPUSim_Init() +{ + static _cuda_device_id *the_device = NULL; + if( !the_device ) { + gpgpu_sim *the_gpu = gpgpu_ptx_sim_init_perf(); + + cudaDeviceProp *prop = (cudaDeviceProp *) calloc(sizeof(cudaDeviceProp),1); + snprintf(prop->name,256,"GPGPU-Sim_v%s", g_gpgpusim_version_string ); + prop->major = 5; + prop->minor = 2; + prop->totalGlobalMem = 0x80000000 /* 2 GB */; + prop->memPitch = 0; + prop->maxThreadsPerBlock = 512; + prop->maxThreadsDim[0] = 512; + prop->maxThreadsDim[1] = 512; + prop->maxThreadsDim[2] = 512; + prop->maxGridSize[0] = 0x40000000; + prop->maxGridSize[1] = 0x40000000; + prop->maxGridSize[2] = 0x40000000; + prop->totalConstMem = 0x40000000; + prop->textureAlignment = 0; + prop->sharedMemPerBlock = the_gpu->shared_mem_size(); + prop->regsPerBlock = the_gpu->num_registers_per_core(); + prop->warpSize = the_gpu->wrp_size(); + prop->clockRate = the_gpu->shader_clock(); +#if (CUDART_VERSION >= 2010) + prop->multiProcessorCount = the_gpu->get_config().num_shader(); +#endif + the_gpu->set_prop(prop); + the_device = new _cuda_device_id(the_gpu); + } + start_sim_thread(1); + return the_device; +} + +static CUctx_st* GPGPUSim_Context() +{ + static CUctx_st *the_context = NULL; + if( the_context == NULL ) { + _cuda_device_id *the_gpu = GPGPUSim_Init(); + the_context = new CUctx_st(the_gpu); + } + return the_context; +} + + void ptxinfo_addinfo() +{ + if(!get_ptxinfo_kname()){ + /* This info is not per kernel (since CUDA 5.0 some info (e.g. gmem, and cmem) is added at the beginning for the whole binary ) */ + CUctx_st *context = GPGPUSim_Context(); + print_ptxinfo(); + context->add_ptxinfo(get_ptxinfo()); + clear_ptxinfo(); + return; + } + if( !strcmp("__cuda_dummy_entry__",get_ptxinfo_kname()) ) { + // this string produced by ptxas for empty ptx files (e.g., bandwidth test) + clear_ptxinfo(); + return; + } + CUctx_st *context = GPGPUSim_Context(); + print_ptxinfo(); + context->add_ptxinfo( get_ptxinfo_kname(), get_ptxinfo() ); + clear_ptxinfo(); +} + +void cuda_not_implemented( const char* func, unsigned line ) +{ + fflush(stdout); + fflush(stderr); + printf("\n\nGPGPU-Sim PTX: Execution error: CUDA API function \"%s()\" has not been implemented yet.\n" + " [$GPGPUSIM_ROOT/libcuda/%s around line %u]\n\n\n", + func,__FILE__, line ); + fflush(stdout); + abort(); +} + + +#define gpgpusim_ptx_error(msg, ...) gpgpusim_ptx_error_impl(__func__, __FILE__,__LINE__, msg, ##__VA_ARGS__) +#define gpgpusim_ptx_assert(cond,msg, ...) gpgpusim_ptx_assert_impl((cond),__func__, __FILE__,__LINE__, msg, ##__VA_ARGS__) + +void gpgpusim_ptx_error_impl( const char *func, const char *file, unsigned line, const char *msg, ... ) +{ + va_list ap; + char buf[1024]; + va_start(ap,msg); + vsnprintf(buf,1024,msg,ap); + va_end(ap); + + printf("GPGPU-Sim CUDA API: %s\n", buf); + printf(" [%s:%u : %s]\n", file, line, func ); + abort(); +} + +void gpgpusim_ptx_assert_impl( int test_value, const char *func, const char *file, unsigned line, const char *msg, ... ) +{ + va_list ap; + char buf[1024]; + va_start(ap,msg); + vsnprintf(buf,1024,msg,ap); + va_end(ap); + + if ( test_value == 0 ) + gpgpusim_ptx_error_impl(func, file, line, msg); +} + + +typedef std::map event_tracker_t; + +int CUevent_st::m_next_event_uid; +event_tracker_t g_timer_events; +int g_active_device = 0; //active gpu that runs the code +std::list g_cuda_launch_stack; + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +extern "C" { + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ +cudaError_t cudaPeekAtLastError(void) +{ + return g_last_cudaError; +} + +__host__ cudaError_t CUDARTAPI cudaMalloc(void **devPtr, size_t size) +{ + CUctx_st* context = GPGPUSim_Context(); + *devPtr = context->get_device()->get_gpgpu()->gpu_malloc(size); + if(g_debug_execution >= 3) + printf("GPGPU-Sim PTX: cudaMallocing %zu bytes starting at 0x%llx..\n",size, (unsigned long long) *devPtr); + if ( *devPtr ) { + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorMemoryAllocation; + } +} + +__host__ cudaError_t CUDARTAPI cudaMallocHost(void **ptr, size_t size) +{ + GPGPUSim_Context(); + *ptr = malloc(size); + if ( *ptr ) { + //track pinned memory size allocated in the host so that same amount of memory is also allocated in GPU. + pinned_memory_size[*ptr]=size; + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorMemoryAllocation; + } +} +__host__ cudaError_t CUDARTAPI cudaMallocPitch(void **devPtr, size_t *pitch, size_t width, size_t height) +{ + unsigned malloc_width_inbytes = width; + printf("GPGPU-Sim PTX: cudaMallocPitch (width = %d)\n", malloc_width_inbytes); + CUctx_st* ctx = GPGPUSim_Context(); + *devPtr = ctx->get_device()->get_gpgpu()->gpu_malloc(malloc_width_inbytes*height); + pitch[0] = malloc_width_inbytes; + if ( *devPtr ) { + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorMemoryAllocation; + } +} + +__host__ cudaError_t CUDARTAPI cudaMallocArray(struct cudaArray **array, const struct cudaChannelFormatDesc *desc, size_t width, size_t height __dv(1)) +{ + unsigned size = width * height * ((desc->x + desc->y + desc->z + desc->w)/8); + CUctx_st* context = GPGPUSim_Context(); + (*array) = (struct cudaArray*) malloc(sizeof(struct cudaArray)); + (*array)->desc = *desc; + (*array)->width = width; + (*array)->height = height; + (*array)->size = size; + (*array)->dimensions = 2; + ((*array)->devPtr32)= (int) (long long)context->get_device()->get_gpgpu()->gpu_mallocarray(size); + printf("GPGPU-Sim PTX: cudaMallocArray: devPtr32 = %d\n", ((*array)->devPtr32)); + ((*array)->devPtr) = (void*) (long long) ((*array)->devPtr32); + if ( ((*array)->devPtr) ) { + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorMemoryAllocation; + } +} + +__host__ cudaError_t CUDARTAPI cudaFree(void *devPtr) +{ + // TODO... manage g_global_mem space? + return g_last_cudaError = cudaSuccess; +} +__host__ cudaError_t CUDARTAPI cudaFreeHost(void *ptr) +{ + free (ptr); // this will crash the system if called twice + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaFreeArray(struct cudaArray *array) +{ + // TODO... manage g_global_mem space? + return g_last_cudaError = cudaSuccess; +}; + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaMemcpy(void *dst, const void *src, size_t count, enum cudaMemcpyKind kind) +{ + //CUctx_st *context = GPGPUSim_Context(); + //gpgpu_t *gpu = context->get_device()->get_gpgpu(); + if(g_debug_execution >= 3) + printf("GPGPU-Sim PTX: cudaMemcpy(): devPtr = %p\n", dst); + if( kind == cudaMemcpyHostToDevice ) + g_stream_manager->push( stream_operation(src,(size_t)dst,count,0) ); + else if( kind == cudaMemcpyDeviceToHost ) + g_stream_manager->push( stream_operation((size_t)src,dst,count,0) ); + else if( kind == cudaMemcpyDeviceToDevice ) + g_stream_manager->push( stream_operation((size_t)src,(size_t)dst,count,0) ); + else if ( kind == cudaMemcpyDefault ) { + if ((size_t)src >= GLOBAL_HEAP_START) { + if ((size_t)dst >= GLOBAL_HEAP_START) + g_stream_manager->push( stream_operation((size_t)src,(size_t)dst,count,0) ); // device to device + else + g_stream_manager->push( stream_operation((size_t)src,dst,count,0) ); // device to host + } + else { + if ((size_t)dst >= GLOBAL_HEAP_START) + g_stream_manager->push( stream_operation(src,(size_t)dst,count,0) ); + else { + printf("GPGPU-Sim PTX: cudaMemcpy - ERROR : unsupported transfer: host to host\n"); + abort(); + } + } + } + else { + printf("GPGPU-Sim PTX: cudaMemcpy - ERROR : unsupported cudaMemcpyKind\n"); + abort(); + } + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaMemcpyToArray(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t count, enum cudaMemcpyKind kind) +{ + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + size_t size = count; + printf("GPGPU-Sim PTX: cudaMemcpyToArray\n"); + if( kind == cudaMemcpyHostToDevice ) + gpu->memcpy_to_gpu( (size_t)(dst->devPtr), src, size); + else if( kind == cudaMemcpyDeviceToHost ) + gpu->memcpy_from_gpu( dst->devPtr, (size_t)src, size); + else if( kind == cudaMemcpyDeviceToDevice ) + gpu->memcpy_gpu_to_gpu( (size_t)(dst->devPtr), (size_t)src, size); + else { + printf("GPGPU-Sim PTX: cudaMemcpyToArray - ERROR : unsupported cudaMemcpyKind\n"); + abort(); + } + dst->devPtr32 = (unsigned) (size_t)(dst->devPtr); + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpyFromArray(void *dst, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t count, enum cudaMemcpyKind kind) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpyArrayToArray(struct cudaArray *dst, size_t wOffsetDst, size_t hOffsetDst, const struct cudaArray *src, size_t wOffsetSrc, size_t hOffsetSrc, size_t count, enum cudaMemcpyKind kind __dv(cudaMemcpyDeviceToDevice)) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpy2D(void *dst, size_t dpitch, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind) +{ + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + size_t size = spitch*height; + gpgpusim_ptx_assert( (dpitch==spitch), "different src and dst pitch not supported yet" ); + if( kind == cudaMemcpyHostToDevice ) + gpu->memcpy_to_gpu( (size_t)dst, src, size ); + else if( kind == cudaMemcpyDeviceToHost ) + gpu->memcpy_from_gpu( dst, (size_t)src, size ); + else if( kind == cudaMemcpyDeviceToDevice ) + gpu->memcpy_gpu_to_gpu( (size_t)dst, (size_t)src, size); + else { + printf("GPGPU-Sim PTX: cudaMemcpy2D - ERROR : unsupported cudaMemcpyKind\n"); + abort(); + } + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpy2DToArray(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind) +{ + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + size_t size = spitch*height; + size_t channel_size = dst->desc.w+dst->desc.x+dst->desc.y+dst->desc.z; + gpgpusim_ptx_assert( ((channel_size%8) == 0), "none byte multiple destination channel size not supported (sz=%u)", channel_size ); + unsigned elem_size = channel_size/8; + gpgpusim_ptx_assert( (dst->dimensions==2), "copy to none 2D array not supported" ); + gpgpusim_ptx_assert( (wOffset==0), "non-zero wOffset not yet supported" ); + gpgpusim_ptx_assert( (hOffset==0), "non-zero hOffset not yet supported" ); + gpgpusim_ptx_assert( (dst->height == (int)height), "partial copy not supported" ); + gpgpusim_ptx_assert( (elem_size*dst->width == width), "partial copy not supported" ); + gpgpusim_ptx_assert( (spitch == width), "spitch != width not supported" ); + if( kind == cudaMemcpyHostToDevice ) + gpu->memcpy_to_gpu( (size_t)(dst->devPtr), src, size); + else if( kind == cudaMemcpyDeviceToHost ) + gpu->memcpy_from_gpu( dst->devPtr, (size_t)src, size); + else if( kind == cudaMemcpyDeviceToDevice ) + gpu->memcpy_gpu_to_gpu( (size_t)dst->devPtr, (size_t)src, size); + else { + printf("GPGPU-Sim PTX: cudaMemcpy2D - ERROR : unsupported cudaMemcpyKind\n"); + abort(); + } + dst->devPtr32 = (unsigned) (size_t)(dst->devPtr); + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpy2DFromArray(void *dst, size_t dpitch, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t width, size_t height, enum cudaMemcpyKind kind) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpy2DArrayToArray(struct cudaArray *dst, size_t wOffsetDst, size_t hOffsetDst, const struct cudaArray *src, size_t wOffsetSrc, size_t hOffsetSrc, size_t width, size_t height, enum cudaMemcpyKind kind __dv(cudaMemcpyDeviceToDevice)) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpyToSymbol(const char *symbol, const void *src, size_t count, size_t offset __dv(0), enum cudaMemcpyKind kind __dv(cudaMemcpyHostToDevice)) +{ + //CUctx_st *context = GPGPUSim_Context(); + assert(kind == cudaMemcpyHostToDevice); + printf("GPGPU-Sim PTX: cudaMemcpyToSymbol: symbol = %p\n", symbol); + //stream_operation( const char *symbol, const void *src, size_t count, size_t offset ) + g_stream_manager->push( stream_operation(src,symbol,count,offset,0) ); + //gpgpu_ptx_sim_memcpy_symbol(symbol,src,count,offset,1,context->get_device()->get_gpgpu()); + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpyFromSymbol(void *dst, const char *symbol, size_t count, size_t offset __dv(0), enum cudaMemcpyKind kind __dv(cudaMemcpyDeviceToHost)) +{ + //CUctx_st *context = GPGPUSim_Context(); + assert(kind == cudaMemcpyDeviceToHost); + printf("GPGPU-Sim PTX: cudaMemcpyFromSymbol: symbol = %p\n", symbol); + g_stream_manager->push( stream_operation(symbol,dst,count,offset,0) ); + //gpgpu_ptx_sim_memcpy_symbol(symbol,dst,count,offset,0,context->get_device()->get_gpgpu()); + return g_last_cudaError = cudaSuccess; +} + + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaMemcpyAsync(void *dst, const void *src, size_t count, enum cudaMemcpyKind kind, cudaStream_t stream) +{ + struct CUstream_st *s = (struct CUstream_st *)stream; + switch( kind ) { + case cudaMemcpyHostToDevice: g_stream_manager->push( stream_operation(src,(size_t)dst,count,s) ); break; + case cudaMemcpyDeviceToHost: g_stream_manager->push( stream_operation((size_t)src,dst,count,s) ); break; + case cudaMemcpyDeviceToDevice: g_stream_manager->push( stream_operation((size_t)src,(size_t)dst,count,s) ); break; + default: + abort(); + } + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpyToArrayAsync(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t count, enum cudaMemcpyKind kind, cudaStream_t stream) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpyFromArrayAsync(void *dst, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t count, enum cudaMemcpyKind kind, cudaStream_t stream) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpy2DAsync(void *dst, size_t dpitch, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind, cudaStream_t stream) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpy2DToArrayAsync(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind, cudaStream_t stream) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaMemcpy2DFromArrayAsync(void *dst, size_t dpitch, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t width, size_t height, enum cudaMemcpyKind kind, cudaStream_t stream) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaMemset(void *mem, int c, size_t count) +{ + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + gpu->gpu_memset((size_t)mem, c, count); + return g_last_cudaError = cudaSuccess; +} + +//memset operation is done but i think its not async? +__host__ cudaError_t CUDARTAPI cudaMemsetAsync(void *mem, int c, size_t count, cudaStream_t stream=0) +{ + printf("GPGPU-Sim PTX: WARNING: Asynchronous memset not supported (%s)\n", __my_func__); + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + gpu->gpu_memset((size_t)mem, c, count); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaMemset2D(void *mem, size_t pitch, int c, size_t width, size_t height) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaGetSymbolAddress(void **devPtr, const char *symbol) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + +__host__ cudaError_t CUDARTAPI cudaGetSymbolSize(size_t *size, const char *symbol) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ +__host__ cudaError_t CUDARTAPI cudaGetDeviceCount(int *count) +{ + _cuda_device_id *dev = GPGPUSim_Init(); + *count = dev->num_devices(); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaGetDeviceProperties(struct cudaDeviceProp *prop, int device) +{ + _cuda_device_id *dev = GPGPUSim_Init(); + if (device <= dev->num_devices() ) { + *prop= *dev->get_prop(); + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorInvalidDevice; + } +} + +#if (CUDART_VERSION > 5000) +__host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDeviceAttr attr, int device) +{ + const struct cudaDeviceProp *prop; + _cuda_device_id *dev = GPGPUSim_Init(); + if (device <= dev->num_devices() ) { + prop = dev->get_prop(); + switch (attr) { + case 5: + *value= prop->maxGridSize[0]; + break; + case 6: + *value= prop->maxGridSize[1]; + break; + case 7: + *value= prop->maxGridSize[2]; + break; + case 10: + *value= prop->warpSize; + break; + case 12: + *value= prop->regsPerBlock; + break; + case 14: + *value= prop->textureAlignment ; + break; + case 16: + *value= prop->multiProcessorCount ; + break; + case 39: + *value= dev->get_gpgpu()->threads_per_core(); + break; + case 75: + *value= 8 ; + break; + case 76: + *value= 3 ; + break; + case 78: + *value= 0 ; //TODO: as of now, we dont support stream priorities. + break; + default: + printf("ERROR: implement the attribute numbered %d \n",attr); + abort(); + } + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorInvalidDevice; + } +} +#endif + +__host__ cudaError_t CUDARTAPI cudaChooseDevice(int *device, const struct cudaDeviceProp *prop) +{ + _cuda_device_id *dev = GPGPUSim_Init(); + *device = dev->get_id(); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaSetDevice(int device) +{ + //set the active device to run cuda + if ( device <= GPGPUSim_Init()->num_devices() ) { + g_active_device = device; + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorInvalidDevice; + } +} + +__host__ cudaError_t CUDARTAPI cudaGetDevice(int *device) +{ + *device = g_active_device; + return g_last_cudaError = cudaSuccess; +} + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaBindTexture(size_t *offset, + const struct textureReference *texref, + const void *devPtr, + const struct cudaChannelFormatDesc *desc, + size_t size __dv(UINT_MAX)) +{ + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + printf("GPGPU-Sim PTX: in cudaBindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); + struct cudaArray *array; + array = (struct cudaArray*) malloc(sizeof(struct cudaArray)); + array->desc = *desc; + array->size = size; + array->width = size; + array->height = 1; + array->dimensions = 1; + array->devPtr = (void*)devPtr; + array->devPtr32 = (int)(long long)devPtr; + offset = 0; + printf("GPGPU-Sim PTX: size = %zu\n", size); + printf("GPGPU-Sim PTX: texref = %p, array = %p\n", texref, array); + printf("GPGPU-Sim PTX: devPtr32 = %x\n", array->devPtr32); + printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); + printf("GPGPU-Sim PTX: ChannelFormatDesc: x=%d, y=%d, z=%d, w=%d\n", desc->x, desc->y, desc->z, desc->w); + printf("GPGPU-Sim PTX: Texture Normalized? = %d\n", texref->normalized); + gpu->gpgpu_ptx_sim_bindTextureToArray(texref, array); + devPtr = (void*)(long long)array->devPtr32; + printf("GPGPU-Sim PTX: devPtr = %p\n", devPtr); + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureReference *texref, const struct cudaArray *array, const struct cudaChannelFormatDesc *desc) +{ + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + printf("GPGPU-Sim PTX: in cudaBindTextureToArray: %p %p\n", texref, array); + printf("GPGPU-Sim PTX: devPtr32 = %x\n", array->devPtr32); + printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); + printf("GPGPU-Sim PTX: Texture Normalized? = %d\n", texref->normalized); + gpu->gpgpu_ptx_sim_bindTextureToArray(texref, array); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) +{ + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaGetTextureAlignmentOffset(size_t *offset, const struct textureReference *texref) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + +__host__ cudaError_t CUDARTAPI cudaGetTextureReference(const struct textureReference **texref, const char *symbol) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + +__host__ cudaError_t CUDARTAPI cudaGetChannelDesc(struct cudaChannelFormatDesc *desc, const struct cudaArray *array) +{ + *desc = array->desc; + return g_last_cudaError = cudaSuccess; +} + + +__host__ struct cudaChannelFormatDesc CUDARTAPI cudaCreateChannelDesc(int x, int y, int z, int w, enum cudaChannelFormatKind f) +{ + struct cudaChannelFormatDesc dummy; + dummy.x = x; + dummy.y = y; + dummy.z = z; + dummy.w = w; + dummy.f = f; + return dummy; +} + +__host__ cudaError_t CUDARTAPI cudaGetLastError(void) +{ + return g_last_cudaError; +} + +__host__ const char* CUDARTAPI cudaGetErrorString(cudaError_t error) +{ + if( g_last_cudaError == cudaSuccess ) + return "no error"; + char buf[1024]; + snprintf(buf,1024,"<>", g_last_cudaError); + return strdup(buf); +} + +__host__ cudaError_t CUDARTAPI cudaConfigureCall(dim3 gridDim, dim3 blockDim, size_t sharedMem, cudaStream_t stream) +{ + struct CUstream_st *s = (struct CUstream_st *)stream; + g_cuda_launch_stack.push_back( kernel_config(gridDim,blockDim,sharedMem,s) ); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaSetupArgument(const void *arg, size_t size, size_t offset) +{ + gpgpusim_ptx_assert( !g_cuda_launch_stack.empty(), "empty launch stack" ); + kernel_config &config = g_cuda_launch_stack.back(); + config.set_arg(arg,size,offset); + + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaLaunch( const char *hostFun ) +{ + CUctx_st* context = GPGPUSim_Context(); + char *mode = getenv("PTX_SIM_MODE_FUNC"); + if( mode ) + sscanf(mode,"%u", &g_ptx_sim_mode); + gpgpusim_ptx_assert( !g_cuda_launch_stack.empty(), "empty launch stack" ); + kernel_config config = g_cuda_launch_stack.back(); + struct CUstream_st *stream = config.get_stream(); + printf("\nGPGPU-Sim PTX: cudaLaunch for 0x%p (mode=%s) on stream %u\n", hostFun, + g_ptx_sim_mode?"functional simulation":"performance simulation", stream?stream->get_uid():0 ); + kernel_info_t *grid = gpgpu_cuda_ptx_sim_init_grid(hostFun,config.get_args(),config.grid_dim(),config.block_dim(),context); + //do dynamic PDOM analysis for performance simulation scenario + std::string kname = grid->name(); + function_info *kernel_func_info = grid->entry(); + if (kernel_func_info->is_pdom_set()) { + printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", kname.c_str() ); + } else { + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", kname.c_str() ); + kernel_func_info->do_pdom(); + kernel_func_info->set_pdom(); + } + dim3 gridDim = config.grid_dim(); + dim3 blockDim = config.block_dim(); + printf("GPGPU-Sim PTX: pushing kernel \'%s\' to stream %u, gridDim= (%u,%u,%u) blockDim = (%u,%u,%u) \n", + kname.c_str(), stream?stream->get_uid():0, gridDim.x,gridDim.y,gridDim.z,blockDim.x,blockDim.y,blockDim.z ); + stream_operation op(grid,g_ptx_sim_mode,stream); + g_stream_manager->push(op); + g_cuda_launch_stack.pop_back(); + return g_last_cudaError = cudaSuccess; +} + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaStreamCreate(cudaStream_t *stream) +{ + printf("GPGPU-Sim PTX: cudaStreamCreate\n"); +#if (CUDART_VERSION >= 3000) + *stream = new struct CUstream_st(); + g_stream_manager->add_stream(*stream); +#else + *stream = 0; + printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); +#endif + return g_last_cudaError = cudaSuccess; +} + +//TODO: introduce priorities +__host__ cudaError_t CUDARTAPI cudaStreamCreateWithPriority(cudaStream_t *stream, unsigned int flags, int priority) { + return cudaStreamCreate(stream); +} + +__host__ cudaError_t CUDARTAPI cudaDeviceGetStreamPriorityRange(int* leastPriority, int* greatestPriority) { + return cudaSuccess; +} + +__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *pStream, unsigned int flags) { + return cudaStreamCreate(pStream); +} + +__host__ cudaError_t CUDARTAPI cudaStreamDestroy(cudaStream_t stream) +{ +#if (CUDART_VERSION >= 3000) + g_stream_manager->destroy_stream(stream); +#endif + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaStreamSynchronize(cudaStream_t stream) +{ +#if (CUDART_VERSION >= 3000) + if( stream == NULL ) + synchronize(); + return g_last_cudaError = cudaSuccess; + stream->synchronize(); +#else + printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); +#endif + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) +{ +#if (CUDART_VERSION >= 3000) + if( stream == NULL ) + return g_last_cudaError = cudaErrorInvalidResourceHandle; + return g_last_cudaError = stream->empty()?cudaSuccess:cudaErrorNotReady; +#else + printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); + return g_last_cudaError = cudaSuccess; // it is always success because all cuda calls are synchronous +#endif +} + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaEventCreate(cudaEvent_t *event) +{ + CUevent_st *e = new CUevent_st(false); + g_timer_events[e->get_uid()] = e; +#if CUDART_VERSION >= 3000 + *event = e; +#else + *event = e->get_uid(); +#endif + return g_last_cudaError = cudaSuccess; +} + +CUevent_st *get_event(cudaEvent_t event) +{ + unsigned event_uid; +#if CUDART_VERSION >= 3000 + event_uid = event->get_uid(); +#else + event_uid = event; +#endif + event_tracker_t::iterator e = g_timer_events.find(event_uid); + if( e == g_timer_events.end() ) + return NULL; + return e->second; +} + +__host__ cudaError_t CUDARTAPI cudaEventRecord(cudaEvent_t event, cudaStream_t stream) +{ + CUevent_st *e = get_event(event); + if( !e ) return g_last_cudaError = cudaErrorUnknown; + struct CUstream_st *s = (struct CUstream_st *)stream; + stream_operation op(e,s); + g_stream_manager->push(op); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaEventQuery(cudaEvent_t event) +{ + CUevent_st *e = get_event(event); + if( e == NULL ) { + return g_last_cudaError = cudaErrorInvalidValue; + } else if( e->done() ) { + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorNotReady; + } +} + +__host__ cudaError_t CUDARTAPI cudaEventSynchronize(cudaEvent_t event) +{ + printf("GPGPU-Sim API: cudaEventSynchronize ** waiting for event\n"); + fflush(stdout); + CUevent_st *e = (CUevent_st*) event; + while( !e->done() ) + ; + printf("GPGPU-Sim API: cudaEventSynchronize ** event detected\n"); + fflush(stdout); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaEventDestroy(cudaEvent_t event) +{ + CUevent_st *e = get_event(event); + unsigned event_uid = e->get_uid(); + event_tracker_t::iterator pe = g_timer_events.find(event_uid); + if( pe == g_timer_events.end() ) + return g_last_cudaError = cudaErrorInvalidValue; + g_timer_events.erase(pe); + return g_last_cudaError = cudaSuccess; +} + + +__host__ cudaError_t CUDARTAPI cudaEventElapsedTime(float *ms, cudaEvent_t start, cudaEvent_t end) +{ + time_t elapsed_time; + CUevent_st *s = get_event(start); + CUevent_st *e = get_event(end); + if( s==NULL || e==NULL ) + return g_last_cudaError = cudaErrorUnknown; + elapsed_time = e->clock() - s->clock(); + *ms = 1000*elapsed_time; + return g_last_cudaError = cudaSuccess; +} + + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +__host__ cudaError_t CUDARTAPI cudaThreadExit(void) +{ + exit_simulation(); + return g_last_cudaError = cudaSuccess; +} + +__host__ cudaError_t CUDARTAPI cudaThreadSynchronize(void) +{ + //Called on host side + synchronize(); + return g_last_cudaError = cudaSuccess; +}; + +int CUDARTAPI __cudaSynchronizeThreads(void**, void*) +{ + return cudaThreadExit(); +} + + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +#if (CUDART_VERSION >= 3010) + +typedef struct CUuuid_st { /**< CUDA definition of UUID */ + char bytes[16]; +} CUuuid; + +/** + * CUDA UUID types + */ +// typedef __device_builtin__ struct CUuuid_st cudaUUID_t; + +__host__ cudaError_t CUDARTAPI cudaGetExportTable(const void **ppExportTable, const cudaUUID_t *pExportTableId) +{ + printf("cudaGetExportTable: UUID = "); + for (int s = 0; s < 16; s++) { + printf("%#2x ", (unsigned char) (pExportTableId->bytes[s])); + } + printf("\n"); + return g_last_cudaError = cudaSuccess; +} + +#endif + + +/******************************************************************************* + * * + * * + * * + *******************************************************************************/ + +//#include "../../cuobjdump_to_ptxplus/cuobjdump_parser.h" + +enum cuobjdumpSectionType { + PTXSECTION=0, + ELFSECTION +}; + + +class cuobjdumpSection { +public: + //Constructor + cuobjdumpSection() { + arch = 0; + identifier = ""; + } + virtual ~cuobjdumpSection() {} + unsigned getArch() {return arch;} + void setArch(unsigned a) {arch = a;} + std::string getIdentifier() {return identifier;} + void setIdentifier(std::string i) {identifier = i;} + virtual void print(){std::cout << "cuobjdump Section: unknown type" << std::endl;} +private: + unsigned arch; + std::string identifier; +}; + +class cuobjdumpELFSection : public cuobjdumpSection +{ +public: + cuobjdumpELFSection() {} + virtual ~cuobjdumpELFSection() { + elffilename = ""; + sassfilename = ""; + } + std::string getELFfilename() {return elffilename;} + void setELFfilename(std::string f) {elffilename = f;} + std::string getSASSfilename() {return sassfilename;} + void setSASSfilename(std::string f) {sassfilename = f;} + virtual void print() { + std::cout << "ELF Section:" << std::endl; + std::cout << "arch: sm_" << getArch() << std::endl; + std::cout << "identifier: " << getIdentifier() << std::endl; + std::cout << "elf filename: " << getELFfilename() << std::endl; + std::cout << "sass filename: " << getSASSfilename() << std::endl; + std::cout << std::endl; + } +private: + std::string elffilename; + std::string sassfilename; +}; + +class cuobjdumpPTXSection : public cuobjdumpSection +{ +public: + cuobjdumpPTXSection(){ + ptxfilename = ""; + } + std::string getPTXfilename() {return ptxfilename;} + void setPTXfilename(std::string f) {ptxfilename = f;} + virtual void print() { + std::cout << "PTX Section:" << std::endl; + std::cout << "arch: sm_" << getArch() << std::endl; + std::cout << "identifier: " << getIdentifier() << std::endl; + std::cout << "ptx filename: " << getPTXfilename() << std::endl; + std::cout << std::endl; + } +private: + std::string ptxfilename; +}; + +std::list cuobjdumpSectionList; +std::list libSectionList; + +// sectiontype: 0 for ptx, 1 for elf +void addCuobjdumpSection(int sectiontype){ + if (sectiontype) + cuobjdumpSectionList.push_front(new cuobjdumpELFSection()); + else + cuobjdumpSectionList.push_front(new cuobjdumpPTXSection()); + printf("## Adding new section %s\n", sectiontype?"ELF":"PTX"); +} + +void setCuobjdumparch(const char* arch){ + unsigned archnum; + sscanf(arch, "sm_%u", &archnum); + assert (archnum && "cannot have sm_0"); + printf("Adding arch: %s\n", arch); + cuobjdumpSectionList.front()->setArch(archnum); +} + +void setCuobjdumpidentifier(const char* identifier){ + printf("Adding identifier: %s\n", identifier); + cuobjdumpSectionList.front()->setIdentifier(identifier); +} + +void setCuobjdumpptxfilename(const char* filename){ + printf("Adding ptx filename: %s\n", filename); + cuobjdumpSection* x = cuobjdumpSectionList.front(); + if (dynamic_cast(x) == NULL){ + assert (0 && "You shouldn't be trying to add a ptxfilename to an elf section"); + } + (dynamic_cast(x))->setPTXfilename(filename); +} + +void setCuobjdumpelffilename(const char* filename){ + if (dynamic_cast(cuobjdumpSectionList.front()) == NULL){ + assert (0 && "You shouldn't be trying to add a elffilename to an ptx section"); + } + (dynamic_cast(cuobjdumpSectionList.front()))->setELFfilename(filename); +} + +void setCuobjdumpsassfilename(const char* filename){ + if (dynamic_cast(cuobjdumpSectionList.front()) == NULL){ + assert (0 && "You shouldn't be trying to add a sassfilename to an ptx section"); + } + (dynamic_cast(cuobjdumpSectionList.front()))->setSASSfilename(filename); +} +extern int cuobjdump_parse(); +extern FILE *cuobjdump_in; + +//! Return the executable file of the process containing the PTX/SASS code +//! +//! This Function returns the executable file ran by the process. This +//! executable is supposed to contain the PTX/SASS code. It provides workaround +//! for processes running on valgrind by dereferencing /proc//exe within the +//! GPGPU-Sim process before calling cuobjdump to extract PTX/SASS. This is +//! needed because valgrind uses x86 emulation to detect memory leak. Other +//! processes (e.g. cuobjdump) reading /proc//exe will see the emulator +//! executable instead of the application binary. +//! +std::string get_app_binary(){ + char self_exe_path[1025]; +#ifdef __APPLE__ + uint32_t size = sizeof(self_exe_path); + if( _NSGetExecutablePath(self_exe_path,&size) != 0 ) { + printf("GPGPU-Sim ** ERROR: _NSGetExecutablePath input buffer too small\n"); + exit(1); + } +#else + std::stringstream exec_link; + exec_link << "/proc/self/exe"; + + ssize_t path_length = readlink(exec_link.str().c_str(), self_exe_path, 1024); + assert(path_length != -1); + self_exe_path[path_length] = '\0'; +#endif + + printf("self exe links to: %s\n", self_exe_path); + return self_exe_path; +} + +//above func gives abs path whereas this give just the name of application. +char* get_app_binary_name(std::string abs_path){ + char *self_exe_path; +#ifdef __APPLE__ + //TODO: get apple device and check the result. + printf("WARNING: not tested for Apple-mac devices \n"); + abort(); +#else + char* buf = strdup(abs_path.c_str()); + char *token = strtok(buf, "/"); + while(token !=NULL){ + self_exe_path = token; + token = strtok(NULL,"/"); + } +#endif + self_exe_path = strtok(self_exe_path, "."); + printf("self exe links to: %s\n", self_exe_path); + return self_exe_path; +} + +//! Call cuobjdump to extract everything (-elf -sass -ptx) +/*! + * This Function extract the whole PTX (for all the files) using cuobjdump + * to _cuobjdump_complete_output_XXXXXX then runs a parser to chop it up with each binary in + * its own file + * It is also responsible for extracting the libraries linked to the binary if the option is + * enabled + * */ +void extract_code_using_cuobjdump(){ + CUctx_st *context = GPGPUSim_Context(); + unsigned forced_max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); + + //prevent the dumping by cuobjdump everytime we execute the code! + const char *override_cuobjdump = getenv("CUOBJDUMP_SIM_FILE"); + char command[1000], ptx_file[1000]; + std::string app_binary = get_app_binary(); + //Running cuobjdump using dynamic link to current process + snprintf(command,1000,"md5sum %s ", app_binary.c_str()); + printf("Running md5sum using \"%s\"\n", command); + system(command); + // Running cuobjdump using dynamic link to current process + // Needs the option '-all' to extract PTX from CDP-enabled binary + extern bool g_cdp_enabled; + + //dump ptx for all individial ptx files into sepearte files which is later used by ptxas. + int result=0; +#if (CUDART_VERSION >= 6000) + char fname2[1024]; + snprintf(fname2,1024,"_cuobjdump_list_ptx_XXXXXX"); + int fd2=mkstemp(fname2); + close(fd2); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -lptx -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname2); + result = system(command); + if( result != 0 ) { + printf("WARNING: Failed to execute cuobjdump to get list of ptx files \n"); + exit(0); + } else { + /* + as we got list of ptx files, we need to extract one by one into seperate files so that ptxas can understand it. + In this way, the duplicate definitions in a single embedded file can be prevented. + No of lines in the file is equal to no of ptx fileis available. + */ + FILE *fp = fopen(fname2,"r"); + if (fp==NULL) { + printf("WARNING: cuobjdump file error! Could not open file %s \n", fname2); + exit(0); + } else { + for (char c = getc(fp); c != EOF; c = getc(fp)) + if (c == '\n') + no_of_ptx = no_of_ptx + 1; + fclose(fp); + } + if(no_of_ptx==0){ + printf("WARNING: Number of ptx in the executable file are 0. One of the reasons might be\n"); + printf("\t1. CDP is enabled\n"); + printf("\t2. cuobjdump -lptx doesnt recognize sm_%u\n",forced_max_capability); + printf("\t3. the application was not compiled iwth nvcc flag sm_%u\n",forced_max_capability); + } + } + if(!g_cdp_enabled) { + //based on the list above, dump ptx files individually. Format of dumped ptx file is prog_name.unique_no.sm_<>.ptx + for (int index=1; index<= no_of_ptx; index++){ + snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", get_app_binary_name(app_binary), index, forced_max_capability); + printf("Extracting specific PTX file named %s \n",ptx_file); + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -arch=sm_%u -xptx %s %s", forced_max_capability, ptx_file, app_binary.c_str()); + if (system(command)!=0) { + printf("ERROR: command: %s failed \n",command); + exit(0); + } + } + } +#endif + //TODO: redundant to dump twice. how can it be prevented? + //dump only for specific arch + char fname[1024]; + if ((override_cuobjdump == NULL) || (strlen(override_cuobjdump)==0)) { + snprintf(fname,1024,"_cuobjdump_complete_output_XXXXXX"); + int fd=mkstemp(fname); + close(fd); + if(!g_cdp_enabled) + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass %s > %s", app_binary.c_str(), fname); + else + snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); + bool parse_output = true; + result = system(command); + if(result) { + if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support() && (result == 65280)) { + // Some CUDA application may exclusively use kernels provided by CUDA + // libraries (e.g. CUBLAS). Skipping cuobjdump extraction from the + // executable for this case. + // 65280 is the return code from cuobjdump denoting the specific error (tested on CUDA 4.0/4.1/4.2) + printf("WARNING: Failed to execute: %s\n", command); + printf(" Executable binary does not contain any GPU kernel.\n"); + parse_output = false; + } else { + printf("ERROR: Failed to execute: %s\n", command); + exit(1); + } + } + + if (parse_output) { + printf("Parsing file %s\n", fname); + cuobjdump_in = fopen(fname, "r"); + + cuobjdump_parse(); + fclose(cuobjdump_in); + printf("Done parsing!!!\n"); + } else { + printf("Parsing skipped for %s\n", fname); + } + + if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ + //Experimental library support + //Currently only for cufft + + std::stringstream cmd; + cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; + int result = system(cmd.str().c_str()); + if(result){ + std::cout << "Failed to execute: " << cmd.str() << std::endl; + exit(1); + } + std::ifstream libsf; + libsf.open("_tempfile_.txt"); + if(!libsf.is_open()) { + std::cout << "Failed to open: _tempfile_.txt" << std::endl; + exit(1); + } + + //Save the original section list + std::list tmpsl = cuobjdumpSectionList; + cuobjdumpSectionList.clear(); + + std::string line; + std::getline(libsf, line); + std::cout << "DOING: " << line << std::endl; + int cnt=1; + while(libsf.good()){ + std::stringstream libcodfn; + libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; + cmd.str(""); //resetting + cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; + cmd << line; + cmd << " > "; + cmd << libcodfn.str(); + std::cout << "Running cuobjdump on " << line << std::endl; + std::cout << "Using command: " << cmd.str() << std::endl; + result = system(cmd.str().c_str()); + if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} + std::cout << "Done" << std::endl; + + std::cout << "Trying to parse " << libcodfn.str() << std::endl; + cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); + cuobjdump_parse(); + fclose(cuobjdump_in); + std::getline(libsf, line); + } + libSectionList = cuobjdumpSectionList; + + //Restore the original section list + cuobjdumpSectionList = tmpsl; + } + } else { + printf("GPGPU-Sim PTX: overriding cuobjdump with '%s' (CUOBJDUMP_SIM_FILE is set)\n", override_cuobjdump); + snprintf(fname,1024, "%s",override_cuobjdump); + } +} + +//! Read file into char* +//TODO: convert this to C++ streams, will be way cleaner +char* readfile (const std::string filename){ + assert (filename != ""); + FILE* fp = fopen(filename.c_str(),"r"); + if (!fp) { + std::cout << "ERROR: Could not open file %s for reading\n" << filename << std::endl; + assert (0); + } + // finding size of the file + int filesize= 0; + fseek (fp , 0 , SEEK_END); + + filesize = ftell (fp); + fseek (fp, 0, SEEK_SET); + // allocate and copy the entire ptx + char* ret = (char*)malloc((filesize +1)* sizeof(char)); + fread(ret,1,filesize,fp); + ret[filesize]='\0'; + fclose(fp); + return ret; +} + +//! Function that helps debugging +void printSectionList(std::list sl) { + std::list::iterator iter; + for ( iter = sl.begin(); + iter != sl.end(); + iter++ + ){ + (*iter)->print(); + } +} + +//! Remove unecessary sm versions from the section list +std::list pruneSectionList(std::list cuobjdumpSectionList, CUctx_st *context) { + unsigned forced_max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); + + //For ptxplus, force the max capability to 19 if it's higher or unspecified(0) + if (context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus()){ + if ( (forced_max_capability == 0) || + (forced_max_capability >= 20)){ + printf("GPGPU-Sim: WARNING: Capability >= 20 are not supported in PTXPlus\n\tSetting forced_max_capability to 19\n"); + forced_max_capability = 19; + } + } + + std::list prunedList; + + //Find the highest capability (that is lower than the forced maximum) for each cubin file + //and set it in cuobjdumpSectionMap. Do this only for ptx sections + std::map cuobjdumpSectionMap; + int min_ptx_capability_found=0; + for ( std::list::iterator iter = cuobjdumpSectionList.begin(); + iter != cuobjdumpSectionList.end(); + iter++){ + unsigned capability = (*iter)->getArch(); + if(dynamic_cast(*iter) != NULL){ + if(capabilitygetIdentifier())==cuobjdumpSectionMap.end()) + || (cuobjdumpSectionMap[(*iter)->getIdentifier()] < capability)) + cuobjdumpSectionMap[(*iter)->getIdentifier()] = capability; + } + } + } + + //Throw away the sections with the lower capabilites and push those with the highest in + //the pruned list + for ( std::list::iterator iter = cuobjdumpSectionList.begin(); + iter != cuobjdumpSectionList.end(); + iter++){ + unsigned capability = (*iter)->getArch(); + if(capability == cuobjdumpSectionMap[(*iter)->getIdentifier()]){ + prunedList.push_back(*iter); + } else { + delete *iter; + } + } + if(prunedList.empty()){ + printf("Error: No PTX sections found with sm capability that is lower than current forced maximum capability \n minimum ptx capability found = %u, maximum forced ptx capability = %u \n User might want to change either the forced maximum capability from gpgpusim configuration or update the compilation to generate the required PTX version\n",min_ptx_capability_found,forced_max_capability); + abort(); + } + return prunedList; +} + +//! Merge all PTX sections that have a specific identifier into one file +std::list mergeMatchingSections(std::list cuobjdumpSectionList, std::string identifier){ + const char *ptxcode = ""; + std::list::iterator old_iter; + cuobjdumpPTXSection* old_ptxsection = NULL; + cuobjdumpPTXSection* ptxsection; + std::list mergedList; + + for ( std::list::iterator iter = cuobjdumpSectionList.begin(); + iter != cuobjdumpSectionList.end(); + iter++){ + if((ptxsection=dynamic_cast(*iter)) != NULL && + strcmp(ptxsection->getIdentifier().c_str(), identifier.c_str()) == 0){ + // Read and remove the last PTX section + if (old_ptxsection != NULL) { + ptxcode = readfile(old_ptxsection->getPTXfilename()); + // remove ptx file? + delete *old_iter; + } + + // Append all the PTX from the last PTX section into the current PTX section + // Add 50 to ptxcode to ignore the information regarding version/target/address_size + if (strlen(ptxcode) >= 50) { + FILE *ptxfile = fopen((ptxsection->getPTXfilename()).c_str(), "a"); + fprintf(ptxfile, "%s", ptxcode + 50); + fclose(ptxfile); + } + + old_iter = iter; + old_ptxsection = ptxsection; + } + // Store all non-PTX sections and PTX sections with non-matching identifiers + else { + mergedList.push_back(*iter); + } + } + + // Store the final PTX section + mergedList.push_back(*old_iter); + + return mergedList; +} + +//! Merge any PTX sections with matching identifiers +std::list mergeSections(std::list cuobjdumpSectionList){ + std::vector identifier; + cuobjdumpPTXSection* ptxsection; + + // Add all identifiers present in PTX sections to a vector + for ( std::list::iterator iter = cuobjdumpSectionList.begin(); + iter != cuobjdumpSectionList.end(); + iter++){ + if((ptxsection=dynamic_cast(*iter)) != NULL){ + std::string current_id = ptxsection->getIdentifier(); + + // If we haven't yet seen a given identifier, add it to the vector + if (std::find(identifier.begin(), identifier.end(), current_id) == identifier.end()) { + identifier.push_back(current_id); + } + } + } + + // Call mergeMatchingSections on all identifiers in the vector + for ( std::vector::iterator iter = identifier.begin(); + iter != identifier.end(); + iter++) { + cuobjdumpSectionList = mergeMatchingSections(cuobjdumpSectionList, *iter); + } + + return cuobjdumpSectionList; +} + + +//! Within the section list, find the ELF section corresponding to a given identifier +cuobjdumpELFSection* findELFSectionInList(std::list sectionlist, const std::string identifier){ + + std::list::iterator iter; + for ( iter = sectionlist.begin(); + iter != sectionlist.end(); + iter++ + ){ + cuobjdumpELFSection* elfsection; + if((elfsection=dynamic_cast(*iter)) != NULL){ + if(elfsection->getIdentifier() == identifier) + return elfsection; + } + } + return NULL; +} + +//! Find an ELF section in all the known lists +cuobjdumpELFSection* findELFSection(const std::string identifier){ + cuobjdumpELFSection* sec = findELFSectionInList(cuobjdumpSectionList, identifier); + if (sec!=NULL)return sec; + sec = findELFSectionInList(libSectionList, identifier); + if (sec!=NULL)return sec; + std::cout << "Could not find " << identifier << std::endl; + assert(0 && "Could not find the required ELF section"); + return NULL; +} + +//! Within the section list, find the PTX section corresponding to a given identifier +cuobjdumpPTXSection* findPTXSectionInList(std::list sectionlist, const std::string identifier){ + std::list::iterator iter; + for ( iter = sectionlist.begin(); + iter != sectionlist.end(); + iter++ + ){ + cuobjdumpPTXSection* ptxsection; + if((ptxsection=dynamic_cast(*iter)) != NULL){ + if(ptxsection->getIdentifier() == identifier) + return ptxsection; + else { + extern bool g_cdp_enabled; + if(g_cdp_enabled) { + printf("Warning: __cudaRegisterFatBinary needs %s, but find PTX section with %s\n", + identifier.c_str(), ptxsection->getIdentifier().c_str()); + return ptxsection; + } + } + } + } + return NULL; +} + +//! Find an PTX section in all the known lists +cuobjdumpPTXSection* findPTXSection(const std::string identifier){ + cuobjdumpPTXSection* sec = findPTXSectionInList(cuobjdumpSectionList, identifier); + if (sec!=NULL)return sec; + sec = findPTXSectionInList(libSectionList, identifier); + if (sec!=NULL)return sec; + std::cout << "Could not find " << identifier << std::endl; + assert(0 && "Could not find the required PTX section"); + return NULL; +} + + + +//! Extract the code using cuobjdump and remove unnecessary sections +void cuobjdumpInit(){ + CUctx_st *context = GPGPUSim_Context(); + extract_code_using_cuobjdump(); //extract all the output of cuobjdump to _cuobjdump_*.* + const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); + if (pre_load ==NULL || strlen(pre_load)==0){ + cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); + cuobjdumpSectionList = mergeSections(cuobjdumpSectionList); + } +} + +std::map fatbinmap; +std::mapfatbin_registered; +std::map name_symtab; + +//! Keep track of the association between filename and cubin handle +void cuobjdumpRegisterFatBinary(unsigned int handle, const char* filename){ + fatbinmap[handle] = filename; +} + +//! Either submit PTX for simulation or convert SASS to PTXPlus and submit it +void cuobjdumpParseBinary(unsigned int handle){ + + if(fatbin_registered[handle]) return; + fatbin_registered[handle] = true; + CUctx_st *context = GPGPUSim_Context(); + std::string fname = fatbinmap[handle]; + + if (name_symtab.find(fname) != name_symtab.end()) { + symbol_table *symtab = name_symtab[fname]; + context->add_binary(symtab, handle); + return; + } + + unsigned max_capability = 0; + for ( std::list::iterator iter = cuobjdumpSectionList.begin(); + iter != cuobjdumpSectionList.end(); + iter++){ + unsigned capability = (*iter)->getArch(); + if (capability > max_capability) max_capability = capability; + } + if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); + + cuobjdumpPTXSection* ptx = NULL; + const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); + if(pre_load==NULL || strlen(pre_load)==0) + ptx = findPTXSection(fname); + symbol_table *symtab; + char *ptxcode; + const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); + if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL or strlen(getenv("PTX_SIM_USE_PTX_FILE"))==0) { + ptxcode = readfile(ptx->getPTXfilename()); + } else { + printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); + ptxcode = readfile(override_ptx_name); + } + if(context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() ) { + cuobjdumpELFSection* elfsection = findELFSection(ptx->getIdentifier()); + assert (elfsection!= NULL); + char *ptxplus_str = gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus( + ptx->getPTXfilename(), + elfsection->getELFfilename(), + elfsection->getSASSfilename()); + symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxplus_str, handle); + printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); + context->add_binary(symtab, handle); + gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability ); + delete[] ptxplus_str; + } else { + symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxcode, handle); + //if CUOBJDUMP_SIM_FILE is not set, ptx is NULL. So comment below. + //printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); + context->add_binary(symtab, handle); + gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability ); + } + load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu()); + load_constants(symtab,STATIC_ALLOC_LIMIT,context->get_device()->get_gpgpu()); + name_symtab[fname] = symtab; + + //TODO: Remove temporarily files as per configurations +} + +void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) +{ +#if (CUDART_VERSION < 2010) + printf("GPGPU-Sim PTX: ERROR ** this version of GPGPU-Sim requires CUDA 2.1 or higher\n"); + exit(1); +#endif + CUctx_st *context = GPGPUSim_Context(); + static unsigned next_fat_bin_handle = 1; + if(context->get_device()->get_gpgpu()->get_config().use_cuobjdump()) { + // The following workaround has only been verified on 64-bit systems. + if (sizeof(void*) == 4) + printf("GPGPU-Sim PTX: FatBin file name extraction has not been tested on 32-bit system.\n"); + + #if (CUDART_VERSION <= 6000) + // FatBin handle from the .fatbin.c file (one of the intermediate files generated by NVCC) + typedef struct {int m; int v; const unsigned long long* d; char* f;} __fatDeviceText __attribute__ ((aligned (8))); + __fatDeviceText * fatDeviceText = (__fatDeviceText *) fatCubin; + + // Extract the source code file name that generate the given FatBin. + // - Obtains the pointer to the actual fatbin structure from the FatBin handle (fatCubin). + // - An integer inside the fatbin structure contains the relative offset to the source code file name. + // - This offset differs among different CUDA and GCC versions. + char * pfatbin = (char*) fatDeviceText->d; + int offset = *((int*)(pfatbin+48)); + char * filename = (pfatbin+16+offset); + #else + const char * filename = "default"; + #endif + // The extracted file name is associated with a fat_cubin_handle passed + // into cudaLaunch(). Inside cudaLaunch(), the associated file name is + // used to find the PTX/SASS section from cuobjdump, which contains the + // PTX/SASS code for the launched kernel function. + // This allows us to work around the fact that cuobjdump only outputs the + // file name associated with each section. + unsigned long long fat_cubin_handle = next_fat_bin_handle; + next_fat_bin_handle++; + printf("GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = %llu, filename=%s\n", fat_cubin_handle, filename); + /*! + * This function extracts all data from all files in first call + * then for next calls, only returns the appropriate number + */ + assert(fat_cubin_handle >= 1); + if (fat_cubin_handle==1) cuobjdumpInit(); + cuobjdumpRegisterFatBinary(fat_cubin_handle, filename); + + return (void**)fat_cubin_handle; + } +#if (CUDART_VERSION < 8000) + else { + static unsigned source_num=1; + unsigned long long fat_cubin_handle = next_fat_bin_handle++; + __cudaFatCudaBinary *info = (__cudaFatCudaBinary *)fatCubin; + assert( info->version >= 3 ); + unsigned num_ptx_versions=0; + unsigned max_capability=0; + unsigned selected_capability=0; + bool found=false; + unsigned forced_max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); + if (!info->ptx){ + printf("ERROR: Cannot find ptx code in cubin file\n" + "\tIf you are using CUDA 4.0 or higher, please enable -gpgpu_ptx_use_cuobjdump or downgrade to CUDA 3.1\n"); + exit(1); + } + while( info->ptx[num_ptx_versions].gpuProfileName != NULL ) { + unsigned capability=0; + sscanf(info->ptx[num_ptx_versions].gpuProfileName,"compute_%u",&capability); + printf("GPGPU-Sim PTX: __cudaRegisterFatBinary found PTX versions for '%s', ", info->ident); + printf("capability = %s\n", info->ptx[num_ptx_versions].gpuProfileName ); + if( forced_max_capability ) { + if( capability > max_capability && capability <= forced_max_capability ) { + found = true; + max_capability=capability; + selected_capability = num_ptx_versions; + } + } else { + if( capability > max_capability ) { + found = true; + max_capability=capability; + selected_capability = num_ptx_versions; + } + } + num_ptx_versions++; + } + if( found ) { + printf("GPGPU-Sim PTX: Loading PTX for %s, capability = %s\n", + info->ident, info->ptx[selected_capability].gpuProfileName ); + symbol_table *symtab; + const char *ptx = info->ptx[selected_capability].ptx; + if(context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() ) { + printf("GPGPU-Sim PTX: ERROR ** PTXPlus is only supported through cuobjdump\n" + "\tEither enable cuobjdump or disable PTXPlus in your configuration file\n"); + exit(1); + } else { + symtab=gpgpu_ptx_sim_load_ptx_from_string(ptx,source_num); + context->add_binary(symtab,fat_cubin_handle); + gpgpu_ptxinfo_load_from_string( ptx, source_num, max_capability ); + } + source_num++; + load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu()); + load_constants(symtab,STATIC_ALLOC_LIMIT,context->get_device()->get_gpgpu()); + } else { + printf("GPGPU-Sim PTX: warning -- did not find an appropriate PTX in cubin\n"); + } + return (void**)fat_cubin_handle; + } +#else + else { + printf("ERROR ** __cudaRegisterFatBinary() needs to be updated\n"); + abort(); + } +#endif +} + +void __cudaUnregisterFatBinary(void **fatCubinHandle) +{ + ; +} + +cudaError_t cudaDeviceReset ( void ) { + // Should reset the simulated GPU + return g_last_cudaError = cudaSuccess; +} +cudaError_t CUDARTAPI cudaDeviceSynchronize(void){ + // I don't know what this should do + return g_last_cudaError = cudaSuccess; +} + + +void CUDARTAPI __cudaRegisterFunction( + void **fatCubinHandle, + const char *hostFun, + char *deviceFun, + const char *deviceName, + int thread_limit, + uint3 *tid, + uint3 *bid, + dim3 *bDim, + dim3 *gDim +) +{ + CUctx_st *context = GPGPUSim_Context(); + unsigned fat_cubin_handle = (unsigned)(unsigned long long)fatCubinHandle; + printf("GPGPU-Sim PTX: __cudaRegisterFunction %s : hostFun 0x%p, fat_cubin_handle = %u\n", + deviceFun, hostFun, fat_cubin_handle); + if(context->get_device()->get_gpgpu()->get_config().use_cuobjdump()) + cuobjdumpParseBinary(fat_cubin_handle); + context->register_function( fat_cubin_handle, hostFun, deviceFun ); +} + +extern void __cudaRegisterVar( + void **fatCubinHandle, + char *hostVar, //pointer to...something + char *deviceAddress, //name of variable + const char *deviceName, //name of variable (same as above) + int ext, + int size, + int constant, + int global ) +{ + printf("GPGPU-Sim PTX: __cudaRegisterVar: hostVar = %p; deviceAddress = %s; deviceName = %s\n", hostVar, deviceAddress, deviceName); + printf("GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of %d bytes\n", size); + if(GPGPUSim_Context()->get_device()->get_gpgpu()->get_config().use_cuobjdump()) + cuobjdumpParseBinary((unsigned)(unsigned long long)fatCubinHandle); + fflush(stdout); + if ( constant && !global && !ext ) { + gpgpu_ptx_sim_register_const_variable(hostVar,deviceName,size); + } else if ( !constant && !global && !ext ) { + gpgpu_ptx_sim_register_global_variable(hostVar,deviceName,size); + } else cuda_not_implemented(__my_func__,__LINE__); +} + + +void __cudaRegisterShared( + void **fatCubinHandle, + void **devicePtr +) +{ + // we don't do anything here + printf("GPGPU-Sim PTX: __cudaRegisterShared\n" ); +} + +void CUDARTAPI __cudaRegisterSharedVar( + void **fatCubinHandle, + void **devicePtr, + size_t size, + size_t alignment, + int storage +) +{ + // we don't do anything here + printf("GPGPU-Sim PTX: __cudaRegisterSharedVar\n" ); +} + +void __cudaRegisterTexture( + void **fatCubinHandle, + const struct textureReference *hostVar, + const void **deviceAddress, + const char *deviceName, + int dim, + int norm, + int ext +) //passes in a newly created textureReference +{ + std::string devStr (deviceName); + #if (CUDART_VERSION > 4020) + if (devStr.size() > 2 && devStr.data()[0] == ':' && devStr.data()[1] == ':') + devStr = devStr.replace(0, 2, ""); + #endif + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + printf("GPGPU-Sim PTX: in __cudaRegisterTexture:\n"); + gpu->gpgpu_ptx_sim_bindNameToTexture(devStr.data(), hostVar, dim, norm, ext); + printf("GPGPU-Sim PTX: int dim = %d\n", dim); + printf("GPGPU-Sim PTX: int norm = %d\n", norm); + printf("GPGPU-Sim PTX: int ext = %d\n", ext); + printf("GPGPU-Sim PTX: Execution warning: Not finished implementing \"%s\"\n", __my_func__ ); +} + +#ifndef OPENGL_SUPPORT +typedef unsigned long GLuint; +#endif + +cudaError_t cudaGLRegisterBufferObject(GLuint bufferObj) +{ + printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); + return g_last_cudaError = cudaSuccess; +} + +struct glbmap_entry { + GLuint m_bufferObj; + void *m_devPtr; + size_t m_size; + struct glbmap_entry *m_next; +}; +typedef struct glbmap_entry glbmap_entry_t; + +glbmap_entry_t* g_glbmap = NULL; + +cudaError_t cudaGLMapBufferObject(void** devPtr, GLuint bufferObj) +{ +#ifdef OPENGL_SUPPORT + GLint buffer_size=0; + CUctx_st* ctx = GPGPUSim_Context(); + + glbmap_entry_t *p = g_glbmap; + while ( p && p->m_bufferObj != bufferObj ) + p = p->m_next; + if ( p == NULL ) { + glBindBuffer(GL_ARRAY_BUFFER,bufferObj); + glGetBufferParameteriv(GL_ARRAY_BUFFER,GL_BUFFER_SIZE,&buffer_size); + assert( buffer_size != 0 ); + *devPtr = ctx->get_device()->get_gpgpu()->gpu_malloc(buffer_size); + + // create entry and insert to front of list + glbmap_entry_t *n = (glbmap_entry_t *) calloc(1,sizeof(glbmap_entry_t)); + n->m_next = g_glbmap; + g_glbmap = n; + + // initialize entry + n->m_bufferObj = bufferObj; + n->m_devPtr = *devPtr; + n->m_size = buffer_size; + + p = n; + } else { + buffer_size = p->m_size; + *devPtr = p->m_devPtr; + } + + if ( *devPtr ) { + char *data = (char *) calloc(p->m_size,1); + glGetBufferSubData(GL_ARRAY_BUFFER,0,buffer_size,data); + memcpy_to_gpu( (size_t) *devPtr, data, buffer_size ); + free(data); + printf("GPGPU-Sim PTX: cudaGLMapBufferObject %zu bytes starting at 0x%llx..\n", (size_t)buffer_size, + (unsigned long long) *devPtr); + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorMemoryAllocation; + } + + return g_last_cudaError = cudaSuccess; +#else + fflush(stdout); + fflush(stderr); + printf("GPGPU-Sim PTX: GPGPU-Sim support for OpenGL integration disabled -- exiting\n"); + fflush(stdout); + exit(50); +#endif +} + +cudaError_t cudaGLUnmapBufferObject(GLuint bufferObj) +{ +#ifdef OPENGL_SUPPORT + glbmap_entry_t *p = g_glbmap; + while ( p && p->m_bufferObj != bufferObj ) + p = p->m_next; + if ( p == NULL ) + return g_last_cudaError = cudaErrorUnknown; + + char *data = (char *) calloc(p->m_size,1); + memcpy_from_gpu( data,(size_t)p->m_devPtr,p->m_size ); + glBufferSubData(GL_ARRAY_BUFFER,0,p->m_size,data); + free(data); + + return g_last_cudaError = cudaSuccess; +#else + fflush(stdout); + fflush(stderr); + printf("GPGPU-Sim PTX: support for OpenGL integration disabled -- exiting\n"); + fflush(stdout); + exit(50); +#endif +} + +cudaError_t cudaGLUnregisterBufferObject(GLuint bufferObj) +{ + printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); + return g_last_cudaError = cudaSuccess; +} + +#if (CUDART_VERSION >= 2010) + +cudaError_t CUDARTAPI cudaHostAlloc(void **pHost, size_t bytes, unsigned int flags) +{ + *pHost = malloc(bytes); + //need to track the size allocated so that cudaHostGetDevicePointer() can function properly. + //TODO: vary this function behavior based on flags value (following nvidia documentation) + pinned_memory_size[*pHost]=bytes; + if( *pHost ) + return g_last_cudaError = cudaSuccess; + else + return g_last_cudaError = cudaErrorMemoryAllocation; +} + +cudaError_t CUDARTAPI cudaHostGetDevicePointer(void **pDevice, void *pHost, unsigned int flags) +{ + //only cpu memory allocation happens in cudaHostAlloc. Linking with device pointer to pinned memory happens here. + //TODO: once kernel is executed, the contents in global pointer of GPU must be copied back to CPU host pointer! + flags=0; + CUctx_st* context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + std::map::const_iterator i = pinned_memory_size.find(pHost); + assert(i != pinned_memory_size.end()); + size_t size = i->second; + *pDevice = gpu->gpu_malloc(size); + if(g_debug_execution >= 3) + printf("GPGPU-Sim PTX: cudaMallocing %zu bytes starting at 0x%llx..\n",size, (unsigned long long) *pDevice); + if ( *pDevice ) { + pinned_memory[pHost]=pDevice; + //Copy contents in cpu to gpu + gpu->memcpy_to_gpu((size_t)*pDevice,pHost,size); + return g_last_cudaError = cudaSuccess; + } else { + return g_last_cudaError = cudaErrorMemoryAllocation; + } +} + +cudaError_t CUDARTAPI cudaSetValidDevices(int *device_arr, int len) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + +cudaError_t CUDARTAPI cudaSetDeviceFlags( int flags ) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + +cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, const char *hostFun ) +{ + CUctx_st *context = GPGPUSim_Context(); + function_info *entry = context->get_kernel(hostFun); + if( entry ) { + const struct gpgpu_ptx_sim_info *kinfo = entry->get_kernel_info(); + attr->sharedSizeBytes = kinfo->smem; + attr->constSizeBytes = kinfo->cmem; + attr->localSizeBytes = kinfo->lmem; + attr->numRegs = kinfo->regs; + attr->maxThreadsPerBlock = 0; // from pragmas? +#if CUDART_VERSION >= 3000 + attr->ptxVersion = kinfo->ptx_version; + attr->binaryVersion = kinfo->sm_target; +#endif + } + return g_last_cudaError = cudaSuccess; +} + +cudaError_t CUDARTAPI cudaEventCreateWithFlags(cudaEvent_t *event, int flags) +{ + CUevent_st *e = new CUevent_st(flags==cudaEventBlockingSync); + g_timer_events[e->get_uid()] = e; +#if CUDART_VERSION >= 3000 + *event = e; +#else + *event = e->get_uid(); +#endif + return g_last_cudaError = cudaSuccess; +} + +cudaError_t CUDARTAPI cudaDriverGetVersion(int *driverVersion) +{ + *driverVersion = CUDART_VERSION; + return g_last_cudaError = cudaErrorUnknown; +} + +cudaError_t CUDARTAPI cudaRuntimeGetVersion(int *runtimeVersion) +{ + *runtimeVersion = CUDART_VERSION; + return g_last_cudaError = cudaErrorUnknown; +} + +#if CUDART_VERSION >= 3000 +__host__ cudaError_t CUDARTAPI cudaFuncSetCacheConfig(const char *func, enum cudaFuncCache cacheConfig ) +{ + CUctx_st *context = GPGPUSim_Context(); + context->get_device()->get_gpgpu()->set_cache_config(context->get_kernel(func)->get_name(), (FuncCache)cacheConfig); + return g_last_cudaError = cudaSuccess; +} + +//Jin: hack for cdp +__host__ cudaError_t CUDARTAPI cudaDeviceSetLimit(enum cudaLimit limit, size_t value) { + return g_last_cudaError = cudaSuccess; +} +#endif + +#endif + +cudaError_t CUDARTAPI cudaGLSetGLDevice(int device) +{ + printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); + return g_last_cudaError = cudaErrorUnknown; +} + +typedef void* HGPUNV; + +cudaError_t CUDARTAPI cudaWGLGetDevice(int *device, HGPUNV hGpu) +{ + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; +} + +void CUDARTAPI __cudaMutexOperation(int lock) +{ + cuda_not_implemented(__my_func__,__LINE__); +} + +void CUDARTAPI __cudaTextureFetch(const void *tex, void *index, int integer, void *val) +{ + cuda_not_implemented(__my_func__,__LINE__); +} + +} + +namespace cuda_math { + +void CUDARTAPI __cudaMutexOperation(int lock) +{ + cuda_not_implemented(__my_func__,__LINE__); +} + +void CUDARTAPI __cudaTextureFetch(const void *tex, void *index, int integer, void *val) +{ + cuda_not_implemented(__my_func__,__LINE__); +} + +int CUDARTAPI __cudaSynchronizeThreads(void**, void*) +{ + //TODO This function should syncronize if we support Asyn kernel calls + return g_last_cudaError = cudaSuccess; +} + +} + +//////// + +extern int ptx_parse(); +extern int ptx__scan_string(const char*); +extern FILE *ptx_in; + +extern int ptxinfo_parse(); +extern int ptxinfo_debug; +extern FILE *ptxinfo_in; + +/// static functions + +static int load_static_globals( symbol_table *symtab, unsigned min_gaddr, unsigned max_gaddr, gpgpu_t *gpu ) +{ + printf( "GPGPU-Sim PTX: loading globals with explicit initializers... \n" ); + fflush(stdout); + int ng_bytes=0; + symbol_table::iterator g=symtab->global_iterator_begin(); + + for ( ; g!=symtab->global_iterator_end(); g++) { + symbol *global = *g; + if ( global->has_initializer() ) { + printf( "GPGPU-Sim PTX: initializing '%s' ... ", global->name().c_str() ); + unsigned addr=global->get_address(); + const type_info *type = global->type(); + type_info_key ti=type->get_key(); + size_t size; + int t; + ti.type_decode(size,t); + int nbytes = size/8; + int offset=0; + std::list init_list = global->get_initializer(); + for ( std::list::iterator i=init_list.begin(); i!=init_list.end(); i++ ) { + operand_info op = *i; + ptx_reg_t value = op.get_literal_value(); + assert( (addr+offset+nbytes) < min_gaddr ); // min_gaddr is start of "heap" for cudaMalloc + gpu->get_global_memory()->write(addr+offset,nbytes,&value,NULL,NULL); // assuming little endian here + offset+=nbytes; + ng_bytes+=nbytes; + } + printf(" wrote %u bytes\n", offset ); + } + } + printf( "GPGPU-Sim PTX: finished loading globals (%u bytes total).\n", ng_bytes ); + fflush(stdout); + return ng_bytes; +} + +static int load_constants( symbol_table *symtab, addr_t min_gaddr, gpgpu_t *gpu ) +{ + printf( "GPGPU-Sim PTX: loading constants with explicit initializers... " ); + fflush(stdout); + int nc_bytes = 0; + symbol_table::iterator g=symtab->const_iterator_begin(); + + for ( ; g!=symtab->const_iterator_end(); g++) { + symbol *constant = *g; + if ( constant->is_const() && constant->has_initializer() ) { + + // get the constant element data size + int basic_type; + size_t num_bits; + constant->type()->get_key().type_decode(num_bits,basic_type); + + std::list init_list = constant->get_initializer(); + int nbytes_written = 0; + for ( std::list::iterator i=init_list.begin(); i!=init_list.end(); i++ ) { + operand_info op = *i; + ptx_reg_t value = op.get_literal_value(); + int nbytes = num_bits/8; + switch ( op.get_type() ) { + case int_t: assert(nbytes >= 1); break; + case float_op_t: assert(nbytes == 4); break; + case double_op_t: assert(nbytes >= 4); break; // account for double DEMOTING + default: + abort(); + } + unsigned addr=constant->get_address() + nbytes_written; + assert( addr+nbytes < min_gaddr ); + + gpu->get_global_memory()->write(addr,nbytes,&value,NULL,NULL); // assume little endian (so u8 is the first byte in u32) + nc_bytes+=nbytes; + nbytes_written += nbytes; + } + } + } + printf( " done.\n"); + fflush(stdout); + return nc_bytes; +} + +kernel_info_t *gpgpu_cuda_ptx_sim_init_grid( const char *hostFun, + gpgpu_ptx_sim_arg_list_t args, + struct dim3 gridDim, + struct dim3 blockDim, + CUctx_st* context ) +{ + function_info *entry = context->get_kernel(hostFun); + kernel_info_t *result = new kernel_info_t(gridDim,blockDim,entry); + if( entry == NULL ) { + printf("GPGPU-Sim PTX: ERROR launching kernel -- no PTX implementation found for %p\n", hostFun); + abort(); + } + unsigned argcount=args.size(); + unsigned argn=1; + for( gpgpu_ptx_sim_arg_list_t::iterator a = args.begin(); a != args.end(); a++ ) { + entry->add_param_data(argcount-argn,&(*a)); + argn++; + } + + entry->finalize(result->get_param_memory()); + g_ptx_kernel_count++; + fflush(stdout); + + return result; +} diff --git a/src/cuda-sim/cuda-sim.cc~ b/src/cuda-sim/cuda-sim.cc~ new file mode 100644 index 0000000..cfd901f --- /dev/null +++ b/src/cuda-sim/cuda-sim.cc~ @@ -0,0 +1,2155 @@ +// Copyright (c) 2009-2011, Tor M. Aamodt, Ali Bakhoda, Wilson W.L. Fung, +// George L. Yuan, Jimmy Kwa +// The University of British Columbia +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// Redistributions in binary form must reproduce the above copyright notice, this +// list of conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. +// Neither the name of The University of British Columbia nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#include "cuda-sim.h" + +#include "instructions.h" +#include "ptx_ir.h" +#include "ptx.tab.h" +#include "ptx_sim.h" +#include + +#include "opcodes.h" +#include "../statwrapper.h" +#include +#include +#include "../abstract_hardware_model.h" +#include "memory.h" +#include "ptx-stats.h" +#include "ptx_loader.h" +#include "ptx_parser.h" +#include "../gpgpu-sim/gpu-sim.h" +#include "ptx_sim.h" +#include "../gpgpusim_entrypoint.h" +#include "decuda_pred_table/decuda_pred_table.h" +#include "../stream_manager.h" +#include "cuda_device_runtime.h" + +int gpgpu_ptx_instruction_classification; +void ** g_inst_classification_stat = NULL; +void ** g_inst_op_classification_stat= NULL; +int g_ptx_kernel_count = -1; // used for classification stat collection purposes +int g_debug_execution = 0; +int g_debug_thread_uid = 0; +addr_t g_debug_pc = 0xBEEF1518; +// Output debug information to file options + +unsigned g_ptx_sim_num_insn = 0; +unsigned gpgpu_param_num_shaders = 0; + +char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp; +char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp; +char *cdp_latency_str; +unsigned cdp_latency[5]; + +void ptx_opcocde_latency_options (option_parser_t opp) { + option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, + "Opcode latencies for integers " + "Default 1,1,19,25,145", + "1,1,19,25,145"); + option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp, + "Opcode latencies for single precision floating points " + "Default 1,1,1,1,30", + "1,1,1,1,30"); + option_parser_register(opp, "-ptx_opcode_latency_dp", OPT_CSTR, &opcode_latency_dp, + "Opcode latencies for double precision floating points " + "Default 8,8,8,8,335", + "8,8,8,8,335"); + option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, + "Opcode initiation intervals for integers " + "Default 1,1,4,4,32", + "1,1,4,4,32"); + option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp, + "Opcode initiation intervals for single precision floating points " + "Default 1,1,1,1,5", + "1,1,1,1,5"); + option_parser_register(opp, "-ptx_opcode_initiation_dp", OPT_CSTR, &opcode_initiation_dp, + "Opcode initiation intervals for double precision floating points " + "Default 8,8,8,8,130", + "8,8,8,8,130"); + option_parser_register(opp, "-cdp_latency", OPT_CSTR, &cdp_latency_str, + "CDP API latency " + "Default 7200,8000,100,12000,1600", + "7200,8000,100,12000,1600"); +} + +static address_type get_converge_point(address_type pc); + +void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) +{ + std::string texname(name); + m_NameToTextureRef[texname] = texref; + const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); + m_TextureRefToAttribute[texref] = texAttr; +} + +const char* gpgpu_t::gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref) +{ + std::map::iterator itr = m_NameToTextureRef.begin(); + while (itr != m_NameToTextureRef.end()) { + if ((*itr).second == texref) { + const char *p = ((*itr).first).c_str(); + return p; + } + itr++; + } + return NULL; +} + +unsigned int intLOGB2( unsigned int v ) { + unsigned int shift; + unsigned int r; + + r = 0; + + shift = (( v & 0xFFFF0000) != 0 ) << 4; v >>= shift; r |= shift; + shift = (( v & 0xFF00 ) != 0 ) << 3; v >>= shift; r |= shift; + shift = (( v & 0xF0 ) != 0 ) << 2; v >>= shift; r |= shift; + shift = (( v & 0xC ) != 0 ) << 1; v >>= shift; r |= shift; + shift = (( v & 0x2 ) != 0 ) << 0; v >>= shift; r |= shift; + + return r; +} + +void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) +{ + m_TextureRefToCudaArray[texref] = array; + unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; + unsigned int texel_size = texel_size_bits/8; + unsigned int Tx, Ty; + int r; + + printf("GPGPU-Sim PTX: texel size = %d\n", texel_size); + printf("GPGPU-Sim PTX: texture cache linesize = %d\n", m_function_model_config.get_texcache_linesize()); + //first determine base Tx size for given linesize + switch (m_function_model_config.get_texcache_linesize()) { + case 16: Tx = 4; break; + case 32: Tx = 8; break; + case 64: Tx = 8; break; + case 128: Tx = 16; break; + case 256: Tx = 16; break; + default: + printf("GPGPU-Sim PTX: Line size of %d bytes currently not supported.\n", m_function_model_config.get_texcache_linesize()); + assert(0); + break; + } + r = texel_size >> 2; + //modify base Tx size to take into account size of each texel in bytes + while (r != 0) { + Tx = Tx >> 1; + r = r >> 2; + } + //by now, got the correct Tx size, calculate correct Ty size + Ty = m_function_model_config.get_texcache_linesize()/(Tx*texel_size); + + printf("GPGPU-Sim PTX: Tx = %d; Ty = %d, Tx_numbits = %d, Ty_numbits = %d\n", Tx, Ty, intLOGB2(Tx), intLOGB2(Ty)); + printf("GPGPU-Sim PTX: Texel size = %d bytes; texel_size_numbits = %d\n", texel_size, intLOGB2(texel_size)); + printf("GPGPU-Sim PTX: Binding texture to array starting at devPtr32 = 0x%x\n", array->devPtr32); + printf("GPGPU-Sim PTX: Texel size = %d bytes\n", texel_size); + struct textureInfo* texInfo = (struct textureInfo*) malloc(sizeof(struct textureInfo)); + texInfo->Tx = Tx; + texInfo->Ty = Ty; + texInfo->Tx_numbits = intLOGB2(Tx); + texInfo->Ty_numbits = intLOGB2(Ty); + texInfo->texel_size = texel_size; + texInfo->texel_size_numbits = intLOGB2(texel_size); + m_TextureRefToTexureInfo[texref] = texInfo; +} + +unsigned g_assemble_code_next_pc=0; +std::map g_pc_to_finfo; +std::vector function_info::s_g_pc_to_insn; + +#define MAX_INST_SIZE 8 /*bytes*/ + +void function_info::ptx_assemble() +{ + if( m_assembled ) { + return; + } + + // get the instructions into instruction memory... + unsigned num_inst = m_instructions.size(); + m_instr_mem_size = MAX_INST_SIZE*(num_inst+1); + m_instr_mem = new ptx_instruction*[ m_instr_mem_size ]; + + printf("GPGPU-Sim PTX: instruction assembly for function \'%s\'... ", m_name.c_str() ); + fflush(stdout); + std::list::iterator i; + + addr_t PC = g_assemble_code_next_pc; // globally unique address (across functions) + // start function on an aligned address + for( unsigned i=0; i < (PC%MAX_INST_SIZE); i++ ) + s_g_pc_to_insn.push_back((ptx_instruction*)NULL); + PC += PC%MAX_INST_SIZE; + m_start_PC = PC; + + addr_t n=0; // offset in m_instr_mem + //Why s_g_pc_to_insn.size() is needed to reserve additional memory for insts? reserve is cumulative. + //s_g_pc_to_insn.reserve(s_g_pc_to_insn.size() + MAX_INST_SIZE*m_instructions.size()); + s_g_pc_to_insn.reserve(MAX_INST_SIZE*m_instructions.size()); + for ( i=m_instructions.begin(); i != m_instructions.end(); i++ ) { + ptx_instruction *pI = *i; + if ( pI->is_label() ) { + const symbol *l = pI->get_label(); + labels[l->name()] = n; + } else { + g_pc_to_finfo[PC] = this; + m_instr_mem[n] = pI; + s_g_pc_to_insn.push_back(pI); + assert(pI == s_g_pc_to_insn[PC]); + pI->set_m_instr_mem_index(n); + pI->set_PC(PC); + assert( pI->inst_size() <= MAX_INST_SIZE ); + for( unsigned i=1; i < pI->inst_size(); i++ ) { + s_g_pc_to_insn.push_back((ptx_instruction*)NULL); + m_instr_mem[n+i]=NULL; + } + n += pI->inst_size(); + PC += pI->inst_size(); + } + } + g_assemble_code_next_pc=PC; + for ( unsigned ii=0; ii < n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions + ptx_instruction *pI = m_instr_mem[ii]; + if ( pI->get_opcode() == BRA_OP || pI->get_opcode() == BREAKADDR_OP || pI->get_opcode() == CALLP_OP) { + operand_info &target = pI->dst(); //get operand, e.g. target name + if ( labels.find(target.name()) == labels.end() ) { + printf("GPGPU-Sim PTX: Loader error (%s:%u): Branch label \"%s\" does not appear in assembly code.", + pI->source_file(),pI->source_line(), target.name().c_str() ); + abort(); + } + unsigned index = labels[ target.name() ]; //determine address from name + unsigned PC = m_instr_mem[index]->get_PC(); + m_symtab->set_label_address( target.get_symbol(), PC ); + target.set_type(label_t); + } + } + m_n = n; + printf(" done.\n"); + fflush(stdout); + + //disable pdom analysis here and do it at runtime + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", m_name.c_str() ); + create_basic_blocks(); + connect_basic_blocks(); + bool modified = false; + do { + find_dominators(); + find_idominators(); + modified = connect_break_targets(); + } while (modified == true); + + if ( g_debug_execution>=50 ) { + print_basic_blocks(); + print_basic_block_links(); + print_basic_block_dot(); + } + if ( g_debug_execution>=2 ) { + print_dominators(); + } + find_postdominators(); + find_ipostdominators(); + if ( g_debug_execution>=50 ) { + print_postdominators(); + print_ipostdominators(); + } + + printf("GPGPU-Sim PTX: pre-decoding instructions for \'%s\'...\n", m_name.c_str() ); + for ( unsigned ii=0; ii < n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions + ptx_instruction *pI = m_instr_mem[ii]; + pI->pre_decode(); + } + printf("GPGPU-Sim PTX: ... done pre-decoding instructions for \'%s\'.\n", m_name.c_str() ); + fflush(stdout); + + m_assembled = true; +} + +addr_t shared_to_generic( unsigned smid, addr_t addr ) +{ + assert( addr < SHARED_MEM_SIZE_MAX ); + return SHARED_GENERIC_START + smid*SHARED_MEM_SIZE_MAX + addr; +} + +addr_t global_to_generic( addr_t addr ) +{ + return addr; +} + +bool isspace_shared( unsigned smid, addr_t addr ) +{ + addr_t start = SHARED_GENERIC_START + smid*SHARED_MEM_SIZE_MAX; + addr_t end = SHARED_GENERIC_START + (smid+1)*SHARED_MEM_SIZE_MAX; + if( (addr >= end) || (addr < start) ) + return false; + return true; +} + +bool isspace_global( addr_t addr ) +{ + return (addr >= GLOBAL_HEAP_START) || (addr < STATIC_ALLOC_LIMIT); +} + +memory_space_t whichspace( addr_t addr ) +{ + if( (addr >= GLOBAL_HEAP_START) || (addr < STATIC_ALLOC_LIMIT) ) { + return global_space; + } else if( addr >= SHARED_GENERIC_START ) { + return shared_space; + } else { + return local_space; + } +} + +addr_t generic_to_shared( unsigned smid, addr_t addr ) +{ + assert(isspace_shared(smid,addr)); + return addr - (SHARED_GENERIC_START + smid*SHARED_MEM_SIZE_MAX); +} + +addr_t local_to_generic( unsigned smid, unsigned hwtid, addr_t addr ) +{ + assert(addr < LOCAL_MEM_SIZE_MAX); + return LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * hwtid) + addr; +} + +bool isspace_local( unsigned smid, unsigned hwtid, addr_t addr ) +{ + addr_t start = LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * hwtid); + addr_t end = LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * (hwtid+1)); + if( (addr >= end) || (addr < start) ) + return false; + return true; +} + +addr_t generic_to_local( unsigned smid, unsigned hwtid, addr_t addr ) +{ + assert(isspace_local(smid,hwtid,addr)); + return addr - (LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * hwtid)); +} + +addr_t generic_to_global( addr_t addr ) +{ + return addr; +} + + +void* gpgpu_t::gpu_malloc( size_t size ) +{ + unsigned long long result = m_dev_malloc; + if(g_debug_execution >= 3) { + printf("GPGPU-Sim PTX: allocating %zu bytes on GPU starting at address 0x%Lx\n", size, m_dev_malloc ); + fflush(stdout); + } + m_dev_malloc += size; + if (size%256) m_dev_malloc += (256 - size%256); //align to 256 byte boundaries + return(void*) result; +} + +void* gpgpu_t::gpu_mallocarray( size_t size ) +{ + unsigned long long result = m_dev_malloc; + if(g_debug_execution >= 3) { + printf("GPGPU-Sim PTX: allocating %zu bytes on GPU starting at address 0x%Lx\n", size, m_dev_malloc ); + fflush(stdout); + } + m_dev_malloc += size; + if (size%256) m_dev_malloc += (256 - size%256); //align to 256 byte boundaries + return(void*) result; +} + + +void gpgpu_t::memcpy_to_gpu( size_t dst_start_addr, const void *src, size_t count ) +{ + if(g_debug_execution >= 3) { + printf("GPGPU-Sim PTX: copying %zu bytes from CPU[0x%Lx] to GPU[0x%Lx] ... ", count, (unsigned long long) src, (unsigned long long) dst_start_addr ); + fflush(stdout); + } + char *src_data = (char*)src; + for (unsigned n=0; n < count; n ++ ) + m_global_mem->write(dst_start_addr+n,1, src_data+n,NULL,NULL); + if(g_debug_execution >= 3) { + printf( " done.\n"); + fflush(stdout); + } +} + +void gpgpu_t::memcpy_from_gpu( void *dst, size_t src_start_addr, size_t count ) +{ + if(g_debug_execution >= 3) { + printf("GPGPU-Sim PTX: copying %zu bytes from GPU[0x%Lx] to CPU[0x%Lx] ...", count, (unsigned long long) src_start_addr, (unsigned long long) dst ); + fflush(stdout); + } + unsigned char *dst_data = (unsigned char*)dst; + for (unsigned n=0; n < count; n ++ ) + m_global_mem->read(src_start_addr+n,1,dst_data+n); + if(g_debug_execution >= 3) { + printf( " done.\n"); + fflush(stdout); + } +} + +void gpgpu_t::memcpy_gpu_to_gpu( size_t dst, size_t src, size_t count ) +{ + if(g_debug_execution >= 3) { + printf("GPGPU-Sim PTX: copying %zu bytes from GPU[0x%Lx] to GPU[0x%Lx] ...", count, + (unsigned long long) src, (unsigned long long) dst ); + fflush(stdout); + } + for (unsigned n=0; n < count; n ++ ) { + unsigned char tmp; + m_global_mem->read(src+n,1,&tmp); + m_global_mem->write(dst+n,1, &tmp,NULL,NULL); + } + if(g_debug_execution >= 3) { + printf( " done.\n"); + fflush(stdout); + } +} + +void gpgpu_t::gpu_memset( size_t dst_start_addr, int c, size_t count ) +{ + if(g_debug_execution >= 3) { + printf("GPGPU-Sim PTX: setting %zu bytes of memory to 0x%x starting at 0x%Lx... ", + count, (unsigned char) c, (unsigned long long) dst_start_addr ); + fflush(stdout); + } + unsigned char c_value = (unsigned char)c; + for (unsigned n=0; n < count; n ++ ) + m_global_mem->write(dst_start_addr+n,1,&c_value,NULL,NULL); + if(g_debug_execution >= 3) { + printf( " done.\n"); + fflush(stdout); + } +} + +void ptx_print_insn( address_type pc, FILE *fp ) +{ + std::map::iterator f = g_pc_to_finfo.find(pc); + if( f == g_pc_to_finfo.end() ) { + fprintf(fp,"", pc ); + return; + } + function_info *finfo = f->second; + assert( finfo ); + finfo->print_insn(pc,fp); +} + +std::string ptx_get_insn_str( address_type pc ) +{ + std::map::iterator f = g_pc_to_finfo.find(pc); + if( f == g_pc_to_finfo.end() ) { + #define STR_SIZE 255 + char buff[STR_SIZE]; + buff[STR_SIZE - 1] = '\0'; + snprintf(buff, STR_SIZE,"", pc ); + return std::string(buff); + } + function_info *finfo = f->second; + assert( finfo ); + return finfo->get_insn_str(pc); +} + +void ptx_instruction::set_fp_or_int_archop(){ + oprnd_type=UN_OP; + if((m_opcode == MEMBAR_OP)||(m_opcode == SSY_OP )||(m_opcode == BRA_OP) || (m_opcode == BAR_OP) || (m_opcode == RET_OP) || (m_opcode == RETP_OP) || (m_opcode == NOP_OP) || (m_opcode == EXIT_OP) || (m_opcode == CALLP_OP) || (m_opcode == CALL_OP)){ + // do nothing + }else if((m_opcode == CVT_OP || m_opcode == SET_OP || m_opcode == SLCT_OP)){ + if(get_type2()==F16_TYPE || get_type2()==F32_TYPE || get_type2() == F64_TYPE || get_type2() == FF64_TYPE){ + oprnd_type= FP_OP; + }else oprnd_type=INT_OP; + + }else{ + if(get_type()==F16_TYPE || get_type()==F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE){ + oprnd_type= FP_OP; + }else oprnd_type=INT_OP; + } +} +void ptx_instruction::set_mul_div_or_other_archop(){ + sp_op=OTHER_OP; + if((m_opcode != MEMBAR_OP) && (m_opcode != SSY_OP) && (m_opcode != BRA_OP) && (m_opcode != BAR_OP) && (m_opcode != EXIT_OP) && (m_opcode != NOP_OP) && (m_opcode != RETP_OP) && (m_opcode != RET_OP) && (m_opcode != CALLP_OP) && (m_opcode != CALL_OP)){ + if(get_type()==F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE){ + switch(get_opcode()){ + case MUL_OP: + case MAD_OP: + sp_op=FP_MUL_OP; + break; + case DIV_OP: + sp_op=FP_DIV_OP; + break; + case LG2_OP: + sp_op=FP_LG_OP; + break; + case RSQRT_OP: + case SQRT_OP: + sp_op=FP_SQRT_OP; + break; + case RCP_OP: + sp_op=FP_DIV_OP; + break; + case SIN_OP: + case COS_OP: + sp_op=FP_SIN_OP; + break; + case EX2_OP: + sp_op=FP_EXP_OP; + break; + default: + if(op==ALU_OP) + sp_op=FP__OP; + break; + + } + }else { + switch(get_opcode()){ + case MUL24_OP: + case MAD24_OP: + sp_op=INT_MUL24_OP; + break; + case MUL_OP: + case MAD_OP: + if(get_type()==U32_TYPE || get_type()==S32_TYPE || get_type()==B32_TYPE) + sp_op=INT_MUL32_OP; + else + sp_op=INT_MUL_OP; + break; + case DIV_OP: + sp_op=INT_DIV_OP; + break; + default: + if(op==ALU_OP) + sp_op=INT__OP; + break; + } + } + } + +} + + + +void ptx_instruction::set_bar_type() +{ + if(m_opcode==BAR_OP) { + switch(m_barrier_op){ + case SYNC_OPTION: + bar_type = SYNC; + break; + case ARRIVE_OPTION: + bar_type = ARRIVE; + break; + case RED_OPTION: + bar_type = RED; + switch(m_atomic_spec){ + case ATOMIC_POPC: + red_type = POPC_RED; + break; + case ATOMIC_AND: + red_type = AND_RED; + break; + case ATOMIC_OR: + red_type = OR_RED; + break; + } + break; + default: + abort(); + } + } +} + + +void ptx_instruction::set_opcode_and_latency() +{ + unsigned int_latency[5]; + unsigned fp_latency[5]; + unsigned dp_latency[5]; + unsigned int_init[5]; + unsigned fp_init[5]; + unsigned dp_init[5]; + /* + * [0] ADD,SUB + * [1] MAX,Min + * [2] MUL + * [3] MAD + * [4] DIV + */ + sscanf(opcode_latency_int, "%u,%u,%u,%u,%u", + &int_latency[0],&int_latency[1],&int_latency[2], + &int_latency[3],&int_latency[4]); + sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u", + &fp_latency[0],&fp_latency[1],&fp_latency[2], + &fp_latency[3],&fp_latency[4]); + sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u", + &dp_latency[0],&dp_latency[1],&dp_latency[2], + &dp_latency[3],&dp_latency[4]); + sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u", + &int_init[0],&int_init[1],&int_init[2], + &int_init[3],&int_init[4]); + sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u", + &fp_init[0],&fp_init[1],&fp_init[2], + &fp_init[3],&fp_init[4]); + sscanf(opcode_initiation_dp, "%u,%u,%u,%u,%u", + &dp_init[0],&dp_init[1],&dp_init[2], + &dp_init[3],&dp_init[4]); + sscanf(cdp_latency_str, "%u,%u,%u,%u,%u", + &cdp_latency[0],&cdp_latency[1],&cdp_latency[2], + &cdp_latency[3],&cdp_latency[4]); + + if(!m_operands.empty()){ + std::vector::iterator it; + for(it=++m_operands.begin();it!=m_operands.end();it++){ + num_operands++; + if((it->is_reg() || it->is_vector())){ + num_regs++; + } + } + } + op = ALU_OP; + mem_op= NOT_TEX; + initiation_interval = latency = 1; + switch( m_opcode ) { + case MOV_OP: + assert( !(has_memory_read() && has_memory_write()) ); + if ( has_memory_read() ) op = LOAD_OP; + if ( has_memory_write() ) op = STORE_OP; + break; + case LD_OP: op = LOAD_OP; break; + case LDU_OP: op = LOAD_OP; break; + case ST_OP: op = STORE_OP; break; + case BRA_OP: op = BRANCH_OP; break; + case BREAKADDR_OP: op = BRANCH_OP; break; + case TEX_OP: op = LOAD_OP; mem_op=TEX; break; + case ATOM_OP: op = LOAD_OP; break; + case BAR_OP: op = BARRIER_OP; break; + case MEMBAR_OP: op = MEMORY_BARRIER_OP; break; + case CALL_OP: + { + if(m_is_printf || m_is_cdp) { + op = ALU_OP; + } + else + op = CALL_OPS; + break; + } + case CALLP_OP: + { + if(m_is_printf || m_is_cdp) { + op = ALU_OP; + } + else + op = CALL_OPS; + break; + } + case RET_OP: case RETP_OP: op = RET_OPS;break; + case ADD_OP: case ADDP_OP: case ADDC_OP: case SUB_OP: case SUBC_OP: + //ADD,SUB latency + switch(get_type()){ + case F32_TYPE: + latency = fp_latency[0]; + initiation_interval = fp_init[0]; + break; + case F64_TYPE: + case FF64_TYPE: + latency = dp_latency[0]; + initiation_interval = dp_init[0]; + break; + case B32_TYPE: + case U32_TYPE: + case S32_TYPE: + default: //Use int settings for default + latency = int_latency[0]; + initiation_interval = int_init[0]; + break; + } + break; + case MAX_OP: case MIN_OP: + //MAX,MIN latency + switch(get_type()){ + case F32_TYPE: + latency = fp_latency[1]; + initiation_interval = fp_init[1]; + break; + case F64_TYPE: + case FF64_TYPE: + latency = dp_latency[1]; + initiation_interval = dp_init[1]; + break; + case B32_TYPE: + case U32_TYPE: + case S32_TYPE: + default: //Use int settings for default + latency = int_latency[1]; + initiation_interval = int_init[1]; + break; + } + break; + case MUL_OP: + //MUL latency + switch(get_type()){ + case F32_TYPE: + latency = fp_latency[2]; + initiation_interval = fp_init[2]; + op = ALU_SFU_OP; + break; + case F64_TYPE: + case FF64_TYPE: + latency = dp_latency[2]; + initiation_interval = dp_init[2]; + op = ALU_SFU_OP; + break; + case B32_TYPE: + case U32_TYPE: + case S32_TYPE: + default: //Use int settings for default + latency = int_latency[2]; + initiation_interval = int_init[2]; + op = SFU_OP; + break; + } + break; + case MAD_OP: case MADC_OP: case MADP_OP: + //MAD latency + switch(get_type()){ + case F32_TYPE: + latency = fp_latency[3]; + initiation_interval = fp_init[3]; + break; + case F64_TYPE: + case FF64_TYPE: + latency = dp_latency[3]; + initiation_interval = dp_init[3]; + break; + case B32_TYPE: + case U32_TYPE: + case S32_TYPE: + default: //Use int settings for default + latency = int_latency[3]; + initiation_interval = int_init[3]; + op = SFU_OP; + break; + } + break; + case DIV_OP: + // Floating point only + op = SFU_OP; + switch(get_type()){ + case F32_TYPE: + latency = fp_latency[4]; + initiation_interval = fp_init[4]; + break; + case F64_TYPE: + case FF64_TYPE: + latency = dp_latency[4]; + initiation_interval = dp_init[4]; + break; + case B32_TYPE: + case U32_TYPE: + case S32_TYPE: + default: //Use int settings for default + latency = int_latency[4]; + initiation_interval = int_init[4]; + break; + } + break; + case SQRT_OP: case SIN_OP: case COS_OP: case EX2_OP: case LG2_OP: case RSQRT_OP: case RCP_OP: + //Using double to approximate those + latency = dp_latency[2]; + initiation_interval = dp_init[2]; + op = SFU_OP; + break; + case SHFL_OP: + latency = 32; + initiation_interval = 15; + break; + default: + break; + } + set_fp_or_int_archop(); + set_mul_div_or_other_archop(); + +} + +void ptx_thread_info::ptx_fetch_inst( inst_t &inst ) const +{ + addr_t pc = get_pc(); + const ptx_instruction *pI = m_func_info->get_instruction(pc); + inst = (const inst_t&)*pI; + assert( inst.valid() ); +} + +static unsigned datatype2size( unsigned data_type ) +{ + unsigned data_size; + switch ( data_type ) { + case B8_TYPE: + case S8_TYPE: + case U8_TYPE: + data_size = 1; break; + case B16_TYPE: + case S16_TYPE: + case U16_TYPE: + case F16_TYPE: + data_size = 2; break; + case B32_TYPE: + case S32_TYPE: + case U32_TYPE: + case F32_TYPE: + data_size = 4; break; + case B64_TYPE: + case BB64_TYPE: + case S64_TYPE: + case U64_TYPE: + case F64_TYPE: + case FF64_TYPE: + data_size = 8; break; + case BB128_TYPE: + data_size = 16; break; + default: assert(0); break; + } + return data_size; +} + +void ptx_instruction::pre_decode() +{ + pc = m_PC; + isize = m_inst_size; + for( unsigned i=0; i<4; i++) { + out[i] = 0; + in[i] = 0; + } + is_vectorin = 0; + is_vectorout = 0; + std::fill_n(arch_reg.src, MAX_REG_OPERANDS, -1); + std::fill_n(arch_reg.dst, MAX_REG_OPERANDS, -1); + pred = 0; + ar1 = 0; + ar2 = 0; + space = m_space_spec; + memory_op = no_memory_op; + data_size = 0; + if ( has_memory_read() || has_memory_write() ) { + unsigned to_type = get_type(); + data_size = datatype2size(to_type); + memory_op = has_memory_read() ? memory_load : memory_store; + } + + bool has_dst = false ; + + switch ( get_opcode() ) { +#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; +#include "opcodes.def" +#undef OP_DEF +#undef OP_W_DEF + default: + printf( "Execution error: Invalid opcode (0x%x)\n", get_opcode() ); + break; + } + + switch( m_cache_option ) { + case CA_OPTION: cache_op = CACHE_ALL; break; + case CG_OPTION: cache_op = CACHE_GLOBAL; break; + case CS_OPTION: cache_op = CACHE_STREAMING; break; + case LU_OPTION: cache_op = CACHE_LAST_USE; break; + case CV_OPTION: cache_op = CACHE_VOLATILE; break; + case WB_OPTION: cache_op = CACHE_WRITE_BACK; break; + case WT_OPTION: cache_op = CACHE_WRITE_THROUGH; break; + default: + if( m_opcode == LD_OP || m_opcode == LDU_OP ) + cache_op = CACHE_ALL; + else if( m_opcode == ST_OP ) + cache_op = CACHE_WRITE_BACK; + else if( m_opcode == ATOM_OP ) + cache_op = CACHE_GLOBAL; + break; + } + + set_opcode_and_latency(); + set_bar_type(); + // Get register operands + int n=0,m=0; + ptx_instruction::const_iterator opr=op_iter_begin(); + for ( ; opr != op_iter_end(); opr++, n++ ) { //process operands + const operand_info &o = *opr; + if ( has_dst && n==0 ) { + // Do not set the null register "_" as an architectural register + if ( o.is_reg() && !o.is_non_arch_reg() ) { + out[0] = o.reg_num(); + arch_reg.dst[0] = o.arch_reg_num(); + } else if ( o.is_vector() ) { + is_vectorin = 1; + unsigned num_elem = o.get_vect_nelem(); + if( num_elem >= 1 ) out[0] = o.reg1_num(); + if( num_elem >= 2 ) out[1] = o.reg2_num(); + if( num_elem >= 3 ) out[2] = o.reg3_num(); + if( num_elem >= 4 ) out[3] = o.reg4_num(); + for (int i = 0; i < num_elem; i++) + arch_reg.dst[i] = o.arch_reg_num(i); + } + } else { + if ( o.is_reg() && !o.is_non_arch_reg() ) { + int reg_num = o.reg_num(); + arch_reg.src[m] = o.arch_reg_num(); + switch ( m ) { + case 0: in[0] = reg_num; break; + case 1: in[1] = reg_num; break; + case 2: in[2] = reg_num; break; + default: break; + } + m++; + } else if ( o.is_vector() ) { + //assert(m == 0); //only support 1 vector operand (for textures) right now + is_vectorout = 1; + unsigned num_elem = o.get_vect_nelem(); + if( num_elem >= 1 ) in[0] = o.reg1_num(); + if( num_elem >= 2 ) in[1] = o.reg2_num(); + if( num_elem >= 3 ) in[2] = o.reg3_num(); + if( num_elem >= 4 ) in[3] = o.reg4_num(); + for (int i = 0; i < num_elem; i++) + arch_reg.src[i] = o.arch_reg_num(i); + m+=4; + } + } + } + + // Get predicate + if(has_pred()) { + const operand_info &p = get_pred(); + pred = p.reg_num(); + } + + // Get address registers inside memory operands. + // Assuming only one memory operand per instruction, + // and maximum of two address registers for one memory operand. + if( has_memory_read() || has_memory_write() ) { + ptx_instruction::const_iterator op=op_iter_begin(); + for ( ; op != op_iter_end(); op++, n++ ) { //process operands + const operand_info &o = *op; + + if(o.is_memory_operand()) { + // We do not support the null register as a memory operand + assert( !o.is_non_arch_reg() ); + + // Check PTXPlus-type operand + // memory operand with addressing (ex. s[0x4] or g[$r1]) + if(o.is_memory_operand2()) { + + // memory operand with one address register (ex. g[$r1+0x4] or s[$r2+=0x4]) + if(o.get_double_operand_type() == 0 || o.get_double_operand_type() == 3){ + ar1 = o.reg_num(); + arch_reg.src[4] = o.arch_reg_num(); + // TODO: address register in $r2+=0x4 should be an output register as well + } + // memory operand with two address register (ex. s[$r1+$r1] or g[$r1+=$r2]) + else if(o.get_double_operand_type() == 1 || o.get_double_operand_type() == 2) { + ar1 = o.reg1_num(); + arch_reg.src[4] = o.arch_reg_num(); + ar2 = o.reg2_num(); + arch_reg.src[5] = o.arch_reg_num(); + // TODO: first address register in $r1+=$r2 should be an output register as well + } + } + else if(o.is_immediate_address()){ + + } + // Regular PTX operand + else if (o.get_symbol()->type()->get_key().is_reg()) { // Memory operand contains a register + ar1 = o.reg_num(); + arch_reg.src[4] = o.arch_reg_num(); + } + + } + } + } + + // get reconvergence pc + reconvergence_pc = get_converge_point(pc); + + m_decoded=true; +} + +void function_info::add_param_name_type_size( unsigned index, std::string name, int type, size_t size, bool ptr, memory_space_t space ) +{ + unsigned parsed_index; + char buffer[2048]; + snprintf(buffer,2048,"%s_param_%%u", m_name.c_str() ); + int ntokens = sscanf(name.c_str(),buffer,&parsed_index); + if( ntokens == 1 ) { + assert( m_ptx_kernel_param_info.find(parsed_index) == m_ptx_kernel_param_info.end() ); + m_ptx_kernel_param_info[parsed_index] = param_info(name, type, size, ptr, space); + } else { + assert( m_ptx_kernel_param_info.find(index) == m_ptx_kernel_param_info.end() ); + m_ptx_kernel_param_info[index] = param_info(name, type, size, ptr, space); + } +} + +void function_info::add_param_data( unsigned argn, struct gpgpu_ptx_sim_arg *args ) +{ + const void *data = args->m_start; + + bool scratchpad_memory_param = false; // Is this parameter in CUDA shared memory or OpenCL local memory + + std::map::iterator i=m_ptx_kernel_param_info.find(argn); + if( i != m_ptx_kernel_param_info.end() ) { + if (i->second.is_ptr_shared()) { + assert(args->m_start == NULL && "OpenCL parameter pointer to local memory must have NULL as value"); + scratchpad_memory_param = true; + } else { + param_t tmp; + tmp.pdata = args->m_start; + tmp.size = args->m_nbytes; + tmp.offset = args->m_offset; + tmp.type = 0; + i->second.add_data(tmp); + i->second.add_offset((unsigned) args->m_offset); + } + } else { + scratchpad_memory_param = true; + } + + if (scratchpad_memory_param) { + // This should only happen for OpenCL: + // + // The LLVM PTX compiler in NVIDIA's driver (version 190.29) + // does not generate an argument in the function declaration + // for __constant arguments. + // + // The associated constant memory space can be allocated in two + // ways. It can be explicitly initialized in the .ptx file where + // it is declared. Or, it can be allocated using the clCreateBuffer + // on the host. In this later case, the .ptx file will contain + // a global declaration of the parameter, but it will have an unknown + // array size. Thus, the symbol's address will not be set and we need + // to set it here before executing the PTX. + + char buffer[2048]; + snprintf(buffer,2048,"%s_param_%u",m_name.c_str(),argn); + + symbol *p = m_symtab->lookup(buffer); + if( p == NULL ) { + printf("GPGPU-Sim PTX: ERROR ** could not locate symbol for \'%s\' : cannot bind buffer\n", buffer); + abort(); + } + if( data ) + p->set_address((addr_t)*(size_t*)data); + else { + // clSetKernelArg was passed NULL pointer for data... + // this is used for dynamically sized shared memory on NVIDIA platforms + bool is_ptr_shared = false; + if( i != m_ptx_kernel_param_info.end() ) { + is_ptr_shared = i->second.is_ptr_shared(); + } + + if( !is_ptr_shared and !p->is_shared() ) { + printf("GPGPU-Sim PTX: ERROR ** clSetKernelArg passed NULL but arg not shared memory\n"); + abort(); + } + unsigned num_bits = 8*args->m_nbytes; + printf("GPGPU-Sim PTX: deferred allocation of shared region for \"%s\" from 0x%x to 0x%x (shared memory space)\n", + p->name().c_str(), + m_symtab->get_shared_next(), + m_symtab->get_shared_next() + num_bits/8 ); + fflush(stdout); + assert( (num_bits%8) == 0 ); + addr_t addr = m_symtab->get_shared_next(); + addr_t addr_pad = num_bits ? (((num_bits/8) - (addr % (num_bits/8))) % (num_bits/8)) : 0; + p->set_address( addr+addr_pad ); + m_symtab->alloc_shared( num_bits/8 + addr_pad ); + } + } +} + +unsigned function_info::get_args_aligned_size() { + + if(m_args_aligned_size >= 0) + return m_args_aligned_size; + + unsigned param_address = 0; + unsigned int total_size = 0; + for( std::map::iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { + param_info &p = i->second; + std::string name = p.get_name(); + symbol *param = m_symtab->lookup(name.c_str()); + + size_t arg_size = p.get_size() / 8; // size of param in bytes + total_size = (total_size + arg_size - 1) / arg_size * arg_size; //aligned + p.add_offset(total_size); + param->set_address(param_address + total_size); + total_size += arg_size; + } + + m_args_aligned_size = (total_size + 3) / 4 * 4; //final size aligned to word + + return m_args_aligned_size; + +} + + +void function_info::finalize( memory_space *param_mem ) +{ + unsigned param_address = 0; + for( std::map::iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { + param_info &p = i->second; + if (p.is_ptr_shared()) continue; // Pointer to local memory: Should we pass the allocated shared memory address to the param memory space? + std::string name = p.get_name(); + int type = p.get_type(); + param_t param_value = p.get_value(); + param_value.type = type; + symbol *param = m_symtab->lookup(name.c_str()); + unsigned xtype = param->type()->get_key().scalar_type(); + assert(xtype==(unsigned)type); + size_t size; + size = param_value.size; // size of param in bytes + // assert(param_value.offset == param_address); + if( size != p.get_size() / 8) { + printf("GPGPU-Sim PTX: WARNING actual kernel paramter size = %zu bytes vs. formal size = %zu (using smaller of two)\n", + size, p.get_size()/8); + size = (size<(p.get_size()/8))?size:(p.get_size()/8); + } + // copy the parameter over word-by-word so that parameter that crosses a memory page can be copied over + //Jin: copy parameter using aligned rules + const size_t word_size = 4; + param_address = (param_address + size - 1) / size * size; //aligned with size + for (size_t idx = 0; idx < size; idx += word_size) { + const char *pdata = reinterpret_cast(param_value.pdata) + idx; // cast to char * for ptr arithmetic + param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); + } + unsigned offset = p.get_offset(); + assert(offset == param_address); + param->set_address(param_address); + param_address += size; + } +} + +void function_info::param_to_shared( memory_space *shared_mem, symbol_table *symtab ) +{ + // TODO: call this only for PTXPlus with GT200 models + extern gpgpu_sim* g_the_gpu; + if (not g_the_gpu->get_config().convert_to_ptxplus()) return; + + // copies parameters into simulated shared memory + for( std::map::iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { + param_info &p = i->second; + if (p.is_ptr_shared()) continue; // Pointer to local memory: Should we pass the allocated shared memory address to the param memory space? + std::string name = p.get_name(); + int type = p.get_type(); + param_t value = p.get_value(); + value.type = type; + symbol *param = symtab->lookup(name.c_str()); + unsigned xtype = param->type()->get_key().scalar_type(); + assert(xtype==(unsigned)type); + + int tmp; + size_t size; + unsigned offset = p.get_offset(); + type_info_key::type_decode(xtype,size,tmp); + + // Write to shared memory - offset + 0x10 + shared_mem->write(offset+0x10,size/8,value.pdata,NULL,NULL); + } +} + + +void function_info::list_param( FILE *fout ) const +{ + for( std::map::const_iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { + const param_info &p = i->second; + std::string name = p.get_name(); + symbol *param = m_symtab->lookup(name.c_str()); + addr_t param_addr = param->get_address(); + fprintf(fout, "%s: %#08x\n", name.c_str(), param_addr); + } + fflush(fout); +} + +template +bool ptx_debug_exec_dump_cond(int thd_uid, addr_t pc) +{ + if (g_debug_execution >= activate_level) { + // check each type of debug dump constraint to filter out dumps + if ( (g_debug_thread_uid != 0) && (thd_uid != (unsigned)g_debug_thread_uid) ) { + return false; + } + if ( (g_debug_pc != 0xBEEF1518) && (pc != g_debug_pc) ) { + return false; + } + + return true; + } + + return false; +} + +void init_inst_classification_stat() +{ + static std::set init; + if( init.find(g_ptx_kernel_count) != init.end() ) + return; + init.insert(g_ptx_kernel_count); + + #define MAX_CLASS_KER 1024 + char kernelname[MAX_CLASS_KER] =""; + if (!g_inst_classification_stat) g_inst_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); + snprintf(kernelname, MAX_CLASS_KER, "Kernel %d Classification\n",g_ptx_kernel_count ); + assert( g_ptx_kernel_count < MAX_CLASS_KER ) ; // a static limit on number of kernels increase it if it fails! + g_inst_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,20); + if (!g_inst_op_classification_stat) g_inst_op_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); + snprintf(kernelname, MAX_CLASS_KER, "Kernel %d OP Classification\n",g_ptx_kernel_count ); + g_inst_op_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,100); +} + +static unsigned get_tex_datasize( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &src1 = pI->src1(); //the name of the texture + std::string texname = src1.name(); + + gpgpu_t *gpu = thread->get_gpu(); + const struct textureReference* texref = gpu->get_texref(texname); + const struct textureInfo* texInfo = gpu->get_texinfo(texref); + + unsigned data_size = texInfo->texel_size; + return data_size; +} + +void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) +{ + + bool skip = false; + int op_classification = 0; + addr_t pc = next_instr(); + assert( pc == inst.pc ); // make sure timing model and functional model are in sync + const ptx_instruction *pI = m_func_info->get_instruction(pc); + set_npc( pc + pI->inst_size() ); + + + try { + + clearRPC(); + m_last_set_operand_value.u64 = 0; + + if(is_done()) + { + printf("attempted to execute instruction on a thread that is already done.\n"); + assert(0); + } + + if ( g_debug_execution >= 6 || m_gpu->get_config().get_ptx_inst_debug_to_file()) { + if ( (g_debug_thread_uid==0) || (get_uid() == (unsigned)g_debug_thread_uid) ) { + + clear_modifiedregs(); + enable_debug_trace(); + } + } + + + if( pI->has_pred() ) { + const operand_info &pred = pI->get_pred(); + ptx_reg_t pred_value = get_operand_value(pred, pred, PRED_TYPE, this, 0); + if(pI->get_pred_mod() == -1) { + skip = (pred_value.pred & 0x0001) ^ pI->get_pred_neg(); //ptxplus inverts the zero flag + } else { + skip = !pred_lookup(pI->get_pred_mod(), pred_value.pred & 0x000F); + } + } + + if( skip ) { + inst.set_not_active(lane_id); + } else { + const ptx_instruction *pI_saved = pI; + ptx_instruction *pJ = NULL; + if( pI->get_opcode() == VOTE_OP ) { + pJ = new ptx_instruction(*pI); + *((warp_inst_t*)pJ) = inst; // copy active mask information + pI = pJ; + } + switch ( pI->get_opcode() ) { +#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; +#include "opcodes.def" +#undef OP_DEF +#undef OP_W_DEF + default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break; + } + delete pJ; + pI = pI_saved; + + // Run exit instruction if exit option included + if(pI->is_exit()) + exit_impl(pI,this); + } + + + + const gpgpu_functional_sim_config &config = m_gpu->get_config(); + + // Output instruction information to file and stdout + if( config.get_ptx_inst_debug_to_file() != 0 && + (config.get_ptx_inst_debug_thread_uid() == 0 || config.get_ptx_inst_debug_thread_uid() == get_uid()) ) { + fprintf(m_gpu->get_ptx_inst_debug_file(), + "[thd=%u] : (%s:%u - %s)\n", + get_uid(), + pI->source_file(), pI->source_line(), pI->get_source() ); + //fprintf(ptx_inst_debug_file, "has memory read=%d, has memory write=%d\n", pI->has_memory_read(), pI->has_memory_write()); + fflush(m_gpu->get_ptx_inst_debug_file()); + } + + if ( ptx_debug_exec_dump_cond<5>(get_uid(), pc) ) { + dim3 ctaid = get_ctaid(); + dim3 tid = get_tid(); + printf("%u [thd=%u][i=%u] : ctaid=(%u,%u,%u) tid=(%u,%u,%u) icount=%u [pc=%u] (%s:%u - %s) [0x%llx]\n", + g_ptx_sim_num_insn, + get_uid(), + pI->uid(), ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z, + get_icount(), + pc, pI->source_file(), pI->source_line(), pI->get_source(), + m_last_set_operand_value.u64 ); + fflush(stdout); + } + + addr_t insn_memaddr = 0xFEEBDAED; + memory_space_t insn_space = undefined_space; + _memory_op_t insn_memory_op = no_memory_op; + unsigned insn_data_size = 0; + if ( (pI->has_memory_read() || pI->has_memory_write()) ) { + insn_memaddr = last_eaddr(); + insn_space = last_space(); + unsigned to_type = pI->get_type(); + insn_data_size = datatype2size(to_type); + insn_memory_op = pI->has_memory_read() ? memory_load : memory_store; + } + + if ( pI->get_opcode() == BAR_OP && pI->barrier_op() == RED_OPTION) { + inst.add_callback( lane_id, last_callback().function, last_callback().instruction, this,false /*not atomic*/); + } + + if ( pI->get_opcode() == ATOM_OP ) { + insn_memaddr = last_eaddr(); + insn_space = last_space(); + inst.add_callback( lane_id, last_callback().function, last_callback().instruction, this,true /*atomic*/); + unsigned to_type = pI->get_type(); + insn_data_size = datatype2size(to_type); + } + + if (pI->get_opcode() == TEX_OP) { + inst.set_addr(lane_id, last_eaddr() ); + assert( inst.space == last_space() ); + insn_data_size = get_tex_datasize(pI, this); // texture obtain its data granularity from the texture info + } + + // Output register information to file and stdout + if( config.get_ptx_inst_debug_to_file()!=0 && + (config.get_ptx_inst_debug_thread_uid()==0||config.get_ptx_inst_debug_thread_uid()==get_uid()) ) { + dump_modifiedregs(m_gpu->get_ptx_inst_debug_file()); + dump_regs(m_gpu->get_ptx_inst_debug_file()); + } + + if ( g_debug_execution >= 6 ) { + if ( ptx_debug_exec_dump_cond<6>(get_uid(), pc) ) + dump_modifiedregs(stdout); + } + if ( g_debug_execution >= 10 ) { + if ( ptx_debug_exec_dump_cond<10>(get_uid(), pc) ) + dump_regs(stdout); + } + update_pc(); + g_ptx_sim_num_insn++; + + //not using it with functional simulation mode + if(!(this->m_functionalSimulationMode)) + ptx_file_line_stats_add_exec_count(pI); + + if ( gpgpu_ptx_instruction_classification ) { + init_inst_classification_stat(); + unsigned space_type=0; + switch ( pI->get_space().get_type() ) { + case global_space: space_type = 10; break; + case local_space: space_type = 11; break; + case tex_space: space_type = 12; break; + case surf_space: space_type = 13; break; + case param_space_kernel: + case param_space_local: + space_type = 14; break; + case shared_space: space_type = 15; break; + case const_space: space_type = 16; break; + default: + space_type = 0 ; + break; + } + StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], op_classification); + if (space_type) StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], ( int )space_type); + StatAddSample( g_inst_op_classification_stat[g_ptx_kernel_count], (int) pI->get_opcode() ); + } + if ( (g_ptx_sim_num_insn % 100000) == 0 ) { + dim3 ctaid = get_ctaid(); + dim3 tid = get_tid(); + printf("GPGPU-Sim PTX: %u instructions simulated : ctaid=(%u,%u,%u) tid=(%u,%u,%u)\n", + g_ptx_sim_num_insn, ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z ); + fflush(stdout); + } + + // "Return values" + if(!skip) { + inst.space = insn_space; + inst.set_addr(lane_id, insn_memaddr); + inst.data_size = insn_data_size; // simpleAtomicIntrinsics + assert( inst.memory_op == insn_memory_op ); + } + + } catch ( int x ) { + printf("GPGPU-Sim PTX: ERROR (%d) executing intruction (%s:%u)\n", x, pI->source_file(), pI->source_line() ); + printf("GPGPU-Sim PTX: '%s'\n", pI->get_source() ); + abort(); + } + +} + +void set_param_gpgpu_num_shaders(int num_shaders) +{ + gpgpu_param_num_shaders = num_shaders; +} + +const struct gpgpu_ptx_sim_info* ptx_sim_kernel_info(const function_info *kernel) +{ + return kernel->get_kernel_info(); +} + +const warp_inst_t *ptx_fetch_inst( address_type pc ) +{ + return function_info::pc_to_instruction(pc); +} + +unsigned ptx_sim_init_thread( kernel_info_t &kernel, + ptx_thread_info** thread_info, + int sid, + unsigned tid, + unsigned threads_left, + unsigned num_threads, + core_t *core, + unsigned hw_cta_id, + unsigned hw_warp_id, + gpgpu_t *gpu, + bool isInFunctionalSimulationMode) +{ + std::list &active_threads = kernel.active_threads(); + + static std::map shared_memory_lookup; + static std::map ptx_cta_lookup; + static std::map ptx_warp_lookup; + static std::map > local_memory_lookup; + + if ( *thread_info != NULL ) { + ptx_thread_info *thd = *thread_info; + assert( thd->is_done() ); + if ( g_debug_execution==-1 ) { + dim3 ctaid = thd->get_ctaid(); + dim3 t = thd->get_tid(); + printf("GPGPU-Sim PTX simulator: thread exiting ctaid=(%u,%u,%u) tid=(%u,%u,%u) uid=%u\n", + ctaid.x,ctaid.y,ctaid.z,t.x,t.y,t.z, thd->get_uid() ); + fflush(stdout); + } + thd->m_cta_info->register_deleted_thread(thd); + delete thd; + *thread_info = NULL; + } + + if ( !active_threads.empty() ) { + assert( active_threads.size() <= threads_left ); + ptx_thread_info *thd = active_threads.front(); + active_threads.pop_front(); + *thread_info = thd; + thd->init(gpu, core, sid, hw_cta_id, hw_warp_id, tid, isInFunctionalSimulationMode ); + return 1; + } + + if ( kernel.no_more_ctas_to_run() ) { + return 0; //finished! + } + + if ( threads_left < kernel.threads_per_cta() ) { + return 0; + } + + if ( g_debug_execution==-1 ) { + printf("GPGPU-Sim PTX simulator: STARTING THREAD ALLOCATION --> \n"); + fflush(stdout); + } + + //initializing new CTA + ptx_cta_info *cta_info = NULL; + memory_space *shared_mem = NULL; + + unsigned cta_size = kernel.threads_per_cta(); + unsigned max_cta_per_sm = num_threads/cta_size; // e.g., 256 / 48 = 5 + assert( max_cta_per_sm > 0 ); + + //unsigned sm_idx = (tid/cta_size)*gpgpu_param_num_shaders + sid; + unsigned sm_idx = hw_cta_id*gpgpu_param_num_shaders + sid; + + if ( shared_memory_lookup.find(sm_idx) == shared_memory_lookup.end() ) { + if ( g_debug_execution >= 1 ) { + printf(" : sm_idx=%u sid=%u max_cta_per_sm=%u\n", + sm_idx, sid, max_cta_per_sm ); + } + char buf[512]; + snprintf(buf,512,"shared_%u", sid); + shared_mem = new memory_space_impl<16*1024>(buf,4); + shared_memory_lookup[sm_idx] = shared_mem; + cta_info = new ptx_cta_info(sm_idx); + ptx_cta_lookup[sm_idx] = cta_info; + } else { + if ( g_debug_execution >= 1 ) { + printf(" : sm_idx=%u sid=%u max_cta_per_sm=%u\n", + sm_idx, sid, max_cta_per_sm ); + } + shared_mem = shared_memory_lookup[sm_idx]; + cta_info = ptx_cta_lookup[sm_idx]; + cta_info->check_cta_thread_status_and_reset(); + } + + std::map &local_mem_lookup = local_memory_lookup[sid]; + while( kernel.more_threads_in_cta() ) { + dim3 ctaid3d = kernel.get_next_cta_id(); + unsigned new_tid = kernel.get_next_thread_id(); + dim3 tid3d = kernel.get_next_thread_id_3d(); + kernel.increment_thread_id(); + new_tid += tid; + ptx_thread_info *thd = new ptx_thread_info(kernel); + + ptx_warp_info *warp_info = NULL; + if ( ptx_warp_lookup.find(hw_warp_id) == ptx_warp_lookup.end() ) { + warp_info = new ptx_warp_info(); + ptx_warp_lookup[hw_warp_id] = warp_info; + } else { + warp_info = ptx_warp_lookup[hw_warp_id]; + } + thd->m_warp_info = warp_info; + + memory_space *local_mem = NULL; + std::map::iterator l = local_mem_lookup.find(new_tid); + if ( l != local_mem_lookup.end() ) { + local_mem = l->second; + } else { + char buf[512]; + snprintf(buf,512,"local_%u_%u", sid, new_tid); + local_mem = new memory_space_impl<32>(buf,32); + local_mem_lookup[new_tid] = local_mem; + } + thd->set_info(kernel.entry()); + thd->set_nctaid(kernel.get_grid_dim()); + thd->set_ntid(kernel.get_cta_dim()); + thd->set_ctaid(ctaid3d); + thd->set_tid(tid3d); + if( kernel.entry()->get_ptx_version().extensions() ) + thd->cpy_tid_to_reg(tid3d); + thd->set_valid(); + thd->m_shared_mem = shared_mem; + function_info *finfo = thd->func_info(); + symbol_table *st = finfo->get_symtab(); + thd->func_info()->param_to_shared(thd->m_shared_mem,st); + thd->m_cta_info = cta_info; + cta_info->add_thread(thd); + thd->m_local_mem = local_mem; + if ( g_debug_execution==-1 ) { + printf("GPGPU-Sim PTX simulator: allocating thread ctaid=(%u,%u,%u) tid=(%u,%u,%u) @ 0x%Lx\n", + ctaid3d.x,ctaid3d.y,ctaid3d.z,tid3d.x,tid3d.y,tid3d.z, (unsigned long long)thd ); + fflush(stdout); + } + active_threads.push_back(thd); + } + if ( g_debug_execution==-1 ) { + printf("GPGPU-Sim PTX simulator: <-- FINISHING THREAD ALLOCATION\n"); + fflush(stdout); + } + + kernel.increment_cta_id(); + + assert( active_threads.size() <= threads_left ); + *thread_info = active_threads.front(); + (*thread_info)->init(gpu, core, sid, hw_cta_id, hw_warp_id, tid,isInFunctionalSimulationMode ); + active_threads.pop_front(); + return 1; +} + +size_t get_kernel_code_size( class function_info *entry ) +{ + return entry->get_function_size(); +} + + +kernel_info_t *gpgpu_opencl_ptx_sim_init_grid(class function_info *entry, + gpgpu_ptx_sim_arg_list_t args, + struct dim3 gridDim, + struct dim3 blockDim, + gpgpu_t *gpu ) +{ + kernel_info_t *result = new kernel_info_t(gridDim,blockDim,entry); + unsigned argcount=args.size(); + unsigned argn=1; + for( gpgpu_ptx_sim_arg_list_t::iterator a = args.begin(); a != args.end(); a++ ) { + entry->add_param_data(argcount-argn,&(*a)); + argn++; + } + entry->finalize(result->get_param_memory()); + g_ptx_kernel_count++; + fflush(stdout); + + return result; +} + +#include "../../version" +#include "detailed_version" + +void print_splash() +{ + static int splash_printed=0; + if ( !splash_printed ) { + fprintf(stdout, "\n\n *** %s [build %s] ***\n\n\n", g_gpgpusim_version_string, g_gpgpusim_build_string ); + splash_printed=1; + } +} + +std::map g_const_name_lookup; // indexed by hostVar +std::map g_global_name_lookup; // indexed by hostVar +std::set g_globals; +std::set g_constants; + +void gpgpu_ptx_sim_register_const_variable(void *hostVar, const char *deviceName, size_t size ) +{ + printf("GPGPU-Sim PTX registering constant %s (%zu bytes) to name mapping\n", deviceName, size ); + g_const_name_lookup[hostVar] = deviceName; +} + +void gpgpu_ptx_sim_register_global_variable(void *hostVar, const char *deviceName, size_t size ) +{ + printf("GPGPU-Sim PTX registering global %s hostVar to name mapping\n", deviceName ); + g_global_name_lookup[hostVar] = deviceName; +} + +void gpgpu_ptx_sim_memcpy_symbol(const char *hostVar, const void *src, size_t count, size_t offset, int to, gpgpu_t *gpu ) +{ + printf("GPGPU-Sim PTX: starting gpgpu_ptx_sim_memcpy_symbol with hostVar 0x%p\n", hostVar); + bool found_sym = false; + memory_space_t mem_region = undefined_space; + std::string sym_name; + + std::map::iterator c=g_const_name_lookup.find(hostVar); + if ( c!=g_const_name_lookup.end() ) { + found_sym = true; + sym_name = c->second; + mem_region = const_space; + } + std::map::iterator g=g_global_name_lookup.find(hostVar); + if ( g!=g_global_name_lookup.end() ) { + if ( found_sym ) { + printf("Execution error: PTX symbol \"%s\" w/ hostVar=0x%Lx is declared both const and global?\n", + sym_name.c_str(), (unsigned long long)hostVar ); + abort(); + } + found_sym = true; + sym_name = g->second; + mem_region = global_space; + } + if( g_globals.find(hostVar) != g_globals.end() ) { + found_sym = true; + sym_name = hostVar; + mem_region = global_space; + } + if( g_constants.find(hostVar) != g_constants.end() ) { + found_sym = true; + sym_name = hostVar; + mem_region = const_space; + } + + if ( !found_sym ) { + printf("Execution error: No information for PTX symbol w/ hostVar=0x%Lx\n", (unsigned long long)hostVar ); + abort(); + } else printf("GPGPU-Sim PTX: gpgpu_ptx_sim_memcpy_symbol: Found PTX symbol w/ hostVar=0x%Lx\n", (unsigned long long)hostVar ); + const char *mem_name = NULL; + memory_space *mem = NULL; + + std::map::iterator st = g_sym_name_to_symbol_table.find(sym_name.c_str()); + assert( st != g_sym_name_to_symbol_table.end() ); + symbol_table *symtab = st->second; + + symbol *sym = symtab->lookup(sym_name.c_str()); + assert(sym); + unsigned dst = sym->get_address() + offset; + switch (mem_region.get_type()) { + case const_space: + mem = gpu->get_global_memory(); + mem_name = "const"; + break; + case global_space: + mem = gpu->get_global_memory(); + mem_name = "global"; + break; + default: + abort(); + } + printf("GPGPU-Sim PTX: gpgpu_ptx_sim_memcpy_symbol: copying %s memory %zu bytes %s symbol %s+%zu @0x%x ...\n", + mem_name, count, (to?" to ":"from"), sym_name.c_str(), offset, dst ); + for ( unsigned n=0; n < count; n++ ) { + if( to ) mem->write(dst+n,1,((char*)src)+n,NULL,NULL); + else mem->read(dst+n,1,((char*)src)+n); + } + fflush(stdout); +} + +int g_ptx_sim_mode; // if non-zero run functional simulation only (i.e., no notion of a clock cycle) + +extern int ptx_debug; + +bool g_cuda_launch_blocking = false; + +void read_sim_environment_variables() +{ + ptx_debug = 0; + g_debug_execution = 0; + g_interactive_debugger_enabled = false; + + char *mode = getenv("PTX_SIM_MODE_FUNC"); + if ( mode ) + sscanf(mode,"%u", &g_ptx_sim_mode); + printf("GPGPU-Sim PTX: simulation mode %d (can change with PTX_SIM_MODE_FUNC environment variable:\n", g_ptx_sim_mode); + printf(" 1=functional simulation only, 0=detailed performance simulator)\n"); + char *dbg_inter = getenv("GPGPUSIM_DEBUG"); + if ( dbg_inter && strlen(dbg_inter) ) { + printf("GPGPU-Sim PTX: enabling interactive debugger\n"); + fflush(stdout); + g_interactive_debugger_enabled = true; + } + char *dbg_level = getenv("PTX_SIM_DEBUG"); + if ( dbg_level && strlen(dbg_level) ) { + printf("GPGPU-Sim PTX: setting debug level to %s\n", dbg_level ); + fflush(stdout); + sscanf(dbg_level,"%d", &g_debug_execution); + } + char *dbg_thread = getenv("PTX_SIM_DEBUG_THREAD_UID"); + if ( dbg_thread && strlen(dbg_thread) ) { + printf("GPGPU-Sim PTX: printing debug information for thread uid %s\n", dbg_thread ); + fflush(stdout); + sscanf(dbg_thread,"%d", &g_debug_thread_uid); + } + char *dbg_pc = getenv("PTX_SIM_DEBUG_PC"); + if ( dbg_pc && strlen(dbg_pc) ) { + printf("GPGPU-Sim PTX: printing debug information for instruction with PC = %s\n", dbg_pc ); + fflush(stdout); + sscanf(dbg_pc,"%d", &g_debug_pc); + } + +#if CUDART_VERSION > 1010 + g_override_embedded_ptx = false; + char *usefile = getenv("PTX_SIM_USE_PTX_FILE"); + if (usefile && strlen(usefile)) { + printf("GPGPU-Sim PTX: overriding embedded ptx with ptx file (PTX_SIM_USE_PTX_FILE is set)\n"); + fflush(stdout); + g_override_embedded_ptx = true; + } + char *blocking = getenv("CUDA_LAUNCH_BLOCKING"); + if( blocking && !strcmp(blocking,"1") ) { + g_cuda_launch_blocking = true; + } +#else + g_cuda_launch_blocking = true; + g_override_embedded_ptx = true; +#endif + + if ( g_debug_execution >= 40 ) { + ptx_debug = 1; + } +} + +ptx_cta_info *g_func_cta_info = NULL; + +#define MAX(a,b) (((a)>(b))?(a):(b)) + +/*! +This function simulates the CUDA code functionally, it takes a kernel_info_t parameter +which holds the data for the CUDA kernel to be executed +!*/ +void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL ) +{ + printf("GPGPU-Sim: Performing Functional Simulation, executing kernel %s...\n",kernel.name().c_str()); + + //using a shader core object for book keeping, it is not needed but as most function built for performance simulation need it we use it here + extern gpgpu_sim *g_the_gpu; + //before we execute, we should do PDOM analysis for functional simulation scenario. + function_info *kernel_func_info = kernel.entry(); + if (kernel_func_info->is_pdom_set()) { + printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", kernel.name().c_str() ); + } else { + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", kernel.name().c_str() ); + //kernel_func_info->do_pdom(); + kernel_func_info->set_pdom(); + } + + //we excute the kernel one CTA (Block) at the time, as synchronization functions work block wise + while(!kernel.no_more_ctas_to_run()){ + functionalCoreSim cta( + &kernel, + g_the_gpu, + g_the_gpu->getShaderCoreConfig()->warp_size + ); + cta.execute(); + +#if (CUDART_VERSION >= 5000) + launch_all_device_kernels(); +#endif + } + + //registering this kernel as done + + //openCL kernel simulation calls don't register the kernel so we don't register its exit + if(!openCL) { + extern stream_manager *g_stream_manager; + g_stream_manager->register_finished_kernel(kernel.get_uid()); + } + + //******PRINTING******* + printf( "GPGPU-Sim: Done functional simulation (%u instructions simulated).\n", g_ptx_sim_num_insn ); + if ( gpgpu_ptx_instruction_classification ) { + StatDisp( g_inst_classification_stat[g_ptx_kernel_count]); + StatDisp ( g_inst_op_classification_stat[g_ptx_kernel_count]); + } + + //time_t variables used to calculate the total simulation time + //the start time of simulation is hold by the global variable g_simulation_starttime + //g_simulation_starttime is initilized by gpgpu_ptx_sim_init_perf() in gpgpusim_entrypoint.cc upon starting gpgpu-sim + time_t end_time, elapsed_time, days, hrs, minutes, sec; + end_time = time((time_t *)NULL); + elapsed_time = MAX(end_time - g_simulation_starttime, 1); + + + //calculating and printing simulation time in terms of days, hours, minutes and seconds + days = elapsed_time/(3600*24); + hrs = elapsed_time/3600 - 24*days; + minutes = elapsed_time/60 - 60*(hrs + 24*days); + sec = elapsed_time - 60*(minutes + 60*(hrs + 24*days)); + + fflush(stderr); + printf("\n\ngpgpu_simulation_time = %u days, %u hrs, %u min, %u sec (%u sec)\n", + (unsigned)days, (unsigned)hrs, (unsigned)minutes, (unsigned)sec, (unsigned)elapsed_time ); + printf("gpgpu_simulation_rate = %u (inst/sec)\n", (unsigned)(g_ptx_sim_num_insn / elapsed_time) ); + fflush(stdout); +} + +void functionalCoreSim::initializeCTA() +{ + int ctaLiveThreads=0; + + for(int i=0; i< m_warp_count; i++){ + m_warpAtBarrier[i]=false; + m_liveThreadCount[i]=0; + } + for(int i=0; i< m_warp_count*m_warp_size;i++) + m_thread[i]=NULL; + + //get threads for a cta + for(unsigned i=0; ithreads_per_cta();i++) { + ptx_sim_init_thread(*m_kernel,&m_thread[i],0,i,m_kernel->threads_per_cta()-i,m_kernel->threads_per_cta(),this,0,i/m_warp_size,(gpgpu_t*)m_gpu, true); + assert(m_thread[i]!=NULL && !m_thread[i]->is_done()); + ctaLiveThreads++; + } + + for(int k=0;klaunch(m_thread[warpId*m_warp_size]->get_pc(),initialMask); + m_liveThreadCount[warpId]= liveThreadsCount; +} + +void functionalCoreSim::execute() + { + initializeCTA(); + + //start executing the CTA + while(true){ + bool someOneLive= false; + bool allAtBarrier = true; + for(unsigned i=0;i0) someOneLive=true; + if(!m_warpAtBarrier[i]&& m_liveThreadCount[i]>0) allAtBarrier = false; +} + +unsigned translate_pc_to_ptxlineno(unsigned pc) +{ + // this function assumes that the kernel fits inside a single PTX file + // function_info *pFunc = g_func_info; // assume that the current kernel is the one in query + const ptx_instruction *pInsn = function_info::pc_to_instruction(pc); + unsigned ptx_line_number = pInsn->source_line(); + + return ptx_line_number; +} + +// ptxinfo parser + +extern std::map get_duplicate(); + +int g_ptxinfo_error_detected; + +static char *g_ptxinfo_kname = NULL; +static struct gpgpu_ptx_sim_info g_ptxinfo; +static std::map g_duplicate; +static const char *g_last_dup_type; + +const char *get_ptxinfo_kname() +{ + return g_ptxinfo_kname; +} + +void print_ptxinfo() +{ + if(! get_ptxinfo_kname()){ + printf ("GPGPU-Sim PTX: Binary info : gmem=%u, cmem=%u\n", + g_ptxinfo.gmem, + g_ptxinfo.cmem); + } + if(get_ptxinfo_kname()){ + printf ("GPGPU-Sim PTX: Kernel \'%s\' : regs=%u, lmem=%u, smem=%u, cmem=%u\n", + get_ptxinfo_kname(), + g_ptxinfo.regs, + g_ptxinfo.lmem, + g_ptxinfo.smem, + g_ptxinfo.cmem ); + } +} + + +struct gpgpu_ptx_sim_info get_ptxinfo() +{ + return g_ptxinfo; +} + +std::map get_duplicate() +{ + return g_duplicate; +} + +void ptxinfo_linenum( unsigned linenum ) +{ + g_duplicate[linenum] = g_last_dup_type; +} + +void ptxinfo_dup_type( const char *dup_type ) +{ + g_last_dup_type = dup_type; +} + +void ptxinfo_function(const char *fname ) +{ + clear_ptxinfo(); + g_ptxinfo_kname = strdup(fname); +} + +void ptxinfo_regs( unsigned nregs ) +{ + g_ptxinfo.regs=nregs; +} + +void ptxinfo_lmem( unsigned declared, unsigned system ) +{ + g_ptxinfo.lmem=declared+system; +} + +void ptxinfo_gmem( unsigned declared, unsigned system ) +{ + g_ptxinfo.gmem=declared+system; +} + +void ptxinfo_smem( unsigned declared, unsigned system ) +{ + g_ptxinfo.smem=declared+system; +} + +void ptxinfo_cmem( unsigned nbytes, unsigned bank ) +{ + g_ptxinfo.cmem+=nbytes; +} + +void clear_ptxinfo() +{ + free(g_ptxinfo_kname); + g_ptxinfo_kname=NULL; + g_ptxinfo.regs=0; + g_ptxinfo.lmem=0; + g_ptxinfo.smem=0; + g_ptxinfo.cmem=0; + g_ptxinfo.gmem=0; + g_ptxinfo.ptx_version=0; + g_ptxinfo.sm_target=0; +} + + +void ptxinfo_opencl_addinfo( std::map &kernels ) +{ + + if(! g_ptxinfo_kname) { + printf ("GPGPU-Sim PTX: Binary info : gmem=%u, cmem=%u\n", + g_ptxinfo.gmem, + g_ptxinfo.cmem); + clear_ptxinfo(); + return; + } + + if( !strcmp("__cuda_dummy_entry__",g_ptxinfo_kname) ) { + // this string produced by ptxas for empty ptx files (e.g., bandwidth test) + clear_ptxinfo(); + return; + } + std::map::iterator k=kernels.find(g_ptxinfo_kname); + if( k==kernels.end() ) { + printf ("GPGPU-Sim PTX: ERROR ** implementation for '%s' not found.\n", g_ptxinfo_kname ); + abort(); + } else { + printf ("GPGPU-Sim PTX: Kernel \'%s\' : regs=%u, lmem=%u, smem=%u, cmem=%u\n", + g_ptxinfo_kname, + g_ptxinfo.regs, + g_ptxinfo.lmem, + g_ptxinfo.smem, + g_ptxinfo.cmem ); + function_info *finfo = k->second; + assert(finfo!=NULL); + finfo->set_kernel_info( g_ptxinfo ); + } + clear_ptxinfo(); +} + +struct rec_pts { + gpgpu_recon_t *s_kernel_recon_points; + int s_num_recon; +}; + +struct std::map g_rpts; + +struct rec_pts find_reconvergence_points( function_info *finfo ) +{ + rec_pts tmp; + std::map::iterator r=g_rpts.find(finfo); + + if( r==g_rpts.end() ) { + int num_recon = finfo->get_num_reconvergence_pairs(); + + gpgpu_recon_t *kernel_recon_points = (struct gpgpu_recon_t*) calloc(num_recon, sizeof(struct gpgpu_recon_t)); + finfo->get_reconvergence_pairs(kernel_recon_points); + printf("GPGPU-Sim PTX: reconvergence points for %s...\n", finfo->get_name().c_str() ); + for (int i=0;iprint_insn(); + printf("\n"); + printf("GPGPU-Sim PTX: immediate post dominator @ " ); + if( kernel_recon_points[i].target_inst ) + kernel_recon_points[i].target_inst->print_insn(); + printf("\n"); + } + printf("GPGPU-Sim PTX: ... end of reconvergence points for %s\n", finfo->get_name().c_str() ); + + tmp.s_kernel_recon_points = kernel_recon_points; + tmp.s_num_recon = num_recon; + g_rpts[finfo] = tmp; + } else { + tmp = r->second; + } + return tmp; +} + +address_type get_return_pc( void *thd ) +{ + // function call return + ptx_thread_info *the_thread = (ptx_thread_info*)thd; + assert( the_thread != NULL ); + return the_thread->get_return_PC(); +} + +address_type get_converge_point( address_type pc ) +{ + // the branch could encode the reconvergence point and/or a bit that indicates the + // reconvergence point is the return PC on the call stack in the case the branch has + // no immediate postdominator in the function (i.e., due to multiple return points). + + std::map::iterator f=g_pc_to_finfo.find(pc); + assert( f != g_pc_to_finfo.end() ); + function_info *finfo = f->second; + rec_pts tmp = find_reconvergence_points(finfo); + + int i=0; + for (; i < tmp.s_num_recon; ++i) { + if (tmp.s_kernel_recon_points[i].source_pc == pc) { + if( tmp.s_kernel_recon_points[i].target_pc == (unsigned) -2 ) { + return RECONVERGE_RETURN_PC; + } else { + return tmp.s_kernel_recon_points[i].target_pc; + } + } + } + return NO_BRANCH_DIVERGENCE; +} + +void functionalCoreSim::warp_exit( unsigned warp_id ) +{ + for(int i=0;im_cta_info->register_deleted_thread(m_thread[i]); + delete m_thread[i]; + } + } +} diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 5d97287..0025c52 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1471,7 +1471,12 @@ void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", target_func->get_name().c_str() ); } else { printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", target_func->get_name().c_str() ); - target_func->do_pdom(); + /* + * Some of the instructions like printf() gives the gpgpusim the wrong impression that it is a function call. + * As printf() doesnt have a body like functions do, doing pdom analysis for printf() causes a crash. + */ + if (target_func->get_function_size() >0) + target_func->do_pdom(); target_func->set_pdom(); } diff --git a/src/cuda-sim/instructions.cc~ b/src/cuda-sim/instructions.cc~ new file mode 100644 index 0000000..0e6f530 --- /dev/null +++ b/src/cuda-sim/instructions.cc~ @@ -0,0 +1,4517 @@ +// Copyright (c) 2009-2011, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda, +// Jimmy Kwa, George L. Yuan +// The University of British Columbia +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// Redistributions in binary form must reproduce the above copyright notice, this +// list of conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. +// Neither the name of The University of British Columbia nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#include "instructions.h" +#include "ptx_ir.h" +#include "opcodes.h" +#include "ptx_sim.h" +#include "ptx.tab.h" +#include +#include +#include +#include "cuda-math.h" +#include "../abstract_hardware_model.h" +#include "ptx_loader.h" +#include "cuda_device_printf.h" +#include "../gpgpu-sim/gpu-sim.h" +#include "../gpgpu-sim/shader.h" + +//Jin: include device runtime for CDP +#include "cuda_device_runtime.h" + +#include + +unsigned ptx_instruction::g_num_ptx_inst_uid=0; + +const char *g_opcode_string[NUM_OPCODES] = { +#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, +#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, +#include "opcodes.def" +#undef OP_DEF +#undef OP_W_DEF +}; + +void inst_not_implemented( const ptx_instruction * pI ) ; +ptx_reg_t srcOperandModifiers(ptx_reg_t opData, operand_info opInfo, operand_info dstInfo, unsigned type, ptx_thread_info *thread); + +void sign_extend( ptx_reg_t &data, unsigned src_size, const operand_info &dst ); + +void ptx_thread_info::set_reg( const symbol *reg, const ptx_reg_t &value ) +{ + assert( reg != NULL ); + if( reg->name() == "_" ) return; + assert( !m_regs.empty() ); + assert( reg->uid() > 0 ); + m_regs.back()[ reg ] = value; + if (m_enable_debug_trace ) + m_debug_trace_regs_modified.back()[ reg ] = value; + m_last_set_operand_value = value; +} + +ptx_reg_t ptx_thread_info::get_reg( const symbol *reg ) +{ + static bool unfound_register_warned = false; + assert( reg != NULL ); + assert( !m_regs.empty() ); + reg_map_t::iterator regs_iter = m_regs.back().find(reg); + if (regs_iter == m_regs.back().end()) { + assert( reg->type()->get_key().is_reg() ); + const std::string &name = reg->name(); + unsigned call_uid = m_callstack.back().m_call_uid; + ptx_reg_t uninit_reg; + uninit_reg.u32 = 0x0; + set_reg(reg, uninit_reg); // give it a value since we are going to warn the user anyway + std::string file_loc = get_location(); + if( !unfound_register_warned ) { + printf("GPGPU-Sim PTX: WARNING (%s) ** reading undefined register \'%s\' (cuid:%u). Setting to 0X00000000. This is okay if you are simulating the native ISA" + "\n", + file_loc.c_str(), name.c_str(), call_uid ); + unfound_register_warned = true; + } + regs_iter = m_regs.back().find(reg); + } + if (m_enable_debug_trace ) + m_debug_trace_regs_read.back()[ reg ] = regs_iter->second; + return regs_iter->second; +} + +ptx_reg_t ptx_thread_info::get_operand_value( const operand_info &op, operand_info dstInfo, unsigned opType, ptx_thread_info *thread, int derefFlag ) +{ + ptx_reg_t result, tmp; + + + if(op.get_double_operand_type() == 0) { + if(((opType != BB128_TYPE) && (opType != BB64_TYPE) && (opType != FF64_TYPE)) || (op.get_addr_space() != undefined_space)) { + if ( op.is_reg() ) { + result = get_reg( op.get_symbol() ); + } else if ( op.is_builtin()) { + result.u32 = get_builtin( op.get_int(), op.get_addr_offset() ); + } else if(op.is_immediate_address()){ + result.u64 = op.get_addr_offset(); + } else if ( op.is_memory_operand() ) { + // a few options here... + const symbol *sym = op.get_symbol(); + const type_info *type = sym->type(); + const type_info_key &info = type->get_key(); + + if ( info.is_reg() ) { + const symbol *name = op.get_symbol(); + result.u64 = get_reg(name).u64 + op.get_addr_offset(); + } else if ( info.is_param_kernel() ) { + result.u64 = sym->get_address() + op.get_addr_offset(); + } else if ( info.is_param_local() ) { + result.u64 = sym->get_address() + op.get_addr_offset(); + } else if ( info.is_global() ) { + assert( op.get_addr_offset() == 0 ); + result.u64 = sym->get_address(); + } else if ( info.is_local() ) { + result.u64 = sym->get_address() + op.get_addr_offset(); + } else if ( info.is_const() ) { + result.u64 = sym->get_address() + op.get_addr_offset(); + } else if ( op.is_shared() ) { + result.u64 = op.get_symbol()->get_address() + op.get_addr_offset(); + } else { + const char *name = op.name().c_str(); + printf("GPGPU-Sim PTX: ERROR ** get_operand_value : unknown memory operand type for %s\n", name ); + abort(); + } + + } else if ( op.is_literal() ) { + result = op.get_literal_value(); + } else if ( op.is_label() ) { + result.u64 = op.get_symbol()->get_address(); + } else if ( op.is_shared() ) { + result.u64 = op.get_symbol()->get_address(); + } else if ( op.is_const() ) { + result.u64 = op.get_symbol()->get_address(); + } else if ( op.is_global() ) { + result.u64 = op.get_symbol()->get_address(); + } else if ( op.is_local() ) { + result.u64 = op.get_symbol()->get_address(); + } else if ( op.is_function_address() ) { + result.u64 = (size_t)op.get_symbol()->get_pc(); + } else { + const char *name = op.name().c_str(); + printf("GPGPU-Sim PTX: ERROR ** get_operand_value : unknown operand type for %s\n", name ); + assert(0); + } + + if(op.get_operand_lohi() == 1) + result.u64 = result.u64 & 0xFFFF; + else if(op.get_operand_lohi() == 2) + result.u64 = (result.u64>>16) & 0xFFFF; + } else if (opType == BB128_TYPE) { + // b128 + result.u128.lowest = get_reg( op.vec_symbol(0) ).u32; + result.u128.low = get_reg( op.vec_symbol(1) ).u32; + result.u128.high = get_reg( op.vec_symbol(2) ).u32; + result.u128.highest = get_reg( op.vec_symbol(3) ).u32; + } else { + // bb64 or ff64 + result.bits.ls = get_reg( op.vec_symbol(0) ).u32; + result.bits.ms = get_reg( op.vec_symbol(1) ).u32; + } + } else if (op.get_double_operand_type() == 1) { + ptx_reg_t firstHalf, secondHalf; + firstHalf.u64 = get_reg( op.vec_symbol(0) ).u64; + secondHalf.u64 = get_reg( op.vec_symbol(1) ).u64; + if(op.get_operand_lohi() == 1) + secondHalf.u64 = secondHalf.u64 & 0xFFFF; + else if(op.get_operand_lohi() == 2) + secondHalf.u64 = (secondHalf.u64>>16) & 0xFFFF; + result.u64 = firstHalf.u64 + secondHalf.u64; + } else if (op.get_double_operand_type() == 2) { + // s[reg1 += reg2] + // reg1 is incremented after value is returned: the value returned is s[reg1] + ptx_reg_t firstHalf, secondHalf; + firstHalf.u64 = get_reg(op.vec_symbol(0)).u64; + secondHalf.u64 = get_reg(op.vec_symbol(1)).u64; + if(op.get_operand_lohi() == 1) + secondHalf.u64 = secondHalf.u64 & 0xFFFF; + else if(op.get_operand_lohi() == 2) + secondHalf.u64 = (secondHalf.u64>>16) & 0xFFFF; + result.u64 = firstHalf.u64; + firstHalf.u64 = firstHalf.u64 + secondHalf.u64; + set_reg(op.vec_symbol(0),firstHalf); + } else if (op.get_double_operand_type() == 3) { + // s[reg += immediate] + // reg is incremented after value is returned: the value returned is s[reg] + ptx_reg_t firstHalf; + firstHalf.u64 = get_reg(op.get_symbol()).u64; + result.u64 = firstHalf.u64; + firstHalf.u64 = firstHalf.u64 + op.get_addr_offset(); + set_reg(op.get_symbol(),firstHalf); + } + + ptx_reg_t finalResult; + memory_space *mem = NULL; + size_t size=0; + int t=0; + finalResult.u64=0; + + //complete other cases for reading from memory, such as reading from other const memory + if((op.get_addr_space() == global_space)&&(derefFlag)) { + // global memory - g[4], g[$r0] + mem = thread->get_global_memory(); + type_info_key::type_decode(opType,size,t); + mem->read(result.u32,size/8,&finalResult.u128); + thread->m_last_effective_address = result.u32; + thread->m_last_memory_space = global_space; + + if( opType == S16_TYPE || opType == S32_TYPE ) + sign_extend(finalResult,size,dstInfo); + } else if((op.get_addr_space() == shared_space)&&(derefFlag)) { + // shared memory - s[4], s[$r0] + mem = thread->m_shared_mem; + type_info_key::type_decode(opType,size,t); + mem->read(result.u32,size/8,&finalResult.u128); + thread->m_last_effective_address = result.u32; + thread->m_last_memory_space = shared_space; + + if( opType == S16_TYPE || opType == S32_TYPE ) + sign_extend(finalResult,size,dstInfo); + } else if((op.get_addr_space() == const_space)&&(derefFlag)) { + // const memory - ce0c1[4], ce0c1[$r0] + mem = thread->get_global_memory(); + type_info_key::type_decode(opType,size,t); + mem->read((result.u32 + op.get_const_mem_offset()),size/8,&finalResult.u128); + thread->m_last_effective_address = result.u32; + thread->m_last_memory_space = const_space; + if( opType == S16_TYPE || opType == S32_TYPE ) + sign_extend(finalResult,size,dstInfo); + } else if((op.get_addr_space() == local_space)&&(derefFlag)) { + // local memory - l0[4], l0[$r0] + mem = thread->m_local_mem; + type_info_key::type_decode(opType,size,t); + mem->read(result.u32,size/8,&finalResult.u128); + thread->m_last_effective_address = result.u32; + thread->m_last_memory_space = local_space; + if( opType == S16_TYPE || opType == S32_TYPE ) + sign_extend(finalResult,size,dstInfo); + } else { + finalResult = result; + } + + if((op.get_operand_neg() == true)&&(derefFlag)) { + switch( opType ) { + // Default to f32 for now, need to add support for others + case S8_TYPE: + case U8_TYPE: + case B8_TYPE: + finalResult.s8 = -finalResult.s8; + break; + case S16_TYPE: + case U16_TYPE: + case B16_TYPE: + finalResult.s16 = -finalResult.s16; + break; + case S32_TYPE: + case U32_TYPE: + case B32_TYPE: + finalResult.s32 = -finalResult.s32; + break; + case S64_TYPE: + case U64_TYPE: + case B64_TYPE: + finalResult.s64 = -finalResult.s64; + break; + case F16_TYPE: + finalResult.f16 = -finalResult.f16; + break; + case F32_TYPE: + finalResult.f32 = -finalResult.f32; + break; + case F64_TYPE: + case FF64_TYPE: + finalResult.f64 = -finalResult.f64; + break; + default: + assert(0); + } + + } + + return finalResult; + +} + +unsigned get_operand_nbits( const operand_info &op ) +{ + if ( op.is_reg() ) { + const symbol *sym = op.get_symbol(); + const type_info *typ = sym->type(); + type_info_key t = typ->get_key(); + switch( t.scalar_type() ) { + case PRED_TYPE: + return 1; + case B8_TYPE: case S8_TYPE: case U8_TYPE: + return 8; + case S16_TYPE: case U16_TYPE: case F16_TYPE: case B16_TYPE: + return 16; + case S32_TYPE: case U32_TYPE: case F32_TYPE: case B32_TYPE: + return 32; + case S64_TYPE: case U64_TYPE: case F64_TYPE: case B64_TYPE: + return 64; + default: + printf("ERROR: unknown register type\n"); + fflush(stdout); + abort(); + } + } else { + printf("ERROR: Need to implement get_operand_nbits() for currently unsupported operand_info type\n"); + fflush(stdout); + abort(); + } + + return 0; +} + +void ptx_thread_info::get_vector_operand_values( const operand_info &op, ptx_reg_t* ptx_regs, unsigned num_elements ) +{ + assert( op.is_vector() ); + assert( num_elements <= 4 ); // max 4 elements in a vector + + for (int idx = num_elements - 1; idx >= 0; --idx) { + const symbol *sym = NULL; + sym = op.vec_symbol(idx); + if( strcmp(sym->name().c_str(),"_") != 0) { + reg_map_t::iterator reg_iter = m_regs.back().find(sym); + assert( reg_iter != m_regs.back().end() ); + ptx_regs[idx] = reg_iter->second; + } + } +} + +void sign_extend( ptx_reg_t &data, unsigned src_size, const operand_info &dst ) +{ + if( !dst.is_reg() ) + return; + unsigned dst_size = get_operand_nbits( dst ); + if( src_size >= dst_size ) + return; + // src_size < dst_size + unsigned long long mask = 1; + mask <<= (src_size-1); + if( (mask & data.u64) == 0 ) { + // no need to sign extend + return; + } + // need to sign extend + mask = 1; + mask <<= dst_size-src_size; + mask -= 1; + mask <<= src_size; + data.u64 |= mask; +} + +void ptx_thread_info::set_operand_value( const operand_info &dst, const ptx_reg_t &data, unsigned type, ptx_thread_info *thread, const ptx_instruction *pI, int overflow, int carry ) +{ + thread->set_operand_value( dst, data, type, thread, pI ); + + if (dst.get_double_operand_type() == -2) + { + ptx_reg_t predValue; + + const symbol *sym = dst.vec_symbol(0); + predValue.u64 = (m_regs.back()[ sym ].u64) & ~(0x0C); + predValue.u64 |= ((overflow & 0x01)<<3); + predValue.u64 |= ((carry & 0x01)<<2); + + set_reg(sym,predValue); + } + else if (dst.get_double_operand_type() == 0) + { + //intentionally do nothing + } + else + { + printf("Unexpected double destination\n"); + assert(0); + } + +} + +void ptx_thread_info::set_operand_value( const operand_info &dst, const ptx_reg_t &data, unsigned type, ptx_thread_info *thread, const ptx_instruction *pI ) +{ + ptx_reg_t dstData; + memory_space *mem = NULL; + size_t size; + int t; + + type_info_key::type_decode(type,size,t); + + /*complete this section for other cases*/ + if(dst.get_addr_space() == undefined_space) + { + ptx_reg_t setValue; + setValue.u64 = data.u64; + + // Double destination in set instruction ($p0|$p1) - second is negation of first + if (dst.get_double_operand_type() == -1) + { + ptx_reg_t setValue2; + const symbol *name1 = dst.vec_symbol(0); + const symbol *name2 = dst.vec_symbol(1); + + if ( (type==F16_TYPE)||(type==F32_TYPE)||(type==F64_TYPE)||(type==FF64_TYPE) ) { + setValue2.f32 = (setValue.u64==0)?1.0f:0.0f; + } else { + setValue2.u32 = (setValue.u64==0)?0xFFFFFFFF:0; + } + + set_reg(name1,setValue); + set_reg(name2,setValue2); + } + + // Double destination in cvt,shr,mul,etc. instruction ($p0|$r4) - second register operand receives data, first predicate operand + // is set as $p0=($r4!=0) + // Also for Double destination in set instruction ($p0/$r1) + else if ((dst.get_double_operand_type() == -2)||(dst.get_double_operand_type() == -3)) + { + ptx_reg_t predValue; + const symbol *predName = dst.vec_symbol(0); + const symbol *regName = dst.vec_symbol(1); + predValue.u64 = 0; + + switch ( type ) { + case S8_TYPE: + if((setValue.s8 & 0x7F) == 0) + predValue.u64 |= 1; + break; + case S16_TYPE: + if((setValue.s16 & 0x7FFF) == 0) + predValue.u64 |= 1; + break; + case S32_TYPE: + if((setValue.s32 & 0x7FFFFFFF) == 0) + predValue.u64 |= 1; + break; + case S64_TYPE: + if((setValue.s64 & 0x7FFFFFFFFFFFFFFF) == 0) + predValue.u64 |= 1; + break; + case U8_TYPE: + case B8_TYPE: + if(setValue.u8 == 0) + predValue.u64 |= 1; + break; + case U16_TYPE: + case B16_TYPE: + if(setValue.u16 == 0) + predValue.u64 |= 1; + break; + case U32_TYPE: + case B32_TYPE: + if(setValue.u32 == 0) + predValue.u64 |= 1; + break; + case U64_TYPE: + case B64_TYPE: + if(setValue.u64 == 0) + predValue.u64 |= 1; + break; + case F16_TYPE: + if(setValue.f16 == 0) + predValue.u64 |= 1; + break; + case F32_TYPE: + if(setValue.f32 == 0) + predValue.u64 |= 1; + break; + case F64_TYPE: + case FF64_TYPE: + if(setValue.f64 == 0) + predValue.u64 |= 1; + break; + default: assert(0); break; + } + + + if ( (type==S8_TYPE)||(type==S16_TYPE)||(type==S32_TYPE)||(type==S64_TYPE)|| + (type==U8_TYPE)||(type==U16_TYPE)||(type==U32_TYPE)||(type==U64_TYPE)|| + (type==B8_TYPE)||(type==B16_TYPE)||(type==B32_TYPE)||(type==B64_TYPE)) { + if((setValue.u32 & (1<<(size-1))) != 0) + predValue.u64 |= 1<<1; + } + if ( type==F32_TYPE ) { + if(setValue.f32 < 0) + predValue.u64 |= 1<<1; + } + + if(dst.get_operand_lohi() == 1) + { + setValue.u64 = ((m_regs.back()[ regName ].u64) & (~(0xFFFF))) + (data.u64 & 0xFFFF); + } + else if(dst.get_operand_lohi() == 2) + { + setValue.u64 = ((m_regs.back()[ regName ].u64) & (~(0xFFFF0000))) + ((data.u64<<16) & 0xFFFF0000); + } + + set_reg(predName,predValue); + set_reg(regName,setValue); + } + else if (type == BB128_TYPE) + { + //b128 stuff here. + ptx_reg_t setValue2, setValue3, setValue4; + setValue.u64 = 0; + setValue2.u64 = 0; + setValue3.u64 = 0; + setValue4.u64 = 0; + setValue.u32 = data.u128.lowest; + setValue2.u32 = data.u128.low; + setValue3.u32 = data.u128.high; + setValue4.u32 = data.u128.highest; + + const symbol *name1, *name2, *name3, *name4 = NULL; + + name1 = dst.vec_symbol(0); + name2 = dst.vec_symbol(1); + name3 = dst.vec_symbol(2); + name4 = dst.vec_symbol(3); + + set_reg(name1,setValue); + set_reg(name2,setValue2); + set_reg(name3,setValue3); + set_reg(name4,setValue4); + } + else if (type == BB64_TYPE || type == FF64_TYPE) + { + //ptxplus version of storing 64 bit values to registers stores to two adjacent registers + ptx_reg_t setValue2; + setValue.u32 = 0; + setValue2.u32 = 0; + + setValue.u32 = data.bits.ls; + setValue2.u32 = data.bits.ms; + + const symbol *name1, *name2 = NULL; + + name1 = dst.vec_symbol(0); + name2 = dst.vec_symbol(1); + + set_reg(name1,setValue); + set_reg(name2,setValue2); + } + else + { + if(dst.get_operand_lohi() == 1) + { + setValue.u64 = ((m_regs.back()[ dst.get_symbol() ].u64) & (~(0xFFFF))) + (data.u64 & 0xFFFF); + } + else if(dst.get_operand_lohi() == 2) + { + setValue.u64 = ((m_regs.back()[ dst.get_symbol() ].u64) & (~(0xFFFF0000))) + ((data.u64<<16) & 0xFFFF0000); + } + set_reg(dst.get_symbol(),setValue); + } + } + + // global memory - g[4], g[$r0] + else if(dst.get_addr_space() == global_space) + { + dstData = thread->get_operand_value(dst, dst, type, thread, 0); + mem = thread->get_global_memory(); + type_info_key::type_decode(type,size,t); + + mem->write(dstData.u32,size/8,&data.u128,thread,pI); + thread->m_last_effective_address = dstData.u32; + thread->m_last_memory_space = global_space; + } + + // shared memory - s[4], s[$r0] + else if(dst.get_addr_space() == shared_space) + { + dstData = thread->get_operand_value(dst, dst, type, thread, 0); + mem = thread->m_shared_mem; + type_info_key::type_decode(type,size,t); + + mem->write(dstData.u32,size/8,&data.u128,thread,pI); + thread->m_last_effective_address = dstData.u32; + thread->m_last_memory_space = shared_space; + } + + // local memory - l0[4], l0[$r0] + else if(dst.get_addr_space() == local_space) + { + dstData = thread->get_operand_value(dst, dst, type, thread, 0); + mem = thread->m_local_mem; + type_info_key::type_decode(type,size,t); + + mem->write(dstData.u32,size/8,&data.u128,thread,pI); + thread->m_last_effective_address = dstData.u32; + thread->m_last_memory_space = local_space; + } + + else + { + printf("Destination stores to unknown location."); + assert(0); + } + + +} + +void ptx_thread_info::set_vector_operand_values( const operand_info &dst, + const ptx_reg_t &data1, + const ptx_reg_t &data2, + const ptx_reg_t &data3, + const ptx_reg_t &data4 ) +{ + unsigned num_elements = dst.get_vect_nelem(); + if (num_elements > 0) { + set_reg(dst.vec_symbol(0), data1); + if (num_elements > 1) { + set_reg(dst.vec_symbol(1), data2); + if (num_elements > 2) { + set_reg(dst.vec_symbol(2), data3); + if (num_elements > 3) { + set_reg(dst.vec_symbol(3), data4); + } + } + } + } + + m_last_set_operand_value = data1; +} + +#define my_abs(a) (((a)<0)?(-a):(a)) + +#define MY_MAX_I(a,b) (a > b) ? a : b +#define MY_MAX_F(a,b) isNaN(a) ? b : isNaN(b) ? a : (a > b) ? a : b + +#define MY_MIN_I(a,b) (a < b) ? a : b +#define MY_MIN_F(a,b) isNaN(a) ? b : isNaN(b) ? a : (a < b) ? a : b + +#define MY_INC_I(a,b) (a >= b) ? 0 : a+1 +#define MY_DEC_I(a,b) ((a == 0) || (a > b)) ? b : a-1 + +#define MY_CAS_I(a,b,c) (a == b) ? c : a + +#define MY_EXCH(a,b) b + +void abs_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case S16_TYPE: d.s16 = my_abs(a.s16); break; + case S32_TYPE: d.s32 = my_abs(a.s32); break; + case S64_TYPE: d.s64 = my_abs(a.s64); break; + case U16_TYPE: d.s16 = my_abs(a.u16); break; + case U32_TYPE: d.s32 = my_abs(a.u32); break; + case U64_TYPE: d.s64 = my_abs(a.u64); break; + case F32_TYPE: d.f32 = my_abs(a.f32); break; + case F64_TYPE: case FF64_TYPE: d.f64 = my_abs(a.f64); break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void addp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + //PTXPlus add instruction with carry (carry is kept in a predicate) register + ptx_reg_t src1_data, src2_data, src3_data, data; + int overflow = 0; + int carry = 0; + + const operand_info &dst = pI->dst(); //get operand info of sources and destination + const operand_info &src1 = pI->src1(); //use them to determine that they are of type 'register' + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + src3_data = thread->get_operand_value(src3, dst, i_type, thread, 1); + + unsigned rounding_mode = pI->rounding_mode(); + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + + //performs addition. Sets carry and overflow if needed. + //src3_data.pred&0x4 is the carry flag + switch ( i_type ) { + case S8_TYPE: + data.s64 = (src1_data.s64 & 0x0000000FF) + (src2_data.s64 & 0x0000000FF) + (src3_data.pred & 0x4); + if(((src1_data.s64 & 0x80)-(src2_data.s64 & 0x80)) == 0) {overflow=((src1_data.s64 & 0x80)-(data.s64 & 0x80))==0?0:1; } + carry = (data.u64 & 0x000000100)>>8; + break; + case S16_TYPE: + data.s64 = (src1_data.s64 & 0x00000FFFF) + (src2_data.s64 & 0x00000FFFF) + (src3_data.pred & 0x4); + if(((src1_data.s64 & 0x8000)-(src2_data.s64 & 0x8000)) == 0) {overflow=((src1_data.s64 & 0x8000)-(data.s64 & 0x8000))==0?0:1; } + carry = (data.u64 & 0x000010000)>>16; + break; + case S32_TYPE: + data.s64 = (src1_data.s64 & 0x0FFFFFFFF) + (src2_data.s64 & 0x0FFFFFFFF) + (src3_data.pred & 0x4); + if(((src1_data.s64 & 0x80000000)-(src2_data.s64 & 0x80000000)) == 0) {overflow=((src1_data.s64 & 0x80000000)-(data.s64 & 0x80000000))==0?0:1; } + carry = (data.u64 & 0x100000000)>>32; + break; + case S64_TYPE: + data.s64 = src1_data.s64 + src2_data.s64 + (src3_data.pred & 0x4); + break; + case U8_TYPE: + data.u64 = (src1_data.u64 & 0xFF) + (src2_data.u64 & 0xFF) + (src3_data.pred & 0x4); + carry = (data.u64 & 0x100)>>8; + break; + case U16_TYPE: + data.u64 = (src1_data.u64 & 0xFFFF) + (src2_data.u64 & 0xFFFF) + (src3_data.pred & 0x4); + carry = (data.u64 & 0x10000)>>16; + break; + case U32_TYPE: + data.u64 = (src1_data.u64 & 0xFFFFFFFF) + (src2_data.u64 & 0xFFFFFFFF) + (src3_data.pred & 0x4); + carry = (data.u64 & 0x100000000)>>32; + break; + case U64_TYPE: + data.s64 = src1_data.s64 + src2_data.s64 + (src3_data.pred & 0x4); + break; + case F16_TYPE: assert(0); break; + case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break; + case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break; + default: assert(0); break; + } + fesetround( orig_rm ); + + thread->set_operand_value(dst, data, i_type, thread, pI, overflow, carry ); +} + +void add_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + int overflow = 0; + int carry = 0; + + const operand_info &dst = pI->dst(); //get operand info of sources and destination + const operand_info &src1 = pI->src1(); //use them to determine that they are of type 'register' + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + unsigned rounding_mode = pI->rounding_mode(); + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + + //performs addition. Sets carry and overflow if needed. + switch ( i_type ) { + case S8_TYPE: + data.s64 = (src1_data.s64 & 0x0000000FF) + (src2_data.s64 & 0x0000000FF); + if(((src1_data.s64 & 0x80)-(src2_data.s64 & 0x80)) == 0) {overflow=((src1_data.s64 & 0x80)-(data.s64 & 0x80))==0?0:1; } + carry = (data.u64 & 0x000000100)>>8; + break; + case S16_TYPE: + data.s64 = (src1_data.s64 & 0x00000FFFF) + (src2_data.s64 & 0x00000FFFF); + if(((src1_data.s64 & 0x8000)-(src2_data.s64 & 0x8000)) == 0) {overflow=((src1_data.s64 & 0x8000)-(data.s64 & 0x8000))==0?0:1; } + carry = (data.u64 & 0x000010000)>>16; + break; + case S32_TYPE: + data.s64 = (src1_data.s64 & 0x0FFFFFFFF) + (src2_data.s64 & 0x0FFFFFFFF); + if(((src1_data.s64 & 0x80000000)-(src2_data.s64 & 0x80000000)) == 0) {overflow=((src1_data.s64 & 0x80000000)-(data.s64 & 0x80000000))==0?0:1; } + carry = (data.u64 & 0x100000000)>>32; + break; + case S64_TYPE: + data.s64 = src1_data.s64 + src2_data.s64; + break; + case U8_TYPE: + data.u64 = (src1_data.u64 & 0xFF) + (src2_data.u64 & 0xFF); + carry = (data.u64 & 0x100)>>8; + break; + case U16_TYPE: + data.u64 = (src1_data.u64 & 0xFFFF) + (src2_data.u64 & 0xFFFF); + carry = (data.u64 & 0x10000)>>16; + break; + case U32_TYPE: + data.u64 = (src1_data.u64 & 0xFFFFFFFF) + (src2_data.u64 & 0xFFFFFFFF); + carry = (data.u64 & 0x100000000)>>32; + break; + case U64_TYPE: + data.u64 = src1_data.u64 + src2_data.u64; + break; + case F16_TYPE: assert(0); break; + case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break; + case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break; + default: assert(0); break; + } + fesetround( orig_rm ); + + thread->set_operand_value(dst, data, i_type, thread, pI, overflow, carry ); +} + +void addc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } + +void and_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + //the way ptxplus handles predicates: 1 = false and 0 = true + if(i_type == PRED_TYPE) + data.pred = ~(~(src1_data.pred) & ~(src2_data.pred)); + else + data.u64 = src1_data.u64 & src2_data.u64; + + thread->set_operand_value(dst,data, i_type, thread, pI); +} + +void andn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + switch ( i_type ) { + case B16_TYPE: src2_data.u16 = ~src2_data.u16; break; + case B32_TYPE: src2_data.u32 = ~src2_data.u32; break; + case B64_TYPE: src2_data.u64 = ~src2_data.u64; break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + data.u64 = src1_data.u64 & src2_data.u64; + + thread->set_operand_value(dst,data, i_type, thread, pI); +} + +void bar_callback( const inst_t* inst, ptx_thread_info* thread) +{ + unsigned ctaid = thread->get_cta_uid(); + unsigned barid = inst->bar_id; + unsigned value = thread->get_reduction_value(ctaid,barid); + const ptx_instruction *pI = dynamic_cast(inst); + const operand_info &dst = pI->dst(); + ptx_reg_t data; + data.u32 = value; + thread->set_operand_value(dst,value, U32_TYPE, thread, pI); +} + +void atom_callback( const inst_t* inst, ptx_thread_info* thread) +{ + const ptx_instruction *pI = dynamic_cast(inst); + + // "Decode" the output type + unsigned to_type = pI->get_type(); + size_t size; + int t; + type_info_key::type_decode(to_type, size, t); + + // Set up operand variables + ptx_reg_t data; // d + ptx_reg_t src1_data; // a + ptx_reg_t src2_data; // b + ptx_reg_t op_result; // temp variable to hold operation result + + bool data_ready = false; + + // Get operand info of sources and destination + const operand_info &dst = pI->dst(); // d + const operand_info &src1 = pI->src1(); // a + const operand_info &src2 = pI->src2(); // b + + // Get operand values + src1_data = thread->get_operand_value(src1, src1, to_type, thread, 1); // a + if (dst.get_symbol()->type()){ + src2_data = thread->get_operand_value(src2, dst, to_type, thread, 1); // b + } else { + //This is the case whent he first argument (dest) is '_' + src2_data = thread->get_operand_value(src2, src1, to_type, thread, 1); // b + } + + // Check state space + addr_t effective_address = src1_data.u64; + memory_space_t space = pI->get_space(); + if (space == undefined_space) { + // generic space - determine space via address + if( whichspace(effective_address) == global_space ) { + effective_address = generic_to_global(effective_address); + space = global_space; + } else if( whichspace(effective_address) == shared_space ) { + unsigned smid = thread->get_hw_sid(); + effective_address = generic_to_shared(smid,effective_address); + space = shared_space; + } else { + abort(); + } + } + assert( space == global_space || space == shared_space ); + + memory_space *mem = NULL; + if(space == global_space) + mem = thread->get_global_memory(); + else if(space == shared_space) + mem = thread->m_shared_mem; + else + abort(); + + // Copy value pointed to in operand 'a' into register 'd' + // (i.e. copy src1_data to dst) + mem->read(effective_address,size/8,&data.s64); + if (dst.get_symbol()->type()){ + thread->set_operand_value(dst, data, to_type, thread, pI); // Write value into register 'd' + } + + // Get the atomic operation to be performed + unsigned m_atomic_spec = pI->get_atomic(); + + switch ( m_atomic_spec ) { + // AND + case ATOMIC_AND: + { + + switch ( to_type ) { + case B32_TYPE: + case U32_TYPE: + op_result.u32 = data.u32 & src2_data.u32; + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = data.s32 & src2_data.s32; + data_ready = true; + break; + default: + printf("Execution error: type mismatch (%x) with instruction\natom.AND only accepts b32\n", to_type); + assert(0); + break; + } + + break; + } + // OR + case ATOMIC_OR: + { + + switch ( to_type ) { + case B32_TYPE: + case U32_TYPE: + op_result.u32 = data.u32 | src2_data.u32; + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = data.s32 | src2_data.s32; + data_ready = true; + break; + default: + printf("Execution error: type mismatch (%x) with instruction\natom.OR only accepts b32\n", to_type); + assert(0); + break; + } + + break; + } + // XOR + case ATOMIC_XOR: + { + + switch ( to_type ) { + case B32_TYPE: + case U32_TYPE: + op_result.u32 = data.u32 ^ src2_data.u32; + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = data.s32 ^ src2_data.s32; + data_ready = true; + break; + default: + printf("Execution error: type mismatch (%x) with instruction\natom.XOR only accepts b32\n", to_type); + assert(0); + break; + } + + break; + } + // CAS + case ATOMIC_CAS: + { + + ptx_reg_t src3_data; + const operand_info &src3 = pI->src3(); + src3_data = thread->get_operand_value(src3, dst, to_type, thread, 1); + + switch ( to_type ) { + case B32_TYPE: + case U32_TYPE: + op_result.u32 = MY_CAS_I(data.u32, src2_data.u32, src3_data.u32); + data_ready = true; + break; + case B64_TYPE: + case U64_TYPE: + op_result.u64 = MY_CAS_I(data.u64, src2_data.u64, src3_data.u64); + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = MY_CAS_I(data.s32, src2_data.s32, src3_data.s32); + data_ready = true; + break; + default: + printf("Execution error: type mismatch (%x) with instruction\natom.CAS only accepts b32 and b64\n", to_type); + assert(0); + break; + } + + break; + } + // EXCH + case ATOMIC_EXCH: + { + switch ( to_type ) { + case B32_TYPE: + case U32_TYPE: + op_result.u32 = MY_EXCH(data.u32, src2_data.u32); + data_ready = true; + break; + case B64_TYPE: + case U64_TYPE: + op_result.u64 = MY_EXCH(data.u64, src2_data.u64); + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = MY_EXCH(data.s32, src2_data.s32); + data_ready = true; + break; + default: + printf("Execution error: type mismatch (%x) with instruction\natom.EXCH only accepts b32\n", to_type); + assert(0); + break; + } + + break; + } + // ADD + case ATOMIC_ADD: + { + + switch ( to_type ) { + case U32_TYPE: + op_result.u32 = data.u32 + src2_data.u32; + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = data.s32 + src2_data.s32; + data_ready = true; + break; + case U64_TYPE: + op_result.u64 = data.u64 + src2_data.u64; + data_ready = true; + break; + case F32_TYPE: + op_result.f32 = data.f32 + src2_data.f32; + data_ready = true; + break; + default: + printf("Execution error: type mismatch with instruction\natom.ADD only accepts u32, s32, u64, and f32\n"); + assert(0); + break; + } + + break; + } + // INC + case ATOMIC_INC: + { + switch ( to_type ) { + case U32_TYPE: + op_result.u32 = MY_INC_I(data.u32, src2_data.u32); + data_ready = true; + break; + default: + printf("Execution error: type mismatch with instruction\natom.INC only accepts u32 and s32\n"); + assert(0); + break; + } + + break; + } + // DEC + case ATOMIC_DEC: + { + switch ( to_type ) { + case U32_TYPE: + op_result.u32 = MY_DEC_I(data.u32, src2_data.u32); + data_ready = true; + break; + default: + printf("Execution error: type mismatch with instruction\natom.DEC only accepts u32 and s32\n"); + assert(0); + break; + } + + break; + } + // MIN + case ATOMIC_MIN: + { + switch ( to_type ) { + case U32_TYPE: + op_result.u32 = MY_MIN_I(data.u32, src2_data.u32); + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = MY_MIN_I(data.s32, src2_data.s32); + data_ready = true; + break; + default: + printf("Execution error: type mismatch with instruction\natom.MIN only accepts u32 and s32\n"); + assert(0); + break; + } + + break; + } + // MAX + case ATOMIC_MAX: + { + switch ( to_type ) { + case U32_TYPE: + op_result.u32 = MY_MAX_I(data.u32, src2_data.u32); + data_ready = true; + break; + case S32_TYPE: + op_result.s32 = MY_MAX_I(data.s32, src2_data.s32); + data_ready = true; + break; + default: + printf("Execution error: type mismatch with instruction\natom.MAX only accepts u32 and s32\n"); + assert(0); + break; + } + + break; + } + // DEFAULT + default: + { + assert(0); + break; + } + } + + // Write operation result into memory + // (i.e. copy src1_data to dst) + if ( data_ready ) { + mem->write(effective_address,size/8,&op_result.s64,thread,pI); + } else { + printf("Execution error: data_ready not set\n"); + assert(0); + } +} + +// atom_impl will now result in a callback being called in mem_ctrl_pop (gpu-sim.c) +void atom_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + // SYNTAX + // atom.space.operation.type d, a, b[, c]; (now read in callback) + + // obtain memory space of the operation + memory_space_t space = pI->get_space(); + + // get the memory address + const operand_info &src1 = pI->src1(); + // const operand_info &dst = pI->dst(); // not needed for effective address calculation + unsigned i_type = pI->get_type(); + ptx_reg_t src1_data; + src1_data = thread->get_operand_value(src1, src1, i_type, thread, 1); + addr_t effective_address = src1_data.u64; + + addr_t effective_address_final; + + // handle generic memory space by converting it to global + if ( space == undefined_space ) { + if( whichspace(effective_address) == global_space ) { + effective_address_final = generic_to_global(effective_address); + space = global_space; + } else if( whichspace(effective_address) == shared_space ) { + unsigned smid = thread->get_hw_sid(); + effective_address_final = generic_to_shared(smid,effective_address); + space = shared_space; + } else { + abort(); + } + } else { + assert( space == global_space || space == shared_space ); + effective_address_final = effective_address; + } + + // Check state space + assert( space == global_space || space == shared_space ); + + thread->m_last_effective_address = effective_address_final; + thread->m_last_memory_space = space; + thread->m_last_dram_callback.function = atom_callback; + thread->m_last_dram_callback.instruction = pI; +} + +void bar_impl( const ptx_instruction *pIin, ptx_thread_info *thread ) +{ + ptx_instruction * pI = const_cast(pIin); + unsigned bar_op = pI->barrier_op(); + unsigned red_op = pI->get_atomic(); + unsigned ctaid = thread->get_cta_uid(); + + switch(bar_op){ + case SYNC_OPTION: + { + if(pI->get_num_operands()>1){ + const operand_info &op0 = pI->dst(); + const operand_info &op1 = pI->src1(); + ptx_reg_t op0_data; + ptx_reg_t op1_data; + op0_data = thread->get_operand_value(op0, op0, U32_TYPE, thread, 1); + op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); + pI->set_bar_id(op0_data.u32); + pI->set_bar_count(op1_data.u32); + }else{ + const operand_info &op0 = pI->dst(); + ptx_reg_t op0_data; + op0_data = thread->get_operand_value(op0, op0, U32_TYPE, thread, 1); + pI->set_bar_id(op0_data.u32); + } + break; + } + case ARRIVE_OPTION: + { + const operand_info &op0 = pI->dst(); + const operand_info &op1 = pI->src1(); + ptx_reg_t op0_data; + ptx_reg_t op1_data; + op0_data = thread->get_operand_value(op0, op0, U32_TYPE, thread, 1); + op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); + pI->set_bar_id(op0_data.u32); + pI->set_bar_count(op1_data.u32); + break; + } + case RED_OPTION: + { + if(pI->get_num_operands()>3){ + const operand_info &op1 = pI->src1(); + const operand_info &op2 = pI->src2(); + const operand_info &op3 = pI->src3(); + ptx_reg_t op1_data; + ptx_reg_t op2_data; + ptx_reg_t op3_data; + op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); + op2_data = thread->get_operand_value(op2, op2, U32_TYPE, thread, 1); + op3_data = thread->get_operand_value(op3, op3, PRED_TYPE, thread, 1); + op3_data.u32=!(op3_data.pred & 0x0001); + pI->set_bar_id(op1_data.u32); + pI->set_bar_count(op2_data.u32); + switch(red_op){ + case ATOMIC_POPC: + thread->popc_reduction(ctaid,op1_data.u32,op3_data.u32); + break; + case ATOMIC_AND: + thread->and_reduction(ctaid,op1_data.u32,op3_data.u32); + break; + case ATOMIC_OR: + thread->or_reduction(ctaid,op1_data.u32,op3_data.u32); + break; + default: + abort(); + break; + } + }else{ + const operand_info &op1 = pI->src1(); + const operand_info &op2 = pI->src2(); + ptx_reg_t op1_data; + ptx_reg_t op2_data; + op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); + op2_data = thread->get_operand_value(op2, op2, PRED_TYPE, thread, 1); + op2_data.u32=!(op2_data.pred & 0x0001); + pI->set_bar_id(op1_data.u32); + switch(red_op){ + case ATOMIC_POPC: + thread->popc_reduction(ctaid,op1_data.u32,op2_data.u32); + break; + case ATOMIC_AND: + thread->and_reduction(ctaid,op1_data.u32,op2_data.u32); + break; + case ATOMIC_OR: + thread->or_reduction(ctaid,op1_data.u32,op2_data.u32); + break; + default: + abort(); + break; + } + } + break; + } + default: + abort(); + break; + } + + thread->m_last_dram_callback.function = bar_callback; + thread->m_last_dram_callback.instruction = pIin; +} + +void bfe_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + unsigned i_type = pI->get_type(); + unsigned msb = (i_type == U32_TYPE || i_type == S32_TYPE) ? 31 : 63; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); + ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); + ptx_reg_t c = thread->get_operand_value(src3, dst, i_type, thread, 1); + unsigned pos = b.u32 & 0xFF; + unsigned len = c.u32 & 0xFF; + unsigned d = 0; + switch (i_type) + { + case U32_TYPE: + { + unsigned mask; + d = a.u32 >> pos; + mask = 0xFFFFFFFF >> (32 - len); + d &= mask; + break; + } + case U64_TYPE: + { + unsigned long mask; + d = a.u64 >> pos; + mask = 0xFFFFFFFFFFFFFFFF >> (64 - len); + d &= mask; + break; + } + case S32_TYPE: + { + unsigned mask; + unsigned min = MY_MIN_I(pos + len - 1, msb); + unsigned sbit = len == 0 ? 0 : (a.s32 >> min) & 0x1; + d = a.s32 >> pos; + if (sbit > 0) + { + mask = 0xFFFFFFFF << len; + d |= mask; + } + else + { + mask = 0xFFFFFFFF >> (32 - len); + d &= mask; + } + break; + } + case S64_TYPE: + { + unsigned long mask; + unsigned min = MY_MIN_I(pos + len - 1, msb); + unsigned sbit = len == 0 ? 0 : (a.s64 >> min) & 0x1; + d = a.s64 >> pos; + if (sbit > 0) + { + mask = 0xFFFFFFFFFFFFFFFF << len; + d |= mask; + } + else + { + mask = 0xFFFFFFFFFFFFFFFF >> (64 - len); + d &= mask; + } + break; + } + default: + printf("Operand type not supported for BFE instruction.\n"); + abort(); + return; + } + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void bfi_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void bfind_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } + +void bra_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &target = pI->dst(); + ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); + + thread->m_branch_taken = true; + thread->set_npc(target_pc); +} + +void brx_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &target = pI->dst(); + ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); + + thread->m_branch_taken = true; + thread->set_npc(target_pc); +} + +void break_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &target = thread->pop_breakaddr(); + ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); + + thread->m_branch_taken = true; + thread->set_npc(target_pc); +} + +void breakaddr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &target = pI->dst(); + thread->push_breakaddr(target); + assert(pI->has_pred() == false); // pdom analysis cannot handle if this instruction is predicated +} + +void brev_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } + +void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + static unsigned call_uid_next = 1; + + const operand_info &target = pI->func_addr(); + assert( target.is_function_address() ); + const symbol *func_addr = target.get_symbol(); + function_info *target_func = func_addr->get_pc(); + if (target_func->is_pdom_set()) { + printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", target_func->get_name().c_str() ); + } else { + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", target_func->get_name().c_str() ); + if (target_func->get_function_size() >0) + target_func->do_pdom(); + target_func->set_pdom(); + } + + // check that number of args and return match function requirements + if( pI->has_return() ^ target_func->has_return() ) { + printf("GPGPU-Sim PTX: Execution error - mismatch in number of return values between\n" + " call instruction and function declaration\n"); + abort(); + } + unsigned n_return = target_func->has_return(); + unsigned n_args = target_func->num_args(); + unsigned n_operands = pI->get_num_operands(); + + if( n_operands != (n_return+1+n_args) ) { + printf("GPGPU-Sim PTX: Execution error - mismatch in number of arguements between\n" + " call instruction and function declaration\n"); + abort(); + } + + // handle intrinsic functions + std::string fname = target_func->get_name(); + if( fname == "vprintf" ) { + gpgpusim_cuda_vprintf(pI, thread, target_func); + return; + } + +#if (CUDART_VERSION >= 5000) + //Jin: handle device runtime apis for CDP + else if(fname == "cudaGetParameterBufferV2") { + gpgpusim_cuda_getParameterBufferV2(pI, thread, target_func); + return; + } + else if(fname == "cudaLaunchDeviceV2") { + gpgpusim_cuda_launchDeviceV2(pI, thread, target_func); + return; + } + else if(fname == "cudaStreamCreateWithFlags") { + gpgpusim_cuda_streamCreateWithFlags(pI, thread, target_func); + return; + } +#endif + + // read source arguements into register specified in declaration of function + arg_buffer_list_t arg_values; + copy_args_into_buffer_list(pI, thread, target_func, arg_values); + + // record local for return value (we only support a single return value) + const symbol *return_var_src = NULL; + const symbol *return_var_dst = NULL; + if( target_func->has_return() ) { + return_var_dst = pI->dst().get_symbol(); + return_var_src = target_func->get_return_var(); + } + + gpgpu_sim *gpu = thread->get_gpu(); + unsigned callee_pc=0, callee_rpc=0; + if( gpu->simd_model() == POST_DOMINATOR ) { + thread->get_core()->get_pdom_stack_top_info(thread->get_hw_wid(),&callee_pc,&callee_rpc); + assert( callee_pc == thread->get_pc() ); + } + + thread->callstack_push(callee_pc + pI->inst_size(), callee_rpc, return_var_src, return_var_dst, call_uid_next++); + + copy_buffer_list_into_frame(thread, arg_values); + + thread->set_npc(target_func); +} + +//Ptxplus version of call instruction. Jumps to a label not a different Kernel. +void callp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + + static unsigned call_uid_next = 1; + + const operand_info &target = pI->dst(); + ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); + + const symbol *return_var_src = NULL; + const symbol *return_var_dst = NULL; + + gpgpu_sim *gpu = thread->get_gpu(); + unsigned callee_pc=0, callee_rpc=0; + if( gpu->simd_model() == POST_DOMINATOR ) { + thread->get_core()->get_pdom_stack_top_info(thread->get_hw_wid(),&callee_pc,&callee_rpc); + assert( callee_pc == thread->get_pc() ); + } + + thread->callstack_push_plus(callee_pc + pI->inst_size(), callee_rpc, return_var_src, return_var_dst, call_uid_next++); + thread->set_npc(target_pc); +} + +void clz_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + int max; + unsigned long long mask; + d.u64 = 0; + + switch ( i_type ) { + case B32_TYPE: + max = 32; + mask = 0x80000000; + break; + case B64_TYPE: + max = 64; + mask = 0x8000000000000000; + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + while ((d.u32 < max) && ((a.u64&mask) == 0) ) { + d.u32++; + a.u64 = a.u64 << 1; + } + + thread->set_operand_value(dst,d, B32_TYPE, thread, pI); +} + +void cnot_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + switch ( i_type ) { + case PRED_TYPE: d.pred = ((a.pred & 0x0001) == 0)?1:0; break; + case B16_TYPE: d.u16 = (a.u16 == 0)?1:0; break; + case B32_TYPE: d.u32 = (a.u32 == 0)?1:0; break; + case B64_TYPE: d.u64 = (a.u64 == 0)?1:0; break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void cos_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case F32_TYPE: + d.f32 = cos(a.f32); + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +ptx_reg_t chop( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + switch ( to_width ) { + case 8: x.mask_and(0,0xFF); break; + case 16: x.mask_and(0,0xFFFF); break; + case 32: x.mask_and(0,0xFFFFFFFF); break; + case 64: break; + default: assert(0); + } + return x; +} + +ptx_reg_t sext( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + x=chop(x,0,from_width,0,rounding_mode,saturation_mode); + switch ( from_width ) { + case 8: if ( x.get_bit(7) ) x.mask_or(0xFFFFFFFF,0xFFFFFF00);break; + case 16:if ( x.get_bit(15) ) x.mask_or(0xFFFFFFFF,0xFFFF0000);break; + case 32: if ( x.get_bit(31) ) x.mask_or(0xFFFFFFFF,0x00000000);break; + case 64: break; + default: assert(0); + } + return x; +} + +// sign extend depending on the destination register size - hack to get SobelFilter working in CUDA 4.2 +ptx_reg_t sexd( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + x=chop(x,0,from_width,0,rounding_mode,saturation_mode); + switch ( to_width ) { + case 8: if ( x.get_bit(7) ) x.mask_or(0xFFFFFFFF,0xFFFFFF00);break; + case 16:if ( x.get_bit(15) ) x.mask_or(0xFFFFFFFF,0xFFFF0000);break; + case 32: if ( x.get_bit(31) ) x.mask_or(0xFFFFFFFF,0x00000000);break; + case 64: break; + default: assert(0); + } + return x; +} + +ptx_reg_t zext( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + return chop(x,0,from_width,0,rounding_mode,saturation_mode); +} + +int saturatei(int a, int max, int min) +{ + if (a > max) a = max; + else if (a < min) a = min; + return a; +} + +unsigned int saturatei(unsigned int a, unsigned int max) +{ + if (a > max) a = max; + return a; +} + +ptx_reg_t f2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + assert( from_width == 32); + + enum cuda_math::cudaRoundMode mode = cuda_math::cudaRoundZero; + switch (rounding_mode) { + case RZI_OPTION: mode = cuda_math::cudaRoundZero; break; + case RNI_OPTION: mode = cuda_math::cudaRoundNearest; break; + case RMI_OPTION: mode = cuda_math::cudaRoundMinInf; break; + case RPI_OPTION: mode = cuda_math::cudaRoundPosInf; break; + default: break; + } + + ptx_reg_t y; + if ( to_sign == 1 ) { // convert to 64-bit number first? + int tmp = cuda_math::float2int(x.f32, mode); + if ((x.u32 & 0x7f800000) == 0) + tmp = 0; // round denorm. FP to 0 + if (saturation_mode && to_width < 32) { + tmp = saturatei(tmp, (1< max) a = max; + else if (a < min) a = min; + return a; +} + +ptx_reg_t d2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + assert( from_width == 64); + + double tmp; + switch (rounding_mode) { + case RZI_OPTION: tmp = trunc(x.f64); break; + case RNI_OPTION: tmp = nearbyint(x.f64); break; + case RMI_OPTION: tmp = floor(x.f64); break; + case RPI_OPTION: tmp = ceil(x.f64); break; + default: tmp = x.f64; break; + } + + ptx_reg_t y; + if ( to_sign == 1 ) { + tmp = saturated2i(tmp, ((1<<(to_width - 1)) - 1), (1<<(to_width - 1)) ); + switch ( to_width ) { + case 8: y.s8 = (char)tmp; break; + case 16: y.s16 = (short)tmp; break; + case 32: y.s32 = (int)tmp; break; + case 64: y.s64 = (long long)tmp; break; + default: assert(0); break; + } + } else if ( to_sign == 0 ) { + tmp = saturated2i(tmp, ((1<<(to_width - 1)) - 1), 0); + switch ( to_width ) { + case 8: y.u8 = (unsigned char)tmp; break; + case 16: y.u16 = (unsigned short)tmp; break; + case 32: y.u32 = (unsigned int)tmp; break; + case 64: y.u64 = (unsigned long long)tmp; break; + default: assert(0); break; + } + } else { + switch ( to_width ) { + case 16: assert(0); break; + case 32: + y.f32 = x.f64; + break; + case 64: + y.f64 = x.f64; // should be handled by d2d + break; + default: assert(0); break; + } + } + return y; +} + +ptx_reg_t s2f( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + ptx_reg_t y; + + if (from_width < 64) { // 32-bit conversion + y = sext(x,from_width,32,0,rounding_mode,saturation_mode); + + switch ( to_width ) { + case 16: assert(0); break; + case 32: + switch (rounding_mode) { + case RZ_OPTION: y.f32 = cuda_math::__int2float_rz(y.s32); break; + case RN_OPTION: y.f32 = cuda_math::__int2float_rn(y.s32); break; + case RM_OPTION: y.f32 = cuda_math::__int2float_rd(y.s32); break; + case RP_OPTION: y.f32 = cuda_math::__int2float_ru(y.s32); break; + default: break; + } + break; + case 64: y.f64 = y.s32; break; // no rounding needed + default: assert(0); break; + } + } else { + switch ( to_width ) { + case 16: assert(0); break; + case 32: + switch (rounding_mode) { + case RZ_OPTION: y.f32 = cuda_math::__ll2float_rz(y.s64); break; + case RN_OPTION: y.f32 = cuda_math::__ll2float_rn(y.s64); break; + case RM_OPTION: y.f32 = cuda_math::__ll2float_rd(y.s64); break; + case RP_OPTION: y.f32 = cuda_math::__ll2float_ru(y.s64); break; + default: break; + } + break; + case 64: y.f64 = y.s64; break; // no internal implementation found + default: assert(0); break; + } + } + + // saturating an integer to 1 or 0? + return y; +} + +ptx_reg_t u2f( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + ptx_reg_t y; + + if (from_width < 64) { // 32-bit conversion + y = zext(x,from_width,32,0,rounding_mode,saturation_mode); + + switch ( to_width ) { + case 16: assert(0); break; + case 32: + switch (rounding_mode) { + case RZ_OPTION: y.f32 = cuda_math::__uint2float_rz(y.u32); break; + case RN_OPTION: y.f32 = cuda_math::__uint2float_rn(y.u32); break; + case RM_OPTION: y.f32 = cuda_math::__uint2float_rd(y.u32); break; + case RP_OPTION: y.f32 = cuda_math::__uint2float_ru(y.u32); break; + default: break; + } + break; + case 64: y.f64 = y.u32; break; // no rounding needed + default: assert(0); break; + } + } else { + switch ( to_width ) { + case 16: assert(0); break; + case 32: + switch (rounding_mode) { + case RZ_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; + case RN_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; + case RM_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; + case RP_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; + default: break; + } + break; + case 64: y.f64 = y.u64; break; // no internal implementation found + default: assert(0); break; + } + } + + // saturating an integer to 1 or 0? + return y; +} + +ptx_reg_t f2f( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + ptx_reg_t y; + switch ( rounding_mode ) { + case RZI_OPTION: + y.f32 = truncf(x.f32); + break; + case RNI_OPTION: +#if CUDART_VERSION >= 3000 + y.f32 = nearbyintf(x.f32); +#else + y.f32 = cuda_math::__internal_nearbyintf(x.f32); +#endif + break; + case RMI_OPTION: + if ((x.u32 & 0x7f800000) == 0) { + y.u32 = x.u32 & 0x80000000; // round denorm. FP to 0, keeping sign + } else { + y.f32 = floorf(x.f32); + } + break; + case RPI_OPTION: + if ((x.u32 & 0x7f800000) == 0) { + y.u32 = x.u32 & 0x80000000; // round denorm. FP to 0, keeping sign + } else { + y.f32 = ceilf(x.f32); + } + break; + default: + if ((x.u32 & 0x7f800000) == 0) { + y.u32 = x.u32 & 0x80000000; // round denorm. FP to 0, keeping sign + } else { + y.f32 = x.f32; + } + break; + } +#if CUDART_VERSION >= 3000 + if (isnanf(y.f32)) +#else + if (cuda_math::__cuda___isnanf(y.f32)) +#endif + { + y.u32 = 0x7fffffff; + } else if (saturation_mode) { + y.f32 = cuda_math::__saturatef(y.f32); + } + + return y; +} + +ptx_reg_t d2d( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) +{ + ptx_reg_t y; + switch ( rounding_mode ) { + case RZI_OPTION: + y.f64 = trunc(x.f64); + break; + case RNI_OPTION: +#if CUDART_VERSION >= 3000 + y.f64 = nearbyint(x.f64); +#else + y.f64 = cuda_math::__internal_nearbyintf(x.f64); +#endif + break; + case RMI_OPTION: + y.f64 = floor(x.f64); + break; + case RPI_OPTION: + y.f64 = ceil(x.f64); + break; + default: + y.f64 = x.f64; + break; + } + if (std::isnan(y.f64)) { + y.u64 = 0xfff8000000000000ull; + } else if (saturation_mode) { + y.f64 = cuda_math::__saturatef(y.f64); + } + return y; +} + +ptx_reg_t (*g_cvt_fn[11][11])( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, + int rounding_mode, int saturation_mode ) = { + { NULL, sext, sext, sext, NULL, sext, sext, sext, s2f, s2f, s2f}, + { chop, NULL, sext, sext, chop, NULL, sext, sext, s2f, s2f, s2f}, + { chop, sexd, NULL, sext, chop, chop, NULL, sext, s2f, s2f, s2f}, + { chop, chop, chop, NULL, chop, chop, chop, NULL, s2f, s2f, s2f}, + { NULL, zext, zext, zext, NULL, zext, zext, zext, u2f, u2f, u2f}, + { chop, NULL, zext, zext, chop, NULL, zext, zext, u2f, u2f, u2f}, + { chop, chop, NULL, zext, chop, chop, NULL, zext, u2f, u2f, u2f}, + { chop, chop, chop, NULL, chop, chop, chop, NULL, u2f, u2f, u2f}, + { f2x , f2x , f2x , f2x , f2x , f2x , f2x , f2x , NULL,f2x, f2x}, + { f2x , f2x , f2x , f2x , f2x , f2x , f2x , f2x , f2x, f2f, f2x}, + { d2x , d2x , d2x , d2x , d2x , d2x , d2x , d2x , d2x, d2x, d2d} +}; + +void ptx_round(ptx_reg_t& data, int rounding_mode, int type) +{ + if (rounding_mode == RN_OPTION) { + return; + } + switch ( rounding_mode ) { + case RZI_OPTION: + switch ( type ) { + case S8_TYPE: + case S16_TYPE: + case S32_TYPE: + case S64_TYPE: + case U8_TYPE: + case U16_TYPE: + case U32_TYPE: + case U64_TYPE: + printf("Trying to round an integer??\n"); assert(0); break; + case F16_TYPE: assert(0); break; + case F32_TYPE: + data.f32 = truncf(data.f32); + break; + case F64_TYPE: + case FF64_TYPE: + if (data.f64 < 0) data.f64 = ceil(data.f64); //negative + else data.f64 = floor(data.f64); //positive + break; + default: assert(0); break; + } + break; + case RNI_OPTION: + switch ( type ) { + case S8_TYPE: + case S16_TYPE: + case S32_TYPE: + case S64_TYPE: + case U8_TYPE: + case U16_TYPE: + case U32_TYPE: + case U64_TYPE: + printf("Trying to round an integer??\n"); assert(0); break; + case F16_TYPE: assert(0); break; + case F32_TYPE: +#if CUDART_VERSION >= 3000 + data.f32 = nearbyintf(data.f32); +#else + data.f32 = cuda_math::__cuda_nearbyintf(data.f32); +#endif + break; + case F64_TYPE: case FF64_TYPE: data.f64 = round(data.f64); break; + default: assert(0); break; + } + break; + case RMI_OPTION: + switch ( type ) { + case S8_TYPE: + case S16_TYPE: + case S32_TYPE: + case S64_TYPE: + case U8_TYPE: + case U16_TYPE: + case U32_TYPE: + case U64_TYPE: + printf("Trying to round an integer??\n"); assert(0); break; + case F16_TYPE: assert(0); break; + case F32_TYPE: + data.f32 = floorf(data.f32); + break; + case F64_TYPE: case FF64_TYPE: data.f64 = floor(data.f64); break; + default: assert(0); break; + } + break; + case RPI_OPTION: + switch ( type ) { + case S8_TYPE: + case S16_TYPE: + case S32_TYPE: + case S64_TYPE: + case U8_TYPE: + case U16_TYPE: + case U32_TYPE: + case U64_TYPE: + printf("Trying to round an integer??\n"); assert(0); break; + case F16_TYPE: assert(0); break; + case F32_TYPE: data.f32 = ceilf(data.f32); break; + case F64_TYPE: case FF64_TYPE: data.f64 = ceil(data.f64); break; + default: assert(0); break; + } + break; + default: break; + } + + if (type == F32_TYPE) { +#if CUDART_VERSION >= 3000 + if (isnanf(data.f32)) +#else + if (cuda_math::__cuda___isnanf(data.f32)) +#endif + { + data.u32 = 0x7fffffff; + } + } + if ((type == F64_TYPE)||(type == FF64_TYPE)) { + if (std::isnan(data.f64)) { + data.u64 = 0xfff8000000000000ull; + } + } +} + +void ptx_saturate(ptx_reg_t& data, int saturation_mode, int type) +{ + if (!saturation_mode) { + return; + } + switch ( type ) { + case S8_TYPE: + case S16_TYPE: + case S32_TYPE: + case S64_TYPE: + case U8_TYPE: + case U16_TYPE: + case U32_TYPE: + case U64_TYPE: + printf("Trying to clamp an integer to 1??\n"); assert(0); break; + case F16_TYPE: assert(0); break; + case F32_TYPE: + if (data.f32 > 1.0f) data.f32 = 1.0f; //negative + if (data.f32 < 0.0f) data.f32 = 0.0f; //positive + break; + case F64_TYPE: + case FF64_TYPE: + if (data.f64 > 1.0f) data.f64 = 1.0f; //negative + if (data.f64 < 0.0f) data.f64 = 0.0f; //positive + break; + default: assert(0); break; + } + +} + +void cvt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + unsigned to_type = pI->get_type(); + unsigned from_type = pI->get_type2(); + unsigned rounding_mode = pI->rounding_mode(); + unsigned saturation_mode = pI->saturation_mode(); + + if ( to_type == F16_TYPE || from_type == F16_TYPE ) + abort(); + + int to_sign, from_sign; + size_t from_width, to_width; + unsigned src_fmt = type_info_key::type_decode(from_type, from_width, from_sign); + unsigned dst_fmt = type_info_key::type_decode(to_type, to_width, to_sign); + + ptx_reg_t data = thread->get_operand_value(src1, dst, from_type, thread, 1); + + if(pI->is_neg()){ + + switch( from_type ) { + // Default to f32 for now, need to add support for others + case S8_TYPE: + case U8_TYPE: + case B8_TYPE: + data.s8 = -data.s8; + break; + case S16_TYPE: + case U16_TYPE: + case B16_TYPE: + data.s16 = -data.s16; + break; + case S32_TYPE: + case U32_TYPE: + case B32_TYPE: + data.s32 = -data.s32; + break; + case S64_TYPE: + case U64_TYPE: + case B64_TYPE: + data.s64 = -data.s64; + break; + case F16_TYPE: + data.f16 = -data.f16; + break; + case F32_TYPE: + data.f32 = -data.f32; + break; + case F64_TYPE: + case FF64_TYPE: + data.f64 = -data.f64; + break; + default: + assert(0); + } + + } + + + if ( g_cvt_fn[src_fmt][dst_fmt] != NULL ) { + ptx_reg_t result = g_cvt_fn[src_fmt][dst_fmt](data,from_width,to_width,to_sign, rounding_mode, saturation_mode); + data = result; + } + + thread->set_operand_value(dst, data, to_type, thread, pI ); +} + +void cvta_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + memory_space_t space = pI->get_space(); + bool to_non_generic = pI->is_to(); + + unsigned i_type = pI->get_type(); + ptx_reg_t from_addr = thread->get_operand_value(src1,dst,i_type,thread,1); + addr_t from_addr_hw = (addr_t)from_addr.u64; + addr_t to_addr_hw = 0; + unsigned smid = thread->get_hw_sid(); + unsigned hwtid = thread->get_hw_tid(); + + if( to_non_generic ) { + switch( space.get_type() ) { + case shared_space: to_addr_hw = generic_to_shared( smid, from_addr_hw ); break; + case local_space: to_addr_hw = generic_to_local( smid, hwtid, from_addr_hw ); break; + case global_space: to_addr_hw = generic_to_global(from_addr_hw ); break; + default: abort(); + } + } else { + switch( space.get_type() ) { + case shared_space: to_addr_hw = shared_to_generic( smid, from_addr_hw ); break; + case local_space: to_addr_hw = local_to_generic( smid, hwtid, from_addr_hw ) + + thread->get_local_mem_stack_pointer(); break; // add stack ptr here so that it can be passed as a pointer at function call + case global_space: to_addr_hw = global_to_generic( from_addr_hw ); break; + default: abort(); + } + } + + ptx_reg_t to_addr; + to_addr.u64 = to_addr_hw; + thread->set_reg(dst.get_symbol(),to_addr); +} + +void div_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + + ptx_reg_t src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + ptx_reg_t src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + switch ( i_type ) { + case S8_TYPE: + data.s8 = src1_data.s8 / src2_data.s8 ; break; + case S16_TYPE: + data.s16 = src1_data.s16 / src2_data.s16; break; + case S32_TYPE: + data.s32 = src1_data.s32 / src2_data.s32; break; + case S64_TYPE: + data.s64 = src1_data.s64 / src2_data.s64; break; + case U8_TYPE: + data.u8 = src1_data.u8 / src2_data.u8 ; break; + case U16_TYPE: + data.u16 = src1_data.u16 / src2_data.u16; break; + case U32_TYPE: + data.u32 = src1_data.u32 / src2_data.u32; break; + case U64_TYPE: + data.u64 = src1_data.u64 / src2_data.u64; break; + case B8_TYPE: + data.u8 = src1_data.u8 / src2_data.u8 ; break; + case B16_TYPE: + data.u16 = src1_data.u16 / src2_data.u16; break; + case B32_TYPE: + data.u32 = src1_data.u32 / src2_data.u32; break; + case B64_TYPE: + data.u64 = src1_data.u64 / src2_data.u64; break; + case F16_TYPE: assert(0); break; + case F32_TYPE: data.f32 = src1_data.f32 / src2_data.f32; break; + case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 / src2_data.f64; break; + default: assert(0); break; + } + thread->set_operand_value(dst,data, i_type, thread,pI); +} + +void ex2_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case F32_TYPE: + data.f32 = cuda_math::__powf(2.0, src1_data.f32); + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,data, i_type, thread,pI); +} + +void exit_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + thread->set_done(); + thread->exitCore(); + thread->registerExit(); +} + +void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry = false ); + +void fma_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + mad_def(pI,thread); +} + +void isspacep_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a; + bool t=false; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + memory_space_t space = pI->get_space(); + + a = thread->get_reg(src1.get_symbol()); + addr_t addr = (addr_t)a.u64; + unsigned smid = thread->get_hw_sid(); + unsigned hwtid = thread->get_hw_tid(); + + switch( space.get_type() ) { + case shared_space: t = isspace_shared( smid, addr ); + case local_space: t = isspace_local( smid, hwtid, addr ); + case global_space: t = isspace_global( addr ); + default: abort(); + } + + ptx_reg_t p; + p.pred = t?1:0; + + thread->set_reg(dst.get_symbol(),p); +} + +void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand_info &op, memory_space *&mem, addr_t &addr) +{ + unsigned smid = thread->get_hw_sid(); + unsigned hwtid = thread->get_hw_tid(); + + if( space == param_space_unclassified ) { + // need to op to determine whether it refers to a kernel param or local param + const symbol *s = op.get_symbol(); + const type_info *t = s->type(); + type_info_key ti = t->get_key(); + if( ti.is_param_kernel() ) + space = param_space_kernel; + else if( ti.is_param_local() ) { + space = param_space_local; + } else { + printf("GPGPU-Sim PTX: ERROR ** cannot resolve .param space for '%s'\n", s->name().c_str() ); + abort(); + } + } + switch ( space.get_type() ) { + case global_space: mem = thread->get_global_memory(); break; + case param_space_local: + case local_space: + mem = thread->m_local_mem; + addr += thread->get_local_mem_stack_pointer(); + break; + case tex_space: mem = thread->get_tex_memory(); break; + case surf_space: mem = thread->get_surf_memory(); break; + case param_space_kernel: mem = thread->get_param_memory(); break; + case shared_space: mem = thread->m_shared_mem; break; + case const_space: mem = thread->get_global_memory(); break; + case generic_space: + if( thread->get_ptx_version().ver() >= 2.0 ) { + // convert generic address to memory space address + space = whichspace(addr); + switch ( space.get_type() ) { + case global_space: mem = thread->get_global_memory(); addr = generic_to_global(addr); break; + case local_space: mem = thread->m_local_mem; addr = generic_to_local(smid,hwtid,addr); break; + case shared_space: mem = thread->m_shared_mem; addr = generic_to_shared(smid,addr); break; + default: abort(); + } + } else { + abort(); + } + break; + case param_space_unclassified: + case undefined_space: + default: + abort(); + } +} + +void ld_exec( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned type = pI->get_type(); + + ptx_reg_t src1_data = thread->get_operand_value(src1, dst, type, thread, 1); + ptx_reg_t data; + memory_space_t space = pI->get_space(); + unsigned vector_spec = pI->get_vector(); + + memory_space *mem = NULL; + addr_t addr = src1_data.u32; + + decode_space(space,thread,src1,mem,addr); + + size_t size; + int t; + data.u64=0; + type_info_key::type_decode(type,size,t); + if (!vector_spec) { + mem->read(addr,size/8,&data.s64); + if( type == S16_TYPE || type == S32_TYPE ) + sign_extend(data,size,dst); + thread->set_operand_value(dst,data, type, thread, pI); + } else { + ptx_reg_t data1, data2, data3, data4; + mem->read(addr,size/8,&data1.s64); + mem->read(addr+size/8,size/8,&data2.s64); + if (vector_spec != V2_TYPE) { //either V3 or V4 + mem->read(addr+2*size/8,size/8,&data3.s64); + if (vector_spec != V3_TYPE) { //v4 + mem->read(addr+3*size/8,size/8,&data4.s64); + thread->set_vector_operand_values(dst,data1,data2,data3,data4); + } else //v3 + thread->set_vector_operand_values(dst,data1,data2,data3,data3); + } else //v2 + thread->set_vector_operand_values(dst,data1,data2,data2,data2); + } + thread->m_last_effective_address = addr; + thread->m_last_memory_space = space; +} + +void ld_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ld_exec(pI,thread); +} +void ldu_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ld_exec(pI,thread); +} + +void lg2_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case F32_TYPE: + d.f32 = log(a.f32)/log(2); + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void mad24_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + ptx_reg_t d, t; + + unsigned i_type = pI->get_type(); + ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); + ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); + ptx_reg_t c = thread->get_operand_value(src3, dst, i_type, thread, 1); + + unsigned sat_mode = pI->saturation_mode(); + + assert( !pI->is_wide() ); + + switch ( i_type ) { + case S32_TYPE: + t.s64 = a.s32 * b.s32; + if ( pI->is_hi() ) { + d.s64 = (t.s64>>16) + c.s32; + if ( sat_mode ) { + if ( d.s64 > (int)0x7FFFFFFF ) + d.s64 = (int)0x7FFFFFFF; + else if ( d.s64 < (int)0x80000000 ) + d.s64 = (int)0x80000000; + } + } else if ( pI->is_lo() ) d.s64 = t.s32 + c.s32; + else assert(0); + break; + case U32_TYPE: + t.u64 = a.u32 * b.u32; + if ( pI->is_hi() ) d.u64 = (t.u64>>16) + c.u32; + else if ( pI->is_lo() ) d.u64 = t.u32 + c.u32; + else assert(0); + break; + default: + assert(0); + break; + } + + thread->set_operand_value(dst, d, i_type, thread, pI); +} + +void mad_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + mad_def(pI, thread, false); +} + +void madp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + mad_def(pI, thread, true); +} + +void madc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + mad_def(pI, thread, true); +} + +void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + ptx_reg_t d, t; + + int carry=0; + int overflow=0; + + unsigned i_type = pI->get_type(); + ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); + ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); + ptx_reg_t c = thread->get_operand_value(src3, dst, i_type, thread, 1); + + // take the carry bit, it should be the 4th operand + ptx_reg_t carry_bit; + carry_bit.u64 = 0; + if (use_carry) { + const operand_info &carry = pI->operand_lookup(4); + carry_bit = thread->get_operand_value(carry, dst, PRED_TYPE, thread, 0); + carry_bit.pred &= 0x4; + carry_bit.pred >>=2; + } + + unsigned rounding_mode = pI->rounding_mode(); + + switch ( i_type ) { + case S16_TYPE: + t.s32 = a.s16 * b.s16; + if ( pI->is_wide() ) d.s32 = t.s32 + c.s32 + carry_bit.pred; + else if ( pI->is_hi() ) d.s16 = (t.s32>>16) + c.s16 + carry_bit.pred; + else if ( pI->is_lo() ) d.s16 = t.s16 + c.s16 + carry_bit.pred; + else assert(0); + carry = ((long long int)(t.s32 + c.s32 + carry_bit.pred)&0x100000000)>>32; + break; + case S32_TYPE: + t.s64 = a.s32 * b.s32; + if ( pI->is_wide() ) d.s64 = t.s64 + c.s64 + carry_bit.pred; + else if ( pI->is_hi() ) d.s32 = (t.s64>>32) + c.s32 + carry_bit.pred; + else if ( pI->is_lo() ) d.s32 = t.s32 + c.s32 + carry_bit.pred; + else assert(0); + break; + case S64_TYPE: + t.s64 = a.s64 * b.s64; + assert( !pI->is_wide() ); + assert( !pI->is_hi() ); + assert( use_carry == false); + if ( pI->is_lo() ) d.s64 = t.s64 + c.s64 + carry_bit.pred; + else assert(0); + break; + case U16_TYPE: + t.u32 = a.u16 * b.u16; + if ( pI->is_wide() ) d.u32 = t.u32 + c.u32 + carry_bit.pred; + else if ( pI->is_hi() ) d.u16 = (t.u32 + c.u16 + carry_bit.pred)>>16; + else if ( pI->is_lo() ) d.u16 = t.u16 + c.u16 + carry_bit.pred; + else assert(0); + carry = ((long long int)((long long int)t.u32 + c.u32 + carry_bit.pred)&0x100000000)>>32; + break; + case U32_TYPE: + t.u64 = a.u32 * b.u32; + if ( pI->is_wide() ) d.u64 = t.u64 + c.u64 + carry_bit.pred; + else if ( pI->is_hi() ) d.u32 = (t.u64 + c.u32 + carry_bit.pred)>>32; + else if ( pI->is_lo() ) d.u32 = t.u32 + c.u32 + carry_bit.pred; + else assert(0); + break; + case U64_TYPE: + t.u64 = a.u64 * b.u64; + assert( !pI->is_wide() ); + assert( !pI->is_hi() ); + assert( use_carry == false); + if ( pI->is_lo() ) d.u64 = t.u64 + c.u64 + carry_bit.pred; + else assert(0); + break; + case F16_TYPE: + assert(0); + break; + case F32_TYPE: { + assert( use_carry == false); + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + d.f32 = a.f32 * b.f32 + c.f32; + if ( pI->saturation_mode() ) { + if ( d.f32 < 0 ) d.f32 = 0; + else if ( d.f32 > 1.0f ) d.f32 = 1.0f; + } + fesetround( orig_rm ); + break; + } + case F64_TYPE: case FF64_TYPE: { + assert( use_carry == false); + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + d.f64 = a.f64 * b.f64 + c.f64; + if ( pI->saturation_mode() ) { + if ( d.f64 < 0 ) d.f64 = 0; + else if ( d.f64 > 1.0f ) d.f64 = 1.0; + } + fesetround( orig_rm ); + break; + } + default: + assert(0); + break; + } + thread->set_operand_value(dst, d, i_type, thread, pI, overflow, carry); +} + +bool isNaN(float x) +{ + return std::isnan(x); +} + +bool isNaN(double x) +{ + return std::isnan(x); +} + +void max_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + b = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + switch ( i_type ) { + case U16_TYPE: d.u16 = MY_MAX_I(a.u16,b.u16); break; + case U32_TYPE: d.u32 = MY_MAX_I(a.u32,b.u32); break; + case U64_TYPE: d.u64 = MY_MAX_I(a.u64,b.u64); break; + case S16_TYPE: d.s16 = MY_MAX_I(a.s16,b.s16); break; + case S32_TYPE: d.s32 = MY_MAX_I(a.s32,b.s32); break; + case S64_TYPE: d.s64 = MY_MAX_I(a.s64,b.s64); break; + case F32_TYPE: d.f32 = MY_MAX_F(a.f32,b.f32); break; + case F64_TYPE: case FF64_TYPE: d.f64 = MY_MAX_F(a.f64,b.f64); break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void membar_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + // handled by timing simulator +} + +void min_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + b = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + switch ( i_type ) { + case U16_TYPE: d.u16 = MY_MIN_I(a.u16,b.u16); break; + case U32_TYPE: d.u32 = MY_MIN_I(a.u32,b.u32); break; + case U64_TYPE: d.u64 = MY_MIN_I(a.u64,b.u64); break; + case S16_TYPE: d.s16 = MY_MIN_I(a.s16,b.s16); break; + case S32_TYPE: d.s32 = MY_MIN_I(a.s32,b.s32); break; + case S64_TYPE: d.s64 = MY_MIN_I(a.s64,b.s64); break; + case F32_TYPE: d.f32 = MY_MIN_F(a.f32,b.f32); break; + case F64_TYPE: case FF64_TYPE: d.f64 = MY_MIN_F(a.f64,b.f64); break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void mov_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + unsigned i_type = pI->get_type(); + + if( (src1.is_vector() || dst.is_vector()) && (i_type != BB64_TYPE) && (i_type != BB128_TYPE) && (i_type != FF64_TYPE) ) { + // pack or unpack operation + unsigned nbits_to_move; + ptx_reg_t tmp_bits; + + switch( pI->get_type() ) { + case B16_TYPE: nbits_to_move = 16; break; + case B32_TYPE: nbits_to_move = 32; break; + case B64_TYPE: nbits_to_move = 64; break; + default: printf("Execution error: mov pack/unpack with unsupported type qualifier\n"); assert(0); break; + } + + if( src1.is_vector() ) { + unsigned nelem = src1.get_vect_nelem(); + ptx_reg_t v[4]; + thread->get_vector_operand_values(src1, v, nelem ); + + unsigned bits_per_src_elem = nbits_to_move / nelem; + for( unsigned i=0; i < nelem; i++ ) { + switch(bits_per_src_elem) { + case 8: tmp_bits.u64 |= ((unsigned long long)(v[i].u8) << (8*i)); break; + case 16: tmp_bits.u64 |= ((unsigned long long)(v[i].u16) << (16*i)); break; + case 32: tmp_bits.u64 |= ((unsigned long long)(v[i].u32) << (32*i)); break; + default: printf("Execution error: mov pack/unpack with unsupported source/dst size ratio (src)\n"); assert(0); break; + } + } + } else { + data = thread->get_operand_value(src1, dst, i_type, thread, 1); + + switch( pI->get_type() ) { + case B16_TYPE: tmp_bits.u16 = data.u16; break; + case B32_TYPE: tmp_bits.u32 = data.u32; break; + case B64_TYPE: tmp_bits.u64 = data.u64; break; + default: assert(0); break; + } + } + + if( dst.is_vector() ) { + unsigned nelem = dst.get_vect_nelem(); + ptx_reg_t v[4]; + unsigned bits_per_dst_elem = nbits_to_move / nelem; + for( unsigned i=0; i < nelem; i++ ) { + switch(bits_per_dst_elem) { + case 8: v[i].u8 = (tmp_bits.u64 >> (8*i)) & ((unsigned long long) 0xFF); break; + case 16: v[i].u16 = (tmp_bits.u64 >> (16*i)) & ((unsigned long long) 0xFFFF); break; + case 32: v[i].u32 = (tmp_bits.u64 >> (32*i)) & ((unsigned long long) 0xFFFFFFFF); break; + default: + printf("Execution error: mov pack/unpack with unsupported source/dst size ratio (dst)\n"); + assert(0); + break; + } + } + thread->set_vector_operand_values(dst,v[0],v[1],v[2],v[3]); + } else { + thread->set_operand_value(dst,tmp_bits, i_type, thread, pI); + } + } else if (i_type == PRED_TYPE and src1.is_literal() == true) { + // in ptx, literal input translate to predicate as 0 = false and 1 = true + // we have adopted the opposite to simplify implementation of zero flags in ptxplus + data = thread->get_operand_value(src1, dst, i_type, thread, 1); + + ptx_reg_t finaldata; + finaldata.pred = (data.u32 == 0)? 1 : 0; // setting zero-flag in predicate + thread->set_operand_value(dst, finaldata, i_type, thread, pI); + } else { + + data = thread->get_operand_value(src1, dst, i_type, thread, 1); + + thread->set_operand_value(dst, data, i_type, thread, pI); + + } +} + +void mul24_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + //src1_data = srcOperandModifiers(src1_data, src1, dst, i_type, thread); + //src2_data = srcOperandModifiers(src2_data, src2, dst, i_type, thread); + + src1_data.mask_and(0,0x00FFFFFF); + src2_data.mask_and(0,0x00FFFFFF); + + switch ( i_type ) { + case S32_TYPE: + if( src1_data.get_bit(23) ) + src1_data.mask_or(0xFFFFFFFF,0xFF000000); + if( src2_data.get_bit(23) ) + src2_data.mask_or(0xFFFFFFFF,0xFF000000); + data.s64 = src1_data.s64 * src2_data.s64; + break; + case U32_TYPE: + data.u64 = src1_data.u64 * src2_data.u64; + break; + default: + printf("GPGPU-Sim PTX: Execution error - type mismatch with instruction\n"); + assert(0); + break; + } + + if ( pI->is_hi() ) { + data.u64 = data.u64 >> 16; + data.mask_and(0,0xFFFFFFFF); + } else if (pI->is_lo()) { + data.mask_and(0,0xFFFFFFFF); + } + + thread->set_operand_value(dst, data, i_type, thread, pI); +} + +void mul_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + ptx_reg_t d, t; + + unsigned i_type = pI->get_type(); + ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); + ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); + + unsigned rounding_mode = pI->rounding_mode(); + + switch ( i_type ) { + case S16_TYPE: + t.s32 = ((int)a.s16) * ((int)b.s16); + if ( pI->is_wide() ) d.s32 = t.s32; + else if ( pI->is_hi() ) d.s16 = (t.s32>>16); + else if ( pI->is_lo() ) d.s16 = t.s16; + else assert(0); + break; + case S32_TYPE: + t.s64 = ((long long)a.s32) * ((long long)b.s32); + if ( pI->is_wide() ) d.s64 = t.s64; + else if ( pI->is_hi() ) d.s32 = (t.s64>>32); + else if ( pI->is_lo() ) d.s32 = t.s32; + else assert(0); + break; + case S64_TYPE: + t.s64 = a.s64 * b.s64; + assert( !pI->is_wide() ); + assert( !pI->is_hi() ); + if ( pI->is_lo() ) d.s64 = t.s64; + else assert(0); + break; + case U16_TYPE: + t.u32 = ((unsigned)a.u16) * ((unsigned)b.u16); + if ( pI->is_wide() ) d.u32 = t.u32; + else if ( pI->is_lo() ) d.u16 = t.u16; + else if ( pI->is_hi() ) d.u16 = (t.u32>>16); + else assert(0); + break; + case U32_TYPE: + t.u64 = ((unsigned long long)a.u32) * ((unsigned long long)b.u32); + if ( pI->is_wide() ) d.u64 = t.u64; + else if ( pI->is_lo() ) d.u32 = t.u32; + else if ( pI->is_hi() ) d.u32 = (t.u64>>32); + else assert(0); + break; + case U64_TYPE: + t.u64 = a.u64 * b.u64; + assert( !pI->is_wide() ); + assert( !pI->is_hi() ); + if ( pI->is_lo() ) d.u64 = t.u64; + else assert(0); + break; + case F16_TYPE: + assert(0); + break; + case F32_TYPE: { + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + + d.f32 = a.f32 * b.f32; + + if ( pI->saturation_mode() ) { + if ( d.f32 < 0 ) d.f32 = 0; + else if ( d.f32 > 1.0f ) d.f32 = 1.0f; + } + fesetround( orig_rm ); + break; + } + case F64_TYPE: case FF64_TYPE:{ + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + d.f64 = a.f64 * b.f64; + if ( pI->saturation_mode() ) { + if ( d.f64 < 0 ) d.f64 = 0; + else if ( d.f64 > 1.0f ) d.f64 = 1.0; + } + fesetround( orig_rm ); + break; + } + default: + assert(0); + break; + } + + thread->set_operand_value(dst, d, i_type, thread, pI); +} + +void neg_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned to_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, to_type, thread, 1); + + + switch ( to_type ) { + case S8_TYPE: + case S16_TYPE: + case S32_TYPE: + case S64_TYPE: + data.s64 = 0 - src1_data.s64; break; // seems buggy, but not (just ignore higher bits) + case U8_TYPE: + case U16_TYPE: + case U32_TYPE: + case U64_TYPE: + assert(0); break; + case F16_TYPE: assert(0); break; + case F32_TYPE: data.f32 = 0.0f - src1_data.f32; break; + case F64_TYPE: case FF64_TYPE: data.f64 = 0.0f - src1_data.f64; break; + default: assert(0); break; + } + + thread->set_operand_value(dst,data, to_type, thread, pI); +} + +//nandn bitwise negates second operand then bitwise nands with the first operand +void nandn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + //the way ptxplus handles predicates: 1 = false and 0 = true + if(i_type == PRED_TYPE) + data.pred = (~src1_data.pred & src2_data.pred); + else + data.u64 = ~(src1_data.u64 & ~src2_data.u64); + + thread->set_operand_value(dst,data, i_type, thread, pI); + +} + +//norn bitwise negates first operand then bitwise ands with the second operand +void norn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + //the way ptxplus handles predicates: 1 = false and 0 = true + if(i_type == PRED_TYPE) + data.pred = ~(src1_data.pred & ~(src2_data.pred)); + else + data.u64 = ~(src1_data.u64) & src2_data.u64; + + thread->set_operand_value(dst,data, i_type, thread, pI); + +} + +void not_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case PRED_TYPE: d.pred = (~(a.pred) & 0x000F); break; + case B16_TYPE: d.u16 = ~a.u16; break; + case B32_TYPE: d.u32 = ~a.u32; break; + case B64_TYPE: d.u64 = ~a.u64; break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void or_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + //the way ptxplus handles predicates: 1 = false and 0 = true + if(i_type == PRED_TYPE) + data.pred = ~(~(src1_data.pred) | ~(src2_data.pred)); + else + data.u64 = src1_data.u64 | src2_data.u64; + + thread->set_operand_value(dst,data, i_type, thread, pI); +} + +void orn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + //the way ptxplus handles predicates: 1 = false and 0 = true + if(i_type == PRED_TYPE) + data.pred = ~(~(src1_data.pred) | (src2_data.pred)); + else + data.u64 = src1_data.u64 | ~src2_data.u64; + + thread->set_operand_value(dst,data, i_type, thread, pI); +} + +void pmevent_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void popc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src_data, data; + const operand_info &dst = pI->dst(); + const operand_info &src = pI->src1(); + + unsigned i_type = pI->get_type(); + src_data = thread->get_operand_value(src, dst, i_type, thread, 1); + + switch ( i_type ) { + case B32_TYPE: { + std::bitset<32> mask(src_data.u32); + data.u32 = mask.count(); + } break; + case B64_TYPE: { + std::bitset<64> mask(src_data.u64); + data.u32 = mask.count(); + } break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,data, i_type, thread, pI); +} +void prefetch_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void prefetchu_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void prmt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } + +void rcp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case F32_TYPE: + data.f32 = 1.0f / src1_data.f32; + break; + case F64_TYPE: + case FF64_TYPE: + data.f64 = 1.0f / src1_data.f64; + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,data, i_type, thread, pI); +} + +void red_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } + +void rem_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + data.u64 = src1_data.u64 % src2_data.u64; + + thread->set_operand_value(dst,data, i_type, thread, pI); +} + +void ret_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + bool empty = thread->callstack_pop(); + if( empty ) { + thread->set_done(); + thread->exitCore(); + thread->registerExit(); + } +} + +//Ptxplus version of ret instruction. +void retp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + bool empty = thread->callstack_pop_plus(); + if( empty ) { + thread->set_done(); + thread->exitCore(); + thread->registerExit(); + } +} + +void rsqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case F32_TYPE: + if ( a.f32 < 0 ) { + d.u64 = 0; + d.u64 = 0x7fc00000; // NaN + } else if ( a.f32 == 0 ) { + d.u64 = 0; + d.u32 = 0x7f800000; // Inf + } else + d.f32 = cuda_math::__internal_accurate_fdividef(1.0f, sqrtf(a.f32)); + break; + case F64_TYPE: + case FF64_TYPE: + if ( a.f32 < 0 ) { + d.u64 = 0; + d.u32 = 0x7fc00000; // NaN + float x = d.f32; + d.f64 = (double)x; + } else if ( a.f32 == 0 ) { + d.u64 = 0; + d.u32 = 0x7f800000; // Inf + float x = d.f32; + d.f64 = (double)x; + } else + d.f64 = 1.0 / sqrt(a.f64); + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +#define SAD(d,a,b,c) d = c + ((adst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + b = thread->get_operand_value(src2, dst, i_type, thread, 1); + c = thread->get_operand_value(src3, dst, i_type, thread, 1); + + + switch ( i_type ) { + case U16_TYPE: SAD(d.u16,a.u16,b.u16,c.u16); break; + case U32_TYPE: SAD(d.u32,a.u32,b.u32,c.u32); break; + case U64_TYPE: SAD(d.u64,a.u64,b.u64,c.u64); break; + case S16_TYPE: SAD(d.s16,a.s16,b.s16,c.s16); break; + case S32_TYPE: SAD(d.s32,a.s32,b.s32,c.s32); break; + case S64_TYPE: SAD(d.s64,a.s64,b.s64,c.s64); break; + case F32_TYPE: SAD(d.f32,a.f32,b.f32,c.f32); break; + case F64_TYPE: case FF64_TYPE: SAD(d.f64,a.f64,b.f64,c.f64); break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void selp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + + ptx_reg_t a, b, c, d; + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + b = thread->get_operand_value(src2, dst, i_type, thread, 1); + c = thread->get_operand_value(src3, dst, i_type, thread, 1); + + //predicate value was changed so the lowest bit being set means the zero flag is set. + //As a result, the value of c.pred must be inverted to get proper behavior + d = (!(c.pred & 0x0001))?a:b; + + thread->set_operand_value(dst,d, PRED_TYPE, thread, pI); +} + +bool isFloat(int type) +{ + switch ( type ) { + case F16_TYPE: + case F32_TYPE: + case F64_TYPE: + case FF64_TYPE: + return true; + default: + return false; + } +} + +bool CmpOp( int type, ptx_reg_t a, ptx_reg_t b, unsigned cmpop ) +{ + bool t = false; + + switch ( type ) { + case B16_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.u16 == b.u16); break; + case NE_OPTION: t = (a.u16 != b.u16); break; + default: + assert(0); + } + + case B32_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.u32 == b.u32); break; + case NE_OPTION: t = (a.u32 != b.u32); break; + default: + assert(0); + } + case B64_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.u64 == b.u64); break; + case NE_OPTION: t = (a.u64 != b.u64); break; + default: + assert(0); + } + break; + case S8_TYPE: + case S16_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.s16 == b.s16); break; + case NE_OPTION: t = (a.s16 != b.s16); break; + case LT_OPTION: t = (a.s16 < b.s16); break; + case LE_OPTION: t = (a.s16 <= b.s16); break; + case GT_OPTION: t = (a.s16 > b.s16); break; + case GE_OPTION: t = (a.s16 >= b.s16); break; + default: + assert(0); + } + break; + case S32_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.s32 == b.s32); break; + case NE_OPTION: t = (a.s32 != b.s32); break; + case LT_OPTION: t = (a.s32 < b.s32); break; + case LE_OPTION: t = (a.s32 <= b.s32); break; + case GT_OPTION: t = (a.s32 > b.s32); break; + case GE_OPTION: t = (a.s32 >= b.s32); break; + default: + assert(0); + } + break; + case S64_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.s64 == b.s64); break; + case NE_OPTION: t = (a.s64 != b.s64); break; + case LT_OPTION: t = (a.s64 < b.s64); break; + case LE_OPTION: t = (a.s64 <= b.s64); break; + case GT_OPTION: t = (a.s64 > b.s64); break; + case GE_OPTION: t = (a.s64 >= b.s64); break; + default: + assert(0); + } + break; + case U8_TYPE: + case U16_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.u16 == b.u16); break; + case NE_OPTION: t = (a.u16 != b.u16); break; + case LT_OPTION: t = (a.u16 < b.u16); break; + case LE_OPTION: t = (a.u16 <= b.u16); break; + case GT_OPTION: t = (a.u16 > b.u16); break; + case GE_OPTION: t = (a.u16 >= b.u16); break; + case LO_OPTION: t = (a.u16 < b.u16); break; + case LS_OPTION: t = (a.u16 <= b.u16); break; + case HI_OPTION: t = (a.u16 > b.u16); break; + case HS_OPTION: t = (a.u16 >= b.u16); break; + default: + assert(0); + } + break; + case U32_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.u32 == b.u32); break; + case NE_OPTION: t = (a.u32 != b.u32); break; + case LT_OPTION: t = (a.u32 < b.u32); break; + case LE_OPTION: t = (a.u32 <= b.u32); break; + case GT_OPTION: t = (a.u32 > b.u32); break; + case GE_OPTION: t = (a.u32 >= b.u32); break; + case LO_OPTION: t = (a.u32 < b.u32); break; + case LS_OPTION: t = (a.u32 <= b.u32); break; + case HI_OPTION: t = (a.u32 > b.u32); break; + case HS_OPTION: t = (a.u32 >= b.u32); break; + default: + assert(0); + } + break; + case U64_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.u64 == b.u64); break; + case NE_OPTION: t = (a.u64 != b.u64); break; + case LT_OPTION: t = (a.u64 < b.u64); break; + case LE_OPTION: t = (a.u64 <= b.u64); break; + case GT_OPTION: t = (a.u64 > b.u64); break; + case GE_OPTION: t = (a.u64 >= b.u64); break; + case LO_OPTION: t = (a.u64 < b.u64); break; + case LS_OPTION: t = (a.u64 <= b.u64); break; + case HI_OPTION: t = (a.u64 > b.u64); break; + case HS_OPTION: t = (a.u64 >= b.u64); break; + default: + assert(0); + } + break; + case F16_TYPE: assert(0); break; + case F32_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.f32 == b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; + case NE_OPTION: t = (a.f32 != b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; + case LT_OPTION: t = (a.f32 < b.f32 ) && !isNaN(a.f32) && !isNaN(b.f32); break; + case LE_OPTION: t = (a.f32 <= b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; + case GT_OPTION: t = (a.f32 > b.f32 ) && !isNaN(a.f32) && !isNaN(b.f32); break; + case GE_OPTION: t = (a.f32 >= b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; + case EQU_OPTION: t = (a.f32 == b.f32) || isNaN(a.f32) || isNaN(b.f32); break; + case NEU_OPTION: t = (a.f32 != b.f32) || isNaN(a.f32) || isNaN(b.f32); break; + case LTU_OPTION: t = (a.f32 < b.f32 ) || isNaN(a.f32) || isNaN(b.f32); break; + case LEU_OPTION: t = (a.f32 <= b.f32) || isNaN(a.f32) || isNaN(b.f32); break; + case GTU_OPTION: t = (a.f32 > b.f32 ) || isNaN(a.f32) || isNaN(b.f32); break; + case GEU_OPTION: t = (a.f32 >= b.f32) || isNaN(a.f32) || isNaN(b.f32); break; + case NUM_OPTION: t = !isNaN(a.f32) && !isNaN(b.f32); break; + case NAN_OPTION: t = isNaN(a.f32) || isNaN(b.f32); break; + default: + assert(0); + } + break; + case F64_TYPE: + case FF64_TYPE: + switch (cmpop) { + case EQ_OPTION: t = (a.f64 == b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; + case NE_OPTION: t = (a.f64 != b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; + case LT_OPTION: t = (a.f64 < b.f64 ) && !isNaN(a.f64) && !isNaN(b.f64); break; + case LE_OPTION: t = (a.f64 <= b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; + case GT_OPTION: t = (a.f64 > b.f64 ) && !isNaN(a.f64) && !isNaN(b.f64); break; + case GE_OPTION: t = (a.f64 >= b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; + case EQU_OPTION: t = (a.f64 == b.f64) || isNaN(a.f64) || isNaN(b.f64); break; + case NEU_OPTION: t = (a.f64 != b.f64) || isNaN(a.f64) || isNaN(b.f64); break; + case LTU_OPTION: t = (a.f64 < b.f64 ) || isNaN(a.f64) || isNaN(b.f64); break; + case LEU_OPTION: t = (a.f64 <= b.f64) || isNaN(a.f64) || isNaN(b.f64); break; + case GTU_OPTION: t = (a.f64 > b.f64 ) || isNaN(a.f64) || isNaN(b.f64); break; + case GEU_OPTION: t = (a.f64 >= b.f64) || isNaN(a.f64) || isNaN(b.f64); break; + case NUM_OPTION: t = !isNaN(a.f64) && !isNaN(b.f64); break; + case NAN_OPTION: t = isNaN(a.f64) || isNaN(b.f64); break; + default: + assert(0); + } + break; + default: assert(0); break; + } + + return t; +} + +void setp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b; + + int t=0; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + assert( pI->get_num_operands() < 4 ); // or need to deal with "c" operand / boolOp + + unsigned type = pI->get_type(); + unsigned cmpop = pI->get_cmpop(); + a = thread->get_operand_value(src1, dst, type, thread, 1); + b = thread->get_operand_value(src2, dst, type, thread, 1); + + t = CmpOp(type,a,b,cmpop); + + ptx_reg_t data; + + //the way ptxplus handles the zero flag, 1 = false and 0 = true + data.pred = (t==0); //inverting predicate since ptxplus uses "1" for a set zero flag + + thread->set_operand_value(dst,data, PRED_TYPE, thread, pI); +} + +void set_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b; + + int t=0; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + assert( pI->get_num_operands() < 4 ); // or need to deal with "c" operand / boolOp + + unsigned src_type = pI->get_type2(); + unsigned cmpop = pI->get_cmpop(); + + a = thread->get_operand_value(src1, dst, src_type, thread, 1); + b = thread->get_operand_value(src2, dst, src_type, thread, 1); + + // Take abs of first operand if needed + if(pI->is_abs()) { + switch ( src_type ) { + case S16_TYPE: a.s16 = my_abs(a.s16); break; + case S32_TYPE: a.s32 = my_abs(a.s32); break; + case S64_TYPE: a.s64 = my_abs(a.s64); break; + case U16_TYPE: a.u16 = a.u16; break; + case U32_TYPE: a.u32 = my_abs(a.u32); break; + case U64_TYPE: a.u64 = my_abs(a.u64); break; + case F32_TYPE: a.f32 = my_abs(a.f32); break; + case F64_TYPE: case FF64_TYPE: a.f64 = my_abs(a.f64); break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + } + + t = CmpOp(src_type,a,b,cmpop); + + ptx_reg_t data; + if ( isFloat(pI->get_type()) ) { + data.f32 = (t!=0)?1.0f:0.0f; + } else { + data.u32 = (t!=0)?0xFFFFFFFF:0; + } + + thread->set_operand_value(dst, data, pI->get_type(), thread, pI); + +} + +void shfl_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) +{ + unsigned i_type = pI->get_type(); + int tid = inst.warp_id() * core->get_warp_size(); + ptx_thread_info *thread = core->get_thread_info()[tid]; + ptx_warp_info *warp_info = thread->m_warp_info; + int lane = warp_info->get_done_threads(); + thread = core->get_thread_info()[tid + lane]; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + int bval = (thread->get_operand_value(src2, dst, i_type, thread, 1)).u32; + int cval = (thread->get_operand_value(src3, dst, i_type, thread, 1)).u32; + int mask = cval >> 8; + bval &= 0x1F; + cval &= 0x1F; + + int maxLane = (lane & mask) | (cval & ~mask); + int minLane = lane & mask; + + int src_idx; + unsigned p; + switch(pI->shfl_op()) { + case UP_OPTION: + src_idx = lane - bval; + p = (src_idx >= maxLane); + break; + case DOWN_OPTION: + src_idx = lane + bval; + p = (src_idx <= maxLane); + break; + case BFLY_OPTION: + src_idx = lane ^ bval; + p = (src_idx <= maxLane); + break; + case IDX_OPTION: + src_idx = minLane | (bval & ~mask); + p = (src_idx <= maxLane); + break; + default: + printf("GPGPU-Sim PTX: ERROR: Invalid shfl option\n"); + assert(0); + break; + } + // copy from own lane + if (!p) src_idx = lane; + + // copy input from lane src_idx + ptx_reg_t data; + if (inst.active(src_idx)) { + ptx_thread_info *source = core->get_thread_info()[tid + src_idx]; + data = source->get_operand_value(src1, dst, i_type, source, 1); + } else { + printf("GPGPU-Sim PTX: WARNING: shfl input value unpredictable for inactive threads in a warp\n"); + data.u32 = 0; + } + thread->set_operand_value(dst, data, i_type, thread, pI); + + /* + TODO: deal with predicates appropriately using the following pseudocode: + if (!isGuardPredicateTrue(src_idx)) { + printf("GPGPU-Sim PTX: WARNING: shfl input value unpredictable for predicated-off threads in a warp\n"); + } + if (dest predicate selected) data.pred = p; + */ + + // keep track of the number of threads that have executed in the warp + warp_info->inc_done_threads(); + if (warp_info->get_done_threads() == inst.active_count()) { + warp_info->reset_done_threads(); + } +} + +void shl_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + b = thread->get_operand_value(src2, dst, i_type, thread, 1); + + switch ( i_type ) { + case B16_TYPE: + case U16_TYPE: + if ( b.u16 >= 16 ) + d.u16 = 0; + else + d.u16 = (unsigned short) ((a.u16 << b.u16) & 0xFFFF); + break; + case B32_TYPE: + case U32_TYPE: + if ( b.u32 >= 32 ) + d.u32 = 0; + else + d.u32 = (unsigned) ((a.u32 << b.u32) & 0xFFFFFFFF); + break; + case B64_TYPE: + case U64_TYPE: + if ( b.u32 >= 64 ) + d.u64 = 0; + else + d.u64 = (a.u64 << b.u64); + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst, d, i_type, thread, pI); +} + +void shr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, b, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + b = thread->get_operand_value(src2, dst, i_type, thread, 1); + + + switch ( i_type ) { + case U16_TYPE: + case B16_TYPE: + if ( b.u16 < 16 ) + d.u16 = (unsigned short) ((a.u16 >> b.u16) & 0xFFFF); + else + d.u16 = 0; + break; + case U32_TYPE: + case B32_TYPE: + if ( b.u32 < 32 ) + d.u32 = (unsigned) ((a.u32 >> b.u32) & 0xFFFFFFFF); + else + d.u32 = 0; + break; + case U64_TYPE: + case B64_TYPE: + if ( b.u32 < 64 ) + d.u64 = (a.u64 >> b.u64); + else + d.u64 = 0; + break; + case S16_TYPE: + if ( b.u16 < 16 ) + d.s64 = (a.s16 >> b.s16); + else { + if ( a.s16 < 0 ) { + d.s64 = -1; + } else { + d.s64 = 0; + } + } + break; + case S32_TYPE: + if ( b.u32 < 32 ) + d.s64 = (a.s32 >> b.s32); + else { + if ( a.s32 < 0 ) { + d.s64 = -1; + } else { + d.s64 = 0; + } + } + break; + case S64_TYPE: + if ( b.u64 < 64 ) + d.s64 = (a.s64 >> b.u64); + else { + if ( a.s64 < 0 ) { + if ( b.s32 < 0 ) { + d.u64 = -1; + d.s32 = 0; + } else { + d.s64 = -1; + } + } else { + d.s64 = 0; + } + } + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void sin_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case F32_TYPE: + d.f32 = sin(a.f32); + break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void slct_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + const operand_info &src3 = pI->src3(); + + ptx_reg_t a, b, c, d; + + unsigned i_type = pI->get_type(); + unsigned c_type = pI->get_type2(); + bool t = false; + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + b = thread->get_operand_value(src2, dst, i_type, thread, 1); + c = thread->get_operand_value(src3, dst, c_type, thread, 1); + + switch ( c_type ) { + case S32_TYPE: t = c.s32 >= 0; break; + case F32_TYPE: t = c.f32 >= 0; break; + default: assert(0); + } + + switch ( i_type ) { + case B16_TYPE: + case S16_TYPE: + case U16_TYPE: d.u16 = t?a.u16:b.u16; break; + case F32_TYPE: + case B32_TYPE: + case S32_TYPE: + case U32_TYPE: d.u32 = t?a.u32:b.u32; break; + case F64_TYPE: + case FF64_TYPE: + case B64_TYPE: + case S64_TYPE: + case U64_TYPE: d.u64 = t?a.u64:b.u64; break; + default: assert(0); + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t a, d; + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + + unsigned i_type = pI->get_type(); + a = thread->get_operand_value(src1, dst, i_type, thread, 1); + + + switch ( i_type ) { + case F32_TYPE: + if ( a.f32 < 0 ) + d.f32 = nanf(""); + else + d.f32 = sqrt(a.f32); break; + case F64_TYPE: + case FF64_TYPE: + if ( a.f64 < 0 ) + d.f64 = nan(""); + else + d.f64 = sqrt(a.f64); break; + default: + printf("Execution error: type mismatch with instruction\n"); + assert(0); + break; + } + + thread->set_operand_value(dst,d, i_type, thread, pI); +} + +void ssy_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + //printf("Execution Warning: unimplemented ssy instruction is treated as a nop\n"); + // TODO: add implementation +} + +void st_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); //may be scalar or vector of regs + unsigned type = pI->get_type(); + ptx_reg_t addr_reg = thread->get_operand_value(dst, dst, type, thread, 1); + ptx_reg_t data; + memory_space_t space = pI->get_space(); + unsigned vector_spec = pI->get_vector(); + + memory_space *mem = NULL; + addr_t addr = addr_reg.u32; + + decode_space(space,thread,dst,mem,addr); + + size_t size; + int t; + type_info_key::type_decode(type,size,t); + + if (!vector_spec) { + data = thread->get_operand_value(src1, dst, type, thread, 1); + mem->write(addr,size/8,&data.s64,thread,pI); + } else { + if (vector_spec == V2_TYPE) { + ptx_reg_t* ptx_regs = new ptx_reg_t[2]; + thread->get_vector_operand_values(src1, ptx_regs, 2); + mem->write(addr,size/8,&ptx_regs[0].s64,thread,pI); + mem->write(addr+size/8,size/8,&ptx_regs[1].s64,thread,pI); + delete [] ptx_regs; + } + if (vector_spec == V3_TYPE) { + ptx_reg_t* ptx_regs = new ptx_reg_t[3]; + thread->get_vector_operand_values(src1, ptx_regs, 3); + mem->write(addr,size/8,&ptx_regs[0].s64,thread,pI); + mem->write(addr+size/8,size/8,&ptx_regs[1].s64,thread,pI); + mem->write(addr+2*size/8,size/8,&ptx_regs[2].s64,thread,pI); + delete [] ptx_regs; + } + if (vector_spec == V4_TYPE) { + ptx_reg_t* ptx_regs = new ptx_reg_t[4]; + thread->get_vector_operand_values(src1, ptx_regs, 4); + mem->write(addr,size/8,&ptx_regs[0].s64,thread,pI); + mem->write(addr+size/8,size/8,&ptx_regs[1].s64,thread,pI); + mem->write(addr+2*size/8,size/8,&ptx_regs[2].s64,thread,pI); + mem->write(addr+3*size/8,size/8,&ptx_regs[3].s64,thread,pI); + delete [] ptx_regs; + } + } + thread->m_last_effective_address = addr; + thread->m_last_memory_space = space; +} + +void sub_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t data; + int overflow = 0; + int carry = 0; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + ptx_reg_t src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + ptx_reg_t src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + //performs addition. Sets carry and overflow if needed. + //the constant is added in during subtraction so the carry bit is set properly. + switch ( i_type ) { + case S8_TYPE: + data.s64 = (src1_data.s64 & 0xFF) - (src2_data.s64 & 0xFF) + 0x100; + if(((src1_data.s64 & 0x80)-(src2_data.s64 & 0x80)) != 0) {overflow=((src1_data.s64 & 0x80)-(data.s64 & 0x80))==0?0:1; } + carry = (data.s32 & 0x100)>>8; + break; + case S16_TYPE: + data.s64 = (src1_data.s64 & 0xFFFF) - (src2_data.s64 & 0xFFFF) + 0x10000; + if(((src1_data.s64 & 0x8000)-(src2_data.s64 & 0x8000)) != 0) {overflow=((src1_data.s64 & 0x8000)-(data.s64 & 0x8000))==0?0:1; } + carry = (data.s32 & 0x10000)>>16; + break; + case S32_TYPE: + data.s64 = (src1_data.s64 & 0xFFFFFFFF) - (src2_data.s64 & 0xFFFFFFFF) + 0x100000000; + if(((src1_data.s64 & 0x80000000)-(src2_data.s64 & 0x80000000)) != 0) {overflow=((src1_data.s64 & 0x80000000)-(data.s64 & 0x80000000))==0?0:1; } + carry = ((data.u64)>>32) & 0x0001; + break; + case S64_TYPE: + data.s64 = src1_data.s64 - src2_data.s64; break; + case B8_TYPE: + case U8_TYPE: + data.u64 = (src1_data.u64 & 0xFF) - (src2_data.u64 & 0xFF) + 0x100; + carry = (data.u64 & 0x100)>>8; + break; + case B16_TYPE: + case U16_TYPE: + data.u64 = (src1_data.u64 & 0xFFFF) - (src2_data.u64 & 0xFFFF) + 0x10000; + carry = (data.u64 & 0x10000)>>16; + break; + case B32_TYPE: + case U32_TYPE: + data.u64 = (src1_data.u64 & 0xFFFFFFFF) - (src2_data.u64 & 0xFFFFFFFF) + 0x100000000; + carry = (data.u64 & 0x100000000)>>32; + break; + case B64_TYPE: + case U64_TYPE: + data.u64 = src1_data.u64 - src2_data.u64; break; + case F16_TYPE: assert(0); break; + case F32_TYPE: data.f32 = src1_data.f32 - src2_data.f32; break; + case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 - src2_data.f64; break; + default: assert(0); break; + } + + thread->set_operand_value(dst,data, i_type, thread, pI, overflow, carry); +} + +void nop_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + // Do nothing +} + +void subc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void suld_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void sured_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void sust_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void suq_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } + +ptx_reg_t* ptx_tex_regs = NULL; + +union intfloat { + int a; + float b; +}; + +float reduce_precision( float x, unsigned bits ) +{ + intfloat tmp; + tmp.b = x; + int v = tmp.a; + int man = v & ((1<<23)-1); + int mask = ((1<= mx) nx -= elem_size; + unsigned ny = (y >= my)? my - 1 : y; + return nx + mx*ny; +} + +typedef unsigned (*texAddr_t) (unsigned x, unsigned y, unsigned mx, unsigned my, size_t elem_size); +float tex_linf_sampling(memory_space* mem, unsigned tex_array_base, + int x, int y, unsigned int width, unsigned int height, size_t elem_size, + float alpha, float beta, texAddr_t b_lim) +{ + float Tij; + float Ti1j; + float Tij1; + float Ti1j1; + + mem->read(tex_array_base + b_lim(x,y,width,height,elem_size), 4, &Tij); + mem->read(tex_array_base + b_lim(x+elem_size,y,width,height,elem_size), 4, &Ti1j); + mem->read(tex_array_base + b_lim(x,y+1,width,height,elem_size), 4, &Tij1); + mem->read(tex_array_base + b_lim(x+elem_size,y+1,width,height,elem_size), 4, &Ti1j1); + + float sample = (1-alpha)*(1-beta)*Tij + + alpha*(1-beta)*Ti1j + + (1-alpha)*beta*Tij1 + + alpha*beta*Ti1j1; + + return sample; +} + +float textureNormalizeElementSigned(int element, int bits) +{ + if (bits) { + int maxN = (1 << bits) - 1; + // removing upper bits + element &= maxN; + // normalizing the number to [-1.0,1.0] + maxN >>= 1; + float output = (float) element / maxN; + if (output < -1.0f) output = -1.0f; + return output; + } else { + return 0.0f; + } +} + +float textureNormalizeElementUnsigned(unsigned int element, int bits) +{ + if (bits) { + unsigned int maxN = (1 << bits) - 1; + // removing upper bits and normalizing the number to [0.0,1.0] + return (float)(element & maxN) / maxN; + } else { + return 0.0f; + } +} + +void textureNormalizeOutput( const struct cudaChannelFormatDesc& desc, ptx_reg_t& datax, ptx_reg_t& datay, ptx_reg_t& dataz, ptx_reg_t& dataw ) +{ + if (desc.f == cudaChannelFormatKindSigned) { + datax.f32 = textureNormalizeElementSigned( datax.s32, desc.x ); + datay.f32 = textureNormalizeElementSigned( datay.s32, desc.y ); + dataz.f32 = textureNormalizeElementSigned( dataz.s32, desc.z ); + dataw.f32 = textureNormalizeElementSigned( dataw.s32, desc.w ); + } else if (desc.f == cudaChannelFormatKindUnsigned) { + datax.f32 = textureNormalizeElementUnsigned( datax.u32, desc.x ); + datay.f32 = textureNormalizeElementUnsigned( datay.u32, desc.y ); + dataz.f32 = textureNormalizeElementUnsigned( dataz.u32, desc.z ); + dataw.f32 = textureNormalizeElementUnsigned( dataw.u32, desc.w ); + } else { + assert(0 && "Undefined texture read mode: cudaReadModeNormalizedFloat expect integer elements"); + } +} + +void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + unsigned dimension = pI->dimension(); + const operand_info &dst = pI->dst(); //the registers to which fetched texel will be placed + const operand_info &src1 = pI->src1(); //the name of the texture + const operand_info &src2 = pI->src2(); //the vector registers containing coordinates of the texel to be fetched + + std::string texname = src1.name(); + unsigned to_type = pI->get_type(); + unsigned c_type = pI->get_type2(); + fflush(stdout); + ptx_reg_t data1, data2, data3, data4; + if (!ptx_tex_regs) ptx_tex_regs = new ptx_reg_t[4]; + unsigned nelem = src2.get_vect_nelem(); + thread->get_vector_operand_values(src2, ptx_tex_regs, nelem); //ptx_reg should be 4 entry vector type...coordinates into texture + + gpgpu_t *gpu = thread->get_gpu(); + const struct textureReference* texref = gpu->get_texref(texname); + const struct cudaArray* cuArray = gpu->get_texarray(texref); + const struct textureInfo* texInfo = gpu->get_texinfo(texref); + const struct textureReferenceAttr* texAttr = gpu->get_texattr(texref); + + //assume always 2D f32 input + //access array with src2 coordinates + memory_space *mem = thread->get_global_memory(); + float x_f32, y_f32; + size_t size; + int t; + unsigned tex_array_base; + unsigned int width = 0, height = 0; + int x = 0; + int y = 0; + unsigned tex_array_index; + float alpha=0, beta=0; + + type_info_key::type_decode(to_type,size,t); + tex_array_base = cuArray->devPtr32; + + switch (dimension) { + case GEOM_MODIFIER_1D: + width = cuArray->width; + height = cuArray->height; + if (texref->normalized) { + assert(c_type == F32_TYPE); + x_f32 = ptx_tex_regs[0].f32; + if (texref->addressMode[0] == cudaAddressModeClamp) { + x_f32 = (x_f32 > 1.0)? 1.0 : x_f32; + x_f32 = (x_f32 < 0.0)? 0.0 : x_f32; + } else if (texref->addressMode[0] == cudaAddressModeWrap) { + x_f32 = x_f32 - floor(x_f32); + } + + if( texref->filterMode == cudaFilterModeLinear ) { + float xb = x_f32 * width - 0.5; + alpha = xb - floor(xb); + alpha = reduce_precision(alpha,9); + beta = 0.0; + + x = (int)floor(xb); + y = 0; + } else { + x = (int) floor(x_f32 * width); + y = 0; + } + } else { + switch ( c_type ) { + case S32_TYPE: + x = ptx_tex_regs[0].s32; + assert(texref->filterMode == cudaFilterModePoint); + break; + case F32_TYPE: + x_f32 = ptx_tex_regs[0].f32; + alpha = x_f32 - floor(x_f32); // offset into subtexel (for linear sampling) + x = (int) x_f32; + break; + default: assert(0 && "Unsupported texture coordinate type."); + } + // handle texture fetch that exceeded boundaries + if (texref->addressMode[0] == cudaAddressModeClamp) { + x = (x > width - 1)? (width - 1) : x; + x = (x < 0)? 0 : x; + } else if (texref->addressMode[0] == cudaAddressModeWrap) { + x = x % width; + } + } + width *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; + x *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; + tex_array_index = tex_array_base + x; + + break; + case GEOM_MODIFIER_2D: + width = cuArray->width; + height = cuArray->height; + if (texref->normalized) { + x_f32 = reduce_precision(ptx_tex_regs[0].f32,16); + y_f32 = reduce_precision(ptx_tex_regs[1].f32,15); + + if (texref->addressMode[0]) {//clamp + if (x_f32<0) x_f32 = 0; + if (x_f32>=1) x_f32 = 1 - 1/x_f32; + } else {//wrap + x_f32 = x_f32 - floor(x_f32); + } + if (texref->addressMode[1]) {//clamp + if (y_f32<0) y_f32 = 0; + if (y_f32>=1) y_f32 = 1 - 1/y_f32; + } else {//wrap + y_f32 = y_f32 - floor(y_f32); + } + + if( texref->filterMode == cudaFilterModeLinear ) { + float xb = x_f32 * width - 0.5; + float yb = y_f32 * height - 0.5; + alpha = xb - floor(xb); + beta = yb - floor(yb); + alpha = reduce_precision(alpha,9); + beta = reduce_precision(beta,9); + + x = (int)floor(xb); + y = (int)floor(yb); + } else { + x = (int) floor(x_f32 * width); + y = (int) floor(y_f32 * height); + } + } else { + x_f32 = ptx_tex_regs[0].f32; + y_f32 = ptx_tex_regs[1].f32; + + alpha = x_f32 - floor(x_f32); + beta = y_f32 - floor(y_f32); + + x = (int) x_f32; + y = (int) y_f32; + if (texref->addressMode[0]) {//clamp + if (x<0) x = 0; + if (x>= (int)width) x = width-1; + } else {//wrap + x = x % width; + if (x < 0) x*= -1; + } + if (texref->addressMode[1]) {//clamp + if (y<0) y = 0; + if (y>= (int)height) y = height -1; + } else {//wrap + y = y % height; + if (y < 0) y *= -1; + } + } + + width *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; + x *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; + tex_array_index = tex_array_base + (x + width*y); + break; + default: + assert(0); break; + } + switch ( to_type ) { + case U8_TYPE: + case U16_TYPE: + case U32_TYPE: + case B8_TYPE: + case B16_TYPE: + case B32_TYPE: + case S8_TYPE: + case S16_TYPE: + case S32_TYPE: { + unsigned long long elementOffset = 0; // offset into the next element + mem->read( tex_array_index, cuArray->desc.x/8, &data1.u32); + elementOffset += cuArray->desc.x/8; + if (cuArray->desc.y) { + mem->read( tex_array_index + elementOffset, cuArray->desc.y/8, &data2.u32); + elementOffset += cuArray->desc.y/8; + if (cuArray->desc.z) { + mem->read( tex_array_index + elementOffset, cuArray->desc.z/8, &data3.u32); + elementOffset += cuArray->desc.z/8; + if (cuArray->desc.w) + mem->read( tex_array_index + elementOffset, cuArray->desc.w/8, &data4.u32); + } + } + break; + } + case B64_TYPE: + case U64_TYPE: + case S64_TYPE: + mem->read( tex_array_index, 8, &data1.u64); + if (cuArray->desc.y) { + mem->read( tex_array_index+8, 8, &data2.u64); + if (cuArray->desc.z) { + mem->read( tex_array_index+16, 8, &data3.u64); + if (cuArray->desc.w) + mem->read( tex_array_index+24, 8, &data4.u64); + } + } + break; + case F16_TYPE: assert(0); break; + case F32_TYPE: { + if( texref->filterMode == cudaFilterModeLinear ) { + texAddr_t b_lim = wrap; + if ( texref->addressMode[0] == cudaAddressModeClamp ) { + b_lim = clamp; + } + size_t elem_size = (cuArray->desc.x + cuArray->desc.y + cuArray->desc.z + cuArray->desc.w) / 8; + size_t elem_ofst = 0; + + data1.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); + elem_ofst += cuArray->desc.x / 8; + if (cuArray->desc.y) { + data2.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); + elem_ofst += cuArray->desc.y / 8; + if (cuArray->desc.z) { + data3.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); + elem_ofst += cuArray->desc.z / 8; + if (cuArray->desc.w) + data4.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); + } + } + } else { + mem->read( tex_array_index, cuArray->desc.x/8, &data1.f32); + if (cuArray->desc.y) { + mem->read( tex_array_index+4, cuArray->desc.y/8, &data2.f32); + if (cuArray->desc.z) { + mem->read( tex_array_index+8, cuArray->desc.z/8, &data3.f32); + if (cuArray->desc.w) + mem->read( tex_array_index+12, cuArray->desc.w/8, &data4.f32); + } + } + } + } break; + case F64_TYPE: + case FF64_TYPE: + mem->read( tex_array_index, 8, &data1.f64); + if (cuArray->desc.y) { + mem->read( tex_array_index+8, 8, &data2.f64); + if (cuArray->desc.z) { + mem->read( tex_array_index+16, 8, &data3.f64); + if (cuArray->desc.w) + mem->read( tex_array_index+24, 8, &data4.f64); + } + } + break; + default: assert(0); break; + } + int x_block_coord, y_block_coord, memreqindex, blockoffset; + + switch (dimension) { + case GEOM_MODIFIER_1D: + thread->m_last_effective_address = tex_array_index; + break; + case GEOM_MODIFIER_2D: + x_block_coord = x >> (texInfo->Tx_numbits + texInfo->texel_size_numbits); + y_block_coord = y >> texInfo->Ty_numbits; + + memreqindex = ((y_block_coord*cuArray->width/texInfo->Tx)+x_block_coord)<<6; + + blockoffset = (x%(texInfo->Tx*texInfo->texel_size) + (y%(texInfo->Ty)<<(texInfo->Tx_numbits + texInfo->texel_size_numbits))); + memreqindex += blockoffset; + thread->m_last_effective_address = tex_array_base + memreqindex;//tex_array_index; + break; + default: + assert(0); + } + thread->m_last_memory_space = tex_space; + + // normalize output into floating point numbers according to the texture read mode + if (texAttr->m_readmode == cudaReadModeNormalizedFloat) { + textureNormalizeOutput(cuArray->desc, data1, data2, data3, data4); + } else { + assert(texAttr->m_readmode == cudaReadModeElementType); + } + + thread->set_vector_operand_values(dst,data1,data2,data3,data4); +} + +void txq_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void trap_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vabsdiff_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vadd_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vmad_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vmax_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vmin_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vset_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vshl_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vshr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } +void vsub_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } + +void vote_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + static bool first_in_warp = true; + static bool and_all; + static bool or_all; + static unsigned int ballot_result; + static std::list threads_in_warp; + static unsigned last_tid; + + if( first_in_warp ) { + first_in_warp = false; + threads_in_warp.clear(); + and_all = true; + or_all = false; + ballot_result = 0; + int offset=31; + while( (offset>=0) && !pI->active(offset) ) + offset--; + assert( offset >= 0 ); + last_tid = (thread->get_hw_tid() - (thread->get_hw_tid()%pI->warp_size())) + offset; + } + + ptx_reg_t src1_data; + const operand_info &src1 = pI->src1(); + src1_data = thread->get_operand_value(src1, pI->dst(), PRED_TYPE, thread, 1); + + //predicate value was changed so the lowest bit being set means the zero flag is set. + //As a result, the value of src1_data.pred must be inverted to get proper behavior + bool pred_value = !(src1_data.pred & 0x0001); + bool invert = src1.is_neg_pred(); + + threads_in_warp.push_back(thread); + and_all &= (invert ^ pred_value); + or_all |= (invert ^ pred_value); + + // vote.ballot + if (invert ^ pred_value) { + int lane_id = thread->get_hw_tid() % pI->warp_size(); + ballot_result |= (1 << lane_id); + } + + if( thread->get_hw_tid() == last_tid ) { + if (pI->vote_mode() == ptx_instruction::vote_ballot) { + ptx_reg_t data = ballot_result; + for( std::list::iterator t=threads_in_warp.begin(); t!=threads_in_warp.end(); ++t ) { + const operand_info &dst = pI->dst(); + (*t)->set_operand_value(dst,data, pI->get_type(), (*t), pI); + } + } else { + bool pred_value = false; + + switch( pI->vote_mode() ) { + case ptx_instruction::vote_any: pred_value = or_all; break; + case ptx_instruction::vote_all: pred_value = and_all; break; + case ptx_instruction::vote_uni: pred_value = (or_all ^ and_all); break; + default: + abort(); + } + ptx_reg_t data; + data.pred = pred_value?0:1; //the way ptxplus handles the zero flag, 1 = false and 0 = true + + for( std::list::iterator t=threads_in_warp.begin(); t!=threads_in_warp.end(); ++t ) { + const operand_info &dst = pI->dst(); + (*t)->set_operand_value(dst,data, PRED_TYPE, (*t), pI); + } + } + first_in_warp = true; + } +} + +void xor_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +{ + ptx_reg_t src1_data, src2_data, data; + + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned i_type = pI->get_type(); + src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); + src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + + //the way ptxplus handles predicates: 1 = false and 0 = true + if(i_type == PRED_TYPE) + data.pred = ~(~(src1_data.pred) ^ ~(src2_data.pred)); + else + data.u64 = src1_data.u64 ^ src2_data.u64; + + thread->set_operand_value(dst,data, i_type, thread, pI); +} + +void inst_not_implemented( const ptx_instruction * pI ) +{ + printf("GPGPU-Sim PTX: ERROR (%s:%u) instruction \"%s\" not (yet) implemented\n", + pI->source_file(), + pI->source_line(), + pI->get_opcode_cstr() ); + abort(); +} + +ptx_reg_t srcOperandModifiers(ptx_reg_t opData, operand_info opInfo, operand_info dstInfo, unsigned type, ptx_thread_info *thread) +{ + ptx_reg_t result; + memory_space *mem = NULL; + size_t size; + int t; + result.u64=0; + + //complete other cases for reading from memory, such as reading from other const memory + if(opInfo.get_addr_space() == global_space) + { + mem = thread->get_global_memory(); + type_info_key::type_decode(type,size,t); + mem->read(opData.u32,size/8,&result.u64); + if( type == S16_TYPE || type == S32_TYPE ) + sign_extend(result,size,dstInfo); + } + else if(opInfo.get_addr_space() == shared_space) + { + mem = thread->m_shared_mem; + type_info_key::type_decode(type,size,t); + mem->read(opData.u32,size/8,&result.u64); + + if( type == S16_TYPE || type == S32_TYPE ) + sign_extend(result,size,dstInfo); + + } + else if(opInfo.get_addr_space() == const_space) + { + mem = thread->get_global_memory(); + type_info_key::type_decode(type,size,t); + + mem->read((opData.u32 + opInfo.get_const_mem_offset()),size/8,&result.u64); + + if( type == S16_TYPE || type == S32_TYPE ) + sign_extend(result,size,dstInfo); + } + else + { + result = opData; + } + + if(opInfo.get_operand_lohi() == 1) + { + result.u64 = result.u64 & 0xFFFF; + } + else if(opInfo.get_operand_lohi() == 2) + { + result.u64 = (result.u64>>16) & 0xFFFF; + } + + if(opInfo.get_operand_neg() == true) { + result.f32 = -result.f32; + } + + return result; +} + diff --git a/src/cuda-sim/ptx_loader.cc~ b/src/cuda-sim/ptx_loader.cc~ new file mode 100644 index 0000000..c922b18 --- /dev/null +++ b/src/cuda-sim/ptx_loader.cc~ @@ -0,0 +1,462 @@ +// Copyright (c) 2009-2011, Tor M. Aamodt +// The University of British Columbia +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// Redistributions in binary form must reproduce the above copyright notice, this +// list of conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. +// Neither the name of The University of British Columbia nor the names of its +// contributors may be used to endorse or promote products derived from this +// software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#include "ptx_loader.h" +#include "ptx_ir.h" +#include "cuda-sim.h" +#include "ptx_parser.h" +#include +#include +#include +#include + +/// globals + +memory_space *g_global_mem; +memory_space *g_tex_mem; +memory_space *g_surf_mem; +memory_space *g_param_mem; +bool g_override_embedded_ptx = false; + +/// extern prototypes + +extern int ptx_parse(); +extern int ptx__scan_string(const char*); + +extern std::map get_duplicate(); + +const char *g_ptxinfo_filename; +extern int ptxinfo_parse(); +extern int ptxinfo_debug; +extern FILE *ptxinfo_in; + +static bool g_save_embedded_ptx; +bool g_keep_intermediate_files; +bool m_ptx_save_converted_ptxplus; + +bool keep_intermediate_files() {return g_keep_intermediate_files;} + +void ptx_reg_options(option_parser_t opp) +{ + option_parser_register(opp, "-save_embedded_ptx", OPT_BOOL, &g_save_embedded_ptx, + "saves ptx files embedded in binary as .ptx", + "0"); + option_parser_register(opp, "-keep", OPT_BOOL, &g_keep_intermediate_files, + "keep intermediate files created by GPGPU-Sim when interfacing with external programs", + "0"); + option_parser_register(opp, "-gpgpu_ptx_save_converted_ptxplus", OPT_BOOL, + &m_ptx_save_converted_ptxplus, + "Saved converted ptxplus to a file", + "0"); +} + +void print_ptx_file( const char *p, unsigned source_num, const char *filename ) +{ + printf("\nGPGPU-Sim PTX: file _%u.ptx contents:\n\n", source_num ); + char *s = strdup(p); + char *t = s; + unsigned n=1; + while ( *t != '\0' ) { + char *u = t; + while ( (*u != '\n') && (*u != '\0') ) u++; + unsigned last = (*u == '\0'); + *u = '\0'; + const ptx_instruction *pI = ptx_instruction_lookup(filename,n); + char pc[64]; + if( pI && pI->get_PC() ) + snprintf(pc,64,"%4u", pI->get_PC() ); + else + snprintf(pc,64," "); + printf(" _%u.ptx %4u (pc=%s): %s\n", source_num, n, pc, t ); + if ( last ) break; + t = u+1; + n++; + } + free(s); + fflush(stdout); +} + +char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptxfilename, const std::string elffilename, const std::string sassfilename) +{ + + printf("GPGPU-Sim PTX: converting EMBEDDED .ptx file to ptxplus \n"); + + char fname_ptxplus[1024]; + snprintf(fname_ptxplus,1024,"_ptxplus_XXXXXX"); + int fd4=mkstemp(fname_ptxplus); + close(fd4); + + // Run cuobjdump_to_ptxplus + char commandline[1024]; + int result; + snprintf(commandline, 1024, "$GPGPUSIM_ROOT/build/$GPGPUSIM_CONFIG/cuobjdump_to_ptxplus/cuobjdump_to_ptxplus %s %s %s %s", + ptxfilename.c_str(), + sassfilename.c_str(), + elffilename.c_str(), + fname_ptxplus); + fflush(stdout); + printf("GPGPU-Sim PTX: calling cuobjdump_to_ptxplus\ncommandline: %s\n", commandline); + result = system(commandline); + if(result){printf("GPGPU-Sim PTX: ERROR ** could not execute %s\n", commandline); exit(1);} + + + // Get ptxplus from file + std::ifstream fileStream(fname_ptxplus, std::ios::in); + std::string text, line; + while(getline(fileStream,line)) { + text += (line + "\n"); + } + fileStream.close(); + + char* ptxplus_str = new char [strlen(text.c_str())+1]; + strcpy(ptxplus_str, text.c_str()); + + if (!m_ptx_save_converted_ptxplus){ + char rm_commandline[1024]; + + snprintf(rm_commandline,1024,"rm -f %s", fname_ptxplus); + + printf("GPGPU-Sim PTX: removing temporary files using \"%s\"\n", rm_commandline); + int rm_result = system(rm_commandline); + if( rm_result != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while removing temporary files %d\n", rm_result); + exit(1); + } + } + printf("GPGPU-Sim PTX: DONE converting EMBEDDED .ptx file to ptxplus \n"); + + return ptxplus_str; +} + + +symbol_table *gpgpu_ptx_sim_load_ptx_from_string( const char *p, unsigned source_num ) +{ + char buf[1024]; + snprintf(buf,1024,"_%u.ptx", source_num ); + if( g_save_embedded_ptx ) { + FILE *fp = fopen(buf,"w"); + fprintf(fp,"%s",p); + fclose(fp); + } + symbol_table *symtab=init_parser(buf); + ptx__scan_string(p); + int errors = ptx_parse (); + if ( errors ) { + char fname[1024]; + snprintf(fname,1024,"_ptx_errors_XXXXXX"); + int fd=mkstemp(fname); + close(fd); + printf("GPGPU-Sim PTX: parser error detected, exiting... but first extracting .ptx to \"%s\"\n", fname); + FILE *ptxfile = fopen(fname,"w"); + fprintf(ptxfile,"%s", p ); + fclose(ptxfile); + abort(); + exit(40); + } + + //if ( g_debug_execution >= 100 ) + print_ptx_file(p,source_num,buf); + + printf("GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file %s\n",buf); + return symtab; +} + +void fix_duplicate_errors(char fname2[1024]) { + char tempfile[1024] = "_temp_ptx"; + char commandline[1024]; + + // change the name of the ptx file to _temp_ptx + snprintf(commandline,1024,"mv %s %s",fname2,tempfile); + printf("Running: %s\n", commandline); + int result = system(commandline); + if (result != 0) { + printf("GPGPU-Sim PTX: ERROR ** while changing filename from %s to %s", fname2, tempfile); + exit(1); + } + + // store all of the ptx into a char array + FILE *ptxsource = fopen(tempfile,"r"); + fseek(ptxsource, 0, SEEK_END); + long filesize = ftell(ptxsource); + rewind(ptxsource); + char *ptxdata = (char*)malloc((filesize+1)*sizeof(char)); + fread(ptxdata, filesize, 1, ptxsource); + fclose(ptxsource); + + FILE *ptxdest = fopen(fname2,"w"); + std::map duplicate = get_duplicate(); + unsigned offset; + unsigned oldlinenum = 1; + unsigned linenum; + char *startptr = ptxdata; + char *funcptr; + char *tempptr = ptxdata - 1; + char *lineptr = ptxdata - 1; + + // recreate the ptx file without duplications + for ( std::map::iterator iter = duplicate.begin(); + iter != duplicate.end(); + iter++){ + // find the line of the next error + linenum = iter->first; + for (int i = oldlinenum; i < linenum; i++) { + lineptr = strchr(lineptr + 1, '\n'); + } + + // find the end of the current section to be copied over + // then find the start of the next section that will be copied + if (strcmp("function", iter->second) == 0) { + // get location of most recent .func + while (tempptr < lineptr && tempptr != NULL) { + funcptr = tempptr; + tempptr = strstr(funcptr + 1, ".func"); + } + + // get the start of the previous line + offset = 0; + while (*(funcptr - offset) != '\n') offset++; + + fwrite(startptr, sizeof(char), funcptr - offset + 1 - startptr, ptxdest); + + //find next location of startptr + if (*(lineptr + 3) == ';') { + // for function definitions + startptr = lineptr + 5; + } else if (*(lineptr + 3) == '{') { + // for functions enclosed with curly brackets + offset = 5; + unsigned bracket = 1; + while (bracket != 0) { + if (*(lineptr + offset) == '{') bracket++; + else if (*(lineptr + offset) == '}') bracket--; + offset++; + } + startptr = lineptr + offset + 1; + } else { + printf("GPGPU-Sim PTX: ERROR ** Unrecognized function format\n"); + abort(); + } + } else if (strcmp("variable", iter->second) == 0) { + fwrite(startptr, sizeof(char), (int)(lineptr + 1 - startptr), ptxdest); + + //find next location of startptr + offset = 1; + while (*(lineptr + offset) != '\n') offset++; + startptr = lineptr + offset + 1; + } else { + printf("GPGPU-Sim PTX: ERROR ** Unsupported duplicate type: %s\n", iter->second); + } + + oldlinenum = linenum; + } + // copy over the rest of the file + fwrite(startptr, sizeof(char), ptxdata + filesize - startptr, ptxdest); + + // cleanup + free(ptxdata); + fclose(ptxdest); + snprintf(commandline,1024,"rm -f %s",tempfile); + printf("Running: %s\n", commandline); + result = system(commandline); + if (result != 0) { + printf("GPGPU-Sim PTX: ERROR ** while deleting %s", tempfile); + exit(1); + } +} + +//we need the application name here too. +char* get_app_binary_name(){ + char exe_path[1025]; + char *self_exe_path; +#ifdef __APPLE__ + //AMRUTH: get apple device and check the result. + printf("WARNING: not tested for Apple-mac devices \n"); + abort(); +#else + std::stringstream exec_link; + exec_link << "/proc/self/exe"; + ssize_t path_length = readlink(exec_link.str().c_str(), exe_path, 1024); + assert(path_length != -1); + exe_path[path_length] = '\0'; + + char *token = strtok(exe_path, "/"); + while(token !=NULL){ + self_exe_path = token; + token = strtok(NULL,"/"); + } +#endif + self_exe_path = strtok(self_exe_path, "."); + printf("self exe links to: %s\n", self_exe_path); + return self_exe_path; +} + +void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version ) +{ + //do ptxas for individual files instead of one big embedded ptx. This prevents the duplicate defs and declarations. + char ptx_file[1000]; + char *name=get_app_binary_name(); + char commandline[4096], fname[1024], fname2[1024], final_tempfile_ptxinfo[1024], tempfile_ptxinfo[1024]; + for (int index=1; index <= no_of_ptx; index++){ + snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", name, index, sm_version); + snprintf(fname,1024,"_ptx_XXXXXX"); + int fd=mkstemp(fname); + close(fd); + + printf("GPGPU-Sim PTX: extracting embedded .ptx to temporary file \"%s\"\n", fname); + snprintf(commandline,4096,"cat %s > %s",ptx_file, fname); + if (system(commandline) !=0) { + printf("ERROR: %s command failed\n", commandline); + exit(0); + } + + snprintf(fname2,1024,"_ptx2_XXXXXX"); + fd=mkstemp(fname2); + close(fd); + char commandline2[4096]; + snprintf(commandline2,4096,"cat %s | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\\(\\.extern \\.const\\[1\\] .b8 \\w\\+\\)\\[\\]/\\1\\[1\\]/' | sed 's/const\\[.\\]/const\\[0\\]/g' > %s", fname, fname2); + printf("Running: %s\n", commandline2); + int result = system(commandline2); + if( result != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); + printf(" Ensure you have write access to simulation directory\n"); + printf(" and have \'cat\' and \'sed\' in your path.\n"); + exit(1); + } + + snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); + char extra_flags[1024]; + extra_flags[0]=0; + + #if CUDART_VERSION >= 3000 + if (sm_version == 0) sm_version = 20; + extern bool g_cdp_enabled; + if(!g_cdp_enabled) + snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); + else + snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version); + #endif + + snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", + extra_flags, fname2, tempfile_ptxinfo); + printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); + result = system(commandline); + if( result != 0 ) { + // 65280 = duplicate errors + if (result == 65280) { + ptxinfo_in = fopen(tempfile_ptxinfo,"r"); + g_ptxinfo_filename = tempfile_ptxinfo; + ptxinfo_parse(); + + fix_duplicate_errors(fname2); + snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", + extra_flags, fname2, tempfile_ptxinfo); + printf("GPGPU-Sim PTX: regenerating ptxinfo using \"%s\"\n", commandline); + result = system(commandline); + } + if (result != 0) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); + printf(" Ensure ptxas is in your path.\n"); + exit(1); + } + } + } + + //TODO: duplicate code! move it into a function so that it can be reused! + if(no_of_ptx==0) { + //For CDP, we dump everything. So no_of_ptx will be 0. + snprintf(fname,1024,"_ptx_XXXXXX"); + int fd=mkstemp(fname); + close(fd); + + printf("GPGPU-Sim PTX: extracting embedded .ptx to temporary file \"%s\"\n", fname); + FILE *ptxfile = fopen(fname,"w"); + fprintf(ptxfile,"%s", p_for_info); + fclose(ptxfile); + + snprintf(fname2,1024,"_ptx2_XXXXXX"); + fd=mkstemp(fname2); + close(fd); + char commandline2[4096]; + snprintf(commandline2,4096,"cat %s | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\\(\\.extern \\.const\\[1\\] .b8 \\w\\+\\)\\[\\]/\\1\\[1\\]/' | sed 's/const\\[.\\]/const\\[0\\]/g' > %s", fname, fname2); + printf("Running: %s\n", commandline2); + int result = system(commandline2); + if( result != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); + printf(" Ensure you have write access to simulation directory\n"); + printf(" and have \'cat\' and \'sed\' in your path.\n"); + exit(1); + } + //char tempfile_ptxinfo[1024]; + snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); + char extra_flags[1024]; + extra_flags[0]=0; +#if CUDART_VERSION >= 3000 + snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); +#endif + + snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", + extra_flags, fname2, tempfile_ptxinfo); + printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); + result = system(commandline); + if( result != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); + printf(" Ensure ptxas is in your path.\n"); + exit(1); + } + } + + //Now that we got resource usage per kernel in a ptx file, we dump all into one file and pass it to rest of the code as usual. + if(no_of_ptx>0){ + char commandline3[4096]; + snprintf(final_tempfile_ptxinfo,1024,"f_tempfile_ptx"); + snprintf(commandline3,4096, "cat *info > %s", final_tempfile_ptxinfo); + if (system(commandline3)!=0) { + printf("ERROR: Either we dont have info files or cat is not working \n"); + printf("ERROR: %s command failed\n",commandline3); + exit(1); + } + } + + ptxinfo_in = fopen(final_tempfile_ptxinfo,"r"); + if(no_of_ptx>0) + g_ptxinfo_filename = final_tempfile_ptxinfo; + else + g_ptxinfo_filename = tempfile_ptxinfo; + ptxinfo_parse(); + + if( ! g_save_embedded_ptx ) { + if(no_of_ptx>0) + snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, final_tempfile_ptxinfo); + else + snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, tempfile_ptxinfo); + printf("GPGPU-Sim PTX: removing ptxinfo using \"%s\"\n", commandline); + if( system(commandline) != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while removing temporary files\n"); + exit(1); + } + } +} -- cgit v1.3 -- cgit v1.3 From f9c42bd10a37b2e7556f006641eff11090762e7e Mon Sep 17 00:00:00 2001 From: Amruth Date: Tue, 3 Apr 2018 12:02:34 -0700 Subject: remove temporarily generated files --- libcuda/cuda_runtime_api.cc~ | 2515 ----------------------- src/cuda-sim/cuda-sim.cc~ | 2155 -------------------- src/cuda-sim/instructions.cc~ | 4517 ----------------------------------------- src/cuda-sim/ptx_loader.cc~ | 462 ----- 4 files changed, 9649 deletions(-) delete mode 100644 libcuda/cuda_runtime_api.cc~ delete mode 100644 src/cuda-sim/cuda-sim.cc~ delete mode 100644 src/cuda-sim/instructions.cc~ delete mode 100644 src/cuda-sim/ptx_loader.cc~ diff --git a/libcuda/cuda_runtime_api.cc~ b/libcuda/cuda_runtime_api.cc~ deleted file mode 100644 index de7f5e9..0000000 --- a/libcuda/cuda_runtime_api.cc~ +++ /dev/null @@ -1,2515 +0,0 @@ -// This file created from cuda_runtime_api.h distributed with CUDA 1.1 -// Changes Copyright 2009, Tor M. Aamodt, Ali Bakhoda and George L. Yuan -// University of British Columbia - -/* - * cuda_runtime_api.cc - * - * Copyright © 2009 by Tor M. Aamodt, Wilson W. L. Fung, Ali Bakhoda, - * George L. Yuan and the University of British Columbia, Vancouver, - * BC V6T 1Z4, All Rights Reserved. - * - * THIS IS A LEGAL DOCUMENT BY DOWNLOADING GPGPU-SIM, YOU ARE AGREEING TO THESE - * TERMS AND CONDITIONS. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNERS OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * NOTE: The files libcuda/cuda_runtime_api.c and src/cuda-sim/cuda-math.h - * are derived from the CUDA Toolset available from http://www.nvidia.com/cuda - * (property of NVIDIA). The files benchmarks/BlackScholes/ and - * benchmarks/template/ are derived from the CUDA SDK available from - * http://www.nvidia.com/cuda (also property of NVIDIA). The files from - * src/intersim/ are derived from Booksim (a simulator provided with the - * textbook "Principles and Practices of Interconnection Networks" available - * from http://cva.stanford.edu/books/ppin/). As such, those files are bound by - * the corresponding legal terms and conditions set forth separately (original - * copyright notices are left in files from these sources and where we have - * modified a file our copyright notice appears before the original copyright - * notice). - * - * Using this version of GPGPU-Sim requires a complete installation of CUDA - * which is distributed seperately by NVIDIA under separate terms and - * conditions. To use this version of GPGPU-Sim with OpenCL requires a - * recent version of NVIDIA's drivers which support OpenCL. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the University of British Columbia nor the names of - * its contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * 4. This version of GPGPU-SIM is distributed freely for non-commercial use only. - * - * 5. No nonprofit user may place any restrictions on the use of this software, - * including as modified by the user, by any other authorized user. - * - * 6. GPGPU-SIM was developed primarily by Tor M. Aamodt, Wilson W. L. Fung, - * Ali Bakhoda, George L. Yuan, at the University of British Columbia, - * Vancouver, BC V6T 1Z4 - */ - -/* - * Copyright 1993-2007 NVIDIA Corporation. All rights reserved. - * - * NOTICE TO USER: - * - * This source code is subject to NVIDIA ownership rights under U.S. and - * international Copyright laws. Users and possessors of this source code - * are hereby granted a nonexclusive, royalty-free license to use this code - * in individual and commercial software. - * - * NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE - * CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR - * IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH - * REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE. - * IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, - * OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS - * OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE - * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE - * OR PERFORMANCE OF THIS SOURCE CODE. - * - * U.S. Government End Users. This source code is a "commercial item" as - * that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of - * "commercial computer software" and "commercial computer software - * documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995) - * and is provided to the U.S. Government only as a commercial end item. - * Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through - * 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the - * source code with only those rights set forth herein. - * - * Any use of this source code in individual and commercial software must - * include, in the user documentation and internal comments to the code, - * the above Disclaimer and U.S. Government End Users Notice. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef OPENGL_SUPPORT -#define GL_GLEXT_PROTOTYPES -#ifdef __APPLE__ -#include // Apple's version of GLUT is here -#else -#include -#endif -#endif - -#define __CUDA_RUNTIME_API_H__ - -#include "host_defines.h" -#include "builtin_types.h" -#include "driver_types.h" -#if (CUDART_VERSION < 8000) -#include "__cudaFatFormat.h" -#endif -#include "../src/gpgpu-sim/gpu-sim.h" -#include "../src/cuda-sim/ptx_loader.h" -#include "../src/cuda-sim/cuda-sim.h" -#include "../src/cuda-sim/ptx_ir.h" -#include "../src/cuda-sim/ptx_parser.h" -#include "../src/gpgpusim_entrypoint.h" -#include "../src/stream_manager.h" -#include "../src/abstract_hardware_model.h" - -#include -#include - -#ifdef __APPLE__ -#include -#endif - -std::map pinned_memory; //support for pinned memories added -std::map pinned_memory_size; -int no_of_ptx=0; - -extern void synchronize(); -extern void exit_simulation(); - -static int load_static_globals( symbol_table *symtab, unsigned min_gaddr, unsigned max_gaddr, gpgpu_t *gpu ); -static int load_constants( symbol_table *symtab, addr_t min_gaddr, gpgpu_t *gpu ); - -static kernel_info_t *gpgpu_cuda_ptx_sim_init_grid( const char *kernel_key, - gpgpu_ptx_sim_arg_list_t args, - struct dim3 gridDim, - struct dim3 blockDim, - struct CUctx_st* context ); - -/*DEVICE_BUILTIN*/ -struct cudaArray -{ - void *devPtr; - int devPtr32; - struct cudaChannelFormatDesc desc; - int width; - int height; - int size; //in bytes - unsigned dimensions; -}; - -#if !defined(__dv) -#if defined(__cplusplus) -#define __dv(v) \ - = v -#else /* __cplusplus */ -#define __dv(v) -#endif /* __cplusplus */ -#endif /* !__dv */ - -cudaError_t g_last_cudaError = cudaSuccess; - -extern stream_manager *g_stream_manager; - -void register_ptx_function( const char *name, function_info *impl ) -{ - // no longer need this -} - -#if defined __APPLE__ -# define __my_func__ __PRETTY_FUNCTION__ -#else -# if defined __cplusplus ? __GNUC_PREREQ (2, 6) : __GNUC_PREREQ (2, 4) -# define __my_func__ __PRETTY_FUNCTION__ -# else -# if defined __STDC_VERSION__ && __STDC_VERSION__ >= 199901L -# define __my_func__ __func__ -# else -# define __my_func__ ((__const char *) 0) -# endif -# endif -#endif - -struct _cuda_device_id { - _cuda_device_id(gpgpu_sim* gpu) {m_id = 0; m_next = NULL; m_gpgpu=gpu;} - struct _cuda_device_id *next() { return m_next; } - unsigned num_shader() const { return m_gpgpu->get_config().num_shader(); } - int num_devices() const { - if( m_next == NULL ) return 1; - else return 1 + m_next->num_devices(); - } - struct _cuda_device_id *get_device( unsigned n ) - { - assert( n < (unsigned)num_devices() ); - struct _cuda_device_id *p=this; - for(unsigned i=0; im_next; - return p; - } - const struct cudaDeviceProp *get_prop() const - { - return m_gpgpu->get_prop(); - } - unsigned get_id() const { return m_id; } - - gpgpu_sim *get_gpgpu() { return m_gpgpu; } -private: - unsigned m_id; - class gpgpu_sim *m_gpgpu; - struct _cuda_device_id *m_next; -}; - -struct CUctx_st { - CUctx_st( _cuda_device_id *gpu ) - { - m_gpu = gpu; - m_binary_info.cmem = 0; - m_binary_info.gmem = 0; - } - - _cuda_device_id *get_device() { return m_gpu; } - - void add_binary( symbol_table *symtab, unsigned fat_cubin_handle ) - { - m_code[fat_cubin_handle] = symtab; - m_last_fat_cubin_handle = fat_cubin_handle; - } - - void add_ptxinfo( const char *deviceFun, const struct gpgpu_ptx_sim_info &info ) - { - symbol *s = m_code[m_last_fat_cubin_handle]->lookup(deviceFun); - assert( s != NULL ); - function_info *f = s->get_pc(); - assert( f != NULL ); - f->set_kernel_info(info); - } - - void add_ptxinfo( const struct gpgpu_ptx_sim_info &info ) - { - m_binary_info = info; - } - - void register_function( unsigned fat_cubin_handle, const char *hostFun, const char *deviceFun ) - { - if( m_code.find(fat_cubin_handle) != m_code.end() ) { - symbol *s = m_code[fat_cubin_handle]->lookup(deviceFun); - if(s != NULL) { - function_info *f = s->get_pc(); - assert( f != NULL ); - m_kernel_lookup[hostFun] = f; - } - else { - printf("Warning: cannot find deviceFun %s\n", deviceFun); - m_kernel_lookup[hostFun] = NULL; - } - // assert( s != NULL ); - // function_info *f = s->get_pc(); - // assert( f != NULL ); - // m_kernel_lookup[hostFun] = f; - } else { - m_kernel_lookup[hostFun] = NULL; - } - } - - function_info *get_kernel(const char *hostFun) - { - std::map::iterator i=m_kernel_lookup.find(hostFun); - assert( i != m_kernel_lookup.end() ); - return i->second; - } - -private: - _cuda_device_id *m_gpu; // selected gpu - std::map m_code; // fat binary handle => global symbol table - unsigned m_last_fat_cubin_handle; - std::map m_kernel_lookup; // unique id (CUDA app function address) => kernel entry point - struct gpgpu_ptx_sim_info m_binary_info; - -}; - -class kernel_config { -public: - kernel_config( dim3 GridDim, dim3 BlockDim, size_t sharedMem, struct CUstream_st *stream ) - { - m_GridDim=GridDim; - m_BlockDim=BlockDim; - m_sharedMem=sharedMem; - m_stream = stream; - } - void set_arg( const void *arg, size_t size, size_t offset ) - { - m_args.push_front( gpgpu_ptx_sim_arg(arg,size,offset) ); - } - dim3 grid_dim() const { return m_GridDim; } - dim3 block_dim() const { return m_BlockDim; } - gpgpu_ptx_sim_arg_list_t get_args() { return m_args; } - struct CUstream_st *get_stream() { return m_stream; } - -private: - dim3 m_GridDim; - dim3 m_BlockDim; - size_t m_sharedMem; - struct CUstream_st *m_stream; - gpgpu_ptx_sim_arg_list_t m_args; -}; - -class _cuda_device_id *GPGPUSim_Init() -{ - static _cuda_device_id *the_device = NULL; - if( !the_device ) { - gpgpu_sim *the_gpu = gpgpu_ptx_sim_init_perf(); - - cudaDeviceProp *prop = (cudaDeviceProp *) calloc(sizeof(cudaDeviceProp),1); - snprintf(prop->name,256,"GPGPU-Sim_v%s", g_gpgpusim_version_string ); - prop->major = 5; - prop->minor = 2; - prop->totalGlobalMem = 0x80000000 /* 2 GB */; - prop->memPitch = 0; - prop->maxThreadsPerBlock = 512; - prop->maxThreadsDim[0] = 512; - prop->maxThreadsDim[1] = 512; - prop->maxThreadsDim[2] = 512; - prop->maxGridSize[0] = 0x40000000; - prop->maxGridSize[1] = 0x40000000; - prop->maxGridSize[2] = 0x40000000; - prop->totalConstMem = 0x40000000; - prop->textureAlignment = 0; - prop->sharedMemPerBlock = the_gpu->shared_mem_size(); - prop->regsPerBlock = the_gpu->num_registers_per_core(); - prop->warpSize = the_gpu->wrp_size(); - prop->clockRate = the_gpu->shader_clock(); -#if (CUDART_VERSION >= 2010) - prop->multiProcessorCount = the_gpu->get_config().num_shader(); -#endif - the_gpu->set_prop(prop); - the_device = new _cuda_device_id(the_gpu); - } - start_sim_thread(1); - return the_device; -} - -static CUctx_st* GPGPUSim_Context() -{ - static CUctx_st *the_context = NULL; - if( the_context == NULL ) { - _cuda_device_id *the_gpu = GPGPUSim_Init(); - the_context = new CUctx_st(the_gpu); - } - return the_context; -} - - void ptxinfo_addinfo() -{ - if(!get_ptxinfo_kname()){ - /* This info is not per kernel (since CUDA 5.0 some info (e.g. gmem, and cmem) is added at the beginning for the whole binary ) */ - CUctx_st *context = GPGPUSim_Context(); - print_ptxinfo(); - context->add_ptxinfo(get_ptxinfo()); - clear_ptxinfo(); - return; - } - if( !strcmp("__cuda_dummy_entry__",get_ptxinfo_kname()) ) { - // this string produced by ptxas for empty ptx files (e.g., bandwidth test) - clear_ptxinfo(); - return; - } - CUctx_st *context = GPGPUSim_Context(); - print_ptxinfo(); - context->add_ptxinfo( get_ptxinfo_kname(), get_ptxinfo() ); - clear_ptxinfo(); -} - -void cuda_not_implemented( const char* func, unsigned line ) -{ - fflush(stdout); - fflush(stderr); - printf("\n\nGPGPU-Sim PTX: Execution error: CUDA API function \"%s()\" has not been implemented yet.\n" - " [$GPGPUSIM_ROOT/libcuda/%s around line %u]\n\n\n", - func,__FILE__, line ); - fflush(stdout); - abort(); -} - - -#define gpgpusim_ptx_error(msg, ...) gpgpusim_ptx_error_impl(__func__, __FILE__,__LINE__, msg, ##__VA_ARGS__) -#define gpgpusim_ptx_assert(cond,msg, ...) gpgpusim_ptx_assert_impl((cond),__func__, __FILE__,__LINE__, msg, ##__VA_ARGS__) - -void gpgpusim_ptx_error_impl( const char *func, const char *file, unsigned line, const char *msg, ... ) -{ - va_list ap; - char buf[1024]; - va_start(ap,msg); - vsnprintf(buf,1024,msg,ap); - va_end(ap); - - printf("GPGPU-Sim CUDA API: %s\n", buf); - printf(" [%s:%u : %s]\n", file, line, func ); - abort(); -} - -void gpgpusim_ptx_assert_impl( int test_value, const char *func, const char *file, unsigned line, const char *msg, ... ) -{ - va_list ap; - char buf[1024]; - va_start(ap,msg); - vsnprintf(buf,1024,msg,ap); - va_end(ap); - - if ( test_value == 0 ) - gpgpusim_ptx_error_impl(func, file, line, msg); -} - - -typedef std::map event_tracker_t; - -int CUevent_st::m_next_event_uid; -event_tracker_t g_timer_events; -int g_active_device = 0; //active gpu that runs the code -std::list g_cuda_launch_stack; - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -extern "C" { - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ -cudaError_t cudaPeekAtLastError(void) -{ - return g_last_cudaError; -} - -__host__ cudaError_t CUDARTAPI cudaMalloc(void **devPtr, size_t size) -{ - CUctx_st* context = GPGPUSim_Context(); - *devPtr = context->get_device()->get_gpgpu()->gpu_malloc(size); - if(g_debug_execution >= 3) - printf("GPGPU-Sim PTX: cudaMallocing %zu bytes starting at 0x%llx..\n",size, (unsigned long long) *devPtr); - if ( *devPtr ) { - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorMemoryAllocation; - } -} - -__host__ cudaError_t CUDARTAPI cudaMallocHost(void **ptr, size_t size) -{ - GPGPUSim_Context(); - *ptr = malloc(size); - if ( *ptr ) { - //track pinned memory size allocated in the host so that same amount of memory is also allocated in GPU. - pinned_memory_size[*ptr]=size; - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorMemoryAllocation; - } -} -__host__ cudaError_t CUDARTAPI cudaMallocPitch(void **devPtr, size_t *pitch, size_t width, size_t height) -{ - unsigned malloc_width_inbytes = width; - printf("GPGPU-Sim PTX: cudaMallocPitch (width = %d)\n", malloc_width_inbytes); - CUctx_st* ctx = GPGPUSim_Context(); - *devPtr = ctx->get_device()->get_gpgpu()->gpu_malloc(malloc_width_inbytes*height); - pitch[0] = malloc_width_inbytes; - if ( *devPtr ) { - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorMemoryAllocation; - } -} - -__host__ cudaError_t CUDARTAPI cudaMallocArray(struct cudaArray **array, const struct cudaChannelFormatDesc *desc, size_t width, size_t height __dv(1)) -{ - unsigned size = width * height * ((desc->x + desc->y + desc->z + desc->w)/8); - CUctx_st* context = GPGPUSim_Context(); - (*array) = (struct cudaArray*) malloc(sizeof(struct cudaArray)); - (*array)->desc = *desc; - (*array)->width = width; - (*array)->height = height; - (*array)->size = size; - (*array)->dimensions = 2; - ((*array)->devPtr32)= (int) (long long)context->get_device()->get_gpgpu()->gpu_mallocarray(size); - printf("GPGPU-Sim PTX: cudaMallocArray: devPtr32 = %d\n", ((*array)->devPtr32)); - ((*array)->devPtr) = (void*) (long long) ((*array)->devPtr32); - if ( ((*array)->devPtr) ) { - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorMemoryAllocation; - } -} - -__host__ cudaError_t CUDARTAPI cudaFree(void *devPtr) -{ - // TODO... manage g_global_mem space? - return g_last_cudaError = cudaSuccess; -} -__host__ cudaError_t CUDARTAPI cudaFreeHost(void *ptr) -{ - free (ptr); // this will crash the system if called twice - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaFreeArray(struct cudaArray *array) -{ - // TODO... manage g_global_mem space? - return g_last_cudaError = cudaSuccess; -}; - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaMemcpy(void *dst, const void *src, size_t count, enum cudaMemcpyKind kind) -{ - //CUctx_st *context = GPGPUSim_Context(); - //gpgpu_t *gpu = context->get_device()->get_gpgpu(); - if(g_debug_execution >= 3) - printf("GPGPU-Sim PTX: cudaMemcpy(): devPtr = %p\n", dst); - if( kind == cudaMemcpyHostToDevice ) - g_stream_manager->push( stream_operation(src,(size_t)dst,count,0) ); - else if( kind == cudaMemcpyDeviceToHost ) - g_stream_manager->push( stream_operation((size_t)src,dst,count,0) ); - else if( kind == cudaMemcpyDeviceToDevice ) - g_stream_manager->push( stream_operation((size_t)src,(size_t)dst,count,0) ); - else if ( kind == cudaMemcpyDefault ) { - if ((size_t)src >= GLOBAL_HEAP_START) { - if ((size_t)dst >= GLOBAL_HEAP_START) - g_stream_manager->push( stream_operation((size_t)src,(size_t)dst,count,0) ); // device to device - else - g_stream_manager->push( stream_operation((size_t)src,dst,count,0) ); // device to host - } - else { - if ((size_t)dst >= GLOBAL_HEAP_START) - g_stream_manager->push( stream_operation(src,(size_t)dst,count,0) ); - else { - printf("GPGPU-Sim PTX: cudaMemcpy - ERROR : unsupported transfer: host to host\n"); - abort(); - } - } - } - else { - printf("GPGPU-Sim PTX: cudaMemcpy - ERROR : unsupported cudaMemcpyKind\n"); - abort(); - } - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaMemcpyToArray(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t count, enum cudaMemcpyKind kind) -{ - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - size_t size = count; - printf("GPGPU-Sim PTX: cudaMemcpyToArray\n"); - if( kind == cudaMemcpyHostToDevice ) - gpu->memcpy_to_gpu( (size_t)(dst->devPtr), src, size); - else if( kind == cudaMemcpyDeviceToHost ) - gpu->memcpy_from_gpu( dst->devPtr, (size_t)src, size); - else if( kind == cudaMemcpyDeviceToDevice ) - gpu->memcpy_gpu_to_gpu( (size_t)(dst->devPtr), (size_t)src, size); - else { - printf("GPGPU-Sim PTX: cudaMemcpyToArray - ERROR : unsupported cudaMemcpyKind\n"); - abort(); - } - dst->devPtr32 = (unsigned) (size_t)(dst->devPtr); - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpyFromArray(void *dst, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t count, enum cudaMemcpyKind kind) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpyArrayToArray(struct cudaArray *dst, size_t wOffsetDst, size_t hOffsetDst, const struct cudaArray *src, size_t wOffsetSrc, size_t hOffsetSrc, size_t count, enum cudaMemcpyKind kind __dv(cudaMemcpyDeviceToDevice)) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpy2D(void *dst, size_t dpitch, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind) -{ - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - size_t size = spitch*height; - gpgpusim_ptx_assert( (dpitch==spitch), "different src and dst pitch not supported yet" ); - if( kind == cudaMemcpyHostToDevice ) - gpu->memcpy_to_gpu( (size_t)dst, src, size ); - else if( kind == cudaMemcpyDeviceToHost ) - gpu->memcpy_from_gpu( dst, (size_t)src, size ); - else if( kind == cudaMemcpyDeviceToDevice ) - gpu->memcpy_gpu_to_gpu( (size_t)dst, (size_t)src, size); - else { - printf("GPGPU-Sim PTX: cudaMemcpy2D - ERROR : unsupported cudaMemcpyKind\n"); - abort(); - } - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpy2DToArray(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind) -{ - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - size_t size = spitch*height; - size_t channel_size = dst->desc.w+dst->desc.x+dst->desc.y+dst->desc.z; - gpgpusim_ptx_assert( ((channel_size%8) == 0), "none byte multiple destination channel size not supported (sz=%u)", channel_size ); - unsigned elem_size = channel_size/8; - gpgpusim_ptx_assert( (dst->dimensions==2), "copy to none 2D array not supported" ); - gpgpusim_ptx_assert( (wOffset==0), "non-zero wOffset not yet supported" ); - gpgpusim_ptx_assert( (hOffset==0), "non-zero hOffset not yet supported" ); - gpgpusim_ptx_assert( (dst->height == (int)height), "partial copy not supported" ); - gpgpusim_ptx_assert( (elem_size*dst->width == width), "partial copy not supported" ); - gpgpusim_ptx_assert( (spitch == width), "spitch != width not supported" ); - if( kind == cudaMemcpyHostToDevice ) - gpu->memcpy_to_gpu( (size_t)(dst->devPtr), src, size); - else if( kind == cudaMemcpyDeviceToHost ) - gpu->memcpy_from_gpu( dst->devPtr, (size_t)src, size); - else if( kind == cudaMemcpyDeviceToDevice ) - gpu->memcpy_gpu_to_gpu( (size_t)dst->devPtr, (size_t)src, size); - else { - printf("GPGPU-Sim PTX: cudaMemcpy2D - ERROR : unsupported cudaMemcpyKind\n"); - abort(); - } - dst->devPtr32 = (unsigned) (size_t)(dst->devPtr); - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpy2DFromArray(void *dst, size_t dpitch, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t width, size_t height, enum cudaMemcpyKind kind) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpy2DArrayToArray(struct cudaArray *dst, size_t wOffsetDst, size_t hOffsetDst, const struct cudaArray *src, size_t wOffsetSrc, size_t hOffsetSrc, size_t width, size_t height, enum cudaMemcpyKind kind __dv(cudaMemcpyDeviceToDevice)) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpyToSymbol(const char *symbol, const void *src, size_t count, size_t offset __dv(0), enum cudaMemcpyKind kind __dv(cudaMemcpyHostToDevice)) -{ - //CUctx_st *context = GPGPUSim_Context(); - assert(kind == cudaMemcpyHostToDevice); - printf("GPGPU-Sim PTX: cudaMemcpyToSymbol: symbol = %p\n", symbol); - //stream_operation( const char *symbol, const void *src, size_t count, size_t offset ) - g_stream_manager->push( stream_operation(src,symbol,count,offset,0) ); - //gpgpu_ptx_sim_memcpy_symbol(symbol,src,count,offset,1,context->get_device()->get_gpgpu()); - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpyFromSymbol(void *dst, const char *symbol, size_t count, size_t offset __dv(0), enum cudaMemcpyKind kind __dv(cudaMemcpyDeviceToHost)) -{ - //CUctx_st *context = GPGPUSim_Context(); - assert(kind == cudaMemcpyDeviceToHost); - printf("GPGPU-Sim PTX: cudaMemcpyFromSymbol: symbol = %p\n", symbol); - g_stream_manager->push( stream_operation(symbol,dst,count,offset,0) ); - //gpgpu_ptx_sim_memcpy_symbol(symbol,dst,count,offset,0,context->get_device()->get_gpgpu()); - return g_last_cudaError = cudaSuccess; -} - - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaMemcpyAsync(void *dst, const void *src, size_t count, enum cudaMemcpyKind kind, cudaStream_t stream) -{ - struct CUstream_st *s = (struct CUstream_st *)stream; - switch( kind ) { - case cudaMemcpyHostToDevice: g_stream_manager->push( stream_operation(src,(size_t)dst,count,s) ); break; - case cudaMemcpyDeviceToHost: g_stream_manager->push( stream_operation((size_t)src,dst,count,s) ); break; - case cudaMemcpyDeviceToDevice: g_stream_manager->push( stream_operation((size_t)src,(size_t)dst,count,s) ); break; - default: - abort(); - } - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpyToArrayAsync(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t count, enum cudaMemcpyKind kind, cudaStream_t stream) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpyFromArrayAsync(void *dst, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t count, enum cudaMemcpyKind kind, cudaStream_t stream) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpy2DAsync(void *dst, size_t dpitch, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind, cudaStream_t stream) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpy2DToArrayAsync(struct cudaArray *dst, size_t wOffset, size_t hOffset, const void *src, size_t spitch, size_t width, size_t height, enum cudaMemcpyKind kind, cudaStream_t stream) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaMemcpy2DFromArrayAsync(void *dst, size_t dpitch, const struct cudaArray *src, size_t wOffset, size_t hOffset, size_t width, size_t height, enum cudaMemcpyKind kind, cudaStream_t stream) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaMemset(void *mem, int c, size_t count) -{ - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - gpu->gpu_memset((size_t)mem, c, count); - return g_last_cudaError = cudaSuccess; -} - -//memset operation is done but i think its not async? -__host__ cudaError_t CUDARTAPI cudaMemsetAsync(void *mem, int c, size_t count, cudaStream_t stream=0) -{ - printf("GPGPU-Sim PTX: WARNING: Asynchronous memset not supported (%s)\n", __my_func__); - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - gpu->gpu_memset((size_t)mem, c, count); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaMemset2D(void *mem, size_t pitch, int c, size_t width, size_t height) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaGetSymbolAddress(void **devPtr, const char *symbol) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - -__host__ cudaError_t CUDARTAPI cudaGetSymbolSize(size_t *size, const char *symbol) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ -__host__ cudaError_t CUDARTAPI cudaGetDeviceCount(int *count) -{ - _cuda_device_id *dev = GPGPUSim_Init(); - *count = dev->num_devices(); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaGetDeviceProperties(struct cudaDeviceProp *prop, int device) -{ - _cuda_device_id *dev = GPGPUSim_Init(); - if (device <= dev->num_devices() ) { - *prop= *dev->get_prop(); - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorInvalidDevice; - } -} - -#if (CUDART_VERSION > 5000) -__host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDeviceAttr attr, int device) -{ - const struct cudaDeviceProp *prop; - _cuda_device_id *dev = GPGPUSim_Init(); - if (device <= dev->num_devices() ) { - prop = dev->get_prop(); - switch (attr) { - case 5: - *value= prop->maxGridSize[0]; - break; - case 6: - *value= prop->maxGridSize[1]; - break; - case 7: - *value= prop->maxGridSize[2]; - break; - case 10: - *value= prop->warpSize; - break; - case 12: - *value= prop->regsPerBlock; - break; - case 14: - *value= prop->textureAlignment ; - break; - case 16: - *value= prop->multiProcessorCount ; - break; - case 39: - *value= dev->get_gpgpu()->threads_per_core(); - break; - case 75: - *value= 8 ; - break; - case 76: - *value= 3 ; - break; - case 78: - *value= 0 ; //TODO: as of now, we dont support stream priorities. - break; - default: - printf("ERROR: implement the attribute numbered %d \n",attr); - abort(); - } - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorInvalidDevice; - } -} -#endif - -__host__ cudaError_t CUDARTAPI cudaChooseDevice(int *device, const struct cudaDeviceProp *prop) -{ - _cuda_device_id *dev = GPGPUSim_Init(); - *device = dev->get_id(); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaSetDevice(int device) -{ - //set the active device to run cuda - if ( device <= GPGPUSim_Init()->num_devices() ) { - g_active_device = device; - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorInvalidDevice; - } -} - -__host__ cudaError_t CUDARTAPI cudaGetDevice(int *device) -{ - *device = g_active_device; - return g_last_cudaError = cudaSuccess; -} - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaBindTexture(size_t *offset, - const struct textureReference *texref, - const void *devPtr, - const struct cudaChannelFormatDesc *desc, - size_t size __dv(UINT_MAX)) -{ - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - printf("GPGPU-Sim PTX: in cudaBindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); - struct cudaArray *array; - array = (struct cudaArray*) malloc(sizeof(struct cudaArray)); - array->desc = *desc; - array->size = size; - array->width = size; - array->height = 1; - array->dimensions = 1; - array->devPtr = (void*)devPtr; - array->devPtr32 = (int)(long long)devPtr; - offset = 0; - printf("GPGPU-Sim PTX: size = %zu\n", size); - printf("GPGPU-Sim PTX: texref = %p, array = %p\n", texref, array); - printf("GPGPU-Sim PTX: devPtr32 = %x\n", array->devPtr32); - printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); - printf("GPGPU-Sim PTX: ChannelFormatDesc: x=%d, y=%d, z=%d, w=%d\n", desc->x, desc->y, desc->z, desc->w); - printf("GPGPU-Sim PTX: Texture Normalized? = %d\n", texref->normalized); - gpu->gpgpu_ptx_sim_bindTextureToArray(texref, array); - devPtr = (void*)(long long)array->devPtr32; - printf("GPGPU-Sim PTX: devPtr = %p\n", devPtr); - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureReference *texref, const struct cudaArray *array, const struct cudaChannelFormatDesc *desc) -{ - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - printf("GPGPU-Sim PTX: in cudaBindTextureToArray: %p %p\n", texref, array); - printf("GPGPU-Sim PTX: devPtr32 = %x\n", array->devPtr32); - printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); - printf("GPGPU-Sim PTX: Texture Normalized? = %d\n", texref->normalized); - gpu->gpgpu_ptx_sim_bindTextureToArray(texref, array); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) -{ - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaGetTextureAlignmentOffset(size_t *offset, const struct textureReference *texref) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - -__host__ cudaError_t CUDARTAPI cudaGetTextureReference(const struct textureReference **texref, const char *symbol) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - -__host__ cudaError_t CUDARTAPI cudaGetChannelDesc(struct cudaChannelFormatDesc *desc, const struct cudaArray *array) -{ - *desc = array->desc; - return g_last_cudaError = cudaSuccess; -} - - -__host__ struct cudaChannelFormatDesc CUDARTAPI cudaCreateChannelDesc(int x, int y, int z, int w, enum cudaChannelFormatKind f) -{ - struct cudaChannelFormatDesc dummy; - dummy.x = x; - dummy.y = y; - dummy.z = z; - dummy.w = w; - dummy.f = f; - return dummy; -} - -__host__ cudaError_t CUDARTAPI cudaGetLastError(void) -{ - return g_last_cudaError; -} - -__host__ const char* CUDARTAPI cudaGetErrorString(cudaError_t error) -{ - if( g_last_cudaError == cudaSuccess ) - return "no error"; - char buf[1024]; - snprintf(buf,1024,"<>", g_last_cudaError); - return strdup(buf); -} - -__host__ cudaError_t CUDARTAPI cudaConfigureCall(dim3 gridDim, dim3 blockDim, size_t sharedMem, cudaStream_t stream) -{ - struct CUstream_st *s = (struct CUstream_st *)stream; - g_cuda_launch_stack.push_back( kernel_config(gridDim,blockDim,sharedMem,s) ); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaSetupArgument(const void *arg, size_t size, size_t offset) -{ - gpgpusim_ptx_assert( !g_cuda_launch_stack.empty(), "empty launch stack" ); - kernel_config &config = g_cuda_launch_stack.back(); - config.set_arg(arg,size,offset); - - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaLaunch( const char *hostFun ) -{ - CUctx_st* context = GPGPUSim_Context(); - char *mode = getenv("PTX_SIM_MODE_FUNC"); - if( mode ) - sscanf(mode,"%u", &g_ptx_sim_mode); - gpgpusim_ptx_assert( !g_cuda_launch_stack.empty(), "empty launch stack" ); - kernel_config config = g_cuda_launch_stack.back(); - struct CUstream_st *stream = config.get_stream(); - printf("\nGPGPU-Sim PTX: cudaLaunch for 0x%p (mode=%s) on stream %u\n", hostFun, - g_ptx_sim_mode?"functional simulation":"performance simulation", stream?stream->get_uid():0 ); - kernel_info_t *grid = gpgpu_cuda_ptx_sim_init_grid(hostFun,config.get_args(),config.grid_dim(),config.block_dim(),context); - //do dynamic PDOM analysis for performance simulation scenario - std::string kname = grid->name(); - function_info *kernel_func_info = grid->entry(); - if (kernel_func_info->is_pdom_set()) { - printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", kname.c_str() ); - } else { - printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", kname.c_str() ); - kernel_func_info->do_pdom(); - kernel_func_info->set_pdom(); - } - dim3 gridDim = config.grid_dim(); - dim3 blockDim = config.block_dim(); - printf("GPGPU-Sim PTX: pushing kernel \'%s\' to stream %u, gridDim= (%u,%u,%u) blockDim = (%u,%u,%u) \n", - kname.c_str(), stream?stream->get_uid():0, gridDim.x,gridDim.y,gridDim.z,blockDim.x,blockDim.y,blockDim.z ); - stream_operation op(grid,g_ptx_sim_mode,stream); - g_stream_manager->push(op); - g_cuda_launch_stack.pop_back(); - return g_last_cudaError = cudaSuccess; -} - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaStreamCreate(cudaStream_t *stream) -{ - printf("GPGPU-Sim PTX: cudaStreamCreate\n"); -#if (CUDART_VERSION >= 3000) - *stream = new struct CUstream_st(); - g_stream_manager->add_stream(*stream); -#else - *stream = 0; - printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); -#endif - return g_last_cudaError = cudaSuccess; -} - -//TODO: introduce priorities -__host__ cudaError_t CUDARTAPI cudaStreamCreateWithPriority(cudaStream_t *stream, unsigned int flags, int priority) { - return cudaStreamCreate(stream); -} - -__host__ cudaError_t CUDARTAPI cudaDeviceGetStreamPriorityRange(int* leastPriority, int* greatestPriority) { - return cudaSuccess; -} - -__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *pStream, unsigned int flags) { - return cudaStreamCreate(pStream); -} - -__host__ cudaError_t CUDARTAPI cudaStreamDestroy(cudaStream_t stream) -{ -#if (CUDART_VERSION >= 3000) - g_stream_manager->destroy_stream(stream); -#endif - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaStreamSynchronize(cudaStream_t stream) -{ -#if (CUDART_VERSION >= 3000) - if( stream == NULL ) - synchronize(); - return g_last_cudaError = cudaSuccess; - stream->synchronize(); -#else - printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); -#endif - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) -{ -#if (CUDART_VERSION >= 3000) - if( stream == NULL ) - return g_last_cudaError = cudaErrorInvalidResourceHandle; - return g_last_cudaError = stream->empty()?cudaSuccess:cudaErrorNotReady; -#else - printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); - return g_last_cudaError = cudaSuccess; // it is always success because all cuda calls are synchronous -#endif -} - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaEventCreate(cudaEvent_t *event) -{ - CUevent_st *e = new CUevent_st(false); - g_timer_events[e->get_uid()] = e; -#if CUDART_VERSION >= 3000 - *event = e; -#else - *event = e->get_uid(); -#endif - return g_last_cudaError = cudaSuccess; -} - -CUevent_st *get_event(cudaEvent_t event) -{ - unsigned event_uid; -#if CUDART_VERSION >= 3000 - event_uid = event->get_uid(); -#else - event_uid = event; -#endif - event_tracker_t::iterator e = g_timer_events.find(event_uid); - if( e == g_timer_events.end() ) - return NULL; - return e->second; -} - -__host__ cudaError_t CUDARTAPI cudaEventRecord(cudaEvent_t event, cudaStream_t stream) -{ - CUevent_st *e = get_event(event); - if( !e ) return g_last_cudaError = cudaErrorUnknown; - struct CUstream_st *s = (struct CUstream_st *)stream; - stream_operation op(e,s); - g_stream_manager->push(op); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaEventQuery(cudaEvent_t event) -{ - CUevent_st *e = get_event(event); - if( e == NULL ) { - return g_last_cudaError = cudaErrorInvalidValue; - } else if( e->done() ) { - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorNotReady; - } -} - -__host__ cudaError_t CUDARTAPI cudaEventSynchronize(cudaEvent_t event) -{ - printf("GPGPU-Sim API: cudaEventSynchronize ** waiting for event\n"); - fflush(stdout); - CUevent_st *e = (CUevent_st*) event; - while( !e->done() ) - ; - printf("GPGPU-Sim API: cudaEventSynchronize ** event detected\n"); - fflush(stdout); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaEventDestroy(cudaEvent_t event) -{ - CUevent_st *e = get_event(event); - unsigned event_uid = e->get_uid(); - event_tracker_t::iterator pe = g_timer_events.find(event_uid); - if( pe == g_timer_events.end() ) - return g_last_cudaError = cudaErrorInvalidValue; - g_timer_events.erase(pe); - return g_last_cudaError = cudaSuccess; -} - - -__host__ cudaError_t CUDARTAPI cudaEventElapsedTime(float *ms, cudaEvent_t start, cudaEvent_t end) -{ - time_t elapsed_time; - CUevent_st *s = get_event(start); - CUevent_st *e = get_event(end); - if( s==NULL || e==NULL ) - return g_last_cudaError = cudaErrorUnknown; - elapsed_time = e->clock() - s->clock(); - *ms = 1000*elapsed_time; - return g_last_cudaError = cudaSuccess; -} - - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -__host__ cudaError_t CUDARTAPI cudaThreadExit(void) -{ - exit_simulation(); - return g_last_cudaError = cudaSuccess; -} - -__host__ cudaError_t CUDARTAPI cudaThreadSynchronize(void) -{ - //Called on host side - synchronize(); - return g_last_cudaError = cudaSuccess; -}; - -int CUDARTAPI __cudaSynchronizeThreads(void**, void*) -{ - return cudaThreadExit(); -} - - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -#if (CUDART_VERSION >= 3010) - -typedef struct CUuuid_st { /**< CUDA definition of UUID */ - char bytes[16]; -} CUuuid; - -/** - * CUDA UUID types - */ -// typedef __device_builtin__ struct CUuuid_st cudaUUID_t; - -__host__ cudaError_t CUDARTAPI cudaGetExportTable(const void **ppExportTable, const cudaUUID_t *pExportTableId) -{ - printf("cudaGetExportTable: UUID = "); - for (int s = 0; s < 16; s++) { - printf("%#2x ", (unsigned char) (pExportTableId->bytes[s])); - } - printf("\n"); - return g_last_cudaError = cudaSuccess; -} - -#endif - - -/******************************************************************************* - * * - * * - * * - *******************************************************************************/ - -//#include "../../cuobjdump_to_ptxplus/cuobjdump_parser.h" - -enum cuobjdumpSectionType { - PTXSECTION=0, - ELFSECTION -}; - - -class cuobjdumpSection { -public: - //Constructor - cuobjdumpSection() { - arch = 0; - identifier = ""; - } - virtual ~cuobjdumpSection() {} - unsigned getArch() {return arch;} - void setArch(unsigned a) {arch = a;} - std::string getIdentifier() {return identifier;} - void setIdentifier(std::string i) {identifier = i;} - virtual void print(){std::cout << "cuobjdump Section: unknown type" << std::endl;} -private: - unsigned arch; - std::string identifier; -}; - -class cuobjdumpELFSection : public cuobjdumpSection -{ -public: - cuobjdumpELFSection() {} - virtual ~cuobjdumpELFSection() { - elffilename = ""; - sassfilename = ""; - } - std::string getELFfilename() {return elffilename;} - void setELFfilename(std::string f) {elffilename = f;} - std::string getSASSfilename() {return sassfilename;} - void setSASSfilename(std::string f) {sassfilename = f;} - virtual void print() { - std::cout << "ELF Section:" << std::endl; - std::cout << "arch: sm_" << getArch() << std::endl; - std::cout << "identifier: " << getIdentifier() << std::endl; - std::cout << "elf filename: " << getELFfilename() << std::endl; - std::cout << "sass filename: " << getSASSfilename() << std::endl; - std::cout << std::endl; - } -private: - std::string elffilename; - std::string sassfilename; -}; - -class cuobjdumpPTXSection : public cuobjdumpSection -{ -public: - cuobjdumpPTXSection(){ - ptxfilename = ""; - } - std::string getPTXfilename() {return ptxfilename;} - void setPTXfilename(std::string f) {ptxfilename = f;} - virtual void print() { - std::cout << "PTX Section:" << std::endl; - std::cout << "arch: sm_" << getArch() << std::endl; - std::cout << "identifier: " << getIdentifier() << std::endl; - std::cout << "ptx filename: " << getPTXfilename() << std::endl; - std::cout << std::endl; - } -private: - std::string ptxfilename; -}; - -std::list cuobjdumpSectionList; -std::list libSectionList; - -// sectiontype: 0 for ptx, 1 for elf -void addCuobjdumpSection(int sectiontype){ - if (sectiontype) - cuobjdumpSectionList.push_front(new cuobjdumpELFSection()); - else - cuobjdumpSectionList.push_front(new cuobjdumpPTXSection()); - printf("## Adding new section %s\n", sectiontype?"ELF":"PTX"); -} - -void setCuobjdumparch(const char* arch){ - unsigned archnum; - sscanf(arch, "sm_%u", &archnum); - assert (archnum && "cannot have sm_0"); - printf("Adding arch: %s\n", arch); - cuobjdumpSectionList.front()->setArch(archnum); -} - -void setCuobjdumpidentifier(const char* identifier){ - printf("Adding identifier: %s\n", identifier); - cuobjdumpSectionList.front()->setIdentifier(identifier); -} - -void setCuobjdumpptxfilename(const char* filename){ - printf("Adding ptx filename: %s\n", filename); - cuobjdumpSection* x = cuobjdumpSectionList.front(); - if (dynamic_cast(x) == NULL){ - assert (0 && "You shouldn't be trying to add a ptxfilename to an elf section"); - } - (dynamic_cast(x))->setPTXfilename(filename); -} - -void setCuobjdumpelffilename(const char* filename){ - if (dynamic_cast(cuobjdumpSectionList.front()) == NULL){ - assert (0 && "You shouldn't be trying to add a elffilename to an ptx section"); - } - (dynamic_cast(cuobjdumpSectionList.front()))->setELFfilename(filename); -} - -void setCuobjdumpsassfilename(const char* filename){ - if (dynamic_cast(cuobjdumpSectionList.front()) == NULL){ - assert (0 && "You shouldn't be trying to add a sassfilename to an ptx section"); - } - (dynamic_cast(cuobjdumpSectionList.front()))->setSASSfilename(filename); -} -extern int cuobjdump_parse(); -extern FILE *cuobjdump_in; - -//! Return the executable file of the process containing the PTX/SASS code -//! -//! This Function returns the executable file ran by the process. This -//! executable is supposed to contain the PTX/SASS code. It provides workaround -//! for processes running on valgrind by dereferencing /proc//exe within the -//! GPGPU-Sim process before calling cuobjdump to extract PTX/SASS. This is -//! needed because valgrind uses x86 emulation to detect memory leak. Other -//! processes (e.g. cuobjdump) reading /proc//exe will see the emulator -//! executable instead of the application binary. -//! -std::string get_app_binary(){ - char self_exe_path[1025]; -#ifdef __APPLE__ - uint32_t size = sizeof(self_exe_path); - if( _NSGetExecutablePath(self_exe_path,&size) != 0 ) { - printf("GPGPU-Sim ** ERROR: _NSGetExecutablePath input buffer too small\n"); - exit(1); - } -#else - std::stringstream exec_link; - exec_link << "/proc/self/exe"; - - ssize_t path_length = readlink(exec_link.str().c_str(), self_exe_path, 1024); - assert(path_length != -1); - self_exe_path[path_length] = '\0'; -#endif - - printf("self exe links to: %s\n", self_exe_path); - return self_exe_path; -} - -//above func gives abs path whereas this give just the name of application. -char* get_app_binary_name(std::string abs_path){ - char *self_exe_path; -#ifdef __APPLE__ - //TODO: get apple device and check the result. - printf("WARNING: not tested for Apple-mac devices \n"); - abort(); -#else - char* buf = strdup(abs_path.c_str()); - char *token = strtok(buf, "/"); - while(token !=NULL){ - self_exe_path = token; - token = strtok(NULL,"/"); - } -#endif - self_exe_path = strtok(self_exe_path, "."); - printf("self exe links to: %s\n", self_exe_path); - return self_exe_path; -} - -//! Call cuobjdump to extract everything (-elf -sass -ptx) -/*! - * This Function extract the whole PTX (for all the files) using cuobjdump - * to _cuobjdump_complete_output_XXXXXX then runs a parser to chop it up with each binary in - * its own file - * It is also responsible for extracting the libraries linked to the binary if the option is - * enabled - * */ -void extract_code_using_cuobjdump(){ - CUctx_st *context = GPGPUSim_Context(); - unsigned forced_max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); - - //prevent the dumping by cuobjdump everytime we execute the code! - const char *override_cuobjdump = getenv("CUOBJDUMP_SIM_FILE"); - char command[1000], ptx_file[1000]; - std::string app_binary = get_app_binary(); - //Running cuobjdump using dynamic link to current process - snprintf(command,1000,"md5sum %s ", app_binary.c_str()); - printf("Running md5sum using \"%s\"\n", command); - system(command); - // Running cuobjdump using dynamic link to current process - // Needs the option '-all' to extract PTX from CDP-enabled binary - extern bool g_cdp_enabled; - - //dump ptx for all individial ptx files into sepearte files which is later used by ptxas. - int result=0; -#if (CUDART_VERSION >= 6000) - char fname2[1024]; - snprintf(fname2,1024,"_cuobjdump_list_ptx_XXXXXX"); - int fd2=mkstemp(fname2); - close(fd2); - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -lptx -arch=sm_%u %s > %s", forced_max_capability, app_binary.c_str(), fname2); - result = system(command); - if( result != 0 ) { - printf("WARNING: Failed to execute cuobjdump to get list of ptx files \n"); - exit(0); - } else { - /* - as we got list of ptx files, we need to extract one by one into seperate files so that ptxas can understand it. - In this way, the duplicate definitions in a single embedded file can be prevented. - No of lines in the file is equal to no of ptx fileis available. - */ - FILE *fp = fopen(fname2,"r"); - if (fp==NULL) { - printf("WARNING: cuobjdump file error! Could not open file %s \n", fname2); - exit(0); - } else { - for (char c = getc(fp); c != EOF; c = getc(fp)) - if (c == '\n') - no_of_ptx = no_of_ptx + 1; - fclose(fp); - } - if(no_of_ptx==0){ - printf("WARNING: Number of ptx in the executable file are 0. One of the reasons might be\n"); - printf("\t1. CDP is enabled\n"); - printf("\t2. cuobjdump -lptx doesnt recognize sm_%u\n",forced_max_capability); - printf("\t3. the application was not compiled iwth nvcc flag sm_%u\n",forced_max_capability); - } - } - if(!g_cdp_enabled) { - //based on the list above, dump ptx files individually. Format of dumped ptx file is prog_name.unique_no.sm_<>.ptx - for (int index=1; index<= no_of_ptx; index++){ - snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", get_app_binary_name(app_binary), index, forced_max_capability); - printf("Extracting specific PTX file named %s \n",ptx_file); - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -arch=sm_%u -xptx %s %s", forced_max_capability, ptx_file, app_binary.c_str()); - if (system(command)!=0) { - printf("ERROR: command: %s failed \n",command); - exit(0); - } - } - } -#endif - //TODO: redundant to dump twice. how can it be prevented? - //dump only for specific arch - char fname[1024]; - if ((override_cuobjdump == NULL) || (strlen(override_cuobjdump)==0)) { - snprintf(fname,1024,"_cuobjdump_complete_output_XXXXXX"); - int fd=mkstemp(fname); - close(fd); - if(!g_cdp_enabled) - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass %s > %s", app_binary.c_str(), fname); - else - snprintf(command,1000,"$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass -all %s > %s", app_binary.c_str(), fname); - bool parse_output = true; - result = system(command); - if(result) { - if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support() && (result == 65280)) { - // Some CUDA application may exclusively use kernels provided by CUDA - // libraries (e.g. CUBLAS). Skipping cuobjdump extraction from the - // executable for this case. - // 65280 is the return code from cuobjdump denoting the specific error (tested on CUDA 4.0/4.1/4.2) - printf("WARNING: Failed to execute: %s\n", command); - printf(" Executable binary does not contain any GPU kernel.\n"); - parse_output = false; - } else { - printf("ERROR: Failed to execute: %s\n", command); - exit(1); - } - } - - if (parse_output) { - printf("Parsing file %s\n", fname); - cuobjdump_in = fopen(fname, "r"); - - cuobjdump_parse(); - fclose(cuobjdump_in); - printf("Done parsing!!!\n"); - } else { - printf("Parsing skipped for %s\n", fname); - } - - if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ - //Experimental library support - //Currently only for cufft - - std::stringstream cmd; - cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; - int result = system(cmd.str().c_str()); - if(result){ - std::cout << "Failed to execute: " << cmd.str() << std::endl; - exit(1); - } - std::ifstream libsf; - libsf.open("_tempfile_.txt"); - if(!libsf.is_open()) { - std::cout << "Failed to open: _tempfile_.txt" << std::endl; - exit(1); - } - - //Save the original section list - std::list tmpsl = cuobjdumpSectionList; - cuobjdumpSectionList.clear(); - - std::string line; - std::getline(libsf, line); - std::cout << "DOING: " << line << std::endl; - int cnt=1; - while(libsf.good()){ - std::stringstream libcodfn; - libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; - cmd.str(""); //resetting - cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; - cmd << line; - cmd << " > "; - cmd << libcodfn.str(); - std::cout << "Running cuobjdump on " << line << std::endl; - std::cout << "Using command: " << cmd.str() << std::endl; - result = system(cmd.str().c_str()); - if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} - std::cout << "Done" << std::endl; - - std::cout << "Trying to parse " << libcodfn.str() << std::endl; - cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); - cuobjdump_parse(); - fclose(cuobjdump_in); - std::getline(libsf, line); - } - libSectionList = cuobjdumpSectionList; - - //Restore the original section list - cuobjdumpSectionList = tmpsl; - } - } else { - printf("GPGPU-Sim PTX: overriding cuobjdump with '%s' (CUOBJDUMP_SIM_FILE is set)\n", override_cuobjdump); - snprintf(fname,1024, "%s",override_cuobjdump); - } -} - -//! Read file into char* -//TODO: convert this to C++ streams, will be way cleaner -char* readfile (const std::string filename){ - assert (filename != ""); - FILE* fp = fopen(filename.c_str(),"r"); - if (!fp) { - std::cout << "ERROR: Could not open file %s for reading\n" << filename << std::endl; - assert (0); - } - // finding size of the file - int filesize= 0; - fseek (fp , 0 , SEEK_END); - - filesize = ftell (fp); - fseek (fp, 0, SEEK_SET); - // allocate and copy the entire ptx - char* ret = (char*)malloc((filesize +1)* sizeof(char)); - fread(ret,1,filesize,fp); - ret[filesize]='\0'; - fclose(fp); - return ret; -} - -//! Function that helps debugging -void printSectionList(std::list sl) { - std::list::iterator iter; - for ( iter = sl.begin(); - iter != sl.end(); - iter++ - ){ - (*iter)->print(); - } -} - -//! Remove unecessary sm versions from the section list -std::list pruneSectionList(std::list cuobjdumpSectionList, CUctx_st *context) { - unsigned forced_max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); - - //For ptxplus, force the max capability to 19 if it's higher or unspecified(0) - if (context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus()){ - if ( (forced_max_capability == 0) || - (forced_max_capability >= 20)){ - printf("GPGPU-Sim: WARNING: Capability >= 20 are not supported in PTXPlus\n\tSetting forced_max_capability to 19\n"); - forced_max_capability = 19; - } - } - - std::list prunedList; - - //Find the highest capability (that is lower than the forced maximum) for each cubin file - //and set it in cuobjdumpSectionMap. Do this only for ptx sections - std::map cuobjdumpSectionMap; - int min_ptx_capability_found=0; - for ( std::list::iterator iter = cuobjdumpSectionList.begin(); - iter != cuobjdumpSectionList.end(); - iter++){ - unsigned capability = (*iter)->getArch(); - if(dynamic_cast(*iter) != NULL){ - if(capabilitygetIdentifier())==cuobjdumpSectionMap.end()) - || (cuobjdumpSectionMap[(*iter)->getIdentifier()] < capability)) - cuobjdumpSectionMap[(*iter)->getIdentifier()] = capability; - } - } - } - - //Throw away the sections with the lower capabilites and push those with the highest in - //the pruned list - for ( std::list::iterator iter = cuobjdumpSectionList.begin(); - iter != cuobjdumpSectionList.end(); - iter++){ - unsigned capability = (*iter)->getArch(); - if(capability == cuobjdumpSectionMap[(*iter)->getIdentifier()]){ - prunedList.push_back(*iter); - } else { - delete *iter; - } - } - if(prunedList.empty()){ - printf("Error: No PTX sections found with sm capability that is lower than current forced maximum capability \n minimum ptx capability found = %u, maximum forced ptx capability = %u \n User might want to change either the forced maximum capability from gpgpusim configuration or update the compilation to generate the required PTX version\n",min_ptx_capability_found,forced_max_capability); - abort(); - } - return prunedList; -} - -//! Merge all PTX sections that have a specific identifier into one file -std::list mergeMatchingSections(std::list cuobjdumpSectionList, std::string identifier){ - const char *ptxcode = ""; - std::list::iterator old_iter; - cuobjdumpPTXSection* old_ptxsection = NULL; - cuobjdumpPTXSection* ptxsection; - std::list mergedList; - - for ( std::list::iterator iter = cuobjdumpSectionList.begin(); - iter != cuobjdumpSectionList.end(); - iter++){ - if((ptxsection=dynamic_cast(*iter)) != NULL && - strcmp(ptxsection->getIdentifier().c_str(), identifier.c_str()) == 0){ - // Read and remove the last PTX section - if (old_ptxsection != NULL) { - ptxcode = readfile(old_ptxsection->getPTXfilename()); - // remove ptx file? - delete *old_iter; - } - - // Append all the PTX from the last PTX section into the current PTX section - // Add 50 to ptxcode to ignore the information regarding version/target/address_size - if (strlen(ptxcode) >= 50) { - FILE *ptxfile = fopen((ptxsection->getPTXfilename()).c_str(), "a"); - fprintf(ptxfile, "%s", ptxcode + 50); - fclose(ptxfile); - } - - old_iter = iter; - old_ptxsection = ptxsection; - } - // Store all non-PTX sections and PTX sections with non-matching identifiers - else { - mergedList.push_back(*iter); - } - } - - // Store the final PTX section - mergedList.push_back(*old_iter); - - return mergedList; -} - -//! Merge any PTX sections with matching identifiers -std::list mergeSections(std::list cuobjdumpSectionList){ - std::vector identifier; - cuobjdumpPTXSection* ptxsection; - - // Add all identifiers present in PTX sections to a vector - for ( std::list::iterator iter = cuobjdumpSectionList.begin(); - iter != cuobjdumpSectionList.end(); - iter++){ - if((ptxsection=dynamic_cast(*iter)) != NULL){ - std::string current_id = ptxsection->getIdentifier(); - - // If we haven't yet seen a given identifier, add it to the vector - if (std::find(identifier.begin(), identifier.end(), current_id) == identifier.end()) { - identifier.push_back(current_id); - } - } - } - - // Call mergeMatchingSections on all identifiers in the vector - for ( std::vector::iterator iter = identifier.begin(); - iter != identifier.end(); - iter++) { - cuobjdumpSectionList = mergeMatchingSections(cuobjdumpSectionList, *iter); - } - - return cuobjdumpSectionList; -} - - -//! Within the section list, find the ELF section corresponding to a given identifier -cuobjdumpELFSection* findELFSectionInList(std::list sectionlist, const std::string identifier){ - - std::list::iterator iter; - for ( iter = sectionlist.begin(); - iter != sectionlist.end(); - iter++ - ){ - cuobjdumpELFSection* elfsection; - if((elfsection=dynamic_cast(*iter)) != NULL){ - if(elfsection->getIdentifier() == identifier) - return elfsection; - } - } - return NULL; -} - -//! Find an ELF section in all the known lists -cuobjdumpELFSection* findELFSection(const std::string identifier){ - cuobjdumpELFSection* sec = findELFSectionInList(cuobjdumpSectionList, identifier); - if (sec!=NULL)return sec; - sec = findELFSectionInList(libSectionList, identifier); - if (sec!=NULL)return sec; - std::cout << "Could not find " << identifier << std::endl; - assert(0 && "Could not find the required ELF section"); - return NULL; -} - -//! Within the section list, find the PTX section corresponding to a given identifier -cuobjdumpPTXSection* findPTXSectionInList(std::list sectionlist, const std::string identifier){ - std::list::iterator iter; - for ( iter = sectionlist.begin(); - iter != sectionlist.end(); - iter++ - ){ - cuobjdumpPTXSection* ptxsection; - if((ptxsection=dynamic_cast(*iter)) != NULL){ - if(ptxsection->getIdentifier() == identifier) - return ptxsection; - else { - extern bool g_cdp_enabled; - if(g_cdp_enabled) { - printf("Warning: __cudaRegisterFatBinary needs %s, but find PTX section with %s\n", - identifier.c_str(), ptxsection->getIdentifier().c_str()); - return ptxsection; - } - } - } - } - return NULL; -} - -//! Find an PTX section in all the known lists -cuobjdumpPTXSection* findPTXSection(const std::string identifier){ - cuobjdumpPTXSection* sec = findPTXSectionInList(cuobjdumpSectionList, identifier); - if (sec!=NULL)return sec; - sec = findPTXSectionInList(libSectionList, identifier); - if (sec!=NULL)return sec; - std::cout << "Could not find " << identifier << std::endl; - assert(0 && "Could not find the required PTX section"); - return NULL; -} - - - -//! Extract the code using cuobjdump and remove unnecessary sections -void cuobjdumpInit(){ - CUctx_st *context = GPGPUSim_Context(); - extract_code_using_cuobjdump(); //extract all the output of cuobjdump to _cuobjdump_*.* - const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); - if (pre_load ==NULL || strlen(pre_load)==0){ - cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); - cuobjdumpSectionList = mergeSections(cuobjdumpSectionList); - } -} - -std::map fatbinmap; -std::mapfatbin_registered; -std::map name_symtab; - -//! Keep track of the association between filename and cubin handle -void cuobjdumpRegisterFatBinary(unsigned int handle, const char* filename){ - fatbinmap[handle] = filename; -} - -//! Either submit PTX for simulation or convert SASS to PTXPlus and submit it -void cuobjdumpParseBinary(unsigned int handle){ - - if(fatbin_registered[handle]) return; - fatbin_registered[handle] = true; - CUctx_st *context = GPGPUSim_Context(); - std::string fname = fatbinmap[handle]; - - if (name_symtab.find(fname) != name_symtab.end()) { - symbol_table *symtab = name_symtab[fname]; - context->add_binary(symtab, handle); - return; - } - - unsigned max_capability = 0; - for ( std::list::iterator iter = cuobjdumpSectionList.begin(); - iter != cuobjdumpSectionList.end(); - iter++){ - unsigned capability = (*iter)->getArch(); - if (capability > max_capability) max_capability = capability; - } - if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); - - cuobjdumpPTXSection* ptx = NULL; - const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); - if(pre_load==NULL || strlen(pre_load)==0) - ptx = findPTXSection(fname); - symbol_table *symtab; - char *ptxcode; - const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); - if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL or strlen(getenv("PTX_SIM_USE_PTX_FILE"))==0) { - ptxcode = readfile(ptx->getPTXfilename()); - } else { - printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); - ptxcode = readfile(override_ptx_name); - } - if(context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() ) { - cuobjdumpELFSection* elfsection = findELFSection(ptx->getIdentifier()); - assert (elfsection!= NULL); - char *ptxplus_str = gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus( - ptx->getPTXfilename(), - elfsection->getELFfilename(), - elfsection->getSASSfilename()); - symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxplus_str, handle); - printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); - context->add_binary(symtab, handle); - gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability ); - delete[] ptxplus_str; - } else { - symtab=gpgpu_ptx_sim_load_ptx_from_string(ptxcode, handle); - //if CUOBJDUMP_SIM_FILE is not set, ptx is NULL. So comment below. - //printf("Adding %s with cubin handle %u\n", ptx->getPTXfilename().c_str(), handle); - context->add_binary(symtab, handle); - gpgpu_ptxinfo_load_from_string( ptxcode, handle, max_capability ); - } - load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu()); - load_constants(symtab,STATIC_ALLOC_LIMIT,context->get_device()->get_gpgpu()); - name_symtab[fname] = symtab; - - //TODO: Remove temporarily files as per configurations -} - -void** CUDARTAPI __cudaRegisterFatBinary( void *fatCubin ) -{ -#if (CUDART_VERSION < 2010) - printf("GPGPU-Sim PTX: ERROR ** this version of GPGPU-Sim requires CUDA 2.1 or higher\n"); - exit(1); -#endif - CUctx_st *context = GPGPUSim_Context(); - static unsigned next_fat_bin_handle = 1; - if(context->get_device()->get_gpgpu()->get_config().use_cuobjdump()) { - // The following workaround has only been verified on 64-bit systems. - if (sizeof(void*) == 4) - printf("GPGPU-Sim PTX: FatBin file name extraction has not been tested on 32-bit system.\n"); - - #if (CUDART_VERSION <= 6000) - // FatBin handle from the .fatbin.c file (one of the intermediate files generated by NVCC) - typedef struct {int m; int v; const unsigned long long* d; char* f;} __fatDeviceText __attribute__ ((aligned (8))); - __fatDeviceText * fatDeviceText = (__fatDeviceText *) fatCubin; - - // Extract the source code file name that generate the given FatBin. - // - Obtains the pointer to the actual fatbin structure from the FatBin handle (fatCubin). - // - An integer inside the fatbin structure contains the relative offset to the source code file name. - // - This offset differs among different CUDA and GCC versions. - char * pfatbin = (char*) fatDeviceText->d; - int offset = *((int*)(pfatbin+48)); - char * filename = (pfatbin+16+offset); - #else - const char * filename = "default"; - #endif - // The extracted file name is associated with a fat_cubin_handle passed - // into cudaLaunch(). Inside cudaLaunch(), the associated file name is - // used to find the PTX/SASS section from cuobjdump, which contains the - // PTX/SASS code for the launched kernel function. - // This allows us to work around the fact that cuobjdump only outputs the - // file name associated with each section. - unsigned long long fat_cubin_handle = next_fat_bin_handle; - next_fat_bin_handle++; - printf("GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = %llu, filename=%s\n", fat_cubin_handle, filename); - /*! - * This function extracts all data from all files in first call - * then for next calls, only returns the appropriate number - */ - assert(fat_cubin_handle >= 1); - if (fat_cubin_handle==1) cuobjdumpInit(); - cuobjdumpRegisterFatBinary(fat_cubin_handle, filename); - - return (void**)fat_cubin_handle; - } -#if (CUDART_VERSION < 8000) - else { - static unsigned source_num=1; - unsigned long long fat_cubin_handle = next_fat_bin_handle++; - __cudaFatCudaBinary *info = (__cudaFatCudaBinary *)fatCubin; - assert( info->version >= 3 ); - unsigned num_ptx_versions=0; - unsigned max_capability=0; - unsigned selected_capability=0; - bool found=false; - unsigned forced_max_capability = context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); - if (!info->ptx){ - printf("ERROR: Cannot find ptx code in cubin file\n" - "\tIf you are using CUDA 4.0 or higher, please enable -gpgpu_ptx_use_cuobjdump or downgrade to CUDA 3.1\n"); - exit(1); - } - while( info->ptx[num_ptx_versions].gpuProfileName != NULL ) { - unsigned capability=0; - sscanf(info->ptx[num_ptx_versions].gpuProfileName,"compute_%u",&capability); - printf("GPGPU-Sim PTX: __cudaRegisterFatBinary found PTX versions for '%s', ", info->ident); - printf("capability = %s\n", info->ptx[num_ptx_versions].gpuProfileName ); - if( forced_max_capability ) { - if( capability > max_capability && capability <= forced_max_capability ) { - found = true; - max_capability=capability; - selected_capability = num_ptx_versions; - } - } else { - if( capability > max_capability ) { - found = true; - max_capability=capability; - selected_capability = num_ptx_versions; - } - } - num_ptx_versions++; - } - if( found ) { - printf("GPGPU-Sim PTX: Loading PTX for %s, capability = %s\n", - info->ident, info->ptx[selected_capability].gpuProfileName ); - symbol_table *symtab; - const char *ptx = info->ptx[selected_capability].ptx; - if(context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() ) { - printf("GPGPU-Sim PTX: ERROR ** PTXPlus is only supported through cuobjdump\n" - "\tEither enable cuobjdump or disable PTXPlus in your configuration file\n"); - exit(1); - } else { - symtab=gpgpu_ptx_sim_load_ptx_from_string(ptx,source_num); - context->add_binary(symtab,fat_cubin_handle); - gpgpu_ptxinfo_load_from_string( ptx, source_num, max_capability ); - } - source_num++; - load_static_globals(symtab,STATIC_ALLOC_LIMIT,0xFFFFFFFF,context->get_device()->get_gpgpu()); - load_constants(symtab,STATIC_ALLOC_LIMIT,context->get_device()->get_gpgpu()); - } else { - printf("GPGPU-Sim PTX: warning -- did not find an appropriate PTX in cubin\n"); - } - return (void**)fat_cubin_handle; - } -#else - else { - printf("ERROR ** __cudaRegisterFatBinary() needs to be updated\n"); - abort(); - } -#endif -} - -void __cudaUnregisterFatBinary(void **fatCubinHandle) -{ - ; -} - -cudaError_t cudaDeviceReset ( void ) { - // Should reset the simulated GPU - return g_last_cudaError = cudaSuccess; -} -cudaError_t CUDARTAPI cudaDeviceSynchronize(void){ - // I don't know what this should do - return g_last_cudaError = cudaSuccess; -} - - -void CUDARTAPI __cudaRegisterFunction( - void **fatCubinHandle, - const char *hostFun, - char *deviceFun, - const char *deviceName, - int thread_limit, - uint3 *tid, - uint3 *bid, - dim3 *bDim, - dim3 *gDim -) -{ - CUctx_st *context = GPGPUSim_Context(); - unsigned fat_cubin_handle = (unsigned)(unsigned long long)fatCubinHandle; - printf("GPGPU-Sim PTX: __cudaRegisterFunction %s : hostFun 0x%p, fat_cubin_handle = %u\n", - deviceFun, hostFun, fat_cubin_handle); - if(context->get_device()->get_gpgpu()->get_config().use_cuobjdump()) - cuobjdumpParseBinary(fat_cubin_handle); - context->register_function( fat_cubin_handle, hostFun, deviceFun ); -} - -extern void __cudaRegisterVar( - void **fatCubinHandle, - char *hostVar, //pointer to...something - char *deviceAddress, //name of variable - const char *deviceName, //name of variable (same as above) - int ext, - int size, - int constant, - int global ) -{ - printf("GPGPU-Sim PTX: __cudaRegisterVar: hostVar = %p; deviceAddress = %s; deviceName = %s\n", hostVar, deviceAddress, deviceName); - printf("GPGPU-Sim PTX: __cudaRegisterVar: Registering const memory space of %d bytes\n", size); - if(GPGPUSim_Context()->get_device()->get_gpgpu()->get_config().use_cuobjdump()) - cuobjdumpParseBinary((unsigned)(unsigned long long)fatCubinHandle); - fflush(stdout); - if ( constant && !global && !ext ) { - gpgpu_ptx_sim_register_const_variable(hostVar,deviceName,size); - } else if ( !constant && !global && !ext ) { - gpgpu_ptx_sim_register_global_variable(hostVar,deviceName,size); - } else cuda_not_implemented(__my_func__,__LINE__); -} - - -void __cudaRegisterShared( - void **fatCubinHandle, - void **devicePtr -) -{ - // we don't do anything here - printf("GPGPU-Sim PTX: __cudaRegisterShared\n" ); -} - -void CUDARTAPI __cudaRegisterSharedVar( - void **fatCubinHandle, - void **devicePtr, - size_t size, - size_t alignment, - int storage -) -{ - // we don't do anything here - printf("GPGPU-Sim PTX: __cudaRegisterSharedVar\n" ); -} - -void __cudaRegisterTexture( - void **fatCubinHandle, - const struct textureReference *hostVar, - const void **deviceAddress, - const char *deviceName, - int dim, - int norm, - int ext -) //passes in a newly created textureReference -{ - std::string devStr (deviceName); - #if (CUDART_VERSION > 4020) - if (devStr.size() > 2 && devStr.data()[0] == ':' && devStr.data()[1] == ':') - devStr = devStr.replace(0, 2, ""); - #endif - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - printf("GPGPU-Sim PTX: in __cudaRegisterTexture:\n"); - gpu->gpgpu_ptx_sim_bindNameToTexture(devStr.data(), hostVar, dim, norm, ext); - printf("GPGPU-Sim PTX: int dim = %d\n", dim); - printf("GPGPU-Sim PTX: int norm = %d\n", norm); - printf("GPGPU-Sim PTX: int ext = %d\n", ext); - printf("GPGPU-Sim PTX: Execution warning: Not finished implementing \"%s\"\n", __my_func__ ); -} - -#ifndef OPENGL_SUPPORT -typedef unsigned long GLuint; -#endif - -cudaError_t cudaGLRegisterBufferObject(GLuint bufferObj) -{ - printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); - return g_last_cudaError = cudaSuccess; -} - -struct glbmap_entry { - GLuint m_bufferObj; - void *m_devPtr; - size_t m_size; - struct glbmap_entry *m_next; -}; -typedef struct glbmap_entry glbmap_entry_t; - -glbmap_entry_t* g_glbmap = NULL; - -cudaError_t cudaGLMapBufferObject(void** devPtr, GLuint bufferObj) -{ -#ifdef OPENGL_SUPPORT - GLint buffer_size=0; - CUctx_st* ctx = GPGPUSim_Context(); - - glbmap_entry_t *p = g_glbmap; - while ( p && p->m_bufferObj != bufferObj ) - p = p->m_next; - if ( p == NULL ) { - glBindBuffer(GL_ARRAY_BUFFER,bufferObj); - glGetBufferParameteriv(GL_ARRAY_BUFFER,GL_BUFFER_SIZE,&buffer_size); - assert( buffer_size != 0 ); - *devPtr = ctx->get_device()->get_gpgpu()->gpu_malloc(buffer_size); - - // create entry and insert to front of list - glbmap_entry_t *n = (glbmap_entry_t *) calloc(1,sizeof(glbmap_entry_t)); - n->m_next = g_glbmap; - g_glbmap = n; - - // initialize entry - n->m_bufferObj = bufferObj; - n->m_devPtr = *devPtr; - n->m_size = buffer_size; - - p = n; - } else { - buffer_size = p->m_size; - *devPtr = p->m_devPtr; - } - - if ( *devPtr ) { - char *data = (char *) calloc(p->m_size,1); - glGetBufferSubData(GL_ARRAY_BUFFER,0,buffer_size,data); - memcpy_to_gpu( (size_t) *devPtr, data, buffer_size ); - free(data); - printf("GPGPU-Sim PTX: cudaGLMapBufferObject %zu bytes starting at 0x%llx..\n", (size_t)buffer_size, - (unsigned long long) *devPtr); - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorMemoryAllocation; - } - - return g_last_cudaError = cudaSuccess; -#else - fflush(stdout); - fflush(stderr); - printf("GPGPU-Sim PTX: GPGPU-Sim support for OpenGL integration disabled -- exiting\n"); - fflush(stdout); - exit(50); -#endif -} - -cudaError_t cudaGLUnmapBufferObject(GLuint bufferObj) -{ -#ifdef OPENGL_SUPPORT - glbmap_entry_t *p = g_glbmap; - while ( p && p->m_bufferObj != bufferObj ) - p = p->m_next; - if ( p == NULL ) - return g_last_cudaError = cudaErrorUnknown; - - char *data = (char *) calloc(p->m_size,1); - memcpy_from_gpu( data,(size_t)p->m_devPtr,p->m_size ); - glBufferSubData(GL_ARRAY_BUFFER,0,p->m_size,data); - free(data); - - return g_last_cudaError = cudaSuccess; -#else - fflush(stdout); - fflush(stderr); - printf("GPGPU-Sim PTX: support for OpenGL integration disabled -- exiting\n"); - fflush(stdout); - exit(50); -#endif -} - -cudaError_t cudaGLUnregisterBufferObject(GLuint bufferObj) -{ - printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); - return g_last_cudaError = cudaSuccess; -} - -#if (CUDART_VERSION >= 2010) - -cudaError_t CUDARTAPI cudaHostAlloc(void **pHost, size_t bytes, unsigned int flags) -{ - *pHost = malloc(bytes); - //need to track the size allocated so that cudaHostGetDevicePointer() can function properly. - //TODO: vary this function behavior based on flags value (following nvidia documentation) - pinned_memory_size[*pHost]=bytes; - if( *pHost ) - return g_last_cudaError = cudaSuccess; - else - return g_last_cudaError = cudaErrorMemoryAllocation; -} - -cudaError_t CUDARTAPI cudaHostGetDevicePointer(void **pDevice, void *pHost, unsigned int flags) -{ - //only cpu memory allocation happens in cudaHostAlloc. Linking with device pointer to pinned memory happens here. - //TODO: once kernel is executed, the contents in global pointer of GPU must be copied back to CPU host pointer! - flags=0; - CUctx_st* context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - std::map::const_iterator i = pinned_memory_size.find(pHost); - assert(i != pinned_memory_size.end()); - size_t size = i->second; - *pDevice = gpu->gpu_malloc(size); - if(g_debug_execution >= 3) - printf("GPGPU-Sim PTX: cudaMallocing %zu bytes starting at 0x%llx..\n",size, (unsigned long long) *pDevice); - if ( *pDevice ) { - pinned_memory[pHost]=pDevice; - //Copy contents in cpu to gpu - gpu->memcpy_to_gpu((size_t)*pDevice,pHost,size); - return g_last_cudaError = cudaSuccess; - } else { - return g_last_cudaError = cudaErrorMemoryAllocation; - } -} - -cudaError_t CUDARTAPI cudaSetValidDevices(int *device_arr, int len) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - -cudaError_t CUDARTAPI cudaSetDeviceFlags( int flags ) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - -cudaError_t CUDARTAPI cudaFuncGetAttributes(struct cudaFuncAttributes *attr, const char *hostFun ) -{ - CUctx_st *context = GPGPUSim_Context(); - function_info *entry = context->get_kernel(hostFun); - if( entry ) { - const struct gpgpu_ptx_sim_info *kinfo = entry->get_kernel_info(); - attr->sharedSizeBytes = kinfo->smem; - attr->constSizeBytes = kinfo->cmem; - attr->localSizeBytes = kinfo->lmem; - attr->numRegs = kinfo->regs; - attr->maxThreadsPerBlock = 0; // from pragmas? -#if CUDART_VERSION >= 3000 - attr->ptxVersion = kinfo->ptx_version; - attr->binaryVersion = kinfo->sm_target; -#endif - } - return g_last_cudaError = cudaSuccess; -} - -cudaError_t CUDARTAPI cudaEventCreateWithFlags(cudaEvent_t *event, int flags) -{ - CUevent_st *e = new CUevent_st(flags==cudaEventBlockingSync); - g_timer_events[e->get_uid()] = e; -#if CUDART_VERSION >= 3000 - *event = e; -#else - *event = e->get_uid(); -#endif - return g_last_cudaError = cudaSuccess; -} - -cudaError_t CUDARTAPI cudaDriverGetVersion(int *driverVersion) -{ - *driverVersion = CUDART_VERSION; - return g_last_cudaError = cudaErrorUnknown; -} - -cudaError_t CUDARTAPI cudaRuntimeGetVersion(int *runtimeVersion) -{ - *runtimeVersion = CUDART_VERSION; - return g_last_cudaError = cudaErrorUnknown; -} - -#if CUDART_VERSION >= 3000 -__host__ cudaError_t CUDARTAPI cudaFuncSetCacheConfig(const char *func, enum cudaFuncCache cacheConfig ) -{ - CUctx_st *context = GPGPUSim_Context(); - context->get_device()->get_gpgpu()->set_cache_config(context->get_kernel(func)->get_name(), (FuncCache)cacheConfig); - return g_last_cudaError = cudaSuccess; -} - -//Jin: hack for cdp -__host__ cudaError_t CUDARTAPI cudaDeviceSetLimit(enum cudaLimit limit, size_t value) { - return g_last_cudaError = cudaSuccess; -} -#endif - -#endif - -cudaError_t CUDARTAPI cudaGLSetGLDevice(int device) -{ - printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); - return g_last_cudaError = cudaErrorUnknown; -} - -typedef void* HGPUNV; - -cudaError_t CUDARTAPI cudaWGLGetDevice(int *device, HGPUNV hGpu) -{ - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; -} - -void CUDARTAPI __cudaMutexOperation(int lock) -{ - cuda_not_implemented(__my_func__,__LINE__); -} - -void CUDARTAPI __cudaTextureFetch(const void *tex, void *index, int integer, void *val) -{ - cuda_not_implemented(__my_func__,__LINE__); -} - -} - -namespace cuda_math { - -void CUDARTAPI __cudaMutexOperation(int lock) -{ - cuda_not_implemented(__my_func__,__LINE__); -} - -void CUDARTAPI __cudaTextureFetch(const void *tex, void *index, int integer, void *val) -{ - cuda_not_implemented(__my_func__,__LINE__); -} - -int CUDARTAPI __cudaSynchronizeThreads(void**, void*) -{ - //TODO This function should syncronize if we support Asyn kernel calls - return g_last_cudaError = cudaSuccess; -} - -} - -//////// - -extern int ptx_parse(); -extern int ptx__scan_string(const char*); -extern FILE *ptx_in; - -extern int ptxinfo_parse(); -extern int ptxinfo_debug; -extern FILE *ptxinfo_in; - -/// static functions - -static int load_static_globals( symbol_table *symtab, unsigned min_gaddr, unsigned max_gaddr, gpgpu_t *gpu ) -{ - printf( "GPGPU-Sim PTX: loading globals with explicit initializers... \n" ); - fflush(stdout); - int ng_bytes=0; - symbol_table::iterator g=symtab->global_iterator_begin(); - - for ( ; g!=symtab->global_iterator_end(); g++) { - symbol *global = *g; - if ( global->has_initializer() ) { - printf( "GPGPU-Sim PTX: initializing '%s' ... ", global->name().c_str() ); - unsigned addr=global->get_address(); - const type_info *type = global->type(); - type_info_key ti=type->get_key(); - size_t size; - int t; - ti.type_decode(size,t); - int nbytes = size/8; - int offset=0; - std::list init_list = global->get_initializer(); - for ( std::list::iterator i=init_list.begin(); i!=init_list.end(); i++ ) { - operand_info op = *i; - ptx_reg_t value = op.get_literal_value(); - assert( (addr+offset+nbytes) < min_gaddr ); // min_gaddr is start of "heap" for cudaMalloc - gpu->get_global_memory()->write(addr+offset,nbytes,&value,NULL,NULL); // assuming little endian here - offset+=nbytes; - ng_bytes+=nbytes; - } - printf(" wrote %u bytes\n", offset ); - } - } - printf( "GPGPU-Sim PTX: finished loading globals (%u bytes total).\n", ng_bytes ); - fflush(stdout); - return ng_bytes; -} - -static int load_constants( symbol_table *symtab, addr_t min_gaddr, gpgpu_t *gpu ) -{ - printf( "GPGPU-Sim PTX: loading constants with explicit initializers... " ); - fflush(stdout); - int nc_bytes = 0; - symbol_table::iterator g=symtab->const_iterator_begin(); - - for ( ; g!=symtab->const_iterator_end(); g++) { - symbol *constant = *g; - if ( constant->is_const() && constant->has_initializer() ) { - - // get the constant element data size - int basic_type; - size_t num_bits; - constant->type()->get_key().type_decode(num_bits,basic_type); - - std::list init_list = constant->get_initializer(); - int nbytes_written = 0; - for ( std::list::iterator i=init_list.begin(); i!=init_list.end(); i++ ) { - operand_info op = *i; - ptx_reg_t value = op.get_literal_value(); - int nbytes = num_bits/8; - switch ( op.get_type() ) { - case int_t: assert(nbytes >= 1); break; - case float_op_t: assert(nbytes == 4); break; - case double_op_t: assert(nbytes >= 4); break; // account for double DEMOTING - default: - abort(); - } - unsigned addr=constant->get_address() + nbytes_written; - assert( addr+nbytes < min_gaddr ); - - gpu->get_global_memory()->write(addr,nbytes,&value,NULL,NULL); // assume little endian (so u8 is the first byte in u32) - nc_bytes+=nbytes; - nbytes_written += nbytes; - } - } - } - printf( " done.\n"); - fflush(stdout); - return nc_bytes; -} - -kernel_info_t *gpgpu_cuda_ptx_sim_init_grid( const char *hostFun, - gpgpu_ptx_sim_arg_list_t args, - struct dim3 gridDim, - struct dim3 blockDim, - CUctx_st* context ) -{ - function_info *entry = context->get_kernel(hostFun); - kernel_info_t *result = new kernel_info_t(gridDim,blockDim,entry); - if( entry == NULL ) { - printf("GPGPU-Sim PTX: ERROR launching kernel -- no PTX implementation found for %p\n", hostFun); - abort(); - } - unsigned argcount=args.size(); - unsigned argn=1; - for( gpgpu_ptx_sim_arg_list_t::iterator a = args.begin(); a != args.end(); a++ ) { - entry->add_param_data(argcount-argn,&(*a)); - argn++; - } - - entry->finalize(result->get_param_memory()); - g_ptx_kernel_count++; - fflush(stdout); - - return result; -} diff --git a/src/cuda-sim/cuda-sim.cc~ b/src/cuda-sim/cuda-sim.cc~ deleted file mode 100644 index cfd901f..0000000 --- a/src/cuda-sim/cuda-sim.cc~ +++ /dev/null @@ -1,2155 +0,0 @@ -// Copyright (c) 2009-2011, Tor M. Aamodt, Ali Bakhoda, Wilson W.L. Fung, -// George L. Yuan, Jimmy Kwa -// The University of British Columbia -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// Redistributions in binary form must reproduce the above copyright notice, this -// list of conditions and the following disclaimer in the documentation and/or -// other materials provided with the distribution. -// Neither the name of The University of British Columbia nor the names of its -// contributors may be used to endorse or promote products derived from this -// software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -#include "cuda-sim.h" - -#include "instructions.h" -#include "ptx_ir.h" -#include "ptx.tab.h" -#include "ptx_sim.h" -#include - -#include "opcodes.h" -#include "../statwrapper.h" -#include -#include -#include "../abstract_hardware_model.h" -#include "memory.h" -#include "ptx-stats.h" -#include "ptx_loader.h" -#include "ptx_parser.h" -#include "../gpgpu-sim/gpu-sim.h" -#include "ptx_sim.h" -#include "../gpgpusim_entrypoint.h" -#include "decuda_pred_table/decuda_pred_table.h" -#include "../stream_manager.h" -#include "cuda_device_runtime.h" - -int gpgpu_ptx_instruction_classification; -void ** g_inst_classification_stat = NULL; -void ** g_inst_op_classification_stat= NULL; -int g_ptx_kernel_count = -1; // used for classification stat collection purposes -int g_debug_execution = 0; -int g_debug_thread_uid = 0; -addr_t g_debug_pc = 0xBEEF1518; -// Output debug information to file options - -unsigned g_ptx_sim_num_insn = 0; -unsigned gpgpu_param_num_shaders = 0; - -char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp; -char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp; -char *cdp_latency_str; -unsigned cdp_latency[5]; - -void ptx_opcocde_latency_options (option_parser_t opp) { - option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int, - "Opcode latencies for integers " - "Default 1,1,19,25,145", - "1,1,19,25,145"); - option_parser_register(opp, "-ptx_opcode_latency_fp", OPT_CSTR, &opcode_latency_fp, - "Opcode latencies for single precision floating points " - "Default 1,1,1,1,30", - "1,1,1,1,30"); - option_parser_register(opp, "-ptx_opcode_latency_dp", OPT_CSTR, &opcode_latency_dp, - "Opcode latencies for double precision floating points " - "Default 8,8,8,8,335", - "8,8,8,8,335"); - option_parser_register(opp, "-ptx_opcode_initiation_int", OPT_CSTR, &opcode_initiation_int, - "Opcode initiation intervals for integers " - "Default 1,1,4,4,32", - "1,1,4,4,32"); - option_parser_register(opp, "-ptx_opcode_initiation_fp", OPT_CSTR, &opcode_initiation_fp, - "Opcode initiation intervals for single precision floating points " - "Default 1,1,1,1,5", - "1,1,1,1,5"); - option_parser_register(opp, "-ptx_opcode_initiation_dp", OPT_CSTR, &opcode_initiation_dp, - "Opcode initiation intervals for double precision floating points " - "Default 8,8,8,8,130", - "8,8,8,8,130"); - option_parser_register(opp, "-cdp_latency", OPT_CSTR, &cdp_latency_str, - "CDP API latency " - "Default 7200,8000,100,12000,1600", - "7200,8000,100,12000,1600"); -} - -static address_type get_converge_point(address_type pc); - -void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) -{ - std::string texname(name); - m_NameToTextureRef[texname] = texref; - const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); - m_TextureRefToAttribute[texref] = texAttr; -} - -const char* gpgpu_t::gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref) -{ - std::map::iterator itr = m_NameToTextureRef.begin(); - while (itr != m_NameToTextureRef.end()) { - if ((*itr).second == texref) { - const char *p = ((*itr).first).c_str(); - return p; - } - itr++; - } - return NULL; -} - -unsigned int intLOGB2( unsigned int v ) { - unsigned int shift; - unsigned int r; - - r = 0; - - shift = (( v & 0xFFFF0000) != 0 ) << 4; v >>= shift; r |= shift; - shift = (( v & 0xFF00 ) != 0 ) << 3; v >>= shift; r |= shift; - shift = (( v & 0xF0 ) != 0 ) << 2; v >>= shift; r |= shift; - shift = (( v & 0xC ) != 0 ) << 1; v >>= shift; r |= shift; - shift = (( v & 0x2 ) != 0 ) << 0; v >>= shift; r |= shift; - - return r; -} - -void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) -{ - m_TextureRefToCudaArray[texref] = array; - unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; - unsigned int texel_size = texel_size_bits/8; - unsigned int Tx, Ty; - int r; - - printf("GPGPU-Sim PTX: texel size = %d\n", texel_size); - printf("GPGPU-Sim PTX: texture cache linesize = %d\n", m_function_model_config.get_texcache_linesize()); - //first determine base Tx size for given linesize - switch (m_function_model_config.get_texcache_linesize()) { - case 16: Tx = 4; break; - case 32: Tx = 8; break; - case 64: Tx = 8; break; - case 128: Tx = 16; break; - case 256: Tx = 16; break; - default: - printf("GPGPU-Sim PTX: Line size of %d bytes currently not supported.\n", m_function_model_config.get_texcache_linesize()); - assert(0); - break; - } - r = texel_size >> 2; - //modify base Tx size to take into account size of each texel in bytes - while (r != 0) { - Tx = Tx >> 1; - r = r >> 2; - } - //by now, got the correct Tx size, calculate correct Ty size - Ty = m_function_model_config.get_texcache_linesize()/(Tx*texel_size); - - printf("GPGPU-Sim PTX: Tx = %d; Ty = %d, Tx_numbits = %d, Ty_numbits = %d\n", Tx, Ty, intLOGB2(Tx), intLOGB2(Ty)); - printf("GPGPU-Sim PTX: Texel size = %d bytes; texel_size_numbits = %d\n", texel_size, intLOGB2(texel_size)); - printf("GPGPU-Sim PTX: Binding texture to array starting at devPtr32 = 0x%x\n", array->devPtr32); - printf("GPGPU-Sim PTX: Texel size = %d bytes\n", texel_size); - struct textureInfo* texInfo = (struct textureInfo*) malloc(sizeof(struct textureInfo)); - texInfo->Tx = Tx; - texInfo->Ty = Ty; - texInfo->Tx_numbits = intLOGB2(Tx); - texInfo->Ty_numbits = intLOGB2(Ty); - texInfo->texel_size = texel_size; - texInfo->texel_size_numbits = intLOGB2(texel_size); - m_TextureRefToTexureInfo[texref] = texInfo; -} - -unsigned g_assemble_code_next_pc=0; -std::map g_pc_to_finfo; -std::vector function_info::s_g_pc_to_insn; - -#define MAX_INST_SIZE 8 /*bytes*/ - -void function_info::ptx_assemble() -{ - if( m_assembled ) { - return; - } - - // get the instructions into instruction memory... - unsigned num_inst = m_instructions.size(); - m_instr_mem_size = MAX_INST_SIZE*(num_inst+1); - m_instr_mem = new ptx_instruction*[ m_instr_mem_size ]; - - printf("GPGPU-Sim PTX: instruction assembly for function \'%s\'... ", m_name.c_str() ); - fflush(stdout); - std::list::iterator i; - - addr_t PC = g_assemble_code_next_pc; // globally unique address (across functions) - // start function on an aligned address - for( unsigned i=0; i < (PC%MAX_INST_SIZE); i++ ) - s_g_pc_to_insn.push_back((ptx_instruction*)NULL); - PC += PC%MAX_INST_SIZE; - m_start_PC = PC; - - addr_t n=0; // offset in m_instr_mem - //Why s_g_pc_to_insn.size() is needed to reserve additional memory for insts? reserve is cumulative. - //s_g_pc_to_insn.reserve(s_g_pc_to_insn.size() + MAX_INST_SIZE*m_instructions.size()); - s_g_pc_to_insn.reserve(MAX_INST_SIZE*m_instructions.size()); - for ( i=m_instructions.begin(); i != m_instructions.end(); i++ ) { - ptx_instruction *pI = *i; - if ( pI->is_label() ) { - const symbol *l = pI->get_label(); - labels[l->name()] = n; - } else { - g_pc_to_finfo[PC] = this; - m_instr_mem[n] = pI; - s_g_pc_to_insn.push_back(pI); - assert(pI == s_g_pc_to_insn[PC]); - pI->set_m_instr_mem_index(n); - pI->set_PC(PC); - assert( pI->inst_size() <= MAX_INST_SIZE ); - for( unsigned i=1; i < pI->inst_size(); i++ ) { - s_g_pc_to_insn.push_back((ptx_instruction*)NULL); - m_instr_mem[n+i]=NULL; - } - n += pI->inst_size(); - PC += pI->inst_size(); - } - } - g_assemble_code_next_pc=PC; - for ( unsigned ii=0; ii < n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions - ptx_instruction *pI = m_instr_mem[ii]; - if ( pI->get_opcode() == BRA_OP || pI->get_opcode() == BREAKADDR_OP || pI->get_opcode() == CALLP_OP) { - operand_info &target = pI->dst(); //get operand, e.g. target name - if ( labels.find(target.name()) == labels.end() ) { - printf("GPGPU-Sim PTX: Loader error (%s:%u): Branch label \"%s\" does not appear in assembly code.", - pI->source_file(),pI->source_line(), target.name().c_str() ); - abort(); - } - unsigned index = labels[ target.name() ]; //determine address from name - unsigned PC = m_instr_mem[index]->get_PC(); - m_symtab->set_label_address( target.get_symbol(), PC ); - target.set_type(label_t); - } - } - m_n = n; - printf(" done.\n"); - fflush(stdout); - - //disable pdom analysis here and do it at runtime - printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", m_name.c_str() ); - create_basic_blocks(); - connect_basic_blocks(); - bool modified = false; - do { - find_dominators(); - find_idominators(); - modified = connect_break_targets(); - } while (modified == true); - - if ( g_debug_execution>=50 ) { - print_basic_blocks(); - print_basic_block_links(); - print_basic_block_dot(); - } - if ( g_debug_execution>=2 ) { - print_dominators(); - } - find_postdominators(); - find_ipostdominators(); - if ( g_debug_execution>=50 ) { - print_postdominators(); - print_ipostdominators(); - } - - printf("GPGPU-Sim PTX: pre-decoding instructions for \'%s\'...\n", m_name.c_str() ); - for ( unsigned ii=0; ii < n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions - ptx_instruction *pI = m_instr_mem[ii]; - pI->pre_decode(); - } - printf("GPGPU-Sim PTX: ... done pre-decoding instructions for \'%s\'.\n", m_name.c_str() ); - fflush(stdout); - - m_assembled = true; -} - -addr_t shared_to_generic( unsigned smid, addr_t addr ) -{ - assert( addr < SHARED_MEM_SIZE_MAX ); - return SHARED_GENERIC_START + smid*SHARED_MEM_SIZE_MAX + addr; -} - -addr_t global_to_generic( addr_t addr ) -{ - return addr; -} - -bool isspace_shared( unsigned smid, addr_t addr ) -{ - addr_t start = SHARED_GENERIC_START + smid*SHARED_MEM_SIZE_MAX; - addr_t end = SHARED_GENERIC_START + (smid+1)*SHARED_MEM_SIZE_MAX; - if( (addr >= end) || (addr < start) ) - return false; - return true; -} - -bool isspace_global( addr_t addr ) -{ - return (addr >= GLOBAL_HEAP_START) || (addr < STATIC_ALLOC_LIMIT); -} - -memory_space_t whichspace( addr_t addr ) -{ - if( (addr >= GLOBAL_HEAP_START) || (addr < STATIC_ALLOC_LIMIT) ) { - return global_space; - } else if( addr >= SHARED_GENERIC_START ) { - return shared_space; - } else { - return local_space; - } -} - -addr_t generic_to_shared( unsigned smid, addr_t addr ) -{ - assert(isspace_shared(smid,addr)); - return addr - (SHARED_GENERIC_START + smid*SHARED_MEM_SIZE_MAX); -} - -addr_t local_to_generic( unsigned smid, unsigned hwtid, addr_t addr ) -{ - assert(addr < LOCAL_MEM_SIZE_MAX); - return LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * hwtid) + addr; -} - -bool isspace_local( unsigned smid, unsigned hwtid, addr_t addr ) -{ - addr_t start = LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * hwtid); - addr_t end = LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * (hwtid+1)); - if( (addr >= end) || (addr < start) ) - return false; - return true; -} - -addr_t generic_to_local( unsigned smid, unsigned hwtid, addr_t addr ) -{ - assert(isspace_local(smid,hwtid,addr)); - return addr - (LOCAL_GENERIC_START + (TOTAL_LOCAL_MEM_PER_SM * smid) + (LOCAL_MEM_SIZE_MAX * hwtid)); -} - -addr_t generic_to_global( addr_t addr ) -{ - return addr; -} - - -void* gpgpu_t::gpu_malloc( size_t size ) -{ - unsigned long long result = m_dev_malloc; - if(g_debug_execution >= 3) { - printf("GPGPU-Sim PTX: allocating %zu bytes on GPU starting at address 0x%Lx\n", size, m_dev_malloc ); - fflush(stdout); - } - m_dev_malloc += size; - if (size%256) m_dev_malloc += (256 - size%256); //align to 256 byte boundaries - return(void*) result; -} - -void* gpgpu_t::gpu_mallocarray( size_t size ) -{ - unsigned long long result = m_dev_malloc; - if(g_debug_execution >= 3) { - printf("GPGPU-Sim PTX: allocating %zu bytes on GPU starting at address 0x%Lx\n", size, m_dev_malloc ); - fflush(stdout); - } - m_dev_malloc += size; - if (size%256) m_dev_malloc += (256 - size%256); //align to 256 byte boundaries - return(void*) result; -} - - -void gpgpu_t::memcpy_to_gpu( size_t dst_start_addr, const void *src, size_t count ) -{ - if(g_debug_execution >= 3) { - printf("GPGPU-Sim PTX: copying %zu bytes from CPU[0x%Lx] to GPU[0x%Lx] ... ", count, (unsigned long long) src, (unsigned long long) dst_start_addr ); - fflush(stdout); - } - char *src_data = (char*)src; - for (unsigned n=0; n < count; n ++ ) - m_global_mem->write(dst_start_addr+n,1, src_data+n,NULL,NULL); - if(g_debug_execution >= 3) { - printf( " done.\n"); - fflush(stdout); - } -} - -void gpgpu_t::memcpy_from_gpu( void *dst, size_t src_start_addr, size_t count ) -{ - if(g_debug_execution >= 3) { - printf("GPGPU-Sim PTX: copying %zu bytes from GPU[0x%Lx] to CPU[0x%Lx] ...", count, (unsigned long long) src_start_addr, (unsigned long long) dst ); - fflush(stdout); - } - unsigned char *dst_data = (unsigned char*)dst; - for (unsigned n=0; n < count; n ++ ) - m_global_mem->read(src_start_addr+n,1,dst_data+n); - if(g_debug_execution >= 3) { - printf( " done.\n"); - fflush(stdout); - } -} - -void gpgpu_t::memcpy_gpu_to_gpu( size_t dst, size_t src, size_t count ) -{ - if(g_debug_execution >= 3) { - printf("GPGPU-Sim PTX: copying %zu bytes from GPU[0x%Lx] to GPU[0x%Lx] ...", count, - (unsigned long long) src, (unsigned long long) dst ); - fflush(stdout); - } - for (unsigned n=0; n < count; n ++ ) { - unsigned char tmp; - m_global_mem->read(src+n,1,&tmp); - m_global_mem->write(dst+n,1, &tmp,NULL,NULL); - } - if(g_debug_execution >= 3) { - printf( " done.\n"); - fflush(stdout); - } -} - -void gpgpu_t::gpu_memset( size_t dst_start_addr, int c, size_t count ) -{ - if(g_debug_execution >= 3) { - printf("GPGPU-Sim PTX: setting %zu bytes of memory to 0x%x starting at 0x%Lx... ", - count, (unsigned char) c, (unsigned long long) dst_start_addr ); - fflush(stdout); - } - unsigned char c_value = (unsigned char)c; - for (unsigned n=0; n < count; n ++ ) - m_global_mem->write(dst_start_addr+n,1,&c_value,NULL,NULL); - if(g_debug_execution >= 3) { - printf( " done.\n"); - fflush(stdout); - } -} - -void ptx_print_insn( address_type pc, FILE *fp ) -{ - std::map::iterator f = g_pc_to_finfo.find(pc); - if( f == g_pc_to_finfo.end() ) { - fprintf(fp,"", pc ); - return; - } - function_info *finfo = f->second; - assert( finfo ); - finfo->print_insn(pc,fp); -} - -std::string ptx_get_insn_str( address_type pc ) -{ - std::map::iterator f = g_pc_to_finfo.find(pc); - if( f == g_pc_to_finfo.end() ) { - #define STR_SIZE 255 - char buff[STR_SIZE]; - buff[STR_SIZE - 1] = '\0'; - snprintf(buff, STR_SIZE,"", pc ); - return std::string(buff); - } - function_info *finfo = f->second; - assert( finfo ); - return finfo->get_insn_str(pc); -} - -void ptx_instruction::set_fp_or_int_archop(){ - oprnd_type=UN_OP; - if((m_opcode == MEMBAR_OP)||(m_opcode == SSY_OP )||(m_opcode == BRA_OP) || (m_opcode == BAR_OP) || (m_opcode == RET_OP) || (m_opcode == RETP_OP) || (m_opcode == NOP_OP) || (m_opcode == EXIT_OP) || (m_opcode == CALLP_OP) || (m_opcode == CALL_OP)){ - // do nothing - }else if((m_opcode == CVT_OP || m_opcode == SET_OP || m_opcode == SLCT_OP)){ - if(get_type2()==F16_TYPE || get_type2()==F32_TYPE || get_type2() == F64_TYPE || get_type2() == FF64_TYPE){ - oprnd_type= FP_OP; - }else oprnd_type=INT_OP; - - }else{ - if(get_type()==F16_TYPE || get_type()==F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE){ - oprnd_type= FP_OP; - }else oprnd_type=INT_OP; - } -} -void ptx_instruction::set_mul_div_or_other_archop(){ - sp_op=OTHER_OP; - if((m_opcode != MEMBAR_OP) && (m_opcode != SSY_OP) && (m_opcode != BRA_OP) && (m_opcode != BAR_OP) && (m_opcode != EXIT_OP) && (m_opcode != NOP_OP) && (m_opcode != RETP_OP) && (m_opcode != RET_OP) && (m_opcode != CALLP_OP) && (m_opcode != CALL_OP)){ - if(get_type()==F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE){ - switch(get_opcode()){ - case MUL_OP: - case MAD_OP: - sp_op=FP_MUL_OP; - break; - case DIV_OP: - sp_op=FP_DIV_OP; - break; - case LG2_OP: - sp_op=FP_LG_OP; - break; - case RSQRT_OP: - case SQRT_OP: - sp_op=FP_SQRT_OP; - break; - case RCP_OP: - sp_op=FP_DIV_OP; - break; - case SIN_OP: - case COS_OP: - sp_op=FP_SIN_OP; - break; - case EX2_OP: - sp_op=FP_EXP_OP; - break; - default: - if(op==ALU_OP) - sp_op=FP__OP; - break; - - } - }else { - switch(get_opcode()){ - case MUL24_OP: - case MAD24_OP: - sp_op=INT_MUL24_OP; - break; - case MUL_OP: - case MAD_OP: - if(get_type()==U32_TYPE || get_type()==S32_TYPE || get_type()==B32_TYPE) - sp_op=INT_MUL32_OP; - else - sp_op=INT_MUL_OP; - break; - case DIV_OP: - sp_op=INT_DIV_OP; - break; - default: - if(op==ALU_OP) - sp_op=INT__OP; - break; - } - } - } - -} - - - -void ptx_instruction::set_bar_type() -{ - if(m_opcode==BAR_OP) { - switch(m_barrier_op){ - case SYNC_OPTION: - bar_type = SYNC; - break; - case ARRIVE_OPTION: - bar_type = ARRIVE; - break; - case RED_OPTION: - bar_type = RED; - switch(m_atomic_spec){ - case ATOMIC_POPC: - red_type = POPC_RED; - break; - case ATOMIC_AND: - red_type = AND_RED; - break; - case ATOMIC_OR: - red_type = OR_RED; - break; - } - break; - default: - abort(); - } - } -} - - -void ptx_instruction::set_opcode_and_latency() -{ - unsigned int_latency[5]; - unsigned fp_latency[5]; - unsigned dp_latency[5]; - unsigned int_init[5]; - unsigned fp_init[5]; - unsigned dp_init[5]; - /* - * [0] ADD,SUB - * [1] MAX,Min - * [2] MUL - * [3] MAD - * [4] DIV - */ - sscanf(opcode_latency_int, "%u,%u,%u,%u,%u", - &int_latency[0],&int_latency[1],&int_latency[2], - &int_latency[3],&int_latency[4]); - sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u", - &fp_latency[0],&fp_latency[1],&fp_latency[2], - &fp_latency[3],&fp_latency[4]); - sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u", - &dp_latency[0],&dp_latency[1],&dp_latency[2], - &dp_latency[3],&dp_latency[4]); - sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u", - &int_init[0],&int_init[1],&int_init[2], - &int_init[3],&int_init[4]); - sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u", - &fp_init[0],&fp_init[1],&fp_init[2], - &fp_init[3],&fp_init[4]); - sscanf(opcode_initiation_dp, "%u,%u,%u,%u,%u", - &dp_init[0],&dp_init[1],&dp_init[2], - &dp_init[3],&dp_init[4]); - sscanf(cdp_latency_str, "%u,%u,%u,%u,%u", - &cdp_latency[0],&cdp_latency[1],&cdp_latency[2], - &cdp_latency[3],&cdp_latency[4]); - - if(!m_operands.empty()){ - std::vector::iterator it; - for(it=++m_operands.begin();it!=m_operands.end();it++){ - num_operands++; - if((it->is_reg() || it->is_vector())){ - num_regs++; - } - } - } - op = ALU_OP; - mem_op= NOT_TEX; - initiation_interval = latency = 1; - switch( m_opcode ) { - case MOV_OP: - assert( !(has_memory_read() && has_memory_write()) ); - if ( has_memory_read() ) op = LOAD_OP; - if ( has_memory_write() ) op = STORE_OP; - break; - case LD_OP: op = LOAD_OP; break; - case LDU_OP: op = LOAD_OP; break; - case ST_OP: op = STORE_OP; break; - case BRA_OP: op = BRANCH_OP; break; - case BREAKADDR_OP: op = BRANCH_OP; break; - case TEX_OP: op = LOAD_OP; mem_op=TEX; break; - case ATOM_OP: op = LOAD_OP; break; - case BAR_OP: op = BARRIER_OP; break; - case MEMBAR_OP: op = MEMORY_BARRIER_OP; break; - case CALL_OP: - { - if(m_is_printf || m_is_cdp) { - op = ALU_OP; - } - else - op = CALL_OPS; - break; - } - case CALLP_OP: - { - if(m_is_printf || m_is_cdp) { - op = ALU_OP; - } - else - op = CALL_OPS; - break; - } - case RET_OP: case RETP_OP: op = RET_OPS;break; - case ADD_OP: case ADDP_OP: case ADDC_OP: case SUB_OP: case SUBC_OP: - //ADD,SUB latency - switch(get_type()){ - case F32_TYPE: - latency = fp_latency[0]; - initiation_interval = fp_init[0]; - break; - case F64_TYPE: - case FF64_TYPE: - latency = dp_latency[0]; - initiation_interval = dp_init[0]; - break; - case B32_TYPE: - case U32_TYPE: - case S32_TYPE: - default: //Use int settings for default - latency = int_latency[0]; - initiation_interval = int_init[0]; - break; - } - break; - case MAX_OP: case MIN_OP: - //MAX,MIN latency - switch(get_type()){ - case F32_TYPE: - latency = fp_latency[1]; - initiation_interval = fp_init[1]; - break; - case F64_TYPE: - case FF64_TYPE: - latency = dp_latency[1]; - initiation_interval = dp_init[1]; - break; - case B32_TYPE: - case U32_TYPE: - case S32_TYPE: - default: //Use int settings for default - latency = int_latency[1]; - initiation_interval = int_init[1]; - break; - } - break; - case MUL_OP: - //MUL latency - switch(get_type()){ - case F32_TYPE: - latency = fp_latency[2]; - initiation_interval = fp_init[2]; - op = ALU_SFU_OP; - break; - case F64_TYPE: - case FF64_TYPE: - latency = dp_latency[2]; - initiation_interval = dp_init[2]; - op = ALU_SFU_OP; - break; - case B32_TYPE: - case U32_TYPE: - case S32_TYPE: - default: //Use int settings for default - latency = int_latency[2]; - initiation_interval = int_init[2]; - op = SFU_OP; - break; - } - break; - case MAD_OP: case MADC_OP: case MADP_OP: - //MAD latency - switch(get_type()){ - case F32_TYPE: - latency = fp_latency[3]; - initiation_interval = fp_init[3]; - break; - case F64_TYPE: - case FF64_TYPE: - latency = dp_latency[3]; - initiation_interval = dp_init[3]; - break; - case B32_TYPE: - case U32_TYPE: - case S32_TYPE: - default: //Use int settings for default - latency = int_latency[3]; - initiation_interval = int_init[3]; - op = SFU_OP; - break; - } - break; - case DIV_OP: - // Floating point only - op = SFU_OP; - switch(get_type()){ - case F32_TYPE: - latency = fp_latency[4]; - initiation_interval = fp_init[4]; - break; - case F64_TYPE: - case FF64_TYPE: - latency = dp_latency[4]; - initiation_interval = dp_init[4]; - break; - case B32_TYPE: - case U32_TYPE: - case S32_TYPE: - default: //Use int settings for default - latency = int_latency[4]; - initiation_interval = int_init[4]; - break; - } - break; - case SQRT_OP: case SIN_OP: case COS_OP: case EX2_OP: case LG2_OP: case RSQRT_OP: case RCP_OP: - //Using double to approximate those - latency = dp_latency[2]; - initiation_interval = dp_init[2]; - op = SFU_OP; - break; - case SHFL_OP: - latency = 32; - initiation_interval = 15; - break; - default: - break; - } - set_fp_or_int_archop(); - set_mul_div_or_other_archop(); - -} - -void ptx_thread_info::ptx_fetch_inst( inst_t &inst ) const -{ - addr_t pc = get_pc(); - const ptx_instruction *pI = m_func_info->get_instruction(pc); - inst = (const inst_t&)*pI; - assert( inst.valid() ); -} - -static unsigned datatype2size( unsigned data_type ) -{ - unsigned data_size; - switch ( data_type ) { - case B8_TYPE: - case S8_TYPE: - case U8_TYPE: - data_size = 1; break; - case B16_TYPE: - case S16_TYPE: - case U16_TYPE: - case F16_TYPE: - data_size = 2; break; - case B32_TYPE: - case S32_TYPE: - case U32_TYPE: - case F32_TYPE: - data_size = 4; break; - case B64_TYPE: - case BB64_TYPE: - case S64_TYPE: - case U64_TYPE: - case F64_TYPE: - case FF64_TYPE: - data_size = 8; break; - case BB128_TYPE: - data_size = 16; break; - default: assert(0); break; - } - return data_size; -} - -void ptx_instruction::pre_decode() -{ - pc = m_PC; - isize = m_inst_size; - for( unsigned i=0; i<4; i++) { - out[i] = 0; - in[i] = 0; - } - is_vectorin = 0; - is_vectorout = 0; - std::fill_n(arch_reg.src, MAX_REG_OPERANDS, -1); - std::fill_n(arch_reg.dst, MAX_REG_OPERANDS, -1); - pred = 0; - ar1 = 0; - ar2 = 0; - space = m_space_spec; - memory_op = no_memory_op; - data_size = 0; - if ( has_memory_read() || has_memory_write() ) { - unsigned to_type = get_type(); - data_size = datatype2size(to_type); - memory_op = has_memory_read() ? memory_load : memory_store; - } - - bool has_dst = false ; - - switch ( get_opcode() ) { -#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; -#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: has_dst = (DST!=0); break; -#include "opcodes.def" -#undef OP_DEF -#undef OP_W_DEF - default: - printf( "Execution error: Invalid opcode (0x%x)\n", get_opcode() ); - break; - } - - switch( m_cache_option ) { - case CA_OPTION: cache_op = CACHE_ALL; break; - case CG_OPTION: cache_op = CACHE_GLOBAL; break; - case CS_OPTION: cache_op = CACHE_STREAMING; break; - case LU_OPTION: cache_op = CACHE_LAST_USE; break; - case CV_OPTION: cache_op = CACHE_VOLATILE; break; - case WB_OPTION: cache_op = CACHE_WRITE_BACK; break; - case WT_OPTION: cache_op = CACHE_WRITE_THROUGH; break; - default: - if( m_opcode == LD_OP || m_opcode == LDU_OP ) - cache_op = CACHE_ALL; - else if( m_opcode == ST_OP ) - cache_op = CACHE_WRITE_BACK; - else if( m_opcode == ATOM_OP ) - cache_op = CACHE_GLOBAL; - break; - } - - set_opcode_and_latency(); - set_bar_type(); - // Get register operands - int n=0,m=0; - ptx_instruction::const_iterator opr=op_iter_begin(); - for ( ; opr != op_iter_end(); opr++, n++ ) { //process operands - const operand_info &o = *opr; - if ( has_dst && n==0 ) { - // Do not set the null register "_" as an architectural register - if ( o.is_reg() && !o.is_non_arch_reg() ) { - out[0] = o.reg_num(); - arch_reg.dst[0] = o.arch_reg_num(); - } else if ( o.is_vector() ) { - is_vectorin = 1; - unsigned num_elem = o.get_vect_nelem(); - if( num_elem >= 1 ) out[0] = o.reg1_num(); - if( num_elem >= 2 ) out[1] = o.reg2_num(); - if( num_elem >= 3 ) out[2] = o.reg3_num(); - if( num_elem >= 4 ) out[3] = o.reg4_num(); - for (int i = 0; i < num_elem; i++) - arch_reg.dst[i] = o.arch_reg_num(i); - } - } else { - if ( o.is_reg() && !o.is_non_arch_reg() ) { - int reg_num = o.reg_num(); - arch_reg.src[m] = o.arch_reg_num(); - switch ( m ) { - case 0: in[0] = reg_num; break; - case 1: in[1] = reg_num; break; - case 2: in[2] = reg_num; break; - default: break; - } - m++; - } else if ( o.is_vector() ) { - //assert(m == 0); //only support 1 vector operand (for textures) right now - is_vectorout = 1; - unsigned num_elem = o.get_vect_nelem(); - if( num_elem >= 1 ) in[0] = o.reg1_num(); - if( num_elem >= 2 ) in[1] = o.reg2_num(); - if( num_elem >= 3 ) in[2] = o.reg3_num(); - if( num_elem >= 4 ) in[3] = o.reg4_num(); - for (int i = 0; i < num_elem; i++) - arch_reg.src[i] = o.arch_reg_num(i); - m+=4; - } - } - } - - // Get predicate - if(has_pred()) { - const operand_info &p = get_pred(); - pred = p.reg_num(); - } - - // Get address registers inside memory operands. - // Assuming only one memory operand per instruction, - // and maximum of two address registers for one memory operand. - if( has_memory_read() || has_memory_write() ) { - ptx_instruction::const_iterator op=op_iter_begin(); - for ( ; op != op_iter_end(); op++, n++ ) { //process operands - const operand_info &o = *op; - - if(o.is_memory_operand()) { - // We do not support the null register as a memory operand - assert( !o.is_non_arch_reg() ); - - // Check PTXPlus-type operand - // memory operand with addressing (ex. s[0x4] or g[$r1]) - if(o.is_memory_operand2()) { - - // memory operand with one address register (ex. g[$r1+0x4] or s[$r2+=0x4]) - if(o.get_double_operand_type() == 0 || o.get_double_operand_type() == 3){ - ar1 = o.reg_num(); - arch_reg.src[4] = o.arch_reg_num(); - // TODO: address register in $r2+=0x4 should be an output register as well - } - // memory operand with two address register (ex. s[$r1+$r1] or g[$r1+=$r2]) - else if(o.get_double_operand_type() == 1 || o.get_double_operand_type() == 2) { - ar1 = o.reg1_num(); - arch_reg.src[4] = o.arch_reg_num(); - ar2 = o.reg2_num(); - arch_reg.src[5] = o.arch_reg_num(); - // TODO: first address register in $r1+=$r2 should be an output register as well - } - } - else if(o.is_immediate_address()){ - - } - // Regular PTX operand - else if (o.get_symbol()->type()->get_key().is_reg()) { // Memory operand contains a register - ar1 = o.reg_num(); - arch_reg.src[4] = o.arch_reg_num(); - } - - } - } - } - - // get reconvergence pc - reconvergence_pc = get_converge_point(pc); - - m_decoded=true; -} - -void function_info::add_param_name_type_size( unsigned index, std::string name, int type, size_t size, bool ptr, memory_space_t space ) -{ - unsigned parsed_index; - char buffer[2048]; - snprintf(buffer,2048,"%s_param_%%u", m_name.c_str() ); - int ntokens = sscanf(name.c_str(),buffer,&parsed_index); - if( ntokens == 1 ) { - assert( m_ptx_kernel_param_info.find(parsed_index) == m_ptx_kernel_param_info.end() ); - m_ptx_kernel_param_info[parsed_index] = param_info(name, type, size, ptr, space); - } else { - assert( m_ptx_kernel_param_info.find(index) == m_ptx_kernel_param_info.end() ); - m_ptx_kernel_param_info[index] = param_info(name, type, size, ptr, space); - } -} - -void function_info::add_param_data( unsigned argn, struct gpgpu_ptx_sim_arg *args ) -{ - const void *data = args->m_start; - - bool scratchpad_memory_param = false; // Is this parameter in CUDA shared memory or OpenCL local memory - - std::map::iterator i=m_ptx_kernel_param_info.find(argn); - if( i != m_ptx_kernel_param_info.end() ) { - if (i->second.is_ptr_shared()) { - assert(args->m_start == NULL && "OpenCL parameter pointer to local memory must have NULL as value"); - scratchpad_memory_param = true; - } else { - param_t tmp; - tmp.pdata = args->m_start; - tmp.size = args->m_nbytes; - tmp.offset = args->m_offset; - tmp.type = 0; - i->second.add_data(tmp); - i->second.add_offset((unsigned) args->m_offset); - } - } else { - scratchpad_memory_param = true; - } - - if (scratchpad_memory_param) { - // This should only happen for OpenCL: - // - // The LLVM PTX compiler in NVIDIA's driver (version 190.29) - // does not generate an argument in the function declaration - // for __constant arguments. - // - // The associated constant memory space can be allocated in two - // ways. It can be explicitly initialized in the .ptx file where - // it is declared. Or, it can be allocated using the clCreateBuffer - // on the host. In this later case, the .ptx file will contain - // a global declaration of the parameter, but it will have an unknown - // array size. Thus, the symbol's address will not be set and we need - // to set it here before executing the PTX. - - char buffer[2048]; - snprintf(buffer,2048,"%s_param_%u",m_name.c_str(),argn); - - symbol *p = m_symtab->lookup(buffer); - if( p == NULL ) { - printf("GPGPU-Sim PTX: ERROR ** could not locate symbol for \'%s\' : cannot bind buffer\n", buffer); - abort(); - } - if( data ) - p->set_address((addr_t)*(size_t*)data); - else { - // clSetKernelArg was passed NULL pointer for data... - // this is used for dynamically sized shared memory on NVIDIA platforms - bool is_ptr_shared = false; - if( i != m_ptx_kernel_param_info.end() ) { - is_ptr_shared = i->second.is_ptr_shared(); - } - - if( !is_ptr_shared and !p->is_shared() ) { - printf("GPGPU-Sim PTX: ERROR ** clSetKernelArg passed NULL but arg not shared memory\n"); - abort(); - } - unsigned num_bits = 8*args->m_nbytes; - printf("GPGPU-Sim PTX: deferred allocation of shared region for \"%s\" from 0x%x to 0x%x (shared memory space)\n", - p->name().c_str(), - m_symtab->get_shared_next(), - m_symtab->get_shared_next() + num_bits/8 ); - fflush(stdout); - assert( (num_bits%8) == 0 ); - addr_t addr = m_symtab->get_shared_next(); - addr_t addr_pad = num_bits ? (((num_bits/8) - (addr % (num_bits/8))) % (num_bits/8)) : 0; - p->set_address( addr+addr_pad ); - m_symtab->alloc_shared( num_bits/8 + addr_pad ); - } - } -} - -unsigned function_info::get_args_aligned_size() { - - if(m_args_aligned_size >= 0) - return m_args_aligned_size; - - unsigned param_address = 0; - unsigned int total_size = 0; - for( std::map::iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { - param_info &p = i->second; - std::string name = p.get_name(); - symbol *param = m_symtab->lookup(name.c_str()); - - size_t arg_size = p.get_size() / 8; // size of param in bytes - total_size = (total_size + arg_size - 1) / arg_size * arg_size; //aligned - p.add_offset(total_size); - param->set_address(param_address + total_size); - total_size += arg_size; - } - - m_args_aligned_size = (total_size + 3) / 4 * 4; //final size aligned to word - - return m_args_aligned_size; - -} - - -void function_info::finalize( memory_space *param_mem ) -{ - unsigned param_address = 0; - for( std::map::iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { - param_info &p = i->second; - if (p.is_ptr_shared()) continue; // Pointer to local memory: Should we pass the allocated shared memory address to the param memory space? - std::string name = p.get_name(); - int type = p.get_type(); - param_t param_value = p.get_value(); - param_value.type = type; - symbol *param = m_symtab->lookup(name.c_str()); - unsigned xtype = param->type()->get_key().scalar_type(); - assert(xtype==(unsigned)type); - size_t size; - size = param_value.size; // size of param in bytes - // assert(param_value.offset == param_address); - if( size != p.get_size() / 8) { - printf("GPGPU-Sim PTX: WARNING actual kernel paramter size = %zu bytes vs. formal size = %zu (using smaller of two)\n", - size, p.get_size()/8); - size = (size<(p.get_size()/8))?size:(p.get_size()/8); - } - // copy the parameter over word-by-word so that parameter that crosses a memory page can be copied over - //Jin: copy parameter using aligned rules - const size_t word_size = 4; - param_address = (param_address + size - 1) / size * size; //aligned with size - for (size_t idx = 0; idx < size; idx += word_size) { - const char *pdata = reinterpret_cast(param_value.pdata) + idx; // cast to char * for ptr arithmetic - param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); - } - unsigned offset = p.get_offset(); - assert(offset == param_address); - param->set_address(param_address); - param_address += size; - } -} - -void function_info::param_to_shared( memory_space *shared_mem, symbol_table *symtab ) -{ - // TODO: call this only for PTXPlus with GT200 models - extern gpgpu_sim* g_the_gpu; - if (not g_the_gpu->get_config().convert_to_ptxplus()) return; - - // copies parameters into simulated shared memory - for( std::map::iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { - param_info &p = i->second; - if (p.is_ptr_shared()) continue; // Pointer to local memory: Should we pass the allocated shared memory address to the param memory space? - std::string name = p.get_name(); - int type = p.get_type(); - param_t value = p.get_value(); - value.type = type; - symbol *param = symtab->lookup(name.c_str()); - unsigned xtype = param->type()->get_key().scalar_type(); - assert(xtype==(unsigned)type); - - int tmp; - size_t size; - unsigned offset = p.get_offset(); - type_info_key::type_decode(xtype,size,tmp); - - // Write to shared memory - offset + 0x10 - shared_mem->write(offset+0x10,size/8,value.pdata,NULL,NULL); - } -} - - -void function_info::list_param( FILE *fout ) const -{ - for( std::map::const_iterator i=m_ptx_kernel_param_info.begin(); i!=m_ptx_kernel_param_info.end(); i++ ) { - const param_info &p = i->second; - std::string name = p.get_name(); - symbol *param = m_symtab->lookup(name.c_str()); - addr_t param_addr = param->get_address(); - fprintf(fout, "%s: %#08x\n", name.c_str(), param_addr); - } - fflush(fout); -} - -template -bool ptx_debug_exec_dump_cond(int thd_uid, addr_t pc) -{ - if (g_debug_execution >= activate_level) { - // check each type of debug dump constraint to filter out dumps - if ( (g_debug_thread_uid != 0) && (thd_uid != (unsigned)g_debug_thread_uid) ) { - return false; - } - if ( (g_debug_pc != 0xBEEF1518) && (pc != g_debug_pc) ) { - return false; - } - - return true; - } - - return false; -} - -void init_inst_classification_stat() -{ - static std::set init; - if( init.find(g_ptx_kernel_count) != init.end() ) - return; - init.insert(g_ptx_kernel_count); - - #define MAX_CLASS_KER 1024 - char kernelname[MAX_CLASS_KER] =""; - if (!g_inst_classification_stat) g_inst_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); - snprintf(kernelname, MAX_CLASS_KER, "Kernel %d Classification\n",g_ptx_kernel_count ); - assert( g_ptx_kernel_count < MAX_CLASS_KER ) ; // a static limit on number of kernels increase it if it fails! - g_inst_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,20); - if (!g_inst_op_classification_stat) g_inst_op_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); - snprintf(kernelname, MAX_CLASS_KER, "Kernel %d OP Classification\n",g_ptx_kernel_count ); - g_inst_op_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,100); -} - -static unsigned get_tex_datasize( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &src1 = pI->src1(); //the name of the texture - std::string texname = src1.name(); - - gpgpu_t *gpu = thread->get_gpu(); - const struct textureReference* texref = gpu->get_texref(texname); - const struct textureInfo* texInfo = gpu->get_texinfo(texref); - - unsigned data_size = texInfo->texel_size; - return data_size; -} - -void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) -{ - - bool skip = false; - int op_classification = 0; - addr_t pc = next_instr(); - assert( pc == inst.pc ); // make sure timing model and functional model are in sync - const ptx_instruction *pI = m_func_info->get_instruction(pc); - set_npc( pc + pI->inst_size() ); - - - try { - - clearRPC(); - m_last_set_operand_value.u64 = 0; - - if(is_done()) - { - printf("attempted to execute instruction on a thread that is already done.\n"); - assert(0); - } - - if ( g_debug_execution >= 6 || m_gpu->get_config().get_ptx_inst_debug_to_file()) { - if ( (g_debug_thread_uid==0) || (get_uid() == (unsigned)g_debug_thread_uid) ) { - - clear_modifiedregs(); - enable_debug_trace(); - } - } - - - if( pI->has_pred() ) { - const operand_info &pred = pI->get_pred(); - ptx_reg_t pred_value = get_operand_value(pred, pred, PRED_TYPE, this, 0); - if(pI->get_pred_mod() == -1) { - skip = (pred_value.pred & 0x0001) ^ pI->get_pred_neg(); //ptxplus inverts the zero flag - } else { - skip = !pred_lookup(pI->get_pred_mod(), pred_value.pred & 0x000F); - } - } - - if( skip ) { - inst.set_not_active(lane_id); - } else { - const ptx_instruction *pI_saved = pI; - ptx_instruction *pJ = NULL; - if( pI->get_opcode() == VOTE_OP ) { - pJ = new ptx_instruction(*pI); - *((warp_inst_t*)pJ) = inst; // copy active mask information - pI = pJ; - } - switch ( pI->get_opcode() ) { -#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; -#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; -#include "opcodes.def" -#undef OP_DEF -#undef OP_W_DEF - default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break; - } - delete pJ; - pI = pI_saved; - - // Run exit instruction if exit option included - if(pI->is_exit()) - exit_impl(pI,this); - } - - - - const gpgpu_functional_sim_config &config = m_gpu->get_config(); - - // Output instruction information to file and stdout - if( config.get_ptx_inst_debug_to_file() != 0 && - (config.get_ptx_inst_debug_thread_uid() == 0 || config.get_ptx_inst_debug_thread_uid() == get_uid()) ) { - fprintf(m_gpu->get_ptx_inst_debug_file(), - "[thd=%u] : (%s:%u - %s)\n", - get_uid(), - pI->source_file(), pI->source_line(), pI->get_source() ); - //fprintf(ptx_inst_debug_file, "has memory read=%d, has memory write=%d\n", pI->has_memory_read(), pI->has_memory_write()); - fflush(m_gpu->get_ptx_inst_debug_file()); - } - - if ( ptx_debug_exec_dump_cond<5>(get_uid(), pc) ) { - dim3 ctaid = get_ctaid(); - dim3 tid = get_tid(); - printf("%u [thd=%u][i=%u] : ctaid=(%u,%u,%u) tid=(%u,%u,%u) icount=%u [pc=%u] (%s:%u - %s) [0x%llx]\n", - g_ptx_sim_num_insn, - get_uid(), - pI->uid(), ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z, - get_icount(), - pc, pI->source_file(), pI->source_line(), pI->get_source(), - m_last_set_operand_value.u64 ); - fflush(stdout); - } - - addr_t insn_memaddr = 0xFEEBDAED; - memory_space_t insn_space = undefined_space; - _memory_op_t insn_memory_op = no_memory_op; - unsigned insn_data_size = 0; - if ( (pI->has_memory_read() || pI->has_memory_write()) ) { - insn_memaddr = last_eaddr(); - insn_space = last_space(); - unsigned to_type = pI->get_type(); - insn_data_size = datatype2size(to_type); - insn_memory_op = pI->has_memory_read() ? memory_load : memory_store; - } - - if ( pI->get_opcode() == BAR_OP && pI->barrier_op() == RED_OPTION) { - inst.add_callback( lane_id, last_callback().function, last_callback().instruction, this,false /*not atomic*/); - } - - if ( pI->get_opcode() == ATOM_OP ) { - insn_memaddr = last_eaddr(); - insn_space = last_space(); - inst.add_callback( lane_id, last_callback().function, last_callback().instruction, this,true /*atomic*/); - unsigned to_type = pI->get_type(); - insn_data_size = datatype2size(to_type); - } - - if (pI->get_opcode() == TEX_OP) { - inst.set_addr(lane_id, last_eaddr() ); - assert( inst.space == last_space() ); - insn_data_size = get_tex_datasize(pI, this); // texture obtain its data granularity from the texture info - } - - // Output register information to file and stdout - if( config.get_ptx_inst_debug_to_file()!=0 && - (config.get_ptx_inst_debug_thread_uid()==0||config.get_ptx_inst_debug_thread_uid()==get_uid()) ) { - dump_modifiedregs(m_gpu->get_ptx_inst_debug_file()); - dump_regs(m_gpu->get_ptx_inst_debug_file()); - } - - if ( g_debug_execution >= 6 ) { - if ( ptx_debug_exec_dump_cond<6>(get_uid(), pc) ) - dump_modifiedregs(stdout); - } - if ( g_debug_execution >= 10 ) { - if ( ptx_debug_exec_dump_cond<10>(get_uid(), pc) ) - dump_regs(stdout); - } - update_pc(); - g_ptx_sim_num_insn++; - - //not using it with functional simulation mode - if(!(this->m_functionalSimulationMode)) - ptx_file_line_stats_add_exec_count(pI); - - if ( gpgpu_ptx_instruction_classification ) { - init_inst_classification_stat(); - unsigned space_type=0; - switch ( pI->get_space().get_type() ) { - case global_space: space_type = 10; break; - case local_space: space_type = 11; break; - case tex_space: space_type = 12; break; - case surf_space: space_type = 13; break; - case param_space_kernel: - case param_space_local: - space_type = 14; break; - case shared_space: space_type = 15; break; - case const_space: space_type = 16; break; - default: - space_type = 0 ; - break; - } - StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], op_classification); - if (space_type) StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], ( int )space_type); - StatAddSample( g_inst_op_classification_stat[g_ptx_kernel_count], (int) pI->get_opcode() ); - } - if ( (g_ptx_sim_num_insn % 100000) == 0 ) { - dim3 ctaid = get_ctaid(); - dim3 tid = get_tid(); - printf("GPGPU-Sim PTX: %u instructions simulated : ctaid=(%u,%u,%u) tid=(%u,%u,%u)\n", - g_ptx_sim_num_insn, ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z ); - fflush(stdout); - } - - // "Return values" - if(!skip) { - inst.space = insn_space; - inst.set_addr(lane_id, insn_memaddr); - inst.data_size = insn_data_size; // simpleAtomicIntrinsics - assert( inst.memory_op == insn_memory_op ); - } - - } catch ( int x ) { - printf("GPGPU-Sim PTX: ERROR (%d) executing intruction (%s:%u)\n", x, pI->source_file(), pI->source_line() ); - printf("GPGPU-Sim PTX: '%s'\n", pI->get_source() ); - abort(); - } - -} - -void set_param_gpgpu_num_shaders(int num_shaders) -{ - gpgpu_param_num_shaders = num_shaders; -} - -const struct gpgpu_ptx_sim_info* ptx_sim_kernel_info(const function_info *kernel) -{ - return kernel->get_kernel_info(); -} - -const warp_inst_t *ptx_fetch_inst( address_type pc ) -{ - return function_info::pc_to_instruction(pc); -} - -unsigned ptx_sim_init_thread( kernel_info_t &kernel, - ptx_thread_info** thread_info, - int sid, - unsigned tid, - unsigned threads_left, - unsigned num_threads, - core_t *core, - unsigned hw_cta_id, - unsigned hw_warp_id, - gpgpu_t *gpu, - bool isInFunctionalSimulationMode) -{ - std::list &active_threads = kernel.active_threads(); - - static std::map shared_memory_lookup; - static std::map ptx_cta_lookup; - static std::map ptx_warp_lookup; - static std::map > local_memory_lookup; - - if ( *thread_info != NULL ) { - ptx_thread_info *thd = *thread_info; - assert( thd->is_done() ); - if ( g_debug_execution==-1 ) { - dim3 ctaid = thd->get_ctaid(); - dim3 t = thd->get_tid(); - printf("GPGPU-Sim PTX simulator: thread exiting ctaid=(%u,%u,%u) tid=(%u,%u,%u) uid=%u\n", - ctaid.x,ctaid.y,ctaid.z,t.x,t.y,t.z, thd->get_uid() ); - fflush(stdout); - } - thd->m_cta_info->register_deleted_thread(thd); - delete thd; - *thread_info = NULL; - } - - if ( !active_threads.empty() ) { - assert( active_threads.size() <= threads_left ); - ptx_thread_info *thd = active_threads.front(); - active_threads.pop_front(); - *thread_info = thd; - thd->init(gpu, core, sid, hw_cta_id, hw_warp_id, tid, isInFunctionalSimulationMode ); - return 1; - } - - if ( kernel.no_more_ctas_to_run() ) { - return 0; //finished! - } - - if ( threads_left < kernel.threads_per_cta() ) { - return 0; - } - - if ( g_debug_execution==-1 ) { - printf("GPGPU-Sim PTX simulator: STARTING THREAD ALLOCATION --> \n"); - fflush(stdout); - } - - //initializing new CTA - ptx_cta_info *cta_info = NULL; - memory_space *shared_mem = NULL; - - unsigned cta_size = kernel.threads_per_cta(); - unsigned max_cta_per_sm = num_threads/cta_size; // e.g., 256 / 48 = 5 - assert( max_cta_per_sm > 0 ); - - //unsigned sm_idx = (tid/cta_size)*gpgpu_param_num_shaders + sid; - unsigned sm_idx = hw_cta_id*gpgpu_param_num_shaders + sid; - - if ( shared_memory_lookup.find(sm_idx) == shared_memory_lookup.end() ) { - if ( g_debug_execution >= 1 ) { - printf(" : sm_idx=%u sid=%u max_cta_per_sm=%u\n", - sm_idx, sid, max_cta_per_sm ); - } - char buf[512]; - snprintf(buf,512,"shared_%u", sid); - shared_mem = new memory_space_impl<16*1024>(buf,4); - shared_memory_lookup[sm_idx] = shared_mem; - cta_info = new ptx_cta_info(sm_idx); - ptx_cta_lookup[sm_idx] = cta_info; - } else { - if ( g_debug_execution >= 1 ) { - printf(" : sm_idx=%u sid=%u max_cta_per_sm=%u\n", - sm_idx, sid, max_cta_per_sm ); - } - shared_mem = shared_memory_lookup[sm_idx]; - cta_info = ptx_cta_lookup[sm_idx]; - cta_info->check_cta_thread_status_and_reset(); - } - - std::map &local_mem_lookup = local_memory_lookup[sid]; - while( kernel.more_threads_in_cta() ) { - dim3 ctaid3d = kernel.get_next_cta_id(); - unsigned new_tid = kernel.get_next_thread_id(); - dim3 tid3d = kernel.get_next_thread_id_3d(); - kernel.increment_thread_id(); - new_tid += tid; - ptx_thread_info *thd = new ptx_thread_info(kernel); - - ptx_warp_info *warp_info = NULL; - if ( ptx_warp_lookup.find(hw_warp_id) == ptx_warp_lookup.end() ) { - warp_info = new ptx_warp_info(); - ptx_warp_lookup[hw_warp_id] = warp_info; - } else { - warp_info = ptx_warp_lookup[hw_warp_id]; - } - thd->m_warp_info = warp_info; - - memory_space *local_mem = NULL; - std::map::iterator l = local_mem_lookup.find(new_tid); - if ( l != local_mem_lookup.end() ) { - local_mem = l->second; - } else { - char buf[512]; - snprintf(buf,512,"local_%u_%u", sid, new_tid); - local_mem = new memory_space_impl<32>(buf,32); - local_mem_lookup[new_tid] = local_mem; - } - thd->set_info(kernel.entry()); - thd->set_nctaid(kernel.get_grid_dim()); - thd->set_ntid(kernel.get_cta_dim()); - thd->set_ctaid(ctaid3d); - thd->set_tid(tid3d); - if( kernel.entry()->get_ptx_version().extensions() ) - thd->cpy_tid_to_reg(tid3d); - thd->set_valid(); - thd->m_shared_mem = shared_mem; - function_info *finfo = thd->func_info(); - symbol_table *st = finfo->get_symtab(); - thd->func_info()->param_to_shared(thd->m_shared_mem,st); - thd->m_cta_info = cta_info; - cta_info->add_thread(thd); - thd->m_local_mem = local_mem; - if ( g_debug_execution==-1 ) { - printf("GPGPU-Sim PTX simulator: allocating thread ctaid=(%u,%u,%u) tid=(%u,%u,%u) @ 0x%Lx\n", - ctaid3d.x,ctaid3d.y,ctaid3d.z,tid3d.x,tid3d.y,tid3d.z, (unsigned long long)thd ); - fflush(stdout); - } - active_threads.push_back(thd); - } - if ( g_debug_execution==-1 ) { - printf("GPGPU-Sim PTX simulator: <-- FINISHING THREAD ALLOCATION\n"); - fflush(stdout); - } - - kernel.increment_cta_id(); - - assert( active_threads.size() <= threads_left ); - *thread_info = active_threads.front(); - (*thread_info)->init(gpu, core, sid, hw_cta_id, hw_warp_id, tid,isInFunctionalSimulationMode ); - active_threads.pop_front(); - return 1; -} - -size_t get_kernel_code_size( class function_info *entry ) -{ - return entry->get_function_size(); -} - - -kernel_info_t *gpgpu_opencl_ptx_sim_init_grid(class function_info *entry, - gpgpu_ptx_sim_arg_list_t args, - struct dim3 gridDim, - struct dim3 blockDim, - gpgpu_t *gpu ) -{ - kernel_info_t *result = new kernel_info_t(gridDim,blockDim,entry); - unsigned argcount=args.size(); - unsigned argn=1; - for( gpgpu_ptx_sim_arg_list_t::iterator a = args.begin(); a != args.end(); a++ ) { - entry->add_param_data(argcount-argn,&(*a)); - argn++; - } - entry->finalize(result->get_param_memory()); - g_ptx_kernel_count++; - fflush(stdout); - - return result; -} - -#include "../../version" -#include "detailed_version" - -void print_splash() -{ - static int splash_printed=0; - if ( !splash_printed ) { - fprintf(stdout, "\n\n *** %s [build %s] ***\n\n\n", g_gpgpusim_version_string, g_gpgpusim_build_string ); - splash_printed=1; - } -} - -std::map g_const_name_lookup; // indexed by hostVar -std::map g_global_name_lookup; // indexed by hostVar -std::set g_globals; -std::set g_constants; - -void gpgpu_ptx_sim_register_const_variable(void *hostVar, const char *deviceName, size_t size ) -{ - printf("GPGPU-Sim PTX registering constant %s (%zu bytes) to name mapping\n", deviceName, size ); - g_const_name_lookup[hostVar] = deviceName; -} - -void gpgpu_ptx_sim_register_global_variable(void *hostVar, const char *deviceName, size_t size ) -{ - printf("GPGPU-Sim PTX registering global %s hostVar to name mapping\n", deviceName ); - g_global_name_lookup[hostVar] = deviceName; -} - -void gpgpu_ptx_sim_memcpy_symbol(const char *hostVar, const void *src, size_t count, size_t offset, int to, gpgpu_t *gpu ) -{ - printf("GPGPU-Sim PTX: starting gpgpu_ptx_sim_memcpy_symbol with hostVar 0x%p\n", hostVar); - bool found_sym = false; - memory_space_t mem_region = undefined_space; - std::string sym_name; - - std::map::iterator c=g_const_name_lookup.find(hostVar); - if ( c!=g_const_name_lookup.end() ) { - found_sym = true; - sym_name = c->second; - mem_region = const_space; - } - std::map::iterator g=g_global_name_lookup.find(hostVar); - if ( g!=g_global_name_lookup.end() ) { - if ( found_sym ) { - printf("Execution error: PTX symbol \"%s\" w/ hostVar=0x%Lx is declared both const and global?\n", - sym_name.c_str(), (unsigned long long)hostVar ); - abort(); - } - found_sym = true; - sym_name = g->second; - mem_region = global_space; - } - if( g_globals.find(hostVar) != g_globals.end() ) { - found_sym = true; - sym_name = hostVar; - mem_region = global_space; - } - if( g_constants.find(hostVar) != g_constants.end() ) { - found_sym = true; - sym_name = hostVar; - mem_region = const_space; - } - - if ( !found_sym ) { - printf("Execution error: No information for PTX symbol w/ hostVar=0x%Lx\n", (unsigned long long)hostVar ); - abort(); - } else printf("GPGPU-Sim PTX: gpgpu_ptx_sim_memcpy_symbol: Found PTX symbol w/ hostVar=0x%Lx\n", (unsigned long long)hostVar ); - const char *mem_name = NULL; - memory_space *mem = NULL; - - std::map::iterator st = g_sym_name_to_symbol_table.find(sym_name.c_str()); - assert( st != g_sym_name_to_symbol_table.end() ); - symbol_table *symtab = st->second; - - symbol *sym = symtab->lookup(sym_name.c_str()); - assert(sym); - unsigned dst = sym->get_address() + offset; - switch (mem_region.get_type()) { - case const_space: - mem = gpu->get_global_memory(); - mem_name = "const"; - break; - case global_space: - mem = gpu->get_global_memory(); - mem_name = "global"; - break; - default: - abort(); - } - printf("GPGPU-Sim PTX: gpgpu_ptx_sim_memcpy_symbol: copying %s memory %zu bytes %s symbol %s+%zu @0x%x ...\n", - mem_name, count, (to?" to ":"from"), sym_name.c_str(), offset, dst ); - for ( unsigned n=0; n < count; n++ ) { - if( to ) mem->write(dst+n,1,((char*)src)+n,NULL,NULL); - else mem->read(dst+n,1,((char*)src)+n); - } - fflush(stdout); -} - -int g_ptx_sim_mode; // if non-zero run functional simulation only (i.e., no notion of a clock cycle) - -extern int ptx_debug; - -bool g_cuda_launch_blocking = false; - -void read_sim_environment_variables() -{ - ptx_debug = 0; - g_debug_execution = 0; - g_interactive_debugger_enabled = false; - - char *mode = getenv("PTX_SIM_MODE_FUNC"); - if ( mode ) - sscanf(mode,"%u", &g_ptx_sim_mode); - printf("GPGPU-Sim PTX: simulation mode %d (can change with PTX_SIM_MODE_FUNC environment variable:\n", g_ptx_sim_mode); - printf(" 1=functional simulation only, 0=detailed performance simulator)\n"); - char *dbg_inter = getenv("GPGPUSIM_DEBUG"); - if ( dbg_inter && strlen(dbg_inter) ) { - printf("GPGPU-Sim PTX: enabling interactive debugger\n"); - fflush(stdout); - g_interactive_debugger_enabled = true; - } - char *dbg_level = getenv("PTX_SIM_DEBUG"); - if ( dbg_level && strlen(dbg_level) ) { - printf("GPGPU-Sim PTX: setting debug level to %s\n", dbg_level ); - fflush(stdout); - sscanf(dbg_level,"%d", &g_debug_execution); - } - char *dbg_thread = getenv("PTX_SIM_DEBUG_THREAD_UID"); - if ( dbg_thread && strlen(dbg_thread) ) { - printf("GPGPU-Sim PTX: printing debug information for thread uid %s\n", dbg_thread ); - fflush(stdout); - sscanf(dbg_thread,"%d", &g_debug_thread_uid); - } - char *dbg_pc = getenv("PTX_SIM_DEBUG_PC"); - if ( dbg_pc && strlen(dbg_pc) ) { - printf("GPGPU-Sim PTX: printing debug information for instruction with PC = %s\n", dbg_pc ); - fflush(stdout); - sscanf(dbg_pc,"%d", &g_debug_pc); - } - -#if CUDART_VERSION > 1010 - g_override_embedded_ptx = false; - char *usefile = getenv("PTX_SIM_USE_PTX_FILE"); - if (usefile && strlen(usefile)) { - printf("GPGPU-Sim PTX: overriding embedded ptx with ptx file (PTX_SIM_USE_PTX_FILE is set)\n"); - fflush(stdout); - g_override_embedded_ptx = true; - } - char *blocking = getenv("CUDA_LAUNCH_BLOCKING"); - if( blocking && !strcmp(blocking,"1") ) { - g_cuda_launch_blocking = true; - } -#else - g_cuda_launch_blocking = true; - g_override_embedded_ptx = true; -#endif - - if ( g_debug_execution >= 40 ) { - ptx_debug = 1; - } -} - -ptx_cta_info *g_func_cta_info = NULL; - -#define MAX(a,b) (((a)>(b))?(a):(b)) - -/*! -This function simulates the CUDA code functionally, it takes a kernel_info_t parameter -which holds the data for the CUDA kernel to be executed -!*/ -void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL ) -{ - printf("GPGPU-Sim: Performing Functional Simulation, executing kernel %s...\n",kernel.name().c_str()); - - //using a shader core object for book keeping, it is not needed but as most function built for performance simulation need it we use it here - extern gpgpu_sim *g_the_gpu; - //before we execute, we should do PDOM analysis for functional simulation scenario. - function_info *kernel_func_info = kernel.entry(); - if (kernel_func_info->is_pdom_set()) { - printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", kernel.name().c_str() ); - } else { - printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", kernel.name().c_str() ); - //kernel_func_info->do_pdom(); - kernel_func_info->set_pdom(); - } - - //we excute the kernel one CTA (Block) at the time, as synchronization functions work block wise - while(!kernel.no_more_ctas_to_run()){ - functionalCoreSim cta( - &kernel, - g_the_gpu, - g_the_gpu->getShaderCoreConfig()->warp_size - ); - cta.execute(); - -#if (CUDART_VERSION >= 5000) - launch_all_device_kernels(); -#endif - } - - //registering this kernel as done - - //openCL kernel simulation calls don't register the kernel so we don't register its exit - if(!openCL) { - extern stream_manager *g_stream_manager; - g_stream_manager->register_finished_kernel(kernel.get_uid()); - } - - //******PRINTING******* - printf( "GPGPU-Sim: Done functional simulation (%u instructions simulated).\n", g_ptx_sim_num_insn ); - if ( gpgpu_ptx_instruction_classification ) { - StatDisp( g_inst_classification_stat[g_ptx_kernel_count]); - StatDisp ( g_inst_op_classification_stat[g_ptx_kernel_count]); - } - - //time_t variables used to calculate the total simulation time - //the start time of simulation is hold by the global variable g_simulation_starttime - //g_simulation_starttime is initilized by gpgpu_ptx_sim_init_perf() in gpgpusim_entrypoint.cc upon starting gpgpu-sim - time_t end_time, elapsed_time, days, hrs, minutes, sec; - end_time = time((time_t *)NULL); - elapsed_time = MAX(end_time - g_simulation_starttime, 1); - - - //calculating and printing simulation time in terms of days, hours, minutes and seconds - days = elapsed_time/(3600*24); - hrs = elapsed_time/3600 - 24*days; - minutes = elapsed_time/60 - 60*(hrs + 24*days); - sec = elapsed_time - 60*(minutes + 60*(hrs + 24*days)); - - fflush(stderr); - printf("\n\ngpgpu_simulation_time = %u days, %u hrs, %u min, %u sec (%u sec)\n", - (unsigned)days, (unsigned)hrs, (unsigned)minutes, (unsigned)sec, (unsigned)elapsed_time ); - printf("gpgpu_simulation_rate = %u (inst/sec)\n", (unsigned)(g_ptx_sim_num_insn / elapsed_time) ); - fflush(stdout); -} - -void functionalCoreSim::initializeCTA() -{ - int ctaLiveThreads=0; - - for(int i=0; i< m_warp_count; i++){ - m_warpAtBarrier[i]=false; - m_liveThreadCount[i]=0; - } - for(int i=0; i< m_warp_count*m_warp_size;i++) - m_thread[i]=NULL; - - //get threads for a cta - for(unsigned i=0; ithreads_per_cta();i++) { - ptx_sim_init_thread(*m_kernel,&m_thread[i],0,i,m_kernel->threads_per_cta()-i,m_kernel->threads_per_cta(),this,0,i/m_warp_size,(gpgpu_t*)m_gpu, true); - assert(m_thread[i]!=NULL && !m_thread[i]->is_done()); - ctaLiveThreads++; - } - - for(int k=0;klaunch(m_thread[warpId*m_warp_size]->get_pc(),initialMask); - m_liveThreadCount[warpId]= liveThreadsCount; -} - -void functionalCoreSim::execute() - { - initializeCTA(); - - //start executing the CTA - while(true){ - bool someOneLive= false; - bool allAtBarrier = true; - for(unsigned i=0;i0) someOneLive=true; - if(!m_warpAtBarrier[i]&& m_liveThreadCount[i]>0) allAtBarrier = false; -} - -unsigned translate_pc_to_ptxlineno(unsigned pc) -{ - // this function assumes that the kernel fits inside a single PTX file - // function_info *pFunc = g_func_info; // assume that the current kernel is the one in query - const ptx_instruction *pInsn = function_info::pc_to_instruction(pc); - unsigned ptx_line_number = pInsn->source_line(); - - return ptx_line_number; -} - -// ptxinfo parser - -extern std::map get_duplicate(); - -int g_ptxinfo_error_detected; - -static char *g_ptxinfo_kname = NULL; -static struct gpgpu_ptx_sim_info g_ptxinfo; -static std::map g_duplicate; -static const char *g_last_dup_type; - -const char *get_ptxinfo_kname() -{ - return g_ptxinfo_kname; -} - -void print_ptxinfo() -{ - if(! get_ptxinfo_kname()){ - printf ("GPGPU-Sim PTX: Binary info : gmem=%u, cmem=%u\n", - g_ptxinfo.gmem, - g_ptxinfo.cmem); - } - if(get_ptxinfo_kname()){ - printf ("GPGPU-Sim PTX: Kernel \'%s\' : regs=%u, lmem=%u, smem=%u, cmem=%u\n", - get_ptxinfo_kname(), - g_ptxinfo.regs, - g_ptxinfo.lmem, - g_ptxinfo.smem, - g_ptxinfo.cmem ); - } -} - - -struct gpgpu_ptx_sim_info get_ptxinfo() -{ - return g_ptxinfo; -} - -std::map get_duplicate() -{ - return g_duplicate; -} - -void ptxinfo_linenum( unsigned linenum ) -{ - g_duplicate[linenum] = g_last_dup_type; -} - -void ptxinfo_dup_type( const char *dup_type ) -{ - g_last_dup_type = dup_type; -} - -void ptxinfo_function(const char *fname ) -{ - clear_ptxinfo(); - g_ptxinfo_kname = strdup(fname); -} - -void ptxinfo_regs( unsigned nregs ) -{ - g_ptxinfo.regs=nregs; -} - -void ptxinfo_lmem( unsigned declared, unsigned system ) -{ - g_ptxinfo.lmem=declared+system; -} - -void ptxinfo_gmem( unsigned declared, unsigned system ) -{ - g_ptxinfo.gmem=declared+system; -} - -void ptxinfo_smem( unsigned declared, unsigned system ) -{ - g_ptxinfo.smem=declared+system; -} - -void ptxinfo_cmem( unsigned nbytes, unsigned bank ) -{ - g_ptxinfo.cmem+=nbytes; -} - -void clear_ptxinfo() -{ - free(g_ptxinfo_kname); - g_ptxinfo_kname=NULL; - g_ptxinfo.regs=0; - g_ptxinfo.lmem=0; - g_ptxinfo.smem=0; - g_ptxinfo.cmem=0; - g_ptxinfo.gmem=0; - g_ptxinfo.ptx_version=0; - g_ptxinfo.sm_target=0; -} - - -void ptxinfo_opencl_addinfo( std::map &kernels ) -{ - - if(! g_ptxinfo_kname) { - printf ("GPGPU-Sim PTX: Binary info : gmem=%u, cmem=%u\n", - g_ptxinfo.gmem, - g_ptxinfo.cmem); - clear_ptxinfo(); - return; - } - - if( !strcmp("__cuda_dummy_entry__",g_ptxinfo_kname) ) { - // this string produced by ptxas for empty ptx files (e.g., bandwidth test) - clear_ptxinfo(); - return; - } - std::map::iterator k=kernels.find(g_ptxinfo_kname); - if( k==kernels.end() ) { - printf ("GPGPU-Sim PTX: ERROR ** implementation for '%s' not found.\n", g_ptxinfo_kname ); - abort(); - } else { - printf ("GPGPU-Sim PTX: Kernel \'%s\' : regs=%u, lmem=%u, smem=%u, cmem=%u\n", - g_ptxinfo_kname, - g_ptxinfo.regs, - g_ptxinfo.lmem, - g_ptxinfo.smem, - g_ptxinfo.cmem ); - function_info *finfo = k->second; - assert(finfo!=NULL); - finfo->set_kernel_info( g_ptxinfo ); - } - clear_ptxinfo(); -} - -struct rec_pts { - gpgpu_recon_t *s_kernel_recon_points; - int s_num_recon; -}; - -struct std::map g_rpts; - -struct rec_pts find_reconvergence_points( function_info *finfo ) -{ - rec_pts tmp; - std::map::iterator r=g_rpts.find(finfo); - - if( r==g_rpts.end() ) { - int num_recon = finfo->get_num_reconvergence_pairs(); - - gpgpu_recon_t *kernel_recon_points = (struct gpgpu_recon_t*) calloc(num_recon, sizeof(struct gpgpu_recon_t)); - finfo->get_reconvergence_pairs(kernel_recon_points); - printf("GPGPU-Sim PTX: reconvergence points for %s...\n", finfo->get_name().c_str() ); - for (int i=0;iprint_insn(); - printf("\n"); - printf("GPGPU-Sim PTX: immediate post dominator @ " ); - if( kernel_recon_points[i].target_inst ) - kernel_recon_points[i].target_inst->print_insn(); - printf("\n"); - } - printf("GPGPU-Sim PTX: ... end of reconvergence points for %s\n", finfo->get_name().c_str() ); - - tmp.s_kernel_recon_points = kernel_recon_points; - tmp.s_num_recon = num_recon; - g_rpts[finfo] = tmp; - } else { - tmp = r->second; - } - return tmp; -} - -address_type get_return_pc( void *thd ) -{ - // function call return - ptx_thread_info *the_thread = (ptx_thread_info*)thd; - assert( the_thread != NULL ); - return the_thread->get_return_PC(); -} - -address_type get_converge_point( address_type pc ) -{ - // the branch could encode the reconvergence point and/or a bit that indicates the - // reconvergence point is the return PC on the call stack in the case the branch has - // no immediate postdominator in the function (i.e., due to multiple return points). - - std::map::iterator f=g_pc_to_finfo.find(pc); - assert( f != g_pc_to_finfo.end() ); - function_info *finfo = f->second; - rec_pts tmp = find_reconvergence_points(finfo); - - int i=0; - for (; i < tmp.s_num_recon; ++i) { - if (tmp.s_kernel_recon_points[i].source_pc == pc) { - if( tmp.s_kernel_recon_points[i].target_pc == (unsigned) -2 ) { - return RECONVERGE_RETURN_PC; - } else { - return tmp.s_kernel_recon_points[i].target_pc; - } - } - } - return NO_BRANCH_DIVERGENCE; -} - -void functionalCoreSim::warp_exit( unsigned warp_id ) -{ - for(int i=0;im_cta_info->register_deleted_thread(m_thread[i]); - delete m_thread[i]; - } - } -} diff --git a/src/cuda-sim/instructions.cc~ b/src/cuda-sim/instructions.cc~ deleted file mode 100644 index 0e6f530..0000000 --- a/src/cuda-sim/instructions.cc~ +++ /dev/null @@ -1,4517 +0,0 @@ -// Copyright (c) 2009-2011, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda, -// Jimmy Kwa, George L. Yuan -// The University of British Columbia -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// Redistributions in binary form must reproduce the above copyright notice, this -// list of conditions and the following disclaimer in the documentation and/or -// other materials provided with the distribution. -// Neither the name of The University of British Columbia nor the names of its -// contributors may be used to endorse or promote products derived from this -// software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -#include "instructions.h" -#include "ptx_ir.h" -#include "opcodes.h" -#include "ptx_sim.h" -#include "ptx.tab.h" -#include -#include -#include -#include "cuda-math.h" -#include "../abstract_hardware_model.h" -#include "ptx_loader.h" -#include "cuda_device_printf.h" -#include "../gpgpu-sim/gpu-sim.h" -#include "../gpgpu-sim/shader.h" - -//Jin: include device runtime for CDP -#include "cuda_device_runtime.h" - -#include - -unsigned ptx_instruction::g_num_ptx_inst_uid=0; - -const char *g_opcode_string[NUM_OPCODES] = { -#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, -#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) STR, -#include "opcodes.def" -#undef OP_DEF -#undef OP_W_DEF -}; - -void inst_not_implemented( const ptx_instruction * pI ) ; -ptx_reg_t srcOperandModifiers(ptx_reg_t opData, operand_info opInfo, operand_info dstInfo, unsigned type, ptx_thread_info *thread); - -void sign_extend( ptx_reg_t &data, unsigned src_size, const operand_info &dst ); - -void ptx_thread_info::set_reg( const symbol *reg, const ptx_reg_t &value ) -{ - assert( reg != NULL ); - if( reg->name() == "_" ) return; - assert( !m_regs.empty() ); - assert( reg->uid() > 0 ); - m_regs.back()[ reg ] = value; - if (m_enable_debug_trace ) - m_debug_trace_regs_modified.back()[ reg ] = value; - m_last_set_operand_value = value; -} - -ptx_reg_t ptx_thread_info::get_reg( const symbol *reg ) -{ - static bool unfound_register_warned = false; - assert( reg != NULL ); - assert( !m_regs.empty() ); - reg_map_t::iterator regs_iter = m_regs.back().find(reg); - if (regs_iter == m_regs.back().end()) { - assert( reg->type()->get_key().is_reg() ); - const std::string &name = reg->name(); - unsigned call_uid = m_callstack.back().m_call_uid; - ptx_reg_t uninit_reg; - uninit_reg.u32 = 0x0; - set_reg(reg, uninit_reg); // give it a value since we are going to warn the user anyway - std::string file_loc = get_location(); - if( !unfound_register_warned ) { - printf("GPGPU-Sim PTX: WARNING (%s) ** reading undefined register \'%s\' (cuid:%u). Setting to 0X00000000. This is okay if you are simulating the native ISA" - "\n", - file_loc.c_str(), name.c_str(), call_uid ); - unfound_register_warned = true; - } - regs_iter = m_regs.back().find(reg); - } - if (m_enable_debug_trace ) - m_debug_trace_regs_read.back()[ reg ] = regs_iter->second; - return regs_iter->second; -} - -ptx_reg_t ptx_thread_info::get_operand_value( const operand_info &op, operand_info dstInfo, unsigned opType, ptx_thread_info *thread, int derefFlag ) -{ - ptx_reg_t result, tmp; - - - if(op.get_double_operand_type() == 0) { - if(((opType != BB128_TYPE) && (opType != BB64_TYPE) && (opType != FF64_TYPE)) || (op.get_addr_space() != undefined_space)) { - if ( op.is_reg() ) { - result = get_reg( op.get_symbol() ); - } else if ( op.is_builtin()) { - result.u32 = get_builtin( op.get_int(), op.get_addr_offset() ); - } else if(op.is_immediate_address()){ - result.u64 = op.get_addr_offset(); - } else if ( op.is_memory_operand() ) { - // a few options here... - const symbol *sym = op.get_symbol(); - const type_info *type = sym->type(); - const type_info_key &info = type->get_key(); - - if ( info.is_reg() ) { - const symbol *name = op.get_symbol(); - result.u64 = get_reg(name).u64 + op.get_addr_offset(); - } else if ( info.is_param_kernel() ) { - result.u64 = sym->get_address() + op.get_addr_offset(); - } else if ( info.is_param_local() ) { - result.u64 = sym->get_address() + op.get_addr_offset(); - } else if ( info.is_global() ) { - assert( op.get_addr_offset() == 0 ); - result.u64 = sym->get_address(); - } else if ( info.is_local() ) { - result.u64 = sym->get_address() + op.get_addr_offset(); - } else if ( info.is_const() ) { - result.u64 = sym->get_address() + op.get_addr_offset(); - } else if ( op.is_shared() ) { - result.u64 = op.get_symbol()->get_address() + op.get_addr_offset(); - } else { - const char *name = op.name().c_str(); - printf("GPGPU-Sim PTX: ERROR ** get_operand_value : unknown memory operand type for %s\n", name ); - abort(); - } - - } else if ( op.is_literal() ) { - result = op.get_literal_value(); - } else if ( op.is_label() ) { - result.u64 = op.get_symbol()->get_address(); - } else if ( op.is_shared() ) { - result.u64 = op.get_symbol()->get_address(); - } else if ( op.is_const() ) { - result.u64 = op.get_symbol()->get_address(); - } else if ( op.is_global() ) { - result.u64 = op.get_symbol()->get_address(); - } else if ( op.is_local() ) { - result.u64 = op.get_symbol()->get_address(); - } else if ( op.is_function_address() ) { - result.u64 = (size_t)op.get_symbol()->get_pc(); - } else { - const char *name = op.name().c_str(); - printf("GPGPU-Sim PTX: ERROR ** get_operand_value : unknown operand type for %s\n", name ); - assert(0); - } - - if(op.get_operand_lohi() == 1) - result.u64 = result.u64 & 0xFFFF; - else if(op.get_operand_lohi() == 2) - result.u64 = (result.u64>>16) & 0xFFFF; - } else if (opType == BB128_TYPE) { - // b128 - result.u128.lowest = get_reg( op.vec_symbol(0) ).u32; - result.u128.low = get_reg( op.vec_symbol(1) ).u32; - result.u128.high = get_reg( op.vec_symbol(2) ).u32; - result.u128.highest = get_reg( op.vec_symbol(3) ).u32; - } else { - // bb64 or ff64 - result.bits.ls = get_reg( op.vec_symbol(0) ).u32; - result.bits.ms = get_reg( op.vec_symbol(1) ).u32; - } - } else if (op.get_double_operand_type() == 1) { - ptx_reg_t firstHalf, secondHalf; - firstHalf.u64 = get_reg( op.vec_symbol(0) ).u64; - secondHalf.u64 = get_reg( op.vec_symbol(1) ).u64; - if(op.get_operand_lohi() == 1) - secondHalf.u64 = secondHalf.u64 & 0xFFFF; - else if(op.get_operand_lohi() == 2) - secondHalf.u64 = (secondHalf.u64>>16) & 0xFFFF; - result.u64 = firstHalf.u64 + secondHalf.u64; - } else if (op.get_double_operand_type() == 2) { - // s[reg1 += reg2] - // reg1 is incremented after value is returned: the value returned is s[reg1] - ptx_reg_t firstHalf, secondHalf; - firstHalf.u64 = get_reg(op.vec_symbol(0)).u64; - secondHalf.u64 = get_reg(op.vec_symbol(1)).u64; - if(op.get_operand_lohi() == 1) - secondHalf.u64 = secondHalf.u64 & 0xFFFF; - else if(op.get_operand_lohi() == 2) - secondHalf.u64 = (secondHalf.u64>>16) & 0xFFFF; - result.u64 = firstHalf.u64; - firstHalf.u64 = firstHalf.u64 + secondHalf.u64; - set_reg(op.vec_symbol(0),firstHalf); - } else if (op.get_double_operand_type() == 3) { - // s[reg += immediate] - // reg is incremented after value is returned: the value returned is s[reg] - ptx_reg_t firstHalf; - firstHalf.u64 = get_reg(op.get_symbol()).u64; - result.u64 = firstHalf.u64; - firstHalf.u64 = firstHalf.u64 + op.get_addr_offset(); - set_reg(op.get_symbol(),firstHalf); - } - - ptx_reg_t finalResult; - memory_space *mem = NULL; - size_t size=0; - int t=0; - finalResult.u64=0; - - //complete other cases for reading from memory, such as reading from other const memory - if((op.get_addr_space() == global_space)&&(derefFlag)) { - // global memory - g[4], g[$r0] - mem = thread->get_global_memory(); - type_info_key::type_decode(opType,size,t); - mem->read(result.u32,size/8,&finalResult.u128); - thread->m_last_effective_address = result.u32; - thread->m_last_memory_space = global_space; - - if( opType == S16_TYPE || opType == S32_TYPE ) - sign_extend(finalResult,size,dstInfo); - } else if((op.get_addr_space() == shared_space)&&(derefFlag)) { - // shared memory - s[4], s[$r0] - mem = thread->m_shared_mem; - type_info_key::type_decode(opType,size,t); - mem->read(result.u32,size/8,&finalResult.u128); - thread->m_last_effective_address = result.u32; - thread->m_last_memory_space = shared_space; - - if( opType == S16_TYPE || opType == S32_TYPE ) - sign_extend(finalResult,size,dstInfo); - } else if((op.get_addr_space() == const_space)&&(derefFlag)) { - // const memory - ce0c1[4], ce0c1[$r0] - mem = thread->get_global_memory(); - type_info_key::type_decode(opType,size,t); - mem->read((result.u32 + op.get_const_mem_offset()),size/8,&finalResult.u128); - thread->m_last_effective_address = result.u32; - thread->m_last_memory_space = const_space; - if( opType == S16_TYPE || opType == S32_TYPE ) - sign_extend(finalResult,size,dstInfo); - } else if((op.get_addr_space() == local_space)&&(derefFlag)) { - // local memory - l0[4], l0[$r0] - mem = thread->m_local_mem; - type_info_key::type_decode(opType,size,t); - mem->read(result.u32,size/8,&finalResult.u128); - thread->m_last_effective_address = result.u32; - thread->m_last_memory_space = local_space; - if( opType == S16_TYPE || opType == S32_TYPE ) - sign_extend(finalResult,size,dstInfo); - } else { - finalResult = result; - } - - if((op.get_operand_neg() == true)&&(derefFlag)) { - switch( opType ) { - // Default to f32 for now, need to add support for others - case S8_TYPE: - case U8_TYPE: - case B8_TYPE: - finalResult.s8 = -finalResult.s8; - break; - case S16_TYPE: - case U16_TYPE: - case B16_TYPE: - finalResult.s16 = -finalResult.s16; - break; - case S32_TYPE: - case U32_TYPE: - case B32_TYPE: - finalResult.s32 = -finalResult.s32; - break; - case S64_TYPE: - case U64_TYPE: - case B64_TYPE: - finalResult.s64 = -finalResult.s64; - break; - case F16_TYPE: - finalResult.f16 = -finalResult.f16; - break; - case F32_TYPE: - finalResult.f32 = -finalResult.f32; - break; - case F64_TYPE: - case FF64_TYPE: - finalResult.f64 = -finalResult.f64; - break; - default: - assert(0); - } - - } - - return finalResult; - -} - -unsigned get_operand_nbits( const operand_info &op ) -{ - if ( op.is_reg() ) { - const symbol *sym = op.get_symbol(); - const type_info *typ = sym->type(); - type_info_key t = typ->get_key(); - switch( t.scalar_type() ) { - case PRED_TYPE: - return 1; - case B8_TYPE: case S8_TYPE: case U8_TYPE: - return 8; - case S16_TYPE: case U16_TYPE: case F16_TYPE: case B16_TYPE: - return 16; - case S32_TYPE: case U32_TYPE: case F32_TYPE: case B32_TYPE: - return 32; - case S64_TYPE: case U64_TYPE: case F64_TYPE: case B64_TYPE: - return 64; - default: - printf("ERROR: unknown register type\n"); - fflush(stdout); - abort(); - } - } else { - printf("ERROR: Need to implement get_operand_nbits() for currently unsupported operand_info type\n"); - fflush(stdout); - abort(); - } - - return 0; -} - -void ptx_thread_info::get_vector_operand_values( const operand_info &op, ptx_reg_t* ptx_regs, unsigned num_elements ) -{ - assert( op.is_vector() ); - assert( num_elements <= 4 ); // max 4 elements in a vector - - for (int idx = num_elements - 1; idx >= 0; --idx) { - const symbol *sym = NULL; - sym = op.vec_symbol(idx); - if( strcmp(sym->name().c_str(),"_") != 0) { - reg_map_t::iterator reg_iter = m_regs.back().find(sym); - assert( reg_iter != m_regs.back().end() ); - ptx_regs[idx] = reg_iter->second; - } - } -} - -void sign_extend( ptx_reg_t &data, unsigned src_size, const operand_info &dst ) -{ - if( !dst.is_reg() ) - return; - unsigned dst_size = get_operand_nbits( dst ); - if( src_size >= dst_size ) - return; - // src_size < dst_size - unsigned long long mask = 1; - mask <<= (src_size-1); - if( (mask & data.u64) == 0 ) { - // no need to sign extend - return; - } - // need to sign extend - mask = 1; - mask <<= dst_size-src_size; - mask -= 1; - mask <<= src_size; - data.u64 |= mask; -} - -void ptx_thread_info::set_operand_value( const operand_info &dst, const ptx_reg_t &data, unsigned type, ptx_thread_info *thread, const ptx_instruction *pI, int overflow, int carry ) -{ - thread->set_operand_value( dst, data, type, thread, pI ); - - if (dst.get_double_operand_type() == -2) - { - ptx_reg_t predValue; - - const symbol *sym = dst.vec_symbol(0); - predValue.u64 = (m_regs.back()[ sym ].u64) & ~(0x0C); - predValue.u64 |= ((overflow & 0x01)<<3); - predValue.u64 |= ((carry & 0x01)<<2); - - set_reg(sym,predValue); - } - else if (dst.get_double_operand_type() == 0) - { - //intentionally do nothing - } - else - { - printf("Unexpected double destination\n"); - assert(0); - } - -} - -void ptx_thread_info::set_operand_value( const operand_info &dst, const ptx_reg_t &data, unsigned type, ptx_thread_info *thread, const ptx_instruction *pI ) -{ - ptx_reg_t dstData; - memory_space *mem = NULL; - size_t size; - int t; - - type_info_key::type_decode(type,size,t); - - /*complete this section for other cases*/ - if(dst.get_addr_space() == undefined_space) - { - ptx_reg_t setValue; - setValue.u64 = data.u64; - - // Double destination in set instruction ($p0|$p1) - second is negation of first - if (dst.get_double_operand_type() == -1) - { - ptx_reg_t setValue2; - const symbol *name1 = dst.vec_symbol(0); - const symbol *name2 = dst.vec_symbol(1); - - if ( (type==F16_TYPE)||(type==F32_TYPE)||(type==F64_TYPE)||(type==FF64_TYPE) ) { - setValue2.f32 = (setValue.u64==0)?1.0f:0.0f; - } else { - setValue2.u32 = (setValue.u64==0)?0xFFFFFFFF:0; - } - - set_reg(name1,setValue); - set_reg(name2,setValue2); - } - - // Double destination in cvt,shr,mul,etc. instruction ($p0|$r4) - second register operand receives data, first predicate operand - // is set as $p0=($r4!=0) - // Also for Double destination in set instruction ($p0/$r1) - else if ((dst.get_double_operand_type() == -2)||(dst.get_double_operand_type() == -3)) - { - ptx_reg_t predValue; - const symbol *predName = dst.vec_symbol(0); - const symbol *regName = dst.vec_symbol(1); - predValue.u64 = 0; - - switch ( type ) { - case S8_TYPE: - if((setValue.s8 & 0x7F) == 0) - predValue.u64 |= 1; - break; - case S16_TYPE: - if((setValue.s16 & 0x7FFF) == 0) - predValue.u64 |= 1; - break; - case S32_TYPE: - if((setValue.s32 & 0x7FFFFFFF) == 0) - predValue.u64 |= 1; - break; - case S64_TYPE: - if((setValue.s64 & 0x7FFFFFFFFFFFFFFF) == 0) - predValue.u64 |= 1; - break; - case U8_TYPE: - case B8_TYPE: - if(setValue.u8 == 0) - predValue.u64 |= 1; - break; - case U16_TYPE: - case B16_TYPE: - if(setValue.u16 == 0) - predValue.u64 |= 1; - break; - case U32_TYPE: - case B32_TYPE: - if(setValue.u32 == 0) - predValue.u64 |= 1; - break; - case U64_TYPE: - case B64_TYPE: - if(setValue.u64 == 0) - predValue.u64 |= 1; - break; - case F16_TYPE: - if(setValue.f16 == 0) - predValue.u64 |= 1; - break; - case F32_TYPE: - if(setValue.f32 == 0) - predValue.u64 |= 1; - break; - case F64_TYPE: - case FF64_TYPE: - if(setValue.f64 == 0) - predValue.u64 |= 1; - break; - default: assert(0); break; - } - - - if ( (type==S8_TYPE)||(type==S16_TYPE)||(type==S32_TYPE)||(type==S64_TYPE)|| - (type==U8_TYPE)||(type==U16_TYPE)||(type==U32_TYPE)||(type==U64_TYPE)|| - (type==B8_TYPE)||(type==B16_TYPE)||(type==B32_TYPE)||(type==B64_TYPE)) { - if((setValue.u32 & (1<<(size-1))) != 0) - predValue.u64 |= 1<<1; - } - if ( type==F32_TYPE ) { - if(setValue.f32 < 0) - predValue.u64 |= 1<<1; - } - - if(dst.get_operand_lohi() == 1) - { - setValue.u64 = ((m_regs.back()[ regName ].u64) & (~(0xFFFF))) + (data.u64 & 0xFFFF); - } - else if(dst.get_operand_lohi() == 2) - { - setValue.u64 = ((m_regs.back()[ regName ].u64) & (~(0xFFFF0000))) + ((data.u64<<16) & 0xFFFF0000); - } - - set_reg(predName,predValue); - set_reg(regName,setValue); - } - else if (type == BB128_TYPE) - { - //b128 stuff here. - ptx_reg_t setValue2, setValue3, setValue4; - setValue.u64 = 0; - setValue2.u64 = 0; - setValue3.u64 = 0; - setValue4.u64 = 0; - setValue.u32 = data.u128.lowest; - setValue2.u32 = data.u128.low; - setValue3.u32 = data.u128.high; - setValue4.u32 = data.u128.highest; - - const symbol *name1, *name2, *name3, *name4 = NULL; - - name1 = dst.vec_symbol(0); - name2 = dst.vec_symbol(1); - name3 = dst.vec_symbol(2); - name4 = dst.vec_symbol(3); - - set_reg(name1,setValue); - set_reg(name2,setValue2); - set_reg(name3,setValue3); - set_reg(name4,setValue4); - } - else if (type == BB64_TYPE || type == FF64_TYPE) - { - //ptxplus version of storing 64 bit values to registers stores to two adjacent registers - ptx_reg_t setValue2; - setValue.u32 = 0; - setValue2.u32 = 0; - - setValue.u32 = data.bits.ls; - setValue2.u32 = data.bits.ms; - - const symbol *name1, *name2 = NULL; - - name1 = dst.vec_symbol(0); - name2 = dst.vec_symbol(1); - - set_reg(name1,setValue); - set_reg(name2,setValue2); - } - else - { - if(dst.get_operand_lohi() == 1) - { - setValue.u64 = ((m_regs.back()[ dst.get_symbol() ].u64) & (~(0xFFFF))) + (data.u64 & 0xFFFF); - } - else if(dst.get_operand_lohi() == 2) - { - setValue.u64 = ((m_regs.back()[ dst.get_symbol() ].u64) & (~(0xFFFF0000))) + ((data.u64<<16) & 0xFFFF0000); - } - set_reg(dst.get_symbol(),setValue); - } - } - - // global memory - g[4], g[$r0] - else if(dst.get_addr_space() == global_space) - { - dstData = thread->get_operand_value(dst, dst, type, thread, 0); - mem = thread->get_global_memory(); - type_info_key::type_decode(type,size,t); - - mem->write(dstData.u32,size/8,&data.u128,thread,pI); - thread->m_last_effective_address = dstData.u32; - thread->m_last_memory_space = global_space; - } - - // shared memory - s[4], s[$r0] - else if(dst.get_addr_space() == shared_space) - { - dstData = thread->get_operand_value(dst, dst, type, thread, 0); - mem = thread->m_shared_mem; - type_info_key::type_decode(type,size,t); - - mem->write(dstData.u32,size/8,&data.u128,thread,pI); - thread->m_last_effective_address = dstData.u32; - thread->m_last_memory_space = shared_space; - } - - // local memory - l0[4], l0[$r0] - else if(dst.get_addr_space() == local_space) - { - dstData = thread->get_operand_value(dst, dst, type, thread, 0); - mem = thread->m_local_mem; - type_info_key::type_decode(type,size,t); - - mem->write(dstData.u32,size/8,&data.u128,thread,pI); - thread->m_last_effective_address = dstData.u32; - thread->m_last_memory_space = local_space; - } - - else - { - printf("Destination stores to unknown location."); - assert(0); - } - - -} - -void ptx_thread_info::set_vector_operand_values( const operand_info &dst, - const ptx_reg_t &data1, - const ptx_reg_t &data2, - const ptx_reg_t &data3, - const ptx_reg_t &data4 ) -{ - unsigned num_elements = dst.get_vect_nelem(); - if (num_elements > 0) { - set_reg(dst.vec_symbol(0), data1); - if (num_elements > 1) { - set_reg(dst.vec_symbol(1), data2); - if (num_elements > 2) { - set_reg(dst.vec_symbol(2), data3); - if (num_elements > 3) { - set_reg(dst.vec_symbol(3), data4); - } - } - } - } - - m_last_set_operand_value = data1; -} - -#define my_abs(a) (((a)<0)?(-a):(a)) - -#define MY_MAX_I(a,b) (a > b) ? a : b -#define MY_MAX_F(a,b) isNaN(a) ? b : isNaN(b) ? a : (a > b) ? a : b - -#define MY_MIN_I(a,b) (a < b) ? a : b -#define MY_MIN_F(a,b) isNaN(a) ? b : isNaN(b) ? a : (a < b) ? a : b - -#define MY_INC_I(a,b) (a >= b) ? 0 : a+1 -#define MY_DEC_I(a,b) ((a == 0) || (a > b)) ? b : a-1 - -#define MY_CAS_I(a,b,c) (a == b) ? c : a - -#define MY_EXCH(a,b) b - -void abs_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case S16_TYPE: d.s16 = my_abs(a.s16); break; - case S32_TYPE: d.s32 = my_abs(a.s32); break; - case S64_TYPE: d.s64 = my_abs(a.s64); break; - case U16_TYPE: d.s16 = my_abs(a.u16); break; - case U32_TYPE: d.s32 = my_abs(a.u32); break; - case U64_TYPE: d.s64 = my_abs(a.u64); break; - case F32_TYPE: d.f32 = my_abs(a.f32); break; - case F64_TYPE: case FF64_TYPE: d.f64 = my_abs(a.f64); break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void addp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - //PTXPlus add instruction with carry (carry is kept in a predicate) register - ptx_reg_t src1_data, src2_data, src3_data, data; - int overflow = 0; - int carry = 0; - - const operand_info &dst = pI->dst(); //get operand info of sources and destination - const operand_info &src1 = pI->src1(); //use them to determine that they are of type 'register' - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - src3_data = thread->get_operand_value(src3, dst, i_type, thread, 1); - - unsigned rounding_mode = pI->rounding_mode(); - int orig_rm = fegetround(); - switch ( rounding_mode ) { - case RN_OPTION: break; - case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; - default: assert(0); break; - } - - //performs addition. Sets carry and overflow if needed. - //src3_data.pred&0x4 is the carry flag - switch ( i_type ) { - case S8_TYPE: - data.s64 = (src1_data.s64 & 0x0000000FF) + (src2_data.s64 & 0x0000000FF) + (src3_data.pred & 0x4); - if(((src1_data.s64 & 0x80)-(src2_data.s64 & 0x80)) == 0) {overflow=((src1_data.s64 & 0x80)-(data.s64 & 0x80))==0?0:1; } - carry = (data.u64 & 0x000000100)>>8; - break; - case S16_TYPE: - data.s64 = (src1_data.s64 & 0x00000FFFF) + (src2_data.s64 & 0x00000FFFF) + (src3_data.pred & 0x4); - if(((src1_data.s64 & 0x8000)-(src2_data.s64 & 0x8000)) == 0) {overflow=((src1_data.s64 & 0x8000)-(data.s64 & 0x8000))==0?0:1; } - carry = (data.u64 & 0x000010000)>>16; - break; - case S32_TYPE: - data.s64 = (src1_data.s64 & 0x0FFFFFFFF) + (src2_data.s64 & 0x0FFFFFFFF) + (src3_data.pred & 0x4); - if(((src1_data.s64 & 0x80000000)-(src2_data.s64 & 0x80000000)) == 0) {overflow=((src1_data.s64 & 0x80000000)-(data.s64 & 0x80000000))==0?0:1; } - carry = (data.u64 & 0x100000000)>>32; - break; - case S64_TYPE: - data.s64 = src1_data.s64 + src2_data.s64 + (src3_data.pred & 0x4); - break; - case U8_TYPE: - data.u64 = (src1_data.u64 & 0xFF) + (src2_data.u64 & 0xFF) + (src3_data.pred & 0x4); - carry = (data.u64 & 0x100)>>8; - break; - case U16_TYPE: - data.u64 = (src1_data.u64 & 0xFFFF) + (src2_data.u64 & 0xFFFF) + (src3_data.pred & 0x4); - carry = (data.u64 & 0x10000)>>16; - break; - case U32_TYPE: - data.u64 = (src1_data.u64 & 0xFFFFFFFF) + (src2_data.u64 & 0xFFFFFFFF) + (src3_data.pred & 0x4); - carry = (data.u64 & 0x100000000)>>32; - break; - case U64_TYPE: - data.s64 = src1_data.s64 + src2_data.s64 + (src3_data.pred & 0x4); - break; - case F16_TYPE: assert(0); break; - case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break; - case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break; - default: assert(0); break; - } - fesetround( orig_rm ); - - thread->set_operand_value(dst, data, i_type, thread, pI, overflow, carry ); -} - -void add_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - int overflow = 0; - int carry = 0; - - const operand_info &dst = pI->dst(); //get operand info of sources and destination - const operand_info &src1 = pI->src1(); //use them to determine that they are of type 'register' - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - unsigned rounding_mode = pI->rounding_mode(); - int orig_rm = fegetround(); - switch ( rounding_mode ) { - case RN_OPTION: break; - case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; - default: assert(0); break; - } - - //performs addition. Sets carry and overflow if needed. - switch ( i_type ) { - case S8_TYPE: - data.s64 = (src1_data.s64 & 0x0000000FF) + (src2_data.s64 & 0x0000000FF); - if(((src1_data.s64 & 0x80)-(src2_data.s64 & 0x80)) == 0) {overflow=((src1_data.s64 & 0x80)-(data.s64 & 0x80))==0?0:1; } - carry = (data.u64 & 0x000000100)>>8; - break; - case S16_TYPE: - data.s64 = (src1_data.s64 & 0x00000FFFF) + (src2_data.s64 & 0x00000FFFF); - if(((src1_data.s64 & 0x8000)-(src2_data.s64 & 0x8000)) == 0) {overflow=((src1_data.s64 & 0x8000)-(data.s64 & 0x8000))==0?0:1; } - carry = (data.u64 & 0x000010000)>>16; - break; - case S32_TYPE: - data.s64 = (src1_data.s64 & 0x0FFFFFFFF) + (src2_data.s64 & 0x0FFFFFFFF); - if(((src1_data.s64 & 0x80000000)-(src2_data.s64 & 0x80000000)) == 0) {overflow=((src1_data.s64 & 0x80000000)-(data.s64 & 0x80000000))==0?0:1; } - carry = (data.u64 & 0x100000000)>>32; - break; - case S64_TYPE: - data.s64 = src1_data.s64 + src2_data.s64; - break; - case U8_TYPE: - data.u64 = (src1_data.u64 & 0xFF) + (src2_data.u64 & 0xFF); - carry = (data.u64 & 0x100)>>8; - break; - case U16_TYPE: - data.u64 = (src1_data.u64 & 0xFFFF) + (src2_data.u64 & 0xFFFF); - carry = (data.u64 & 0x10000)>>16; - break; - case U32_TYPE: - data.u64 = (src1_data.u64 & 0xFFFFFFFF) + (src2_data.u64 & 0xFFFFFFFF); - carry = (data.u64 & 0x100000000)>>32; - break; - case U64_TYPE: - data.u64 = src1_data.u64 + src2_data.u64; - break; - case F16_TYPE: assert(0); break; - case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break; - case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break; - default: assert(0); break; - } - fesetround( orig_rm ); - - thread->set_operand_value(dst, data, i_type, thread, pI, overflow, carry ); -} - -void addc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } - -void and_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - //the way ptxplus handles predicates: 1 = false and 0 = true - if(i_type == PRED_TYPE) - data.pred = ~(~(src1_data.pred) & ~(src2_data.pred)); - else - data.u64 = src1_data.u64 & src2_data.u64; - - thread->set_operand_value(dst,data, i_type, thread, pI); -} - -void andn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - switch ( i_type ) { - case B16_TYPE: src2_data.u16 = ~src2_data.u16; break; - case B32_TYPE: src2_data.u32 = ~src2_data.u32; break; - case B64_TYPE: src2_data.u64 = ~src2_data.u64; break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - data.u64 = src1_data.u64 & src2_data.u64; - - thread->set_operand_value(dst,data, i_type, thread, pI); -} - -void bar_callback( const inst_t* inst, ptx_thread_info* thread) -{ - unsigned ctaid = thread->get_cta_uid(); - unsigned barid = inst->bar_id; - unsigned value = thread->get_reduction_value(ctaid,barid); - const ptx_instruction *pI = dynamic_cast(inst); - const operand_info &dst = pI->dst(); - ptx_reg_t data; - data.u32 = value; - thread->set_operand_value(dst,value, U32_TYPE, thread, pI); -} - -void atom_callback( const inst_t* inst, ptx_thread_info* thread) -{ - const ptx_instruction *pI = dynamic_cast(inst); - - // "Decode" the output type - unsigned to_type = pI->get_type(); - size_t size; - int t; - type_info_key::type_decode(to_type, size, t); - - // Set up operand variables - ptx_reg_t data; // d - ptx_reg_t src1_data; // a - ptx_reg_t src2_data; // b - ptx_reg_t op_result; // temp variable to hold operation result - - bool data_ready = false; - - // Get operand info of sources and destination - const operand_info &dst = pI->dst(); // d - const operand_info &src1 = pI->src1(); // a - const operand_info &src2 = pI->src2(); // b - - // Get operand values - src1_data = thread->get_operand_value(src1, src1, to_type, thread, 1); // a - if (dst.get_symbol()->type()){ - src2_data = thread->get_operand_value(src2, dst, to_type, thread, 1); // b - } else { - //This is the case whent he first argument (dest) is '_' - src2_data = thread->get_operand_value(src2, src1, to_type, thread, 1); // b - } - - // Check state space - addr_t effective_address = src1_data.u64; - memory_space_t space = pI->get_space(); - if (space == undefined_space) { - // generic space - determine space via address - if( whichspace(effective_address) == global_space ) { - effective_address = generic_to_global(effective_address); - space = global_space; - } else if( whichspace(effective_address) == shared_space ) { - unsigned smid = thread->get_hw_sid(); - effective_address = generic_to_shared(smid,effective_address); - space = shared_space; - } else { - abort(); - } - } - assert( space == global_space || space == shared_space ); - - memory_space *mem = NULL; - if(space == global_space) - mem = thread->get_global_memory(); - else if(space == shared_space) - mem = thread->m_shared_mem; - else - abort(); - - // Copy value pointed to in operand 'a' into register 'd' - // (i.e. copy src1_data to dst) - mem->read(effective_address,size/8,&data.s64); - if (dst.get_symbol()->type()){ - thread->set_operand_value(dst, data, to_type, thread, pI); // Write value into register 'd' - } - - // Get the atomic operation to be performed - unsigned m_atomic_spec = pI->get_atomic(); - - switch ( m_atomic_spec ) { - // AND - case ATOMIC_AND: - { - - switch ( to_type ) { - case B32_TYPE: - case U32_TYPE: - op_result.u32 = data.u32 & src2_data.u32; - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = data.s32 & src2_data.s32; - data_ready = true; - break; - default: - printf("Execution error: type mismatch (%x) with instruction\natom.AND only accepts b32\n", to_type); - assert(0); - break; - } - - break; - } - // OR - case ATOMIC_OR: - { - - switch ( to_type ) { - case B32_TYPE: - case U32_TYPE: - op_result.u32 = data.u32 | src2_data.u32; - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = data.s32 | src2_data.s32; - data_ready = true; - break; - default: - printf("Execution error: type mismatch (%x) with instruction\natom.OR only accepts b32\n", to_type); - assert(0); - break; - } - - break; - } - // XOR - case ATOMIC_XOR: - { - - switch ( to_type ) { - case B32_TYPE: - case U32_TYPE: - op_result.u32 = data.u32 ^ src2_data.u32; - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = data.s32 ^ src2_data.s32; - data_ready = true; - break; - default: - printf("Execution error: type mismatch (%x) with instruction\natom.XOR only accepts b32\n", to_type); - assert(0); - break; - } - - break; - } - // CAS - case ATOMIC_CAS: - { - - ptx_reg_t src3_data; - const operand_info &src3 = pI->src3(); - src3_data = thread->get_operand_value(src3, dst, to_type, thread, 1); - - switch ( to_type ) { - case B32_TYPE: - case U32_TYPE: - op_result.u32 = MY_CAS_I(data.u32, src2_data.u32, src3_data.u32); - data_ready = true; - break; - case B64_TYPE: - case U64_TYPE: - op_result.u64 = MY_CAS_I(data.u64, src2_data.u64, src3_data.u64); - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = MY_CAS_I(data.s32, src2_data.s32, src3_data.s32); - data_ready = true; - break; - default: - printf("Execution error: type mismatch (%x) with instruction\natom.CAS only accepts b32 and b64\n", to_type); - assert(0); - break; - } - - break; - } - // EXCH - case ATOMIC_EXCH: - { - switch ( to_type ) { - case B32_TYPE: - case U32_TYPE: - op_result.u32 = MY_EXCH(data.u32, src2_data.u32); - data_ready = true; - break; - case B64_TYPE: - case U64_TYPE: - op_result.u64 = MY_EXCH(data.u64, src2_data.u64); - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = MY_EXCH(data.s32, src2_data.s32); - data_ready = true; - break; - default: - printf("Execution error: type mismatch (%x) with instruction\natom.EXCH only accepts b32\n", to_type); - assert(0); - break; - } - - break; - } - // ADD - case ATOMIC_ADD: - { - - switch ( to_type ) { - case U32_TYPE: - op_result.u32 = data.u32 + src2_data.u32; - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = data.s32 + src2_data.s32; - data_ready = true; - break; - case U64_TYPE: - op_result.u64 = data.u64 + src2_data.u64; - data_ready = true; - break; - case F32_TYPE: - op_result.f32 = data.f32 + src2_data.f32; - data_ready = true; - break; - default: - printf("Execution error: type mismatch with instruction\natom.ADD only accepts u32, s32, u64, and f32\n"); - assert(0); - break; - } - - break; - } - // INC - case ATOMIC_INC: - { - switch ( to_type ) { - case U32_TYPE: - op_result.u32 = MY_INC_I(data.u32, src2_data.u32); - data_ready = true; - break; - default: - printf("Execution error: type mismatch with instruction\natom.INC only accepts u32 and s32\n"); - assert(0); - break; - } - - break; - } - // DEC - case ATOMIC_DEC: - { - switch ( to_type ) { - case U32_TYPE: - op_result.u32 = MY_DEC_I(data.u32, src2_data.u32); - data_ready = true; - break; - default: - printf("Execution error: type mismatch with instruction\natom.DEC only accepts u32 and s32\n"); - assert(0); - break; - } - - break; - } - // MIN - case ATOMIC_MIN: - { - switch ( to_type ) { - case U32_TYPE: - op_result.u32 = MY_MIN_I(data.u32, src2_data.u32); - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = MY_MIN_I(data.s32, src2_data.s32); - data_ready = true; - break; - default: - printf("Execution error: type mismatch with instruction\natom.MIN only accepts u32 and s32\n"); - assert(0); - break; - } - - break; - } - // MAX - case ATOMIC_MAX: - { - switch ( to_type ) { - case U32_TYPE: - op_result.u32 = MY_MAX_I(data.u32, src2_data.u32); - data_ready = true; - break; - case S32_TYPE: - op_result.s32 = MY_MAX_I(data.s32, src2_data.s32); - data_ready = true; - break; - default: - printf("Execution error: type mismatch with instruction\natom.MAX only accepts u32 and s32\n"); - assert(0); - break; - } - - break; - } - // DEFAULT - default: - { - assert(0); - break; - } - } - - // Write operation result into memory - // (i.e. copy src1_data to dst) - if ( data_ready ) { - mem->write(effective_address,size/8,&op_result.s64,thread,pI); - } else { - printf("Execution error: data_ready not set\n"); - assert(0); - } -} - -// atom_impl will now result in a callback being called in mem_ctrl_pop (gpu-sim.c) -void atom_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - // SYNTAX - // atom.space.operation.type d, a, b[, c]; (now read in callback) - - // obtain memory space of the operation - memory_space_t space = pI->get_space(); - - // get the memory address - const operand_info &src1 = pI->src1(); - // const operand_info &dst = pI->dst(); // not needed for effective address calculation - unsigned i_type = pI->get_type(); - ptx_reg_t src1_data; - src1_data = thread->get_operand_value(src1, src1, i_type, thread, 1); - addr_t effective_address = src1_data.u64; - - addr_t effective_address_final; - - // handle generic memory space by converting it to global - if ( space == undefined_space ) { - if( whichspace(effective_address) == global_space ) { - effective_address_final = generic_to_global(effective_address); - space = global_space; - } else if( whichspace(effective_address) == shared_space ) { - unsigned smid = thread->get_hw_sid(); - effective_address_final = generic_to_shared(smid,effective_address); - space = shared_space; - } else { - abort(); - } - } else { - assert( space == global_space || space == shared_space ); - effective_address_final = effective_address; - } - - // Check state space - assert( space == global_space || space == shared_space ); - - thread->m_last_effective_address = effective_address_final; - thread->m_last_memory_space = space; - thread->m_last_dram_callback.function = atom_callback; - thread->m_last_dram_callback.instruction = pI; -} - -void bar_impl( const ptx_instruction *pIin, ptx_thread_info *thread ) -{ - ptx_instruction * pI = const_cast(pIin); - unsigned bar_op = pI->barrier_op(); - unsigned red_op = pI->get_atomic(); - unsigned ctaid = thread->get_cta_uid(); - - switch(bar_op){ - case SYNC_OPTION: - { - if(pI->get_num_operands()>1){ - const operand_info &op0 = pI->dst(); - const operand_info &op1 = pI->src1(); - ptx_reg_t op0_data; - ptx_reg_t op1_data; - op0_data = thread->get_operand_value(op0, op0, U32_TYPE, thread, 1); - op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); - pI->set_bar_id(op0_data.u32); - pI->set_bar_count(op1_data.u32); - }else{ - const operand_info &op0 = pI->dst(); - ptx_reg_t op0_data; - op0_data = thread->get_operand_value(op0, op0, U32_TYPE, thread, 1); - pI->set_bar_id(op0_data.u32); - } - break; - } - case ARRIVE_OPTION: - { - const operand_info &op0 = pI->dst(); - const operand_info &op1 = pI->src1(); - ptx_reg_t op0_data; - ptx_reg_t op1_data; - op0_data = thread->get_operand_value(op0, op0, U32_TYPE, thread, 1); - op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); - pI->set_bar_id(op0_data.u32); - pI->set_bar_count(op1_data.u32); - break; - } - case RED_OPTION: - { - if(pI->get_num_operands()>3){ - const operand_info &op1 = pI->src1(); - const operand_info &op2 = pI->src2(); - const operand_info &op3 = pI->src3(); - ptx_reg_t op1_data; - ptx_reg_t op2_data; - ptx_reg_t op3_data; - op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); - op2_data = thread->get_operand_value(op2, op2, U32_TYPE, thread, 1); - op3_data = thread->get_operand_value(op3, op3, PRED_TYPE, thread, 1); - op3_data.u32=!(op3_data.pred & 0x0001); - pI->set_bar_id(op1_data.u32); - pI->set_bar_count(op2_data.u32); - switch(red_op){ - case ATOMIC_POPC: - thread->popc_reduction(ctaid,op1_data.u32,op3_data.u32); - break; - case ATOMIC_AND: - thread->and_reduction(ctaid,op1_data.u32,op3_data.u32); - break; - case ATOMIC_OR: - thread->or_reduction(ctaid,op1_data.u32,op3_data.u32); - break; - default: - abort(); - break; - } - }else{ - const operand_info &op1 = pI->src1(); - const operand_info &op2 = pI->src2(); - ptx_reg_t op1_data; - ptx_reg_t op2_data; - op1_data = thread->get_operand_value(op1, op1, U32_TYPE, thread, 1); - op2_data = thread->get_operand_value(op2, op2, PRED_TYPE, thread, 1); - op2_data.u32=!(op2_data.pred & 0x0001); - pI->set_bar_id(op1_data.u32); - switch(red_op){ - case ATOMIC_POPC: - thread->popc_reduction(ctaid,op1_data.u32,op2_data.u32); - break; - case ATOMIC_AND: - thread->and_reduction(ctaid,op1_data.u32,op2_data.u32); - break; - case ATOMIC_OR: - thread->or_reduction(ctaid,op1_data.u32,op2_data.u32); - break; - default: - abort(); - break; - } - } - break; - } - default: - abort(); - break; - } - - thread->m_last_dram_callback.function = bar_callback; - thread->m_last_dram_callback.instruction = pIin; -} - -void bfe_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - unsigned i_type = pI->get_type(); - unsigned msb = (i_type == U32_TYPE || i_type == S32_TYPE) ? 31 : 63; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); - ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); - ptx_reg_t c = thread->get_operand_value(src3, dst, i_type, thread, 1); - unsigned pos = b.u32 & 0xFF; - unsigned len = c.u32 & 0xFF; - unsigned d = 0; - switch (i_type) - { - case U32_TYPE: - { - unsigned mask; - d = a.u32 >> pos; - mask = 0xFFFFFFFF >> (32 - len); - d &= mask; - break; - } - case U64_TYPE: - { - unsigned long mask; - d = a.u64 >> pos; - mask = 0xFFFFFFFFFFFFFFFF >> (64 - len); - d &= mask; - break; - } - case S32_TYPE: - { - unsigned mask; - unsigned min = MY_MIN_I(pos + len - 1, msb); - unsigned sbit = len == 0 ? 0 : (a.s32 >> min) & 0x1; - d = a.s32 >> pos; - if (sbit > 0) - { - mask = 0xFFFFFFFF << len; - d |= mask; - } - else - { - mask = 0xFFFFFFFF >> (32 - len); - d &= mask; - } - break; - } - case S64_TYPE: - { - unsigned long mask; - unsigned min = MY_MIN_I(pos + len - 1, msb); - unsigned sbit = len == 0 ? 0 : (a.s64 >> min) & 0x1; - d = a.s64 >> pos; - if (sbit > 0) - { - mask = 0xFFFFFFFFFFFFFFFF << len; - d |= mask; - } - else - { - mask = 0xFFFFFFFFFFFFFFFF >> (64 - len); - d &= mask; - } - break; - } - default: - printf("Operand type not supported for BFE instruction.\n"); - abort(); - return; - } - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void bfi_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void bfind_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } - -void bra_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &target = pI->dst(); - ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); - - thread->m_branch_taken = true; - thread->set_npc(target_pc); -} - -void brx_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &target = pI->dst(); - ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); - - thread->m_branch_taken = true; - thread->set_npc(target_pc); -} - -void break_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &target = thread->pop_breakaddr(); - ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); - - thread->m_branch_taken = true; - thread->set_npc(target_pc); -} - -void breakaddr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &target = pI->dst(); - thread->push_breakaddr(target); - assert(pI->has_pred() == false); // pdom analysis cannot handle if this instruction is predicated -} - -void brev_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void brkpt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } - -void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - static unsigned call_uid_next = 1; - - const operand_info &target = pI->func_addr(); - assert( target.is_function_address() ); - const symbol *func_addr = target.get_symbol(); - function_info *target_func = func_addr->get_pc(); - if (target_func->is_pdom_set()) { - printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", target_func->get_name().c_str() ); - } else { - printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", target_func->get_name().c_str() ); - if (target_func->get_function_size() >0) - target_func->do_pdom(); - target_func->set_pdom(); - } - - // check that number of args and return match function requirements - if( pI->has_return() ^ target_func->has_return() ) { - printf("GPGPU-Sim PTX: Execution error - mismatch in number of return values between\n" - " call instruction and function declaration\n"); - abort(); - } - unsigned n_return = target_func->has_return(); - unsigned n_args = target_func->num_args(); - unsigned n_operands = pI->get_num_operands(); - - if( n_operands != (n_return+1+n_args) ) { - printf("GPGPU-Sim PTX: Execution error - mismatch in number of arguements between\n" - " call instruction and function declaration\n"); - abort(); - } - - // handle intrinsic functions - std::string fname = target_func->get_name(); - if( fname == "vprintf" ) { - gpgpusim_cuda_vprintf(pI, thread, target_func); - return; - } - -#if (CUDART_VERSION >= 5000) - //Jin: handle device runtime apis for CDP - else if(fname == "cudaGetParameterBufferV2") { - gpgpusim_cuda_getParameterBufferV2(pI, thread, target_func); - return; - } - else if(fname == "cudaLaunchDeviceV2") { - gpgpusim_cuda_launchDeviceV2(pI, thread, target_func); - return; - } - else if(fname == "cudaStreamCreateWithFlags") { - gpgpusim_cuda_streamCreateWithFlags(pI, thread, target_func); - return; - } -#endif - - // read source arguements into register specified in declaration of function - arg_buffer_list_t arg_values; - copy_args_into_buffer_list(pI, thread, target_func, arg_values); - - // record local for return value (we only support a single return value) - const symbol *return_var_src = NULL; - const symbol *return_var_dst = NULL; - if( target_func->has_return() ) { - return_var_dst = pI->dst().get_symbol(); - return_var_src = target_func->get_return_var(); - } - - gpgpu_sim *gpu = thread->get_gpu(); - unsigned callee_pc=0, callee_rpc=0; - if( gpu->simd_model() == POST_DOMINATOR ) { - thread->get_core()->get_pdom_stack_top_info(thread->get_hw_wid(),&callee_pc,&callee_rpc); - assert( callee_pc == thread->get_pc() ); - } - - thread->callstack_push(callee_pc + pI->inst_size(), callee_rpc, return_var_src, return_var_dst, call_uid_next++); - - copy_buffer_list_into_frame(thread, arg_values); - - thread->set_npc(target_func); -} - -//Ptxplus version of call instruction. Jumps to a label not a different Kernel. -void callp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - - static unsigned call_uid_next = 1; - - const operand_info &target = pI->dst(); - ptx_reg_t target_pc = thread->get_operand_value(target, target, U32_TYPE, thread, 1); - - const symbol *return_var_src = NULL; - const symbol *return_var_dst = NULL; - - gpgpu_sim *gpu = thread->get_gpu(); - unsigned callee_pc=0, callee_rpc=0; - if( gpu->simd_model() == POST_DOMINATOR ) { - thread->get_core()->get_pdom_stack_top_info(thread->get_hw_wid(),&callee_pc,&callee_rpc); - assert( callee_pc == thread->get_pc() ); - } - - thread->callstack_push_plus(callee_pc + pI->inst_size(), callee_rpc, return_var_src, return_var_dst, call_uid_next++); - thread->set_npc(target_pc); -} - -void clz_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - int max; - unsigned long long mask; - d.u64 = 0; - - switch ( i_type ) { - case B32_TYPE: - max = 32; - mask = 0x80000000; - break; - case B64_TYPE: - max = 64; - mask = 0x8000000000000000; - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - while ((d.u32 < max) && ((a.u64&mask) == 0) ) { - d.u32++; - a.u64 = a.u64 << 1; - } - - thread->set_operand_value(dst,d, B32_TYPE, thread, pI); -} - -void cnot_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - switch ( i_type ) { - case PRED_TYPE: d.pred = ((a.pred & 0x0001) == 0)?1:0; break; - case B16_TYPE: d.u16 = (a.u16 == 0)?1:0; break; - case B32_TYPE: d.u32 = (a.u32 == 0)?1:0; break; - case B64_TYPE: d.u64 = (a.u64 == 0)?1:0; break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void cos_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case F32_TYPE: - d.f32 = cos(a.f32); - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -ptx_reg_t chop( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - switch ( to_width ) { - case 8: x.mask_and(0,0xFF); break; - case 16: x.mask_and(0,0xFFFF); break; - case 32: x.mask_and(0,0xFFFFFFFF); break; - case 64: break; - default: assert(0); - } - return x; -} - -ptx_reg_t sext( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - x=chop(x,0,from_width,0,rounding_mode,saturation_mode); - switch ( from_width ) { - case 8: if ( x.get_bit(7) ) x.mask_or(0xFFFFFFFF,0xFFFFFF00);break; - case 16:if ( x.get_bit(15) ) x.mask_or(0xFFFFFFFF,0xFFFF0000);break; - case 32: if ( x.get_bit(31) ) x.mask_or(0xFFFFFFFF,0x00000000);break; - case 64: break; - default: assert(0); - } - return x; -} - -// sign extend depending on the destination register size - hack to get SobelFilter working in CUDA 4.2 -ptx_reg_t sexd( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - x=chop(x,0,from_width,0,rounding_mode,saturation_mode); - switch ( to_width ) { - case 8: if ( x.get_bit(7) ) x.mask_or(0xFFFFFFFF,0xFFFFFF00);break; - case 16:if ( x.get_bit(15) ) x.mask_or(0xFFFFFFFF,0xFFFF0000);break; - case 32: if ( x.get_bit(31) ) x.mask_or(0xFFFFFFFF,0x00000000);break; - case 64: break; - default: assert(0); - } - return x; -} - -ptx_reg_t zext( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - return chop(x,0,from_width,0,rounding_mode,saturation_mode); -} - -int saturatei(int a, int max, int min) -{ - if (a > max) a = max; - else if (a < min) a = min; - return a; -} - -unsigned int saturatei(unsigned int a, unsigned int max) -{ - if (a > max) a = max; - return a; -} - -ptx_reg_t f2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - assert( from_width == 32); - - enum cuda_math::cudaRoundMode mode = cuda_math::cudaRoundZero; - switch (rounding_mode) { - case RZI_OPTION: mode = cuda_math::cudaRoundZero; break; - case RNI_OPTION: mode = cuda_math::cudaRoundNearest; break; - case RMI_OPTION: mode = cuda_math::cudaRoundMinInf; break; - case RPI_OPTION: mode = cuda_math::cudaRoundPosInf; break; - default: break; - } - - ptx_reg_t y; - if ( to_sign == 1 ) { // convert to 64-bit number first? - int tmp = cuda_math::float2int(x.f32, mode); - if ((x.u32 & 0x7f800000) == 0) - tmp = 0; // round denorm. FP to 0 - if (saturation_mode && to_width < 32) { - tmp = saturatei(tmp, (1< max) a = max; - else if (a < min) a = min; - return a; -} - -ptx_reg_t d2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - assert( from_width == 64); - - double tmp; - switch (rounding_mode) { - case RZI_OPTION: tmp = trunc(x.f64); break; - case RNI_OPTION: tmp = nearbyint(x.f64); break; - case RMI_OPTION: tmp = floor(x.f64); break; - case RPI_OPTION: tmp = ceil(x.f64); break; - default: tmp = x.f64; break; - } - - ptx_reg_t y; - if ( to_sign == 1 ) { - tmp = saturated2i(tmp, ((1<<(to_width - 1)) - 1), (1<<(to_width - 1)) ); - switch ( to_width ) { - case 8: y.s8 = (char)tmp; break; - case 16: y.s16 = (short)tmp; break; - case 32: y.s32 = (int)tmp; break; - case 64: y.s64 = (long long)tmp; break; - default: assert(0); break; - } - } else if ( to_sign == 0 ) { - tmp = saturated2i(tmp, ((1<<(to_width - 1)) - 1), 0); - switch ( to_width ) { - case 8: y.u8 = (unsigned char)tmp; break; - case 16: y.u16 = (unsigned short)tmp; break; - case 32: y.u32 = (unsigned int)tmp; break; - case 64: y.u64 = (unsigned long long)tmp; break; - default: assert(0); break; - } - } else { - switch ( to_width ) { - case 16: assert(0); break; - case 32: - y.f32 = x.f64; - break; - case 64: - y.f64 = x.f64; // should be handled by d2d - break; - default: assert(0); break; - } - } - return y; -} - -ptx_reg_t s2f( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - ptx_reg_t y; - - if (from_width < 64) { // 32-bit conversion - y = sext(x,from_width,32,0,rounding_mode,saturation_mode); - - switch ( to_width ) { - case 16: assert(0); break; - case 32: - switch (rounding_mode) { - case RZ_OPTION: y.f32 = cuda_math::__int2float_rz(y.s32); break; - case RN_OPTION: y.f32 = cuda_math::__int2float_rn(y.s32); break; - case RM_OPTION: y.f32 = cuda_math::__int2float_rd(y.s32); break; - case RP_OPTION: y.f32 = cuda_math::__int2float_ru(y.s32); break; - default: break; - } - break; - case 64: y.f64 = y.s32; break; // no rounding needed - default: assert(0); break; - } - } else { - switch ( to_width ) { - case 16: assert(0); break; - case 32: - switch (rounding_mode) { - case RZ_OPTION: y.f32 = cuda_math::__ll2float_rz(y.s64); break; - case RN_OPTION: y.f32 = cuda_math::__ll2float_rn(y.s64); break; - case RM_OPTION: y.f32 = cuda_math::__ll2float_rd(y.s64); break; - case RP_OPTION: y.f32 = cuda_math::__ll2float_ru(y.s64); break; - default: break; - } - break; - case 64: y.f64 = y.s64; break; // no internal implementation found - default: assert(0); break; - } - } - - // saturating an integer to 1 or 0? - return y; -} - -ptx_reg_t u2f( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - ptx_reg_t y; - - if (from_width < 64) { // 32-bit conversion - y = zext(x,from_width,32,0,rounding_mode,saturation_mode); - - switch ( to_width ) { - case 16: assert(0); break; - case 32: - switch (rounding_mode) { - case RZ_OPTION: y.f32 = cuda_math::__uint2float_rz(y.u32); break; - case RN_OPTION: y.f32 = cuda_math::__uint2float_rn(y.u32); break; - case RM_OPTION: y.f32 = cuda_math::__uint2float_rd(y.u32); break; - case RP_OPTION: y.f32 = cuda_math::__uint2float_ru(y.u32); break; - default: break; - } - break; - case 64: y.f64 = y.u32; break; // no rounding needed - default: assert(0); break; - } - } else { - switch ( to_width ) { - case 16: assert(0); break; - case 32: - switch (rounding_mode) { - case RZ_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; - case RN_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; - case RM_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; - case RP_OPTION: y.f32 = cuda_math::__ull2float_rn(y.u64); break; - default: break; - } - break; - case 64: y.f64 = y.u64; break; // no internal implementation found - default: assert(0); break; - } - } - - // saturating an integer to 1 or 0? - return y; -} - -ptx_reg_t f2f( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - ptx_reg_t y; - switch ( rounding_mode ) { - case RZI_OPTION: - y.f32 = truncf(x.f32); - break; - case RNI_OPTION: -#if CUDART_VERSION >= 3000 - y.f32 = nearbyintf(x.f32); -#else - y.f32 = cuda_math::__internal_nearbyintf(x.f32); -#endif - break; - case RMI_OPTION: - if ((x.u32 & 0x7f800000) == 0) { - y.u32 = x.u32 & 0x80000000; // round denorm. FP to 0, keeping sign - } else { - y.f32 = floorf(x.f32); - } - break; - case RPI_OPTION: - if ((x.u32 & 0x7f800000) == 0) { - y.u32 = x.u32 & 0x80000000; // round denorm. FP to 0, keeping sign - } else { - y.f32 = ceilf(x.f32); - } - break; - default: - if ((x.u32 & 0x7f800000) == 0) { - y.u32 = x.u32 & 0x80000000; // round denorm. FP to 0, keeping sign - } else { - y.f32 = x.f32; - } - break; - } -#if CUDART_VERSION >= 3000 - if (isnanf(y.f32)) -#else - if (cuda_math::__cuda___isnanf(y.f32)) -#endif - { - y.u32 = 0x7fffffff; - } else if (saturation_mode) { - y.f32 = cuda_math::__saturatef(y.f32); - } - - return y; -} - -ptx_reg_t d2d( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, int rounding_mode, int saturation_mode ) -{ - ptx_reg_t y; - switch ( rounding_mode ) { - case RZI_OPTION: - y.f64 = trunc(x.f64); - break; - case RNI_OPTION: -#if CUDART_VERSION >= 3000 - y.f64 = nearbyint(x.f64); -#else - y.f64 = cuda_math::__internal_nearbyintf(x.f64); -#endif - break; - case RMI_OPTION: - y.f64 = floor(x.f64); - break; - case RPI_OPTION: - y.f64 = ceil(x.f64); - break; - default: - y.f64 = x.f64; - break; - } - if (std::isnan(y.f64)) { - y.u64 = 0xfff8000000000000ull; - } else if (saturation_mode) { - y.f64 = cuda_math::__saturatef(y.f64); - } - return y; -} - -ptx_reg_t (*g_cvt_fn[11][11])( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, - int rounding_mode, int saturation_mode ) = { - { NULL, sext, sext, sext, NULL, sext, sext, sext, s2f, s2f, s2f}, - { chop, NULL, sext, sext, chop, NULL, sext, sext, s2f, s2f, s2f}, - { chop, sexd, NULL, sext, chop, chop, NULL, sext, s2f, s2f, s2f}, - { chop, chop, chop, NULL, chop, chop, chop, NULL, s2f, s2f, s2f}, - { NULL, zext, zext, zext, NULL, zext, zext, zext, u2f, u2f, u2f}, - { chop, NULL, zext, zext, chop, NULL, zext, zext, u2f, u2f, u2f}, - { chop, chop, NULL, zext, chop, chop, NULL, zext, u2f, u2f, u2f}, - { chop, chop, chop, NULL, chop, chop, chop, NULL, u2f, u2f, u2f}, - { f2x , f2x , f2x , f2x , f2x , f2x , f2x , f2x , NULL,f2x, f2x}, - { f2x , f2x , f2x , f2x , f2x , f2x , f2x , f2x , f2x, f2f, f2x}, - { d2x , d2x , d2x , d2x , d2x , d2x , d2x , d2x , d2x, d2x, d2d} -}; - -void ptx_round(ptx_reg_t& data, int rounding_mode, int type) -{ - if (rounding_mode == RN_OPTION) { - return; - } - switch ( rounding_mode ) { - case RZI_OPTION: - switch ( type ) { - case S8_TYPE: - case S16_TYPE: - case S32_TYPE: - case S64_TYPE: - case U8_TYPE: - case U16_TYPE: - case U32_TYPE: - case U64_TYPE: - printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; - case F32_TYPE: - data.f32 = truncf(data.f32); - break; - case F64_TYPE: - case FF64_TYPE: - if (data.f64 < 0) data.f64 = ceil(data.f64); //negative - else data.f64 = floor(data.f64); //positive - break; - default: assert(0); break; - } - break; - case RNI_OPTION: - switch ( type ) { - case S8_TYPE: - case S16_TYPE: - case S32_TYPE: - case S64_TYPE: - case U8_TYPE: - case U16_TYPE: - case U32_TYPE: - case U64_TYPE: - printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; - case F32_TYPE: -#if CUDART_VERSION >= 3000 - data.f32 = nearbyintf(data.f32); -#else - data.f32 = cuda_math::__cuda_nearbyintf(data.f32); -#endif - break; - case F64_TYPE: case FF64_TYPE: data.f64 = round(data.f64); break; - default: assert(0); break; - } - break; - case RMI_OPTION: - switch ( type ) { - case S8_TYPE: - case S16_TYPE: - case S32_TYPE: - case S64_TYPE: - case U8_TYPE: - case U16_TYPE: - case U32_TYPE: - case U64_TYPE: - printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; - case F32_TYPE: - data.f32 = floorf(data.f32); - break; - case F64_TYPE: case FF64_TYPE: data.f64 = floor(data.f64); break; - default: assert(0); break; - } - break; - case RPI_OPTION: - switch ( type ) { - case S8_TYPE: - case S16_TYPE: - case S32_TYPE: - case S64_TYPE: - case U8_TYPE: - case U16_TYPE: - case U32_TYPE: - case U64_TYPE: - printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; - case F32_TYPE: data.f32 = ceilf(data.f32); break; - case F64_TYPE: case FF64_TYPE: data.f64 = ceil(data.f64); break; - default: assert(0); break; - } - break; - default: break; - } - - if (type == F32_TYPE) { -#if CUDART_VERSION >= 3000 - if (isnanf(data.f32)) -#else - if (cuda_math::__cuda___isnanf(data.f32)) -#endif - { - data.u32 = 0x7fffffff; - } - } - if ((type == F64_TYPE)||(type == FF64_TYPE)) { - if (std::isnan(data.f64)) { - data.u64 = 0xfff8000000000000ull; - } - } -} - -void ptx_saturate(ptx_reg_t& data, int saturation_mode, int type) -{ - if (!saturation_mode) { - return; - } - switch ( type ) { - case S8_TYPE: - case S16_TYPE: - case S32_TYPE: - case S64_TYPE: - case U8_TYPE: - case U16_TYPE: - case U32_TYPE: - case U64_TYPE: - printf("Trying to clamp an integer to 1??\n"); assert(0); break; - case F16_TYPE: assert(0); break; - case F32_TYPE: - if (data.f32 > 1.0f) data.f32 = 1.0f; //negative - if (data.f32 < 0.0f) data.f32 = 0.0f; //positive - break; - case F64_TYPE: - case FF64_TYPE: - if (data.f64 > 1.0f) data.f64 = 1.0f; //negative - if (data.f64 < 0.0f) data.f64 = 0.0f; //positive - break; - default: assert(0); break; - } - -} - -void cvt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - unsigned to_type = pI->get_type(); - unsigned from_type = pI->get_type2(); - unsigned rounding_mode = pI->rounding_mode(); - unsigned saturation_mode = pI->saturation_mode(); - - if ( to_type == F16_TYPE || from_type == F16_TYPE ) - abort(); - - int to_sign, from_sign; - size_t from_width, to_width; - unsigned src_fmt = type_info_key::type_decode(from_type, from_width, from_sign); - unsigned dst_fmt = type_info_key::type_decode(to_type, to_width, to_sign); - - ptx_reg_t data = thread->get_operand_value(src1, dst, from_type, thread, 1); - - if(pI->is_neg()){ - - switch( from_type ) { - // Default to f32 for now, need to add support for others - case S8_TYPE: - case U8_TYPE: - case B8_TYPE: - data.s8 = -data.s8; - break; - case S16_TYPE: - case U16_TYPE: - case B16_TYPE: - data.s16 = -data.s16; - break; - case S32_TYPE: - case U32_TYPE: - case B32_TYPE: - data.s32 = -data.s32; - break; - case S64_TYPE: - case U64_TYPE: - case B64_TYPE: - data.s64 = -data.s64; - break; - case F16_TYPE: - data.f16 = -data.f16; - break; - case F32_TYPE: - data.f32 = -data.f32; - break; - case F64_TYPE: - case FF64_TYPE: - data.f64 = -data.f64; - break; - default: - assert(0); - } - - } - - - if ( g_cvt_fn[src_fmt][dst_fmt] != NULL ) { - ptx_reg_t result = g_cvt_fn[src_fmt][dst_fmt](data,from_width,to_width,to_sign, rounding_mode, saturation_mode); - data = result; - } - - thread->set_operand_value(dst, data, to_type, thread, pI ); -} - -void cvta_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - memory_space_t space = pI->get_space(); - bool to_non_generic = pI->is_to(); - - unsigned i_type = pI->get_type(); - ptx_reg_t from_addr = thread->get_operand_value(src1,dst,i_type,thread,1); - addr_t from_addr_hw = (addr_t)from_addr.u64; - addr_t to_addr_hw = 0; - unsigned smid = thread->get_hw_sid(); - unsigned hwtid = thread->get_hw_tid(); - - if( to_non_generic ) { - switch( space.get_type() ) { - case shared_space: to_addr_hw = generic_to_shared( smid, from_addr_hw ); break; - case local_space: to_addr_hw = generic_to_local( smid, hwtid, from_addr_hw ); break; - case global_space: to_addr_hw = generic_to_global(from_addr_hw ); break; - default: abort(); - } - } else { - switch( space.get_type() ) { - case shared_space: to_addr_hw = shared_to_generic( smid, from_addr_hw ); break; - case local_space: to_addr_hw = local_to_generic( smid, hwtid, from_addr_hw ) - + thread->get_local_mem_stack_pointer(); break; // add stack ptr here so that it can be passed as a pointer at function call - case global_space: to_addr_hw = global_to_generic( from_addr_hw ); break; - default: abort(); - } - } - - ptx_reg_t to_addr; - to_addr.u64 = to_addr_hw; - thread->set_reg(dst.get_symbol(),to_addr); -} - -void div_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - - ptx_reg_t src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - ptx_reg_t src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - switch ( i_type ) { - case S8_TYPE: - data.s8 = src1_data.s8 / src2_data.s8 ; break; - case S16_TYPE: - data.s16 = src1_data.s16 / src2_data.s16; break; - case S32_TYPE: - data.s32 = src1_data.s32 / src2_data.s32; break; - case S64_TYPE: - data.s64 = src1_data.s64 / src2_data.s64; break; - case U8_TYPE: - data.u8 = src1_data.u8 / src2_data.u8 ; break; - case U16_TYPE: - data.u16 = src1_data.u16 / src2_data.u16; break; - case U32_TYPE: - data.u32 = src1_data.u32 / src2_data.u32; break; - case U64_TYPE: - data.u64 = src1_data.u64 / src2_data.u64; break; - case B8_TYPE: - data.u8 = src1_data.u8 / src2_data.u8 ; break; - case B16_TYPE: - data.u16 = src1_data.u16 / src2_data.u16; break; - case B32_TYPE: - data.u32 = src1_data.u32 / src2_data.u32; break; - case B64_TYPE: - data.u64 = src1_data.u64 / src2_data.u64; break; - case F16_TYPE: assert(0); break; - case F32_TYPE: data.f32 = src1_data.f32 / src2_data.f32; break; - case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 / src2_data.f64; break; - default: assert(0); break; - } - thread->set_operand_value(dst,data, i_type, thread,pI); -} - -void ex2_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case F32_TYPE: - data.f32 = cuda_math::__powf(2.0, src1_data.f32); - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,data, i_type, thread,pI); -} - -void exit_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - thread->set_done(); - thread->exitCore(); - thread->registerExit(); -} - -void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry = false ); - -void fma_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - mad_def(pI,thread); -} - -void isspacep_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a; - bool t=false; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - memory_space_t space = pI->get_space(); - - a = thread->get_reg(src1.get_symbol()); - addr_t addr = (addr_t)a.u64; - unsigned smid = thread->get_hw_sid(); - unsigned hwtid = thread->get_hw_tid(); - - switch( space.get_type() ) { - case shared_space: t = isspace_shared( smid, addr ); - case local_space: t = isspace_local( smid, hwtid, addr ); - case global_space: t = isspace_global( addr ); - default: abort(); - } - - ptx_reg_t p; - p.pred = t?1:0; - - thread->set_reg(dst.get_symbol(),p); -} - -void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand_info &op, memory_space *&mem, addr_t &addr) -{ - unsigned smid = thread->get_hw_sid(); - unsigned hwtid = thread->get_hw_tid(); - - if( space == param_space_unclassified ) { - // need to op to determine whether it refers to a kernel param or local param - const symbol *s = op.get_symbol(); - const type_info *t = s->type(); - type_info_key ti = t->get_key(); - if( ti.is_param_kernel() ) - space = param_space_kernel; - else if( ti.is_param_local() ) { - space = param_space_local; - } else { - printf("GPGPU-Sim PTX: ERROR ** cannot resolve .param space for '%s'\n", s->name().c_str() ); - abort(); - } - } - switch ( space.get_type() ) { - case global_space: mem = thread->get_global_memory(); break; - case param_space_local: - case local_space: - mem = thread->m_local_mem; - addr += thread->get_local_mem_stack_pointer(); - break; - case tex_space: mem = thread->get_tex_memory(); break; - case surf_space: mem = thread->get_surf_memory(); break; - case param_space_kernel: mem = thread->get_param_memory(); break; - case shared_space: mem = thread->m_shared_mem; break; - case const_space: mem = thread->get_global_memory(); break; - case generic_space: - if( thread->get_ptx_version().ver() >= 2.0 ) { - // convert generic address to memory space address - space = whichspace(addr); - switch ( space.get_type() ) { - case global_space: mem = thread->get_global_memory(); addr = generic_to_global(addr); break; - case local_space: mem = thread->m_local_mem; addr = generic_to_local(smid,hwtid,addr); break; - case shared_space: mem = thread->m_shared_mem; addr = generic_to_shared(smid,addr); break; - default: abort(); - } - } else { - abort(); - } - break; - case param_space_unclassified: - case undefined_space: - default: - abort(); - } -} - -void ld_exec( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned type = pI->get_type(); - - ptx_reg_t src1_data = thread->get_operand_value(src1, dst, type, thread, 1); - ptx_reg_t data; - memory_space_t space = pI->get_space(); - unsigned vector_spec = pI->get_vector(); - - memory_space *mem = NULL; - addr_t addr = src1_data.u32; - - decode_space(space,thread,src1,mem,addr); - - size_t size; - int t; - data.u64=0; - type_info_key::type_decode(type,size,t); - if (!vector_spec) { - mem->read(addr,size/8,&data.s64); - if( type == S16_TYPE || type == S32_TYPE ) - sign_extend(data,size,dst); - thread->set_operand_value(dst,data, type, thread, pI); - } else { - ptx_reg_t data1, data2, data3, data4; - mem->read(addr,size/8,&data1.s64); - mem->read(addr+size/8,size/8,&data2.s64); - if (vector_spec != V2_TYPE) { //either V3 or V4 - mem->read(addr+2*size/8,size/8,&data3.s64); - if (vector_spec != V3_TYPE) { //v4 - mem->read(addr+3*size/8,size/8,&data4.s64); - thread->set_vector_operand_values(dst,data1,data2,data3,data4); - } else //v3 - thread->set_vector_operand_values(dst,data1,data2,data3,data3); - } else //v2 - thread->set_vector_operand_values(dst,data1,data2,data2,data2); - } - thread->m_last_effective_address = addr; - thread->m_last_memory_space = space; -} - -void ld_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ld_exec(pI,thread); -} -void ldu_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ld_exec(pI,thread); -} - -void lg2_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case F32_TYPE: - d.f32 = log(a.f32)/log(2); - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void mad24_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - ptx_reg_t d, t; - - unsigned i_type = pI->get_type(); - ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); - ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); - ptx_reg_t c = thread->get_operand_value(src3, dst, i_type, thread, 1); - - unsigned sat_mode = pI->saturation_mode(); - - assert( !pI->is_wide() ); - - switch ( i_type ) { - case S32_TYPE: - t.s64 = a.s32 * b.s32; - if ( pI->is_hi() ) { - d.s64 = (t.s64>>16) + c.s32; - if ( sat_mode ) { - if ( d.s64 > (int)0x7FFFFFFF ) - d.s64 = (int)0x7FFFFFFF; - else if ( d.s64 < (int)0x80000000 ) - d.s64 = (int)0x80000000; - } - } else if ( pI->is_lo() ) d.s64 = t.s32 + c.s32; - else assert(0); - break; - case U32_TYPE: - t.u64 = a.u32 * b.u32; - if ( pI->is_hi() ) d.u64 = (t.u64>>16) + c.u32; - else if ( pI->is_lo() ) d.u64 = t.u32 + c.u32; - else assert(0); - break; - default: - assert(0); - break; - } - - thread->set_operand_value(dst, d, i_type, thread, pI); -} - -void mad_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - mad_def(pI, thread, false); -} - -void madp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - mad_def(pI, thread, true); -} - -void madc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - mad_def(pI, thread, true); -} - -void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry ) -{ - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - ptx_reg_t d, t; - - int carry=0; - int overflow=0; - - unsigned i_type = pI->get_type(); - ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); - ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); - ptx_reg_t c = thread->get_operand_value(src3, dst, i_type, thread, 1); - - // take the carry bit, it should be the 4th operand - ptx_reg_t carry_bit; - carry_bit.u64 = 0; - if (use_carry) { - const operand_info &carry = pI->operand_lookup(4); - carry_bit = thread->get_operand_value(carry, dst, PRED_TYPE, thread, 0); - carry_bit.pred &= 0x4; - carry_bit.pred >>=2; - } - - unsigned rounding_mode = pI->rounding_mode(); - - switch ( i_type ) { - case S16_TYPE: - t.s32 = a.s16 * b.s16; - if ( pI->is_wide() ) d.s32 = t.s32 + c.s32 + carry_bit.pred; - else if ( pI->is_hi() ) d.s16 = (t.s32>>16) + c.s16 + carry_bit.pred; - else if ( pI->is_lo() ) d.s16 = t.s16 + c.s16 + carry_bit.pred; - else assert(0); - carry = ((long long int)(t.s32 + c.s32 + carry_bit.pred)&0x100000000)>>32; - break; - case S32_TYPE: - t.s64 = a.s32 * b.s32; - if ( pI->is_wide() ) d.s64 = t.s64 + c.s64 + carry_bit.pred; - else if ( pI->is_hi() ) d.s32 = (t.s64>>32) + c.s32 + carry_bit.pred; - else if ( pI->is_lo() ) d.s32 = t.s32 + c.s32 + carry_bit.pred; - else assert(0); - break; - case S64_TYPE: - t.s64 = a.s64 * b.s64; - assert( !pI->is_wide() ); - assert( !pI->is_hi() ); - assert( use_carry == false); - if ( pI->is_lo() ) d.s64 = t.s64 + c.s64 + carry_bit.pred; - else assert(0); - break; - case U16_TYPE: - t.u32 = a.u16 * b.u16; - if ( pI->is_wide() ) d.u32 = t.u32 + c.u32 + carry_bit.pred; - else if ( pI->is_hi() ) d.u16 = (t.u32 + c.u16 + carry_bit.pred)>>16; - else if ( pI->is_lo() ) d.u16 = t.u16 + c.u16 + carry_bit.pred; - else assert(0); - carry = ((long long int)((long long int)t.u32 + c.u32 + carry_bit.pred)&0x100000000)>>32; - break; - case U32_TYPE: - t.u64 = a.u32 * b.u32; - if ( pI->is_wide() ) d.u64 = t.u64 + c.u64 + carry_bit.pred; - else if ( pI->is_hi() ) d.u32 = (t.u64 + c.u32 + carry_bit.pred)>>32; - else if ( pI->is_lo() ) d.u32 = t.u32 + c.u32 + carry_bit.pred; - else assert(0); - break; - case U64_TYPE: - t.u64 = a.u64 * b.u64; - assert( !pI->is_wide() ); - assert( !pI->is_hi() ); - assert( use_carry == false); - if ( pI->is_lo() ) d.u64 = t.u64 + c.u64 + carry_bit.pred; - else assert(0); - break; - case F16_TYPE: - assert(0); - break; - case F32_TYPE: { - assert( use_carry == false); - int orig_rm = fegetround(); - switch ( rounding_mode ) { - case RN_OPTION: break; - case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; - default: assert(0); break; - } - d.f32 = a.f32 * b.f32 + c.f32; - if ( pI->saturation_mode() ) { - if ( d.f32 < 0 ) d.f32 = 0; - else if ( d.f32 > 1.0f ) d.f32 = 1.0f; - } - fesetround( orig_rm ); - break; - } - case F64_TYPE: case FF64_TYPE: { - assert( use_carry == false); - int orig_rm = fegetround(); - switch ( rounding_mode ) { - case RN_OPTION: break; - case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; - default: assert(0); break; - } - d.f64 = a.f64 * b.f64 + c.f64; - if ( pI->saturation_mode() ) { - if ( d.f64 < 0 ) d.f64 = 0; - else if ( d.f64 > 1.0f ) d.f64 = 1.0; - } - fesetround( orig_rm ); - break; - } - default: - assert(0); - break; - } - thread->set_operand_value(dst, d, i_type, thread, pI, overflow, carry); -} - -bool isNaN(float x) -{ - return std::isnan(x); -} - -bool isNaN(double x) -{ - return std::isnan(x); -} - -void max_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - b = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - switch ( i_type ) { - case U16_TYPE: d.u16 = MY_MAX_I(a.u16,b.u16); break; - case U32_TYPE: d.u32 = MY_MAX_I(a.u32,b.u32); break; - case U64_TYPE: d.u64 = MY_MAX_I(a.u64,b.u64); break; - case S16_TYPE: d.s16 = MY_MAX_I(a.s16,b.s16); break; - case S32_TYPE: d.s32 = MY_MAX_I(a.s32,b.s32); break; - case S64_TYPE: d.s64 = MY_MAX_I(a.s64,b.s64); break; - case F32_TYPE: d.f32 = MY_MAX_F(a.f32,b.f32); break; - case F64_TYPE: case FF64_TYPE: d.f64 = MY_MAX_F(a.f64,b.f64); break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void membar_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - // handled by timing simulator -} - -void min_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - b = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - switch ( i_type ) { - case U16_TYPE: d.u16 = MY_MIN_I(a.u16,b.u16); break; - case U32_TYPE: d.u32 = MY_MIN_I(a.u32,b.u32); break; - case U64_TYPE: d.u64 = MY_MIN_I(a.u64,b.u64); break; - case S16_TYPE: d.s16 = MY_MIN_I(a.s16,b.s16); break; - case S32_TYPE: d.s32 = MY_MIN_I(a.s32,b.s32); break; - case S64_TYPE: d.s64 = MY_MIN_I(a.s64,b.s64); break; - case F32_TYPE: d.f32 = MY_MIN_F(a.f32,b.f32); break; - case F64_TYPE: case FF64_TYPE: d.f64 = MY_MIN_F(a.f64,b.f64); break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void mov_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - unsigned i_type = pI->get_type(); - - if( (src1.is_vector() || dst.is_vector()) && (i_type != BB64_TYPE) && (i_type != BB128_TYPE) && (i_type != FF64_TYPE) ) { - // pack or unpack operation - unsigned nbits_to_move; - ptx_reg_t tmp_bits; - - switch( pI->get_type() ) { - case B16_TYPE: nbits_to_move = 16; break; - case B32_TYPE: nbits_to_move = 32; break; - case B64_TYPE: nbits_to_move = 64; break; - default: printf("Execution error: mov pack/unpack with unsupported type qualifier\n"); assert(0); break; - } - - if( src1.is_vector() ) { - unsigned nelem = src1.get_vect_nelem(); - ptx_reg_t v[4]; - thread->get_vector_operand_values(src1, v, nelem ); - - unsigned bits_per_src_elem = nbits_to_move / nelem; - for( unsigned i=0; i < nelem; i++ ) { - switch(bits_per_src_elem) { - case 8: tmp_bits.u64 |= ((unsigned long long)(v[i].u8) << (8*i)); break; - case 16: tmp_bits.u64 |= ((unsigned long long)(v[i].u16) << (16*i)); break; - case 32: tmp_bits.u64 |= ((unsigned long long)(v[i].u32) << (32*i)); break; - default: printf("Execution error: mov pack/unpack with unsupported source/dst size ratio (src)\n"); assert(0); break; - } - } - } else { - data = thread->get_operand_value(src1, dst, i_type, thread, 1); - - switch( pI->get_type() ) { - case B16_TYPE: tmp_bits.u16 = data.u16; break; - case B32_TYPE: tmp_bits.u32 = data.u32; break; - case B64_TYPE: tmp_bits.u64 = data.u64; break; - default: assert(0); break; - } - } - - if( dst.is_vector() ) { - unsigned nelem = dst.get_vect_nelem(); - ptx_reg_t v[4]; - unsigned bits_per_dst_elem = nbits_to_move / nelem; - for( unsigned i=0; i < nelem; i++ ) { - switch(bits_per_dst_elem) { - case 8: v[i].u8 = (tmp_bits.u64 >> (8*i)) & ((unsigned long long) 0xFF); break; - case 16: v[i].u16 = (tmp_bits.u64 >> (16*i)) & ((unsigned long long) 0xFFFF); break; - case 32: v[i].u32 = (tmp_bits.u64 >> (32*i)) & ((unsigned long long) 0xFFFFFFFF); break; - default: - printf("Execution error: mov pack/unpack with unsupported source/dst size ratio (dst)\n"); - assert(0); - break; - } - } - thread->set_vector_operand_values(dst,v[0],v[1],v[2],v[3]); - } else { - thread->set_operand_value(dst,tmp_bits, i_type, thread, pI); - } - } else if (i_type == PRED_TYPE and src1.is_literal() == true) { - // in ptx, literal input translate to predicate as 0 = false and 1 = true - // we have adopted the opposite to simplify implementation of zero flags in ptxplus - data = thread->get_operand_value(src1, dst, i_type, thread, 1); - - ptx_reg_t finaldata; - finaldata.pred = (data.u32 == 0)? 1 : 0; // setting zero-flag in predicate - thread->set_operand_value(dst, finaldata, i_type, thread, pI); - } else { - - data = thread->get_operand_value(src1, dst, i_type, thread, 1); - - thread->set_operand_value(dst, data, i_type, thread, pI); - - } -} - -void mul24_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - //src1_data = srcOperandModifiers(src1_data, src1, dst, i_type, thread); - //src2_data = srcOperandModifiers(src2_data, src2, dst, i_type, thread); - - src1_data.mask_and(0,0x00FFFFFF); - src2_data.mask_and(0,0x00FFFFFF); - - switch ( i_type ) { - case S32_TYPE: - if( src1_data.get_bit(23) ) - src1_data.mask_or(0xFFFFFFFF,0xFF000000); - if( src2_data.get_bit(23) ) - src2_data.mask_or(0xFFFFFFFF,0xFF000000); - data.s64 = src1_data.s64 * src2_data.s64; - break; - case U32_TYPE: - data.u64 = src1_data.u64 * src2_data.u64; - break; - default: - printf("GPGPU-Sim PTX: Execution error - type mismatch with instruction\n"); - assert(0); - break; - } - - if ( pI->is_hi() ) { - data.u64 = data.u64 >> 16; - data.mask_and(0,0xFFFFFFFF); - } else if (pI->is_lo()) { - data.mask_and(0,0xFFFFFFFF); - } - - thread->set_operand_value(dst, data, i_type, thread, pI); -} - -void mul_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - ptx_reg_t d, t; - - unsigned i_type = pI->get_type(); - ptx_reg_t a = thread->get_operand_value(src1, dst, i_type, thread, 1); - ptx_reg_t b = thread->get_operand_value(src2, dst, i_type, thread, 1); - - unsigned rounding_mode = pI->rounding_mode(); - - switch ( i_type ) { - case S16_TYPE: - t.s32 = ((int)a.s16) * ((int)b.s16); - if ( pI->is_wide() ) d.s32 = t.s32; - else if ( pI->is_hi() ) d.s16 = (t.s32>>16); - else if ( pI->is_lo() ) d.s16 = t.s16; - else assert(0); - break; - case S32_TYPE: - t.s64 = ((long long)a.s32) * ((long long)b.s32); - if ( pI->is_wide() ) d.s64 = t.s64; - else if ( pI->is_hi() ) d.s32 = (t.s64>>32); - else if ( pI->is_lo() ) d.s32 = t.s32; - else assert(0); - break; - case S64_TYPE: - t.s64 = a.s64 * b.s64; - assert( !pI->is_wide() ); - assert( !pI->is_hi() ); - if ( pI->is_lo() ) d.s64 = t.s64; - else assert(0); - break; - case U16_TYPE: - t.u32 = ((unsigned)a.u16) * ((unsigned)b.u16); - if ( pI->is_wide() ) d.u32 = t.u32; - else if ( pI->is_lo() ) d.u16 = t.u16; - else if ( pI->is_hi() ) d.u16 = (t.u32>>16); - else assert(0); - break; - case U32_TYPE: - t.u64 = ((unsigned long long)a.u32) * ((unsigned long long)b.u32); - if ( pI->is_wide() ) d.u64 = t.u64; - else if ( pI->is_lo() ) d.u32 = t.u32; - else if ( pI->is_hi() ) d.u32 = (t.u64>>32); - else assert(0); - break; - case U64_TYPE: - t.u64 = a.u64 * b.u64; - assert( !pI->is_wide() ); - assert( !pI->is_hi() ); - if ( pI->is_lo() ) d.u64 = t.u64; - else assert(0); - break; - case F16_TYPE: - assert(0); - break; - case F32_TYPE: { - int orig_rm = fegetround(); - switch ( rounding_mode ) { - case RN_OPTION: break; - case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; - default: assert(0); break; - } - - d.f32 = a.f32 * b.f32; - - if ( pI->saturation_mode() ) { - if ( d.f32 < 0 ) d.f32 = 0; - else if ( d.f32 > 1.0f ) d.f32 = 1.0f; - } - fesetround( orig_rm ); - break; - } - case F64_TYPE: case FF64_TYPE:{ - int orig_rm = fegetround(); - switch ( rounding_mode ) { - case RN_OPTION: break; - case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; - default: assert(0); break; - } - d.f64 = a.f64 * b.f64; - if ( pI->saturation_mode() ) { - if ( d.f64 < 0 ) d.f64 = 0; - else if ( d.f64 > 1.0f ) d.f64 = 1.0; - } - fesetround( orig_rm ); - break; - } - default: - assert(0); - break; - } - - thread->set_operand_value(dst, d, i_type, thread, pI); -} - -void neg_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned to_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, to_type, thread, 1); - - - switch ( to_type ) { - case S8_TYPE: - case S16_TYPE: - case S32_TYPE: - case S64_TYPE: - data.s64 = 0 - src1_data.s64; break; // seems buggy, but not (just ignore higher bits) - case U8_TYPE: - case U16_TYPE: - case U32_TYPE: - case U64_TYPE: - assert(0); break; - case F16_TYPE: assert(0); break; - case F32_TYPE: data.f32 = 0.0f - src1_data.f32; break; - case F64_TYPE: case FF64_TYPE: data.f64 = 0.0f - src1_data.f64; break; - default: assert(0); break; - } - - thread->set_operand_value(dst,data, to_type, thread, pI); -} - -//nandn bitwise negates second operand then bitwise nands with the first operand -void nandn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - //the way ptxplus handles predicates: 1 = false and 0 = true - if(i_type == PRED_TYPE) - data.pred = (~src1_data.pred & src2_data.pred); - else - data.u64 = ~(src1_data.u64 & ~src2_data.u64); - - thread->set_operand_value(dst,data, i_type, thread, pI); - -} - -//norn bitwise negates first operand then bitwise ands with the second operand -void norn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - //the way ptxplus handles predicates: 1 = false and 0 = true - if(i_type == PRED_TYPE) - data.pred = ~(src1_data.pred & ~(src2_data.pred)); - else - data.u64 = ~(src1_data.u64) & src2_data.u64; - - thread->set_operand_value(dst,data, i_type, thread, pI); - -} - -void not_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case PRED_TYPE: d.pred = (~(a.pred) & 0x000F); break; - case B16_TYPE: d.u16 = ~a.u16; break; - case B32_TYPE: d.u32 = ~a.u32; break; - case B64_TYPE: d.u64 = ~a.u64; break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void or_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - //the way ptxplus handles predicates: 1 = false and 0 = true - if(i_type == PRED_TYPE) - data.pred = ~(~(src1_data.pred) | ~(src2_data.pred)); - else - data.u64 = src1_data.u64 | src2_data.u64; - - thread->set_operand_value(dst,data, i_type, thread, pI); -} - -void orn_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - //the way ptxplus handles predicates: 1 = false and 0 = true - if(i_type == PRED_TYPE) - data.pred = ~(~(src1_data.pred) | (src2_data.pred)); - else - data.u64 = src1_data.u64 | ~src2_data.u64; - - thread->set_operand_value(dst,data, i_type, thread, pI); -} - -void pmevent_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void popc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src_data, data; - const operand_info &dst = pI->dst(); - const operand_info &src = pI->src1(); - - unsigned i_type = pI->get_type(); - src_data = thread->get_operand_value(src, dst, i_type, thread, 1); - - switch ( i_type ) { - case B32_TYPE: { - std::bitset<32> mask(src_data.u32); - data.u32 = mask.count(); - } break; - case B64_TYPE: { - std::bitset<64> mask(src_data.u64); - data.u32 = mask.count(); - } break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,data, i_type, thread, pI); -} -void prefetch_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void prefetchu_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void prmt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } - -void rcp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case F32_TYPE: - data.f32 = 1.0f / src1_data.f32; - break; - case F64_TYPE: - case FF64_TYPE: - data.f64 = 1.0f / src1_data.f64; - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,data, i_type, thread, pI); -} - -void red_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } - -void rem_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - data.u64 = src1_data.u64 % src2_data.u64; - - thread->set_operand_value(dst,data, i_type, thread, pI); -} - -void ret_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - bool empty = thread->callstack_pop(); - if( empty ) { - thread->set_done(); - thread->exitCore(); - thread->registerExit(); - } -} - -//Ptxplus version of ret instruction. -void retp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - bool empty = thread->callstack_pop_plus(); - if( empty ) { - thread->set_done(); - thread->exitCore(); - thread->registerExit(); - } -} - -void rsqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case F32_TYPE: - if ( a.f32 < 0 ) { - d.u64 = 0; - d.u64 = 0x7fc00000; // NaN - } else if ( a.f32 == 0 ) { - d.u64 = 0; - d.u32 = 0x7f800000; // Inf - } else - d.f32 = cuda_math::__internal_accurate_fdividef(1.0f, sqrtf(a.f32)); - break; - case F64_TYPE: - case FF64_TYPE: - if ( a.f32 < 0 ) { - d.u64 = 0; - d.u32 = 0x7fc00000; // NaN - float x = d.f32; - d.f64 = (double)x; - } else if ( a.f32 == 0 ) { - d.u64 = 0; - d.u32 = 0x7f800000; // Inf - float x = d.f32; - d.f64 = (double)x; - } else - d.f64 = 1.0 / sqrt(a.f64); - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -#define SAD(d,a,b,c) d = c + ((adst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - b = thread->get_operand_value(src2, dst, i_type, thread, 1); - c = thread->get_operand_value(src3, dst, i_type, thread, 1); - - - switch ( i_type ) { - case U16_TYPE: SAD(d.u16,a.u16,b.u16,c.u16); break; - case U32_TYPE: SAD(d.u32,a.u32,b.u32,c.u32); break; - case U64_TYPE: SAD(d.u64,a.u64,b.u64,c.u64); break; - case S16_TYPE: SAD(d.s16,a.s16,b.s16,c.s16); break; - case S32_TYPE: SAD(d.s32,a.s32,b.s32,c.s32); break; - case S64_TYPE: SAD(d.s64,a.s64,b.s64,c.s64); break; - case F32_TYPE: SAD(d.f32,a.f32,b.f32,c.f32); break; - case F64_TYPE: case FF64_TYPE: SAD(d.f64,a.f64,b.f64,c.f64); break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void selp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - - ptx_reg_t a, b, c, d; - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - b = thread->get_operand_value(src2, dst, i_type, thread, 1); - c = thread->get_operand_value(src3, dst, i_type, thread, 1); - - //predicate value was changed so the lowest bit being set means the zero flag is set. - //As a result, the value of c.pred must be inverted to get proper behavior - d = (!(c.pred & 0x0001))?a:b; - - thread->set_operand_value(dst,d, PRED_TYPE, thread, pI); -} - -bool isFloat(int type) -{ - switch ( type ) { - case F16_TYPE: - case F32_TYPE: - case F64_TYPE: - case FF64_TYPE: - return true; - default: - return false; - } -} - -bool CmpOp( int type, ptx_reg_t a, ptx_reg_t b, unsigned cmpop ) -{ - bool t = false; - - switch ( type ) { - case B16_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.u16 == b.u16); break; - case NE_OPTION: t = (a.u16 != b.u16); break; - default: - assert(0); - } - - case B32_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.u32 == b.u32); break; - case NE_OPTION: t = (a.u32 != b.u32); break; - default: - assert(0); - } - case B64_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.u64 == b.u64); break; - case NE_OPTION: t = (a.u64 != b.u64); break; - default: - assert(0); - } - break; - case S8_TYPE: - case S16_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.s16 == b.s16); break; - case NE_OPTION: t = (a.s16 != b.s16); break; - case LT_OPTION: t = (a.s16 < b.s16); break; - case LE_OPTION: t = (a.s16 <= b.s16); break; - case GT_OPTION: t = (a.s16 > b.s16); break; - case GE_OPTION: t = (a.s16 >= b.s16); break; - default: - assert(0); - } - break; - case S32_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.s32 == b.s32); break; - case NE_OPTION: t = (a.s32 != b.s32); break; - case LT_OPTION: t = (a.s32 < b.s32); break; - case LE_OPTION: t = (a.s32 <= b.s32); break; - case GT_OPTION: t = (a.s32 > b.s32); break; - case GE_OPTION: t = (a.s32 >= b.s32); break; - default: - assert(0); - } - break; - case S64_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.s64 == b.s64); break; - case NE_OPTION: t = (a.s64 != b.s64); break; - case LT_OPTION: t = (a.s64 < b.s64); break; - case LE_OPTION: t = (a.s64 <= b.s64); break; - case GT_OPTION: t = (a.s64 > b.s64); break; - case GE_OPTION: t = (a.s64 >= b.s64); break; - default: - assert(0); - } - break; - case U8_TYPE: - case U16_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.u16 == b.u16); break; - case NE_OPTION: t = (a.u16 != b.u16); break; - case LT_OPTION: t = (a.u16 < b.u16); break; - case LE_OPTION: t = (a.u16 <= b.u16); break; - case GT_OPTION: t = (a.u16 > b.u16); break; - case GE_OPTION: t = (a.u16 >= b.u16); break; - case LO_OPTION: t = (a.u16 < b.u16); break; - case LS_OPTION: t = (a.u16 <= b.u16); break; - case HI_OPTION: t = (a.u16 > b.u16); break; - case HS_OPTION: t = (a.u16 >= b.u16); break; - default: - assert(0); - } - break; - case U32_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.u32 == b.u32); break; - case NE_OPTION: t = (a.u32 != b.u32); break; - case LT_OPTION: t = (a.u32 < b.u32); break; - case LE_OPTION: t = (a.u32 <= b.u32); break; - case GT_OPTION: t = (a.u32 > b.u32); break; - case GE_OPTION: t = (a.u32 >= b.u32); break; - case LO_OPTION: t = (a.u32 < b.u32); break; - case LS_OPTION: t = (a.u32 <= b.u32); break; - case HI_OPTION: t = (a.u32 > b.u32); break; - case HS_OPTION: t = (a.u32 >= b.u32); break; - default: - assert(0); - } - break; - case U64_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.u64 == b.u64); break; - case NE_OPTION: t = (a.u64 != b.u64); break; - case LT_OPTION: t = (a.u64 < b.u64); break; - case LE_OPTION: t = (a.u64 <= b.u64); break; - case GT_OPTION: t = (a.u64 > b.u64); break; - case GE_OPTION: t = (a.u64 >= b.u64); break; - case LO_OPTION: t = (a.u64 < b.u64); break; - case LS_OPTION: t = (a.u64 <= b.u64); break; - case HI_OPTION: t = (a.u64 > b.u64); break; - case HS_OPTION: t = (a.u64 >= b.u64); break; - default: - assert(0); - } - break; - case F16_TYPE: assert(0); break; - case F32_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.f32 == b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; - case NE_OPTION: t = (a.f32 != b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; - case LT_OPTION: t = (a.f32 < b.f32 ) && !isNaN(a.f32) && !isNaN(b.f32); break; - case LE_OPTION: t = (a.f32 <= b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; - case GT_OPTION: t = (a.f32 > b.f32 ) && !isNaN(a.f32) && !isNaN(b.f32); break; - case GE_OPTION: t = (a.f32 >= b.f32) && !isNaN(a.f32) && !isNaN(b.f32); break; - case EQU_OPTION: t = (a.f32 == b.f32) || isNaN(a.f32) || isNaN(b.f32); break; - case NEU_OPTION: t = (a.f32 != b.f32) || isNaN(a.f32) || isNaN(b.f32); break; - case LTU_OPTION: t = (a.f32 < b.f32 ) || isNaN(a.f32) || isNaN(b.f32); break; - case LEU_OPTION: t = (a.f32 <= b.f32) || isNaN(a.f32) || isNaN(b.f32); break; - case GTU_OPTION: t = (a.f32 > b.f32 ) || isNaN(a.f32) || isNaN(b.f32); break; - case GEU_OPTION: t = (a.f32 >= b.f32) || isNaN(a.f32) || isNaN(b.f32); break; - case NUM_OPTION: t = !isNaN(a.f32) && !isNaN(b.f32); break; - case NAN_OPTION: t = isNaN(a.f32) || isNaN(b.f32); break; - default: - assert(0); - } - break; - case F64_TYPE: - case FF64_TYPE: - switch (cmpop) { - case EQ_OPTION: t = (a.f64 == b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; - case NE_OPTION: t = (a.f64 != b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; - case LT_OPTION: t = (a.f64 < b.f64 ) && !isNaN(a.f64) && !isNaN(b.f64); break; - case LE_OPTION: t = (a.f64 <= b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; - case GT_OPTION: t = (a.f64 > b.f64 ) && !isNaN(a.f64) && !isNaN(b.f64); break; - case GE_OPTION: t = (a.f64 >= b.f64) && !isNaN(a.f64) && !isNaN(b.f64); break; - case EQU_OPTION: t = (a.f64 == b.f64) || isNaN(a.f64) || isNaN(b.f64); break; - case NEU_OPTION: t = (a.f64 != b.f64) || isNaN(a.f64) || isNaN(b.f64); break; - case LTU_OPTION: t = (a.f64 < b.f64 ) || isNaN(a.f64) || isNaN(b.f64); break; - case LEU_OPTION: t = (a.f64 <= b.f64) || isNaN(a.f64) || isNaN(b.f64); break; - case GTU_OPTION: t = (a.f64 > b.f64 ) || isNaN(a.f64) || isNaN(b.f64); break; - case GEU_OPTION: t = (a.f64 >= b.f64) || isNaN(a.f64) || isNaN(b.f64); break; - case NUM_OPTION: t = !isNaN(a.f64) && !isNaN(b.f64); break; - case NAN_OPTION: t = isNaN(a.f64) || isNaN(b.f64); break; - default: - assert(0); - } - break; - default: assert(0); break; - } - - return t; -} - -void setp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b; - - int t=0; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - assert( pI->get_num_operands() < 4 ); // or need to deal with "c" operand / boolOp - - unsigned type = pI->get_type(); - unsigned cmpop = pI->get_cmpop(); - a = thread->get_operand_value(src1, dst, type, thread, 1); - b = thread->get_operand_value(src2, dst, type, thread, 1); - - t = CmpOp(type,a,b,cmpop); - - ptx_reg_t data; - - //the way ptxplus handles the zero flag, 1 = false and 0 = true - data.pred = (t==0); //inverting predicate since ptxplus uses "1" for a set zero flag - - thread->set_operand_value(dst,data, PRED_TYPE, thread, pI); -} - -void set_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b; - - int t=0; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - assert( pI->get_num_operands() < 4 ); // or need to deal with "c" operand / boolOp - - unsigned src_type = pI->get_type2(); - unsigned cmpop = pI->get_cmpop(); - - a = thread->get_operand_value(src1, dst, src_type, thread, 1); - b = thread->get_operand_value(src2, dst, src_type, thread, 1); - - // Take abs of first operand if needed - if(pI->is_abs()) { - switch ( src_type ) { - case S16_TYPE: a.s16 = my_abs(a.s16); break; - case S32_TYPE: a.s32 = my_abs(a.s32); break; - case S64_TYPE: a.s64 = my_abs(a.s64); break; - case U16_TYPE: a.u16 = a.u16; break; - case U32_TYPE: a.u32 = my_abs(a.u32); break; - case U64_TYPE: a.u64 = my_abs(a.u64); break; - case F32_TYPE: a.f32 = my_abs(a.f32); break; - case F64_TYPE: case FF64_TYPE: a.f64 = my_abs(a.f64); break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - } - - t = CmpOp(src_type,a,b,cmpop); - - ptx_reg_t data; - if ( isFloat(pI->get_type()) ) { - data.f32 = (t!=0)?1.0f:0.0f; - } else { - data.u32 = (t!=0)?0xFFFFFFFF:0; - } - - thread->set_operand_value(dst, data, pI->get_type(), thread, pI); - -} - -void shfl_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) -{ - unsigned i_type = pI->get_type(); - int tid = inst.warp_id() * core->get_warp_size(); - ptx_thread_info *thread = core->get_thread_info()[tid]; - ptx_warp_info *warp_info = thread->m_warp_info; - int lane = warp_info->get_done_threads(); - thread = core->get_thread_info()[tid + lane]; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - int bval = (thread->get_operand_value(src2, dst, i_type, thread, 1)).u32; - int cval = (thread->get_operand_value(src3, dst, i_type, thread, 1)).u32; - int mask = cval >> 8; - bval &= 0x1F; - cval &= 0x1F; - - int maxLane = (lane & mask) | (cval & ~mask); - int minLane = lane & mask; - - int src_idx; - unsigned p; - switch(pI->shfl_op()) { - case UP_OPTION: - src_idx = lane - bval; - p = (src_idx >= maxLane); - break; - case DOWN_OPTION: - src_idx = lane + bval; - p = (src_idx <= maxLane); - break; - case BFLY_OPTION: - src_idx = lane ^ bval; - p = (src_idx <= maxLane); - break; - case IDX_OPTION: - src_idx = minLane | (bval & ~mask); - p = (src_idx <= maxLane); - break; - default: - printf("GPGPU-Sim PTX: ERROR: Invalid shfl option\n"); - assert(0); - break; - } - // copy from own lane - if (!p) src_idx = lane; - - // copy input from lane src_idx - ptx_reg_t data; - if (inst.active(src_idx)) { - ptx_thread_info *source = core->get_thread_info()[tid + src_idx]; - data = source->get_operand_value(src1, dst, i_type, source, 1); - } else { - printf("GPGPU-Sim PTX: WARNING: shfl input value unpredictable for inactive threads in a warp\n"); - data.u32 = 0; - } - thread->set_operand_value(dst, data, i_type, thread, pI); - - /* - TODO: deal with predicates appropriately using the following pseudocode: - if (!isGuardPredicateTrue(src_idx)) { - printf("GPGPU-Sim PTX: WARNING: shfl input value unpredictable for predicated-off threads in a warp\n"); - } - if (dest predicate selected) data.pred = p; - */ - - // keep track of the number of threads that have executed in the warp - warp_info->inc_done_threads(); - if (warp_info->get_done_threads() == inst.active_count()) { - warp_info->reset_done_threads(); - } -} - -void shl_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - b = thread->get_operand_value(src2, dst, i_type, thread, 1); - - switch ( i_type ) { - case B16_TYPE: - case U16_TYPE: - if ( b.u16 >= 16 ) - d.u16 = 0; - else - d.u16 = (unsigned short) ((a.u16 << b.u16) & 0xFFFF); - break; - case B32_TYPE: - case U32_TYPE: - if ( b.u32 >= 32 ) - d.u32 = 0; - else - d.u32 = (unsigned) ((a.u32 << b.u32) & 0xFFFFFFFF); - break; - case B64_TYPE: - case U64_TYPE: - if ( b.u32 >= 64 ) - d.u64 = 0; - else - d.u64 = (a.u64 << b.u64); - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst, d, i_type, thread, pI); -} - -void shr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, b, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - b = thread->get_operand_value(src2, dst, i_type, thread, 1); - - - switch ( i_type ) { - case U16_TYPE: - case B16_TYPE: - if ( b.u16 < 16 ) - d.u16 = (unsigned short) ((a.u16 >> b.u16) & 0xFFFF); - else - d.u16 = 0; - break; - case U32_TYPE: - case B32_TYPE: - if ( b.u32 < 32 ) - d.u32 = (unsigned) ((a.u32 >> b.u32) & 0xFFFFFFFF); - else - d.u32 = 0; - break; - case U64_TYPE: - case B64_TYPE: - if ( b.u32 < 64 ) - d.u64 = (a.u64 >> b.u64); - else - d.u64 = 0; - break; - case S16_TYPE: - if ( b.u16 < 16 ) - d.s64 = (a.s16 >> b.s16); - else { - if ( a.s16 < 0 ) { - d.s64 = -1; - } else { - d.s64 = 0; - } - } - break; - case S32_TYPE: - if ( b.u32 < 32 ) - d.s64 = (a.s32 >> b.s32); - else { - if ( a.s32 < 0 ) { - d.s64 = -1; - } else { - d.s64 = 0; - } - } - break; - case S64_TYPE: - if ( b.u64 < 64 ) - d.s64 = (a.s64 >> b.u64); - else { - if ( a.s64 < 0 ) { - if ( b.s32 < 0 ) { - d.u64 = -1; - d.s32 = 0; - } else { - d.s64 = -1; - } - } else { - d.s64 = 0; - } - } - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void sin_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case F32_TYPE: - d.f32 = sin(a.f32); - break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void slct_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - const operand_info &src3 = pI->src3(); - - ptx_reg_t a, b, c, d; - - unsigned i_type = pI->get_type(); - unsigned c_type = pI->get_type2(); - bool t = false; - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - b = thread->get_operand_value(src2, dst, i_type, thread, 1); - c = thread->get_operand_value(src3, dst, c_type, thread, 1); - - switch ( c_type ) { - case S32_TYPE: t = c.s32 >= 0; break; - case F32_TYPE: t = c.f32 >= 0; break; - default: assert(0); - } - - switch ( i_type ) { - case B16_TYPE: - case S16_TYPE: - case U16_TYPE: d.u16 = t?a.u16:b.u16; break; - case F32_TYPE: - case B32_TYPE: - case S32_TYPE: - case U32_TYPE: d.u32 = t?a.u32:b.u32; break; - case F64_TYPE: - case FF64_TYPE: - case B64_TYPE: - case S64_TYPE: - case U64_TYPE: d.u64 = t?a.u64:b.u64; break; - default: assert(0); - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void sqrt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t a, d; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - - unsigned i_type = pI->get_type(); - a = thread->get_operand_value(src1, dst, i_type, thread, 1); - - - switch ( i_type ) { - case F32_TYPE: - if ( a.f32 < 0 ) - d.f32 = nanf(""); - else - d.f32 = sqrt(a.f32); break; - case F64_TYPE: - case FF64_TYPE: - if ( a.f64 < 0 ) - d.f64 = nan(""); - else - d.f64 = sqrt(a.f64); break; - default: - printf("Execution error: type mismatch with instruction\n"); - assert(0); - break; - } - - thread->set_operand_value(dst,d, i_type, thread, pI); -} - -void ssy_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - //printf("Execution Warning: unimplemented ssy instruction is treated as a nop\n"); - // TODO: add implementation -} - -void st_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); //may be scalar or vector of regs - unsigned type = pI->get_type(); - ptx_reg_t addr_reg = thread->get_operand_value(dst, dst, type, thread, 1); - ptx_reg_t data; - memory_space_t space = pI->get_space(); - unsigned vector_spec = pI->get_vector(); - - memory_space *mem = NULL; - addr_t addr = addr_reg.u32; - - decode_space(space,thread,dst,mem,addr); - - size_t size; - int t; - type_info_key::type_decode(type,size,t); - - if (!vector_spec) { - data = thread->get_operand_value(src1, dst, type, thread, 1); - mem->write(addr,size/8,&data.s64,thread,pI); - } else { - if (vector_spec == V2_TYPE) { - ptx_reg_t* ptx_regs = new ptx_reg_t[2]; - thread->get_vector_operand_values(src1, ptx_regs, 2); - mem->write(addr,size/8,&ptx_regs[0].s64,thread,pI); - mem->write(addr+size/8,size/8,&ptx_regs[1].s64,thread,pI); - delete [] ptx_regs; - } - if (vector_spec == V3_TYPE) { - ptx_reg_t* ptx_regs = new ptx_reg_t[3]; - thread->get_vector_operand_values(src1, ptx_regs, 3); - mem->write(addr,size/8,&ptx_regs[0].s64,thread,pI); - mem->write(addr+size/8,size/8,&ptx_regs[1].s64,thread,pI); - mem->write(addr+2*size/8,size/8,&ptx_regs[2].s64,thread,pI); - delete [] ptx_regs; - } - if (vector_spec == V4_TYPE) { - ptx_reg_t* ptx_regs = new ptx_reg_t[4]; - thread->get_vector_operand_values(src1, ptx_regs, 4); - mem->write(addr,size/8,&ptx_regs[0].s64,thread,pI); - mem->write(addr+size/8,size/8,&ptx_regs[1].s64,thread,pI); - mem->write(addr+2*size/8,size/8,&ptx_regs[2].s64,thread,pI); - mem->write(addr+3*size/8,size/8,&ptx_regs[3].s64,thread,pI); - delete [] ptx_regs; - } - } - thread->m_last_effective_address = addr; - thread->m_last_memory_space = space; -} - -void sub_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t data; - int overflow = 0; - int carry = 0; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - ptx_reg_t src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - ptx_reg_t src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - //performs addition. Sets carry and overflow if needed. - //the constant is added in during subtraction so the carry bit is set properly. - switch ( i_type ) { - case S8_TYPE: - data.s64 = (src1_data.s64 & 0xFF) - (src2_data.s64 & 0xFF) + 0x100; - if(((src1_data.s64 & 0x80)-(src2_data.s64 & 0x80)) != 0) {overflow=((src1_data.s64 & 0x80)-(data.s64 & 0x80))==0?0:1; } - carry = (data.s32 & 0x100)>>8; - break; - case S16_TYPE: - data.s64 = (src1_data.s64 & 0xFFFF) - (src2_data.s64 & 0xFFFF) + 0x10000; - if(((src1_data.s64 & 0x8000)-(src2_data.s64 & 0x8000)) != 0) {overflow=((src1_data.s64 & 0x8000)-(data.s64 & 0x8000))==0?0:1; } - carry = (data.s32 & 0x10000)>>16; - break; - case S32_TYPE: - data.s64 = (src1_data.s64 & 0xFFFFFFFF) - (src2_data.s64 & 0xFFFFFFFF) + 0x100000000; - if(((src1_data.s64 & 0x80000000)-(src2_data.s64 & 0x80000000)) != 0) {overflow=((src1_data.s64 & 0x80000000)-(data.s64 & 0x80000000))==0?0:1; } - carry = ((data.u64)>>32) & 0x0001; - break; - case S64_TYPE: - data.s64 = src1_data.s64 - src2_data.s64; break; - case B8_TYPE: - case U8_TYPE: - data.u64 = (src1_data.u64 & 0xFF) - (src2_data.u64 & 0xFF) + 0x100; - carry = (data.u64 & 0x100)>>8; - break; - case B16_TYPE: - case U16_TYPE: - data.u64 = (src1_data.u64 & 0xFFFF) - (src2_data.u64 & 0xFFFF) + 0x10000; - carry = (data.u64 & 0x10000)>>16; - break; - case B32_TYPE: - case U32_TYPE: - data.u64 = (src1_data.u64 & 0xFFFFFFFF) - (src2_data.u64 & 0xFFFFFFFF) + 0x100000000; - carry = (data.u64 & 0x100000000)>>32; - break; - case B64_TYPE: - case U64_TYPE: - data.u64 = src1_data.u64 - src2_data.u64; break; - case F16_TYPE: assert(0); break; - case F32_TYPE: data.f32 = src1_data.f32 - src2_data.f32; break; - case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 - src2_data.f64; break; - default: assert(0); break; - } - - thread->set_operand_value(dst,data, i_type, thread, pI, overflow, carry); -} - -void nop_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - // Do nothing -} - -void subc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void suld_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void sured_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void sust_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void suq_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } - -ptx_reg_t* ptx_tex_regs = NULL; - -union intfloat { - int a; - float b; -}; - -float reduce_precision( float x, unsigned bits ) -{ - intfloat tmp; - tmp.b = x; - int v = tmp.a; - int man = v & ((1<<23)-1); - int mask = ((1<= mx) nx -= elem_size; - unsigned ny = (y >= my)? my - 1 : y; - return nx + mx*ny; -} - -typedef unsigned (*texAddr_t) (unsigned x, unsigned y, unsigned mx, unsigned my, size_t elem_size); -float tex_linf_sampling(memory_space* mem, unsigned tex_array_base, - int x, int y, unsigned int width, unsigned int height, size_t elem_size, - float alpha, float beta, texAddr_t b_lim) -{ - float Tij; - float Ti1j; - float Tij1; - float Ti1j1; - - mem->read(tex_array_base + b_lim(x,y,width,height,elem_size), 4, &Tij); - mem->read(tex_array_base + b_lim(x+elem_size,y,width,height,elem_size), 4, &Ti1j); - mem->read(tex_array_base + b_lim(x,y+1,width,height,elem_size), 4, &Tij1); - mem->read(tex_array_base + b_lim(x+elem_size,y+1,width,height,elem_size), 4, &Ti1j1); - - float sample = (1-alpha)*(1-beta)*Tij + - alpha*(1-beta)*Ti1j + - (1-alpha)*beta*Tij1 + - alpha*beta*Ti1j1; - - return sample; -} - -float textureNormalizeElementSigned(int element, int bits) -{ - if (bits) { - int maxN = (1 << bits) - 1; - // removing upper bits - element &= maxN; - // normalizing the number to [-1.0,1.0] - maxN >>= 1; - float output = (float) element / maxN; - if (output < -1.0f) output = -1.0f; - return output; - } else { - return 0.0f; - } -} - -float textureNormalizeElementUnsigned(unsigned int element, int bits) -{ - if (bits) { - unsigned int maxN = (1 << bits) - 1; - // removing upper bits and normalizing the number to [0.0,1.0] - return (float)(element & maxN) / maxN; - } else { - return 0.0f; - } -} - -void textureNormalizeOutput( const struct cudaChannelFormatDesc& desc, ptx_reg_t& datax, ptx_reg_t& datay, ptx_reg_t& dataz, ptx_reg_t& dataw ) -{ - if (desc.f == cudaChannelFormatKindSigned) { - datax.f32 = textureNormalizeElementSigned( datax.s32, desc.x ); - datay.f32 = textureNormalizeElementSigned( datay.s32, desc.y ); - dataz.f32 = textureNormalizeElementSigned( dataz.s32, desc.z ); - dataw.f32 = textureNormalizeElementSigned( dataw.s32, desc.w ); - } else if (desc.f == cudaChannelFormatKindUnsigned) { - datax.f32 = textureNormalizeElementUnsigned( datax.u32, desc.x ); - datay.f32 = textureNormalizeElementUnsigned( datay.u32, desc.y ); - dataz.f32 = textureNormalizeElementUnsigned( dataz.u32, desc.z ); - dataw.f32 = textureNormalizeElementUnsigned( dataw.u32, desc.w ); - } else { - assert(0 && "Undefined texture read mode: cudaReadModeNormalizedFloat expect integer elements"); - } -} - -void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - unsigned dimension = pI->dimension(); - const operand_info &dst = pI->dst(); //the registers to which fetched texel will be placed - const operand_info &src1 = pI->src1(); //the name of the texture - const operand_info &src2 = pI->src2(); //the vector registers containing coordinates of the texel to be fetched - - std::string texname = src1.name(); - unsigned to_type = pI->get_type(); - unsigned c_type = pI->get_type2(); - fflush(stdout); - ptx_reg_t data1, data2, data3, data4; - if (!ptx_tex_regs) ptx_tex_regs = new ptx_reg_t[4]; - unsigned nelem = src2.get_vect_nelem(); - thread->get_vector_operand_values(src2, ptx_tex_regs, nelem); //ptx_reg should be 4 entry vector type...coordinates into texture - - gpgpu_t *gpu = thread->get_gpu(); - const struct textureReference* texref = gpu->get_texref(texname); - const struct cudaArray* cuArray = gpu->get_texarray(texref); - const struct textureInfo* texInfo = gpu->get_texinfo(texref); - const struct textureReferenceAttr* texAttr = gpu->get_texattr(texref); - - //assume always 2D f32 input - //access array with src2 coordinates - memory_space *mem = thread->get_global_memory(); - float x_f32, y_f32; - size_t size; - int t; - unsigned tex_array_base; - unsigned int width = 0, height = 0; - int x = 0; - int y = 0; - unsigned tex_array_index; - float alpha=0, beta=0; - - type_info_key::type_decode(to_type,size,t); - tex_array_base = cuArray->devPtr32; - - switch (dimension) { - case GEOM_MODIFIER_1D: - width = cuArray->width; - height = cuArray->height; - if (texref->normalized) { - assert(c_type == F32_TYPE); - x_f32 = ptx_tex_regs[0].f32; - if (texref->addressMode[0] == cudaAddressModeClamp) { - x_f32 = (x_f32 > 1.0)? 1.0 : x_f32; - x_f32 = (x_f32 < 0.0)? 0.0 : x_f32; - } else if (texref->addressMode[0] == cudaAddressModeWrap) { - x_f32 = x_f32 - floor(x_f32); - } - - if( texref->filterMode == cudaFilterModeLinear ) { - float xb = x_f32 * width - 0.5; - alpha = xb - floor(xb); - alpha = reduce_precision(alpha,9); - beta = 0.0; - - x = (int)floor(xb); - y = 0; - } else { - x = (int) floor(x_f32 * width); - y = 0; - } - } else { - switch ( c_type ) { - case S32_TYPE: - x = ptx_tex_regs[0].s32; - assert(texref->filterMode == cudaFilterModePoint); - break; - case F32_TYPE: - x_f32 = ptx_tex_regs[0].f32; - alpha = x_f32 - floor(x_f32); // offset into subtexel (for linear sampling) - x = (int) x_f32; - break; - default: assert(0 && "Unsupported texture coordinate type."); - } - // handle texture fetch that exceeded boundaries - if (texref->addressMode[0] == cudaAddressModeClamp) { - x = (x > width - 1)? (width - 1) : x; - x = (x < 0)? 0 : x; - } else if (texref->addressMode[0] == cudaAddressModeWrap) { - x = x % width; - } - } - width *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; - x *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; - tex_array_index = tex_array_base + x; - - break; - case GEOM_MODIFIER_2D: - width = cuArray->width; - height = cuArray->height; - if (texref->normalized) { - x_f32 = reduce_precision(ptx_tex_regs[0].f32,16); - y_f32 = reduce_precision(ptx_tex_regs[1].f32,15); - - if (texref->addressMode[0]) {//clamp - if (x_f32<0) x_f32 = 0; - if (x_f32>=1) x_f32 = 1 - 1/x_f32; - } else {//wrap - x_f32 = x_f32 - floor(x_f32); - } - if (texref->addressMode[1]) {//clamp - if (y_f32<0) y_f32 = 0; - if (y_f32>=1) y_f32 = 1 - 1/y_f32; - } else {//wrap - y_f32 = y_f32 - floor(y_f32); - } - - if( texref->filterMode == cudaFilterModeLinear ) { - float xb = x_f32 * width - 0.5; - float yb = y_f32 * height - 0.5; - alpha = xb - floor(xb); - beta = yb - floor(yb); - alpha = reduce_precision(alpha,9); - beta = reduce_precision(beta,9); - - x = (int)floor(xb); - y = (int)floor(yb); - } else { - x = (int) floor(x_f32 * width); - y = (int) floor(y_f32 * height); - } - } else { - x_f32 = ptx_tex_regs[0].f32; - y_f32 = ptx_tex_regs[1].f32; - - alpha = x_f32 - floor(x_f32); - beta = y_f32 - floor(y_f32); - - x = (int) x_f32; - y = (int) y_f32; - if (texref->addressMode[0]) {//clamp - if (x<0) x = 0; - if (x>= (int)width) x = width-1; - } else {//wrap - x = x % width; - if (x < 0) x*= -1; - } - if (texref->addressMode[1]) {//clamp - if (y<0) y = 0; - if (y>= (int)height) y = height -1; - } else {//wrap - y = y % height; - if (y < 0) y *= -1; - } - } - - width *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; - x *= (cuArray->desc.w+cuArray->desc.x+cuArray->desc.y+cuArray->desc.z)/8; - tex_array_index = tex_array_base + (x + width*y); - break; - default: - assert(0); break; - } - switch ( to_type ) { - case U8_TYPE: - case U16_TYPE: - case U32_TYPE: - case B8_TYPE: - case B16_TYPE: - case B32_TYPE: - case S8_TYPE: - case S16_TYPE: - case S32_TYPE: { - unsigned long long elementOffset = 0; // offset into the next element - mem->read( tex_array_index, cuArray->desc.x/8, &data1.u32); - elementOffset += cuArray->desc.x/8; - if (cuArray->desc.y) { - mem->read( tex_array_index + elementOffset, cuArray->desc.y/8, &data2.u32); - elementOffset += cuArray->desc.y/8; - if (cuArray->desc.z) { - mem->read( tex_array_index + elementOffset, cuArray->desc.z/8, &data3.u32); - elementOffset += cuArray->desc.z/8; - if (cuArray->desc.w) - mem->read( tex_array_index + elementOffset, cuArray->desc.w/8, &data4.u32); - } - } - break; - } - case B64_TYPE: - case U64_TYPE: - case S64_TYPE: - mem->read( tex_array_index, 8, &data1.u64); - if (cuArray->desc.y) { - mem->read( tex_array_index+8, 8, &data2.u64); - if (cuArray->desc.z) { - mem->read( tex_array_index+16, 8, &data3.u64); - if (cuArray->desc.w) - mem->read( tex_array_index+24, 8, &data4.u64); - } - } - break; - case F16_TYPE: assert(0); break; - case F32_TYPE: { - if( texref->filterMode == cudaFilterModeLinear ) { - texAddr_t b_lim = wrap; - if ( texref->addressMode[0] == cudaAddressModeClamp ) { - b_lim = clamp; - } - size_t elem_size = (cuArray->desc.x + cuArray->desc.y + cuArray->desc.z + cuArray->desc.w) / 8; - size_t elem_ofst = 0; - - data1.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); - elem_ofst += cuArray->desc.x / 8; - if (cuArray->desc.y) { - data2.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); - elem_ofst += cuArray->desc.y / 8; - if (cuArray->desc.z) { - data3.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); - elem_ofst += cuArray->desc.z / 8; - if (cuArray->desc.w) - data4.f32 = tex_linf_sampling(mem, tex_array_base, x + elem_ofst, y, width, height, elem_size, alpha, beta, b_lim); - } - } - } else { - mem->read( tex_array_index, cuArray->desc.x/8, &data1.f32); - if (cuArray->desc.y) { - mem->read( tex_array_index+4, cuArray->desc.y/8, &data2.f32); - if (cuArray->desc.z) { - mem->read( tex_array_index+8, cuArray->desc.z/8, &data3.f32); - if (cuArray->desc.w) - mem->read( tex_array_index+12, cuArray->desc.w/8, &data4.f32); - } - } - } - } break; - case F64_TYPE: - case FF64_TYPE: - mem->read( tex_array_index, 8, &data1.f64); - if (cuArray->desc.y) { - mem->read( tex_array_index+8, 8, &data2.f64); - if (cuArray->desc.z) { - mem->read( tex_array_index+16, 8, &data3.f64); - if (cuArray->desc.w) - mem->read( tex_array_index+24, 8, &data4.f64); - } - } - break; - default: assert(0); break; - } - int x_block_coord, y_block_coord, memreqindex, blockoffset; - - switch (dimension) { - case GEOM_MODIFIER_1D: - thread->m_last_effective_address = tex_array_index; - break; - case GEOM_MODIFIER_2D: - x_block_coord = x >> (texInfo->Tx_numbits + texInfo->texel_size_numbits); - y_block_coord = y >> texInfo->Ty_numbits; - - memreqindex = ((y_block_coord*cuArray->width/texInfo->Tx)+x_block_coord)<<6; - - blockoffset = (x%(texInfo->Tx*texInfo->texel_size) + (y%(texInfo->Ty)<<(texInfo->Tx_numbits + texInfo->texel_size_numbits))); - memreqindex += blockoffset; - thread->m_last_effective_address = tex_array_base + memreqindex;//tex_array_index; - break; - default: - assert(0); - } - thread->m_last_memory_space = tex_space; - - // normalize output into floating point numbers according to the texture read mode - if (texAttr->m_readmode == cudaReadModeNormalizedFloat) { - textureNormalizeOutput(cuArray->desc, data1, data2, data3, data4); - } else { - assert(texAttr->m_readmode == cudaReadModeElementType); - } - - thread->set_vector_operand_values(dst,data1,data2,data3,data4); -} - -void txq_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void trap_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vabsdiff_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vadd_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vmad_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vmax_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vmin_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vset_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vshl_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vshr_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } -void vsub_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); } - -void vote_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - static bool first_in_warp = true; - static bool and_all; - static bool or_all; - static unsigned int ballot_result; - static std::list threads_in_warp; - static unsigned last_tid; - - if( first_in_warp ) { - first_in_warp = false; - threads_in_warp.clear(); - and_all = true; - or_all = false; - ballot_result = 0; - int offset=31; - while( (offset>=0) && !pI->active(offset) ) - offset--; - assert( offset >= 0 ); - last_tid = (thread->get_hw_tid() - (thread->get_hw_tid()%pI->warp_size())) + offset; - } - - ptx_reg_t src1_data; - const operand_info &src1 = pI->src1(); - src1_data = thread->get_operand_value(src1, pI->dst(), PRED_TYPE, thread, 1); - - //predicate value was changed so the lowest bit being set means the zero flag is set. - //As a result, the value of src1_data.pred must be inverted to get proper behavior - bool pred_value = !(src1_data.pred & 0x0001); - bool invert = src1.is_neg_pred(); - - threads_in_warp.push_back(thread); - and_all &= (invert ^ pred_value); - or_all |= (invert ^ pred_value); - - // vote.ballot - if (invert ^ pred_value) { - int lane_id = thread->get_hw_tid() % pI->warp_size(); - ballot_result |= (1 << lane_id); - } - - if( thread->get_hw_tid() == last_tid ) { - if (pI->vote_mode() == ptx_instruction::vote_ballot) { - ptx_reg_t data = ballot_result; - for( std::list::iterator t=threads_in_warp.begin(); t!=threads_in_warp.end(); ++t ) { - const operand_info &dst = pI->dst(); - (*t)->set_operand_value(dst,data, pI->get_type(), (*t), pI); - } - } else { - bool pred_value = false; - - switch( pI->vote_mode() ) { - case ptx_instruction::vote_any: pred_value = or_all; break; - case ptx_instruction::vote_all: pred_value = and_all; break; - case ptx_instruction::vote_uni: pred_value = (or_all ^ and_all); break; - default: - abort(); - } - ptx_reg_t data; - data.pred = pred_value?0:1; //the way ptxplus handles the zero flag, 1 = false and 0 = true - - for( std::list::iterator t=threads_in_warp.begin(); t!=threads_in_warp.end(); ++t ) { - const operand_info &dst = pI->dst(); - (*t)->set_operand_value(dst,data, PRED_TYPE, (*t), pI); - } - } - first_in_warp = true; - } -} - -void xor_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -{ - ptx_reg_t src1_data, src2_data, data; - - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); - - unsigned i_type = pI->get_type(); - src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); - src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); - - //the way ptxplus handles predicates: 1 = false and 0 = true - if(i_type == PRED_TYPE) - data.pred = ~(~(src1_data.pred) ^ ~(src2_data.pred)); - else - data.u64 = src1_data.u64 ^ src2_data.u64; - - thread->set_operand_value(dst,data, i_type, thread, pI); -} - -void inst_not_implemented( const ptx_instruction * pI ) -{ - printf("GPGPU-Sim PTX: ERROR (%s:%u) instruction \"%s\" not (yet) implemented\n", - pI->source_file(), - pI->source_line(), - pI->get_opcode_cstr() ); - abort(); -} - -ptx_reg_t srcOperandModifiers(ptx_reg_t opData, operand_info opInfo, operand_info dstInfo, unsigned type, ptx_thread_info *thread) -{ - ptx_reg_t result; - memory_space *mem = NULL; - size_t size; - int t; - result.u64=0; - - //complete other cases for reading from memory, such as reading from other const memory - if(opInfo.get_addr_space() == global_space) - { - mem = thread->get_global_memory(); - type_info_key::type_decode(type,size,t); - mem->read(opData.u32,size/8,&result.u64); - if( type == S16_TYPE || type == S32_TYPE ) - sign_extend(result,size,dstInfo); - } - else if(opInfo.get_addr_space() == shared_space) - { - mem = thread->m_shared_mem; - type_info_key::type_decode(type,size,t); - mem->read(opData.u32,size/8,&result.u64); - - if( type == S16_TYPE || type == S32_TYPE ) - sign_extend(result,size,dstInfo); - - } - else if(opInfo.get_addr_space() == const_space) - { - mem = thread->get_global_memory(); - type_info_key::type_decode(type,size,t); - - mem->read((opData.u32 + opInfo.get_const_mem_offset()),size/8,&result.u64); - - if( type == S16_TYPE || type == S32_TYPE ) - sign_extend(result,size,dstInfo); - } - else - { - result = opData; - } - - if(opInfo.get_operand_lohi() == 1) - { - result.u64 = result.u64 & 0xFFFF; - } - else if(opInfo.get_operand_lohi() == 2) - { - result.u64 = (result.u64>>16) & 0xFFFF; - } - - if(opInfo.get_operand_neg() == true) { - result.f32 = -result.f32; - } - - return result; -} - diff --git a/src/cuda-sim/ptx_loader.cc~ b/src/cuda-sim/ptx_loader.cc~ deleted file mode 100644 index c922b18..0000000 --- a/src/cuda-sim/ptx_loader.cc~ +++ /dev/null @@ -1,462 +0,0 @@ -// Copyright (c) 2009-2011, Tor M. Aamodt -// The University of British Columbia -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// Redistributions of source code must retain the above copyright notice, this -// list of conditions and the following disclaimer. -// Redistributions in binary form must reproduce the above copyright notice, this -// list of conditions and the following disclaimer in the documentation and/or -// other materials provided with the distribution. -// Neither the name of The University of British Columbia nor the names of its -// contributors may be used to endorse or promote products derived from this -// software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -#include "ptx_loader.h" -#include "ptx_ir.h" -#include "cuda-sim.h" -#include "ptx_parser.h" -#include -#include -#include -#include - -/// globals - -memory_space *g_global_mem; -memory_space *g_tex_mem; -memory_space *g_surf_mem; -memory_space *g_param_mem; -bool g_override_embedded_ptx = false; - -/// extern prototypes - -extern int ptx_parse(); -extern int ptx__scan_string(const char*); - -extern std::map get_duplicate(); - -const char *g_ptxinfo_filename; -extern int ptxinfo_parse(); -extern int ptxinfo_debug; -extern FILE *ptxinfo_in; - -static bool g_save_embedded_ptx; -bool g_keep_intermediate_files; -bool m_ptx_save_converted_ptxplus; - -bool keep_intermediate_files() {return g_keep_intermediate_files;} - -void ptx_reg_options(option_parser_t opp) -{ - option_parser_register(opp, "-save_embedded_ptx", OPT_BOOL, &g_save_embedded_ptx, - "saves ptx files embedded in binary as .ptx", - "0"); - option_parser_register(opp, "-keep", OPT_BOOL, &g_keep_intermediate_files, - "keep intermediate files created by GPGPU-Sim when interfacing with external programs", - "0"); - option_parser_register(opp, "-gpgpu_ptx_save_converted_ptxplus", OPT_BOOL, - &m_ptx_save_converted_ptxplus, - "Saved converted ptxplus to a file", - "0"); -} - -void print_ptx_file( const char *p, unsigned source_num, const char *filename ) -{ - printf("\nGPGPU-Sim PTX: file _%u.ptx contents:\n\n", source_num ); - char *s = strdup(p); - char *t = s; - unsigned n=1; - while ( *t != '\0' ) { - char *u = t; - while ( (*u != '\n') && (*u != '\0') ) u++; - unsigned last = (*u == '\0'); - *u = '\0'; - const ptx_instruction *pI = ptx_instruction_lookup(filename,n); - char pc[64]; - if( pI && pI->get_PC() ) - snprintf(pc,64,"%4u", pI->get_PC() ); - else - snprintf(pc,64," "); - printf(" _%u.ptx %4u (pc=%s): %s\n", source_num, n, pc, t ); - if ( last ) break; - t = u+1; - n++; - } - free(s); - fflush(stdout); -} - -char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptxfilename, const std::string elffilename, const std::string sassfilename) -{ - - printf("GPGPU-Sim PTX: converting EMBEDDED .ptx file to ptxplus \n"); - - char fname_ptxplus[1024]; - snprintf(fname_ptxplus,1024,"_ptxplus_XXXXXX"); - int fd4=mkstemp(fname_ptxplus); - close(fd4); - - // Run cuobjdump_to_ptxplus - char commandline[1024]; - int result; - snprintf(commandline, 1024, "$GPGPUSIM_ROOT/build/$GPGPUSIM_CONFIG/cuobjdump_to_ptxplus/cuobjdump_to_ptxplus %s %s %s %s", - ptxfilename.c_str(), - sassfilename.c_str(), - elffilename.c_str(), - fname_ptxplus); - fflush(stdout); - printf("GPGPU-Sim PTX: calling cuobjdump_to_ptxplus\ncommandline: %s\n", commandline); - result = system(commandline); - if(result){printf("GPGPU-Sim PTX: ERROR ** could not execute %s\n", commandline); exit(1);} - - - // Get ptxplus from file - std::ifstream fileStream(fname_ptxplus, std::ios::in); - std::string text, line; - while(getline(fileStream,line)) { - text += (line + "\n"); - } - fileStream.close(); - - char* ptxplus_str = new char [strlen(text.c_str())+1]; - strcpy(ptxplus_str, text.c_str()); - - if (!m_ptx_save_converted_ptxplus){ - char rm_commandline[1024]; - - snprintf(rm_commandline,1024,"rm -f %s", fname_ptxplus); - - printf("GPGPU-Sim PTX: removing temporary files using \"%s\"\n", rm_commandline); - int rm_result = system(rm_commandline); - if( rm_result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while removing temporary files %d\n", rm_result); - exit(1); - } - } - printf("GPGPU-Sim PTX: DONE converting EMBEDDED .ptx file to ptxplus \n"); - - return ptxplus_str; -} - - -symbol_table *gpgpu_ptx_sim_load_ptx_from_string( const char *p, unsigned source_num ) -{ - char buf[1024]; - snprintf(buf,1024,"_%u.ptx", source_num ); - if( g_save_embedded_ptx ) { - FILE *fp = fopen(buf,"w"); - fprintf(fp,"%s",p); - fclose(fp); - } - symbol_table *symtab=init_parser(buf); - ptx__scan_string(p); - int errors = ptx_parse (); - if ( errors ) { - char fname[1024]; - snprintf(fname,1024,"_ptx_errors_XXXXXX"); - int fd=mkstemp(fname); - close(fd); - printf("GPGPU-Sim PTX: parser error detected, exiting... but first extracting .ptx to \"%s\"\n", fname); - FILE *ptxfile = fopen(fname,"w"); - fprintf(ptxfile,"%s", p ); - fclose(ptxfile); - abort(); - exit(40); - } - - //if ( g_debug_execution >= 100 ) - print_ptx_file(p,source_num,buf); - - printf("GPGPU-Sim PTX: finished parsing EMBEDDED .ptx file %s\n",buf); - return symtab; -} - -void fix_duplicate_errors(char fname2[1024]) { - char tempfile[1024] = "_temp_ptx"; - char commandline[1024]; - - // change the name of the ptx file to _temp_ptx - snprintf(commandline,1024,"mv %s %s",fname2,tempfile); - printf("Running: %s\n", commandline); - int result = system(commandline); - if (result != 0) { - printf("GPGPU-Sim PTX: ERROR ** while changing filename from %s to %s", fname2, tempfile); - exit(1); - } - - // store all of the ptx into a char array - FILE *ptxsource = fopen(tempfile,"r"); - fseek(ptxsource, 0, SEEK_END); - long filesize = ftell(ptxsource); - rewind(ptxsource); - char *ptxdata = (char*)malloc((filesize+1)*sizeof(char)); - fread(ptxdata, filesize, 1, ptxsource); - fclose(ptxsource); - - FILE *ptxdest = fopen(fname2,"w"); - std::map duplicate = get_duplicate(); - unsigned offset; - unsigned oldlinenum = 1; - unsigned linenum; - char *startptr = ptxdata; - char *funcptr; - char *tempptr = ptxdata - 1; - char *lineptr = ptxdata - 1; - - // recreate the ptx file without duplications - for ( std::map::iterator iter = duplicate.begin(); - iter != duplicate.end(); - iter++){ - // find the line of the next error - linenum = iter->first; - for (int i = oldlinenum; i < linenum; i++) { - lineptr = strchr(lineptr + 1, '\n'); - } - - // find the end of the current section to be copied over - // then find the start of the next section that will be copied - if (strcmp("function", iter->second) == 0) { - // get location of most recent .func - while (tempptr < lineptr && tempptr != NULL) { - funcptr = tempptr; - tempptr = strstr(funcptr + 1, ".func"); - } - - // get the start of the previous line - offset = 0; - while (*(funcptr - offset) != '\n') offset++; - - fwrite(startptr, sizeof(char), funcptr - offset + 1 - startptr, ptxdest); - - //find next location of startptr - if (*(lineptr + 3) == ';') { - // for function definitions - startptr = lineptr + 5; - } else if (*(lineptr + 3) == '{') { - // for functions enclosed with curly brackets - offset = 5; - unsigned bracket = 1; - while (bracket != 0) { - if (*(lineptr + offset) == '{') bracket++; - else if (*(lineptr + offset) == '}') bracket--; - offset++; - } - startptr = lineptr + offset + 1; - } else { - printf("GPGPU-Sim PTX: ERROR ** Unrecognized function format\n"); - abort(); - } - } else if (strcmp("variable", iter->second) == 0) { - fwrite(startptr, sizeof(char), (int)(lineptr + 1 - startptr), ptxdest); - - //find next location of startptr - offset = 1; - while (*(lineptr + offset) != '\n') offset++; - startptr = lineptr + offset + 1; - } else { - printf("GPGPU-Sim PTX: ERROR ** Unsupported duplicate type: %s\n", iter->second); - } - - oldlinenum = linenum; - } - // copy over the rest of the file - fwrite(startptr, sizeof(char), ptxdata + filesize - startptr, ptxdest); - - // cleanup - free(ptxdata); - fclose(ptxdest); - snprintf(commandline,1024,"rm -f %s",tempfile); - printf("Running: %s\n", commandline); - result = system(commandline); - if (result != 0) { - printf("GPGPU-Sim PTX: ERROR ** while deleting %s", tempfile); - exit(1); - } -} - -//we need the application name here too. -char* get_app_binary_name(){ - char exe_path[1025]; - char *self_exe_path; -#ifdef __APPLE__ - //AMRUTH: get apple device and check the result. - printf("WARNING: not tested for Apple-mac devices \n"); - abort(); -#else - std::stringstream exec_link; - exec_link << "/proc/self/exe"; - ssize_t path_length = readlink(exec_link.str().c_str(), exe_path, 1024); - assert(path_length != -1); - exe_path[path_length] = '\0'; - - char *token = strtok(exe_path, "/"); - while(token !=NULL){ - self_exe_path = token; - token = strtok(NULL,"/"); - } -#endif - self_exe_path = strtok(self_exe_path, "."); - printf("self exe links to: %s\n", self_exe_path); - return self_exe_path; -} - -void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num, unsigned sm_version ) -{ - //do ptxas for individual files instead of one big embedded ptx. This prevents the duplicate defs and declarations. - char ptx_file[1000]; - char *name=get_app_binary_name(); - char commandline[4096], fname[1024], fname2[1024], final_tempfile_ptxinfo[1024], tempfile_ptxinfo[1024]; - for (int index=1; index <= no_of_ptx; index++){ - snprintf(ptx_file, 1000, "%s.%d.sm_%u.ptx", name, index, sm_version); - snprintf(fname,1024,"_ptx_XXXXXX"); - int fd=mkstemp(fname); - close(fd); - - printf("GPGPU-Sim PTX: extracting embedded .ptx to temporary file \"%s\"\n", fname); - snprintf(commandline,4096,"cat %s > %s",ptx_file, fname); - if (system(commandline) !=0) { - printf("ERROR: %s command failed\n", commandline); - exit(0); - } - - snprintf(fname2,1024,"_ptx2_XXXXXX"); - fd=mkstemp(fname2); - close(fd); - char commandline2[4096]; - snprintf(commandline2,4096,"cat %s | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\\(\\.extern \\.const\\[1\\] .b8 \\w\\+\\)\\[\\]/\\1\\[1\\]/' | sed 's/const\\[.\\]/const\\[0\\]/g' > %s", fname, fname2); - printf("Running: %s\n", commandline2); - int result = system(commandline2); - if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); - printf(" Ensure you have write access to simulation directory\n"); - printf(" and have \'cat\' and \'sed\' in your path.\n"); - exit(1); - } - - snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); - char extra_flags[1024]; - extra_flags[0]=0; - - #if CUDART_VERSION >= 3000 - if (sm_version == 0) sm_version = 20; - extern bool g_cdp_enabled; - if(!g_cdp_enabled) - snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); - else - snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version); - #endif - - snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", - extra_flags, fname2, tempfile_ptxinfo); - printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); - result = system(commandline); - if( result != 0 ) { - // 65280 = duplicate errors - if (result == 65280) { - ptxinfo_in = fopen(tempfile_ptxinfo,"r"); - g_ptxinfo_filename = tempfile_ptxinfo; - ptxinfo_parse(); - - fix_duplicate_errors(fname2); - snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", - extra_flags, fname2, tempfile_ptxinfo); - printf("GPGPU-Sim PTX: regenerating ptxinfo using \"%s\"\n", commandline); - result = system(commandline); - } - if (result != 0) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); - printf(" Ensure ptxas is in your path.\n"); - exit(1); - } - } - } - - //TODO: duplicate code! move it into a function so that it can be reused! - if(no_of_ptx==0) { - //For CDP, we dump everything. So no_of_ptx will be 0. - snprintf(fname,1024,"_ptx_XXXXXX"); - int fd=mkstemp(fname); - close(fd); - - printf("GPGPU-Sim PTX: extracting embedded .ptx to temporary file \"%s\"\n", fname); - FILE *ptxfile = fopen(fname,"w"); - fprintf(ptxfile,"%s", p_for_info); - fclose(ptxfile); - - snprintf(fname2,1024,"_ptx2_XXXXXX"); - fd=mkstemp(fname2); - close(fd); - char commandline2[4096]; - snprintf(commandline2,4096,"cat %s | sed 's/.version 1.5/.version 1.4/' | sed 's/, texmode_independent//' | sed 's/\\(\\.extern \\.const\\[1\\] .b8 \\w\\+\\)\\[\\]/\\1\\[1\\]/' | sed 's/const\\[.\\]/const\\[0\\]/g' > %s", fname, fname2); - printf("Running: %s\n", commandline2); - int result = system(commandline2); - if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (a) %d\n", result); - printf(" Ensure you have write access to simulation directory\n"); - printf(" and have \'cat\' and \'sed\' in your path.\n"); - exit(1); - } - //char tempfile_ptxinfo[1024]; - snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); - char extra_flags[1024]; - extra_flags[0]=0; -#if CUDART_VERSION >= 3000 - snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); -#endif - - snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", - extra_flags, fname2, tempfile_ptxinfo); - printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); - result = system(commandline); - if( result != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); - printf(" Ensure ptxas is in your path.\n"); - exit(1); - } - } - - //Now that we got resource usage per kernel in a ptx file, we dump all into one file and pass it to rest of the code as usual. - if(no_of_ptx>0){ - char commandline3[4096]; - snprintf(final_tempfile_ptxinfo,1024,"f_tempfile_ptx"); - snprintf(commandline3,4096, "cat *info > %s", final_tempfile_ptxinfo); - if (system(commandline3)!=0) { - printf("ERROR: Either we dont have info files or cat is not working \n"); - printf("ERROR: %s command failed\n",commandline3); - exit(1); - } - } - - ptxinfo_in = fopen(final_tempfile_ptxinfo,"r"); - if(no_of_ptx>0) - g_ptxinfo_filename = final_tempfile_ptxinfo; - else - g_ptxinfo_filename = tempfile_ptxinfo; - ptxinfo_parse(); - - if( ! g_save_embedded_ptx ) { - if(no_of_ptx>0) - snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, final_tempfile_ptxinfo); - else - snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, tempfile_ptxinfo); - printf("GPGPU-Sim PTX: removing ptxinfo using \"%s\"\n", commandline); - if( system(commandline) != 0 ) { - printf("GPGPU-Sim PTX: ERROR ** while removing temporary files\n"); - exit(1); - } - } -} -- cgit v1.3 From 31ad7674de6dc4b25ba862bcd00b660fdb1a5cff Mon Sep 17 00:00:00 2001 From: Amruth Date: Wed, 4 Apr 2018 13:44:10 -0700 Subject: adding missing ptxas flags for cdp support --- README | 66 +++++++++++++++++++++++++++++++++++++++++++++ libcuda/cuda_runtime_api.cc | 4 +-- src/cuda-sim/ptx_loader.cc | 27 ++++++++++++------- 3 files changed, 85 insertions(+), 12 deletions(-) diff --git a/README b/README index 6e2d734..4426cdd 100644 --- a/README +++ b/README @@ -346,3 +346,69 @@ the applications you care about (implying these applications worked for you before you did the merge). You want to do this before making further changes to identify any compile time or runtime errors that occur due to the code merging process. + + +** Debugging failing GPGPU-Sim Regressions ** + +To debug failing GPGPU-Sim regression tests you need to run them locally. The fastest way to do this, assuming you are working with GPGPU-Sim versions more recent than the GPGPU-Sim dev branch circa March 28, 2018 (commit hash 2221d208a745a098a60b0d24c05007e92aaba092), is to install Docker. The instructions below were tested with Docker CE version 18.03 on Ubuntu and Mac OS. Docker will enable you to run the same set of regressions used by GPGPU-Sim when submitting a pull request to https://github.com/gpgpu-sim/gpgpu-sim_distribution and also allow you to log in and launch GPGPU-Sim in gdb so you can inspect failures. + +1. Install Docker. On Ubuntu 14.04 and 16.04 the following instructions work: https://docs.docker.com/install/linux/docker-ce/ubuntu/#uninstall-old-versions + +2. Clone GPGPU-Sim from your fork of GPGPU-Sim. For example: + + git clone https://github.com//gpgpu-sim_distribution.git + + +3. Run the following command (this is all one line) to run the regressions in docker: + + docker run --privileged -v `pwd`:/home/runner/gpgpu-sim_distribution:rw aamodt/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.gtx1080ti.yml -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress’; tail -f /dev/null" + +Explanation: The last part of this command, "tail -f /dev/null" will keep the docker container running after the regressions finish. This enables you to log into the container to run the same tests inside gdb so you can debug. The "--privileged" part enables you to use breakpoints inside gdb in a container. The "-v" part maps the current directory (with the GPGPU-Sim source code you want to test) into the container. The string "aamodt/gpgpu-sim_regress:latest" is a tag for a container setup to run regressions which will be downloaded from docker hub. The portion starting with /bin/bash is a set of commands run inside a bash shell inside the container. E.g., the command start_torque.sh starts up a queue manager inside the container. + +If the above command stops with the message "fatal: unable to access 'https://github.com/tgrogers/gpgpu-sim_simulations.git/': Could not resolve host: github.com" this likely means your computer sits behind a firewall which is blocking access to Google's name servers (e.g., 8.8.8.8). To get around this you will need to modify th above command to point to your local DNS server. Lookup your DNS server IP address which we will call below. On Ubuntu run "ifconfig" to lookup the network interface connecting your computer to the network. Then run "nmcli device show " to find the IP address of your DNS server. Modify the above command to include "--dns " after "run", E.g., + + docker run --dns --privileged -v `pwd`:/home/runner/gpgpu-sim_distribution:rw aamodt/gpgpu-sim_regress:latest /bin/bash -c "./start_torque.sh; chown -R runner /home/runner/gpgpu-sim_distribution; su - runner -c 'source /home/runner/gpgpu-sim_distribution/setup_environment && make -j -C /home/runner/gpgpu-sim_distribution && cd /home/runner/gpgpu-sim_simulations/ && git pull && /home/runner/gpgpu-sim_simulations/util/job_launching/run_simulations.py -c /home/runner/gpgpu-sim_simulations/util/job_launching/regression_recipies/rodinia_2.0-ft/configs.gtx1080ti.yml -N regress && /home/runner/gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress’; tail -f /dev/null" + +4. Find the CONTAINER ID associated with your docker container by running "docker ps". + +5. Log into the container by running the command: + + docker exec -it /bin/bash -c "su -l runner" + +The container is running Ubuntu 16.04 and has screen, cscope and vim installed (if you find a favorite Linux tool missing, it is fairly easy to create derived containers that have additional tools). + +6. Lookup the directory of the regression test you want to debug by going to the regression log file directory: + + cd /home/runner/gpgpu-sim_simulations/util/job_launching/logfiles + +7. The file "failed_job_log_sim_log.regress..txt" includes information about the failed test including its simulation directory. For the following example, I'll assume the first failing test was "hotspot-rodinia-2.0-ft-30_6_40___data_result_30_6_40_txt--GTX1080Ti" for which the simulation directory is /home/runner/gpgpu-sim_simulations/util/job_launching/../../sim_run_4.2/hotspot-rodinia-2.0-ft/30_6_40___data_result_30_6_40_txt/GTX1080Ti/ + +8. Change to the simulation directory using: + + cd + +E.g., "cd /home/runner/gpgpu-sim_simulations/util/job_launching/../../sim_run_4.2/hotspot-rodinia-2.0-ft/30_6_40___data_result_30_6_40_txt/GTX1080Ti/" + +This directory should contain a file called "torque.sim" that contains commands used to launch the simulation during regression tests. We will modify this file to enable us to re-run the regression test in gdb. This directory should also contain a file containing the standard output during the regression test. This file will end in .o where is the torque queue manager job number. For the running example for me this file is called "hotspot-rodinia-2.0-ft-30_6_40___data_result_30_6_40_txt.o2". Open this file to determine the LD_LIBRARY_PATH settings used when launching the simulation. Look for a line that starts "doing: export LD_LIBRARY_PATH" and copy the entire line starting with "export LD_LIBRARY_PATH ..." + +9. Paste the "export LD_LIBRARY_PATH ..." line into the bash shell to set LD_LIBRARY_PATH. E.g., + + export LD_LIBRARY_PATH=/home/runner/gpgpu-sim_simulations/util/job_launching/../../sim_run_4.2/gpgpu-sim-builds/libcudart_gpgpu-sim_git-commit-177d02254ae38b6331b17dd6cd139b570a03c589_modified_0.so:/gpgpu-sim/usr/local/gcc-4.5.4/lib64:/gpgpu-sim/usr/local/gcc-4.5.4/lib:/gpgpu-sim/usr/local/gcc-4.5.4/lib/gcc/x86_64-unknown-linux-gnu/lib64/:/gpgpu-sim/usr/local/gcc-4.5.4/lib/gcc/x86_64-unknown-linux-gnu/4.5.4/:/usr/lib/x86_64-linux-gnu:/home/runner/gpgpu-sim_distribution/lib/gcc-4.5.4/cuda-4020/release:/gpgpu-sim/usr/local/gcc-4.5.4/lib64:/gpgpu-sim/usr/local/gcc-4.5.4/lib:/gpgpu-sim/usr/local/gcc-4.5.4/lib/gcc/x86_64-unknown-linux-gnu/lib64/:/gpgpu-sim/usr/local/gcc-4.5.4/lib/gcc/x86_64-unknown-linux-gnu/4.5.4/:/usr/lib/x86_64-linux-gnu: + +10. In the same shell, build the debug version of GPGPU-Sim then return to the directory above: + + pushd ~/gpgpu-sim_distribution/ + source setup_environment debug + make + popd + +11. Open and edit torque.sim and preface the very last line with "gdb --args ". After editing the last line in torque.sim should look something like: + + gdb --args /home/runner/gpgpu-sim_simulations/util/job_launching/../../benchmarks/bin/4.2/release/hotspot-rodinia-2.0-ft 30 6 40 ./data/result_30_6_40.txt + +12. Re-run the regression test in gdb by sourcing the torque.sim file: + + . torque.sim + +This will put you in at the (gdb) prompt. Setup any breakpoints needed and run. + diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index ded1aee..c103244 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1085,8 +1085,8 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetStreamPriorityRange(int* leastPriori return cudaSuccess; } -__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *pStream, unsigned int flags) { - return cudaStreamCreate(pStream); +__host__ __device__ cudaError_t CUDARTAPI cudaStreamCreateWithFlags(cudaStream_t *stream, unsigned int flags) { + return cudaStreamCreate(stream); } __host__ cudaError_t CUDARTAPI cudaStreamDestroy(cudaStream_t stream) diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 34870c4..7863be4 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -353,11 +353,7 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num #if CUDART_VERSION >= 3000 if (sm_version == 0) sm_version = 20; - extern bool g_cdp_enabled; - if(!g_cdp_enabled) - snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); - else - snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version); + snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); #endif snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", @@ -414,9 +410,15 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num snprintf(tempfile_ptxinfo,1024,"%sinfo",fname); char extra_flags[1024]; extra_flags[0]=0; -#if CUDART_VERSION >= 3000 - snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); -#endif + + #if CUDART_VERSION >= 3000 + if (sm_version == 0) sm_version = 20; + extern bool g_cdp_enabled; + if(!g_cdp_enabled) + snprintf(extra_flags,1024,"--gpu-name=sm_%u",sm_version); + else + snprintf(extra_flags,1024,"--compile-only --gpu-name=sm_%u",sm_version); + #endif snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", extra_flags, fname2, tempfile_ptxinfo); @@ -448,11 +450,16 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num g_ptxinfo_filename = tempfile_ptxinfo; ptxinfo_parse(); + snprintf(commandline,1024,"rm -f *info"); + if( system(commandline) != 0 ) { + printf("GPGPU-Sim PTX: ERROR ** while removing temporary info files\n"); + exit(1); + } if( ! g_save_embedded_ptx ) { if(no_of_ptx>0) - snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, final_tempfile_ptxinfo); + snprintf(commandline,1024,"rm -f %s %s %s", fname, fname2, final_tempfile_ptxinfo); else - snprintf(commandline,1024,"rm -f %s %s %s *info", fname, fname2, tempfile_ptxinfo); + snprintf(commandline,1024,"rm -f %s %s %s", fname, fname2, tempfile_ptxinfo); printf("GPGPU-Sim PTX: removing ptxinfo using \"%s\"\n", commandline); if( system(commandline) != 0 ) { printf("GPGPU-Sim PTX: ERROR ** while removing temporary files\n"); -- cgit v1.3 From 335bb4b38974b1843e1786c5d86b0fcf2a7943c8 Mon Sep 17 00:00:00 2001 From: Amruth Date: Wed, 4 Apr 2018 16:01:32 -0700 Subject: Prog gets stuck because it doesnt recieve EOF --- src/cuda-sim/ptx_loader.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 7863be4..03ea31a 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -448,6 +448,9 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num g_ptxinfo_filename = final_tempfile_ptxinfo; else g_ptxinfo_filename = tempfile_ptxinfo; + + //The program might get stuck because the parser didnt receive a EOF. + printf("NOTE: If the program is stuck, please press ctrl+d for ubuntu and ctrl+z for windows users \n"); ptxinfo_parse(); snprintf(commandline,1024,"rm -f *info"); -- cgit v1.3 From 69c57b077d6799f46ad43b99cc0e0049b7c43775 Mon Sep 17 00:00:00 2001 From: Amruth Date: Wed, 4 Apr 2018 16:06:42 -0700 Subject: updating EOF condition for Mac users --- src/cuda-sim/ptx_loader.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 03ea31a..4ddc6bf 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -450,7 +450,7 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num g_ptxinfo_filename = tempfile_ptxinfo; //The program might get stuck because the parser didnt receive a EOF. - printf("NOTE: If the program is stuck, please press ctrl+d for ubuntu and ctrl+z for windows users \n"); + printf("NOTE: If the program is stuck, please press ctrl+d for Ubuntu/Mac and ctrl+z for Windows users \n"); ptxinfo_parse(); snprintf(commandline,1024,"rm -f *info"); -- cgit v1.3 From 49429d3b01dcb5bac49b71df2156bceb70b64ce9 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Thu, 5 Apr 2018 10:10:15 -0400 Subject: GPGPU-Sim should always print when the sim thread exits - if this doesn't happen, something bad has happened --- src/gpgpusim_entrypoint.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index dac9fd8..64962ab 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -165,10 +165,10 @@ void *gpgpu_sim_thread_concurrent(void*) g_sim_active = false; pthread_mutex_unlock(&g_sim_lock); } while( !g_sim_done ); - if(g_debug_execution >= 3) { - printf("GPGPU-Sim: *** simulation thread exiting ***\n"); - fflush(stdout); - } + + printf("GPGPU-Sim: *** simulation thread exiting ***\n"); + fflush(stdout); + if(break_limit) { printf("GPGPU-Sim: ** break due to reaching the maximum cycles (or instructions) **\n"); exit(1); -- cgit v1.3 From 60a32420caa0e79c7d5133ff67a55c02333b1dc2 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 28 Mar 2018 14:00:16 -0400 Subject: adding new counters for parition level para and L2 BW --- src/gpgpu-sim/gpu-sim.cc | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 0ef267d..95951a8 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -88,6 +88,12 @@ unsigned long long gpu_tot_sim_cycle = 0; // performance counter for stalls due to congestion. unsigned int gpu_stall_dramfull = 0; unsigned int gpu_stall_icnt2sh = 0; +unsigned long long partiton_reqs_in_parallel = 0; +unsigned long long partiton_reqs_in_parallel_total = 0; +unsigned long long partiton_reqs_in_parallel_util = 0; +unsigned long long partiton_reqs_in_parallel_util_total = 0; +unsigned long long partiton_replys_in_parallel = 0; +unsigned long long partiton_replys_in_parallel_total = 0; /* Clock Domains */ @@ -745,6 +751,9 @@ void gpgpu_sim::init() gpu_sim_insn = 0; last_gpu_sim_insn = 0; m_total_cta_launched=0; + partiton_reqs_in_parallel = 0; + partiton_replys_in_parallel = 0; + partiton_reqs_in_parallel_util = 0; reinit_clock_domains(); set_param_gpgpu_num_shaders(m_config.num_shader()); @@ -781,8 +790,14 @@ void gpgpu_sim::update_stats() { gpu_tot_sim_cycle += gpu_sim_cycle; gpu_tot_sim_insn += gpu_sim_insn; gpu_tot_issued_cta += m_total_cta_launched; + partiton_reqs_in_parallel_total += partiton_reqs_in_parallel; + partiton_replys_in_parallel_total += partiton_replys_in_parallel; + partiton_reqs_in_parallel_util_total += partiton_reqs_in_parallel_util; gpu_sim_cycle = 0; + partiton_reqs_in_parallel = 0; + partiton_replys_in_parallel = 0; + partiton_reqs_in_parallel_util = 0; gpu_sim_insn = 0; m_total_cta_launched = 0; } @@ -966,6 +981,19 @@ void gpgpu_sim::gpu_print_stat() printf("gpu_stall_dramfull = %d\n", gpu_stall_dramfull); printf("gpu_stall_icnt2sh = %d\n", gpu_stall_icnt2sh ); + printf("partiton_reqs_in_parallel = %lld\n", partiton_reqs_in_parallel); + printf("partiton_reqs_in_parallel_total = %lld\n", partiton_reqs_in_parallel_total ); + printf("partiton_level_parallism = %12.4f\n", (float)partiton_reqs_in_parallel / gpu_sim_cycle); + printf("partiton_level_parallism_total = %12.4f\n", (float)(partiton_reqs_in_parallel+partiton_reqs_in_parallel_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); + printf("partiton_reqs_in_parallel_util = %lld\n", partiton_reqs_in_parallel_util); + printf("partiton_reqs_in_parallel_util_total = %lld\n", partiton_reqs_in_parallel_util_total ); + printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle); + printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); + printf("partiton_replys_in_parallel = %lld\n", partiton_replys_in_parallel); + printf("partiton_replys_in_parallel_total = %lld\n", partiton_replys_in_parallel_total ); + printf("L2_BW = %12.4f GB/Sec\n", ((float)(partiton_replys_in_parallel * 32) / (gpu_sim_cycle * m_config.icnt_period)) / 1000000000); + printf("L2_BW_total = %12.4f GB/Sec\n", ((float)((partiton_replys_in_parallel+partiton_replys_in_parallel_total) * 32) / ((gpu_tot_sim_cycle+gpu_sim_cycle) * m_config.icnt_period)) / 1000000000 ); + time_t curr_time; time(&curr_time); unsigned long long elapsed_time = MAX( curr_time - g_simulation_starttime, 1 ); @@ -1367,6 +1395,7 @@ void gpgpu_sim::cycle() for (unsigned i=0;in_simt_clusters;i++) m_cluster[i]->icnt_cycle(); } + unsigned partiton_replys_in_parallel_per_cycle = 0; if (clock_mask & ICNT) { // pop from memory controller to interconnect for (unsigned i=0;im_n_mem_sub_partition;i++) { @@ -1379,6 +1408,7 @@ void gpgpu_sim::cycle() mf->set_status(IN_ICNT_TO_SHADER,gpu_sim_cycle+gpu_tot_sim_cycle); ::icnt_push( m_shader_config->mem2device(i), mf->get_tpc(), mf, response_size ); m_memory_sub_partition[i]->pop(); + partiton_replys_in_parallel_per_cycle++; } else { gpu_stall_icnt2sh++; } @@ -1387,6 +1417,7 @@ void gpgpu_sim::cycle() } } } + partiton_replys_in_parallel += partiton_replys_in_parallel_per_cycle; if (clock_mask & DRAM) { for (unsigned i=0;im_n_mem;i++){ @@ -1399,6 +1430,7 @@ void gpgpu_sim::cycle() } // L2 operations follow L2 clock domain + unsigned partiton_reqs_in_parallel_per_cycle = 0; if (clock_mask & L2) { m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].clear(); for (unsigned i=0;im_n_mem_sub_partition;i++) { @@ -1409,11 +1441,15 @@ void gpgpu_sim::cycle() } else { mem_fetch* mf = (mem_fetch*) icnt_pop( m_shader_config->mem2device(i) ); m_memory_sub_partition[i]->push( mf, gpu_sim_cycle + gpu_tot_sim_cycle ); + partiton_reqs_in_parallel_per_cycle++; } m_memory_sub_partition[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle); m_memory_sub_partition[i]->accumulate_L2cache_stats(m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX]); } } + partiton_reqs_in_parallel += partiton_reqs_in_parallel_per_cycle; + if(partiton_reqs_in_parallel_per_cycle > 0) + partiton_reqs_in_parallel_util += partiton_reqs_in_parallel_per_cycle; if (clock_mask & ICNT) { icnt_transfer(); -- cgit v1.3 From 038df10118351d44f8950065ddeb698ae3e390a1 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Wed, 28 Mar 2018 15:22:33 -0400 Subject: adding new stats counter --- src/gpgpu-sim/gpu-sim.cc | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 95951a8..da35dc3 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -92,6 +92,8 @@ unsigned long long partiton_reqs_in_parallel = 0; unsigned long long partiton_reqs_in_parallel_total = 0; unsigned long long partiton_reqs_in_parallel_util = 0; unsigned long long partiton_reqs_in_parallel_util_total = 0; +unsigned long long gpu_sim_cycle_parition_util = 0; +unsigned long long gpu_tot_sim_cycle_parition_util = 0; unsigned long long partiton_replys_in_parallel = 0; unsigned long long partiton_replys_in_parallel_total = 0; @@ -754,6 +756,7 @@ void gpgpu_sim::init() partiton_reqs_in_parallel = 0; partiton_replys_in_parallel = 0; partiton_reqs_in_parallel_util = 0; + gpu_sim_cycle_parition_util = 0; reinit_clock_domains(); set_param_gpgpu_num_shaders(m_config.num_shader()); @@ -793,11 +796,14 @@ void gpgpu_sim::update_stats() { partiton_reqs_in_parallel_total += partiton_reqs_in_parallel; partiton_replys_in_parallel_total += partiton_replys_in_parallel; partiton_reqs_in_parallel_util_total += partiton_reqs_in_parallel_util; + gpu_tot_sim_cycle_parition_util += gpu_sim_cycle_parition_util ; gpu_sim_cycle = 0; partiton_reqs_in_parallel = 0; partiton_replys_in_parallel = 0; partiton_reqs_in_parallel_util = 0; + gpu_sim_cycle_parition_util = 0; + gpu_tot_sim_cycle = 0; gpu_sim_insn = 0; m_total_cta_launched = 0; } @@ -987,8 +993,10 @@ void gpgpu_sim::gpu_print_stat() printf("partiton_level_parallism_total = %12.4f\n", (float)(partiton_reqs_in_parallel+partiton_reqs_in_parallel_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); printf("partiton_reqs_in_parallel_util = %lld\n", partiton_reqs_in_parallel_util); printf("partiton_reqs_in_parallel_util_total = %lld\n", partiton_reqs_in_parallel_util_total ); - printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle); - printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) ); + printf("gpu_sim_cycle_parition_util = %lld\n", gpu_sim_cycle_parition_util); + printf("gpu_tot_sim_cycle_parition_util = %lld\n", gpu_tot_sim_cycle_parition_util ); + printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle_parition_util); + printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_sim_cycle_parition_util+gpu_tot_sim_cycle_parition_util) ); printf("partiton_replys_in_parallel = %lld\n", partiton_replys_in_parallel); printf("partiton_replys_in_parallel_total = %lld\n", partiton_replys_in_parallel_total ); printf("L2_BW = %12.4f GB/Sec\n", ((float)(partiton_replys_in_parallel * 32) / (gpu_sim_cycle * m_config.icnt_period)) / 1000000000); @@ -1448,8 +1456,10 @@ void gpgpu_sim::cycle() } } partiton_reqs_in_parallel += partiton_reqs_in_parallel_per_cycle; - if(partiton_reqs_in_parallel_per_cycle > 0) + if(partiton_reqs_in_parallel_per_cycle > 0){ partiton_reqs_in_parallel_util += partiton_reqs_in_parallel_per_cycle; + gpu_sim_cycle_parition_util++; + } if (clock_mask & ICNT) { icnt_transfer(); -- cgit v1.3 From cfab001e7c65541eaf8f7573bbf4a2e5d69f296e Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Fri, 30 Mar 2018 11:27:57 -0400 Subject: fixing gpu-tot-cycle bug --- src/gpgpu-sim/gpu-sim.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index da35dc3..550c550 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -803,7 +803,6 @@ void gpgpu_sim::update_stats() { partiton_replys_in_parallel = 0; partiton_reqs_in_parallel_util = 0; gpu_sim_cycle_parition_util = 0; - gpu_tot_sim_cycle = 0; gpu_sim_insn = 0; m_total_cta_launched = 0; } -- cgit v1.3 From d2ae7fb6889cf622673ce1c0d6696d2984963946 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Thu, 5 Apr 2018 11:27:17 -0400 Subject: Nice to know when the simulaton thread actually gets the exit call under normal operation. This helps immensely in a clustered environmrnt where jobs randomly fail --- src/gpgpusim_entrypoint.cc | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index dac9fd8..52e2f5e 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -93,8 +93,15 @@ bool g_sim_active = false; bool g_sim_done = true; bool break_limit = false; +static void termination_callback() +{ + printf("GPGPU-Sim: *** exit detected ***\n"); + fflush(stdout); +} + void *gpgpu_sim_thread_concurrent(void*) { + atexit(termination_callback); // concurrent kernel execution simulation thread do { if(g_debug_execution >= 3) { @@ -165,10 +172,10 @@ void *gpgpu_sim_thread_concurrent(void*) g_sim_active = false; pthread_mutex_unlock(&g_sim_lock); } while( !g_sim_done ); - if(g_debug_execution >= 3) { - printf("GPGPU-Sim: *** simulation thread exiting ***\n"); - fflush(stdout); - } + + printf("GPGPU-Sim: *** simulation thread exiting ***\n"); + fflush(stdout); + if(break_limit) { printf("GPGPU-Sim: ** break due to reaching the maximum cycles (or instructions) **\n"); exit(1); -- cgit v1.3 From 913c8934d89068ea96729b238a42879d2e02e7f4 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Thu, 5 Apr 2018 11:27:17 -0400 Subject: Nice to know when the simulaton thread actually gets the exit call under normal operation. This helps immensely in a clustered environmrnt where jobs randomly fail --- src/gpgpusim_entrypoint.cc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index 64962ab..ede9f20 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -93,8 +93,15 @@ bool g_sim_active = false; bool g_sim_done = true; bool break_limit = false; +static void termination_callback() +{ + printf("GPGPU-Sim: *** exit detected ***\n"); + fflush(stdout); +} + void *gpgpu_sim_thread_concurrent(void*) { + atexit(termination_callback); // concurrent kernel execution simulation thread do { if(g_debug_execution >= 3) { @@ -165,7 +172,6 @@ void *gpgpu_sim_thread_concurrent(void*) g_sim_active = false; pthread_mutex_unlock(&g_sim_lock); } while( !g_sim_done ); - printf("GPGPU-Sim: *** simulation thread exiting ***\n"); fflush(stdout); -- cgit v1.3 From e1dc8113aa2a51885541f96943bd8d90eaccd968 Mon Sep 17 00:00:00 2001 From: Amruth Date: Thu, 5 Apr 2018 16:31:44 -0700 Subject: fixing file pointer and attributes issues --- README | 1 + libcuda/cuda_runtime_api.cc | 34 ++++++++++++++++++++++++++++++++-- src/cuda-sim/cuda-sim.cc | 1 + src/cuda-sim/ptx_loader.cc | 5 ++--- 4 files changed, 36 insertions(+), 5 deletions(-) diff --git a/README b/README index 4426cdd..543177c 100644 --- a/README +++ b/README @@ -349,6 +349,7 @@ process. ** Debugging failing GPGPU-Sim Regressions ** +Credits: Tor M Aamodt To debug failing GPGPU-Sim regression tests you need to run them locally. The fastest way to do this, assuming you are working with GPGPU-Sim versions more recent than the GPGPU-Sim dev branch circa March 28, 2018 (commit hash 2221d208a745a098a60b0d24c05007e92aaba092), is to install Docker. The instructions below were tested with Docker CE version 18.03 on Ubuntu and Mac OS. Docker will enable you to run the same set of regressions used by GPGPU-Sim when submitting a pull request to https://github.com/gpgpu-sim/gpgpu-sim_distribution and also allow you to log in and launch GPGPU-Sim in gdb so you can inspect failures. diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index c103244..3fd88dc 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -349,7 +349,15 @@ class _cuda_device_id *GPGPUSim_Init() prop->maxGridSize[2] = 0x40000000; prop->totalConstMem = 0x40000000; prop->textureAlignment = 0; - prop->sharedMemPerBlock = the_gpu->shared_mem_size(); + /* + * TODO: Update the .config and xml files of all GPU config files with new value of sharedMemPerBlock. + * Previously, this was thought as sharedMemPerMultiprocessor and is being used in many places. + * Check whether all the instances of shared_mem_size(), gpgpu_shmem_size or sharedMemPerBlock are meant to use sharedMemPerBlock or sharedMemPerMultiprocessor. + */ + prop->sharedMemPerBlock = 49152; +#if (CUDART_VERSION > 5000) + prop->sharedMemPerMultiprocessor = the_gpu->shared_mem_size(); +#endif prop->regsPerBlock = the_gpu->num_registers_per_core(); prop->warpSize = the_gpu->wrp_size(); prop->clockRate = the_gpu->shader_clock(); @@ -840,6 +848,15 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic if (device <= dev->num_devices() ) { prop = dev->get_prop(); switch (attr) { + case 2: + *value= prop->maxThreadsDim[0]; + break; + case 3: + *value= prop->maxThreadsDim[1]; + break; + case 4: + *value= prop->maxThreadsDim[2]; + break; case 5: *value= prop->maxGridSize[0]; break; @@ -849,6 +866,12 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 7: *value= prop->maxGridSize[2]; break; + case 8: + *value= prop->sharedMemPerBlock; + break; + case 9: + *value= prop->totalConstMem; + break; case 10: *value= prop->warpSize; break; @@ -861,11 +884,14 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 16: *value= prop->multiProcessorCount ; break; + case 34: + *value= 0; + break; case 39: *value= dev->get_gpgpu()->threads_per_core(); break; case 75: - *value= 8 ; + *value= 9 ; break; case 76: *value= 3 ; @@ -873,6 +899,9 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 78: *value= 0 ; //TODO: as of now, we dont support stream priorities. break; + case 81: + *value= prop->sharedMemPerMultiprocessor; + break; default: printf("ERROR: implement the attribute numbered %d \n",attr); abort(); @@ -1882,6 +1911,7 @@ void cuobjdumpParseBinary(unsigned int handle){ if (capability > max_capability) max_capability = capability; } if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); + max_capability=context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index dce35ca..b1eaf01 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -2155,3 +2155,4 @@ void functionalCoreSim::warp_exit( unsigned warp_id ) } } } + diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc index 4ddc6bf..33a4260 100644 --- a/src/cuda-sim/ptx_loader.cc +++ b/src/cuda-sim/ptx_loader.cc @@ -423,6 +423,7 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num snprintf(commandline,1024,"$CUDA_INSTALL_PATH/bin/ptxas %s -v %s --output-file /dev/null 2> %s", extra_flags, fname2, tempfile_ptxinfo); printf("GPGPU-Sim PTX: generating ptxinfo using \"%s\"\n", commandline); + fflush(stdout); result = system(commandline); if( result != 0 ) { printf("GPGPU-Sim PTX: ERROR ** while loading PTX (b) %d\n", result); @@ -443,14 +444,12 @@ void gpgpu_ptxinfo_load_from_string( const char *p_for_info, unsigned source_num } } - ptxinfo_in = fopen(final_tempfile_ptxinfo,"r"); if(no_of_ptx>0) g_ptxinfo_filename = final_tempfile_ptxinfo; else g_ptxinfo_filename = tempfile_ptxinfo; + ptxinfo_in = fopen(g_ptxinfo_filename,"r"); - //The program might get stuck because the parser didnt receive a EOF. - printf("NOTE: If the program is stuck, please press ctrl+d for Ubuntu/Mac and ctrl+z for Windows users \n"); ptxinfo_parse(); snprintf(commandline,1024,"rm -f *info"); -- cgit v1.3 From 2f9cdd0ac0954bae8822d0cfdb68fa4173087c1b Mon Sep 17 00:00:00 2001 From: Amruth Date: Fri, 6 Apr 2018 11:22:48 -0700 Subject: fixing arch flags --- libcuda/cuda_runtime_api.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 3fd88dc..184325c 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1911,7 +1911,7 @@ void cuobjdumpParseBinary(unsigned int handle){ if (capability > max_capability) max_capability = capability; } if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); - max_capability=context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); + //max_capability=context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); -- cgit v1.3 From 6c9555d42f3ab7f11dd003a9271d0c7e0ad21031 Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Mon, 9 Apr 2018 12:42:20 -0500 Subject: adding additional device attributes in cudaDeviceGetAttributes function for mnist --- libcuda/cuda_runtime_api.cc | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index c103244..bcc3e14 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -840,7 +840,16 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic if (device <= dev->num_devices() ) { prop = dev->get_prop(); switch (attr) { - case 5: + case 2: + *value= prop->maxThreadsDim[0]; + break; + case 3: + *value= prop->maxThreadsDim[1]; + break; + case 4: + *value= prop->maxThreadsDim[2]; + break; + case 5: *value= prop->maxGridSize[0]; break; case 6: @@ -849,6 +858,9 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 7: *value= prop->maxGridSize[2]; break; + case 8: + *value= prop->sharedMemPerBlock; + break; case 10: *value= prop->warpSize; break; @@ -873,6 +885,12 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 78: *value= 0 ; //TODO: as of now, we dont support stream priorities. break; + case 81: + *value= prop->sharedMemPerBlock; + break; + case 82: + *value= prop->regsPerBlock; + break; default: printf("ERROR: implement the attribute numbered %d \n",attr); abort(); -- cgit v1.3 From 960a1492fbbf2a4d098c8d060bc22782211ca60b Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Tue, 10 Apr 2018 14:52:49 -0500 Subject: added config -gpgpu_shmem_per_block and fixed cudaGetDeviceAttributes function --- libcuda/cuda_runtime_api.cc | 31 +++++++++++++++++++++++++++---- src/gpgpu-sim/gpu-sim.cc | 8 ++++++++ src/gpgpu-sim/gpu-sim.h | 1 + src/gpgpu-sim/shader.h | 2 +- 4 files changed, 37 insertions(+), 5 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index bcc3e14..d6ce4e0 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -349,7 +349,24 @@ class _cuda_device_id *GPGPUSim_Init() prop->maxGridSize[2] = 0x40000000; prop->totalConstMem = 0x40000000; prop->textureAlignment = 0; - prop->sharedMemPerBlock = the_gpu->shared_mem_size(); + /* + + * TODO: Update the .config and xml files of all GPU config files with new value of sharedMemPerBlock. + + * Previously, this was thought as sharedMemPerMultiprocessor and is being used in many places. + + * Check whether all the instances of shared_mem_size(), gpgpu_shmem_size or sharedMemPerBlock are meant to use sharedMemPerBlock or sharedMemPerMultiprocessor. + + */ + + prop->sharedMemPerBlock = the_gpu->shared_mem_per_block(); + + #if (CUDART_VERSION > 5000) + + prop->sharedMemPerMultiprocessor = the_gpu->shared_mem_size(); + + #endif + prop->regsPerBlock = the_gpu->num_registers_per_core(); prop->warpSize = the_gpu->wrp_size(); prop->clockRate = the_gpu->shader_clock(); @@ -861,6 +878,9 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 8: *value= prop->sharedMemPerBlock; break; + case 9: + *value= prop->totalConstMem; + break; case 10: *value= prop->warpSize; break; @@ -873,11 +893,14 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 16: *value= prop->multiProcessorCount ; break; + case 34: + *value= 0; + break; case 39: *value= dev->get_gpgpu()->threads_per_core(); break; case 75: - *value= 8 ; + *value= 9 ; break; case 76: *value= 3 ; @@ -886,13 +909,13 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic *value= 0 ; //TODO: as of now, we dont support stream priorities. break; case 81: - *value= prop->sharedMemPerBlock; + *value= prop->sharedMemPerMultiprocessor; break; case 82: *value= prop->regsPerBlock; break; default: - printf("ERROR: implement the attribute numbered %d \n",attr); + printf("ERROR: Attribute number %d unimplemented \n",attr); abort(); } return g_last_cudaError = cudaSuccess; diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 3829861..5d63ab7 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -265,6 +265,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_n_ldst_response_buffer_size", OPT_UINT32, &ldst_unit_response_queue_size, "number of response packets in ld/st unit ejection buffer", "2"); + option_parser_register(opp, "-gpgpu_shmem_per_block", OPT_UINT32, &gpgpu_shmem_per_block, + "Size of shared memory per thread block or CTA (default 48kB)", + "49152"); option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size, "Size of shared memory per shader core (default 16kB)", "16384"); @@ -661,6 +664,11 @@ int gpgpu_sim::shared_mem_size() const return m_shader_config->gpgpu_shmem_size; } +int gpgpu_sim::shared_mem_per_block() const +{ + return m_shader_config->gpgpu_shmem_per_block; +} + int gpgpu_sim::num_registers_per_core() const { return m_shader_config->gpgpu_shader_registers; diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 7d92c66..8d1c4fc 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -389,6 +389,7 @@ public: void get_pdom_stack_top_info( unsigned sid, unsigned tid, unsigned *pc, unsigned *rpc ); int shared_mem_size() const; + int shared_mem_per_block() const; int num_registers_per_core() const; int wrp_size() const; int shader_clock() const; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index bdd8dbe..fbddd18 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1285,7 +1285,7 @@ struct shader_core_config : public core_config unsigned max_cta_per_core; //Limit on number of concurrent CTAs in shader core unsigned max_barriers_per_cta; char * gpgpu_scheduler_string; - + unsigned gpgpu_shmem_per_block; char* pipeline_widths_string; int pipe_widths[N_PIPELINE_STAGES]; -- cgit v1.3 From c99a4ff88ecf7f69715939d96c1fa8152eee524c Mon Sep 17 00:00:00 2001 From: Amruth Date: Wed, 11 Apr 2018 11:05:12 -0700 Subject: PDOM analysis for child kernel in CDP --- src/cuda-sim/cuda_device_runtime.cc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc index 4a8ffe5..b399133 100644 --- a/src/cuda-sim/cuda_device_runtime.cc +++ b/src/cuda-sim/cuda_device_runtime.cc @@ -177,6 +177,20 @@ void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * //device_grid = op.grid; device_kernel_entry = config.entry; DEV_RUNTIME_REPORT("find device kernel " << device_kernel_entry->get_name()); + + //PDOM analysis is done for Parent kernel but not for child kernel. + if (device_kernel_entry->is_pdom_set()) { + printf("GPGPU-Sim PTX: PDOM analysis already done for %s \n", device_kernel_entry->get_name().c_str() ); + } else { + printf("GPGPU-Sim PTX: finding reconvergence points for \'%s\'...\n", device_kernel_entry->get_name().c_str() ); + /* + * Some of the instructions like printf() gives the gpgpusim the wrong impression that it is a function call. + * As printf() doesnt have a body like functions do, doing pdom analysis for printf() causes a crash. + */ + if (device_kernel_entry->get_function_size() >0) + device_kernel_entry->do_pdom(); + device_kernel_entry->set_pdom(); + } //copy data in parameter_buffer to device kernel param memory unsigned device_kernel_arg_size = device_kernel_entry->get_args_aligned_size(); -- cgit v1.3 From f118b10cc49bf771755f2afdee04cde0359d745e Mon Sep 17 00:00:00 2001 From: Amruth Date: Wed, 11 Apr 2018 12:07:34 -0700 Subject: clean up --- libcuda/cuda_runtime_api.cc | 36 +++--------------------------------- src/cuda-sim/cuda-sim.cc | 1 - 2 files changed, 3 insertions(+), 34 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 184325c..abdc345 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -349,15 +349,7 @@ class _cuda_device_id *GPGPUSim_Init() prop->maxGridSize[2] = 0x40000000; prop->totalConstMem = 0x40000000; prop->textureAlignment = 0; - /* - * TODO: Update the .config and xml files of all GPU config files with new value of sharedMemPerBlock. - * Previously, this was thought as sharedMemPerMultiprocessor and is being used in many places. - * Check whether all the instances of shared_mem_size(), gpgpu_shmem_size or sharedMemPerBlock are meant to use sharedMemPerBlock or sharedMemPerMultiprocessor. - */ - prop->sharedMemPerBlock = 49152; -#if (CUDART_VERSION > 5000) - prop->sharedMemPerMultiprocessor = the_gpu->shared_mem_size(); -#endif + prop->sharedMemPerBlock = the_gpu->shared_mem_size(); prop->regsPerBlock = the_gpu->num_registers_per_core(); prop->warpSize = the_gpu->wrp_size(); prop->clockRate = the_gpu->shader_clock(); @@ -848,17 +840,8 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic if (device <= dev->num_devices() ) { prop = dev->get_prop(); switch (attr) { - case 2: - *value= prop->maxThreadsDim[0]; - break; - case 3: - *value= prop->maxThreadsDim[1]; - break; - case 4: - *value= prop->maxThreadsDim[2]; - break; case 5: - *value= prop->maxGridSize[0]; + *value= prop->maxGridSize[1]; break; case 6: *value= prop->maxGridSize[1]; @@ -866,12 +849,6 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 7: *value= prop->maxGridSize[2]; break; - case 8: - *value= prop->sharedMemPerBlock; - break; - case 9: - *value= prop->totalConstMem; - break; case 10: *value= prop->warpSize; break; @@ -884,14 +861,11 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 16: *value= prop->multiProcessorCount ; break; - case 34: - *value= 0; - break; case 39: *value= dev->get_gpgpu()->threads_per_core(); break; case 75: - *value= 9 ; + *value= 8 ; break; case 76: *value= 3 ; @@ -899,9 +873,6 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic case 78: *value= 0 ; //TODO: as of now, we dont support stream priorities. break; - case 81: - *value= prop->sharedMemPerMultiprocessor; - break; default: printf("ERROR: implement the attribute numbered %d \n",attr); abort(); @@ -1911,7 +1882,6 @@ void cuobjdumpParseBinary(unsigned int handle){ if (capability > max_capability) max_capability = capability; } if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); - //max_capability=context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index b1eaf01..dce35ca 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -2155,4 +2155,3 @@ void functionalCoreSim::warp_exit( unsigned warp_id ) } } } - -- cgit v1.3 From f052807cd6acfaf3221fbfe40ab905fd3aeaf2ef Mon Sep 17 00:00:00 2001 From: Amruth Date: Wed, 11 Apr 2018 19:11:47 +0000 Subject: cuda_runtime_api.cc edited online with Bitbucket --- libcuda/cuda_runtime_api.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index abdc345..dd32654 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -5,7 +5,7 @@ /* * cuda_runtime_api.cc * - * Copyright © 2009 by Tor M. Aamodt, Wilson W. L. Fung, Ali Bakhoda, + * Copyright © 2009 by Tor M. Aamodt, Wilson W. L. Fung, Ali Bakhoda, * George L. Yuan and the University of British Columbia, Vancouver, * BC V6T 1Z4, All Rights Reserved. * @@ -841,7 +841,7 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic prop = dev->get_prop(); switch (attr) { case 5: - *value= prop->maxGridSize[1]; + *value= prop->maxGridSize[0]; break; case 6: *value= prop->maxGridSize[1]; -- cgit v1.3 From 89094df5b4e861b104393ea0f41886494a7f26a4 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 11 Apr 2018 15:46:01 -0400 Subject: This build status line was broken when there were cached files --- setup_environment | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/setup_environment b/setup_environment index 96cc362..3f2476e 100644 --- a/setup_environment +++ b/setup_environment @@ -8,7 +8,8 @@ export GPGPUSIM_ROOT="$( cd "$( dirname "$BASH_SOURCE" )" && pwd )" GPGPUSIM_VERSION_STRING=`cat $GPGPUSIM_ROOT/version | awk '/Version/ {print $8}'` #Detect Git branch and commit # GIT_COMMIT=`git log -n 1 | head -1 | sed -re 's/commit (.*)/\1/'` -GIT_FILES_CHANGED=`git diff --numstat --cached && git diff --numstat | wc | sed -re 's/^\s+([0-9]+).*/\1/'` +GIT_FILES_CHANGED=`git diff --numstat | wc | sed -re 's/^\s+([0-9]+).*/\1./'` +GIT_FILES_CHANGED+=`git diff --numstat --cached | wc | sed -re 's/^\s+([0-9]+).*/\1/'` GPGPUSIM_BUILD_STRING="gpgpu-sim_git-commit-$GIT_COMMIT-modified_$GIT_FILES_CHANGED" echo -n "GPGPU-Sim version $GPGPUSIM_VERSION_STRING (build $GPGPUSIM_BUILD_STRING) "; -- cgit v1.3 From 90a0a1e4093df69505d0ffc0b08eedc9d0355ac3 Mon Sep 17 00:00:00 2001 From: Amruth Date: Wed, 11 Apr 2018 19:55:24 +0000 Subject: Copyright symbol error --- libcuda/cuda_runtime_api.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index dd32654..c103244 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -5,7 +5,7 @@ /* * cuda_runtime_api.cc * - * Copyright © 2009 by Tor M. Aamodt, Wilson W. L. Fung, Ali Bakhoda, + * Copyright © 2009 by Tor M. Aamodt, Wilson W. L. Fung, Ali Bakhoda, * George L. Yuan and the University of British Columbia, Vancouver, * BC V6T 1Z4, All Rights Reserved. * -- cgit v1.3 From 755a3cfa1b2b1711f395702d32a927dc53bee212 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 11 Apr 2018 16:07:08 -0400 Subject: Don't need to delete these anymore for the quick linking --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index a8bd7f7..4e4ef8c 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -28,7 +28,7 @@ pipeline { cd gpgpu-sim_simulations && \ git checkout purdue-cluster && \ git pull && \ - rm -r ./benchmarks/data_dirs && ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' + ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ -- cgit v1.3 From 353f89859216ea5939c0e5998e0048708384440c Mon Sep 17 00:00:00 2001 From: Roland Green Date: Wed, 11 Apr 2018 16:15:31 -0400 Subject: Add support for isnan to compile with GCC-4.8.2 --- src/cuda-sim/cuda-math.h | 4 +++- src/cuda-sim/instructions.cc | 9 +++++---- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/src/cuda-sim/cuda-math.h b/src/cuda-sim/cuda-math.h index 4721e8a..f88c526 100644 --- a/src/cuda-sim/cuda-math.h +++ b/src/cuda-sim/cuda-math.h @@ -67,6 +67,8 @@ #ifndef CUDA_MATH #define CUDA_MATH +#include + // cuda math implementations #undef max #undef min @@ -321,7 +323,7 @@ float __internal_accurate_fdividef(float a, float b) float __saturatef(float a) { float b; - if (isnan(a)) b = 0.0f; + if (std::isnan(a)) b = 0.0f; else if (a >= 1.0f) b = 1.0f; else if (a <= 0.0f) b = 0.0f; else b = a; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 011c285..e3b8970 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -33,6 +33,7 @@ #include "ptx.tab.h" #include #include +#include #include #include "cuda-math.h" #include "../abstract_hardware_model.h" @@ -1961,7 +1962,7 @@ ptx_reg_t d2d( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, y.f64 = x.f64; break; } - if (isnan(y.f64)) { + if (std::isnan(y.f64)) { y.u64 = 0xfff8000000000000ull; } else if (saturation_mode) { y.f64 = cuda_math::__saturatef(y.f64); @@ -2086,7 +2087,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) } } if ((type == F64_TYPE)||(type == FF64_TYPE)) { - if (isnan(data.f64)) { + if (std::isnan(data.f64)) { data.u64 = 0xfff8000000000000ull; } } @@ -2648,12 +2649,12 @@ void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry bool isNaN(float x) { - return isnan(x); + return std::isnan(x); } bool isNaN(double x) { - return isnan(x); + return std::isnan(x); } void max_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -- cgit v1.3 From f25a04e6a3db604f52d655fa98b99ad8f5343015 Mon Sep 17 00:00:00 2001 From: green349 Date: Wed, 11 Apr 2018 16:15:31 -0400 Subject: Add support for isnan to compile with GCC-4.8.2 --- src/cuda-sim/cuda-math.h | 4 +++- src/cuda-sim/instructions.cc | 9 +++++---- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/src/cuda-sim/cuda-math.h b/src/cuda-sim/cuda-math.h index 4721e8a..f88c526 100644 --- a/src/cuda-sim/cuda-math.h +++ b/src/cuda-sim/cuda-math.h @@ -67,6 +67,8 @@ #ifndef CUDA_MATH #define CUDA_MATH +#include + // cuda math implementations #undef max #undef min @@ -321,7 +323,7 @@ float __internal_accurate_fdividef(float a, float b) float __saturatef(float a) { float b; - if (isnan(a)) b = 0.0f; + if (std::isnan(a)) b = 0.0f; else if (a >= 1.0f) b = 1.0f; else if (a <= 0.0f) b = 0.0f; else b = a; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 011c285..e3b8970 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -33,6 +33,7 @@ #include "ptx.tab.h" #include #include +#include #include #include "cuda-math.h" #include "../abstract_hardware_model.h" @@ -1961,7 +1962,7 @@ ptx_reg_t d2d( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, y.f64 = x.f64; break; } - if (isnan(y.f64)) { + if (std::isnan(y.f64)) { y.u64 = 0xfff8000000000000ull; } else if (saturation_mode) { y.f64 = cuda_math::__saturatef(y.f64); @@ -2086,7 +2087,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) } } if ((type == F64_TYPE)||(type == FF64_TYPE)) { - if (isnan(data.f64)) { + if (std::isnan(data.f64)) { data.u64 = 0xfff8000000000000ull; } } @@ -2648,12 +2649,12 @@ void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry bool isNaN(float x) { - return isnan(x); + return std::isnan(x); } bool isNaN(double x) { - return isnan(x); + return std::isnan(x); } void max_impl( const ptx_instruction *pI, ptx_thread_info *thread ) -- cgit v1.3 From 0fed92bcefeffc16822bd07e3b436fcd7e490f57 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 12 Apr 2018 11:49:01 -0400 Subject: fixing FCFS bug --- src/gpgpu-sim/mem_latency_stat.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc index 35d6d84..8fdbe06 100644 --- a/src/gpgpu-sim/mem_latency_stat.cc +++ b/src/gpgpu-sim/mem_latency_stat.cc @@ -230,6 +230,7 @@ void memory_stats_t::memlatstat_print( unsigned n_mem, unsigned gpu_mem_n_bk ) if (num_mfs) { printf("averagemflatency = %lld \n", mf_total_lat/num_mfs); printf("avg_icnt2mem_latency = %lld \n", tot_icnt2mem_latency/num_mfs); + if(tot_mrq_num) printf("avg_mrq_latency = %lld \n", tot_mrq_latency/tot_mrq_num); printf("avg_icnt2sh_latency = %lld \n", tot_icnt2sh_latency/num_mfs); } -- cgit v1.3 From 9217cff18ab7608ee21ad48061be8f6febf88780 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 12 Apr 2018 13:05:04 -0400 Subject: adding sime spaces --- src/gpgpu-sim/mem_latency_stat.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc index 8fdbe06..c5452b9 100644 --- a/src/gpgpu-sim/mem_latency_stat.cc +++ b/src/gpgpu-sim/mem_latency_stat.cc @@ -231,7 +231,8 @@ void memory_stats_t::memlatstat_print( unsigned n_mem, unsigned gpu_mem_n_bk ) printf("averagemflatency = %lld \n", mf_total_lat/num_mfs); printf("avg_icnt2mem_latency = %lld \n", tot_icnt2mem_latency/num_mfs); if(tot_mrq_num) - printf("avg_mrq_latency = %lld \n", tot_mrq_latency/tot_mrq_num); + printf("avg_mrq_latency = %lld \n", tot_mrq_latency/tot_mrq_num); + printf("avg_icnt2sh_latency = %lld \n", tot_icnt2sh_latency/num_mfs); } printf("mrq_lat_table:"); -- cgit v1.3 From 8ea33c977b26cfe96beb98cdda289b81b8fda899 Mon Sep 17 00:00:00 2001 From: Amruth Date: Sat, 14 Apr 2018 17:17:11 -0700 Subject: solving alignment issue --- libcuda/cuda_runtime_api.cc | 1 + src/cuda-sim/cuda-sim.cc | 7 ++++++- src/cuda-sim/ptx.l | 5 +++-- src/cuda-sim/ptx_ir.h | 1 + 4 files changed, 11 insertions(+), 3 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index d6ce4e0..ef46f00 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1923,6 +1923,7 @@ void cuobjdumpParseBinary(unsigned int handle){ if (capability > max_capability) max_capability = capability; } if (max_capability > 20) printf("WARNING: No guarantee that PTX will be parsed for SM version %u\n", max_capability); + if (max_capability == 0) max_capability=context->get_device()->get_gpgpu()->get_config().get_forced_max_capability(); cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index dce35ca..2c87031 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -1139,8 +1139,13 @@ void function_info::finalize( memory_space *param_mem ) } // copy the parameter over word-by-word so that parameter that crosses a memory page can be copied over //Jin: copy parameter using aligned rules + const type_info *paramtype = param->type(); + int align_amount = paramtype->get_key().get_alignment_spec(); + align_amount = (align_amount == -1) ? size : align_amount; + param_address = (param_address + align_amount - 1) / align_amount * align_amount; //aligned + const size_t word_size = 4; - param_address = (param_address + size - 1) / size * size; //aligned with size + //param_address = (param_address + size - 1) / size * size; //aligned with size for (size_t idx = 0; idx < size; idx += word_size) { const char *pdata = reinterpret_cast(param_value.pdata) + idx; // cast to char * for ptr arithmetic param_mem->write(param_address + idx, word_size, pdata,NULL,NULL); diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 1b5d7f6..908c5be 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -36,7 +36,8 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #include "ptx.tab.h" #include -char linebuf[1024]; +#define LINEBUF_SIZE (64*1024) +char linebuf[LINEBUF_SIZE]; unsigned col = 0; #define TC col+=strlen(ptx_text); #define CHECK_UNSIGNED \ @@ -384,7 +385,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; "//"[^\n]* TC; // eat single -\n.* col=0; strncpy(linebuf, yytext + 1, 1024); yyless( 1 ); +\n.* col=0; strncpy(linebuf, yytext + 1, LINEBUF_SIZE); yyless( 1 ); " " TC; "\t" TC; diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 85b2a3b..6731763 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -91,6 +91,7 @@ public: bool is_tex() const { return m_space_spec == tex_space;} bool is_func_addr() const { return m_is_function?true:false; } int scalar_type() const { return m_scalar_type_spec;} + int get_alignment_spec() const { return m_alignment_spec;} unsigned type_decode( size_t &size, int &t ) const; static unsigned type_decode( int type, size_t &size, int &t ); memory_space_t get_memory_space() const { return m_space_spec; } -- cgit v1.3 -- cgit v1.3 From 60017ca1ddbe844a93f631fe2b86bc4101850037 Mon Sep 17 00:00:00 2001 From: Amruth Date: Thu, 19 Apr 2018 18:13:44 -0700 Subject: Crash when array pointers are passed --- README | 27 ++++++++++++++++++++++++++- src/cuda-sim/instructions.cc | 4 +++- src/cuda-sim/ptx_ir.h | 13 +++++++++++++ 3 files changed, 42 insertions(+), 2 deletions(-) diff --git a/README b/README index 543177c..bf5aa62 100644 --- a/README +++ b/README @@ -235,6 +235,14 @@ The documentation resides at doc/doxygen/html. Step 3: Run ============ +Before we run, we need to make sure the application's executable file is dynamically linked to CUDA runtime library. This can be done during compilation of your program by introducing the nvcc flag "--cudart shared" in makefile (quotes should be excluded). + +To confirm the same, type the follwoing command: + +ldd + +You should see that your application is using libcudart.so file in GPGPUSim directory. + Copy the contents of configs/QuadroFX5800/ or configs/GTX480/ to your application's working directory. These files configure the microarchitecture models to resemble the respective GPGPU architectures. @@ -348,7 +356,24 @@ identify any compile time or runtime errors that occur due to the code merging process. -** Debugging failing GPGPU-Sim Regressions ** +4. MISCELLANEOUS + +4.1 Speeding up the execution + +Some applications take several hours to execute on GPGPUSim. This is because the simulator has to dump the PTX, analyze them and get resource usage statistics. This can be avoided everytime we execute the program in the following way: + +Step 1: Execute the program by enabling “-save_embedded_ptx 1†in config file, execute the code and let cuobjdump command dump all necessary files. After this process, you will get 2 new files namely: _cuobjdump_complete_output_ and _1.ptx + +Step 2: Create new environment variables or include the below in your .bashrc file: + a. export PTX_SIM_USE_PTX_FILE=_1.ptx + b. export PTX_SIM_KERNELFILE=_1.ptx + c. export CUOBJDUMP_SIM_FILE=_cuobjdump_complete_output_ + +Step 3: Disable -save_embedded_ptx flag, execute the code again. This will skip the dumping by cuobjdump and directly goes to executing the program thus saving time. + + +4.2 Debugging failing GPGPU-Sim Regressions + Credits: Tor M Aamodt To debug failing GPGPU-Sim regression tests you need to run them locally. The fastest way to do this, assuming you are working with GPGPU-Sim versions more recent than the GPGPU-Sim dev branch circa March 28, 2018 (commit hash 2221d208a745a098a60b0d24c05007e92aaba092), is to install Docker. The instructions below were tested with Docker CE version 18.03 on Ubuntu and Mac OS. Docker will enable you to run the same set of regressions used by GPGPU-Sim when submitting a pull request to https://github.com/gpgpu-sim/gpgpu-sim_distribution and also allow you to log in and launch GPGPU-Sim in gdb so you can inspect failures. diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 0025c52..e53aaab 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -154,7 +154,9 @@ ptx_reg_t ptx_thread_info::get_operand_value( const operand_info &op, operand_in } else if ( op.is_local() ) { result.u64 = op.get_symbol()->get_address(); } else if ( op.is_function_address() ) { - result.u64 = (size_t)op.get_symbol()->get_pc(); + result.u64 = (size_t)op.get_symbol()->get_pc(); + } else if ( op.is_param_kernel()) { + result.u64 = op.get_symbol()->get_address(); } else { const char *name = op.name().c_str(); printf("GPGPU-Sim PTX: ERROR ** get_operand_value : unknown operand type for %s\n", name ); diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 6731763..58d5f49 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -164,6 +164,7 @@ public: m_is_global = false; m_is_local = false; m_is_param_local = false; + m_is_param_kernel = false; m_is_tex = false; m_is_func_addr = false; m_reg_num_valid = false; @@ -177,6 +178,7 @@ public: if ( type ) m_is_global = type->get_key().is_global(); if ( type ) m_is_local = type->get_key().is_local(); if ( type ) m_is_param_local = type->get_key().is_param_local(); + if ( type ) m_is_param_kernel = type->get_key().is_param_kernel(); if ( type ) m_is_tex = type->get_key().is_tex(); if ( type ) m_is_func_addr = type->get_key().is_func_addr(); } @@ -227,6 +229,7 @@ public: bool is_global() const { return m_is_global;} bool is_local() const { return m_is_local;} bool is_param_local() const { return m_is_param_local; } + bool is_param_kernel() const { return m_is_param_kernel; } bool is_tex() const { return m_is_tex;} bool is_func_addr() const { return m_is_func_addr; } bool is_reg() const @@ -284,6 +287,7 @@ private: bool m_is_global; bool m_is_local; bool m_is_param_local; + bool m_is_param_kernel; bool m_is_tex; bool m_is_func_addr; unsigned m_reg_num; @@ -400,6 +404,8 @@ public: m_type = symbolic_t; } else if ( addr->is_param_local() ) { m_type = symbolic_t; + } else if ( addr->is_param_kernel() ) { + m_type = symbolic_t; } else if ( addr->is_tex() ) { m_type = symbolic_t; } else if ( addr->is_func_addr() ) { @@ -676,6 +682,13 @@ public: return m_value.m_symbolic->type()->get_key().is_param_local(); } + bool is_param_kernel() const + { + if ( m_type != symbolic_t ) + return false; + return m_value.m_symbolic->type()->get_key().is_param_kernel(); + } + bool is_vector() const { if ( m_vector) return true; -- cgit v1.3 From f97a699ea5bee0a9df79afec40c0142d7ff8c5be Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Sun, 22 Apr 2018 23:29:09 -0400 Subject: Add cmath include to cuda-math.h, to allow std::isnan to be used --- src/cuda-sim/cuda-math.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cuda-sim/cuda-math.h b/src/cuda-sim/cuda-math.h index a3db0df..f88c526 100644 --- a/src/cuda-sim/cuda-math.h +++ b/src/cuda-sim/cuda-math.h @@ -67,6 +67,8 @@ #ifndef CUDA_MATH #define CUDA_MATH +#include + // cuda math implementations #undef max #undef min -- cgit v1.3 From 373d64290239f3ed74d98b20494383f03fe189b6 Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Sun, 22 Apr 2018 23:31:42 -0400 Subject: Some classes were referred to as a class and a struct (reported as clang warnings). This makes these consistent. --- libcuda/cuda_runtime_api.cc | 2 +- src/cuda-sim/cuda-sim.cc | 2 +- src/cuda-sim/ptx_ir.h | 2 +- src/debug.cc | 2 +- src/debug.h | 2 +- src/gpgpu-sim/dram.h | 4 ++-- src/gpgpu-sim/mem_fetch.cc | 2 +- src/gpgpu-sim/mem_fetch.h | 4 ++-- src/gpgpu-sim/shader.h | 4 ++-- src/stream_manager.h | 6 +++--- 10 files changed, 15 insertions(+), 15 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 9bdb993..5ef6115 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -324,7 +324,7 @@ private: gpgpu_ptx_sim_arg_list_t m_args; }; -class _cuda_device_id *GPGPUSim_Init() +struct _cuda_device_id *GPGPUSim_Init() { static _cuda_device_id *the_device = NULL; if( !the_device ) { diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index a34b99b..9f24c69 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -2067,7 +2067,7 @@ struct rec_pts { int s_num_recon; }; -struct std::map g_rpts; +class std::map g_rpts; struct rec_pts find_reconvergence_points( function_info *finfo ) { diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 9ad1571..8750187 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -105,7 +105,7 @@ private: int m_is_function; bool m_is_non_arch_reg; - friend class type_info_key_compare; + friend struct type_info_key_compare; }; class symbol_table; diff --git a/src/debug.cc b/src/debug.cc index cfd7bb0..ae15760 100644 --- a/src/debug.cc +++ b/src/debug.cc @@ -222,7 +222,7 @@ void gpgpu_sim::gpgpu_debug() } } -bool thread_at_brkpt( ptx_thread_info *thread, const struct brk_pt &b ) +bool thread_at_brkpt( ptx_thread_info *thread, const class brk_pt &b ) { return b.is_equal(thread->get_location(),thread->get_uid()); } diff --git a/src/debug.h b/src/debug.h index 7c79f1e..1277494 100644 --- a/src/debug.h +++ b/src/debug.h @@ -87,7 +87,7 @@ extern int gpgpu_ptx_instruction_classification ; class ptx_thread_info; class ptx_instruction; -bool thread_at_brkpt( ptx_thread_info *thd_info, const struct brk_pt &b ); +bool thread_at_brkpt( ptx_thread_info *thd_info, const class brk_pt &b ); void hit_watchpoint( unsigned watchpoint_num, ptx_thread_info *thd, const ptx_instruction *pI ); #endif diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h index a8bff14..15c63e7 100644 --- a/src/gpgpu-sim/dram.h +++ b/src/gpgpu-sim/dram.h @@ -87,7 +87,7 @@ struct bank_t unsigned int bkgrpindex; }; -struct mem_fetch; +class mem_fetch; class dram_t { @@ -178,7 +178,7 @@ private: unsigned int ave_mrqs_partial; unsigned int bwutil_partial; - struct memory_stats_t *m_stats; + class memory_stats_t *m_stats; class Stats* mrqq_Dist; //memory request queue inside DRAM friend class frfcfs_scheduler; diff --git a/src/gpgpu-sim/mem_fetch.cc b/src/gpgpu-sim/mem_fetch.cc index 580c051..729636d 100644 --- a/src/gpgpu-sim/mem_fetch.cc +++ b/src/gpgpu-sim/mem_fetch.cc @@ -39,7 +39,7 @@ mem_fetch::mem_fetch( const mem_access_t &access, unsigned wid, unsigned sid, unsigned tpc, - const class memory_config *config ) + const struct memory_config *config ) { m_request_uid = sm_next_mf_request_uid++; m_access = access; diff --git a/src/gpgpu-sim/mem_fetch.h b/src/gpgpu-sim/mem_fetch.h index c89edbb..de98748 100644 --- a/src/gpgpu-sim/mem_fetch.h +++ b/src/gpgpu-sim/mem_fetch.h @@ -55,7 +55,7 @@ public: unsigned wid, unsigned sid, unsigned tpc, - const class memory_config *config ); + const struct memory_config *config ); ~mem_fetch(); void set_status( enum mem_fetch_status status, unsigned long long cycle ); @@ -141,7 +141,7 @@ private: static unsigned sm_next_mf_request_uid; - const class memory_config *m_mem_config; + const struct memory_config *m_mem_config; unsigned icnt_flit_size; }; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index bdd8dbe..ea8c019 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -286,7 +286,7 @@ typedef std::bitset warp_set_t; int register_bank(int regnum, int wid, unsigned num_banks, unsigned bank_warp_shift); class shader_core_ctx; -class shader_core_config; +struct shader_core_config; class shader_core_stats; enum scheduler_prioritization_type @@ -967,7 +967,7 @@ struct ifetch_buffer_t { unsigned m_warp_id; }; -class shader_core_config; +struct shader_core_config; class simd_function_unit { public: diff --git a/src/stream_manager.h b/src/stream_manager.h index 222a1b2..d3a804f 100644 --- a/src/stream_manager.h +++ b/src/stream_manager.h @@ -93,7 +93,7 @@ public: m_stream=stream; m_done=false; } - stream_operation( class CUevent_st *e, struct CUstream_st *stream ) + stream_operation( struct CUevent_st *e, struct CUstream_st *stream ) { m_kernel=NULL; m_type=stream_event; @@ -172,10 +172,10 @@ private: bool m_sim_mode; kernel_info_t *m_kernel; - class CUevent_st *m_event; + struct CUevent_st *m_event; }; -class CUevent_st { +struct CUevent_st { public: CUevent_st( bool blocking ) { -- cgit v1.3 From 968a0510e7d1826fefa7b6688eb662d71d048809 Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Sun, 22 Apr 2018 23:35:05 -0400 Subject: One more instance of where a string should be escaped with %s before being passed to printf. --- cuobjdump_to_ptxplus/cuobjdumpInst.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cuobjdump_to_ptxplus/cuobjdumpInst.cc b/cuobjdump_to_ptxplus/cuobjdumpInst.cc index c74d2d8..392f829 100644 --- a/cuobjdump_to_ptxplus/cuobjdumpInst.cc +++ b/cuobjdump_to_ptxplus/cuobjdumpInst.cc @@ -2083,7 +2083,7 @@ void cuobjdumpInst::printCuobjdumpPtxPlus(std::list labelList, std: else { printf("Unknown Instruction: "); - printf(m_base.c_str()); + printf("%s",m_base.c_str()); printf("\n"); output("Unknown Instruction: "); output(m_base); -- cgit v1.3 From c246c12dffa6683a1fe61ad3a311cce8b1c1cbbf Mon Sep 17 00:00:00 2001 From: Nathan Conrad Date: Sun, 22 Apr 2018 23:35:57 -0400 Subject: Clang disallows empty bracks to show array indices. I believe that inserting a zero is the intent. --- src/gpgpu-sim/shader.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index ea8c019..53a10e0 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1347,7 +1347,7 @@ struct shader_core_config : public core_config struct shader_core_stats_pod { - void* shader_core_stats_pod_start[]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure + void* shader_core_stats_pod_start[0]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure unsigned long long *shader_cycles; unsigned *m_num_sim_insn; // number of scalar thread instructions committed by this shader core unsigned *m_num_sim_winsn; // number of warp instructions committed by this shader core -- cgit v1.3 From 4a3a875382a40f8b48bd086849e378c672c6d98b Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 23 Apr 2018 11:42:53 -0400 Subject: renaming the nightly file --- Jenkinsfile.nightly | 77 ----------------------------------------------------- nightly.jenkinsfile | 77 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+), 77 deletions(-) delete mode 100644 Jenkinsfile.nightly create mode 100644 nightly.jenkinsfile diff --git a/Jenkinsfile.nightly b/Jenkinsfile.nightly deleted file mode 100644 index a8b5fc7..0000000 --- a/Jenkinsfile.nightly +++ /dev/null @@ -1,77 +0,0 @@ -pipeline { - agent { - label "purdue-cluster" - } - - triggers { - chron('H H * * *') - } - - stages { - stage('simulator-build') { - steps { - "9.1" : { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ - source `pwd`/setup_environment &&\ - make -j' - } - } - } - stage('simulations-build'){ - steps{ - sh 'rm -rf gpgpu-sim_simulations' - sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ - cd gpgpu-sim_simulations && \ - git checkout purdue-cluster && \ - git pull && \ - rm -r ./benchmarks/data_dirs && ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ - source `pwd`/setup_environment &&\ - cd gpgpu-sim_simulations && \ - source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src/ rodinia_2.0-ft sdk-4.2 && \ - make -C ./benchmarks/src data' - } - } - stage('2B-insn'){ - steps { - "9.1-rodinia": { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ - source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM -N nightly-$$ && \ - PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N nightly-$$ && \ - ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' - } - } - } - stage('9.1-correlate'){ - steps { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ - source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B `cat apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM > stats-9.1.csv && \ - PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ - ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ - scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' - } - } - } - post { - success { - emailext body: "See ${BUILD_URL}", - recipientProviders: [[$class: 'CulpritsRecipientProvider'], - [$class: 'RequesterRecipientProvider']], - subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - Success!", - to: 'tgrogers@purdue.edu' - } - failure { - emailext body: "See ${BUILD_URL}", - recipientProviders: [[$class: 'CulpritsRecipientProvider'], - [$class: 'RequesterRecipientProvider']], - subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - ${currentBuild.result}", - to: 'tgrogers@purdue.edu' - } - } -} - diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile new file mode 100644 index 0000000..a8b5fc7 --- /dev/null +++ b/nightly.jenkinsfile @@ -0,0 +1,77 @@ +pipeline { + agent { + label "purdue-cluster" + } + + triggers { + chron('H H * * *') + } + + stages { + stage('simulator-build') { + steps { + "9.1" : { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + make -j' + } + } + } + stage('simulations-build'){ + steps{ + sh 'rm -rf gpgpu-sim_simulations' + sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ + cd gpgpu-sim_simulations && \ + git checkout purdue-cluster && \ + git pull && \ + rm -r ./benchmarks/data_dirs && ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + cd gpgpu-sim_simulations && \ + source ./benchmarks/src/setup_environment && \ + make -j -C ./benchmarks/src/ rodinia_2.0-ft sdk-4.2 && \ + make -C ./benchmarks/src data' + } + } + stage('2B-insn'){ + steps { + "9.1-rodinia": { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM -N nightly-$$ && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N nightly-$$ && \ + ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' + } + } + } + stage('9.1-correlate'){ + steps { + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B `cat apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM > stats-9.1.csv && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ + ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ + scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' + } + } + } + post { + success { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - Success!", + to: 'tgrogers@purdue.edu' + } + failure { + emailext body: "See ${BUILD_URL}", + recipientProviders: [[$class: 'CulpritsRecipientProvider'], + [$class: 'RequesterRecipientProvider']], + subject: "[AALP Jenkins] Build #${BUILD_NUMBER} - ${currentBuild.result}", + to: 'tgrogers@purdue.edu' + } + } +} + -- cgit v1.3 From c18b3f717449eb8c9dabe7a6036972d4c60c8f45 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 23 Apr 2018 11:46:11 -0400 Subject: renaming some stuff in the nightly file --- nightly.jenkinsfile | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile index a8b5fc7..96667ee 100644 --- a/nightly.jenkinsfile +++ b/nightly.jenkinsfile @@ -8,7 +8,7 @@ pipeline { } stages { - stage('simulator-build') { + stage('nightly-simulator-build') { steps { "9.1" : { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ @@ -17,7 +17,7 @@ pipeline { } } } - stage('simulations-build'){ + stage('nightly-simulations-build'){ steps{ sh 'rm -rf gpgpu-sim_simulations' sh 'git clone git@github.rcac.purdue.edu:TimRogersGroup/gpgpu-sim_simulations.git && \ @@ -33,9 +33,9 @@ pipeline { make -C ./benchmarks/src data' } } - stage('2B-insn'){ + stage('nightly-2B-insn'){ steps { - "9.1-rodinia": { + "9.1-all": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM -N nightly-$$ && \ @@ -45,7 +45,7 @@ pipeline { } } } - stage('9.1-correlate'){ + stage('nightly-9.1-correlate'){ steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ -- cgit v1.3 From a6442a718d221a83bf502797ce2845e5b0ef89af Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 23 Apr 2018 14:39:46 -0400 Subject: Fixing some bugs --- nightly.jenkinsfile | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile index 96667ee..4f0b6cd 100644 --- a/nightly.jenkinsfile +++ b/nightly.jenkinsfile @@ -10,11 +10,9 @@ pipeline { stages { stage('nightly-simulator-build') { steps { - "9.1" : { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ - source `pwd`/setup_environment &&\ - make -j' - } + sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ + source `pwd`/setup_environment &&\ + make -j' } } stage('nightly-simulations-build'){ @@ -33,19 +31,17 @@ pipeline { make -C ./benchmarks/src data' } } - stage('nightly-2B-insn'){ + stage('nightly-2B-insn-run'){ steps { - "9.1-all": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM -N nightly-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N nightly-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' - } } } - stage('nightly-9.1-correlate'){ + stage('nightly-correlate'){ steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ -- cgit v1.3 From 05f505caa29c6f6a4ff27039fbb35c34620080fa Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 23 Apr 2018 14:43:23 -0400 Subject: bad trigger --- nightly.jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile index 4f0b6cd..8705103 100644 --- a/nightly.jenkinsfile +++ b/nightly.jenkinsfile @@ -3,8 +3,8 @@ pipeline { label "purdue-cluster" } - triggers { - chron('H H * * *') + options { + disableConcurrentBuilds() } stages { -- cgit v1.3 From 5d8be5e655884afb59d31957cdad764e5237cf80 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 23 Apr 2018 14:51:24 -0400 Subject: Fixing the data directory linkage --- nightly.jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile index 8705103..92b8214 100644 --- a/nightly.jenkinsfile +++ b/nightly.jenkinsfile @@ -22,12 +22,12 @@ pipeline { cd gpgpu-sim_simulations && \ git checkout purdue-cluster && \ git pull && \ - rm -r ./benchmarks/data_dirs && ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' + ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ source ./benchmarks/src/setup_environment && \ - make -j -C ./benchmarks/src/ rodinia_2.0-ft sdk-4.2 && \ + make -i -j -C ./benchmarks/src/ all && \ make -C ./benchmarks/src data' } } -- cgit v1.3 From 934e79d18c34c00b8814d93ba073181821e45a4c Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 23 Apr 2018 16:16:28 -0400 Subject: propoerly pointing to the app list --- nightly.jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile index 92b8214..d00c9b3 100644 --- a/nightly.jenkinsfile +++ b/nightly.jenkinsfile @@ -35,7 +35,7 @@ pipeline { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM -N nightly-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM -N nightly-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N nightly-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' @@ -45,7 +45,7 @@ pipeline { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B `cat apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM > stats-9.1.csv && \ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM > stats-9.1.csv && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ -- cgit v1.3 From a472aa61ec5318f79e77553fec9b4dd8f88f4bf3 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 23 Apr 2018 16:28:16 -0400 Subject: change the filename for the app list --- nightly.jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile index d00c9b3..ab15198 100644 --- a/nightly.jenkinsfile +++ b/nightly.jenkinsfile @@ -35,7 +35,7 @@ pipeline { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM -N nightly-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM -N nightly-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N nightly-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' -- cgit v1.3 From 9fa3527992cf0e3d4f88a6a0e86b371aa30e9daa Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 23 Apr 2018 16:30:39 -0400 Subject: Oops forgot last .txt reference --- nightly.jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile index ab15198..c064202 100644 --- a/nightly.jenkinsfile +++ b/nightly.jenkinsfile @@ -45,7 +45,7 @@ pipeline { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.txt` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM > stats-9.1.csv && \ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM > stats-9.1.csv && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ -- cgit v1.3 From 0149fcc2aedd6db1abe591cd02fbe004b59aedb7 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 23 Apr 2018 16:46:34 -0400 Subject: trying to make this only once per day --- nightly.jenkinsfile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile index c064202..be957f2 100644 --- a/nightly.jenkinsfile +++ b/nightly.jenkinsfile @@ -5,6 +5,11 @@ pipeline { options { disableConcurrentBuilds() + overrideIndexTriggers(true) + } + + triggers { + pollSCM('0 1 * * *') } stages { -- cgit v1.3 From 538a145367a750a9ff93ffd19a06328f4766e70a Mon Sep 17 00:00:00 2001 From: tgrogers Date: Mon, 23 Apr 2018 17:09:48 -0400 Subject: Do not fail when some of the apps fails and fail 30 minutes between polling the results. --- nightly.jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile index be957f2..4257e0b 100644 --- a/nightly.jenkinsfile +++ b/nightly.jenkinsfile @@ -42,7 +42,7 @@ pipeline { source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM -N nightly-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N nightly-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -I -S 1800 -v -s stats-$$.csv -N nightly-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' } } -- cgit v1.3 From d455ec1279dc831700f1f68d574678ae0ea6ac3d Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 25 Apr 2018 14:22:34 -0400 Subject: Changing the config specs to reflect the new flex configs --- Jenkinsfile | 6 +++--- nightly.jenkinsfile | 5 ++--- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 4e4ef8c..f4389cf 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -56,7 +56,7 @@ pipeline { }, "9.1-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C TITANX_P102,TITANX_P102-L1ON,P100_HBM -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N regress-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' @@ -70,7 +70,7 @@ pipeline { }, "9.1-sdk-4.2": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C TITANX-P102,TITANX-P102-L1ON,P100-HBM -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C TITANX_P102,TITANX_P102-L1ON,P100_HBM -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' @@ -92,7 +92,7 @@ pipeline { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C TITANX-P102,P100-HBM > stats-9.1.csv && \ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C TITANX_P102,P100_HBM > stats-9.1.csv && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile index 4257e0b..7bb6372 100644 --- a/nightly.jenkinsfile +++ b/nightly.jenkinsfile @@ -40,7 +40,7 @@ pipeline { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list` -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM -N nightly-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list` -C TITANX_P102-2B,TITANX_P102-L1ON-2B,P100_HBM-2B -N nightly-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -I -S 1800 -v -s stats-$$.csv -N nightly-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' @@ -50,7 +50,7 @@ pipeline { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list -C 2B-TITANX-P102,2B-TITANX-P102-L1ON,2B-P100-HBM > stats-9.1.csv && \ + ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list` -C TITANX_P102-2B,TITANX_P102-L1ON-2B,P100_HBM-2B > stats-9.1.csv && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ @@ -75,4 +75,3 @@ pipeline { } } } - -- cgit v1.3 From e2a8646b67287957fc9f2b7ee5452b765dc46422 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 25 Apr 2018 15:16:52 -0400 Subject: Naming the plot sub-directories in a more sane way --- nightly.jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile index 7bb6372..1bf8542 100644 --- a/nightly.jenkinsfile +++ b/nightly.jenkinsfile @@ -41,7 +41,7 @@ pipeline { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list` -C TITANX_P102-2B,TITANX_P102-L1ON-2B,P100_HBM-2B -N nightly-$$ && \ - PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/getstats" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -I -S 1800 -v -s stats-$$.csv -N nightly-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' } @@ -51,7 +51,7 @@ pipeline { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list` -C TITANX_P102-2B,TITANX_P102-L1ON-2B,P100_HBM-2B > stats-9.1.csv && \ - PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ + PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' -- cgit v1.3 From 8927b0e7e41fd8d8b6b00480724161ab255e88a2 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Thu, 26 Apr 2018 16:19:02 -0400 Subject: Consolidating a number of these tests and using the new correlation script in the simulations repo --- Jenkinsfile | 33 ++++++--------------------------- nightly.jenkinsfile | 7 ++----- 2 files changed, 8 insertions(+), 32 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index f4389cf..c2b2b64 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -45,7 +45,6 @@ pipeline { } stage('regress'){ steps { - parallel "4.2-rodinia": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ @@ -53,27 +52,13 @@ pipeline { PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' - }, "9.1-rodinia": { + }, "9.1-functest": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft -C TITANX_P102,TITANX_P102-L1ON,P100_HBM -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft,sdk-4.2 -C TITANX_P102,TITANX_P102-L1ON,P100_HBM -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N regress-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' - }, "4.2-sdk-4.2": { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ - source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C GTX480 -N regress-$$ && \ - PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/4.2-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ - ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' - }, "9.1-sdk-4.2": { - sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ - source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B sdk-4.2 -C TITANX_P102,TITANX_P102-L1ON,P100_HBM -N regress-$$ && \ - PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-sdk-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -N regress-$$ -s stats-$$.csv && \ - ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' } } } @@ -81,22 +66,16 @@ pipeline { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS > stats-4.2.csv && \ - PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ - ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-4.2.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ - scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' + PLOTDIR="jenkins/${JOB_NAME}" &&\ + ./gpgpu-sim_simulations/util/correlation/correlate_and_publish.sh GTX480,GTX480-PTXPLUS $PLOTDIR ${BUILD_NUMBER}' } } stage('9.1-correlate'){ steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C TITANX_P102,P100_HBM > stats-9.1.csv && \ - PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ - ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ - scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' + PLOTDIR="jenkins/${JOB_NAME}" &&\ + ./gpgpu-sim_simulations/util/correlation/correlate_and_publish.sh TITANX_P102,TITANX_P102-L1ON,P100_HBM $PLOTDIR ${BUILD_NUMBER}' } } } diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile index 1bf8542..e48d931 100644 --- a/nightly.jenkinsfile +++ b/nightly.jenkinsfile @@ -50,11 +50,8 @@ pipeline { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list` -C TITANX_P102-2B,TITANX_P102-L1ON-2B,P100_HBM-2B > stats-9.1.csv && \ - PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ - sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ - ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ - scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' + PLOTDIR="jenkins/${JOB_NAME}" &&\ + ./gpgpu-sim_simulations/util/correlation/correlate_and_publish.sh TITANX_P102-2B,TITANX_P102-L1ON-2B,P100_HBM-2B $PLOTDIR ${BUILD_NUMBER}' } } } -- cgit v1.3 From 535f05ff6ffcef8397d3e51315efb8b4d19a8b24 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Thu, 26 Apr 2018 20:54:15 -0400 Subject: Updating to use the correct correlation file --- Jenkinsfile | 4 ++-- nightly.jenkinsfile | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index c2b2b64..aeb0978 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -67,7 +67,7 @@ pipeline { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ PLOTDIR="jenkins/${JOB_NAME}" &&\ - ./gpgpu-sim_simulations/util/correlation/correlate_and_publish.sh GTX480,GTX480-PTXPLUS $PLOTDIR ${BUILD_NUMBER}' + ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh GTX480,GTX480-PTXPLUS $PLOTDIR ${BUILD_NUMBER}' } } stage('9.1-correlate'){ @@ -75,7 +75,7 @@ pipeline { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ PLOTDIR="jenkins/${JOB_NAME}" &&\ - ./gpgpu-sim_simulations/util/correlation/correlate_and_publish.sh TITANX_P102,TITANX_P102-L1ON,P100_HBM $PLOTDIR ${BUILD_NUMBER}' + ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh TITANX_P102,TITANX_P102-L1ON,P100_HBM $PLOTDIR ${BUILD_NUMBER}' } } } diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile index e48d931..d16f546 100644 --- a/nightly.jenkinsfile +++ b/nightly.jenkinsfile @@ -51,7 +51,7 @@ pipeline { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ PLOTDIR="jenkins/${JOB_NAME}" &&\ - ./gpgpu-sim_simulations/util/correlation/correlate_and_publish.sh TITANX_P102-2B,TITANX_P102-L1ON-2B,P100_HBM-2B $PLOTDIR ${BUILD_NUMBER}' + ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh TITANX_P102-2B,TITANX_P102-L1ON-2B,P100_HBM-2B $PLOTDIR ${BUILD_NUMBER}' } } } -- cgit v1.3 From 70e036c6007135c43d213139e1a6963090721f59 Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Tue, 1 May 2018 14:58:35 -0500 Subject: Added support for -gpgpu_registers_per_block config --- libcuda/cuda_runtime_api.cc | 27 ++++++++------------------- src/gpgpu-sim/gpu-sim.cc | 8 ++++++++ src/gpgpu-sim/gpu-sim.h | 1 + src/gpgpu-sim/shader.h | 1 + 4 files changed, 18 insertions(+), 19 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index ef46f00..e3c2542 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -349,24 +349,13 @@ class _cuda_device_id *GPGPUSim_Init() prop->maxGridSize[2] = 0x40000000; prop->totalConstMem = 0x40000000; prop->textureAlignment = 0; - /* - - * TODO: Update the .config and xml files of all GPU config files with new value of sharedMemPerBlock. - - * Previously, this was thought as sharedMemPerMultiprocessor and is being used in many places. - - * Check whether all the instances of shared_mem_size(), gpgpu_shmem_size or sharedMemPerBlock are meant to use sharedMemPerBlock or sharedMemPerMultiprocessor. - - */ - - prop->sharedMemPerBlock = the_gpu->shared_mem_per_block(); - - #if (CUDART_VERSION > 5000) - - prop->sharedMemPerMultiprocessor = the_gpu->shared_mem_size(); - - #endif - +// * TODO: Update the .config and xml files of all GPU config files with new value of sharedMemPerBlock and regsPerBlock + prop->sharedMemPerBlock = the_gpu->shared_mem_per_block(); +#if (CUDART_VERSION > 5000) + prop->regsPerMultiprocessor = the_gpu->num_registers_per_core(); + prop->sharedMemPerMultiprocessor = the_gpu->shared_mem_size(); +#endif + prop->sharedMemPerBlock = the_gpu->shared_mem_per_block(); prop->regsPerBlock = the_gpu->num_registers_per_core(); prop->warpSize = the_gpu->wrp_size(); prop->clockRate = the_gpu->shader_clock(); @@ -912,7 +901,7 @@ __host__ cudaError_t CUDARTAPI cudaDeviceGetAttribute(int *value, enum cudaDevic *value= prop->sharedMemPerMultiprocessor; break; case 82: - *value= prop->regsPerBlock; + *value= prop->regsPerMultiprocessor; break; default: printf("ERROR: Attribute number %d unimplemented \n",attr); diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 5d63ab7..b283964 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -247,6 +247,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shader_registers", OPT_UINT32, &gpgpu_shader_registers, "Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)", "8192"); + option_parser_register(opp, "-gpgpu_registers_per_block", OPT_UINT32, &gpgpu_registers_per_block, + "Maximum number of registers per thread block. (default 8192)", + "8192"); option_parser_register(opp, "-gpgpu_shader_cta", OPT_UINT32, &max_cta_per_core, "Maximum number of concurrent CTAs in shader (default 8)", "8"); @@ -674,6 +677,11 @@ int gpgpu_sim::num_registers_per_core() const return m_shader_config->gpgpu_shader_registers; } +int gpgpu_sim::num_registers_per_block() const +{ + return m_shader_config->gpgpu_registers_per_block; +} + int gpgpu_sim::wrp_size() const { return m_shader_config->warp_size; diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 8d1c4fc..5908fd5 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -391,6 +391,7 @@ public: int shared_mem_size() const; int shared_mem_per_block() const; int num_registers_per_core() const; + int num_registers_per_block() const; int wrp_size() const; int shader_clock() const; const struct cudaDeviceProp *get_prop() const; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index fbddd18..6201840 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1286,6 +1286,7 @@ struct shader_core_config : public core_config unsigned max_barriers_per_cta; char * gpgpu_scheduler_string; unsigned gpgpu_shmem_per_block; + unsigned gpgpu_registers_per_block; char* pipeline_widths_string; int pipe_widths[N_PIPELINE_STAGES]; -- cgit v1.3 -- cgit v1.3 From e096e97dc6d38e26d21a83347bd0367cb6d78aeb Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Tue, 1 May 2018 15:18:11 -0500 Subject: Added -save_embedded_ptx 1 to config files --- configs/GTX480/gpgpusim.config | 3 +++ configs/GeForceGTX1080Ti/gpgpusim.config | 3 +++ configs/GeForceGTX750Ti/gpgpusim.config | 3 +++ configs/QuadroFX5600/gpgpusim.config | 3 +++ configs/QuadroFX5800/gpgpusim.config | 3 +++ configs/TeslaC2050/gpgpusim.config | 3 +++ 6 files changed, 18 insertions(+) diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config index 436cb41..580929f 100644 --- a/configs/GTX480/gpgpusim.config +++ b/configs/GTX480/gpgpusim.config @@ -1,3 +1,6 @@ +#Save the cuobjdump dump +#-save_embedded_ptx 1 + # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 diff --git a/configs/GeForceGTX1080Ti/gpgpusim.config b/configs/GeForceGTX1080Ti/gpgpusim.config index a5ada34..6d8b43a 100644 --- a/configs/GeForceGTX1080Ti/gpgpusim.config +++ b/configs/GeForceGTX1080Ti/gpgpusim.config @@ -1,5 +1,8 @@ # This config models the Pascal GP102 (GeForceGTX 1080Ti) +#Save the cuobjdump dump +#-save_embedded_ptx 1 + # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index 8b030b6..b6870b0 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -1,3 +1,6 @@ +#Save the cuobjdump dump +#-save_embedded_ptx 1 + # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 diff --git a/configs/QuadroFX5600/gpgpusim.config b/configs/QuadroFX5600/gpgpusim.config index cb87b65..6f6e032 100644 --- a/configs/QuadroFX5600/gpgpusim.config +++ b/configs/QuadroFX5600/gpgpusim.config @@ -1,3 +1,6 @@ +#Save the cuobjdump dump +#-save_embedded_ptx 1 + # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index 82243c2..77d9c6d 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -1,3 +1,6 @@ +#Save the cuobjdump dump +#-save_embedded_ptx 1 + # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config index 442ab8b..480aaa4 100644 --- a/configs/TeslaC2050/gpgpusim.config +++ b/configs/TeslaC2050/gpgpusim.config @@ -1,3 +1,6 @@ +#Save the cuobjdump dump +#-save_embedded_ptx 1 + # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 -- cgit v1.3 From f405cb9484a8b0f961bd7c143bebf1fcb17546da Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Wed, 2 May 2018 12:23:59 -0500 Subject: Minor change in config description --- src/gpgpu-sim/gpu-sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index b283964..07a0c57 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -248,7 +248,7 @@ void shader_core_config::reg_options(class OptionParser * opp) "Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)", "8192"); option_parser_register(opp, "-gpgpu_registers_per_block", OPT_UINT32, &gpgpu_registers_per_block, - "Maximum number of registers per thread block. (default 8192)", + "Maximum number of registers per CTA. (default 8192)", "8192"); option_parser_register(opp, "-gpgpu_shader_cta", OPT_UINT32, &max_cta_per_core, "Maximum number of concurrent CTAs in shader (default 8)", -- cgit v1.3 From 2be06dee25a11f9c37e94ed8d92cdeac71cf504e Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 4 May 2018 12:04:19 -0400 Subject: Getting the simulator to compile with older versions of g++ --- src/cuda-sim/cuda-math.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cuda-sim/cuda-math.h b/src/cuda-sim/cuda-math.h index a3db0df..afac330 100644 --- a/src/cuda-sim/cuda-math.h +++ b/src/cuda-sim/cuda-math.h @@ -67,6 +67,8 @@ #ifndef CUDA_MATH #define CUDA_MATH +#include + // cuda math implementations #undef max #undef min @@ -148,6 +150,7 @@ float __ll2float_rd(long long int a) { #include #include + // 32-bit integer to float float __int2float_rn(int a) { int orig_rnd_mode = fegetround(); -- cgit v1.3 From 6ff157a4ec13e33dc69856de33a7690afa408f6d Mon Sep 17 00:00:00 2001 From: tgrogers Date: Fri, 4 May 2018 12:04:19 -0400 Subject: Getting the simulator to compile with older versions of g++ --- src/cuda-sim/cuda-math.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cuda-sim/cuda-math.h b/src/cuda-sim/cuda-math.h index a3db0df..afac330 100644 --- a/src/cuda-sim/cuda-math.h +++ b/src/cuda-sim/cuda-math.h @@ -67,6 +67,8 @@ #ifndef CUDA_MATH #define CUDA_MATH +#include + // cuda math implementations #undef max #undef min @@ -148,6 +150,7 @@ float __ll2float_rd(long long int a) { #include #include + // 32-bit integer to float float __int2float_rn(int a) { int orig_rnd_mode = fegetround(); -- cgit v1.3 From 7d2b1a546cfc4a03eac998fa37b7720ce9e68109 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 9 May 2018 11:24:50 -0400 Subject: if data_dirs is not there - forget about it --- Jenkinsfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Jenkinsfile b/Jenkinsfile index 806231e..57fc6c3 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -28,7 +28,7 @@ pipeline { cd gpgpu-sim_simulations && \ git checkout purdue-cluster && \ git pull && \ - rm -r ./benchmarks/data_dirs && ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' + rm -fr ./benchmarks/data_dirs && ln -s /home/tgrogers-raid/a/common/data_dirs benchmarks/' sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/4.2_env_setup.sh &&\ source `pwd`/setup_environment &&\ cd gpgpu-sim_simulations && \ -- cgit v1.3 From 0f8c407eea99e1622486127912a83ef3e0dcf397 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 9 May 2018 16:04:09 -0400 Subject: When doing the HW correlation, do not count the first 4 cycle runs (all our data now has 10 run cycle runs). The first 4 are unreliable cause of DVFS --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index 57fc6c3..db0c18f 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -84,7 +84,7 @@ pipeline { ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B rodinia_2.0-ft -C GTX480,GTX480-PTXPLUS > stats-4.2.csv && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-4.2" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ - ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-4.2.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ + ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-4.2.csv -H ./gpgpu-sim_simulations/run_hw/ -B 4 &&\ scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' } } @@ -95,7 +95,7 @@ pipeline { ./gpgpu-sim_simulations/util/job_launching/get_stats.py -R -K -k -B sdk-4.2,rodinia_2.0-ft -C GTX1080Ti > stats-9.1.csv && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/correlate-9.1" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ sh ./gpgpu-sim_simulations/run_hw/get_hw_data.sh && rm -rf ./gpgpu-sim_simulations/util/plotting/correl-html &&\ - ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ &&\ + ./gpgpu-sim_simulations/util/plotting/plot-correlation.py -c stats-9.1.csv -H ./gpgpu-sim_simulations/run_hw/ -B 4 &&\ scp ./gpgpu-sim_simulations/util/plotting/correl-html/* tgrogers@dynamo.ecn.purdue.edu:/home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR' } } -- cgit v1.3 From 68674d4ba230df0d3bf9f4e5b035f4cf9cfc185b Mon Sep 17 00:00:00 2001 From: negargoli93 Date: Sat, 12 May 2018 16:09:04 -0700 Subject: commit for eece527project --- src/abstract_hardware_model.h | 6 +- src/cuda-sim/cuda-sim.cc | 11 ++- src/cuda-sim/instructions.cc | 213 +++++++++++++++++++----------------------- src/cuda-sim/opcodes.def | 2 +- src/cuda-sim/ptx.l | 2 +- src/cuda-sim/ptx_ir.h | 25 +++++ src/gpgpu-sim/scoreboard.cc | 4 + src/gpgpusim_entrypoint.cc | 1 - 8 files changed, 136 insertions(+), 128 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index cdd9cf3..9dc58d4 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -750,7 +750,7 @@ public: }; // the maximum number of destination, source, or address uarch operands in a instruction -#define MAX_REG_OPERANDS 8 +#define MAX_REG_OPERANDS 32 struct dram_callback_t { dram_callback_t() { function=NULL; instruction=NULL; thread=NULL; } @@ -825,8 +825,8 @@ public: address_type reconvergence_pc; // -1 => not a branch, -2 => use function return address - unsigned out[4]; - unsigned in[4]; + unsigned out[8]; + unsigned in[8]; unsigned char is_vectorin; unsigned char is_vectorout; int pred; // predicate register number diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 54d8796..006738a 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -792,9 +792,9 @@ void ptx_instruction::set_opcode_and_latency() initiation_interval = dp_init[2]; op = SFU_OP; break; - case BSMAD_OP: - latency = int_precision/int_lane_width; - initiation_interval = int_init_precision/int_init_lane_width; + case MMA_OP: + latency = 64; + initiation_interval = 64; break; case SHFL_OP: latency = 32; @@ -1301,6 +1301,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) *((warp_inst_t*)pJ) = inst; // copy active mask information pI = pJ; } + if((pI->get_opcode()!=MMA_OP)||((pI->get_opcode()==MMA_OP)&&(lane_id==0))){ switch ( pI->get_opcode() ) { #define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,this); op_classification = CLASSIFICATION; break; #define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) case OP: FUNC(pI,get_core(),inst); op_classification = CLASSIFICATION; break; @@ -1308,7 +1309,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) #undef OP_DEF #undef OP_W_DEF default: printf( "Execution error: Invalid opcode (0x%x)\n", pI->get_opcode() ); break; - } + }} delete pJ; pI = pI_saved; @@ -1930,7 +1931,7 @@ void functionalCoreSim::executeWarp(unsigned i, bool &allAtBarrier, bool & someO { if(!m_warpAtBarrier[i] && m_liveThreadCount[i]!=0){ warp_inst_t inst =getExecuteWarp(i); - execute_warp_inst_t(inst,i); + execute_warp_inst_t(inst,i); if(inst.isatomic()) inst.do_atomic(true); if(inst.op==BARRIER_OP || inst.op==MEMORY_BARRIER_OP ) m_warpAtBarrier[i]=true; updateSIMTStack( i, &inst ); diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 493e307..7903343 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -771,6 +771,17 @@ void add_impl( const ptx_instruction *pI, ptx_thread_info *thread ) unsigned i_type = pI->get_type(); src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1); src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1); + //unsigned warpId_aa,warp_size_aa; + //warpId_aa = pI->warp_id(); + //warp_size_aa=32; + //dim3 t=thread->get_tid(); + //unsigned tid_aa=warp_size_aa*warpId_aa; + + ptx_thread_info *thread2; + thread2=thread; + src1_data = thread2->get_operand_value(src1, dst, i_type, thread2, 1); + src2_data = thread2->get_operand_value(src2, dst, i_type, thread2, 1); + unsigned rounding_mode = pI->rounding_mode(); int orig_rm = fegetround(); @@ -1483,135 +1494,102 @@ unsigned trunc(unsigned num, unsigned precision) { return num; } -void bsmad_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) +void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { - // operands: - // 0 = output - // 1 = input precision - // 2 = output precision - // 3 = buffer0 - // 4 = buffer1 - // 5 = buffer2 - // 6 = buffer3 - // 7 = synapse value - // 8 = output value + int i,j,k,thrd; + int row,offset; + printf("mmaWorld\n"); + ptx_reg_t matrix_a[16][16]; + ptx_reg_t matrix_b[16][16]; + ptx_reg_t matrix_c[16][16]; + ptx_reg_t matrix_d[16][16]; + ptx_reg_t src_data; + ptx_thread_info *thread; - const operand_info &dst = pI->dst(); - const operand_info &src1 = pI->src1(); - const operand_info &src2 = pI->src2(); unsigned type = pI->get_type(); int tid = inst.warp_id_func() * core->get_warp_size(); - ptx_thread_info *thread = core->get_thread_info()[tid]; - const int ip = (thread->get_operand_value(src1, dst, type, thread, 1)).u32; - const int op = (thread->get_operand_value(src2, dst, type, thread, 1)).u32; - const int THREADS = inst.active_count(); - const int INBUFFERS = 4; - const int OUTBUFFERS = (((32/ip)*INBUFFERS) / (32/op)) + ((((32/ip)*INBUFFERS) % (32/op)) != 0); - if (OUTBUFFERS > THREADS) { - printf("GPGPU-Sim PTX: BSMAD ERROR - Number of output registers required (%d) is greater than the number available (%d)\n", OUTBUFFERS, THREADS); - abort(); - } - ptx_warp_info *warp_info = thread->m_warp_info; - warp_info->inc_done_threads(); + const operand_info &dst = pI->operand_lookup(0); + +//NOT WOR thread = core->get_thread_info()[tid]; +//NOT WOR const operand_info &src_a= pI->operand_lookup(1); +//NOT WOR src_data= (thread->get_operand_value(src_a, dst, type, thread, 1)); +//NOT WOR thread->set_operand_value(dst, src_data, type, thread, pI); + for (thrd=0; thrd < core->get_warp_size(); thrd++){ + row=thrd/2; + offset=8*(thrd%2); + thread = core->get_thread_info()[tid+thrd]; + printf("thread=%d:",thrd); + for(i=8;i<=31;i++){ + const operand_info &src_a= pI->operand_lookup(i); + src_data= (thread->get_operand_value(src_a, dst, type, thread, 1)); + printf("%f ",src_data.f32); + if(i<=15) + matrix_a[row][offset+(i)%8]=src_data; + else if((i>15)&&(i<=23)) + matrix_b[row][offset+(i)%8]=src_data; + else if(i>23) + matrix_c[row][offset+(i)%8]=src_data; + - // threads within the warp are executed sequentially by the simulator, store output in first four registers - if (warp_info->get_done_threads() <= OUTBUFFERS) { - unsigned buffer[THREADS][INBUFFERS]; - unsigned synapse[THREADS]; - unsigned output; - - // loop through all threads in the warp and get all data - for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { - if (inst.active(i)) { - const operand_info &src3 = pI->operand_lookup(3); - const operand_info &src4 = pI->operand_lookup(4); - const operand_info &src5 = pI->operand_lookup(5); - const operand_info &src6 = pI->operand_lookup(6); - const operand_info &src7 = pI->operand_lookup(7); - const operand_info &src8 = pI->operand_lookup(8); - - thread = core->get_thread_info()[tid+i]; - // get buffer data and synapse data from each thread - buffer[j][0] = (thread->get_operand_value(src3, dst, type, thread, 1)).u32; - buffer[j][1] = (thread->get_operand_value(src4, dst, type, thread, 1)).u32; - buffer[j][2] = (thread->get_operand_value(src5, dst, type, thread, 1)).u32; - buffer[j][3] = (thread->get_operand_value(src6, dst, type, thread, 1)).u32; - synapse[j] = (thread->get_operand_value(src7, dst, type, thread, 1)).u32; - j++; - // get output data from the first 4 threads - if (j == warp_info->get_done_threads()) { - output = (thread->get_operand_value(src8, dst, type, thread, 1)).u32; - } - } } + printf("\n"); + } - // unpack registers, compute enough outputs to fill an output register - unsigned *unpacked_output = (unsigned*)calloc(32/op,sizeof(unsigned)); - unsigned buffer_data_start = (32/op)*(warp_info->get_done_threads()-1); - for (unsigned i = buffer_data_start; i < (32/op + buffer_data_start) && i < (32/ip)*INBUFFERS; i++) { - unsigned buf = i/(32/ip); - unsigned pos = i%(32/ip); - // sum values from the buffers - int sum = 0; - unsigned mask = (unsigned)(pow(2,ip)-1) << (pos*ip); - for (int j = 0; j < THREADS; j++) { - //sum += ((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j]; - sum += trunc(((mask & buffer[j][buf]) >> (pos*ip)) * synapse[j], op); - } - // get the previous output - mask = (unsigned)(pow(2,op)-1) << (op*(i-buffer_data_start)); - int past_output = (mask & output) >> (op*(i-buffer_data_start)); - unpacked_output[i-buffer_data_start] = trunc(trunc(sum,op) + past_output,op); - // truncate sum, truncate (truncated sum + past_output) + printf("MATRIX_A\n"); + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + printf("%f ",matrix_a[i][j].f32); } - - // truncate output - /*for (unsigned i = 0; i < 32/op; i++) { - int mask = 1, latest_one = -1; - unsigned data = unpacked_output[i]; - for (unsigned j = 0; j < sizeof(unsigned)*8; j++) { - int bit = data & mask; - if (bit == 1) latest_one = j; - data >>= 1; - } - if (latest_one >= op) { - // round_up is 1 if the most significant truncated digit is a 1, otherwise it is 0 - int round_up = (unpacked_output[i] & (1 << (latest_one-op))) >> (latest_one-op); - unsigned shifted_output = unpacked_output[i] >> (latest_one-op+1); - // if shifted_output is a number like 1111, don't round up - if (shifted_output == (pow(2,op)-1)) round_up = 0; - unpacked_output[i] = shifted_output + round_up; - } - }*/ - - // pack the outputs into one register - unsigned mask = pow(2,op)-1; - unsigned output_data = 0; - for (int i = 0; i < 32/op; i++) { - output_data |= (unpacked_output[i] & mask) << (op*i); + printf("\n"); + } + printf("MATRIX_B\n"); + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + printf("%f ",matrix_b[i][j].f32); } - - // store the result in the correct thread's output register - for (unsigned i = 0, j = 0; i < core->get_warp_size(); i++) { - if (inst.active(i)) j++; - if (j == warp_info->get_done_threads()) { - thread = core->get_thread_info()[tid+i]; - ptx_reg_t data; - data.u32 = output_data; - thread->set_operand_value(dst, data, type, thread, pI); - break; + printf("\n"); + } + printf("MATRIX_C\n"); + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + printf("%f ",matrix_c[i][j].f32); + } + printf("\n"); + } + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + matrix_d[i][j].f32=0; + } + } + + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + for(k=0;k<16;k++){ + matrix_d[i][j].f32=matrix_d[i][j].f32+matrix_a[i][k].f32*matrix_b[j][k].f32; } + matrix_d[i][j].f32+=matrix_c[i][j].f32; } } - - // once the warp has finished, set the number of completed threads back to 0 for the next warp - if (warp_info->get_done_threads() == THREADS) { - warp_info->reset_done_threads(); + printf("MATRIX_D\n"); + for (i=0;i<16;i++){ + for(j=0;j<16;j++){ + printf("%f ",matrix_d[i][j].f32); + } + printf("\n"); + } + for (thrd=0; thrd < core->get_warp_size(); thrd++){ + thread = core->get_thread_info()[tid+thrd]; + row=thrd/2; + offset=8*(thrd%2); + for(i=0;i<8;i++){ + const operand_info &dst = pI->operand_lookup(i); + const symbol *r2; + r2=dst.get_symbol(); + printf("thrd=%d,i=%d,register%s, data=%f\n",thrd,i,(r2->name()).c_str(),matrix_d[row][offset+i].f32); + thread->set_operand_value(dst, matrix_d[row][offset+i], type, thread, pI); + } } - - // set the latency assuming 4 bits of each input get processed every cycle - // mutable latency variable??? - //pI->latency = (ip+3)/4; + } void call_impl( const ptx_instruction *pI, ptx_thread_info *thread ) @@ -4098,7 +4076,8 @@ void st_impl( const ptx_instruction *pI, ptx_thread_info *thread ) if (!vector_spec) { data = thread->get_operand_value(src1, dst, type, thread, 1); mem->write(addr,size/8,&data.s64,thread,pI); - } else { + printf("addr=%d data=%d\n",addr,data.s64); + } else { if (vector_spec == V2_TYPE) { ptx_reg_t* ptx_regs = new ptx_reg_t[2]; thread->get_vector_operand_values(src1, ptx_regs, 2); diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 41f2f22..a3cc83f 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -52,7 +52,7 @@ OP_DEF(BRA_OP,bra_impl,"bra",0,3) OP_DEF(BRX_OP,brx_impl,"brx",0,3) OP_DEF(BREV_OP,brev_impl,"brev",1,1) OP_DEF(BRKPT_OP,brkpt_impl,"brkpt",1,9) -OP_W_DEF(BSMAD_OP,bsmad_impl,"bsmad",1,1) +OP_W_DEF(MMA_OP,mma_impl,"mma",1,1) OP_DEF(CALL_OP,call_impl,"call",1,3) OP_DEF(CALLP_OP,callp_impl,"callp",1,3) OP_DEF(CLZ_OP,clz_impl,"clz",1,1) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 7620134..e07e339 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -68,7 +68,7 @@ bra TC; ptx_lval.int_value = BRA_OP; return OPCODE; brx TC; ptx_lval.int_value = BRX_OP; return OPCODE; brev TC; ptx_lval.int_value = BREV_OP; return OPCODE; brkpt TC; ptx_lval.int_value = BRKPT_OP; return OPCODE; -bsmad TC; ptx_lval.int_value = BSMAD_OP; return OPCODE; +mma TC; ptx_lval.int_value = MMA_OP; return OPCODE; call TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALL_OP; return OPCODE; // blocking opcode token in case the callee has the same name as an opcode callp TC; BEGIN(NOT_OPCODE); ptx_lval.int_value = CALLP_OP; return OPCODE; clz TC; ptx_lval.int_value = CLZ_OP; return OPCODE; diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 4c10373..0601b97 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -948,6 +948,31 @@ public: assert( m_operands.size() > 3 ); return m_operands[3]; } + const operand_info &src4() const + { + assert( m_operands.size() > 4 ); + return m_operands[4]; + } + const operand_info &src5() const + { + assert( m_operands.size() > 5 ); + return m_operands[5]; + } + const operand_info &src6() const + { + assert( m_operands.size() > 6 ); + return m_operands[6]; + } + const operand_info &src7() const + { + assert( m_operands.size() > 7 ); + return m_operands[7]; + } + const operand_info &src8() const + { + assert( m_operands.size() > 8 ); + return m_operands[8]; + } const operand_info &operand_lookup( unsigned n ) const { diff --git a/src/gpgpu-sim/scoreboard.cc b/src/gpgpu-sim/scoreboard.cc index f412054..b538fdf 100644 --- a/src/gpgpu-sim/scoreboard.cc +++ b/src/gpgpu-sim/scoreboard.cc @@ -146,6 +146,10 @@ bool Scoreboard::checkCollision( unsigned wid, const class inst_t *inst ) const if(inst->in[1] > 0) inst_regs.insert(inst->in[1]); if(inst->in[2] > 0) inst_regs.insert(inst->in[2]); if(inst->in[3] > 0) inst_regs.insert(inst->in[3]); + if(inst->in[3] > 0) inst_regs.insert(inst->in[4]); + if(inst->in[3] > 0) inst_regs.insert(inst->in[5]); + if(inst->in[3] > 0) inst_regs.insert(inst->in[6]); + if(inst->in[3] > 0) inst_regs.insert(inst->in[7]); if(inst->pred > 0) inst_regs.insert(inst->pred); if(inst->ar1 > 0) inst_regs.insert(inst->ar1); if(inst->ar2 > 0) inst_regs.insert(inst->ar2); diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index 04845e7..a6d7eb4 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -134,7 +134,6 @@ void *gpgpu_sim_thread_concurrent(void*) gpgpu_cuda_ptx_sim_main_func(*kernel); g_the_gpu->finish_functional_sim(kernel); } - //performance simulation if( g_the_gpu->active() ) { g_the_gpu->cycle(); -- cgit v1.3 From bae67e6a355047e360c30391588c2076913f86fa Mon Sep 17 00:00:00 2001 From: negargoli93 Date: Sat, 12 May 2018 17:11:34 -0700 Subject: mma added --- src/cuda-sim/instructions.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 7903343..bddaf8c 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -1565,7 +1565,7 @@ void mma_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) for (i=0;i<16;i++){ for(j=0;j<16;j++){ for(k=0;k<16;k++){ - matrix_d[i][j].f32=matrix_d[i][j].f32+matrix_a[i][k].f32*matrix_b[j][k].f32; + matrix_d[i][j].f32=matrix_d[i][j].f32+matrix_a[i][k].f32*matrix_b[k][j].f32; } matrix_d[i][j].f32+=matrix_c[i][j].f32; } -- cgit v1.3 From f169276e3916d6ffbaef78b0b836c91f1e169044 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Tue, 15 May 2018 19:57:44 -0400 Subject: adding Volta model configs --- .../gpgpu-sim-3.x/config_fermi_islip.icnt | 70 ++++++++ .../gpgpu-sim-3.x/gpgpusim.config | 166 ++++++++++++++++++ .../gpgpu-sim-4.x/config_fermi_islip.icnt | 74 ++++++++ .../gpgpu-sim-4.x/gpgpusim.config | 186 +++++++++++++++++++++ 4 files changed, 496 insertions(+) create mode 100644 configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/config_fermi_islip.icnt create mode 100644 configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config create mode 100644 configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/config_fermi_islip.icnt create mode 100644 configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/gpgpusim.config diff --git a/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/config_fermi_islip.icnt b/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/config_fermi_islip.icnt new file mode 100644 index 0000000..d26c8d9 --- /dev/null +++ b/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 60; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config b/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config new file mode 100644 index 0000000..c0406e9 --- /dev/null +++ b/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config @@ -0,0 +1,166 @@ +# This config models the Volta Titan X +# For more info about this card: +# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf +# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf +# https://devblogs.nvidia.com/inside-volta/ +# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 70 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 40 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 24 +-gpgpu_n_sub_partition_per_mchannel 1 + +# volta clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA GP100 clock domains are adopted from +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +-gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0 +# boost mode +# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 +-gpgpu_num_dp_units 4 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 2,2,2,2,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,4,4,4,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP100 has 64KB Shared memory +-gpgpu_cache:dl1 S:64:128:8,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:64:128:16,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 1 +-gpgpu_shmem_size_PrefShared 98304 +-gmem_skip_L1D 0 + +# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache +-gpgpu_cache:dl2 S:64:128:24,L:B:m:F:L,A:256:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 + +# 128 KB Inst. +-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 +# 64 KB Const +-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 14 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_units_mem 10 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for HBM, 32 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: + CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/config_fermi_islip.icnt b/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/config_fermi_islip.icnt new file mode 100644 index 0000000..616e9f3 --- /dev/null +++ b/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/config_fermi_islip.icnt @@ -0,0 +1,74 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 64; +n = 1; + +// Routing + +routing_function = dest_tag; + + +// Flow control + +num_vcs = 1; +vc_buf_size = 128; +input_buffer_size = 256; +ejection_buffer_size = 128; +boundary_buffer_size = 128; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/gpgpusim.config b/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/gpgpusim.config new file mode 100644 index 0000000..3d8c161 --- /dev/null +++ b/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/gpgpusim.config @@ -0,0 +1,186 @@ +# This config models the Volta Titan X +# For more info about this card: +# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf +# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf +# https://devblogs.nvidia.com/inside-volta/ +# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 70 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 40 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 24 +-gpgpu_n_sub_partition_per_mchannel 1 + +# volta clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA GP100 clock domains are adopted from +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +-gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0 +# boost mode +# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 +-gpgpu_num_dp_units 4 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 2,2,2,2,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,4,4,4,130 +-ptx_opcode_latency_sfu 100 +-ptx_opcode_initiation_sfu 8 + + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP100 has 64KB Shared memory +-gpgpu_cache:dl1 S:64:128:8,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:64:128:16,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 1 +-gpgpu_shmem_size_PrefShared 98304 +-gmem_skip_L1D 0 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 + +# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache +-gpgpu_cache:dl2 S:64:128:24,L:B:m:F:L,A:256:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 +-perf_sim_memcpy 0 + +# 128 KB Inst. +-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 +# 64 KB Const +-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 70 + +## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units +-gpgpu_max_insn_issue_per_warp 1 +-gpgpu_dual_issue_diff_exec_units 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 192 + +# for HBM, 32 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: + CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" + +# HBM has dual bus interface, in which it can issue two col and row commands at a time +-dual_bus_interface 1 +# select lower bits for bnkgrp to increase bnkgrp parallelism +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + +# Pascal has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Pascal 100 +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + -- cgit v1.3 From e06cd8efa02bf54f4788b0655930c9c6c0e12311 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Tue, 15 May 2018 19:58:48 -0400 Subject: fixnig icnt volta --- configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/config_fermi_islip.icnt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/config_fermi_islip.icnt b/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/config_fermi_islip.icnt index d26c8d9..fac792a 100644 --- a/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/config_fermi_islip.icnt +++ b/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/config_fermi_islip.icnt @@ -7,7 +7,7 @@ network_count = 2; // Topology topology = fly; -k = 60; +k = 64; n = 1; // Routing -- cgit v1.3 From c2b43f1ff592563c1abf8bc1ac3230f2892b380a Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Tue, 15 May 2018 20:17:27 -0400 Subject: 60 coals mode --- configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/gpgpusim.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/gpgpusim.config b/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/gpgpusim.config index 3d8c161..8969168 100644 --- a/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/gpgpusim.config +++ b/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/gpgpusim.config @@ -109,7 +109,7 @@ -gpgpu_shmem_num_banks 32 -gpgpu_shmem_limited_broadcast 0 -gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 70 +-gpgpu_coalesce_arch 60 ## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units -gpgpu_max_insn_issue_per_warp 1 -- cgit v1.3 From 8738aa4cde553dcf3b3315f4e7e61f1fa4faeadd Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Tue, 15 May 2018 20:29:42 -0400 Subject: fixing vache for volta --- .../Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config b/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config index c0406e9..f1ae2dc 100644 --- a/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config @@ -43,10 +43,9 @@ # ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB ## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12 +-gpgpu_pipeline_widths 4,4,1,4,4,1,9 -gpgpu_num_sp_units 4 -gpgpu_num_sfu_units 4 --gpgpu_num_dp_units 4 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" @@ -64,25 +63,25 @@ # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. # Pascal GP100 has 64KB Shared memory --gpgpu_cache:dl1 S:64:128:8,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefL1 S:64:128:16,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1 64:128:8,L:L:m:N:H,A:256:8,16:0 +-gpgpu_cache:dl1PrefL1 64:128:16,L:L:m:N:H,A:256:8,16:0 +-gpgpu_cache:dl1PrefShared 32:128:6,L:L:m:N:H,A:256:8,16:0 -gpgpu_shmem_size 65536 -gpgpu_shmem_size_PrefL1 1 -gpgpu_shmem_size_PrefShared 98304 -gmem_skip_L1D 0 # 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache --gpgpu_cache:dl2 S:64:128:24,L:B:m:F:L,A:256:4,32:0,32 +-gpgpu_cache:dl2 64:128:24,L:B:m:W:L,A:256:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 # 128 KB Inst. --gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +-gpgpu_cache:il1 64:128:16,L:R:f:N:L,A:2:48,4 # 48 KB Tex --gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # 64 KB Const --gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 +-gpgpu_const_cache:l1 128:64:8,L:R:f:N:L,A:2:64,4 # enable operand collector -gpgpu_operand_collector_num_units_sp 14 -- cgit v1.3 From 8b34db6513e20335e06c8b40ead6d181e3ebba44 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Wed, 16 May 2018 13:36:15 -0700 Subject: is_reg change --- .gitignore | 4 ++++ src/cuda-sim/instructions.cc | 6 ++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/.gitignore b/.gitignore index 887b605..428abce 100644 --- a/.gitignore +++ b/.gitignore @@ -29,3 +29,7 @@ cuobjdump_to_ptxplus/sass_parser.output build/* *.swp +*~ +cscope* +tags + diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index e53aaab..8a3539b 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2366,9 +2366,11 @@ void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand type_info_key ti = t->get_key(); if( ti.is_param_kernel() ) space = param_space_kernel; - else if( ti.is_param_local() ) { + else if( ti.is_param_local() ) space = param_space_local; - } else { + else if( ti.is_reg() ) + space = param_space_kernel; + else { printf("GPGPU-Sim PTX: ERROR ** cannot resolve .param space for '%s'\n", s->name().c_str() ); abort(); } -- cgit v1.3 From 97fcd60a4fdef22d3ab89eb660ec4cdc07553f72 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 16 May 2018 18:20:14 -0400 Subject: Moving all the 3.x cfgs to a new subdirectory --- .../3.x-cfgs/PASCAL_P100/config_fermi_islip.icnt | 70 +++ configs/3.x-cfgs/PASCAL_P100/gpgpusim.config | 156 ++++++ configs/3.x-cfgs/PASCAL_P100/gpuwattch_gtx480.xml | 538 +++++++++++++++++++++ .../3.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt | 70 +++ configs/3.x-cfgs/PASCAL_TITANX/gpgpusim.config | 156 ++++++ .../3.x-cfgs/PASCAL_TITANX/gpuwattch_gtx480.xml | 538 +++++++++++++++++++++ .../3.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt | 70 +++ configs/3.x-cfgs/VOLTA_TITANV/gpgpusim.config | 165 +++++++ .../gpgpu-sim-3.x/config_fermi_islip.icnt | 70 --- .../gpgpu-sim-3.x/gpgpusim.config | 165 ------- .../gpgpu-sim-3.x/config_fermi_islip.icnt | 70 --- configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config | 156 ------ .../PascalP100X/gpgpu-sim-3.x/gpuwattch_gtx480.xml | 538 --------------------- .../gpgpu-sim-3.x/config_fermi_islip.icnt | 70 --- configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 156 ------ .../gpgpu-sim-3.x/gpuwattch_gtx480.xml | 538 --------------------- 16 files changed, 1763 insertions(+), 1763 deletions(-) create mode 100644 configs/3.x-cfgs/PASCAL_P100/config_fermi_islip.icnt create mode 100644 configs/3.x-cfgs/PASCAL_P100/gpgpusim.config create mode 100755 configs/3.x-cfgs/PASCAL_P100/gpuwattch_gtx480.xml create mode 100644 configs/3.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt create mode 100644 configs/3.x-cfgs/PASCAL_TITANX/gpgpusim.config create mode 100755 configs/3.x-cfgs/PASCAL_TITANX/gpuwattch_gtx480.xml create mode 100644 configs/3.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt create mode 100644 configs/3.x-cfgs/VOLTA_TITANV/gpgpusim.config delete mode 100644 configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/config_fermi_islip.icnt delete mode 100644 configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config delete mode 100644 configs/PascalP100X/gpgpu-sim-3.x/config_fermi_islip.icnt delete mode 100644 configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config delete mode 100755 configs/PascalP100X/gpgpu-sim-3.x/gpuwattch_gtx480.xml delete mode 100644 configs/PascalTitanX/gpgpu-sim-3.x/config_fermi_islip.icnt delete mode 100644 configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config delete mode 100755 configs/PascalTitanX/gpgpu-sim-3.x/gpuwattch_gtx480.xml diff --git a/configs/3.x-cfgs/PASCAL_P100/config_fermi_islip.icnt b/configs/3.x-cfgs/PASCAL_P100/config_fermi_islip.icnt new file mode 100644 index 0000000..d26c8d9 --- /dev/null +++ b/configs/3.x-cfgs/PASCAL_P100/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 60; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/3.x-cfgs/PASCAL_P100/gpgpusim.config b/configs/3.x-cfgs/PASCAL_P100/gpgpusim.config new file mode 100644 index 0000000..a5e6736 --- /dev/null +++ b/configs/3.x-cfgs/PASCAL_P100/gpgpusim.config @@ -0,0 +1,156 @@ +# This config models the Pascal GP100 +# For more info about this card, see Nvidia White paper +# https://images.nvidia.com/content/pdf/tesla/whitepaper/pascal-architecture-whitepaper.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 60 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 32 +-gpgpu_n_sub_partition_per_mchannel 1 + +# Pscal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA GP100 clock domains are adopted from +# https://en.wikipedia.org/wiki/Nvidia_Tesla +-gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 2,2,1,2,2,1,4 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 2,2,2,2,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP100 has 64KB Shared memory +# Pascal GP100 has 48KB L1 cache +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 65536 +-gpgpu_shmem_size_PrefShared 65536 +-gmem_skip_L1D 0 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 14 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_units_mem 10 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for HBM, 32 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: + CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/3.x-cfgs/PASCAL_P100/gpuwattch_gtx480.xml b/configs/3.x-cfgs/PASCAL_P100/gpuwattch_gtx480.xml new file mode 100755 index 0000000..304e0fd --- /dev/null +++ b/configs/3.x-cfgs/PASCAL_P100/gpuwattch_gtx480.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/3.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt b/configs/3.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt new file mode 100644 index 0000000..602daee --- /dev/null +++ b/configs/3.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 52; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/3.x-cfgs/PASCAL_TITANX/gpgpusim.config b/configs/3.x-cfgs/PASCAL_TITANX/gpgpusim.config new file mode 100644 index 0000000..f78bd02 --- /dev/null +++ b/configs/3.x-cfgs/PASCAL_TITANX/gpgpusim.config @@ -0,0 +1,156 @@ +# This config models the Pascal GP102 (NVIDIA TITAN X) +# For more info about this card, see Nvidia White paper +# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 61 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 12 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,8,4,4,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The defulat is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_shmem_size 98304 +-gpgpu_shmem_size_PrefL1 98304 +-gpgpu_shmem_size_PrefShared 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +# gpgpu_num_reg_banks should be increased to 32 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) +# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 4 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/3.x-cfgs/PASCAL_TITANX/gpuwattch_gtx480.xml b/configs/3.x-cfgs/PASCAL_TITANX/gpuwattch_gtx480.xml new file mode 100755 index 0000000..304e0fd --- /dev/null +++ b/configs/3.x-cfgs/PASCAL_TITANX/gpuwattch_gtx480.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/3.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt b/configs/3.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt new file mode 100644 index 0000000..fac792a --- /dev/null +++ b/configs/3.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 64; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/3.x-cfgs/VOLTA_TITANV/gpgpusim.config b/configs/3.x-cfgs/VOLTA_TITANV/gpgpusim.config new file mode 100644 index 0000000..f1ae2dc --- /dev/null +++ b/configs/3.x-cfgs/VOLTA_TITANV/gpgpusim.config @@ -0,0 +1,165 @@ +# This config models the Volta Titan X +# For more info about this card: +# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf +# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf +# https://devblogs.nvidia.com/inside-volta/ +# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 70 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 40 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 24 +-gpgpu_n_sub_partition_per_mchannel 1 + +# volta clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA GP100 clock domains are adopted from +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +-gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0 +# boost mode +# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,4,1,4,4,1,9 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 2,2,2,2,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,4,4,4,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP100 has 64KB Shared memory +-gpgpu_cache:dl1 64:128:8,L:L:m:N:H,A:256:8,16:0 +-gpgpu_cache:dl1PrefL1 64:128:16,L:L:m:N:H,A:256:8,16:0 +-gpgpu_cache:dl1PrefShared 32:128:6,L:L:m:N:H,A:256:8,16:0 +-gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 1 +-gpgpu_shmem_size_PrefShared 98304 +-gmem_skip_L1D 0 + +# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache +-gpgpu_cache:dl2 64:128:24,L:B:m:W:L,A:256:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 + +# 128 KB Inst. +-gpgpu_cache:il1 64:128:16,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 64 KB Const +-gpgpu_const_cache:l1 128:64:8,L:R:f:N:L,A:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 14 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_units_mem 10 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for HBM, 32 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: + CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/config_fermi_islip.icnt b/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/config_fermi_islip.icnt deleted file mode 100644 index fac792a..0000000 --- a/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 64; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config b/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config deleted file mode 100644 index f1ae2dc..0000000 --- a/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config +++ /dev/null @@ -1,165 +0,0 @@ -# This config models the Volta Titan X -# For more info about this card: -# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf -# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) -# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf -# https://devblogs.nvidia.com/inside-volta/ -# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 70 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 40 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 24 --gpgpu_n_sub_partition_per_mchannel 1 - -# volta clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA GP100 clock domains are adopted from -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) --gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0 -# boost mode -# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,1,4,4,1,9 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 4 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 2,2,2,2,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 2,2,2,2,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 4,4,4,4,130 - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP100 has 64KB Shared memory --gpgpu_cache:dl1 64:128:8,L:L:m:N:H,A:256:8,16:0 --gpgpu_cache:dl1PrefL1 64:128:16,L:L:m:N:H,A:256:8,16:0 --gpgpu_cache:dl1PrefShared 32:128:6,L:L:m:N:H,A:256:8,16:0 --gpgpu_shmem_size 65536 --gpgpu_shmem_size_PrefL1 1 --gpgpu_shmem_size_PrefShared 98304 --gmem_skip_L1D 0 - -# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache --gpgpu_cache:dl2 64:128:24,L:B:m:W:L,A:256:4,32:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 64:64:64:64 - -# 128 KB Inst. --gpgpu_cache:il1 64:128:16,L:R:f:N:L,A:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 -# 64 KB Const --gpgpu_const_cache:l1 128:64:8,L:R:f:N:L,A:2:64,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 14 --gpgpu_operand_collector_num_units_sfu 8 --gpgpu_operand_collector_num_units_mem 10 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - -## In Pascal, a warp scheduler can issue 2 insts per cycle --gpgpu_max_insn_issue_per_warp 1 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 116 - -# for HBM, 32 channles, each (128 bits) 16 bytes width --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 16 --gpgpu_dram_burst_length 2 --dram_data_command_freq_ratio 2 # HBM is DDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS - -# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) -# Timing for 1 GHZ -# tRRDl and tWTR are missing, need to be added -#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: -# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" - -# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ --gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: - CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" - -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs --power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/PascalP100X/gpgpu-sim-3.x/config_fermi_islip.icnt b/configs/PascalP100X/gpgpu-sim-3.x/config_fermi_islip.icnt deleted file mode 100644 index d26c8d9..0000000 --- a/configs/PascalP100X/gpgpu-sim-3.x/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 60; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config deleted file mode 100644 index a5e6736..0000000 --- a/configs/PascalP100X/gpgpu-sim-3.x/gpgpusim.config +++ /dev/null @@ -1,156 +0,0 @@ -# This config models the Pascal GP100 -# For more info about this card, see Nvidia White paper -# https://images.nvidia.com/content/pdf/tesla/whitepaper/pascal-architecture-whitepaper.pdf - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 60 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 32 --gpgpu_n_sub_partition_per_mchannel 1 - -# Pscal clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA GP100 clock domains are adopted from -# https://en.wikipedia.org/wiki/Nvidia_Tesla --gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 1 SFU unit -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 2,2,1,2,2,1,4 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 1 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# SFU is 32-width in pascal, then dp units initiation is 1 cycle --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 2,2,2,2,130 - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP100 has 64KB Shared memory -# Pascal GP100 has 48KB L1 cache --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 --gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 --gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 --gpgpu_shmem_size 65536 --gpgpu_shmem_size_PrefL1 65536 --gpgpu_shmem_size_PrefShared 65536 --gmem_skip_L1D 0 - -# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 32:32:32:32 - -# 4 KB Inst. --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 -# 12 KB Const --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 14 --gpgpu_operand_collector_num_units_sfu 8 --gpgpu_operand_collector_num_units_mem 10 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - -## In Pascal, a warp scheduler can issue 2 insts per cycle --gpgpu_max_insn_issue_per_warp 2 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 116 - -# for HBM, 32 channles, each (128 bits) 16 bytes width --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 16 --gpgpu_dram_burst_length 2 --dram_data_command_freq_ratio 2 # HBM is DDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS - -# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) -# Timing for 1 GHZ -# tRRDl and tWTR are missing, need to be added -#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: -# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" - -# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ --gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: - CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" - -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs --power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/PascalP100X/gpgpu-sim-3.x/gpuwattch_gtx480.xml b/configs/PascalP100X/gpgpu-sim-3.x/gpuwattch_gtx480.xml deleted file mode 100755 index 304e0fd..0000000 --- a/configs/PascalP100X/gpgpu-sim-3.x/gpuwattch_gtx480.xml +++ /dev/null @@ -1,538 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/config_fermi_islip.icnt b/configs/PascalTitanX/gpgpu-sim-3.x/config_fermi_islip.icnt deleted file mode 100644 index 602daee..0000000 --- a/configs/PascalTitanX/gpgpu-sim-3.x/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 52; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config deleted file mode 100644 index f78bd02..0000000 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ /dev/null @@ -1,156 +0,0 @@ -# This config models the Pascal GP102 (NVIDIA TITAN X) -# For more info about this card, see Nvidia White paper -# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 61 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 12 --gpgpu_n_sub_partition_per_mchannel 2 - -# Pascal clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA TITAN X clock domains are adopted from -# https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 1 SFU unit -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,1,1,4,1,1,6 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 1 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# SFU is 32-width in pascal, then dp units initiation is 1 cycle --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 4,8,4,4,130 - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP102 has 96KB Shared memory -# Pascal GP102 has 64KB L1 cache -# The defulat is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 --gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 --gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 --gpgpu_shmem_size 98304 --gpgpu_shmem_size_PrefL1 98304 --gpgpu_shmem_size_PrefShared 98304 --gmem_skip_L1D 1 - -# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 32:32:32:32 - -# 4 KB Inst. --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 -# 12 KB Const --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 - -# enable operand collector -## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units --gpgpu_operand_collector_num_units_sp 20 --gpgpu_operand_collector_num_units_sfu 4 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 -# gpgpu_num_reg_banks should be increased to 32 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - -## In Pascal, a warp scheduler can issue 2 insts per cycle --gpgpu_max_insn_issue_per_warp 2 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 116 - -# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) -# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition -# the atom size of GDDR5X (the smallest read request) is 32 bytes --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5X is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS - -# Use the same GDDR5 timing from hynix H5GQ1H24AFR -# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" - -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 4 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs --power_simulation_enabled 1 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpuwattch_gtx480.xml b/configs/PascalTitanX/gpgpu-sim-3.x/gpuwattch_gtx480.xml deleted file mode 100755 index 304e0fd..0000000 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpuwattch_gtx480.xml +++ /dev/null @@ -1,538 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- cgit v1.3 From 355c86895faf122deecb5de5ef17ff4ff9d654d9 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Wed, 16 May 2018 19:20:53 -0400 Subject: More sane naming convention --- configs/4.x-cfgs/GTX1080/config_fermi_islip.icnt | 70 +++ configs/4.x-cfgs/GTX1080/gpgpusim.config | 149 ++++++ configs/4.x-cfgs/GTX1080/gpuwattch_gtx1080Ti.xml | 538 ++++++++++++++++++++ configs/4.x-cfgs/GTX480/config_fermi_islip.icnt | 70 +++ configs/4.x-cfgs/GTX480/gpgpusim.config | 135 ++++++ configs/4.x-cfgs/GTX480/gpuwattch_gtx480.xml | 538 ++++++++++++++++++++ configs/4.x-cfgs/GTX750/config_fermi_islip.icnt | 70 +++ configs/4.x-cfgs/GTX750/gpgpusim.config | 131 +++++ configs/4.x-cfgs/GTX750/gpuwattch_gtx750Ti.xml | 539 +++++++++++++++++++++ .../4.x-cfgs/PASCAL_P100/config_fermi_islip.icnt | 73 +++ configs/4.x-cfgs/PASCAL_P100/gpgpusim.config | 173 +++++++ .../4.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt | 73 +++ configs/4.x-cfgs/PASCAL_TITANX/gpgpusim.config | 178 +++++++ configs/4.x-cfgs/QuadroFX5600/gpgpusim.config | 97 ++++ .../QuadroFX5600/gpuwattch_quadrofx5600.xml | 538 ++++++++++++++++++++ .../4.x-cfgs/QuadroFX5600/icnt_config_islip.icnt | 70 +++ .../4.x-cfgs/QuadroFX5800/config_quadro_islip.icnt | 69 +++ configs/4.x-cfgs/QuadroFX5800/gpgpusim.config | 87 ++++ .../4.x-cfgs/TeslaC2050/config_fermi_islip.icnt | 70 +++ configs/4.x-cfgs/TeslaC2050/gpgpusim.config | 133 +++++ .../4.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt | 74 +++ configs/4.x-cfgs/VOLTA_TITANV/gpgpusim.config | 186 +++++++ configs/GTX480/config_fermi_islip.icnt | 70 --- configs/GTX480/gpgpusim.config | 135 ------ configs/GTX480/gpuwattch_gtx480.xml | 538 -------------------- configs/GeForceGTX1080Ti/config_fermi_islip.icnt | 70 --- configs/GeForceGTX1080Ti/gpgpusim.config | 149 ------ configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml | 538 -------------------- configs/GeForceGTX750Ti/config_fermi_islip.icnt | 70 --- configs/GeForceGTX750Ti/gpgpusim.config | 131 ----- configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml | 539 --------------------- .../gpgpu-sim-4.x/config_fermi_islip.icnt | 74 --- .../gpgpu-sim-4.x/gpgpusim.config | 186 ------- configs/Pascal-P100-HBM/config_fermi_islip.icnt | 73 --- configs/Pascal-P100-HBM/gpgpusim.config | 173 ------- configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt | 73 --- configs/Pascal-P102-GDDR5X/gpgpusim.config | 178 ------- configs/QuadroFX5600/gpgpusim.config | 97 ---- configs/QuadroFX5600/gpuwattch_quadrofx5600.xml | 538 -------------------- configs/QuadroFX5600/icnt_config_islip.icnt | 70 --- configs/QuadroFX5800/config_quadro_islip.icnt | 69 --- configs/QuadroFX5800/gpgpusim.config | 87 ---- configs/TeslaC2050/config_fermi_islip.icnt | 70 --- configs/TeslaC2050/gpgpusim.config | 133 ----- 44 files changed, 4061 insertions(+), 4061 deletions(-) create mode 100644 configs/4.x-cfgs/GTX1080/config_fermi_islip.icnt create mode 100644 configs/4.x-cfgs/GTX1080/gpgpusim.config create mode 100755 configs/4.x-cfgs/GTX1080/gpuwattch_gtx1080Ti.xml create mode 100644 configs/4.x-cfgs/GTX480/config_fermi_islip.icnt create mode 100644 configs/4.x-cfgs/GTX480/gpgpusim.config create mode 100755 configs/4.x-cfgs/GTX480/gpuwattch_gtx480.xml create mode 100644 configs/4.x-cfgs/GTX750/config_fermi_islip.icnt create mode 100644 configs/4.x-cfgs/GTX750/gpgpusim.config create mode 100755 configs/4.x-cfgs/GTX750/gpuwattch_gtx750Ti.xml create mode 100644 configs/4.x-cfgs/PASCAL_P100/config_fermi_islip.icnt create mode 100644 configs/4.x-cfgs/PASCAL_P100/gpgpusim.config create mode 100644 configs/4.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt create mode 100644 configs/4.x-cfgs/PASCAL_TITANX/gpgpusim.config create mode 100644 configs/4.x-cfgs/QuadroFX5600/gpgpusim.config create mode 100644 configs/4.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml create mode 100644 configs/4.x-cfgs/QuadroFX5600/icnt_config_islip.icnt create mode 100644 configs/4.x-cfgs/QuadroFX5800/config_quadro_islip.icnt create mode 100644 configs/4.x-cfgs/QuadroFX5800/gpgpusim.config create mode 100644 configs/4.x-cfgs/TeslaC2050/config_fermi_islip.icnt create mode 100644 configs/4.x-cfgs/TeslaC2050/gpgpusim.config create mode 100644 configs/4.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt create mode 100644 configs/4.x-cfgs/VOLTA_TITANV/gpgpusim.config delete mode 100644 configs/GTX480/config_fermi_islip.icnt delete mode 100644 configs/GTX480/gpgpusim.config delete mode 100755 configs/GTX480/gpuwattch_gtx480.xml delete mode 100644 configs/GeForceGTX1080Ti/config_fermi_islip.icnt delete mode 100644 configs/GeForceGTX1080Ti/gpgpusim.config delete mode 100755 configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml delete mode 100644 configs/GeForceGTX750Ti/config_fermi_islip.icnt delete mode 100644 configs/GeForceGTX750Ti/gpgpusim.config delete mode 100755 configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml delete mode 100644 configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/config_fermi_islip.icnt delete mode 100644 configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/gpgpusim.config delete mode 100644 configs/Pascal-P100-HBM/config_fermi_islip.icnt delete mode 100644 configs/Pascal-P100-HBM/gpgpusim.config delete mode 100644 configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt delete mode 100644 configs/Pascal-P102-GDDR5X/gpgpusim.config delete mode 100644 configs/QuadroFX5600/gpgpusim.config delete mode 100644 configs/QuadroFX5600/gpuwattch_quadrofx5600.xml delete mode 100644 configs/QuadroFX5600/icnt_config_islip.icnt delete mode 100644 configs/QuadroFX5800/config_quadro_islip.icnt delete mode 100644 configs/QuadroFX5800/gpgpusim.config delete mode 100644 configs/TeslaC2050/config_fermi_islip.icnt delete mode 100644 configs/TeslaC2050/gpgpusim.config diff --git a/configs/4.x-cfgs/GTX1080/config_fermi_islip.icnt b/configs/4.x-cfgs/GTX1080/config_fermi_islip.icnt new file mode 100644 index 0000000..2a69ddd --- /dev/null +++ b/configs/4.x-cfgs/GTX1080/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 50; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/GTX1080/gpgpusim.config b/configs/4.x-cfgs/GTX1080/gpgpusim.config new file mode 100644 index 0000000..47c2b6a --- /dev/null +++ b/configs/4.x-cfgs/GTX1080/gpgpusim.config @@ -0,0 +1,149 @@ +# This config models the Pascal GP102 (GeForceGTX 1080Ti) + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 20 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 11 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 1,2,1,1,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The default is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_shmem_size 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 +-gpgpu_cache:dl2_texture_only 0 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +# gpgpu_num_reg_banks should be increased to 32, but it gives an error! +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) +# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" + +# Pascal has four schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/4.x-cfgs/GTX1080/gpuwattch_gtx1080Ti.xml b/configs/4.x-cfgs/GTX1080/gpuwattch_gtx1080Ti.xml new file mode 100755 index 0000000..02619ff --- /dev/null +++ b/configs/4.x-cfgs/GTX1080/gpuwattch_gtx1080Ti.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/4.x-cfgs/GTX480/config_fermi_islip.icnt b/configs/4.x-cfgs/GTX480/config_fermi_islip.icnt new file mode 100644 index 0000000..7820e4e --- /dev/null +++ b/configs/4.x-cfgs/GTX480/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 27; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/GTX480/gpgpusim.config b/configs/4.x-cfgs/GTX480/gpgpusim.config new file mode 100644 index 0000000..03fcda1 --- /dev/null +++ b/configs/4.x-cfgs/GTX480/gpgpusim.config @@ -0,0 +1,135 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 20 + + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 15 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 6 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Fermi clock domains +#-gpgpu_clock_domains ::: +# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided +# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 +-gpgpu_clock_domains 700.0:700.0:700.0:924.0 + +# shader core pipeline config +-gpgpu_shader_registers 32768 + +# This implies a maximum of 48 warps/SM +-gpgpu_shader_core_pipeline 1536:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +#For Fermi, DP unit =0, DP inst is executed on SFU +-gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 1 +-gpgpu_num_dp_units 0 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,1,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,16,8,8,130 + + +# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +-gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_shmem_size 49152 + +# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected +#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8 +#-gpgpu_shmem_size 16384 + +# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache +-gpgpu_cache:dl2 N:64:128:8,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 + +-gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_num_reg_banks 16 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +-gpgpu_max_insn_issue_per_warp 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 116 + +# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS + +# GDDR5 timing from hynix H5GQ1H24AFR +# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/4.x-cfgs/GTX480/gpuwattch_gtx480.xml b/configs/4.x-cfgs/GTX480/gpuwattch_gtx480.xml new file mode 100755 index 0000000..304e0fd --- /dev/null +++ b/configs/4.x-cfgs/GTX480/gpuwattch_gtx480.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/4.x-cfgs/GTX750/config_fermi_islip.icnt b/configs/4.x-cfgs/GTX750/config_fermi_islip.icnt new file mode 100644 index 0000000..069ca02 --- /dev/null +++ b/configs/4.x-cfgs/GTX750/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 7; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/GTX750/gpgpusim.config b/configs/4.x-cfgs/GTX750/gpgpusim.config new file mode 100644 index 0000000..9366f93 --- /dev/null +++ b/configs/4.x-cfgs/GTX750/gpgpusim.config @@ -0,0 +1,131 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 52 + + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 5 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 2 +-gpgpu_n_sub_partition_per_mchannel 1 + +# Maxwell clock domains +#-gpgpu_clock_domains ::: +# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number. +-gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 +-gpgpu_num_sp_units 8 +-gpgpu_num_sfu_units 32 +-gpgpu_num_dp_units 0 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 6,12,13,13,210 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 6,12,6,6,374 +-ptx_opcode_initiation_fp 1,1,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,16,8,8,130 + +-gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8 +-gmem_skip_L1D 1 +-gpgpu_shmem_size 65536 + +# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected +#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8 +#-gpgpu_shmem_size 16384 + +# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache +-gpgpu_cache:dl2 N:1024:128:8,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 + +-gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 N:16:128:32,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_num_reg_banks 16 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 150 +-dram_latency 130 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 300 + +# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 32 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS + +# GDDR5 timing from hynix H5GQ1H24AFR +# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# Maxwell has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +# power modeling is currently disabled for GTX750Ti. The gpuwattch_gtx750ti.xml file present is only a placeholder and has NOT been tested for accuracy. +# proper modeling of Maxwell power is planned, but should be considered completely unsupported at present. +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx750Ti.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/4.x-cfgs/GTX750/gpuwattch_gtx750Ti.xml b/configs/4.x-cfgs/GTX750/gpuwattch_gtx750Ti.xml new file mode 100755 index 0000000..e2b2324 --- /dev/null +++ b/configs/4.x-cfgs/GTX750/gpuwattch_gtx750Ti.xml @@ -0,0 +1,539 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/4.x-cfgs/PASCAL_P100/config_fermi_islip.icnt b/configs/4.x-cfgs/PASCAL_P100/config_fermi_islip.icnt new file mode 100644 index 0000000..e7c2c3b --- /dev/null +++ b/configs/4.x-cfgs/PASCAL_P100/config_fermi_islip.icnt @@ -0,0 +1,73 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 60; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 128; +input_buffer_size = 256; +ejection_buffer_size = 128; +boundary_buffer_size = 128; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/PASCAL_P100/gpgpusim.config b/configs/4.x-cfgs/PASCAL_P100/gpgpusim.config new file mode 100644 index 0000000..9a7259e --- /dev/null +++ b/configs/4.x-cfgs/PASCAL_P100/gpgpusim.config @@ -0,0 +1,173 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 60 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 32 +-gpgpu_n_sub_partition_per_mchannel 1 + +# Pscal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA GP100 clock domains are adopted from +# https://en.wikipedia.org/wiki/Nvidia_Tesla +-gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 2,2,2,1,2,2,2,1,6 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 2 +-gpgpu_num_dp_units 2 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 2,2,2,2,130 +-ptx_opcode_latency_sfu 8 +-ptx_opcode_initiation_sfu 4 + + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP100 has 64KB Shared memory +-gpgpu_cache:dl1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 65536 +-gpgpu_shmem_size_PrefShared 65536 +-gmem_skip_L1D 0 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 + +# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 4MB L2 cache +-gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:256:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 +-perf_sim_memcpy 0 + +# 4 KB Inst. +-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 60 + +## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units +-gpgpu_max_insn_issue_per_warp 2 +-gpgpu_dual_issue_diff_exec_units 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 192 + +# for HBM, 32 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: + CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" + +# HBM has dual bus interface, in which it can issue two col and row commands at a time +-dual_bus_interface 1 +# select lower bits for bnkgrp to increase bnkgrp parallelism +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + +# Pascal has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Pascal 100 +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/4.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt b/configs/4.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt new file mode 100644 index 0000000..714d933 --- /dev/null +++ b/configs/4.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt @@ -0,0 +1,73 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 52; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 64; +input_buffer_size = 256; +ejection_buffer_size = 64; +boundary_buffer_size = 64; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/PASCAL_TITANX/gpgpusim.config b/configs/4.x-cfgs/PASCAL_TITANX/gpgpusim.config new file mode 100644 index 0000000..3097d19 --- /dev/null +++ b/configs/4.x-cfgs/PASCAL_TITANX/gpgpusim.config @@ -0,0 +1,178 @@ +# This config models the Pascal GP102 (NVIDIA TITAN X) +# For more info about this card, see Nvidia White paper +# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 61 +-gpgpu_ignore_resources_limitation 1 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +# P102 has two semi-indp scheds per core, and two cores per cluster +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 12 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 + +# shader core pipeline config +-gpgpu_shader_registers 32768 + +# This implies a maximum of 32 warps/SM +-gpgpu_shader_core_pipeline 1024:32 +-gpgpu_shader_cta 16 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 4 SFU units +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 2 +-gpgpu_num_dp_units 1 + + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,8,8,8,130 +-ptx_opcode_initiation_sfu 4 +-ptx_opcode_latency_sfu 8 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 24KB L1 cache +# The defulat is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_shmem_size 49152 +-gpgpu_shmem_size_PrefL1 49152 +-gpgpu_shmem_size_PrefShared 49152 +-gmem_skip_L1D 1 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:128:4,16:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 +-perf_sim_memcpy 0 + +# 4 KB Inst. +-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 +# 48 KB Tex +# this is unused +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_operand_collector_num_in_ports_sfu 2 +-gpgpu_operand_collector_num_out_ports_sfu 2 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 +# gpgpu_num_reg_banks should be increased to 32 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +# Use Fermi Coalsce arhitetecture which is the same as Pascal +-gpgpu_coalesce_arch 61 + +## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units +-gpgpu_max_insn_issue_per_warp 2 +-gpgpu_dual_issue_diff_exec_units 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 100 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 240 + +# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) +# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: + CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" + +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + +# Pascal 102 has four schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Pascal 102 +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/4.x-cfgs/QuadroFX5600/gpgpusim.config b/configs/4.x-cfgs/QuadroFX5600/gpgpusim.config new file mode 100644 index 0000000..e3cab18 --- /dev/null +++ b/configs/4.x-cfgs/QuadroFX5600/gpgpusim.config @@ -0,0 +1,97 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 12 + +# high level architecture configuration +-gpgpu_n_clusters 8 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 6 +-gpgpu_clock_domains 337.5:600.0:600.0:800.0 + +# shader core pipeline config +-gpgpu_shader_registers 16384 +#8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though) +-gpgpu_shader_core_pipeline 768:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 1,0,1,1,1,0,1,1,1 +-gpgpu_num_sp_units 1 +-gpgpu_num_sfu_units 1 +-gpgpu_num_dp_units 0 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 1,1,19,25,145 +-ptx_opcode_initiation_int 1,1,4,4,32 +-ptx_opcode_latency_fp 1,1,1,1,30 +-ptx_opcode_initiation_fp 1,1,1,1,5 +-ptx_opcode_latency_dp 8,8,8,8,335 +-ptx_opcode_initiation_dp 8,8,8,8,130 + +# memory stage behaviour +-gpgpu_cache:il1 N:4:256:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 N:8:128:5,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 +-gpgpu_cache:dl2 N:16:256:8,L:B:m:W:L,A:16:4,4 +-gpgpu_cache:dl2_texture_only 1 + +# TLB parameters +#-gpgpu_cache:tlbl1 1:524288:16:1:L:R:m,A:32:8,8 +#-gpgpu_tlbl2_latency 45 + + +-gpgpu_shmem_warp_parts 2 + +# interconnection +-network_mode 1 +-inter_config_file icnt_config_islip.icnt + +# dram scheduler config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (30 core cycles). I.e. +# Total buffer space required = 30 x 800MHz / 337.5MHz = 71 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 55 + +# dram model config +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 4 +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS +# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz +# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11 + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 + + + +# Using cuobjdump to extract ptx/SASS +-gpgpu_ptx_use_cuobjdump 1 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 + +-visualizer_enabled 0 +-power_trace_enabled 0 +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_quadrofx5600.xml + +-steady_power_levels_enabled 1 +-steady_state_definition 8,4 diff --git a/configs/4.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml b/configs/4.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml new file mode 100644 index 0000000..2c5a6fc --- /dev/null +++ b/configs/4.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/4.x-cfgs/QuadroFX5600/icnt_config_islip.icnt b/configs/4.x-cfgs/QuadroFX5600/icnt_config_islip.icnt new file mode 100644 index 0000000..de3bcc8 --- /dev/null +++ b/configs/4.x-cfgs/QuadroFX5600/icnt_config_islip.icnt @@ -0,0 +1,70 @@ +//14*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we donot use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 14; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/QuadroFX5800/config_quadro_islip.icnt b/configs/4.x-cfgs/QuadroFX5800/config_quadro_islip.icnt new file mode 100644 index 0000000..cfe9cac --- /dev/null +++ b/configs/4.x-cfgs/QuadroFX5800/config_quadro_islip.icnt @@ -0,0 +1,69 @@ +//18*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we donot use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 18; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/QuadroFX5800/gpgpusim.config b/configs/4.x-cfgs/QuadroFX5800/gpgpusim.config new file mode 100644 index 0000000..56dbb17 --- /dev/null +++ b/configs/4.x-cfgs/QuadroFX5800/gpgpusim.config @@ -0,0 +1,87 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 13 + +# high level architecture configuration +-gpgpu_n_clusters 10 +-gpgpu_n_cores_per_cluster 3 +-gpgpu_n_mem 8 +-gpgpu_clock_domains 325.0:650.0:650.0:800.0 + +# shader core pipeline config +-gpgpu_shader_registers 16384 +-gpgpu_shader_core_pipeline 1024:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 1,0,1,1,1,0,1,1,1 +-gpgpu_num_sp_units 1 +-gpgpu_num_sfu_units 1 +-gpgpu_num_dp_units 0 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 1,1,19,25,145 +-ptx_opcode_initiation_int 1,1,4,4,32 +-ptx_opcode_latency_fp 1,1,1,1,30 +-ptx_opcode_initiation_fp 1,1,1,1,5 +-ptx_opcode_latency_dp 8,8,8,8,335 +-ptx_opcode_initiation_dp 8,8,8,8,130 + +# memory stage behaviour +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +-gpgpu_cache:il1 N:4:256:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 N:8:128:5,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 +-gpgpu_cache:dl2 N:16:256:8,L:B:m:W:L,A:16:4,4 +-gpgpu_cache:dl2_texture_only 1 + +-gpgpu_shmem_warp_parts 2 + +# interconnection +-network_mode 1 +-inter_config_file config_quadro_islip.icnt + +# dram scheduler config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (30 core cycles). I.e. +# Total buffer space required = 30 x 800MHz / 325MHz = 74 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 58 + +# dram model config +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 4 +-dram_data_command_freq_ratio 2 # GDDR3 is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS +# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz +-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11 + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 + +-visualizer_enabled 0 + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/4.x-cfgs/TeslaC2050/config_fermi_islip.icnt b/configs/4.x-cfgs/TeslaC2050/config_fermi_islip.icnt new file mode 100644 index 0000000..a11bd8e --- /dev/null +++ b/configs/4.x-cfgs/TeslaC2050/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//20*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we donot use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 26; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; diff --git a/configs/4.x-cfgs/TeslaC2050/gpgpusim.config b/configs/4.x-cfgs/TeslaC2050/gpgpusim.config new file mode 100644 index 0000000..aa5f5f3 --- /dev/null +++ b/configs/4.x-cfgs/TeslaC2050/gpgpusim.config @@ -0,0 +1,133 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 20 + +# Using cuobjdump to extract ptx/SASS +#-gpgpu_ptx_use_cuobjdump 1 # use default + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + + +# high level architecture configuration +-gpgpu_n_clusters 14 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 6 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Fermi clock domains +#-gpgpu_clock_domains ::: +# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided +# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 +-gpgpu_clock_domains 575.0:575.0:575.0:750.0 + +# shader core pipeline config +-gpgpu_shader_registers 32768 + +# This implies a maximum of 48 warps/SM +-gpgpu_shader_core_pipeline 1536:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 1 +-gpgpu_num_dp_units 0 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,1,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,16,8,8,130 + + +# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +-gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_shmem_size 49152 + +# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected +#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8 +#-gpgpu_shmem_size 16384 + +# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache +-gpgpu_cache:dl2 N:64:128:8,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 + +-gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_num_reg_banks 16 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +-gpgpu_max_insn_issue_per_warp 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 750MHz / 575MHz = 130 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 114 + +# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS + +# GDDR5 timing from hynix H5GQ1H24AFR +# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/4.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt b/configs/4.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt new file mode 100644 index 0000000..616e9f3 --- /dev/null +++ b/configs/4.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt @@ -0,0 +1,74 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 64; +n = 1; + +// Routing + +routing_function = dest_tag; + + +// Flow control + +num_vcs = 1; +vc_buf_size = 128; +input_buffer_size = 256; +ejection_buffer_size = 128; +boundary_buffer_size = 128; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/VOLTA_TITANV/gpgpusim.config b/configs/4.x-cfgs/VOLTA_TITANV/gpgpusim.config new file mode 100644 index 0000000..8969168 --- /dev/null +++ b/configs/4.x-cfgs/VOLTA_TITANV/gpgpusim.config @@ -0,0 +1,186 @@ +# This config models the Volta Titan X +# For more info about this card: +# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf +# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf +# https://devblogs.nvidia.com/inside-volta/ +# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 70 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 40 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 24 +-gpgpu_n_sub_partition_per_mchannel 1 + +# volta clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA GP100 clock domains are adopted from +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +-gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0 +# boost mode +# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 +-gpgpu_num_dp_units 4 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 2,2,2,2,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,4,4,4,130 +-ptx_opcode_latency_sfu 100 +-ptx_opcode_initiation_sfu 8 + + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP100 has 64KB Shared memory +-gpgpu_cache:dl1 S:64:128:8,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:64:128:16,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 1 +-gpgpu_shmem_size_PrefShared 98304 +-gmem_skip_L1D 0 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 + +# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache +-gpgpu_cache:dl2 S:64:128:24,L:B:m:F:L,A:256:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 +-perf_sim_memcpy 0 + +# 128 KB Inst. +-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 +# 64 KB Const +-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 60 + +## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units +-gpgpu_max_insn_issue_per_warp 1 +-gpgpu_dual_issue_diff_exec_units 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 192 + +# for HBM, 32 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: + CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" + +# HBM has dual bus interface, in which it can issue two col and row commands at a time +-dual_bus_interface 1 +# select lower bits for bnkgrp to increase bnkgrp parallelism +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + +# Pascal has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Pascal 100 +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/GTX480/config_fermi_islip.icnt b/configs/GTX480/config_fermi_islip.icnt deleted file mode 100644 index 7820e4e..0000000 --- a/configs/GTX480/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 27; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config deleted file mode 100644 index 03fcda1..0000000 --- a/configs/GTX480/gpgpusim.config +++ /dev/null @@ -1,135 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 20 - - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 15 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 6 --gpgpu_n_sub_partition_per_mchannel 2 - -# Fermi clock domains -#-gpgpu_clock_domains ::: -# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided -# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 700.0:700.0:700.0:924.0 - -# shader core pipeline config --gpgpu_shader_registers 32768 - -# This implies a maximum of 48 warps/SM --gpgpu_shader_core_pipeline 1536:32 --gpgpu_shader_cta 8 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -#For Fermi, DP unit =0, DP inst is executed on SFU --gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 1 --gpgpu_num_dp_units 0 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,2,2,1,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 8,16,8,8,130 - - -# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. --gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8 --gpgpu_shmem_size 49152 - -# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected -#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8 -#-gpgpu_shmem_size 16384 - -# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache --gpgpu_cache:dl2 N:64:128:8,L:B:m:W:L,A:32:4,4:0,32 --gpgpu_cache:dl2_texture_only 0 - --gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 --gpgpu_num_reg_banks 16 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - --gpgpu_max_insn_issue_per_warp 1 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 116 - -# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition --gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5 is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS - -# GDDR5 timing from hynix H5GQ1H24AFR -# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" - -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs --power_simulation_enabled 1 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 diff --git a/configs/GTX480/gpuwattch_gtx480.xml b/configs/GTX480/gpuwattch_gtx480.xml deleted file mode 100755 index 304e0fd..0000000 --- a/configs/GTX480/gpuwattch_gtx480.xml +++ /dev/null @@ -1,538 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/configs/GeForceGTX1080Ti/config_fermi_islip.icnt b/configs/GeForceGTX1080Ti/config_fermi_islip.icnt deleted file mode 100644 index 2a69ddd..0000000 --- a/configs/GeForceGTX1080Ti/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 50; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/GeForceGTX1080Ti/gpgpusim.config b/configs/GeForceGTX1080Ti/gpgpusim.config deleted file mode 100644 index 47c2b6a..0000000 --- a/configs/GeForceGTX1080Ti/gpgpusim.config +++ /dev/null @@ -1,149 +0,0 @@ -# This config models the Pascal GP102 (GeForceGTX 1080Ti) - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 20 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 11 --gpgpu_n_sub_partition_per_mchannel 2 - -# Pascal clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA TITAN X clock domains are adopted from -# https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 1 SFU unit -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,1,1,4,1,1,6 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 1 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# SFU is 32-width in pascal, then dp units initiation is 1 cycle --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,2,2,2,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 1,2,1,1,130 - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP102 has 96KB Shared memory -# Pascal GP102 has 64KB L1 cache -# The default is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 --gpgpu_shmem_size 98304 --gmem_skip_L1D 1 - -# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 --gpgpu_cache:dl2_texture_only 0 - -# 4 KB Inst. --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 -# 12 KB Const --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 - -# enable operand collector -## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units --gpgpu_operand_collector_num_units_sp 20 --gpgpu_operand_collector_num_units_sfu 4 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 -# gpgpu_num_reg_banks should be increased to 32, but it gives an error! --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - -## In Pascal, a warp scheduler can issue 2 insts per cycle --gpgpu_max_insn_issue_per_warp 2 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 116 - -# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) -# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition -# the atom size of GDDR5X (the smallest read request) is 32 bytes --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5X is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS - -# Use the same GDDR5 timing from hynix H5GQ1H24AFR -# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" - -# Pascal has four schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs --power_simulation_enabled 1 --gpuwattch_xml_file gpuwattch_gtx1080Ti.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml b/configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml deleted file mode 100755 index 02619ff..0000000 --- a/configs/GeForceGTX1080Ti/gpuwattch_gtx1080Ti.xml +++ /dev/null @@ -1,538 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/configs/GeForceGTX750Ti/config_fermi_islip.icnt b/configs/GeForceGTX750Ti/config_fermi_islip.icnt deleted file mode 100644 index 069ca02..0000000 --- a/configs/GeForceGTX750Ti/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 7; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config deleted file mode 100644 index 9366f93..0000000 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ /dev/null @@ -1,131 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 52 - - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 5 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 2 --gpgpu_n_sub_partition_per_mchannel 1 - -# Maxwell clock domains -#-gpgpu_clock_domains ::: -# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number. --gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 8 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 --gpgpu_num_sp_units 8 --gpgpu_num_sfu_units 32 --gpgpu_num_dp_units 0 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 6,12,13,13,210 --ptx_opcode_initiation_int 1,1,1,1,4 --ptx_opcode_latency_fp 6,12,6,6,374 --ptx_opcode_initiation_fp 1,1,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 8,16,8,8,130 - --gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8 --gmem_skip_L1D 1 --gpgpu_shmem_size 65536 - -# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected -#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8 -#-gpgpu_shmem_size 16384 - -# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache --gpgpu_cache:dl2 N:1024:128:8,L:B:m:W:L,A:32:4,4:0,32 --gpgpu_cache:dl2_texture_only 0 - --gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 N:16:128:32,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 --gpgpu_num_reg_banks 16 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - --gpgpu_max_insn_issue_per_warp 2 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 150 --dram_latency 130 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 300 - -# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition --gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 32 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5 is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS - -# GDDR5 timing from hynix H5GQ1H24AFR -# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" - -# Maxwell has four schedulers per core --gpgpu_num_sched_per_core 4 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs -# power modeling is currently disabled for GTX750Ti. The gpuwattch_gtx750ti.xml file present is only a placeholder and has NOT been tested for accuracy. -# proper modeling of Maxwell power is planned, but should be considered completely unsupported at present. --power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx750Ti.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 diff --git a/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml b/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml deleted file mode 100755 index e2b2324..0000000 --- a/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml +++ /dev/null @@ -1,539 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/config_fermi_islip.icnt b/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/config_fermi_islip.icnt deleted file mode 100644 index 616e9f3..0000000 --- a/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/config_fermi_islip.icnt +++ /dev/null @@ -1,74 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 40; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 64; -n = 1; - -// Routing - -routing_function = dest_tag; - - -// Flow control - -num_vcs = 1; -vc_buf_size = 128; -input_buffer_size = 256; -ejection_buffer_size = 128; -boundary_buffer_size = 128; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/gpgpusim.config b/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/gpgpusim.config deleted file mode 100644 index 8969168..0000000 --- a/configs/Nvidia-Titan-Volta/gpgpu-sim-4.x/gpgpusim.config +++ /dev/null @@ -1,186 +0,0 @@ -# This config models the Volta Titan X -# For more info about this card: -# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf -# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) -# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf -# https://devblogs.nvidia.com/inside-volta/ -# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 70 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 40 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 24 --gpgpu_n_sub_partition_per_mchannel 1 - -# volta clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA GP100 clock domains are adopted from -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) --gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0 -# boost mode -# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 4 --gpgpu_num_dp_units 4 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 2,2,2,2,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 2,2,2,2,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 4,4,4,4,130 --ptx_opcode_latency_sfu 100 --ptx_opcode_initiation_sfu 8 - - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP100 has 64KB Shared memory --gpgpu_cache:dl1 S:64:128:8,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefL1 S:64:128:16,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_shmem_size 65536 --gpgpu_shmem_size_PrefL1 1 --gpgpu_shmem_size_PrefShared 98304 --gmem_skip_L1D 0 --icnt_flit_size 40 --gpgpu_n_cluster_ejection_buffer_size 32 - -# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache --gpgpu_cache:dl2 S:64:128:24,L:B:m:F:L,A:256:4,32:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 64:64:64:64 --perf_sim_memcpy 0 - -# 128 KB Inst. --gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 -# 64 KB Const --gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 12 --gpgpu_operand_collector_num_units_sfu 6 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_units_dp 6 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 --gpgpu_operand_collector_num_in_ports_dp 1 --gpgpu_operand_collector_num_out_ports_dp 1 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 60 - -## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units --gpgpu_max_insn_issue_per_warp 1 --gpgpu_dual_issue_diff_exec_units 1 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 192 - -# for HBM, 32 channles, each (128 bits) 16 bytes width --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 16 --gpgpu_dram_burst_length 2 --dram_data_command_freq_ratio 2 # HBM is DDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS - -# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) -# Timing for 1 GHZ -# tRRDl and tWTR are missing, need to be added -#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: -# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" - -# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ --gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: - CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" - -# HBM has dual bus interface, in which it can issue two col and row commands at a time --dual_bus_interface 1 -# select lower bits for bnkgrp to increase bnkgrp parallelism --dram_bnk_indexing_policy 0 --dram_bnkgrp_indexing_policy 1 - -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 - -# Pascal has two schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs, disable it untill we create a real energy model for Pascal 100 --power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/Pascal-P100-HBM/config_fermi_islip.icnt b/configs/Pascal-P100-HBM/config_fermi_islip.icnt deleted file mode 100644 index e7c2c3b..0000000 --- a/configs/Pascal-P100-HBM/config_fermi_islip.icnt +++ /dev/null @@ -1,73 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 40; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 60; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 128; -input_buffer_size = 256; -ejection_buffer_size = 128; -boundary_buffer_size = 128; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config deleted file mode 100644 index 9a7259e..0000000 --- a/configs/Pascal-P100-HBM/gpgpusim.config +++ /dev/null @@ -1,173 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 60 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 32 --gpgpu_n_sub_partition_per_mchannel 1 - -# Pscal clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA GP100 clock domains are adopted from -# https://en.wikipedia.org/wiki/Nvidia_Tesla --gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 2,2,2,1,2,2,2,1,6 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 2 --gpgpu_num_dp_units 2 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 2,2,2,2,130 --ptx_opcode_latency_sfu 8 --ptx_opcode_initiation_sfu 4 - - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP100 has 64KB Shared memory --gpgpu_cache:dl1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefL1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefShared S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_shmem_size 65536 --gpgpu_shmem_size_PrefL1 65536 --gpgpu_shmem_size_PrefShared 65536 --gmem_skip_L1D 0 --icnt_flit_size 40 --gpgpu_n_cluster_ejection_buffer_size 32 - -# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 4MB L2 cache --gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:256:4,32:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 64:64:64:64 --perf_sim_memcpy 0 - -# 4 KB Inst. --gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 -# 12 KB Const --gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 12 --gpgpu_operand_collector_num_units_sfu 6 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_units_dp 6 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 --gpgpu_operand_collector_num_in_ports_dp 1 --gpgpu_operand_collector_num_out_ports_dp 1 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 60 - -## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units --gpgpu_max_insn_issue_per_warp 2 --gpgpu_dual_issue_diff_exec_units 1 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 192 - -# for HBM, 32 channles, each (128 bits) 16 bytes width --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 16 --gpgpu_dram_burst_length 2 --dram_data_command_freq_ratio 2 # HBM is DDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS - -# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) -# Timing for 1 GHZ -# tRRDl and tWTR are missing, need to be added -#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: -# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" - -# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ --gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: - CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" - -# HBM has dual bus interface, in which it can issue two col and row commands at a time --dual_bus_interface 1 -# select lower bits for bnkgrp to increase bnkgrp parallelism --dram_bnk_indexing_policy 0 --dram_bnkgrp_indexing_policy 1 - -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 - -# Pascal has two schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs, disable it untill we create a real energy model for Pascal 100 --power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt deleted file mode 100644 index 714d933..0000000 --- a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt +++ /dev/null @@ -1,73 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 40; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 52; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 64; -input_buffer_size = 256; -ejection_buffer_size = 64; -boundary_buffer_size = 64; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config deleted file mode 100644 index 3097d19..0000000 --- a/configs/Pascal-P102-GDDR5X/gpgpusim.config +++ /dev/null @@ -1,178 +0,0 @@ -# This config models the Pascal GP102 (NVIDIA TITAN X) -# For more info about this card, see Nvidia White paper -# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 61 --gpgpu_ignore_resources_limitation 1 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration -# P102 has two semi-indp scheds per core, and two cores per cluster --gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 12 --gpgpu_n_sub_partition_per_mchannel 2 - -# Pascal clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA TITAN X clock domains are adopted from -# https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 - -# shader core pipeline config --gpgpu_shader_registers 32768 - -# This implies a maximum of 32 warps/SM --gpgpu_shader_core_pipeline 1024:32 --gpgpu_shader_cta 16 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 4 SFU units -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 2 --gpgpu_num_dp_units 1 - - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 8,8,8,8,130 --ptx_opcode_initiation_sfu 4 --ptx_opcode_latency_sfu 8 - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP102 has 96KB Shared memory -# Pascal GP102 has 24KB L1 cache -# The defulat is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefL1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_shmem_size 49152 --gpgpu_shmem_size_PrefL1 49152 --gpgpu_shmem_size_PrefShared 49152 --gmem_skip_L1D 1 --icnt_flit_size 40 --gpgpu_n_cluster_ejection_buffer_size 32 - -# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:128:4,16:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 32:32:32:32 --perf_sim_memcpy 0 - -# 4 KB Inst. --gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 -# 48 KB Tex -# this is unused --gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 -# 12 KB Const --gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 12 --gpgpu_operand_collector_num_units_sfu 6 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_units_dp 6 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 --gpgpu_operand_collector_num_in_ports_sfu 2 --gpgpu_operand_collector_num_out_ports_sfu 2 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 --gpgpu_operand_collector_num_in_ports_dp 1 --gpgpu_operand_collector_num_out_ports_dp 1 -# gpgpu_num_reg_banks should be increased to 32 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 -# Use Fermi Coalsce arhitetecture which is the same as Pascal --gpgpu_coalesce_arch 61 - -## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units --gpgpu_max_insn_issue_per_warp 2 --gpgpu_dual_issue_diff_exec_units 1 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 100 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 240 - -# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) -# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition -# the atom size of GDDR5X (the smallest read request) is 32 bytes --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5X is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS - -# Use the same GDDR5 timing from hynix H5GQ1H24AFR -# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: - CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" - --dram_bnk_indexing_policy 0 --dram_bnkgrp_indexing_policy 1 - -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 - -# Pascal 102 has four schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs, disable it untill we create a real energy model for Pascal 102 --power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/QuadroFX5600/gpgpusim.config b/configs/QuadroFX5600/gpgpusim.config deleted file mode 100644 index e3cab18..0000000 --- a/configs/QuadroFX5600/gpgpusim.config +++ /dev/null @@ -1,97 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 12 - -# high level architecture configuration --gpgpu_n_clusters 8 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 6 --gpgpu_clock_domains 337.5:600.0:600.0:800.0 - -# shader core pipeline config --gpgpu_shader_registers 16384 -#8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though) --gpgpu_shader_core_pipeline 768:32 --gpgpu_shader_cta 8 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 1,0,1,1,1,0,1,1,1 --gpgpu_num_sp_units 1 --gpgpu_num_sfu_units 1 --gpgpu_num_dp_units 0 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 1,1,19,25,145 --ptx_opcode_initiation_int 1,1,4,4,32 --ptx_opcode_latency_fp 1,1,1,1,30 --ptx_opcode_initiation_fp 1,1,1,1,5 --ptx_opcode_latency_dp 8,8,8,8,335 --ptx_opcode_initiation_dp 8,8,8,8,130 - -# memory stage behaviour --gpgpu_cache:il1 N:4:256:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 N:8:128:5,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 --gpgpu_cache:dl2 N:16:256:8,L:B:m:W:L,A:16:4,4 --gpgpu_cache:dl2_texture_only 1 - -# TLB parameters -#-gpgpu_cache:tlbl1 1:524288:16:1:L:R:m,A:32:8,8 -#-gpgpu_tlbl2_latency 45 - - --gpgpu_shmem_warp_parts 2 - -# interconnection --network_mode 1 --inter_config_file icnt_config_islip.icnt - -# dram scheduler config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (30 core cycles). I.e. -# Total buffer space required = 30 x 800MHz / 337.5MHz = 71 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 55 - -# dram model config --gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 4 --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS -# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz -# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} --gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11 - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 - - - -# Using cuobjdump to extract ptx/SASS --gpgpu_ptx_use_cuobjdump 1 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 - --visualizer_enabled 0 --power_trace_enabled 0 --power_simulation_enabled 1 --gpuwattch_xml_file gpuwattch_quadrofx5600.xml - --steady_power_levels_enabled 1 --steady_state_definition 8,4 diff --git a/configs/QuadroFX5600/gpuwattch_quadrofx5600.xml b/configs/QuadroFX5600/gpuwattch_quadrofx5600.xml deleted file mode 100644 index 2c5a6fc..0000000 --- a/configs/QuadroFX5600/gpuwattch_quadrofx5600.xml +++ /dev/null @@ -1,538 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/configs/QuadroFX5600/icnt_config_islip.icnt b/configs/QuadroFX5600/icnt_config_islip.icnt deleted file mode 100644 index de3bcc8..0000000 --- a/configs/QuadroFX5600/icnt_config_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//14*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we donot use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 14; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/QuadroFX5800/config_quadro_islip.icnt b/configs/QuadroFX5800/config_quadro_islip.icnt deleted file mode 100644 index cfe9cac..0000000 --- a/configs/QuadroFX5800/config_quadro_islip.icnt +++ /dev/null @@ -1,69 +0,0 @@ -//18*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we donot use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 18; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config deleted file mode 100644 index 56dbb17..0000000 --- a/configs/QuadroFX5800/gpgpusim.config +++ /dev/null @@ -1,87 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 13 - -# high level architecture configuration --gpgpu_n_clusters 10 --gpgpu_n_cores_per_cluster 3 --gpgpu_n_mem 8 --gpgpu_clock_domains 325.0:650.0:650.0:800.0 - -# shader core pipeline config --gpgpu_shader_registers 16384 --gpgpu_shader_core_pipeline 1024:32 --gpgpu_shader_cta 8 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 1,0,1,1,1,0,1,1,1 --gpgpu_num_sp_units 1 --gpgpu_num_sfu_units 1 --gpgpu_num_dp_units 0 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 1,1,19,25,145 --ptx_opcode_initiation_int 1,1,4,4,32 --ptx_opcode_latency_fp 1,1,1,1,30 --ptx_opcode_initiation_fp 1,1,1,1,5 --ptx_opcode_latency_dp 8,8,8,8,335 --ptx_opcode_initiation_dp 8,8,8,8,130 - -# memory stage behaviour -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo --gpgpu_cache:il1 N:4:256:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 N:8:128:5,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 --gpgpu_cache:dl2 N:16:256:8,L:B:m:W:L,A:16:4,4 --gpgpu_cache:dl2_texture_only 1 - --gpgpu_shmem_warp_parts 2 - -# interconnection --network_mode 1 --inter_config_file config_quadro_islip.icnt - -# dram scheduler config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (30 core cycles). I.e. -# Total buffer space required = 30 x 800MHz / 325MHz = 74 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 58 - -# dram model config --gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 4 --dram_data_command_freq_ratio 2 # GDDR3 is DDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS -# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz --gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11 - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 - --visualizer_enabled 0 - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 diff --git a/configs/TeslaC2050/config_fermi_islip.icnt b/configs/TeslaC2050/config_fermi_islip.icnt deleted file mode 100644 index a11bd8e..0000000 --- a/configs/TeslaC2050/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//20*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we donot use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 26; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config deleted file mode 100644 index aa5f5f3..0000000 --- a/configs/TeslaC2050/gpgpusim.config +++ /dev/null @@ -1,133 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 20 - -# Using cuobjdump to extract ptx/SASS -#-gpgpu_ptx_use_cuobjdump 1 # use default - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - - -# high level architecture configuration --gpgpu_n_clusters 14 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 6 --gpgpu_n_sub_partition_per_mchannel 2 - -# Fermi clock domains -#-gpgpu_clock_domains ::: -# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided -# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 575.0:575.0:575.0:750.0 - -# shader core pipeline config --gpgpu_shader_registers 32768 - -# This implies a maximum of 48 warps/SM --gpgpu_shader_core_pipeline 1536:32 --gpgpu_shader_cta 8 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 1 --gpgpu_num_dp_units 0 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,2,2,1,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 8,16,8,8,130 - - -# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. --gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8 --gpgpu_shmem_size 49152 - -# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected -#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8 -#-gpgpu_shmem_size 16384 - -# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache --gpgpu_cache:dl2 N:64:128:8,L:B:m:W:L,A:32:4,4:0,32 --gpgpu_cache:dl2_texture_only 0 - --gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 --gpgpu_num_reg_banks 16 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - --gpgpu_max_insn_issue_per_warp 1 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 750MHz / 575MHz = 130 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 114 - -# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition --gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5 is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS - -# GDDR5 timing from hynix H5GQ1H24AFR -# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" - -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 -- cgit v1.3 From a851f6d6217396ebd8cd8a895ecad697336387b4 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 09:27:07 -0700 Subject: allows gpgpusim to select a set of texture array,attr,info but maybe not the right one --- src/abstract_hardware_model.h | 73 +++++++++++++++++++++++++++++++++++++------ src/cuda-sim/cuda-sim.cc | 30 ++++++++++++++++++ 2 files changed, 94 insertions(+), 9 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index f5708bc..ca41e68 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -522,22 +522,77 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); - assert(t != m_TextureRefToCudaArray.end()); - return t->second; + + for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); kv!= m_TextureRefToCudaArray.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f){ + + return kv->second; + } + } + + assert(false); +// std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); +// assert(t != m_TextureRefToCudaArray.end()); +// return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); - assert(t != m_TextureRefToTexureInfo.end()); - return t->second; + for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); kv!= m_TextureRefToTexureInfo.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f){ + + return kv->second; + } + } + + assert(false); +// std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); +// assert(t != m_TextureRefToTexureInfo.end()); +// return t->second; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToAttribute.find(texref); - assert(t != m_TextureRefToAttribute.end()); - return t->second; + for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f){ + + return kv->second; + } + } + + assert(false); +// std::map::const_iterator t=m_TextureRefToAttribute.find(texref); +// assert(t != m_TextureRefToAttribute.end()); +// return t->second; } const gpgpu_functional_sim_config &get_config() const { return m_function_model_config; } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 946043a..6e04ca8 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -140,6 +140,36 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { + // counts number of matches +// int normalized; +// enum cudaTextureFilterMode filterMode; +// enum cudaTextureAddressMode addressMode[3]; +// struct cudaChannelFormatDesc channelDesc; +// int x; +// int y; +// int z; +// int w; +// enum cudaChannelFormatKind f; +// int trMatches = 0; +// for (auto& kv : m_NameToTextureRef){ +// const struct textureReference* tr = kv.second; +// if (tr->normalized==texref->normalized&& +// tr->filterMode==texref->filterMode&& +// tr->addressMode[0]==texref->addressMode[0]&& +// tr->addressMode[1]==texref->addressMode[1]&& +// tr->addressMode[2]==texref->addressMode[2]&& +// tr->channelDesc.x==texref->channelDesc.x&& +// tr->channelDesc.y==texref->channelDesc.y&& +// tr->channelDesc.z==texref->channelDesc.z&& +// tr->channelDesc.w==texref->channelDesc.w&& +// tr->channelDesc.f==texref->channelDesc.f){ +// +// m_TextureRefToCudaArray[tr] = array; +// trMatches++; +// } +// } +// printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); +// assert(trMatches==1); m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; -- cgit v1.3 From 7546c12af13aca0fdcba6a339913120c0ffed50d Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 16:24:41 -0700 Subject: counting matches with same texref contents, added cuda8 fields to texref struct --- src/abstract_hardware_model.h | 143 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 130 insertions(+), 13 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index ca41e68..c21ff6d 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -25,6 +25,11 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#ifndef VERSION_EIGHT +#define VERSION_EIGHT +#endif + #ifndef ABSTRACT_HARDWARE_MODEL_INCLUDED #define ABSTRACT_HARDWARE_MODEL_INCLUDED @@ -445,6 +450,35 @@ struct textureReference { enum cudaTextureFilterMode filterMode; enum cudaTextureAddressMode addressMode[3]; struct cudaChannelFormatDesc channelDesc; + +#ifdef VERSION_EIGHT + /** + * Perform sRGB->linear conversion during texture read + */ + int sRGB; + /** + * Limit to the anisotropy ratio + */ + unsigned int maxAnisotropy; + /** + * Mipmap filter mode + */ + enum cudaTextureFilterMode mipmapFilterMode; + /** + * Offset applied to the supplied mipmap level + */ + float mipmapLevelBias; + /** + * Lower end of the mipmap level range to clamp access to + */ + float minMipmapLevelClamp; + /** + * Upper end of the mipmap level range to clamp access to + */ + float maxMipmapLevelClamp; + int __cudaReserved[15]; +#endif + }; #endif @@ -522,7 +556,8 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - + int matches = 0; + const struct cudaArray* t = NULL; for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); kv!= m_TextureRefToCudaArray.end(); kv ++){ const struct textureReference* tr = kv->first; if (tr->normalized==texref->normalized&& @@ -534,19 +569,49 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f){ - - return kv->second; + tr->channelDesc.f==texref->channelDesc.f && + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14] + ){ + matches++; + t = kv->second; + //return kv->second; } } - assert(false); + printf("matches (texarray) = %d\n", matches); + //assert(matches==1); + return t; + + //assert(false); + // std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); // assert(t != m_TextureRefToCudaArray.end()); // return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { + int matches = 0; + const struct textureInfo* t = NULL; for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); kv!= m_TextureRefToTexureInfo.end(); kv ++){ const struct textureReference* tr = kv->first; if (tr->normalized==texref->normalized&& @@ -558,13 +623,38 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f){ - - return kv->second; + tr->channelDesc.f==texref->channelDesc.f&& + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14]){ + matches++; + t = kv->second; + //return kv->second; } } - assert(false); + printf("matches (texinfo) = %d\n", matches); + //assert(matches==1); + return t; + // std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); // assert(t != m_TextureRefToTexureInfo.end()); // return t->second; @@ -572,6 +662,8 @@ public: const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { + int matches = 0; + const struct textureReferenceAttr* t = NULL; for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ const struct textureReference* tr = kv->first; if (tr->normalized==texref->normalized&& @@ -583,13 +675,38 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f){ - - return kv->second; + tr->channelDesc.f==texref->channelDesc.f&& + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14]){ + matches++; + t = kv->second; + //return kv->second; } } - assert(false); + printf("matches (texattr) = %d\n", matches); + //assert(matches==1); + return t; + // std::map::const_iterator t=m_TextureRefToAttribute.find(texref); // assert(t != m_TextureRefToAttribute.end()); // return t->second; -- cgit v1.3 From 9476c4ccf17949a67a430155dfc93e66ca73d4a8 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 16:26:55 -0700 Subject: abstract_hardware_model.h:texrefAttr is different and can be searched via pointer cuda-sim.cc: counts matches between cudaBinTextureToArray texref param (pointer) to texref pointers in m_NameToTextureRef --- src/abstract_hardware_model.h | 94 +++++++++++++++++++++---------------------- src/cuda-sim/cuda-sim.cc | 47 +++++++++++++++++----- 2 files changed, 84 insertions(+), 57 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index c21ff6d..608a7e2 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -662,54 +662,54 @@ public: const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { - int matches = 0; - const struct textureReferenceAttr* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f&& - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14]){ - matches++; - t = kv->second; - //return kv->second; - } - } - - printf("matches (texattr) = %d\n", matches); - //assert(matches==1); - return t; +// int matches = 0; +// const struct textureReferenceAttr* t = NULL; +// for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ +// const struct textureReference* tr = kv->first; +// if (tr->normalized==texref->normalized&& +// tr->filterMode==texref->filterMode&& +// tr->addressMode[0]==texref->addressMode[0]&& +// tr->addressMode[1]==texref->addressMode[1]&& +// tr->addressMode[2]==texref->addressMode[2]&& +// tr->channelDesc.x==texref->channelDesc.x&& +// tr->channelDesc.y==texref->channelDesc.y&& +// tr->channelDesc.z==texref->channelDesc.z&& +// tr->channelDesc.w==texref->channelDesc.w&& +// tr->channelDesc.f==texref->channelDesc.f&& +// tr->sRGB==texref->sRGB&& +// tr->maxAnisotropy==texref->maxAnisotropy&& +// tr->mipmapFilterMode==texref->mipmapFilterMode&& +// tr->mipmapLevelBias==texref->mipmapLevelBias&& +// tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& +// tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& +// tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& +// tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& +// tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& +// tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& +// tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& +// tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& +// tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& +// tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& +// tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& +// tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& +// tr->__cudaReserved[10]==texref->__cudaReserved[10]&& +// tr->__cudaReserved[11]==texref->__cudaReserved[11]&& +// tr->__cudaReserved[12]==texref->__cudaReserved[12]&& +// tr->__cudaReserved[13]==texref->__cudaReserved[13]&& +// tr->__cudaReserved[14]==texref->__cudaReserved[14]){ +// matches++; +// t = kv->second; +// //return kv->second; +// } +// } +// +// printf("matches (texattr) = %d\n", matches); +// //assert(matches==1); +// return t; -// std::map::const_iterator t=m_TextureRefToAttribute.find(texref); -// assert(t != m_TextureRefToAttribute.end()); -// return t->second; + std::map::const_iterator t=m_TextureRefToAttribute.find(texref); + assert(t != m_TextureRefToAttribute.end()); + return t->second; } const gpgpu_functional_sim_config &get_config() const { return m_function_model_config; } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 6e04ca8..39ffa63 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -26,6 +26,10 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +#ifndef VERSION_EIGHT +#define VERSION_EIGHT +#endif + #include "cuda-sim.h" #include "instructions.h" @@ -104,6 +108,16 @@ static address_type get_converge_point(address_type pc); void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) { + +//#ifdef VERSION_EIGHT +// int i; +// printf("%s ", name); +// printf("__cudaReserved:"); +// for (i = 0; i<15; i++){ +// printf(" %i", texref->__cudaReserved[i]); +// } +// printf("\n"); +//#endif std::string texname(name); m_NameToTextureRef[texname] = texref; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); @@ -140,16 +154,15 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { +//#ifdef VERSION_EIGHT +// int i; +// printf("__cudaReserved:"); +// for (i = 0; i<15; i++){ +// printf(" %i", texref->__cudaReserved[i]); +// } +// printf("\n"); +//#endif // counts number of matches -// int normalized; -// enum cudaTextureFilterMode filterMode; -// enum cudaTextureAddressMode addressMode[3]; -// struct cudaChannelFormatDesc channelDesc; -// int x; -// int y; -// int z; -// int w; -// enum cudaChannelFormatKind f; // int trMatches = 0; // for (auto& kv : m_NameToTextureRef){ // const struct textureReference* tr = kv.second; @@ -170,7 +183,21 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te // } // printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); // assert(trMatches==1); - m_TextureRefToCudaArray[texref] = array; + + //tests if texref pointer matches any pointer in m_NameToTextureRef map + int trMatches = 0; + for (auto& kv : m_NameToTextureRef){ + const struct textureReference* tr = kv.second; + if (tr==texref){ + m_TextureRefToCudaArray[tr] = array; + //printf("%s\n", kv.first); + trMatches++; + } + } + printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); + //assert(trMatches==1); + + //m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; unsigned int Tx, Ty; -- cgit v1.3 From ab1f21e94756b4276e97124a7f2af6bec645c81e Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 16:49:55 -0700 Subject: changed for loop, pass pipeline? --- 0517_13-24cudaReserved.log | 0 517-1418cudaReserved.log | 0 src/cuda-sim/cuda-sim.cc | 6 +++--- 3 files changed, 3 insertions(+), 3 deletions(-) create mode 100644 0517_13-24cudaReserved.log create mode 100644 517-1418cudaReserved.log diff --git a/0517_13-24cudaReserved.log b/0517_13-24cudaReserved.log new file mode 100644 index 0000000..e69de29 diff --git a/517-1418cudaReserved.log b/517-1418cudaReserved.log new file mode 100644 index 0000000..e69de29 diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 39ffa63..656091c 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -186,11 +186,11 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te //tests if texref pointer matches any pointer in m_NameToTextureRef map int trMatches = 0; - for (auto& kv : m_NameToTextureRef){ - const struct textureReference* tr = kv.second; + for (std::map::const_iterator kv = m_NameToTextureRef.begin(); kv!= m_NameToTextureRef.end(); kv ++){ + const struct textureReference* tr = kv->second; if (tr==texref){ m_TextureRefToCudaArray[tr] = array; - //printf("%s\n", kv.first); + printf("%s\n", kv->first.c_str()); trMatches++; } } -- cgit v1.3 From c8a6dfa9bb8bcec0458a58f0b702cd7b739ac1f1 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 18 May 2018 10:50:19 -0700 Subject: reverted cuda8 changes (extra fields) and assert texture bug fix's assumption --- src/abstract_hardware_model.h | 134 ++++++++++++++---------------------------- src/cuda-sim/cuda-sim.cc | 59 +------------------ 2 files changed, 45 insertions(+), 148 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 608a7e2..412c0a8 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -451,33 +451,32 @@ struct textureReference { enum cudaTextureAddressMode addressMode[3]; struct cudaChannelFormatDesc channelDesc; -#ifdef VERSION_EIGHT - /** - * Perform sRGB->linear conversion during texture read - */ - int sRGB; - /** - * Limit to the anisotropy ratio - */ - unsigned int maxAnisotropy; - /** - * Mipmap filter mode - */ - enum cudaTextureFilterMode mipmapFilterMode; - /** - * Offset applied to the supplied mipmap level - */ - float mipmapLevelBias; - /** - * Lower end of the mipmap level range to clamp access to - */ - float minMipmapLevelClamp; - /** - * Upper end of the mipmap level range to clamp access to - */ - float maxMipmapLevelClamp; - int __cudaReserved[15]; -#endif +//following commented section applies only to CUDA_VERSION 8+ +// /** +// * Perform sRGB->linear conversion during texture read +// */ +// int sRGB; +// /** +// * Limit to the anisotropy ratio +// */ +// unsigned int maxAnisotropy; +// /** +// * Mipmap filter mode +// */ +// enum cudaTextureFilterMode mipmapFilterMode; +// /** +// * Offset applied to the supplied mipmap level +// */ +// float mipmapLevelBias; +// /** +// * Lower end of the mipmap level range to clamp access to +// */ +// float minMipmapLevelClamp; +// /** +// * Upper end of the mipmap level range to clamp access to +// */ +// float maxMipmapLevelClamp; +// int __cudaReserved[15]; }; @@ -569,7 +568,10 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f && + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && tr->sRGB==texref->sRGB&& tr->maxAnisotropy==texref->maxAnisotropy&& tr->mipmapFilterMode==texref->mipmapFilterMode&& @@ -591,6 +593,7 @@ public: tr->__cudaReserved[12]==texref->__cudaReserved[12]&& tr->__cudaReserved[13]==texref->__cudaReserved[13]&& tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ ){ matches++; t = kv->second; @@ -598,15 +601,9 @@ public: } } - printf("matches (texarray) = %d\n", matches); - //assert(matches==1); + //printf("matches (texarray) = %d\n", matches); + assert(matches==1); return t; - - //assert(false); - -// std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); -// assert(t != m_TextureRefToCudaArray.end()); -// return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { @@ -623,7 +620,10 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f&& + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && tr->sRGB==texref->sRGB&& tr->maxAnisotropy==texref->maxAnisotropy&& tr->mipmapFilterMode==texref->mipmapFilterMode&& @@ -644,69 +644,23 @@ public: tr->__cudaReserved[11]==texref->__cudaReserved[11]&& tr->__cudaReserved[12]==texref->__cudaReserved[12]&& tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14]){ + tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ + ){ matches++; t = kv->second; - //return kv->second; } } - printf("matches (texinfo) = %d\n", matches); - //assert(matches==1); + //printf("matches (texinfo) = %d\n", matches); + assert(matches==1); return t; - -// std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); -// assert(t != m_TextureRefToTexureInfo.end()); -// return t->second; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { -// int matches = 0; -// const struct textureReferenceAttr* t = NULL; -// for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ -// const struct textureReference* tr = kv->first; -// if (tr->normalized==texref->normalized&& -// tr->filterMode==texref->filterMode&& -// tr->addressMode[0]==texref->addressMode[0]&& -// tr->addressMode[1]==texref->addressMode[1]&& -// tr->addressMode[2]==texref->addressMode[2]&& -// tr->channelDesc.x==texref->channelDesc.x&& -// tr->channelDesc.y==texref->channelDesc.y&& -// tr->channelDesc.z==texref->channelDesc.z&& -// tr->channelDesc.w==texref->channelDesc.w&& -// tr->channelDesc.f==texref->channelDesc.f&& -// tr->sRGB==texref->sRGB&& -// tr->maxAnisotropy==texref->maxAnisotropy&& -// tr->mipmapFilterMode==texref->mipmapFilterMode&& -// tr->mipmapLevelBias==texref->mipmapLevelBias&& -// tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& -// tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& -// tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& -// tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& -// tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& -// tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& -// tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& -// tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& -// tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& -// tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& -// tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& -// tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& -// tr->__cudaReserved[10]==texref->__cudaReserved[10]&& -// tr->__cudaReserved[11]==texref->__cudaReserved[11]&& -// tr->__cudaReserved[12]==texref->__cudaReserved[12]&& -// tr->__cudaReserved[13]==texref->__cudaReserved[13]&& -// tr->__cudaReserved[14]==texref->__cudaReserved[14]){ -// matches++; -// t = kv->second; -// //return kv->second; -// } -// } -// -// printf("matches (texattr) = %d\n", matches); -// //assert(matches==1); -// return t; - + //note textureReferenceAttr map behaves differently from cudaArray and + //textureInfo maps std::map::const_iterator t=m_TextureRefToAttribute.find(texref); assert(t != m_TextureRefToAttribute.end()); return t->second; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 656091c..946043a 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -26,10 +26,6 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -#ifndef VERSION_EIGHT -#define VERSION_EIGHT -#endif - #include "cuda-sim.h" #include "instructions.h" @@ -108,16 +104,6 @@ static address_type get_converge_point(address_type pc); void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) { - -//#ifdef VERSION_EIGHT -// int i; -// printf("%s ", name); -// printf("__cudaReserved:"); -// for (i = 0; i<15; i++){ -// printf(" %i", texref->__cudaReserved[i]); -// } -// printf("\n"); -//#endif std::string texname(name); m_NameToTextureRef[texname] = texref; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); @@ -154,50 +140,7 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { -//#ifdef VERSION_EIGHT -// int i; -// printf("__cudaReserved:"); -// for (i = 0; i<15; i++){ -// printf(" %i", texref->__cudaReserved[i]); -// } -// printf("\n"); -//#endif - // counts number of matches -// int trMatches = 0; -// for (auto& kv : m_NameToTextureRef){ -// const struct textureReference* tr = kv.second; -// if (tr->normalized==texref->normalized&& -// tr->filterMode==texref->filterMode&& -// tr->addressMode[0]==texref->addressMode[0]&& -// tr->addressMode[1]==texref->addressMode[1]&& -// tr->addressMode[2]==texref->addressMode[2]&& -// tr->channelDesc.x==texref->channelDesc.x&& -// tr->channelDesc.y==texref->channelDesc.y&& -// tr->channelDesc.z==texref->channelDesc.z&& -// tr->channelDesc.w==texref->channelDesc.w&& -// tr->channelDesc.f==texref->channelDesc.f){ -// -// m_TextureRefToCudaArray[tr] = array; -// trMatches++; -// } -// } -// printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); -// assert(trMatches==1); - - //tests if texref pointer matches any pointer in m_NameToTextureRef map - int trMatches = 0; - for (std::map::const_iterator kv = m_NameToTextureRef.begin(); kv!= m_NameToTextureRef.end(); kv ++){ - const struct textureReference* tr = kv->second; - if (tr==texref){ - m_TextureRefToCudaArray[tr] = array; - printf("%s\n", kv->first.c_str()); - trMatches++; - } - } - printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); - //assert(trMatches==1); - - //m_TextureRefToCudaArray[texref] = array; + m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; unsigned int Tx, Ty; -- cgit v1.3 From 9f6bfadf5c0b07d66b002e966940f9620f8b5623 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 18 May 2018 11:52:31 -0700 Subject: implemented unbind, currently only affects cudaArray map --- 0517_13-24cudaReserved.log | 0 517-1418cudaReserved.log | 0 libcuda/cuda_runtime_api.cc | 11 +++++++++++ src/abstract_hardware_model.h | 1 + src/cuda-sim/cuda-sim.cc | 5 +++++ 5 files changed, 17 insertions(+) delete mode 100644 0517_13-24cudaReserved.log delete mode 100644 517-1418cudaReserved.log diff --git a/0517_13-24cudaReserved.log b/0517_13-24cudaReserved.log deleted file mode 100644 index e69de29..0000000 diff --git a/517-1418cudaReserved.log b/517-1418cudaReserved.log deleted file mode 100644 index e69de29..0000000 diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index ef46f00..292d43d 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1002,6 +1002,14 @@ __host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureRefere __host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) { + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + printf("GPGPU-Sim PTX: in cudaUnbindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); + printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); + const struct cudaArray* array = gpu->get_texarray(texref); + printf("GPGPU-Sim PTX: texref = %p, array = %p\n", texref, array); + + gpu->gpgpu_ptx_sim_unbindTexture(texref); return g_last_cudaError = cudaSuccess; } @@ -2084,10 +2092,12 @@ void __cudaUnregisterFatBinary(void **fatCubinHandle) cudaError_t cudaDeviceReset ( void ) { // Should reset the simulated GPU + // TODO: Implement return g_last_cudaError = cudaSuccess; } cudaError_t CUDARTAPI cudaDeviceSynchronize(void){ // I don't know what this should do + // TODO: Implement return g_last_cudaError = cudaSuccess; } @@ -2189,6 +2199,7 @@ typedef unsigned long GLuint; cudaError_t cudaGLRegisterBufferObject(GLuint bufferObj) { printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); + // TODO: Implement return g_last_cudaError = cudaSuccess; } diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 412c0a8..3ef450e 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -544,6 +544,7 @@ public: class memory_space *get_surf_memory() { return m_surf_mem; } void gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array); + void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); void gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 946043a..ef16f43 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -183,6 +183,11 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te m_TextureRefToTexureInfo[texref] = texInfo; } +void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) +{ + m_TextureRefToCudaArray.erase(texref); +} + unsigned g_assemble_code_next_pc=0; std::map g_pc_to_finfo; std::vector function_info::s_g_pc_to_insn; -- cgit v1.3 From f754ad8e135befe98998193121fff6cb4c22fe25 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 18 May 2018 14:41:23 -0700 Subject: erase texinfo in unbind and disable assert --- src/abstract_hardware_model.h | 195 ++++++++++++++++++++++-------------------- src/cuda-sim/cuda-sim.cc | 2 + 2 files changed, 104 insertions(+), 93 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 3ef450e..6dd5436 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -556,106 +556,115 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - int matches = 0; - const struct cudaArray* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); kv!= m_TextureRefToCudaArray.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; - //return kv->second; + + std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); + if(t != m_TextureRefToCudaArray.end()){ + return t->second; + } else{ + int matches = 0; + const struct cudaArray* t = NULL; + for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); + kv!= m_TextureRefToCudaArray.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ + ){ + matches++; + t = kv->second; + } } + + //assert(matches==1); + return t; } - - //printf("matches (texarray) = %d\n", matches); - assert(matches==1); - return t; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { - int matches = 0; - const struct textureInfo* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); kv!= m_TextureRefToTexureInfo.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; + std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); + if(t != m_TextureRefToTexureInfo.end()){ + return t->second; + }else{ + int matches = 0; + const struct textureInfo* t = NULL; + for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); + kv!= m_TextureRefToTexureInfo.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ + ){ + matches++; + t = kv->second; + } } + //assert(matches==1); + return t; } - - //printf("matches (texinfo) = %d\n", matches); - assert(matches==1); - return t; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index ef16f43..6bdf75f 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -140,6 +140,7 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { + printf("GPGPU-Simm PTX: name from texture = %s\n", gpgpu_ptx_sim_findNamefromTexture(texref)); m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; @@ -186,6 +187,7 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) { m_TextureRefToCudaArray.erase(texref); + m_TextureRefToTexureInfo.erase(texref); } unsigned g_assemble_code_next_pc=0; -- cgit v1.3 From 5fd987fc8e551b823b0299e0cd3ce0d161fb84b6 Mon Sep 17 00:00:00 2001 From: Suchita Pati Date: Fri, 18 May 2018 20:28:02 -0500 Subject: ld operand in register space --- src/cuda-sim/instructions.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index e53aaab..583a49a 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2368,7 +2368,11 @@ void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand space = param_space_kernel; else if( ti.is_param_local() ) { space = param_space_local; - } else { + } + else if( ti.is_reg() ) { + space = param_space_kernel; + } + else { printf("GPGPU-Sim PTX: ERROR ** cannot resolve .param space for '%s'\n", s->name().c_str() ); abort(); } -- cgit v1.3 -- cgit v1.3 From 06845c73e513082262dff97ab3828c6c67ee2af2 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 19 May 2018 13:06:25 -0400 Subject: Config rename --- .../3.x-cfgs/PASCAL_P100/config_fermi_islip.icnt | 70 --- configs/3.x-cfgs/PASCAL_P100/gpgpusim.config | 156 ------ configs/3.x-cfgs/PASCAL_P100/gpuwattch_gtx480.xml | 538 -------------------- .../3.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt | 70 --- configs/3.x-cfgs/PASCAL_TITANX/gpgpusim.config | 156 ------ .../3.x-cfgs/PASCAL_TITANX/gpuwattch_gtx480.xml | 538 -------------------- configs/3.x-cfgs/SM6_P100/config_fermi_islip.icnt | 70 +++ configs/3.x-cfgs/SM6_P100/gpgpusim.config | 156 ++++++ configs/3.x-cfgs/SM6_P100/gpuwattch_gtx480.xml | 538 ++++++++++++++++++++ .../3.x-cfgs/SM6_TITANX/config_fermi_islip.icnt | 70 +++ configs/3.x-cfgs/SM6_TITANX/gpgpusim.config | 156 ++++++ configs/3.x-cfgs/SM6_TITANX/gpuwattch_gtx480.xml | 538 ++++++++++++++++++++ .../3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt | 70 +++ configs/3.x-cfgs/SM7_TITANV/gpgpusim.config | 165 +++++++ .../3.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt | 70 --- configs/3.x-cfgs/VOLTA_TITANV/gpgpusim.config | 165 ------- configs/4.x-cfgs/GTX1080/config_fermi_islip.icnt | 70 --- configs/4.x-cfgs/GTX1080/gpgpusim.config | 149 ------ configs/4.x-cfgs/GTX1080/gpuwattch_gtx1080Ti.xml | 538 -------------------- configs/4.x-cfgs/GTX480/config_fermi_islip.icnt | 70 --- configs/4.x-cfgs/GTX480/gpgpusim.config | 135 ------ configs/4.x-cfgs/GTX480/gpuwattch_gtx480.xml | 538 -------------------- configs/4.x-cfgs/GTX750/config_fermi_islip.icnt | 70 --- configs/4.x-cfgs/GTX750/gpgpusim.config | 131 ----- configs/4.x-cfgs/GTX750/gpuwattch_gtx750Ti.xml | 539 --------------------- .../4.x-cfgs/PASCAL_P100/config_fermi_islip.icnt | 73 --- configs/4.x-cfgs/PASCAL_P100/gpgpusim.config | 173 ------- .../4.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt | 73 --- configs/4.x-cfgs/PASCAL_TITANX/gpgpusim.config | 178 ------- configs/4.x-cfgs/QuadroFX5600/gpgpusim.config | 97 ---- .../QuadroFX5600/gpuwattch_quadrofx5600.xml | 538 -------------------- .../4.x-cfgs/QuadroFX5600/icnt_config_islip.icnt | 70 --- .../4.x-cfgs/QuadroFX5800/config_quadro_islip.icnt | 69 --- configs/4.x-cfgs/QuadroFX5800/gpgpusim.config | 87 ---- configs/4.x-cfgs/SM1_QFX5600/gpgpusim.config | 97 ++++ .../SM1_QFX5600/gpuwattch_quadrofx5600.xml | 538 ++++++++++++++++++++ .../4.x-cfgs/SM1_QFX5600/icnt_config_islip.icnt | 70 +++ .../4.x-cfgs/SM1_QFX5800/config_quadro_islip.icnt | 69 +++ configs/4.x-cfgs/SM1_QFX5800/gpgpusim.config | 87 ++++ configs/4.x-cfgs/SM2_C2050/config_fermi_islip.icnt | 70 +++ configs/4.x-cfgs/SM2_C2050/gpgpusim.config | 133 +++++ .../4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt | 70 +++ configs/4.x-cfgs/SM2_GTX480/gpgpusim.config | 135 ++++++ configs/4.x-cfgs/SM2_GTX480/gpuwattch_gtx480.xml | 538 ++++++++++++++++++++ .../4.x-cfgs/SM5_GTX750/config_fermi_islip.icnt | 70 +++ configs/4.x-cfgs/SM5_GTX750/gpgpusim.config | 131 +++++ configs/4.x-cfgs/SM5_GTX750/gpuwattch_gtx750Ti.xml | 539 +++++++++++++++++++++ .../4.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt | 70 +++ configs/4.x-cfgs/SM6_GTX1080/gpgpusim.config | 149 ++++++ .../4.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml | 538 ++++++++++++++++++++ configs/4.x-cfgs/SM6_P100/config_fermi_islip.icnt | 73 +++ configs/4.x-cfgs/SM6_P100/gpgpusim.config | 173 +++++++ .../4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt | 73 +++ configs/4.x-cfgs/SM6_TITANX/gpgpusim.config | 178 +++++++ .../4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt | 74 +++ configs/4.x-cfgs/SM7_TITANV/gpgpusim.config | 186 +++++++ .../4.x-cfgs/TeslaC2050/config_fermi_islip.icnt | 70 --- configs/4.x-cfgs/TeslaC2050/gpgpusim.config | 133 ----- .../4.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt | 74 --- configs/4.x-cfgs/VOLTA_TITANV/gpgpusim.config | 186 ------- 60 files changed, 5824 insertions(+), 5824 deletions(-) delete mode 100644 configs/3.x-cfgs/PASCAL_P100/config_fermi_islip.icnt delete mode 100644 configs/3.x-cfgs/PASCAL_P100/gpgpusim.config delete mode 100755 configs/3.x-cfgs/PASCAL_P100/gpuwattch_gtx480.xml delete mode 100644 configs/3.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt delete mode 100644 configs/3.x-cfgs/PASCAL_TITANX/gpgpusim.config delete mode 100755 configs/3.x-cfgs/PASCAL_TITANX/gpuwattch_gtx480.xml create mode 100644 configs/3.x-cfgs/SM6_P100/config_fermi_islip.icnt create mode 100644 configs/3.x-cfgs/SM6_P100/gpgpusim.config create mode 100755 configs/3.x-cfgs/SM6_P100/gpuwattch_gtx480.xml create mode 100644 configs/3.x-cfgs/SM6_TITANX/config_fermi_islip.icnt create mode 100644 configs/3.x-cfgs/SM6_TITANX/gpgpusim.config create mode 100755 configs/3.x-cfgs/SM6_TITANX/gpuwattch_gtx480.xml create mode 100644 configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt create mode 100644 configs/3.x-cfgs/SM7_TITANV/gpgpusim.config delete mode 100644 configs/3.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt delete mode 100644 configs/3.x-cfgs/VOLTA_TITANV/gpgpusim.config delete mode 100644 configs/4.x-cfgs/GTX1080/config_fermi_islip.icnt delete mode 100644 configs/4.x-cfgs/GTX1080/gpgpusim.config delete mode 100755 configs/4.x-cfgs/GTX1080/gpuwattch_gtx1080Ti.xml delete mode 100644 configs/4.x-cfgs/GTX480/config_fermi_islip.icnt delete mode 100644 configs/4.x-cfgs/GTX480/gpgpusim.config delete mode 100755 configs/4.x-cfgs/GTX480/gpuwattch_gtx480.xml delete mode 100644 configs/4.x-cfgs/GTX750/config_fermi_islip.icnt delete mode 100644 configs/4.x-cfgs/GTX750/gpgpusim.config delete mode 100755 configs/4.x-cfgs/GTX750/gpuwattch_gtx750Ti.xml delete mode 100644 configs/4.x-cfgs/PASCAL_P100/config_fermi_islip.icnt delete mode 100644 configs/4.x-cfgs/PASCAL_P100/gpgpusim.config delete mode 100644 configs/4.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt delete mode 100644 configs/4.x-cfgs/PASCAL_TITANX/gpgpusim.config delete mode 100644 configs/4.x-cfgs/QuadroFX5600/gpgpusim.config delete mode 100644 configs/4.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml delete mode 100644 configs/4.x-cfgs/QuadroFX5600/icnt_config_islip.icnt delete mode 100644 configs/4.x-cfgs/QuadroFX5800/config_quadro_islip.icnt delete mode 100644 configs/4.x-cfgs/QuadroFX5800/gpgpusim.config create mode 100644 configs/4.x-cfgs/SM1_QFX5600/gpgpusim.config create mode 100644 configs/4.x-cfgs/SM1_QFX5600/gpuwattch_quadrofx5600.xml create mode 100644 configs/4.x-cfgs/SM1_QFX5600/icnt_config_islip.icnt create mode 100644 configs/4.x-cfgs/SM1_QFX5800/config_quadro_islip.icnt create mode 100644 configs/4.x-cfgs/SM1_QFX5800/gpgpusim.config create mode 100644 configs/4.x-cfgs/SM2_C2050/config_fermi_islip.icnt create mode 100644 configs/4.x-cfgs/SM2_C2050/gpgpusim.config create mode 100644 configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt create mode 100644 configs/4.x-cfgs/SM2_GTX480/gpgpusim.config create mode 100755 configs/4.x-cfgs/SM2_GTX480/gpuwattch_gtx480.xml create mode 100644 configs/4.x-cfgs/SM5_GTX750/config_fermi_islip.icnt create mode 100644 configs/4.x-cfgs/SM5_GTX750/gpgpusim.config create mode 100755 configs/4.x-cfgs/SM5_GTX750/gpuwattch_gtx750Ti.xml create mode 100644 configs/4.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt create mode 100644 configs/4.x-cfgs/SM6_GTX1080/gpgpusim.config create mode 100755 configs/4.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml create mode 100644 configs/4.x-cfgs/SM6_P100/config_fermi_islip.icnt create mode 100644 configs/4.x-cfgs/SM6_P100/gpgpusim.config create mode 100644 configs/4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt create mode 100644 configs/4.x-cfgs/SM6_TITANX/gpgpusim.config create mode 100644 configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt create mode 100644 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config delete mode 100644 configs/4.x-cfgs/TeslaC2050/config_fermi_islip.icnt delete mode 100644 configs/4.x-cfgs/TeslaC2050/gpgpusim.config delete mode 100644 configs/4.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt delete mode 100644 configs/4.x-cfgs/VOLTA_TITANV/gpgpusim.config diff --git a/configs/3.x-cfgs/PASCAL_P100/config_fermi_islip.icnt b/configs/3.x-cfgs/PASCAL_P100/config_fermi_islip.icnt deleted file mode 100644 index d26c8d9..0000000 --- a/configs/3.x-cfgs/PASCAL_P100/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 60; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/3.x-cfgs/PASCAL_P100/gpgpusim.config b/configs/3.x-cfgs/PASCAL_P100/gpgpusim.config deleted file mode 100644 index a5e6736..0000000 --- a/configs/3.x-cfgs/PASCAL_P100/gpgpusim.config +++ /dev/null @@ -1,156 +0,0 @@ -# This config models the Pascal GP100 -# For more info about this card, see Nvidia White paper -# https://images.nvidia.com/content/pdf/tesla/whitepaper/pascal-architecture-whitepaper.pdf - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 60 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 32 --gpgpu_n_sub_partition_per_mchannel 1 - -# Pscal clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA GP100 clock domains are adopted from -# https://en.wikipedia.org/wiki/Nvidia_Tesla --gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 1 SFU unit -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 2,2,1,2,2,1,4 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 1 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# SFU is 32-width in pascal, then dp units initiation is 1 cycle --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 2,2,2,2,130 - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP100 has 64KB Shared memory -# Pascal GP100 has 48KB L1 cache --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 --gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 --gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 --gpgpu_shmem_size 65536 --gpgpu_shmem_size_PrefL1 65536 --gpgpu_shmem_size_PrefShared 65536 --gmem_skip_L1D 0 - -# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 32:32:32:32 - -# 4 KB Inst. --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 -# 12 KB Const --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 14 --gpgpu_operand_collector_num_units_sfu 8 --gpgpu_operand_collector_num_units_mem 10 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - -## In Pascal, a warp scheduler can issue 2 insts per cycle --gpgpu_max_insn_issue_per_warp 2 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 116 - -# for HBM, 32 channles, each (128 bits) 16 bytes width --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 16 --gpgpu_dram_burst_length 2 --dram_data_command_freq_ratio 2 # HBM is DDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS - -# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) -# Timing for 1 GHZ -# tRRDl and tWTR are missing, need to be added -#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: -# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" - -# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ --gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: - CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" - -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs --power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/3.x-cfgs/PASCAL_P100/gpuwattch_gtx480.xml b/configs/3.x-cfgs/PASCAL_P100/gpuwattch_gtx480.xml deleted file mode 100755 index 304e0fd..0000000 --- a/configs/3.x-cfgs/PASCAL_P100/gpuwattch_gtx480.xml +++ /dev/null @@ -1,538 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/configs/3.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt b/configs/3.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt deleted file mode 100644 index 602daee..0000000 --- a/configs/3.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 52; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/3.x-cfgs/PASCAL_TITANX/gpgpusim.config b/configs/3.x-cfgs/PASCAL_TITANX/gpgpusim.config deleted file mode 100644 index f78bd02..0000000 --- a/configs/3.x-cfgs/PASCAL_TITANX/gpgpusim.config +++ /dev/null @@ -1,156 +0,0 @@ -# This config models the Pascal GP102 (NVIDIA TITAN X) -# For more info about this card, see Nvidia White paper -# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 61 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 12 --gpgpu_n_sub_partition_per_mchannel 2 - -# Pascal clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA TITAN X clock domains are adopted from -# https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 1 SFU unit -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,1,1,4,1,1,6 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 1 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# SFU is 32-width in pascal, then dp units initiation is 1 cycle --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 4,8,4,4,130 - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP102 has 96KB Shared memory -# Pascal GP102 has 64KB L1 cache -# The defulat is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 --gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 --gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 --gpgpu_shmem_size 98304 --gpgpu_shmem_size_PrefL1 98304 --gpgpu_shmem_size_PrefShared 98304 --gmem_skip_L1D 1 - -# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 32:32:32:32 - -# 4 KB Inst. --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 -# 12 KB Const --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 - -# enable operand collector -## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units --gpgpu_operand_collector_num_units_sp 20 --gpgpu_operand_collector_num_units_sfu 4 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 -# gpgpu_num_reg_banks should be increased to 32 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - -## In Pascal, a warp scheduler can issue 2 insts per cycle --gpgpu_max_insn_issue_per_warp 2 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 116 - -# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) -# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition -# the atom size of GDDR5X (the smallest read request) is 32 bytes --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5X is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS - -# Use the same GDDR5 timing from hynix H5GQ1H24AFR -# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" - -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 4 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs --power_simulation_enabled 1 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/3.x-cfgs/PASCAL_TITANX/gpuwattch_gtx480.xml b/configs/3.x-cfgs/PASCAL_TITANX/gpuwattch_gtx480.xml deleted file mode 100755 index 304e0fd..0000000 --- a/configs/3.x-cfgs/PASCAL_TITANX/gpuwattch_gtx480.xml +++ /dev/null @@ -1,538 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/configs/3.x-cfgs/SM6_P100/config_fermi_islip.icnt b/configs/3.x-cfgs/SM6_P100/config_fermi_islip.icnt new file mode 100644 index 0000000..d26c8d9 --- /dev/null +++ b/configs/3.x-cfgs/SM6_P100/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 60; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/3.x-cfgs/SM6_P100/gpgpusim.config b/configs/3.x-cfgs/SM6_P100/gpgpusim.config new file mode 100644 index 0000000..a5e6736 --- /dev/null +++ b/configs/3.x-cfgs/SM6_P100/gpgpusim.config @@ -0,0 +1,156 @@ +# This config models the Pascal GP100 +# For more info about this card, see Nvidia White paper +# https://images.nvidia.com/content/pdf/tesla/whitepaper/pascal-architecture-whitepaper.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 60 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 32 +-gpgpu_n_sub_partition_per_mchannel 1 + +# Pscal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA GP100 clock domains are adopted from +# https://en.wikipedia.org/wiki/Nvidia_Tesla +-gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 2,2,1,2,2,1,4 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 2,2,2,2,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP100 has 64KB Shared memory +# Pascal GP100 has 48KB L1 cache +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 65536 +-gpgpu_shmem_size_PrefShared 65536 +-gmem_skip_L1D 0 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 14 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_units_mem 10 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for HBM, 32 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: + CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/3.x-cfgs/SM6_P100/gpuwattch_gtx480.xml b/configs/3.x-cfgs/SM6_P100/gpuwattch_gtx480.xml new file mode 100755 index 0000000..304e0fd --- /dev/null +++ b/configs/3.x-cfgs/SM6_P100/gpuwattch_gtx480.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/3.x-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/3.x-cfgs/SM6_TITANX/config_fermi_islip.icnt new file mode 100644 index 0000000..602daee --- /dev/null +++ b/configs/3.x-cfgs/SM6_TITANX/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 52; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config new file mode 100644 index 0000000..f78bd02 --- /dev/null +++ b/configs/3.x-cfgs/SM6_TITANX/gpgpusim.config @@ -0,0 +1,156 @@ +# This config models the Pascal GP102 (NVIDIA TITAN X) +# For more info about this card, see Nvidia White paper +# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 61 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 12 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,8,4,4,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The defulat is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefL1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1PrefShared 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_shmem_size 98304 +-gpgpu_shmem_size_PrefL1 98304 +-gpgpu_shmem_size_PrefShared 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +# gpgpu_num_reg_banks should be increased to 32 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) +# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 4 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/3.x-cfgs/SM6_TITANX/gpuwattch_gtx480.xml b/configs/3.x-cfgs/SM6_TITANX/gpuwattch_gtx480.xml new file mode 100755 index 0000000..304e0fd --- /dev/null +++ b/configs/3.x-cfgs/SM6_TITANX/gpuwattch_gtx480.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt new file mode 100644 index 0000000..fac792a --- /dev/null +++ b/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 64; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config new file mode 100644 index 0000000..f1ae2dc --- /dev/null +++ b/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config @@ -0,0 +1,165 @@ +# This config models the Volta Titan X +# For more info about this card: +# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf +# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf +# https://devblogs.nvidia.com/inside-volta/ +# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 70 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 40 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 24 +-gpgpu_n_sub_partition_per_mchannel 1 + +# volta clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA GP100 clock domains are adopted from +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +-gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0 +# boost mode +# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,4,1,4,4,1,9 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 2,2,2,2,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,4,4,4,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP100 has 64KB Shared memory +-gpgpu_cache:dl1 64:128:8,L:L:m:N:H,A:256:8,16:0 +-gpgpu_cache:dl1PrefL1 64:128:16,L:L:m:N:H,A:256:8,16:0 +-gpgpu_cache:dl1PrefShared 32:128:6,L:L:m:N:H,A:256:8,16:0 +-gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 1 +-gpgpu_shmem_size_PrefShared 98304 +-gmem_skip_L1D 0 + +# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache +-gpgpu_cache:dl2 64:128:24,L:B:m:W:L,A:256:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 + +# 128 KB Inst. +-gpgpu_cache:il1 64:128:16,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 64 KB Const +-gpgpu_const_cache:l1 128:64:8,L:R:f:N:L,A:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 14 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_units_mem 10 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for HBM, 32 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: + CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/3.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt b/configs/3.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt deleted file mode 100644 index fac792a..0000000 --- a/configs/3.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 64; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/3.x-cfgs/VOLTA_TITANV/gpgpusim.config b/configs/3.x-cfgs/VOLTA_TITANV/gpgpusim.config deleted file mode 100644 index f1ae2dc..0000000 --- a/configs/3.x-cfgs/VOLTA_TITANV/gpgpusim.config +++ /dev/null @@ -1,165 +0,0 @@ -# This config models the Volta Titan X -# For more info about this card: -# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf -# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) -# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf -# https://devblogs.nvidia.com/inside-volta/ -# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 70 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 40 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 24 --gpgpu_n_sub_partition_per_mchannel 1 - -# volta clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA GP100 clock domains are adopted from -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) --gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0 -# boost mode -# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,1,4,4,1,9 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 4 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 2,2,2,2,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 2,2,2,2,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 4,4,4,4,130 - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP100 has 64KB Shared memory --gpgpu_cache:dl1 64:128:8,L:L:m:N:H,A:256:8,16:0 --gpgpu_cache:dl1PrefL1 64:128:16,L:L:m:N:H,A:256:8,16:0 --gpgpu_cache:dl1PrefShared 32:128:6,L:L:m:N:H,A:256:8,16:0 --gpgpu_shmem_size 65536 --gpgpu_shmem_size_PrefL1 1 --gpgpu_shmem_size_PrefShared 98304 --gmem_skip_L1D 0 - -# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache --gpgpu_cache:dl2 64:128:24,L:B:m:W:L,A:256:4,32:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 64:64:64:64 - -# 128 KB Inst. --gpgpu_cache:il1 64:128:16,L:R:f:N:L,A:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 -# 64 KB Const --gpgpu_const_cache:l1 128:64:8,L:R:f:N:L,A:2:64,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 14 --gpgpu_operand_collector_num_units_sfu 8 --gpgpu_operand_collector_num_units_mem 10 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - -## In Pascal, a warp scheduler can issue 2 insts per cycle --gpgpu_max_insn_issue_per_warp 1 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 116 - -# for HBM, 32 channles, each (128 bits) 16 bytes width --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 16 --gpgpu_dram_burst_length 2 --dram_data_command_freq_ratio 2 # HBM is DDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS - -# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) -# Timing for 1 GHZ -# tRRDl and tWTR are missing, need to be added -#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: -# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" - -# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ --gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: - CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" - -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs --power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/4.x-cfgs/GTX1080/config_fermi_islip.icnt b/configs/4.x-cfgs/GTX1080/config_fermi_islip.icnt deleted file mode 100644 index 2a69ddd..0000000 --- a/configs/4.x-cfgs/GTX1080/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 50; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/4.x-cfgs/GTX1080/gpgpusim.config b/configs/4.x-cfgs/GTX1080/gpgpusim.config deleted file mode 100644 index 47c2b6a..0000000 --- a/configs/4.x-cfgs/GTX1080/gpgpusim.config +++ /dev/null @@ -1,149 +0,0 @@ -# This config models the Pascal GP102 (GeForceGTX 1080Ti) - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 20 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 11 --gpgpu_n_sub_partition_per_mchannel 2 - -# Pascal clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA TITAN X clock domains are adopted from -# https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 1 SFU unit -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,1,1,4,1,1,6 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 1 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# SFU is 32-width in pascal, then dp units initiation is 1 cycle --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,2,2,2,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 1,2,1,1,130 - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP102 has 96KB Shared memory -# Pascal GP102 has 64KB L1 cache -# The default is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 --gpgpu_shmem_size 98304 --gmem_skip_L1D 1 - -# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 --gpgpu_cache:dl2_texture_only 0 - -# 4 KB Inst. --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 -# 12 KB Const --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 - -# enable operand collector -## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units --gpgpu_operand_collector_num_units_sp 20 --gpgpu_operand_collector_num_units_sfu 4 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 -# gpgpu_num_reg_banks should be increased to 32, but it gives an error! --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - -## In Pascal, a warp scheduler can issue 2 insts per cycle --gpgpu_max_insn_issue_per_warp 2 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 116 - -# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) -# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition -# the atom size of GDDR5X (the smallest read request) is 32 bytes --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5X is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS - -# Use the same GDDR5 timing from hynix H5GQ1H24AFR -# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" - -# Pascal has four schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs --power_simulation_enabled 1 --gpuwattch_xml_file gpuwattch_gtx1080Ti.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/4.x-cfgs/GTX1080/gpuwattch_gtx1080Ti.xml b/configs/4.x-cfgs/GTX1080/gpuwattch_gtx1080Ti.xml deleted file mode 100755 index 02619ff..0000000 --- a/configs/4.x-cfgs/GTX1080/gpuwattch_gtx1080Ti.xml +++ /dev/null @@ -1,538 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/configs/4.x-cfgs/GTX480/config_fermi_islip.icnt b/configs/4.x-cfgs/GTX480/config_fermi_islip.icnt deleted file mode 100644 index 7820e4e..0000000 --- a/configs/4.x-cfgs/GTX480/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 27; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/4.x-cfgs/GTX480/gpgpusim.config b/configs/4.x-cfgs/GTX480/gpgpusim.config deleted file mode 100644 index 03fcda1..0000000 --- a/configs/4.x-cfgs/GTX480/gpgpusim.config +++ /dev/null @@ -1,135 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 20 - - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 15 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 6 --gpgpu_n_sub_partition_per_mchannel 2 - -# Fermi clock domains -#-gpgpu_clock_domains ::: -# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided -# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 700.0:700.0:700.0:924.0 - -# shader core pipeline config --gpgpu_shader_registers 32768 - -# This implies a maximum of 48 warps/SM --gpgpu_shader_core_pipeline 1536:32 --gpgpu_shader_cta 8 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -#For Fermi, DP unit =0, DP inst is executed on SFU --gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 1 --gpgpu_num_dp_units 0 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,2,2,1,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 8,16,8,8,130 - - -# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. --gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8 --gpgpu_shmem_size 49152 - -# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected -#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8 -#-gpgpu_shmem_size 16384 - -# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache --gpgpu_cache:dl2 N:64:128:8,L:B:m:W:L,A:32:4,4:0,32 --gpgpu_cache:dl2_texture_only 0 - --gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 --gpgpu_num_reg_banks 16 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - --gpgpu_max_insn_issue_per_warp 1 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 116 - -# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition --gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5 is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS - -# GDDR5 timing from hynix H5GQ1H24AFR -# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" - -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs --power_simulation_enabled 1 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 diff --git a/configs/4.x-cfgs/GTX480/gpuwattch_gtx480.xml b/configs/4.x-cfgs/GTX480/gpuwattch_gtx480.xml deleted file mode 100755 index 304e0fd..0000000 --- a/configs/4.x-cfgs/GTX480/gpuwattch_gtx480.xml +++ /dev/null @@ -1,538 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/configs/4.x-cfgs/GTX750/config_fermi_islip.icnt b/configs/4.x-cfgs/GTX750/config_fermi_islip.icnt deleted file mode 100644 index 069ca02..0000000 --- a/configs/4.x-cfgs/GTX750/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 7; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/4.x-cfgs/GTX750/gpgpusim.config b/configs/4.x-cfgs/GTX750/gpgpusim.config deleted file mode 100644 index 9366f93..0000000 --- a/configs/4.x-cfgs/GTX750/gpgpusim.config +++ /dev/null @@ -1,131 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 52 - - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 5 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 2 --gpgpu_n_sub_partition_per_mchannel 1 - -# Maxwell clock domains -#-gpgpu_clock_domains ::: -# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number. --gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 8 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 --gpgpu_num_sp_units 8 --gpgpu_num_sfu_units 32 --gpgpu_num_dp_units 0 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 6,12,13,13,210 --ptx_opcode_initiation_int 1,1,1,1,4 --ptx_opcode_latency_fp 6,12,6,6,374 --ptx_opcode_initiation_fp 1,1,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 8,16,8,8,130 - --gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8 --gmem_skip_L1D 1 --gpgpu_shmem_size 65536 - -# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected -#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8 -#-gpgpu_shmem_size 16384 - -# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache --gpgpu_cache:dl2 N:1024:128:8,L:B:m:W:L,A:32:4,4:0,32 --gpgpu_cache:dl2_texture_only 0 - --gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 N:16:128:32,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 --gpgpu_num_reg_banks 16 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - --gpgpu_max_insn_issue_per_warp 2 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 150 --dram_latency 130 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 300 - -# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition --gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 32 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5 is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS - -# GDDR5 timing from hynix H5GQ1H24AFR -# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" - -# Maxwell has four schedulers per core --gpgpu_num_sched_per_core 4 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs -# power modeling is currently disabled for GTX750Ti. The gpuwattch_gtx750ti.xml file present is only a placeholder and has NOT been tested for accuracy. -# proper modeling of Maxwell power is planned, but should be considered completely unsupported at present. --power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx750Ti.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 diff --git a/configs/4.x-cfgs/GTX750/gpuwattch_gtx750Ti.xml b/configs/4.x-cfgs/GTX750/gpuwattch_gtx750Ti.xml deleted file mode 100755 index e2b2324..0000000 --- a/configs/4.x-cfgs/GTX750/gpuwattch_gtx750Ti.xml +++ /dev/null @@ -1,539 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/configs/4.x-cfgs/PASCAL_P100/config_fermi_islip.icnt b/configs/4.x-cfgs/PASCAL_P100/config_fermi_islip.icnt deleted file mode 100644 index e7c2c3b..0000000 --- a/configs/4.x-cfgs/PASCAL_P100/config_fermi_islip.icnt +++ /dev/null @@ -1,73 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 40; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 60; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 128; -input_buffer_size = 256; -ejection_buffer_size = 128; -boundary_buffer_size = 128; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/4.x-cfgs/PASCAL_P100/gpgpusim.config b/configs/4.x-cfgs/PASCAL_P100/gpgpusim.config deleted file mode 100644 index 9a7259e..0000000 --- a/configs/4.x-cfgs/PASCAL_P100/gpgpusim.config +++ /dev/null @@ -1,173 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 60 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 32 --gpgpu_n_sub_partition_per_mchannel 1 - -# Pscal clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA GP100 clock domains are adopted from -# https://en.wikipedia.org/wiki/Nvidia_Tesla --gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 2,2,2,1,2,2,2,1,6 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 2 --gpgpu_num_dp_units 2 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 2,2,2,2,130 --ptx_opcode_latency_sfu 8 --ptx_opcode_initiation_sfu 4 - - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP100 has 64KB Shared memory --gpgpu_cache:dl1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefL1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefShared S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_shmem_size 65536 --gpgpu_shmem_size_PrefL1 65536 --gpgpu_shmem_size_PrefShared 65536 --gmem_skip_L1D 0 --icnt_flit_size 40 --gpgpu_n_cluster_ejection_buffer_size 32 - -# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 4MB L2 cache --gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:256:4,32:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 64:64:64:64 --perf_sim_memcpy 0 - -# 4 KB Inst. --gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 -# 12 KB Const --gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 12 --gpgpu_operand_collector_num_units_sfu 6 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_units_dp 6 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 --gpgpu_operand_collector_num_in_ports_dp 1 --gpgpu_operand_collector_num_out_ports_dp 1 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 60 - -## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units --gpgpu_max_insn_issue_per_warp 2 --gpgpu_dual_issue_diff_exec_units 1 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 192 - -# for HBM, 32 channles, each (128 bits) 16 bytes width --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 16 --gpgpu_dram_burst_length 2 --dram_data_command_freq_ratio 2 # HBM is DDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS - -# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) -# Timing for 1 GHZ -# tRRDl and tWTR are missing, need to be added -#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: -# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" - -# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ --gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: - CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" - -# HBM has dual bus interface, in which it can issue two col and row commands at a time --dual_bus_interface 1 -# select lower bits for bnkgrp to increase bnkgrp parallelism --dram_bnk_indexing_policy 0 --dram_bnkgrp_indexing_policy 1 - -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 - -# Pascal has two schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs, disable it untill we create a real energy model for Pascal 100 --power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/4.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt b/configs/4.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt deleted file mode 100644 index 714d933..0000000 --- a/configs/4.x-cfgs/PASCAL_TITANX/config_fermi_islip.icnt +++ /dev/null @@ -1,73 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 40; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 52; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 64; -input_buffer_size = 256; -ejection_buffer_size = 64; -boundary_buffer_size = 64; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/4.x-cfgs/PASCAL_TITANX/gpgpusim.config b/configs/4.x-cfgs/PASCAL_TITANX/gpgpusim.config deleted file mode 100644 index 3097d19..0000000 --- a/configs/4.x-cfgs/PASCAL_TITANX/gpgpusim.config +++ /dev/null @@ -1,178 +0,0 @@ -# This config models the Pascal GP102 (NVIDIA TITAN X) -# For more info about this card, see Nvidia White paper -# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 61 --gpgpu_ignore_resources_limitation 1 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration -# P102 has two semi-indp scheds per core, and two cores per cluster --gpgpu_n_clusters 28 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 12 --gpgpu_n_sub_partition_per_mchannel 2 - -# Pascal clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA TITAN X clock domains are adopted from -# https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 - -# shader core pipeline config --gpgpu_shader_registers 32768 - -# This implies a maximum of 32 warps/SM --gpgpu_shader_core_pipeline 1024:32 --gpgpu_shader_cta 16 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP102 has 4 SP SIMD units and 4 SFU units -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 2 --gpgpu_num_dp_units 1 - - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,1,1,1,4 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 8,8,8,8,130 --ptx_opcode_initiation_sfu 4 --ptx_opcode_latency_sfu 8 - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP102 has 96KB Shared memory -# Pascal GP102 has 24KB L1 cache -# The defulat is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefL1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_shmem_size 49152 --gpgpu_shmem_size_PrefL1 49152 --gpgpu_shmem_size_PrefShared 49152 --gmem_skip_L1D 1 --icnt_flit_size 40 --gpgpu_n_cluster_ejection_buffer_size 32 - -# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:128:4,16:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 32:32:32:32 --perf_sim_memcpy 0 - -# 4 KB Inst. --gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 -# 48 KB Tex -# this is unused --gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 -# 12 KB Const --gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 12 --gpgpu_operand_collector_num_units_sfu 6 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_units_dp 6 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 --gpgpu_operand_collector_num_in_ports_sfu 2 --gpgpu_operand_collector_num_out_ports_sfu 2 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 --gpgpu_operand_collector_num_in_ports_dp 1 --gpgpu_operand_collector_num_out_ports_dp 1 -# gpgpu_num_reg_banks should be increased to 32 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 -# Use Fermi Coalsce arhitetecture which is the same as Pascal --gpgpu_coalesce_arch 61 - -## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units --gpgpu_max_insn_issue_per_warp 2 --gpgpu_dual_issue_diff_exec_units 1 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 100 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 240 - -# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) -# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition -# the atom size of GDDR5X (the smallest read request) is 32 bytes --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5X is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS - -# Use the same GDDR5 timing from hynix H5GQ1H24AFR -# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: - CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" - --dram_bnk_indexing_policy 0 --dram_bnkgrp_indexing_policy 1 - -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 - -# Pascal 102 has four schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs, disable it untill we create a real energy model for Pascal 102 --power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - diff --git a/configs/4.x-cfgs/QuadroFX5600/gpgpusim.config b/configs/4.x-cfgs/QuadroFX5600/gpgpusim.config deleted file mode 100644 index e3cab18..0000000 --- a/configs/4.x-cfgs/QuadroFX5600/gpgpusim.config +++ /dev/null @@ -1,97 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 12 - -# high level architecture configuration --gpgpu_n_clusters 8 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 6 --gpgpu_clock_domains 337.5:600.0:600.0:800.0 - -# shader core pipeline config --gpgpu_shader_registers 16384 -#8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though) --gpgpu_shader_core_pipeline 768:32 --gpgpu_shader_cta 8 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 1,0,1,1,1,0,1,1,1 --gpgpu_num_sp_units 1 --gpgpu_num_sfu_units 1 --gpgpu_num_dp_units 0 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 1,1,19,25,145 --ptx_opcode_initiation_int 1,1,4,4,32 --ptx_opcode_latency_fp 1,1,1,1,30 --ptx_opcode_initiation_fp 1,1,1,1,5 --ptx_opcode_latency_dp 8,8,8,8,335 --ptx_opcode_initiation_dp 8,8,8,8,130 - -# memory stage behaviour --gpgpu_cache:il1 N:4:256:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 N:8:128:5,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 --gpgpu_cache:dl2 N:16:256:8,L:B:m:W:L,A:16:4,4 --gpgpu_cache:dl2_texture_only 1 - -# TLB parameters -#-gpgpu_cache:tlbl1 1:524288:16:1:L:R:m,A:32:8,8 -#-gpgpu_tlbl2_latency 45 - - --gpgpu_shmem_warp_parts 2 - -# interconnection --network_mode 1 --inter_config_file icnt_config_islip.icnt - -# dram scheduler config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (30 core cycles). I.e. -# Total buffer space required = 30 x 800MHz / 337.5MHz = 71 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 55 - -# dram model config --gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 4 --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS -# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz -# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} --gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11 - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 - - - -# Using cuobjdump to extract ptx/SASS --gpgpu_ptx_use_cuobjdump 1 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 - --visualizer_enabled 0 --power_trace_enabled 0 --power_simulation_enabled 1 --gpuwattch_xml_file gpuwattch_quadrofx5600.xml - --steady_power_levels_enabled 1 --steady_state_definition 8,4 diff --git a/configs/4.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml b/configs/4.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml deleted file mode 100644 index 2c5a6fc..0000000 --- a/configs/4.x-cfgs/QuadroFX5600/gpuwattch_quadrofx5600.xml +++ /dev/null @@ -1,538 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/configs/4.x-cfgs/QuadroFX5600/icnt_config_islip.icnt b/configs/4.x-cfgs/QuadroFX5600/icnt_config_islip.icnt deleted file mode 100644 index de3bcc8..0000000 --- a/configs/4.x-cfgs/QuadroFX5600/icnt_config_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//14*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we donot use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 14; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/4.x-cfgs/QuadroFX5800/config_quadro_islip.icnt b/configs/4.x-cfgs/QuadroFX5800/config_quadro_islip.icnt deleted file mode 100644 index cfe9cac..0000000 --- a/configs/4.x-cfgs/QuadroFX5800/config_quadro_islip.icnt +++ /dev/null @@ -1,69 +0,0 @@ -//18*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we donot use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 18; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/4.x-cfgs/QuadroFX5800/gpgpusim.config b/configs/4.x-cfgs/QuadroFX5800/gpgpusim.config deleted file mode 100644 index 56dbb17..0000000 --- a/configs/4.x-cfgs/QuadroFX5800/gpgpusim.config +++ /dev/null @@ -1,87 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 13 - -# high level architecture configuration --gpgpu_n_clusters 10 --gpgpu_n_cores_per_cluster 3 --gpgpu_n_mem 8 --gpgpu_clock_domains 325.0:650.0:650.0:800.0 - -# shader core pipeline config --gpgpu_shader_registers 16384 --gpgpu_shader_core_pipeline 1024:32 --gpgpu_shader_cta 8 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 1,0,1,1,1,0,1,1,1 --gpgpu_num_sp_units 1 --gpgpu_num_sfu_units 1 --gpgpu_num_dp_units 0 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 1,1,19,25,145 --ptx_opcode_initiation_int 1,1,4,4,32 --ptx_opcode_latency_fp 1,1,1,1,30 --ptx_opcode_initiation_fp 1,1,1,1,5 --ptx_opcode_latency_dp 8,8,8,8,335 --ptx_opcode_initiation_dp 8,8,8,8,130 - -# memory stage behaviour -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo --gpgpu_cache:il1 N:4:256:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 N:8:128:5,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 --gpgpu_cache:dl2 N:16:256:8,L:B:m:W:L,A:16:4,4 --gpgpu_cache:dl2_texture_only 1 - --gpgpu_shmem_warp_parts 2 - -# interconnection --network_mode 1 --inter_config_file config_quadro_islip.icnt - -# dram scheduler config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (30 core cycles). I.e. -# Total buffer space required = 30 x 800MHz / 325MHz = 74 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 58 - -# dram model config --gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 4 --dram_data_command_freq_ratio 2 # GDDR3 is DDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS -# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz --gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11 - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 - --visualizer_enabled 0 - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 diff --git a/configs/4.x-cfgs/SM1_QFX5600/gpgpusim.config b/configs/4.x-cfgs/SM1_QFX5600/gpgpusim.config new file mode 100644 index 0000000..e3cab18 --- /dev/null +++ b/configs/4.x-cfgs/SM1_QFX5600/gpgpusim.config @@ -0,0 +1,97 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 12 + +# high level architecture configuration +-gpgpu_n_clusters 8 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 6 +-gpgpu_clock_domains 337.5:600.0:600.0:800.0 + +# shader core pipeline config +-gpgpu_shader_registers 16384 +#8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though) +-gpgpu_shader_core_pipeline 768:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 1,0,1,1,1,0,1,1,1 +-gpgpu_num_sp_units 1 +-gpgpu_num_sfu_units 1 +-gpgpu_num_dp_units 0 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 1,1,19,25,145 +-ptx_opcode_initiation_int 1,1,4,4,32 +-ptx_opcode_latency_fp 1,1,1,1,30 +-ptx_opcode_initiation_fp 1,1,1,1,5 +-ptx_opcode_latency_dp 8,8,8,8,335 +-ptx_opcode_initiation_dp 8,8,8,8,130 + +# memory stage behaviour +-gpgpu_cache:il1 N:4:256:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 N:8:128:5,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 +-gpgpu_cache:dl2 N:16:256:8,L:B:m:W:L,A:16:4,4 +-gpgpu_cache:dl2_texture_only 1 + +# TLB parameters +#-gpgpu_cache:tlbl1 1:524288:16:1:L:R:m,A:32:8,8 +#-gpgpu_tlbl2_latency 45 + + +-gpgpu_shmem_warp_parts 2 + +# interconnection +-network_mode 1 +-inter_config_file icnt_config_islip.icnt + +# dram scheduler config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (30 core cycles). I.e. +# Total buffer space required = 30 x 800MHz / 337.5MHz = 71 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 55 + +# dram model config +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 4 +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS +# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz +# {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11 + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 + + + +# Using cuobjdump to extract ptx/SASS +-gpgpu_ptx_use_cuobjdump 1 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 + +-visualizer_enabled 0 +-power_trace_enabled 0 +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_quadrofx5600.xml + +-steady_power_levels_enabled 1 +-steady_state_definition 8,4 diff --git a/configs/4.x-cfgs/SM1_QFX5600/gpuwattch_quadrofx5600.xml b/configs/4.x-cfgs/SM1_QFX5600/gpuwattch_quadrofx5600.xml new file mode 100644 index 0000000..2c5a6fc --- /dev/null +++ b/configs/4.x-cfgs/SM1_QFX5600/gpuwattch_quadrofx5600.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/4.x-cfgs/SM1_QFX5600/icnt_config_islip.icnt b/configs/4.x-cfgs/SM1_QFX5600/icnt_config_islip.icnt new file mode 100644 index 0000000..de3bcc8 --- /dev/null +++ b/configs/4.x-cfgs/SM1_QFX5600/icnt_config_islip.icnt @@ -0,0 +1,70 @@ +//14*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we donot use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 14; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/SM1_QFX5800/config_quadro_islip.icnt b/configs/4.x-cfgs/SM1_QFX5800/config_quadro_islip.icnt new file mode 100644 index 0000000..cfe9cac --- /dev/null +++ b/configs/4.x-cfgs/SM1_QFX5800/config_quadro_islip.icnt @@ -0,0 +1,69 @@ +//18*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we donot use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 18; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/SM1_QFX5800/gpgpusim.config b/configs/4.x-cfgs/SM1_QFX5800/gpgpusim.config new file mode 100644 index 0000000..56dbb17 --- /dev/null +++ b/configs/4.x-cfgs/SM1_QFX5800/gpgpusim.config @@ -0,0 +1,87 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 13 + +# high level architecture configuration +-gpgpu_n_clusters 10 +-gpgpu_n_cores_per_cluster 3 +-gpgpu_n_mem 8 +-gpgpu_clock_domains 325.0:650.0:650.0:800.0 + +# shader core pipeline config +-gpgpu_shader_registers 16384 +-gpgpu_shader_core_pipeline 1024:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 1,0,1,1,1,0,1,1,1 +-gpgpu_num_sp_units 1 +-gpgpu_num_sfu_units 1 +-gpgpu_num_dp_units 0 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 1,1,19,25,145 +-ptx_opcode_initiation_int 1,1,4,4,32 +-ptx_opcode_latency_fp 1,1,1,1,30 +-ptx_opcode_initiation_fp 1,1,1,1,5 +-ptx_opcode_latency_dp 8,8,8,8,335 +-ptx_opcode_initiation_dp 8,8,8,8,130 + +# memory stage behaviour +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +-gpgpu_cache:il1 N:4:256:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 N:8:128:5,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 +-gpgpu_cache:dl2 N:16:256:8,L:B:m:W:L,A:16:4,4 +-gpgpu_cache:dl2_texture_only 1 + +-gpgpu_shmem_warp_parts 2 + +# interconnection +-network_mode 1 +-inter_config_file config_quadro_islip.icnt + +# dram scheduler config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (30 core cycles). I.e. +# Total buffer space required = 30 x 800MHz / 325MHz = 74 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 58 + +# dram model config +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 4 +-dram_data_command_freq_ratio 2 # GDDR3 is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS +# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz +-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11 + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 + +-visualizer_enabled 0 + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/4.x-cfgs/SM2_C2050/config_fermi_islip.icnt b/configs/4.x-cfgs/SM2_C2050/config_fermi_islip.icnt new file mode 100644 index 0000000..a11bd8e --- /dev/null +++ b/configs/4.x-cfgs/SM2_C2050/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//20*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we donot use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 26; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; diff --git a/configs/4.x-cfgs/SM2_C2050/gpgpusim.config b/configs/4.x-cfgs/SM2_C2050/gpgpusim.config new file mode 100644 index 0000000..aa5f5f3 --- /dev/null +++ b/configs/4.x-cfgs/SM2_C2050/gpgpusim.config @@ -0,0 +1,133 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 20 + +# Using cuobjdump to extract ptx/SASS +#-gpgpu_ptx_use_cuobjdump 1 # use default + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + + +# high level architecture configuration +-gpgpu_n_clusters 14 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 6 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Fermi clock domains +#-gpgpu_clock_domains ::: +# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided +# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 +-gpgpu_clock_domains 575.0:575.0:575.0:750.0 + +# shader core pipeline config +-gpgpu_shader_registers 32768 + +# This implies a maximum of 48 warps/SM +-gpgpu_shader_core_pipeline 1536:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 1 +-gpgpu_num_dp_units 0 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,1,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,16,8,8,130 + + +# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +-gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_shmem_size 49152 + +# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected +#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8 +#-gpgpu_shmem_size 16384 + +# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache +-gpgpu_cache:dl2 N:64:128:8,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 + +-gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_num_reg_banks 16 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +-gpgpu_max_insn_issue_per_warp 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 750MHz / 575MHz = 130 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 114 + +# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS + +# GDDR5 timing from hynix H5GQ1H24AFR +# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt b/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt new file mode 100644 index 0000000..7820e4e --- /dev/null +++ b/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 27; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config new file mode 100644 index 0000000..03fcda1 --- /dev/null +++ b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config @@ -0,0 +1,135 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 20 + + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 15 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 6 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Fermi clock domains +#-gpgpu_clock_domains ::: +# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided +# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 +-gpgpu_clock_domains 700.0:700.0:700.0:924.0 + +# shader core pipeline config +-gpgpu_shader_registers 32768 + +# This implies a maximum of 48 warps/SM +-gpgpu_shader_core_pipeline 1536:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +#For Fermi, DP unit =0, DP inst is executed on SFU +-gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 1 +-gpgpu_num_dp_units 0 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,1,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,16,8,8,130 + + +# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +-gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_shmem_size 49152 + +# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected +#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8 +#-gpgpu_shmem_size 16384 + +# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache +-gpgpu_cache:dl2 N:64:128:8,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 + +-gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_num_reg_banks 16 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +-gpgpu_max_insn_issue_per_warp 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 116 + +# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS + +# GDDR5 timing from hynix H5GQ1H24AFR +# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/4.x-cfgs/SM2_GTX480/gpuwattch_gtx480.xml b/configs/4.x-cfgs/SM2_GTX480/gpuwattch_gtx480.xml new file mode 100755 index 0000000..304e0fd --- /dev/null +++ b/configs/4.x-cfgs/SM2_GTX480/gpuwattch_gtx480.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/4.x-cfgs/SM5_GTX750/config_fermi_islip.icnt b/configs/4.x-cfgs/SM5_GTX750/config_fermi_islip.icnt new file mode 100644 index 0000000..069ca02 --- /dev/null +++ b/configs/4.x-cfgs/SM5_GTX750/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 7; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/SM5_GTX750/gpgpusim.config b/configs/4.x-cfgs/SM5_GTX750/gpgpusim.config new file mode 100644 index 0000000..9366f93 --- /dev/null +++ b/configs/4.x-cfgs/SM5_GTX750/gpgpusim.config @@ -0,0 +1,131 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 52 + + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 5 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 2 +-gpgpu_n_sub_partition_per_mchannel 1 + +# Maxwell clock domains +#-gpgpu_clock_domains ::: +# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number. +-gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 +-gpgpu_num_sp_units 8 +-gpgpu_num_sfu_units 32 +-gpgpu_num_dp_units 0 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 6,12,13,13,210 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 6,12,6,6,374 +-ptx_opcode_initiation_fp 1,1,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,16,8,8,130 + +-gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8 +-gmem_skip_L1D 1 +-gpgpu_shmem_size 65536 + +# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected +#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8 +#-gpgpu_shmem_size 16384 + +# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache +-gpgpu_cache:dl2 N:1024:128:8,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 + +-gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 N:16:128:32,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_num_reg_banks 16 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 150 +-dram_latency 130 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 300 + +# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 32 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS + +# GDDR5 timing from hynix H5GQ1H24AFR +# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# Maxwell has four schedulers per core +-gpgpu_num_sched_per_core 4 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +# power modeling is currently disabled for GTX750Ti. The gpuwattch_gtx750ti.xml file present is only a placeholder and has NOT been tested for accuracy. +# proper modeling of Maxwell power is planned, but should be considered completely unsupported at present. +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx750Ti.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/4.x-cfgs/SM5_GTX750/gpuwattch_gtx750Ti.xml b/configs/4.x-cfgs/SM5_GTX750/gpuwattch_gtx750Ti.xml new file mode 100755 index 0000000..e2b2324 --- /dev/null +++ b/configs/4.x-cfgs/SM5_GTX750/gpuwattch_gtx750Ti.xml @@ -0,0 +1,539 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/4.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt new file mode 100644 index 0000000..2a69ddd --- /dev/null +++ b/configs/4.x-cfgs/SM6_GTX1080/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 50; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/SM6_GTX1080/gpgpusim.config b/configs/4.x-cfgs/SM6_GTX1080/gpgpusim.config new file mode 100644 index 0000000..47c2b6a --- /dev/null +++ b/configs/4.x-cfgs/SM6_GTX1080/gpgpusim.config @@ -0,0 +1,149 @@ +# This config models the Pascal GP102 (GeForceGTX 1080Ti) + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 20 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 11 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 1,2,1,1,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The default is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_shmem_size 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 +-gpgpu_cache:dl2_texture_only 0 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +# gpgpu_num_reg_banks should be increased to 32, but it gives an error! +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) +# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" + +# Pascal has four schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/4.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml b/configs/4.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml new file mode 100755 index 0000000..02619ff --- /dev/null +++ b/configs/4.x-cfgs/SM6_GTX1080/gpuwattch_gtx1080Ti.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/configs/4.x-cfgs/SM6_P100/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_P100/config_fermi_islip.icnt new file mode 100644 index 0000000..e7c2c3b --- /dev/null +++ b/configs/4.x-cfgs/SM6_P100/config_fermi_islip.icnt @@ -0,0 +1,73 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 60; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 128; +input_buffer_size = 256; +ejection_buffer_size = 128; +boundary_buffer_size = 128; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/SM6_P100/gpgpusim.config b/configs/4.x-cfgs/SM6_P100/gpgpusim.config new file mode 100644 index 0000000..9a7259e --- /dev/null +++ b/configs/4.x-cfgs/SM6_P100/gpgpusim.config @@ -0,0 +1,173 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 60 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 32 +-gpgpu_n_sub_partition_per_mchannel 1 + +# Pscal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA GP100 clock domains are adopted from +# https://en.wikipedia.org/wiki/Nvidia_Tesla +-gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 2,2,2,1,2,2,2,1,6 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 2 +-gpgpu_num_dp_units 2 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 2,2,2,2,130 +-ptx_opcode_latency_sfu 8 +-ptx_opcode_initiation_sfu 4 + + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP100 has 64KB Shared memory +-gpgpu_cache:dl1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:64:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 65536 +-gpgpu_shmem_size_PrefShared 65536 +-gmem_skip_L1D 0 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 + +# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 4MB L2 cache +-gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:256:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 +-perf_sim_memcpy 0 + +# 4 KB Inst. +-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 60 + +## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units +-gpgpu_max_insn_issue_per_warp 2 +-gpgpu_dual_issue_diff_exec_units 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 192 + +# for HBM, 32 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: + CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" + +# HBM has dual bus interface, in which it can issue two col and row commands at a time +-dual_bus_interface 1 +# select lower bits for bnkgrp to increase bnkgrp parallelism +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + +# Pascal has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Pascal 100 +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt new file mode 100644 index 0000000..714d933 --- /dev/null +++ b/configs/4.x-cfgs/SM6_TITANX/config_fermi_islip.icnt @@ -0,0 +1,73 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 52; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 64; +input_buffer_size = 256; +ejection_buffer_size = 64; +boundary_buffer_size = 64; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config new file mode 100644 index 0000000..3097d19 --- /dev/null +++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config @@ -0,0 +1,178 @@ +# This config models the Pascal GP102 (NVIDIA TITAN X) +# For more info about this card, see Nvidia White paper +# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 61 +-gpgpu_ignore_resources_limitation 1 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +# P102 has two semi-indp scheds per core, and two cores per cluster +-gpgpu_n_clusters 28 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 12 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 + +# shader core pipeline config +-gpgpu_shader_registers 32768 + +# This implies a maximum of 32 warps/SM +-gpgpu_shader_core_pipeline 1024:32 +-gpgpu_shader_cta 16 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 4 SFU units +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 2 +-gpgpu_num_dp_units 1 + + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,8,8,8,130 +-ptx_opcode_initiation_sfu 4 +-ptx_opcode_latency_sfu 8 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 24KB L1 cache +# The defulat is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_shmem_size 49152 +-gpgpu_shmem_size_PrefL1 49152 +-gpgpu_shmem_size_PrefShared 49152 +-gmem_skip_L1D 1 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:128:4,16:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 32:32:32:32 +-perf_sim_memcpy 0 + +# 4 KB Inst. +-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 +# 48 KB Tex +# this is unused +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_operand_collector_num_in_ports_sfu 2 +-gpgpu_operand_collector_num_out_ports_sfu 2 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 +# gpgpu_num_reg_banks should be increased to 32 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +# Use Fermi Coalsce arhitetecture which is the same as Pascal +-gpgpu_coalesce_arch 61 + +## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units +-gpgpu_max_insn_issue_per_warp 2 +-gpgpu_dual_issue_diff_exec_units 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 100 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 240 + +# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits) +# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: + CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" + +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + +# Pascal 102 has four schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Pascal 102 +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt new file mode 100644 index 0000000..616e9f3 --- /dev/null +++ b/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt @@ -0,0 +1,74 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 40; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 64; +n = 1; + +// Routing + +routing_function = dest_tag; + + +// Flow control + +num_vcs = 1; +vc_buf_size = 128; +input_buffer_size = 256; +ejection_buffer_size = 128; +boundary_buffer_size = 128; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config new file mode 100644 index 0000000..8969168 --- /dev/null +++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config @@ -0,0 +1,186 @@ +# This config models the Volta Titan X +# For more info about this card: +# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf +# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf +# https://devblogs.nvidia.com/inside-volta/ +# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 70 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 40 +-gpgpu_n_cores_per_cluster 2 +-gpgpu_n_mem 24 +-gpgpu_n_sub_partition_per_mchannel 1 + +# volta clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA GP100 clock domains are adopted from +# https://en.wikipedia.org/wiki/Volta_(microarchitecture) +-gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0 +# boost mode +# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 +-gpgpu_num_dp_units 4 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from +# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 2,2,2,2,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 2,2,2,2,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 4,4,4,4,130 +-ptx_opcode_latency_sfu 100 +-ptx_opcode_initiation_sfu 8 + + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP100 has 64KB Shared memory +-gpgpu_cache:dl1 S:64:128:8,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:64:128:16,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_shmem_size 65536 +-gpgpu_shmem_size_PrefL1 1 +-gpgpu_shmem_size_PrefShared 98304 +-gmem_skip_L1D 0 +-icnt_flit_size 40 +-gpgpu_n_cluster_ejection_buffer_size 32 + +# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache +-gpgpu_cache:dl2 S:64:128:24,L:B:m:F:L,A:256:4,32:0,32 +-gpgpu_cache:dl2_texture_only 0 +-gpgpu_dram_partition_queues 64:64:64:64 +-perf_sim_memcpy 0 + +# 128 KB Inst. +-gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 +# 64 KB Const +-gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 +-gpgpu_coalesce_arch 60 + +## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units +-gpgpu_max_insn_issue_per_warp 1 +-gpgpu_dual_issue_diff_exec_units 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 192 + +# for HBM, 32 channles, each (128 bits) 16 bytes width +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 16 +-gpgpu_dram_burst_length 2 +-dram_data_command_freq_ratio 2 # HBM is DDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS + +# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) +# Timing for 1 GHZ +# tRRDl and tWTR are missing, need to be added +#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: +# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" + +# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ +-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: + CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" + +# HBM has dual bus interface, in which it can issue two col and row commands at a time +-dual_bus_interface 1 +# select lower bits for bnkgrp to increase bnkgrp parallelism +-dram_bnk_indexing_policy 0 +-dram_bnkgrp_indexing_policy 1 + +#-Seperate_Write_Queue_Enable 1 +#-Write_Queue_Size 64:56:32 + +# Pascal has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs, disable it untill we create a real energy model for Pascal 100 +-power_simulation_enabled 0 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/configs/4.x-cfgs/TeslaC2050/config_fermi_islip.icnt b/configs/4.x-cfgs/TeslaC2050/config_fermi_islip.icnt deleted file mode 100644 index a11bd8e..0000000 --- a/configs/4.x-cfgs/TeslaC2050/config_fermi_islip.icnt +++ /dev/null @@ -1,70 +0,0 @@ -//20*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 32; - -// currently we donot use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 26; -n = 1; - -// Routing - -routing_function = dest_tag; - -// Flow control - -num_vcs = 1; -vc_buf_size = 8; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; diff --git a/configs/4.x-cfgs/TeslaC2050/gpgpusim.config b/configs/4.x-cfgs/TeslaC2050/gpgpusim.config deleted file mode 100644 index aa5f5f3..0000000 --- a/configs/4.x-cfgs/TeslaC2050/gpgpusim.config +++ /dev/null @@ -1,133 +0,0 @@ -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 20 - -# Using cuobjdump to extract ptx/SASS -#-gpgpu_ptx_use_cuobjdump 1 # use default - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - - -# high level architecture configuration --gpgpu_n_clusters 14 --gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 6 --gpgpu_n_sub_partition_per_mchannel 2 - -# Fermi clock domains -#-gpgpu_clock_domains ::: -# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided -# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 575.0:575.0:575.0:750.0 - -# shader core pipeline config --gpgpu_shader_registers 32768 - -# This implies a maximum of 48 warps/SM --gpgpu_shader_core_pipeline 1536:32 --gpgpu_shader_cta 8 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB --gpgpu_pipeline_widths 2,0,1,1,2,0,1,1,2 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 1 --gpgpu_num_dp_units 0 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,2,2,1,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 8,16,8,8,130 - - -# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. --gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,A:32:8,8 --gpgpu_shmem_size 49152 - -# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected -#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:32:8,8 -#-gpgpu_shmem_size 16384 - -# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache --gpgpu_cache:dl2 N:64:128:8,L:B:m:W:L,A:32:4,4:0,32 --gpgpu_cache:dl2_texture_only 0 - --gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2 --gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,A:2:32,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 --gpgpu_num_reg_banks 16 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 - --gpgpu_max_insn_issue_per_warp 1 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 750MHz / 575MHz = 130 --gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 114 - -# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition --gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 4 --gpgpu_dram_burst_length 8 --dram_data_command_freq_ratio 4 # GDDR5 is QDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS - -# GDDR5 timing from hynix H5GQ1H24AFR -# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" - -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 diff --git a/configs/4.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt b/configs/4.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt deleted file mode 100644 index 616e9f3..0000000 --- a/configs/4.x-cfgs/VOLTA_TITANV/config_fermi_islip.icnt +++ /dev/null @@ -1,74 +0,0 @@ -//21*1 fly with 32 flits per packet under gpgpusim injection mode -use_map = 0; -flit_size = 40; - -// currently we do not use this, see subnets below -network_count = 2; - -// Topology -topology = fly; -k = 64; -n = 1; - -// Routing - -routing_function = dest_tag; - - -// Flow control - -num_vcs = 1; -vc_buf_size = 128; -input_buffer_size = 256; -ejection_buffer_size = 128; -boundary_buffer_size = 128; - -wait_for_tail_credit = 0; - -// Router architecture - -vc_allocator = islip; //separable_input_first; -sw_allocator = islip; //separable_input_first; -alloc_iters = 1; - -credit_delay = 0; -routing_delay = 0; -vc_alloc_delay = 1; -sw_alloc_delay = 1; - -input_speedup = 2; -output_speedup = 1; -internal_speedup = 1.0; - -// Traffic, GPGPU-Sim does not use this - -traffic = uniform; -packet_size ={{1,2,3,4},{10,20}}; -packet_size_rate={{1,1,1,1},{2,1}}; - -// Simulation - Don't change - -sim_type = gpgpusim; -//sim_type = latency; -injection_rate = 0.1; - -subnets = 2; - -// Always use read and write no matter following line -//use_read_write = 1; - - -read_request_subnet = 0; -read_reply_subnet = 1; -write_request_subnet = 0; -write_reply_subnet = 1; - -read_request_begin_vc = 0; -read_request_end_vc = 0; -write_request_begin_vc = 0; -write_request_end_vc = 0; -read_reply_begin_vc = 0; -read_reply_end_vc = 0; -write_reply_begin_vc = 0; -write_reply_end_vc = 0; - diff --git a/configs/4.x-cfgs/VOLTA_TITANV/gpgpusim.config b/configs/4.x-cfgs/VOLTA_TITANV/gpgpusim.config deleted file mode 100644 index 8969168..0000000 --- a/configs/4.x-cfgs/VOLTA_TITANV/gpgpusim.config +++ /dev/null @@ -1,186 +0,0 @@ -# This config models the Volta Titan X -# For more info about this card: -# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf -# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) -# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf -# https://devblogs.nvidia.com/inside-volta/ -# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf - -# functional simulator specification --gpgpu_ptx_instruction_classification 0 --gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 70 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# high level architecture configuration --gpgpu_n_clusters 40 --gpgpu_n_cores_per_cluster 2 --gpgpu_n_mem 24 --gpgpu_n_sub_partition_per_mchannel 1 - -# volta clock domains -#-gpgpu_clock_domains ::: -# Pascal NVIDIA GP100 clock domains are adopted from -# https://en.wikipedia.org/wiki/Volta_(microarchitecture) --gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0 -# boost mode -# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0 - -# shader core pipeline config --gpgpu_shader_registers 65536 - -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 --gpgpu_shader_cta 32 --gpgpu_simd_model 1 - -# Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB -## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core -## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 4 --gpgpu_num_dp_units 4 - -# Instruction latencies and initiation intervals -# "ADD,MAX,MUL,MAD,DIV" -# All Div operations are executed on SFU unit -# Throughput (initiation latency) are adopted from -# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 2,2,2,2,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 2,2,2,2,4 --ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 4,4,4,4,130 --ptx_opcode_latency_sfu 100 --ptx_opcode_initiation_sfu 8 - - -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. -# Pascal GP100 has 64KB Shared memory --gpgpu_cache:dl1 S:64:128:8,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefL1 S:64:128:16,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_shmem_size 65536 --gpgpu_shmem_size_PrefL1 1 --gpgpu_shmem_size_PrefShared 98304 --gmem_skip_L1D 0 --icnt_flit_size 40 --gpgpu_n_cluster_ejection_buffer_size 32 - -# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache --gpgpu_cache:dl2 S:64:128:24,L:B:m:F:L,A:256:4,32:0,32 --gpgpu_cache:dl2_texture_only 0 --gpgpu_dram_partition_queues 64:64:64:64 --perf_sim_memcpy 0 - -# 128 KB Inst. --gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 -# 48 KB Tex --gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 -# 64 KB Const --gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 12 --gpgpu_operand_collector_num_units_sfu 6 --gpgpu_operand_collector_num_units_mem 8 --gpgpu_operand_collector_num_units_dp 6 --gpgpu_operand_collector_num_in_ports_sp 4 --gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 --gpgpu_operand_collector_num_in_ports_mem 1 --gpgpu_operand_collector_num_out_ports_mem 1 --gpgpu_operand_collector_num_in_ports_dp 1 --gpgpu_operand_collector_num_out_ports_dp 1 --gpgpu_num_reg_banks 32 - -# shared memory bankconflict detection --gpgpu_shmem_num_banks 32 --gpgpu_shmem_limited_broadcast 0 --gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 60 - -## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units --gpgpu_max_insn_issue_per_warp 1 --gpgpu_dual_issue_diff_exec_units 1 - -# interconnection --network_mode 1 --inter_config_file config_fermi_islip.icnt - -# memory partition latency config --rop_latency 120 --dram_latency 100 - -# dram model config --gpgpu_dram_scheduler 1 -# The DRAM return queue and the scheduler queue together should provide buffer -# to sustain the memory level parallelism to tolerate DRAM latency -# To allow 100% DRAM utility, there should at least be enough buffer to sustain -# the minimum DRAM latency (100 core cycles). I.e. -# Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 64 --gpgpu_dram_return_queue_size 192 - -# for HBM, 32 channles, each (128 bits) 16 bytes width --gpgpu_n_mem_per_ctrlr 1 --gpgpu_dram_buswidth 16 --gpgpu_dram_burst_length 2 --dram_data_command_freq_ratio 2 # HBM is DDR --gpgpu_mem_address_mask 1 --gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS - -# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf) -# Timing for 1 GHZ -# tRRDl and tWTR are missing, need to be added -#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: -# CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" - -# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ --gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34: - CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3" - -# HBM has dual bus interface, in which it can issue two col and row commands at a time --dual_bus_interface 1 -# select lower bits for bnkgrp to increase bnkgrp parallelism --dram_bnk_indexing_policy 0 --dram_bnkgrp_indexing_policy 1 - -#-Seperate_Write_Queue_Enable 1 -#-Write_Queue_Size 64:56:32 - -# Pascal has two schedulers per core --gpgpu_num_sched_per_core 2 -# Two Level Scheduler with active and pending pools -#-gpgpu_scheduler two_level_active:6:0:1 -# Loose round robbin scheduler -#-gpgpu_scheduler lrr -# Greedy then oldest scheduler --gpgpu_scheduler gto - -# stat collection --gpgpu_memlatency_stat 14 --gpgpu_runtime_stat 500 --enable_ptx_file_line_stats 1 --visualizer_enabled 0 - -# power model configs, disable it untill we create a real energy model for Pascal 100 --power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx480.xml - -# tracing functionality -#-trace_enabled 1 -#-trace_components WARP_SCHEDULER,SCOREBOARD -#-trace_sampling_core 0 - -- cgit v1.3 From 9b73d9052abe163f557f025020ab1721a02fb0d5 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 19 May 2018 13:11:06 -0400 Subject: Updating to run the volta config and reflect the new config names --- Jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Jenkinsfile b/Jenkinsfile index aeb0978..16e932e 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -55,7 +55,7 @@ pipeline { }, "9.1-functest": { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft,sdk-4.2 -C TITANX_P102,TITANX_P102-L1ON,P100_HBM -N regress-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B rodinia_2.0-ft,sdk-4.2 -C TITANX,TITANX-L1ON,P100,TITANV -N regress-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/9.1-rodinia" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -v -s stats-$$.csv -N regress-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' @@ -75,7 +75,7 @@ pipeline { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ PLOTDIR="jenkins/${JOB_NAME}" &&\ - ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh TITANX_P102,TITANX_P102-L1ON,P100_HBM $PLOTDIR ${BUILD_NUMBER}' + ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh TITANX,TITANX-L1ON,P100,TITANV $PLOTDIR ${BUILD_NUMBER}' } } } -- cgit v1.3 From 738f04e8c31843855881b2e24ba318dce04be1cd Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sat, 19 May 2018 13:12:39 -0400 Subject: Updating the nightly to use the TITANV as well --- nightly.jenkinsfile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nightly.jenkinsfile b/nightly.jenkinsfile index d16f546..78f3920 100644 --- a/nightly.jenkinsfile +++ b/nightly.jenkinsfile @@ -40,7 +40,7 @@ pipeline { steps { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ - ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list` -C TITANX_P102-2B,TITANX_P102-L1ON-2B,P100_HBM-2B -N nightly-$$ && \ + ./gpgpu-sim_simulations/util/job_launching/run_simulations.py -B `cat ./gpgpu-sim_simulations/util/job_launching/apps/all-apps.list` -C TITANX-2B,TITANX-L1ON-2B,P100-2B,TITANV-2B -N nightly-$$ && \ PLOTDIR="jenkins/${JOB_NAME}/${BUILD_NUMBER}/getstats" && ssh tgrogers@dynamo.ecn.purdue.edu mkdir -p /home/dynamo/a/tgrogers/website/gpgpu-sim-plots/$PLOTDIR && \ ./gpgpu-sim_simulations/util/job_launching/monitor_func_test.py -I -S 1800 -v -s stats-$$.csv -N nightly-$$ && \ ./gpgpu-sim_simulations/util/plotting/plot-get-stats.py -c stats-$$.csv -p tgrogers@dynamo.ecn.purdue.edu:~/website/gpgpu-sim-plots/$PLOTDIR -w https://engineering.purdue.edu/tgrogers/gpgpu-sim-plots/$PLOTDIR -n $PLOTDIR' @@ -51,7 +51,7 @@ pipeline { sh 'source /home/tgrogers-raid/a/common/gpgpu-sim-setup/9.1_env_setup.sh &&\ source `pwd`/setup_environment &&\ PLOTDIR="jenkins/${JOB_NAME}" &&\ - ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh TITANX_P102-2B,TITANX_P102-L1ON-2B,P100_HBM-2B $PLOTDIR ${BUILD_NUMBER}' + ./gpgpu-sim_simulations/util/plotting/correlate_and_publish.sh TITANX-2B,TITANX-L1ON-2B,P100-2B,TITANV-2B $PLOTDIR ${BUILD_NUMBER}' } } } -- cgit v1.3 From 7c57ad4c1186d28ccc7fb7ea45f66007f2903bf2 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 09:49:26 -0700 Subject: revert to before texture bug --- libcuda/cuda_runtime_api.cc | 11 ---- src/abstract_hardware_model.h | 144 ++---------------------------------------- src/cuda-sim/cuda-sim.cc | 7 -- 3 files changed, 4 insertions(+), 158 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 292d43d..ef46f00 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1002,14 +1002,6 @@ __host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureRefere __host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) { - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - printf("GPGPU-Sim PTX: in cudaUnbindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); - printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); - const struct cudaArray* array = gpu->get_texarray(texref); - printf("GPGPU-Sim PTX: texref = %p, array = %p\n", texref, array); - - gpu->gpgpu_ptx_sim_unbindTexture(texref); return g_last_cudaError = cudaSuccess; } @@ -2092,12 +2084,10 @@ void __cudaUnregisterFatBinary(void **fatCubinHandle) cudaError_t cudaDeviceReset ( void ) { // Should reset the simulated GPU - // TODO: Implement return g_last_cudaError = cudaSuccess; } cudaError_t CUDARTAPI cudaDeviceSynchronize(void){ // I don't know what this should do - // TODO: Implement return g_last_cudaError = cudaSuccess; } @@ -2199,7 +2189,6 @@ typedef unsigned long GLuint; cudaError_t cudaGLRegisterBufferObject(GLuint bufferObj) { printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); - // TODO: Implement return g_last_cudaError = cudaSuccess; } diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 6dd5436..f5708bc 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -25,11 +25,6 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -#ifndef VERSION_EIGHT -#define VERSION_EIGHT -#endif - #ifndef ABSTRACT_HARDWARE_MODEL_INCLUDED #define ABSTRACT_HARDWARE_MODEL_INCLUDED @@ -450,34 +445,6 @@ struct textureReference { enum cudaTextureFilterMode filterMode; enum cudaTextureAddressMode addressMode[3]; struct cudaChannelFormatDesc channelDesc; - -//following commented section applies only to CUDA_VERSION 8+ -// /** -// * Perform sRGB->linear conversion during texture read -// */ -// int sRGB; -// /** -// * Limit to the anisotropy ratio -// */ -// unsigned int maxAnisotropy; -// /** -// * Mipmap filter mode -// */ -// enum cudaTextureFilterMode mipmapFilterMode; -// /** -// * Offset applied to the supplied mipmap level -// */ -// float mipmapLevelBias; -// /** -// * Lower end of the mipmap level range to clamp access to -// */ -// float minMipmapLevelClamp; -// /** -// * Upper end of the mipmap level range to clamp access to -// */ -// float maxMipmapLevelClamp; -// int __cudaReserved[15]; - }; #endif @@ -544,7 +511,6 @@ public: class memory_space *get_surf_memory() { return m_surf_mem; } void gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array); - void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); void gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); @@ -556,121 +522,19 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); - if(t != m_TextureRefToCudaArray.end()){ - return t->second; - } else{ - int matches = 0; - const struct cudaArray* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); - kv!= m_TextureRefToCudaArray.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; - } - } - - //assert(matches==1); - return t; - } + assert(t != m_TextureRefToCudaArray.end()); + return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); - if(t != m_TextureRefToTexureInfo.end()){ - return t->second; - }else{ - int matches = 0; - const struct textureInfo* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); - kv!= m_TextureRefToTexureInfo.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; - } - } - //assert(matches==1); - return t; - } + assert(t != m_TextureRefToTexureInfo.end()); + return t->second; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { - //note textureReferenceAttr map behaves differently from cudaArray and - //textureInfo maps std::map::const_iterator t=m_TextureRefToAttribute.find(texref); assert(t != m_TextureRefToAttribute.end()); return t->second; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 6bdf75f..946043a 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -140,7 +140,6 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { - printf("GPGPU-Simm PTX: name from texture = %s\n", gpgpu_ptx_sim_findNamefromTexture(texref)); m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; @@ -184,12 +183,6 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te m_TextureRefToTexureInfo[texref] = texInfo; } -void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) -{ - m_TextureRefToCudaArray.erase(texref); - m_TextureRefToTexureInfo.erase(texref); -} - unsigned g_assemble_code_next_pc=0; std::map g_pc_to_finfo; std::vector function_info::s_g_pc_to_insn; -- cgit v1.3 From 26ab318c443339e14940772c2199e486411d12ed Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 09:56:07 -0700 Subject: unbind implementation --- libcuda/cuda_runtime_api.cc | 11 ++++++++--- src/abstract_hardware_model.h | 1 + src/cuda-sim/cuda-sim.cc | 6 ++++++ src/cuda-sim/instructions.cc | 2 +- 4 files changed, 16 insertions(+), 4 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index ef46f00..fa5a523 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1000,9 +1000,14 @@ __host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureRefere return g_last_cudaError = cudaSuccess; } -__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) -{ - return g_last_cudaError = cudaSuccess; +__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) { + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + printf("GPGPU-Sim PTX: in cudaUnbindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); + printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); + + gpu->gpgpu_ptx_sim_unbindTexture(texref); + return g_last_cudaError = cudaSuccess; } __host__ cudaError_t CUDARTAPI cudaGetTextureAlignmentOffset(size_t *offset, const struct textureReference *texref) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index f5708bc..ab94ded 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -512,6 +512,7 @@ public: void gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array); void gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext); + void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); const struct textureReference* get_texref(const std::string &texname) const diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 946043a..6125422 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -183,6 +183,12 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te m_TextureRefToTexureInfo[texref] = texInfo; } +void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) +{ + m_TextureRefToCudaArray.erase(texref); + m_TextureRefToTexureInfo.erase(texref); +} + unsigned g_assemble_code_next_pc=0; std::map g_pc_to_finfo; std::vector function_info::s_g_pc_to_insn; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 8a3539b..31162b4 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2368,7 +2368,7 @@ void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand space = param_space_kernel; else if( ti.is_param_local() ) space = param_space_local; - else if( ti.is_reg() ) + else if( ti.is_reg() ) space = param_space_kernel; else { printf("GPGPU-Sim PTX: ERROR ** cannot resolve .param space for '%s'\n", s->name().c_str() ); -- cgit v1.3 From 91db4fc3b6a3ef4c4a330736896e498694fc3455 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 14:00:59 -0700 Subject: restructured texref maps to fix texture bug --- src/abstract_hardware_model.h | 36 +++++++++++++++++-------------- src/cuda-sim/cuda-sim.cc | 49 ++++++++++++++++++++++++++++--------------- src/cuda-sim/instructions.cc | 6 +++--- 3 files changed, 55 insertions(+), 36 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index ab94ded..d0af1ea 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -65,6 +65,7 @@ enum FuncCache #include #include +#include typedef unsigned long long new_addr_type; typedef unsigned address_type; @@ -515,29 +516,31 @@ public: void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); - const struct textureReference* get_texref(const std::string &texname) const + const struct textureReference* get_texref( const std::string &texname ) const { - std::map::const_iterator t=m_NameToTextureRef.find(texname); + std::map >::const_iterator t=m_NameToTextureRef.find(texname); assert( t != m_NameToTextureRef.end() ); - return t->second; + return *(t->second.begin()); } - const struct cudaArray* get_texarray( const struct textureReference *texref ) const + + const struct cudaArray* get_texarray( const std::string &texname ) const { - std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); - assert(t != m_TextureRefToCudaArray.end()); + std::map::const_iterator t=m_NameToCudaArray.find(texname); + assert(t != m_NameToCudaArray.end()); return t->second; } - const struct textureInfo* get_texinfo( const struct textureReference *texref ) const + + const struct textureInfo* get_texinfo( const std::string &texname ) const { - std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); - assert(t != m_TextureRefToTexureInfo.end()); + std::map::const_iterator t=m_NameToTexureInfo.find(texname); + assert(t != m_NameToTexureInfo.end()); return t->second; } - const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const + const struct textureReferenceAttr* get_texattr( const std::string &texname ) const { - std::map::const_iterator t=m_TextureRefToAttribute.find(texref); - assert(t != m_TextureRefToAttribute.end()); + std::map::const_iterator t=m_NameToAttribute.find(texname); + assert(t != m_NameToAttribute.end()); return t->second; } @@ -554,10 +557,11 @@ protected: unsigned long long m_dev_malloc; - std::map m_NameToTextureRef; - std::map m_TextureRefToCudaArray; - std::map m_TextureRefToTexureInfo; - std::map m_TextureRefToAttribute; + std::map > m_NameToTextureRef; + std::map m_TextureRefToName; + std::map m_NameToCudaArray; + std::map m_NameToTexureInfo; + std::map m_NameToAttribute; }; struct gpgpu_ptx_sim_info diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 6125422..05b6201 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -105,22 +105,36 @@ static address_type get_converge_point(address_type pc); void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) { std::string texname(name); - m_NameToTextureRef[texname] = texref; + if (m_NameToTextureRef.find(texname)==m_NameToTextureRef.end()){ + m_NameToTextureRef[texname] = std::set(); + m_NameToTextureRef[texname].insert(texref); + }else{ + const struct textureReference* tr = *m_NameToTextureRef[texname].begin(); + assert(tr!=NULL); + //asserts that all texrefs in set have same fields + assert(tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f + ); + m_NameToTextureRef[texname].insert(texref); + } + m_TextureRefToName[texref] = texname; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); - m_TextureRefToAttribute[texref] = texAttr; + m_NameToAttribute[texname] = texAttr; } const char* gpgpu_t::gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref) { - std::map::iterator itr = m_NameToTextureRef.begin(); - while (itr != m_NameToTextureRef.end()) { - if ((*itr).second == texref) { - const char *p = ((*itr).first).c_str(); - return p; - } - itr++; - } - return NULL; + std::map::const_iterator t=m_TextureRefToName.find(texref); + assert( t != m_TextureRefToName.end() ); + return t->second.c_str(); } unsigned int intLOGB2( unsigned int v ) { @@ -140,7 +154,8 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { - m_TextureRefToCudaArray[texref] = array; + std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); + m_NameToCudaArray[texname] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; unsigned int Tx, Ty; @@ -180,13 +195,14 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te texInfo->Ty_numbits = intLOGB2(Ty); texInfo->texel_size = texel_size; texInfo->texel_size_numbits = intLOGB2(texel_size); - m_TextureRefToTexureInfo[texref] = texInfo; + m_NameToTexureInfo[texname] = texInfo; } void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) { - m_TextureRefToCudaArray.erase(texref); - m_TextureRefToTexureInfo.erase(texref); + std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); + m_NameToCudaArray.erase(texname); + m_NameToTexureInfo.erase(texname); } unsigned g_assemble_code_next_pc=0; @@ -1246,8 +1262,7 @@ static unsigned get_tex_datasize( const ptx_instruction *pI, ptx_thread_info *th std::string texname = src1.name(); gpgpu_t *gpu = thread->get_gpu(); - const struct textureReference* texref = gpu->get_texref(texname); - const struct textureInfo* texInfo = gpu->get_texinfo(texref); + const struct textureInfo* texInfo = gpu->get_texinfo(texname); unsigned data_size = texInfo->texel_size; return data_size; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 31162b4..ac9b387 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -4098,9 +4098,9 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread ) gpgpu_t *gpu = thread->get_gpu(); const struct textureReference* texref = gpu->get_texref(texname); - const struct cudaArray* cuArray = gpu->get_texarray(texref); - const struct textureInfo* texInfo = gpu->get_texinfo(texref); - const struct textureReferenceAttr* texAttr = gpu->get_texattr(texref); + const struct cudaArray* cuArray = gpu->get_texarray(texname); + const struct textureInfo* texInfo = gpu->get_texinfo(texname); + const struct textureReferenceAttr* texAttr = gpu->get_texattr(texname); //assume always 2D f32 input //access array with src2 coordinates -- cgit v1.3 From 1d37aee592b621c3113dc878403dfd1ccf547746 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 17:27:28 -0700 Subject: cudaStreamWaitEvent tentative implementation --- libcuda/cuda_runtime_api.cc | 20 ++++++++++++++++++++ src/cuda-sim/cuda-sim.cc | 3 +-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index fa5a523..f597a15 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1168,6 +1168,26 @@ __host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) #endif } +__host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) +{ + +#if (CUDART_VERSION >= 3000) + if( stream == NULL ) + return g_last_cudaError = cudaErrorInvalidResourceHandle; + return g_last_cudaError = stream->empty()?cudaSuccess:cudaErrorNotReady; +#else + printf("GPGPU-Sim API: cudaStreamWaitEvent ** waiting for event\n"); + fflush(stdout); + CUevent_st *e = (CUevent_st*) event; + while( !e->done() ) + ; + printf("GPGPU-Sim API: cudaStreamWaitEvent ** event detected\n"); + fflush(stdout); + printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); + return g_last_cudaError = cudaSuccess; // it is always success because all cuda calls are synchronous +#endif +} + /******************************************************************************* * * * * diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 05b6201..0e14dd0 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -107,7 +107,6 @@ void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct tex std::string texname(name); if (m_NameToTextureRef.find(texname)==m_NameToTextureRef.end()){ m_NameToTextureRef[texname] = std::set(); - m_NameToTextureRef[texname].insert(texref); }else{ const struct textureReference* tr = *m_NameToTextureRef[texname].begin(); assert(tr!=NULL); @@ -123,8 +122,8 @@ void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct tex tr->channelDesc.w==texref->channelDesc.w&& tr->channelDesc.f==texref->channelDesc.f ); - m_NameToTextureRef[texname].insert(texref); } + m_NameToTextureRef[texname].insert(texref); m_TextureRefToName[texref] = texname; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); m_NameToAttribute[texname] = texAttr; -- cgit v1.3 From 7dc5e8fba40a30d7e5d7299646332482136a477b Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 22:31:13 -0700 Subject: gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 428abce..0e2a898 100644 --- a/.gitignore +++ b/.gitignore @@ -32,4 +32,5 @@ build/* *~ cscope* tags +regression.sh -- cgit v1.3 From 835b78988ce1797e394cb1b169db83e7d0fc1038 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Wed, 23 May 2018 10:04:11 -0700 Subject: assertions and comments that allow the current unbind implementation to behave correctly --- src/cuda-sim/cuda-sim.cc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 0e14dd0..2a197c3 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -154,6 +154,10 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); + + std::map::const_iterator t=m_NameToCudaArray.find(texname); + //check that there's nothing there first + assert(t == m_NameToCudaArray.end()); m_NameToCudaArray[texname] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; @@ -199,6 +203,7 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) { + //assumes bind-use-unbind-bind-use-unbind pattern std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); m_NameToCudaArray.erase(texname); m_NameToTexureInfo.erase(texname); -- cgit v1.3 From 9636bbfef261c732c990b7159c9ad699888f5553 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Wed, 23 May 2018 11:14:42 -0700 Subject: unimplement cudaStreaWaitEvent because I don't know what I'm doing --- libcuda/cuda_runtime_api.cc | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index f597a15..e61ed0b 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1170,22 +1170,8 @@ __host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) __host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) { - -#if (CUDART_VERSION >= 3000) - if( stream == NULL ) - return g_last_cudaError = cudaErrorInvalidResourceHandle; - return g_last_cudaError = stream->empty()?cudaSuccess:cudaErrorNotReady; -#else - printf("GPGPU-Sim API: cudaStreamWaitEvent ** waiting for event\n"); - fflush(stdout); - CUevent_st *e = (CUevent_st*) event; - while( !e->done() ) - ; - printf("GPGPU-Sim API: cudaStreamWaitEvent ** event detected\n"); - fflush(stdout); - printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); - return g_last_cudaError = cudaSuccess; // it is always success because all cuda calls are synchronous -#endif + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; } /******************************************************************************* -- cgit v1.3 From 64e80dd0c771dce517973ec0a27eb01238f4d8e6 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 24 May 2018 15:35:05 -0700 Subject: changed assertion to warning when binding to previously bound name. --- src/cuda-sim/cuda-sim.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 2a197c3..34368ce 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -157,7 +157,9 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te std::map::const_iterator t=m_NameToCudaArray.find(texname); //check that there's nothing there first - assert(t == m_NameToCudaArray.end()); + if(t != m_NameToCudaArray.end()){ + printf("GPGPU-Sim PTX: Warning: binding to texref associated with %s, which was previously bound.\nImplicitly unbinding texref associated to %s first\n", texname.c_str(), texname.c_str()); + } m_NameToCudaArray[texname] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; -- cgit v1.3 From a9f90b837af13e205886c19696f779e15e2499b0 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Wed, 16 May 2018 13:36:15 -0700 Subject: is_reg change --- .gitignore | 4 ++++ src/cuda-sim/instructions.cc | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 887b605..428abce 100644 --- a/.gitignore +++ b/.gitignore @@ -29,3 +29,7 @@ cuobjdump_to_ptxplus/sass_parser.output build/* *.swp +*~ +cscope* +tags + diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 583a49a..86951ed 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2366,7 +2366,7 @@ void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand type_info_key ti = t->get_key(); if( ti.is_param_kernel() ) space = param_space_kernel; - else if( ti.is_param_local() ) { + else if( ti.is_param_local() ) space = param_space_local; } else if( ti.is_reg() ) { -- cgit v1.3 From 4fb2d23f350bd8921417f5c09bde73594e5c8a0b Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 09:27:07 -0700 Subject: allows gpgpusim to select a set of texture array,attr,info but maybe not the right one --- src/abstract_hardware_model.h | 73 +++++++++++++++++++++++++++++++++++++------ src/cuda-sim/cuda-sim.cc | 30 ++++++++++++++++++ 2 files changed, 94 insertions(+), 9 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index f5708bc..ca41e68 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -522,22 +522,77 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); - assert(t != m_TextureRefToCudaArray.end()); - return t->second; + + for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); kv!= m_TextureRefToCudaArray.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f){ + + return kv->second; + } + } + + assert(false); +// std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); +// assert(t != m_TextureRefToCudaArray.end()); +// return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); - assert(t != m_TextureRefToTexureInfo.end()); - return t->second; + for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); kv!= m_TextureRefToTexureInfo.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f){ + + return kv->second; + } + } + + assert(false); +// std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); +// assert(t != m_TextureRefToTexureInfo.end()); +// return t->second; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToAttribute.find(texref); - assert(t != m_TextureRefToAttribute.end()); - return t->second; + for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f){ + + return kv->second; + } + } + + assert(false); +// std::map::const_iterator t=m_TextureRefToAttribute.find(texref); +// assert(t != m_TextureRefToAttribute.end()); +// return t->second; } const gpgpu_functional_sim_config &get_config() const { return m_function_model_config; } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 946043a..6e04ca8 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -140,6 +140,36 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { + // counts number of matches +// int normalized; +// enum cudaTextureFilterMode filterMode; +// enum cudaTextureAddressMode addressMode[3]; +// struct cudaChannelFormatDesc channelDesc; +// int x; +// int y; +// int z; +// int w; +// enum cudaChannelFormatKind f; +// int trMatches = 0; +// for (auto& kv : m_NameToTextureRef){ +// const struct textureReference* tr = kv.second; +// if (tr->normalized==texref->normalized&& +// tr->filterMode==texref->filterMode&& +// tr->addressMode[0]==texref->addressMode[0]&& +// tr->addressMode[1]==texref->addressMode[1]&& +// tr->addressMode[2]==texref->addressMode[2]&& +// tr->channelDesc.x==texref->channelDesc.x&& +// tr->channelDesc.y==texref->channelDesc.y&& +// tr->channelDesc.z==texref->channelDesc.z&& +// tr->channelDesc.w==texref->channelDesc.w&& +// tr->channelDesc.f==texref->channelDesc.f){ +// +// m_TextureRefToCudaArray[tr] = array; +// trMatches++; +// } +// } +// printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); +// assert(trMatches==1); m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; -- cgit v1.3 From d36216db7a9d1d2360acf00afb5303b1f76fb7c7 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 16:24:41 -0700 Subject: counting matches with same texref contents, added cuda8 fields to texref struct --- src/abstract_hardware_model.h | 143 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 130 insertions(+), 13 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index ca41e68..c21ff6d 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -25,6 +25,11 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +#ifndef VERSION_EIGHT +#define VERSION_EIGHT +#endif + #ifndef ABSTRACT_HARDWARE_MODEL_INCLUDED #define ABSTRACT_HARDWARE_MODEL_INCLUDED @@ -445,6 +450,35 @@ struct textureReference { enum cudaTextureFilterMode filterMode; enum cudaTextureAddressMode addressMode[3]; struct cudaChannelFormatDesc channelDesc; + +#ifdef VERSION_EIGHT + /** + * Perform sRGB->linear conversion during texture read + */ + int sRGB; + /** + * Limit to the anisotropy ratio + */ + unsigned int maxAnisotropy; + /** + * Mipmap filter mode + */ + enum cudaTextureFilterMode mipmapFilterMode; + /** + * Offset applied to the supplied mipmap level + */ + float mipmapLevelBias; + /** + * Lower end of the mipmap level range to clamp access to + */ + float minMipmapLevelClamp; + /** + * Upper end of the mipmap level range to clamp access to + */ + float maxMipmapLevelClamp; + int __cudaReserved[15]; +#endif + }; #endif @@ -522,7 +556,8 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - + int matches = 0; + const struct cudaArray* t = NULL; for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); kv!= m_TextureRefToCudaArray.end(); kv ++){ const struct textureReference* tr = kv->first; if (tr->normalized==texref->normalized&& @@ -534,19 +569,49 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f){ - - return kv->second; + tr->channelDesc.f==texref->channelDesc.f && + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14] + ){ + matches++; + t = kv->second; + //return kv->second; } } - assert(false); + printf("matches (texarray) = %d\n", matches); + //assert(matches==1); + return t; + + //assert(false); + // std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); // assert(t != m_TextureRefToCudaArray.end()); // return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { + int matches = 0; + const struct textureInfo* t = NULL; for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); kv!= m_TextureRefToTexureInfo.end(); kv ++){ const struct textureReference* tr = kv->first; if (tr->normalized==texref->normalized&& @@ -558,13 +623,38 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f){ - - return kv->second; + tr->channelDesc.f==texref->channelDesc.f&& + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14]){ + matches++; + t = kv->second; + //return kv->second; } } - assert(false); + printf("matches (texinfo) = %d\n", matches); + //assert(matches==1); + return t; + // std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); // assert(t != m_TextureRefToTexureInfo.end()); // return t->second; @@ -572,6 +662,8 @@ public: const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { + int matches = 0; + const struct textureReferenceAttr* t = NULL; for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ const struct textureReference* tr = kv->first; if (tr->normalized==texref->normalized&& @@ -583,13 +675,38 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f){ - - return kv->second; + tr->channelDesc.f==texref->channelDesc.f&& + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14]){ + matches++; + t = kv->second; + //return kv->second; } } - assert(false); + printf("matches (texattr) = %d\n", matches); + //assert(matches==1); + return t; + // std::map::const_iterator t=m_TextureRefToAttribute.find(texref); // assert(t != m_TextureRefToAttribute.end()); // return t->second; -- cgit v1.3 From d75898c2bf867ac6ea45594f3da9f18525f2ad6f Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 16:26:55 -0700 Subject: abstract_hardware_model.h:texrefAttr is different and can be searched via pointer cuda-sim.cc: counts matches between cudaBinTextureToArray texref param (pointer) to texref pointers in m_NameToTextureRef --- src/abstract_hardware_model.h | 94 +++++++++++++++++++++---------------------- src/cuda-sim/cuda-sim.cc | 47 +++++++++++++++++----- 2 files changed, 84 insertions(+), 57 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index c21ff6d..608a7e2 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -662,54 +662,54 @@ public: const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { - int matches = 0; - const struct textureReferenceAttr* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f&& - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14]){ - matches++; - t = kv->second; - //return kv->second; - } - } - - printf("matches (texattr) = %d\n", matches); - //assert(matches==1); - return t; +// int matches = 0; +// const struct textureReferenceAttr* t = NULL; +// for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ +// const struct textureReference* tr = kv->first; +// if (tr->normalized==texref->normalized&& +// tr->filterMode==texref->filterMode&& +// tr->addressMode[0]==texref->addressMode[0]&& +// tr->addressMode[1]==texref->addressMode[1]&& +// tr->addressMode[2]==texref->addressMode[2]&& +// tr->channelDesc.x==texref->channelDesc.x&& +// tr->channelDesc.y==texref->channelDesc.y&& +// tr->channelDesc.z==texref->channelDesc.z&& +// tr->channelDesc.w==texref->channelDesc.w&& +// tr->channelDesc.f==texref->channelDesc.f&& +// tr->sRGB==texref->sRGB&& +// tr->maxAnisotropy==texref->maxAnisotropy&& +// tr->mipmapFilterMode==texref->mipmapFilterMode&& +// tr->mipmapLevelBias==texref->mipmapLevelBias&& +// tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& +// tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& +// tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& +// tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& +// tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& +// tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& +// tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& +// tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& +// tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& +// tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& +// tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& +// tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& +// tr->__cudaReserved[10]==texref->__cudaReserved[10]&& +// tr->__cudaReserved[11]==texref->__cudaReserved[11]&& +// tr->__cudaReserved[12]==texref->__cudaReserved[12]&& +// tr->__cudaReserved[13]==texref->__cudaReserved[13]&& +// tr->__cudaReserved[14]==texref->__cudaReserved[14]){ +// matches++; +// t = kv->second; +// //return kv->second; +// } +// } +// +// printf("matches (texattr) = %d\n", matches); +// //assert(matches==1); +// return t; -// std::map::const_iterator t=m_TextureRefToAttribute.find(texref); -// assert(t != m_TextureRefToAttribute.end()); -// return t->second; + std::map::const_iterator t=m_TextureRefToAttribute.find(texref); + assert(t != m_TextureRefToAttribute.end()); + return t->second; } const gpgpu_functional_sim_config &get_config() const { return m_function_model_config; } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 6e04ca8..39ffa63 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -26,6 +26,10 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +#ifndef VERSION_EIGHT +#define VERSION_EIGHT +#endif + #include "cuda-sim.h" #include "instructions.h" @@ -104,6 +108,16 @@ static address_type get_converge_point(address_type pc); void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) { + +//#ifdef VERSION_EIGHT +// int i; +// printf("%s ", name); +// printf("__cudaReserved:"); +// for (i = 0; i<15; i++){ +// printf(" %i", texref->__cudaReserved[i]); +// } +// printf("\n"); +//#endif std::string texname(name); m_NameToTextureRef[texname] = texref; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); @@ -140,16 +154,15 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { +//#ifdef VERSION_EIGHT +// int i; +// printf("__cudaReserved:"); +// for (i = 0; i<15; i++){ +// printf(" %i", texref->__cudaReserved[i]); +// } +// printf("\n"); +//#endif // counts number of matches -// int normalized; -// enum cudaTextureFilterMode filterMode; -// enum cudaTextureAddressMode addressMode[3]; -// struct cudaChannelFormatDesc channelDesc; -// int x; -// int y; -// int z; -// int w; -// enum cudaChannelFormatKind f; // int trMatches = 0; // for (auto& kv : m_NameToTextureRef){ // const struct textureReference* tr = kv.second; @@ -170,7 +183,21 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te // } // printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); // assert(trMatches==1); - m_TextureRefToCudaArray[texref] = array; + + //tests if texref pointer matches any pointer in m_NameToTextureRef map + int trMatches = 0; + for (auto& kv : m_NameToTextureRef){ + const struct textureReference* tr = kv.second; + if (tr==texref){ + m_TextureRefToCudaArray[tr] = array; + //printf("%s\n", kv.first); + trMatches++; + } + } + printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); + //assert(trMatches==1); + + //m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; unsigned int Tx, Ty; -- cgit v1.3 From c875860b1a79d3dc828275b6129c92f154b516e1 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 17 May 2018 16:49:55 -0700 Subject: changed for loop, pass pipeline? --- 0517_13-24cudaReserved.log | 0 517-1418cudaReserved.log | 0 src/cuda-sim/cuda-sim.cc | 6 +++--- 3 files changed, 3 insertions(+), 3 deletions(-) create mode 100644 0517_13-24cudaReserved.log create mode 100644 517-1418cudaReserved.log diff --git a/0517_13-24cudaReserved.log b/0517_13-24cudaReserved.log new file mode 100644 index 0000000..e69de29 diff --git a/517-1418cudaReserved.log b/517-1418cudaReserved.log new file mode 100644 index 0000000..e69de29 diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 39ffa63..656091c 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -186,11 +186,11 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te //tests if texref pointer matches any pointer in m_NameToTextureRef map int trMatches = 0; - for (auto& kv : m_NameToTextureRef){ - const struct textureReference* tr = kv.second; + for (std::map::const_iterator kv = m_NameToTextureRef.begin(); kv!= m_NameToTextureRef.end(); kv ++){ + const struct textureReference* tr = kv->second; if (tr==texref){ m_TextureRefToCudaArray[tr] = array; - //printf("%s\n", kv.first); + printf("%s\n", kv->first.c_str()); trMatches++; } } -- cgit v1.3 From 3b4c3898771ac5e774bca9445a5a4a81670b7b17 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 18 May 2018 10:50:19 -0700 Subject: reverted cuda8 changes (extra fields) and assert texture bug fix's assumption --- src/abstract_hardware_model.h | 134 ++++++++++++++---------------------------- src/cuda-sim/cuda-sim.cc | 59 +------------------ 2 files changed, 45 insertions(+), 148 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 608a7e2..412c0a8 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -451,33 +451,32 @@ struct textureReference { enum cudaTextureAddressMode addressMode[3]; struct cudaChannelFormatDesc channelDesc; -#ifdef VERSION_EIGHT - /** - * Perform sRGB->linear conversion during texture read - */ - int sRGB; - /** - * Limit to the anisotropy ratio - */ - unsigned int maxAnisotropy; - /** - * Mipmap filter mode - */ - enum cudaTextureFilterMode mipmapFilterMode; - /** - * Offset applied to the supplied mipmap level - */ - float mipmapLevelBias; - /** - * Lower end of the mipmap level range to clamp access to - */ - float minMipmapLevelClamp; - /** - * Upper end of the mipmap level range to clamp access to - */ - float maxMipmapLevelClamp; - int __cudaReserved[15]; -#endif +//following commented section applies only to CUDA_VERSION 8+ +// /** +// * Perform sRGB->linear conversion during texture read +// */ +// int sRGB; +// /** +// * Limit to the anisotropy ratio +// */ +// unsigned int maxAnisotropy; +// /** +// * Mipmap filter mode +// */ +// enum cudaTextureFilterMode mipmapFilterMode; +// /** +// * Offset applied to the supplied mipmap level +// */ +// float mipmapLevelBias; +// /** +// * Lower end of the mipmap level range to clamp access to +// */ +// float minMipmapLevelClamp; +// /** +// * Upper end of the mipmap level range to clamp access to +// */ +// float maxMipmapLevelClamp; +// int __cudaReserved[15]; }; @@ -569,7 +568,10 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f && + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && tr->sRGB==texref->sRGB&& tr->maxAnisotropy==texref->maxAnisotropy&& tr->mipmapFilterMode==texref->mipmapFilterMode&& @@ -591,6 +593,7 @@ public: tr->__cudaReserved[12]==texref->__cudaReserved[12]&& tr->__cudaReserved[13]==texref->__cudaReserved[13]&& tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ ){ matches++; t = kv->second; @@ -598,15 +601,9 @@ public: } } - printf("matches (texarray) = %d\n", matches); - //assert(matches==1); + //printf("matches (texarray) = %d\n", matches); + assert(matches==1); return t; - - //assert(false); - -// std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); -// assert(t != m_TextureRefToCudaArray.end()); -// return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { @@ -623,7 +620,10 @@ public: tr->channelDesc.y==texref->channelDesc.y&& tr->channelDesc.z==texref->channelDesc.z&& tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f&& + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && tr->sRGB==texref->sRGB&& tr->maxAnisotropy==texref->maxAnisotropy&& tr->mipmapFilterMode==texref->mipmapFilterMode&& @@ -644,69 +644,23 @@ public: tr->__cudaReserved[11]==texref->__cudaReserved[11]&& tr->__cudaReserved[12]==texref->__cudaReserved[12]&& tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14]){ + tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ + ){ matches++; t = kv->second; - //return kv->second; } } - printf("matches (texinfo) = %d\n", matches); - //assert(matches==1); + //printf("matches (texinfo) = %d\n", matches); + assert(matches==1); return t; - -// std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); -// assert(t != m_TextureRefToTexureInfo.end()); -// return t->second; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { -// int matches = 0; -// const struct textureReferenceAttr* t = NULL; -// for (std::map::const_iterator kv = m_TextureRefToAttribute.begin(); kv!= m_TextureRefToAttribute.end(); kv ++){ -// const struct textureReference* tr = kv->first; -// if (tr->normalized==texref->normalized&& -// tr->filterMode==texref->filterMode&& -// tr->addressMode[0]==texref->addressMode[0]&& -// tr->addressMode[1]==texref->addressMode[1]&& -// tr->addressMode[2]==texref->addressMode[2]&& -// tr->channelDesc.x==texref->channelDesc.x&& -// tr->channelDesc.y==texref->channelDesc.y&& -// tr->channelDesc.z==texref->channelDesc.z&& -// tr->channelDesc.w==texref->channelDesc.w&& -// tr->channelDesc.f==texref->channelDesc.f&& -// tr->sRGB==texref->sRGB&& -// tr->maxAnisotropy==texref->maxAnisotropy&& -// tr->mipmapFilterMode==texref->mipmapFilterMode&& -// tr->mipmapLevelBias==texref->mipmapLevelBias&& -// tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& -// tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& -// tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& -// tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& -// tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& -// tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& -// tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& -// tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& -// tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& -// tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& -// tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& -// tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& -// tr->__cudaReserved[10]==texref->__cudaReserved[10]&& -// tr->__cudaReserved[11]==texref->__cudaReserved[11]&& -// tr->__cudaReserved[12]==texref->__cudaReserved[12]&& -// tr->__cudaReserved[13]==texref->__cudaReserved[13]&& -// tr->__cudaReserved[14]==texref->__cudaReserved[14]){ -// matches++; -// t = kv->second; -// //return kv->second; -// } -// } -// -// printf("matches (texattr) = %d\n", matches); -// //assert(matches==1); -// return t; - + //note textureReferenceAttr map behaves differently from cudaArray and + //textureInfo maps std::map::const_iterator t=m_TextureRefToAttribute.find(texref); assert(t != m_TextureRefToAttribute.end()); return t->second; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 656091c..946043a 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -26,10 +26,6 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -#ifndef VERSION_EIGHT -#define VERSION_EIGHT -#endif - #include "cuda-sim.h" #include "instructions.h" @@ -108,16 +104,6 @@ static address_type get_converge_point(address_type pc); void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) { - -//#ifdef VERSION_EIGHT -// int i; -// printf("%s ", name); -// printf("__cudaReserved:"); -// for (i = 0; i<15; i++){ -// printf(" %i", texref->__cudaReserved[i]); -// } -// printf("\n"); -//#endif std::string texname(name); m_NameToTextureRef[texname] = texref; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); @@ -154,50 +140,7 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { -//#ifdef VERSION_EIGHT -// int i; -// printf("__cudaReserved:"); -// for (i = 0; i<15; i++){ -// printf(" %i", texref->__cudaReserved[i]); -// } -// printf("\n"); -//#endif - // counts number of matches -// int trMatches = 0; -// for (auto& kv : m_NameToTextureRef){ -// const struct textureReference* tr = kv.second; -// if (tr->normalized==texref->normalized&& -// tr->filterMode==texref->filterMode&& -// tr->addressMode[0]==texref->addressMode[0]&& -// tr->addressMode[1]==texref->addressMode[1]&& -// tr->addressMode[2]==texref->addressMode[2]&& -// tr->channelDesc.x==texref->channelDesc.x&& -// tr->channelDesc.y==texref->channelDesc.y&& -// tr->channelDesc.z==texref->channelDesc.z&& -// tr->channelDesc.w==texref->channelDesc.w&& -// tr->channelDesc.f==texref->channelDesc.f){ -// -// m_TextureRefToCudaArray[tr] = array; -// trMatches++; -// } -// } -// printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); -// assert(trMatches==1); - - //tests if texref pointer matches any pointer in m_NameToTextureRef map - int trMatches = 0; - for (std::map::const_iterator kv = m_NameToTextureRef.begin(); kv!= m_NameToTextureRef.end(); kv ++){ - const struct textureReference* tr = kv->second; - if (tr==texref){ - m_TextureRefToCudaArray[tr] = array; - printf("%s\n", kv->first.c_str()); - trMatches++; - } - } - printf("GPGPU-Sim PTX: matches to texref = %d\n", trMatches); - //assert(trMatches==1); - - //m_TextureRefToCudaArray[texref] = array; + m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; unsigned int Tx, Ty; -- cgit v1.3 From 6a39e5c5964f23a97dafaa6a66f2a9d9c37bbfdd Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 18 May 2018 11:52:31 -0700 Subject: implemented unbind, currently only affects cudaArray map --- 0517_13-24cudaReserved.log | 0 517-1418cudaReserved.log | 0 libcuda/cuda_runtime_api.cc | 11 +++++++++++ src/abstract_hardware_model.h | 1 + src/cuda-sim/cuda-sim.cc | 5 +++++ 5 files changed, 17 insertions(+) delete mode 100644 0517_13-24cudaReserved.log delete mode 100644 517-1418cudaReserved.log diff --git a/0517_13-24cudaReserved.log b/0517_13-24cudaReserved.log deleted file mode 100644 index e69de29..0000000 diff --git a/517-1418cudaReserved.log b/517-1418cudaReserved.log deleted file mode 100644 index e69de29..0000000 diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index e3c2542..71926f8 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -991,6 +991,14 @@ __host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureRefere __host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) { + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + printf("GPGPU-Sim PTX: in cudaUnbindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); + printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); + const struct cudaArray* array = gpu->get_texarray(texref); + printf("GPGPU-Sim PTX: texref = %p, array = %p\n", texref, array); + + gpu->gpgpu_ptx_sim_unbindTexture(texref); return g_last_cudaError = cudaSuccess; } @@ -2073,10 +2081,12 @@ void __cudaUnregisterFatBinary(void **fatCubinHandle) cudaError_t cudaDeviceReset ( void ) { // Should reset the simulated GPU + // TODO: Implement return g_last_cudaError = cudaSuccess; } cudaError_t CUDARTAPI cudaDeviceSynchronize(void){ // I don't know what this should do + // TODO: Implement return g_last_cudaError = cudaSuccess; } @@ -2178,6 +2188,7 @@ typedef unsigned long GLuint; cudaError_t cudaGLRegisterBufferObject(GLuint bufferObj) { printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); + // TODO: Implement return g_last_cudaError = cudaSuccess; } diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 412c0a8..3ef450e 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -544,6 +544,7 @@ public: class memory_space *get_surf_memory() { return m_surf_mem; } void gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array); + void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); void gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 946043a..ef16f43 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -183,6 +183,11 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te m_TextureRefToTexureInfo[texref] = texInfo; } +void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) +{ + m_TextureRefToCudaArray.erase(texref); +} + unsigned g_assemble_code_next_pc=0; std::map g_pc_to_finfo; std::vector function_info::s_g_pc_to_insn; -- cgit v1.3 From a93aa28a94140ee912c0cba0d9414d9da1588d54 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 18 May 2018 14:41:23 -0700 Subject: erase texinfo in unbind and disable assert --- src/abstract_hardware_model.h | 195 ++++++++++++++++++++++-------------------- src/cuda-sim/cuda-sim.cc | 2 + 2 files changed, 104 insertions(+), 93 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 3ef450e..6dd5436 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -556,106 +556,115 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - int matches = 0; - const struct cudaArray* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); kv!= m_TextureRefToCudaArray.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; - //return kv->second; + + std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); + if(t != m_TextureRefToCudaArray.end()){ + return t->second; + } else{ + int matches = 0; + const struct cudaArray* t = NULL; + for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); + kv!= m_TextureRefToCudaArray.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ + ){ + matches++; + t = kv->second; + } } + + //assert(matches==1); + return t; } - - //printf("matches (texarray) = %d\n", matches); - assert(matches==1); - return t; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { - int matches = 0; - const struct textureInfo* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); kv!= m_TextureRefToTexureInfo.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; + std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); + if(t != m_TextureRefToTexureInfo.end()){ + return t->second; + }else{ + int matches = 0; + const struct textureInfo* t = NULL; + for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); + kv!= m_TextureRefToTexureInfo.end(); kv ++){ + const struct textureReference* tr = kv->first; + if (tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f + //following commented section applies only to CUDA_VERSION 8+ + /* + && + tr->sRGB==texref->sRGB&& + tr->maxAnisotropy==texref->maxAnisotropy&& + tr->mipmapFilterMode==texref->mipmapFilterMode&& + tr->mipmapLevelBias==texref->mipmapLevelBias&& + tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& + tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& + tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& + tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& + tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& + tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& + tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& + tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& + tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& + tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& + tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& + tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& + tr->__cudaReserved[10]==texref->__cudaReserved[10]&& + tr->__cudaReserved[11]==texref->__cudaReserved[11]&& + tr->__cudaReserved[12]==texref->__cudaReserved[12]&& + tr->__cudaReserved[13]==texref->__cudaReserved[13]&& + tr->__cudaReserved[14]==texref->__cudaReserved[14] + */ + ){ + matches++; + t = kv->second; + } } + //assert(matches==1); + return t; } - - //printf("matches (texinfo) = %d\n", matches); - assert(matches==1); - return t; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index ef16f43..6bdf75f 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -140,6 +140,7 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { + printf("GPGPU-Simm PTX: name from texture = %s\n", gpgpu_ptx_sim_findNamefromTexture(texref)); m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; @@ -186,6 +187,7 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) { m_TextureRefToCudaArray.erase(texref); + m_TextureRefToTexureInfo.erase(texref); } unsigned g_assemble_code_next_pc=0; -- cgit v1.3 From 958e430266cb3de73033a7e0aab6e7c697fdc6bc Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 09:49:26 -0700 Subject: revert to before texture bug --- libcuda/cuda_runtime_api.cc | 11 ---- src/abstract_hardware_model.h | 144 ++---------------------------------------- src/cuda-sim/cuda-sim.cc | 7 -- 3 files changed, 4 insertions(+), 158 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 71926f8..e3c2542 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -991,14 +991,6 @@ __host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureRefere __host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) { - CUctx_st *context = GPGPUSim_Context(); - gpgpu_t *gpu = context->get_device()->get_gpgpu(); - printf("GPGPU-Sim PTX: in cudaUnbindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); - printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); - const struct cudaArray* array = gpu->get_texarray(texref); - printf("GPGPU-Sim PTX: texref = %p, array = %p\n", texref, array); - - gpu->gpgpu_ptx_sim_unbindTexture(texref); return g_last_cudaError = cudaSuccess; } @@ -2081,12 +2073,10 @@ void __cudaUnregisterFatBinary(void **fatCubinHandle) cudaError_t cudaDeviceReset ( void ) { // Should reset the simulated GPU - // TODO: Implement return g_last_cudaError = cudaSuccess; } cudaError_t CUDARTAPI cudaDeviceSynchronize(void){ // I don't know what this should do - // TODO: Implement return g_last_cudaError = cudaSuccess; } @@ -2188,7 +2178,6 @@ typedef unsigned long GLuint; cudaError_t cudaGLRegisterBufferObject(GLuint bufferObj) { printf("GPGPU-Sim PTX: Execution warning: ignoring call to \"%s\"\n", __my_func__ ); - // TODO: Implement return g_last_cudaError = cudaSuccess; } diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 6dd5436..f5708bc 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -25,11 +25,6 @@ // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -#ifndef VERSION_EIGHT -#define VERSION_EIGHT -#endif - #ifndef ABSTRACT_HARDWARE_MODEL_INCLUDED #define ABSTRACT_HARDWARE_MODEL_INCLUDED @@ -450,34 +445,6 @@ struct textureReference { enum cudaTextureFilterMode filterMode; enum cudaTextureAddressMode addressMode[3]; struct cudaChannelFormatDesc channelDesc; - -//following commented section applies only to CUDA_VERSION 8+ -// /** -// * Perform sRGB->linear conversion during texture read -// */ -// int sRGB; -// /** -// * Limit to the anisotropy ratio -// */ -// unsigned int maxAnisotropy; -// /** -// * Mipmap filter mode -// */ -// enum cudaTextureFilterMode mipmapFilterMode; -// /** -// * Offset applied to the supplied mipmap level -// */ -// float mipmapLevelBias; -// /** -// * Lower end of the mipmap level range to clamp access to -// */ -// float minMipmapLevelClamp; -// /** -// * Upper end of the mipmap level range to clamp access to -// */ -// float maxMipmapLevelClamp; -// int __cudaReserved[15]; - }; #endif @@ -544,7 +511,6 @@ public: class memory_space *get_surf_memory() { return m_surf_mem; } void gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array); - void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); void gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); @@ -556,121 +522,19 @@ public: } const struct cudaArray* get_texarray( const struct textureReference *texref ) const { - std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); - if(t != m_TextureRefToCudaArray.end()){ - return t->second; - } else{ - int matches = 0; - const struct cudaArray* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToCudaArray.begin(); - kv!= m_TextureRefToCudaArray.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; - } - } - - //assert(matches==1); - return t; - } + assert(t != m_TextureRefToCudaArray.end()); + return t->second; } const struct textureInfo* get_texinfo( const struct textureReference *texref ) const { std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); - if(t != m_TextureRefToTexureInfo.end()){ - return t->second; - }else{ - int matches = 0; - const struct textureInfo* t = NULL; - for (std::map::const_iterator kv = m_TextureRefToTexureInfo.begin(); - kv!= m_TextureRefToTexureInfo.end(); kv ++){ - const struct textureReference* tr = kv->first; - if (tr->normalized==texref->normalized&& - tr->filterMode==texref->filterMode&& - tr->addressMode[0]==texref->addressMode[0]&& - tr->addressMode[1]==texref->addressMode[1]&& - tr->addressMode[2]==texref->addressMode[2]&& - tr->channelDesc.x==texref->channelDesc.x&& - tr->channelDesc.y==texref->channelDesc.y&& - tr->channelDesc.z==texref->channelDesc.z&& - tr->channelDesc.w==texref->channelDesc.w&& - tr->channelDesc.f==texref->channelDesc.f - //following commented section applies only to CUDA_VERSION 8+ - /* - && - tr->sRGB==texref->sRGB&& - tr->maxAnisotropy==texref->maxAnisotropy&& - tr->mipmapFilterMode==texref->mipmapFilterMode&& - tr->mipmapLevelBias==texref->mipmapLevelBias&& - tr->minMipmapLevelClamp==texref->minMipmapLevelClamp&& - tr->maxMipmapLevelClamp==texref->maxMipmapLevelClamp&& - tr->__cudaReserved[0] ==texref->__cudaReserved[0]&& - tr->__cudaReserved[1] ==texref->__cudaReserved[1]&& - tr->__cudaReserved[2] ==texref->__cudaReserved[2]&& - tr->__cudaReserved[3] ==texref->__cudaReserved[3]&& - tr->__cudaReserved[4] ==texref->__cudaReserved[4]&& - tr->__cudaReserved[5] ==texref->__cudaReserved[5]&& - tr->__cudaReserved[6] ==texref->__cudaReserved[6]&& - tr->__cudaReserved[7] ==texref->__cudaReserved[7]&& - tr->__cudaReserved[8] ==texref->__cudaReserved[8]&& - tr->__cudaReserved[9] ==texref->__cudaReserved[9]&& - tr->__cudaReserved[10]==texref->__cudaReserved[10]&& - tr->__cudaReserved[11]==texref->__cudaReserved[11]&& - tr->__cudaReserved[12]==texref->__cudaReserved[12]&& - tr->__cudaReserved[13]==texref->__cudaReserved[13]&& - tr->__cudaReserved[14]==texref->__cudaReserved[14] - */ - ){ - matches++; - t = kv->second; - } - } - //assert(matches==1); - return t; - } + assert(t != m_TextureRefToTexureInfo.end()); + return t->second; } const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const { - //note textureReferenceAttr map behaves differently from cudaArray and - //textureInfo maps std::map::const_iterator t=m_TextureRefToAttribute.find(texref); assert(t != m_TextureRefToAttribute.end()); return t->second; diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 6bdf75f..946043a 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -140,7 +140,6 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { - printf("GPGPU-Simm PTX: name from texture = %s\n", gpgpu_ptx_sim_findNamefromTexture(texref)); m_TextureRefToCudaArray[texref] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; @@ -184,12 +183,6 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te m_TextureRefToTexureInfo[texref] = texInfo; } -void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) -{ - m_TextureRefToCudaArray.erase(texref); - m_TextureRefToTexureInfo.erase(texref); -} - unsigned g_assemble_code_next_pc=0; std::map g_pc_to_finfo; std::vector function_info::s_g_pc_to_insn; -- cgit v1.3 From 4a567a94aca58fdd2298b50ae9e9da3a889e2173 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 09:56:07 -0700 Subject: unbind implementation --- libcuda/cuda_runtime_api.cc | 11 ++++++++--- src/abstract_hardware_model.h | 1 + src/cuda-sim/cuda-sim.cc | 6 ++++++ 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index e3c2542..d971222 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -989,9 +989,14 @@ __host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureRefere return g_last_cudaError = cudaSuccess; } -__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) -{ - return g_last_cudaError = cudaSuccess; +__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) { + CUctx_st *context = GPGPUSim_Context(); + gpgpu_t *gpu = context->get_device()->get_gpgpu(); + printf("GPGPU-Sim PTX: in cudaUnbindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); + printf("GPGPU-Sim PTX: Name corresponding to textureReference: %s\n", gpu->gpgpu_ptx_sim_findNamefromTexture(texref)); + + gpu->gpgpu_ptx_sim_unbindTexture(texref); + return g_last_cudaError = cudaSuccess; } __host__ cudaError_t CUDARTAPI cudaGetTextureAlignmentOffset(size_t *offset, const struct textureReference *texref) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index f5708bc..ab94ded 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -512,6 +512,7 @@ public: void gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array); void gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext); + void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); const struct textureReference* get_texref(const std::string &texname) const diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 946043a..6125422 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -183,6 +183,12 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te m_TextureRefToTexureInfo[texref] = texInfo; } +void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) +{ + m_TextureRefToCudaArray.erase(texref); + m_TextureRefToTexureInfo.erase(texref); +} + unsigned g_assemble_code_next_pc=0; std::map g_pc_to_finfo; std::vector function_info::s_g_pc_to_insn; -- cgit v1.3 From ff958f36689c9c217eb099326ceb8f70ed3ac447 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 14:00:59 -0700 Subject: restructured texref maps to fix texture bug --- src/abstract_hardware_model.h | 36 +++++++++++++++++-------------- src/cuda-sim/cuda-sim.cc | 49 ++++++++++++++++++++++++++++--------------- src/cuda-sim/instructions.cc | 6 +++--- 3 files changed, 55 insertions(+), 36 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index ab94ded..d0af1ea 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -65,6 +65,7 @@ enum FuncCache #include #include +#include typedef unsigned long long new_addr_type; typedef unsigned address_type; @@ -515,29 +516,31 @@ public: void gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref); const char* gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref); - const struct textureReference* get_texref(const std::string &texname) const + const struct textureReference* get_texref( const std::string &texname ) const { - std::map::const_iterator t=m_NameToTextureRef.find(texname); + std::map >::const_iterator t=m_NameToTextureRef.find(texname); assert( t != m_NameToTextureRef.end() ); - return t->second; + return *(t->second.begin()); } - const struct cudaArray* get_texarray( const struct textureReference *texref ) const + + const struct cudaArray* get_texarray( const std::string &texname ) const { - std::map::const_iterator t=m_TextureRefToCudaArray.find(texref); - assert(t != m_TextureRefToCudaArray.end()); + std::map::const_iterator t=m_NameToCudaArray.find(texname); + assert(t != m_NameToCudaArray.end()); return t->second; } - const struct textureInfo* get_texinfo( const struct textureReference *texref ) const + + const struct textureInfo* get_texinfo( const std::string &texname ) const { - std::map::const_iterator t=m_TextureRefToTexureInfo.find(texref); - assert(t != m_TextureRefToTexureInfo.end()); + std::map::const_iterator t=m_NameToTexureInfo.find(texname); + assert(t != m_NameToTexureInfo.end()); return t->second; } - const struct textureReferenceAttr* get_texattr( const struct textureReference *texref ) const + const struct textureReferenceAttr* get_texattr( const std::string &texname ) const { - std::map::const_iterator t=m_TextureRefToAttribute.find(texref); - assert(t != m_TextureRefToAttribute.end()); + std::map::const_iterator t=m_NameToAttribute.find(texname); + assert(t != m_NameToAttribute.end()); return t->second; } @@ -554,10 +557,11 @@ protected: unsigned long long m_dev_malloc; - std::map m_NameToTextureRef; - std::map m_TextureRefToCudaArray; - std::map m_TextureRefToTexureInfo; - std::map m_TextureRefToAttribute; + std::map > m_NameToTextureRef; + std::map m_TextureRefToName; + std::map m_NameToCudaArray; + std::map m_NameToTexureInfo; + std::map m_NameToAttribute; }; struct gpgpu_ptx_sim_info diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 6125422..05b6201 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -105,22 +105,36 @@ static address_type get_converge_point(address_type pc); void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext) { std::string texname(name); - m_NameToTextureRef[texname] = texref; + if (m_NameToTextureRef.find(texname)==m_NameToTextureRef.end()){ + m_NameToTextureRef[texname] = std::set(); + m_NameToTextureRef[texname].insert(texref); + }else{ + const struct textureReference* tr = *m_NameToTextureRef[texname].begin(); + assert(tr!=NULL); + //asserts that all texrefs in set have same fields + assert(tr->normalized==texref->normalized&& + tr->filterMode==texref->filterMode&& + tr->addressMode[0]==texref->addressMode[0]&& + tr->addressMode[1]==texref->addressMode[1]&& + tr->addressMode[2]==texref->addressMode[2]&& + tr->channelDesc.x==texref->channelDesc.x&& + tr->channelDesc.y==texref->channelDesc.y&& + tr->channelDesc.z==texref->channelDesc.z&& + tr->channelDesc.w==texref->channelDesc.w&& + tr->channelDesc.f==texref->channelDesc.f + ); + m_NameToTextureRef[texname].insert(texref); + } + m_TextureRefToName[texref] = texname; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); - m_TextureRefToAttribute[texref] = texAttr; + m_NameToAttribute[texname] = texAttr; } const char* gpgpu_t::gpgpu_ptx_sim_findNamefromTexture(const struct textureReference* texref) { - std::map::iterator itr = m_NameToTextureRef.begin(); - while (itr != m_NameToTextureRef.end()) { - if ((*itr).second == texref) { - const char *p = ((*itr).first).c_str(); - return p; - } - itr++; - } - return NULL; + std::map::const_iterator t=m_TextureRefToName.find(texref); + assert( t != m_TextureRefToName.end() ); + return t->second.c_str(); } unsigned int intLOGB2( unsigned int v ) { @@ -140,7 +154,8 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { - m_TextureRefToCudaArray[texref] = array; + std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); + m_NameToCudaArray[texname] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; unsigned int Tx, Ty; @@ -180,13 +195,14 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te texInfo->Ty_numbits = intLOGB2(Ty); texInfo->texel_size = texel_size; texInfo->texel_size_numbits = intLOGB2(texel_size); - m_TextureRefToTexureInfo[texref] = texInfo; + m_NameToTexureInfo[texname] = texInfo; } void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) { - m_TextureRefToCudaArray.erase(texref); - m_TextureRefToTexureInfo.erase(texref); + std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); + m_NameToCudaArray.erase(texname); + m_NameToTexureInfo.erase(texname); } unsigned g_assemble_code_next_pc=0; @@ -1246,8 +1262,7 @@ static unsigned get_tex_datasize( const ptx_instruction *pI, ptx_thread_info *th std::string texname = src1.name(); gpgpu_t *gpu = thread->get_gpu(); - const struct textureReference* texref = gpu->get_texref(texname); - const struct textureInfo* texInfo = gpu->get_texinfo(texref); + const struct textureInfo* texInfo = gpu->get_texinfo(texname); unsigned data_size = texInfo->texel_size; return data_size; diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 86951ed..d362231 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -4100,9 +4100,9 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread ) gpgpu_t *gpu = thread->get_gpu(); const struct textureReference* texref = gpu->get_texref(texname); - const struct cudaArray* cuArray = gpu->get_texarray(texref); - const struct textureInfo* texInfo = gpu->get_texinfo(texref); - const struct textureReferenceAttr* texAttr = gpu->get_texattr(texref); + const struct cudaArray* cuArray = gpu->get_texarray(texname); + const struct textureInfo* texInfo = gpu->get_texinfo(texname); + const struct textureReferenceAttr* texAttr = gpu->get_texattr(texname); //assume always 2D f32 input //access array with src2 coordinates -- cgit v1.3 From 3fcc3f8fd99b4183be4f5511800049198a9a0116 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 17:27:28 -0700 Subject: cudaStreamWaitEvent tentative implementation --- libcuda/cuda_runtime_api.cc | 20 ++++++++++++++++++++ src/cuda-sim/cuda-sim.cc | 3 +-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index d971222..a45ed61 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1157,6 +1157,26 @@ __host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) #endif } +__host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) +{ + +#if (CUDART_VERSION >= 3000) + if( stream == NULL ) + return g_last_cudaError = cudaErrorInvalidResourceHandle; + return g_last_cudaError = stream->empty()?cudaSuccess:cudaErrorNotReady; +#else + printf("GPGPU-Sim API: cudaStreamWaitEvent ** waiting for event\n"); + fflush(stdout); + CUevent_st *e = (CUevent_st*) event; + while( !e->done() ) + ; + printf("GPGPU-Sim API: cudaStreamWaitEvent ** event detected\n"); + fflush(stdout); + printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); + return g_last_cudaError = cudaSuccess; // it is always success because all cuda calls are synchronous +#endif +} + /******************************************************************************* * * * * diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 05b6201..0e14dd0 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -107,7 +107,6 @@ void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct tex std::string texname(name); if (m_NameToTextureRef.find(texname)==m_NameToTextureRef.end()){ m_NameToTextureRef[texname] = std::set(); - m_NameToTextureRef[texname].insert(texref); }else{ const struct textureReference* tr = *m_NameToTextureRef[texname].begin(); assert(tr!=NULL); @@ -123,8 +122,8 @@ void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct tex tr->channelDesc.w==texref->channelDesc.w&& tr->channelDesc.f==texref->channelDesc.f ); - m_NameToTextureRef[texname].insert(texref); } + m_NameToTextureRef[texname].insert(texref); m_TextureRefToName[texref] = texname; const textureReferenceAttr *texAttr = new textureReferenceAttr(texref, dim, (enum cudaTextureReadMode)readmode, ext); m_NameToAttribute[texname] = texAttr; -- cgit v1.3 From d659ac82a83dc985a441001a7a7b46004d3ad11d Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 22 May 2018 22:31:13 -0700 Subject: gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 428abce..0e2a898 100644 --- a/.gitignore +++ b/.gitignore @@ -32,4 +32,5 @@ build/* *~ cscope* tags +regression.sh -- cgit v1.3 From 11aa36f93b49b384d5620df69ab3ce2a50a84d24 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Wed, 23 May 2018 10:04:11 -0700 Subject: assertions and comments that allow the current unbind implementation to behave correctly --- src/cuda-sim/cuda-sim.cc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 0e14dd0..2a197c3 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -154,6 +154,10 @@ unsigned int intLOGB2( unsigned int v ) { void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* texref, const struct cudaArray* array) { std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); + + std::map::const_iterator t=m_NameToCudaArray.find(texname); + //check that there's nothing there first + assert(t == m_NameToCudaArray.end()); m_NameToCudaArray[texname] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; @@ -199,6 +203,7 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref) { + //assumes bind-use-unbind-bind-use-unbind pattern std::string texname = gpgpu_ptx_sim_findNamefromTexture(texref); m_NameToCudaArray.erase(texname); m_NameToTexureInfo.erase(texname); -- cgit v1.3 From 14db8e9d45ff253ae79376c7e8e4dc4cb06042b6 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Wed, 23 May 2018 11:14:42 -0700 Subject: unimplement cudaStreaWaitEvent because I don't know what I'm doing --- libcuda/cuda_runtime_api.cc | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index a45ed61..30e3989 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1159,22 +1159,8 @@ __host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) __host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) { - -#if (CUDART_VERSION >= 3000) - if( stream == NULL ) - return g_last_cudaError = cudaErrorInvalidResourceHandle; - return g_last_cudaError = stream->empty()?cudaSuccess:cudaErrorNotReady; -#else - printf("GPGPU-Sim API: cudaStreamWaitEvent ** waiting for event\n"); - fflush(stdout); - CUevent_st *e = (CUevent_st*) event; - while( !e->done() ) - ; - printf("GPGPU-Sim API: cudaStreamWaitEvent ** event detected\n"); - fflush(stdout); - printf("GPGPU-Sim PTX: WARNING: Asynchronous kernel execution not supported (%s)\n", __my_func__); - return g_last_cudaError = cudaSuccess; // it is always success because all cuda calls are synchronous -#endif + cuda_not_implemented(__my_func__,__LINE__); + return g_last_cudaError = cudaErrorUnknown; } /******************************************************************************* -- cgit v1.3 From 006006efb4290f007ec96f0c2e6023d53e7601ff Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 24 May 2018 15:35:05 -0700 Subject: changed assertion to warning when binding to previously bound name. --- src/cuda-sim/cuda-sim.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 2a197c3..34368ce 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -157,7 +157,9 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te std::map::const_iterator t=m_NameToCudaArray.find(texname); //check that there's nothing there first - assert(t == m_NameToCudaArray.end()); + if(t != m_NameToCudaArray.end()){ + printf("GPGPU-Sim PTX: Warning: binding to texref associated with %s, which was previously bound.\nImplicitly unbinding texref associated to %s first\n", texname.c_str(), texname.c_str()); + } m_NameToCudaArray[texname] = array; unsigned int texel_size_bits = array->desc.w + array->desc.x + array->desc.y + array->desc.z; unsigned int texel_size = texel_size_bits/8; -- cgit v1.3 From 7e08538246f386a8e4ce0686d3f6eafff99f23cc Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 25 May 2018 09:32:49 -0700 Subject: fixed merge issue --- src/cuda-sim/instructions.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index d362231..35d1782 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2366,12 +2366,12 @@ void decode_space( memory_space_t &space, ptx_thread_info *thread, const operand type_info_key ti = t->get_key(); if( ti.is_param_kernel() ) space = param_space_kernel; - else if( ti.is_param_local() ) + else if( ti.is_param_local() ) { space = param_space_local; } else if( ti.is_reg() ) { space = param_space_kernel; - } + } else { printf("GPGPU-Sim PTX: ERROR ** cannot resolve .param space for '%s'\n", s->name().c_str() ); abort(); -- cgit v1.3 From 7aa77ad0cb1265b3858a0daa08b5afe026c129f7 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 25 May 2018 09:41:51 -0700 Subject: fixed weird spacing issue --- libcuda/cuda_runtime_api.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 30e3989..cfa9cec 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -989,7 +989,7 @@ __host__ cudaError_t CUDARTAPI cudaBindTextureToArray(const struct textureRefere return g_last_cudaError = cudaSuccess; } -__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref) { +__host__ cudaError_t CUDARTAPI cudaUnbindTexture(const struct textureReference *texref){ CUctx_st *context = GPGPUSim_Context(); gpgpu_t *gpu = context->get_device()->get_gpgpu(); printf("GPGPU-Sim PTX: in cudaUnbindTexture: sizeof(struct textureReference) = %zu\n", sizeof(struct textureReference)); -- cgit v1.3 From fbf8e1180008db2fec31ba1f1e916ea4cb4af97a Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 25 May 2018 17:05:28 -0700 Subject: tentative impl of cudaStreamWaitEvent --- libcuda/cuda_runtime_api.cc | 4 ++-- src/stream_manager.cc | 7 +++++++ src/stream_manager.h | 11 ++++++++++- 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index cfa9cec..de6d5a5 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1159,8 +1159,8 @@ __host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) __host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) { - cuda_not_implemented(__my_func__,__LINE__); - return g_last_cudaError = cudaErrorUnknown; + stream->push(stream_operation(stream, event, flags)); + return g_last_cudaError = cudaSuccess; } /******************************************************************************* diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 3b6cbd5..5b886ab 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -195,6 +195,13 @@ bool stream_operation::do_operation( gpgpu_sim *gpu ) m_stream->record_next_done(); } break; + case stream_wait_event: { + if(g_debug_execution >= 3) + printf("stream wait event\n"); + if(m_event->done()) + m_stream->record_next_done(); + } + break; default: abort(); } diff --git a/src/stream_manager.h b/src/stream_manager.h index 222a1b2..edf2b24 100644 --- a/src/stream_manager.h +++ b/src/stream_manager.h @@ -51,7 +51,8 @@ enum stream_operation_type { stream_memcpy_to_symbol, stream_memcpy_from_symbol, stream_kernel_launch, - stream_event + stream_event, + stream_wait_event }; class stream_operation { @@ -101,6 +102,14 @@ public: m_stream=stream; m_done=false; } + stream_operation( struct CUstream_st *stream, class CUevent_st *e, unsigned int flags ) + { + m_kernel=NULL; + m_type=stream_wait_event; + m_event=e; + m_stream=stream; + m_done=false; + } stream_operation( const void *host_address_src, size_t device_address_dst, size_t cnt, struct CUstream_st *stream ) { m_kernel=NULL; -- cgit v1.3 From 2778712a298a58be4a5abaa28f45805eb3c027c6 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Fri, 25 May 2018 17:41:40 -0700 Subject: seg fault fix --- libcuda/cuda_runtime_api.cc | 16 ++++++++++------ src/stream_manager.cc | 1 + 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index de6d5a5..f130a37 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1157,12 +1157,6 @@ __host__ cudaError_t CUDARTAPI cudaStreamQuery(cudaStream_t stream) #endif } -__host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) -{ - stream->push(stream_operation(stream, event, flags)); - return g_last_cudaError = cudaSuccess; -} - /******************************************************************************* * * * * @@ -1205,6 +1199,16 @@ __host__ cudaError_t CUDARTAPI cudaEventRecord(cudaEvent_t event, cudaStream_t s return g_last_cudaError = cudaSuccess; } +__host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) +{ + CUevent_st *e = get_event(event); + if( !e ) return g_last_cudaError = cudaErrorUnknown; + struct CUstream_st *s = (struct CUstream_st *)stream; + stream_operation op(s,e,flags); + g_stream_manager->push(op); + return g_last_cudaError = cudaSuccess; +} + __host__ cudaError_t CUDARTAPI cudaEventQuery(cudaEvent_t event) { CUevent_st *e = get_event(event); diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 5b886ab..1b8ebb1 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -199,6 +199,7 @@ bool stream_operation::do_operation( gpgpu_sim *gpu ) if(g_debug_execution >= 3) printf("stream wait event\n"); if(m_event->done()) + printf("stream wait event done\n"); m_stream->record_next_done(); } break; -- cgit v1.3 From 7dfa2ae2e6f8ccaaf133318265a7ab00de546e82 Mon Sep 17 00:00:00 2001 From: aamir Date: Sun, 27 May 2018 14:18:53 -0700 Subject: added wmma parsing but execution getting aborted --- cuda-kernels/Makefile | 7 + cuda-kernels/_cuobjdump_1.elf | 15 + cuda-kernels/_cuobjdump_1.ptx | 170 ++++ cuda-kernels/_cuobjdump_1.sass | 2 + cuda-kernels/_cuobjdump_2.elf | 494 +++++++++ cuda-kernels/_cuobjdump_2.sass | 348 +++++++ cuda-kernels/_cuobjdump_complete_output_EIGzTK | 1055 ++++++++++++++++++++ cuda-kernels/_cuobjdump_complete_output_rndQyq | 1055 ++++++++++++++++++++ cuda-kernels/config_fermi_islip.icnt | 70 ++ cuda-kernels/gpgpu_inst_stats.txt | 1 + cuda-kernels/gpgpusim.config | 149 +++ ...usim_power_report__Sun-May-27-14-17-34-2018.log | 324 ++++++ ...usim_power_report__Sun-May-27-14-17-47-2018.log | 324 ++++++ cuda-kernels/gpuwattch_gtx1080Ti.xml | 538 ++++++++++ cuda-kernels/tensor_core | Bin 0 -> 48541 bytes cuda-kernels/tensor_core.cu | 250 +++++ cuobjdump_to_ptxplus/ptx_parser.h | 2 + src/cuda-sim/instructions.cc | 8 +- src/cuda-sim/opcodes.def | 2 + src/cuda-sim/opcodes.h | 11 +- src/cuda-sim/ptx.l | 18 +- src/cuda-sim/ptx.y | 10 + src/cuda-sim/ptx_ir.cc | 6 +- src/cuda-sim/ptx_ir.h | 33 + src/cuda-sim/ptx_parser.cc | 33 +- src/cuda-sim/ptx_parser.h | 2 + 26 files changed, 4918 insertions(+), 9 deletions(-) create mode 100755 cuda-kernels/Makefile create mode 100644 cuda-kernels/_cuobjdump_1.elf create mode 100644 cuda-kernels/_cuobjdump_1.ptx create mode 100644 cuda-kernels/_cuobjdump_1.sass create mode 100644 cuda-kernels/_cuobjdump_2.elf create mode 100644 cuda-kernels/_cuobjdump_2.sass create mode 100644 cuda-kernels/_cuobjdump_complete_output_EIGzTK create mode 100644 cuda-kernels/_cuobjdump_complete_output_rndQyq create mode 100755 cuda-kernels/config_fermi_islip.icnt create mode 100755 cuda-kernels/gpgpu_inst_stats.txt create mode 100755 cuda-kernels/gpgpusim.config create mode 100644 cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log create mode 100644 cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log create mode 100755 cuda-kernels/gpuwattch_gtx1080Ti.xml create mode 100755 cuda-kernels/tensor_core create mode 100644 cuda-kernels/tensor_core.cu diff --git a/cuda-kernels/Makefile b/cuda-kernels/Makefile new file mode 100755 index 0000000..51a7760 --- /dev/null +++ b/cuda-kernels/Makefile @@ -0,0 +1,7 @@ +all: tensor_core.cu + nvcc -arch=sm_70 -lcudart -g -o tensor_core tensor_core.cu + +.PHONY: +clean: + rm tensorcore +# nvcc -arch=sm_70 --gpu-architecture=compute_50 --gpu-code=compute_50 -lcudart -g -o tensor_core tensor_core.cu diff --git a/cuda-kernels/_cuobjdump_1.elf b/cuda-kernels/_cuobjdump_1.elf new file mode 100644 index 0000000..672b0f0 --- /dev/null +++ b/cuda-kernels/_cuobjdump_1.elf @@ -0,0 +1,15 @@ +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 32 0 1 STRTAB 0 0 0 .shstrtab + 2 72 32 0 1 STRTAB 0 0 0 .strtab + 3 a8 18 18 8 SYMTAB 0 2 0 .symtab + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + diff --git a/cuda-kernels/_cuobjdump_1.ptx b/cuda-kernels/_cuobjdump_1.ptx new file mode 100644 index 0000000..3453f4a --- /dev/null +++ b/cuda-kernels/_cuobjdump_1.ptx @@ -0,0 +1,170 @@ + + + + + + + +.version 6.0 +.target sm_70 +.address_size 64 + + +.extern .func (.param .b32 func_retval0) vprintf +( +.param .b64 vprintf_param_0, +.param .b64 vprintf_param_1 +) +; +.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0}; + +.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff( +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7 +) +{ +.local .align 8 .b8 __local_depot0[8]; +.reg .b64 %SP; +.reg .b64 %SPL; +.reg .pred %p<6>; +.reg .f32 %f<34>; +.reg .b32 %r<38>; +.reg .b64 %rd<18>; + + +mov.u64 %rd17, __local_depot0; +cvta.local.u64 %SP, %rd17; +ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0]; +ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1]; +ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2]; +ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3]; +ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4]; +ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5]; + + mov.u32 %r6, %clock; + + mov.u32 %r8, %ntid.x; +mov.u32 %r9, %ctaid.x; +mov.u32 %r10, %tid.x; +mad.lo.s32 %r11, %r8, %r9, %r10; +mov.u32 %r12, WARP_SZ; +div.u32 %r13, %r11, %r12; +mov.u32 %r14, %ntid.y; +mov.u32 %r15, %ctaid.y; +mov.u32 %r16, %tid.y; +mad.lo.s32 %r17, %r14, %r15, %r16; +shl.b32 %r2, %r13, 4; +shl.b32 %r3, %r17, 4; +setp.lt.s32 %p1, %r2, %r4; +setp.gt.s32 %p2, %r5, 0; +and.pred %p3, %p1, %p2; +setp.lt.s32 %p4, %r3, %r7; +and.pred %p5, %p3, %p4; +mov.f32 %f26, 0f00000000; +mov.f32 %f27, %f26; +mov.f32 %f28, %f26; +mov.f32 %f29, %f26; +mov.f32 %f30, %f26; +mov.f32 %f31, %f26; +mov.f32 %f32, %f26; +mov.f32 %f33, %f26; +@!%p5 bra BB0_2; +bra.uni BB0_1; + +BB0_1: +mul.wide.s32 %rd4, %r2, 2; +add.s64 %rd5, %rd1, %rd4; +wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4; +mul.wide.s32 %rd6, %r3, 2; +add.s64 %rd7, %rd2, %rd6; +wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5; +mov.f32 %f25, 0f00000000; +wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25}; + +BB0_2: +add.u64 %rd8, %SP, 0; +cvta.to.local.u64 %rd9, %rd8; +mul.lo.s32 %r35, %r3, %r4; +cvt.s64.s32 %rd10, %r35; +cvt.s64.s32 %rd11, %r2; +add.s64 %rd12, %rd10, %rd11; +shl.b64 %rd13, %rd12, 2; +add.s64 %rd14, %rd3, %rd13; +wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4; + + mov.u32 %r34, %clock; + + sub.s32 %r36, %r34, %r6; +st.local.u32 [%rd9], %r36; +mov.u64 %rd15, $str; +cvta.global.u64 %rd16, %rd15; + + { +.reg .b32 temp_param_reg; + + .param .b64 param0; +st.param.b64 [param0+0], %rd16; +.param .b64 param1; +st.param.b64 [param1+0], %rd8; +.param .b32 retval0; +call.uni (retval0), +vprintf, +( +param0, +param1 +); +ld.param.b32 %r37, [retval0+0]; + + + } + ret; +} + + +.visible .entry _Z17convertFp32ToFp16P6__halfPfi( +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0, +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1, +.param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2 +) +{ +.reg .pred %p<2>; +.reg .b16 %rs<2>; +.reg .f32 %f<2>; +.reg .b32 %r<6>; +.reg .b64 %rd<9>; + + +ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0]; +ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1]; +ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2]; +mov.u32 %r3, %ntid.x; +mov.u32 %r4, %ctaid.x; +mov.u32 %r5, %tid.x; +mad.lo.s32 %r1, %r4, %r3, %r5; +setp.ge.s32 %p1, %r1, %r2; +@%p1 bra BB1_2; + +cvta.to.global.u64 %rd3, %rd2; +mul.wide.s32 %rd4, %r1, 4; +add.s64 %rd5, %rd3, %rd4; +ld.global.f32 %f1, [%rd5]; + + { cvt.rn.f16.f32 %rs1, %f1;} + + + cvta.to.global.u64 %rd6, %rd1; +mul.wide.s32 %rd7, %r1, 2; +add.s64 %rd8, %rd6, %rd7; +st.global.u16 [%rd8], %rs1; + +BB1_2: +ret; +} + + diff --git a/cuda-kernels/_cuobjdump_1.sass b/cuda-kernels/_cuobjdump_1.sass new file mode 100644 index 0000000..2aac29a --- /dev/null +++ b/cuda-kernels/_cuobjdump_1.sass @@ -0,0 +1,2 @@ + code for sm_70 + diff --git a/cuda-kernels/_cuobjdump_2.elf b/cuda-kernels/_cuobjdump_2.elf new file mode 100644 index 0000000..c03b06d --- /dev/null +++ b/cuda-kernels/_cuobjdump_2.elf @@ -0,0 +1,494 @@ +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 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0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 + + +.nv.global.init +0x636f6c63 0x64253d6b 0 + + +.nv.info + <0x1> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x9 0x0 + <0x2> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) min stack size: 0x8 + <0x3> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) frame size: 0x8 + <0x4> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x8 0x0 + <0x5> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) min stack size: 0x0 + <0x6> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) frame size: 0x0 + + +.nv.info._Z17convertFp32ToFp16P6__halfPfi + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x4 0x140160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x14 + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x7> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x60 0xe0 + + +.nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x6 0x2c0160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x2c + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x7 Offset : 0x28 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x6 Offset : 0x24 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x5 Offset : 0x20 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x4 Offset : 0x1c Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x7> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x3 Offset : 0x18 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x8> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x9> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x10> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x11> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x12> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x940 + <0x13> + Attribute: EIATTR_EXTERNS + Format: EIFMT_SVAL + Value: externs: vprintf(0xa) + <0x14> + Attribute: EIATTR_CRS_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x0 + + +.text._Z17convertFp32ToFp16P6__halfPfi +bar = 0 reg = 9 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0x00017a02 0x00000a00 0x00000f00 0x000fd000 +0x00047919 0x00000000 0x00002500 0x000e2200 +0x00027919 0x00000000 0x00002100 0x000e2400 +0x04047a24 0x00000000 0x078e0202 0x001fca00 +0x04007a0c 0x00005c00 0x03f062f0 0x000fd800 +0x0000094d 0x00000000 0x03800000 0x000fea00 +0x00027802 0x00000004 0x00000f00 0x000fca00 +0x04027625 0x00005a00 0x078e0202 0x000fd400 +0x02027381 0x00000000 0x001ee900 0x000e2200 +0x00057802 0x00000002 0x00000f00 0x000fca00 +0x04047625 0x00005800 0x078e0205 0x000fe200 +0x00067304 0x00000002 0x00200800 0x001e3200 +0x04007386 0x00000006 0x0010e500 0x0011e200 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 + + + +.text._Z12wmma_exampleP6__halfS0_Pfiiiff +bar = 0 reg = 32 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0xff017624 0x00000a00 0x078e00ff 0x000fd000 +0x01017810 0xfffffff8 0x07ffe0ff 0x000fc800 +0x01027a10 0x00000800 0x07f1e0ff 0x000fca00 +0xff007624 0x00000900 0x000e06ff 0x000fd000 +0x00037805 0x00000000 0x00005000 0x000fd000 +0x00077906 0x00000020 0x00209000 0x000e2400 +0x00077308 0x00000007 0x00001000 0x001e2200 +0x00067919 0x00000000 0x00002500 0x000e6200 +0x00097919 0x00000000 0x00002100 0x000e6200 +0x07087810 0x0ffffffe 0x07ffe0ff 0x001fcc00 +0x00057305 0x00000008 0x0021f000 0x0000a200 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0x06067a24 0x00000000 0x078e0209 0x002fe400 +0x050a7824 0xffffffe0 0x078e00ff 0x004fc800 +0x05047225 0x0000000a 0x078e0004 0x000fd000 +0x05047225 0x00000006 0x078e00ff 0x000fcc00 +0xff047224 0x000000ff 0x078e0a05 0x000fc800 +0x04067824 0x00000020 0x078e0206 0x000fca00 +0x0600780c 0x00000020 0x03f060f0 0x040fe200 +0x001c7919 0x00000000 0x00002600 0x000e2200 +0x00077919 0x00000000 0x00002200 0x000e3400 +0x06060810 0xffffffe0 0x07ffe0ff 0x000fc800 +0x0600780c 0x00000020 0x03f260f0 0x000fe400 +0x05050810 0x00000001 0x07ffe0ff 0x000fe400 +0xff007a0c 0x00006000 0x03f012f0 0x000fd000 +0x05051810 0x00000001 0x07ffe0ff 0x000fe200 +0x1c1c7a24 0x00000100 0x078e0207 0x001fc600 +0x051d7819 0x00000004 0x000006ff 0x000fe200 +0x1c1c7824 0x00000010 0x078e00ff 0x000fc600 +0x1d007a0c 0x00005e00 0x007012f0 0x000fc800 +0x1c007a0c 0x00005f00 0x007012f0 0x000fe200 +0x00007945 0x000003a0 0x03800000 0x000fe200 +0xff077224 0x000000ff 0x078e00ff 0x000fe200 +0x000b7202 0x000000ff 0x00000f00 0x000fe200 +0xff067224 0x000000ff 0x078e00ff 0x000fe400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0xff0a7224 0x000000ff 0x078e00ff 0x000fc400 +0xff097224 0x000000ff 0x078e00ff 0x000fe400 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00008947 0x00000300 0x03800000 0x000fee00 +0x00067919 0x00000000 0x00000000 0x000e2200 +0xff0a7424 0x00000002 0x078e00ff 0x000fc800 +0x1d107625 0x00005800 0x078e020a 0x000fe200 +0xff047819 0x00000002 0x00011606 0x001fc800 +0x04057812 0x00000003 0x078ec0ff 0x000fe400 +0x06047812 0x00000003 0x078ec0ff 0x000fe400 +0x05077812 0x00000001 0x078ec0ff 0x000fe400 +0xff067819 0x00000004 0x00011606 0x000fe400 +0xff057819 0x00000001 0x00011605 0x000fe200 +0x07077824 0x00000008 0x078e0204 0x000fe200 +0x06067812 0x00000001 0x078ec0ff 0x000fc400 +0x05047211 0x00000004 0x078e18ff 0x000fe200 +0x1c0c7625 0x00005a00 0x078e020a 0x000fe400 +0x06077824 0x00000004 0x078e0207 0x040fe400 +0x06047824 0x00000004 0x078e0204 0x000fe400 +0x07077824 0x00000002 0x078e00ff 0x000fe400 +0x04057824 0x00000002 0x078e00ff 0x000fe400 +0x07107a25 0x00005e00 0x078e0010 0x000fc400 +0x050c7a25 0x00006000 0x078e000c 0x000fd000 +0x10187980 0x00000000 0x0010ed00 0x00006400 +0x0c147980 0x00000000 0x0010ed00 0x00046200 +0x10107980 0x00000010 0x0010ed00 0x001e2200 +0x0c0c7980 0x00000010 0x0010ed00 0x004e2200 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00097202 0x000000ff 0x00000f00 0x000fe200 +0xff0a7224 0x000000ff 0x078e00ff 0x000fe400 +0xff0b7224 0x000000ff 0x078e00ff 0x000fe200 +0x00077202 0x000000ff 0x00000f00 0x000fe200 +0xff047224 0x000000ff 0x078e00ff 0x000fc400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff067224 0x000000ff 0x078e00ff 0x000fe200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x18087236 0x00000014 0x00005408 0x0c226400 +0x180a7236 0x00000014 0x0000d40a 0x0c04a400 +0x18047236 0x00000014 0x00015404 0x0c06e400 +0x18067236 0x00000014 0x0001d406 0x00092800 +0x1a087236 0x00000016 0x00005408 0x0c202400 +0x1a0a7236 0x00000016 0x0000d40a 0x0c426400 +0x1a047236 0x00000016 0x00015404 0x0c84a400 +0x1a067236 0x00000016 0x0001d406 0x0106e800 +0x10087236 0x0000000c 0x00005408 0x0c102400 +0x100a7236 0x0000000c 0x0000d40a 0x0c226400 +0x10047236 0x0000000c 0x00015404 0x0c44a400 +0x10067236 0x0000000c 0x0001d406 0x0086e800 +0x12087236 0x0000000e 0x00005408 0x0c102400 +0x120a7236 0x0000000e 0x0000d40a 0x0c202400 +0x12047236 0x0000000e 0x00015404 0x0c402400 +0x12067236 0x0000000e 0x0001d406 0x00803400 +0x00007941 0x00000000 0x03800000 0x001fea00 +0x000c7919 0x00000000 0x00000000 0x000e2200 +0x1c1c7a24 0x00005e00 0x078e02ff 0x000fe200 +0xff0e7819 0x00000004 0x0001160c 0x001fc400 +0xff0d7819 0x00000002 0x0001160c 0x000fe400 +0x0c0c7812 0x00000003 0x078ec0ff 0x000fe400 +0x0e0e7812 0x00000001 0x078ec0ff 0x000fe400 +0x0d0d7812 0x00000003 0x078ec0ff 0x000fc600 +0x0e0c7824 0x00000004 0x078e020c 0x000fe200 +0x0d0f7812 0x00000001 0x078ec0ff 0x000fe400 +0xff107819 0x00000001 0x0001160d 0x000fe400 +0x0c0d7812 0x00000005 0x078ec0ff 0x040fe400 +0x0c0e7812 0x00000002 0x078ec0ff 0x000fc600 +0x0f0c7824 0x00000008 0x078e020d 0x000fe200 +0xff0f7819 0x0000001f 0x0001141d 0x000fe200 +0x100e7824 0x00000008 0x078e020e 0x000fe200 +0x1d117210 0x0000001c 0x07f1e0ff 0x000fe200 +0xff0d7224 0x000000ff 0x078e00ff 0x000fc600 +0x1c0f7211 0x0000000f 0x000f0eff 0x000fe200 +0x0e0c7a25 0x00005e00 0x078e000c 0x000fe200 +0x110e7a11 0x00005c00 0x078010ff 0x000fe200 +0xff127624 0x00005e00 0x078e00ff 0x000fc600 +0x11117a11 0x00005d00 0x000f140f 0x000fe400 +0x0c107211 0x0000000e 0x078010ff 0x000fe400 +0x120e7819 0x00000002 0x000006ff 0x000fe400 +0xff0f7819 0x0000001e 0x00011612 0x000fe400 +0x0c0d7211 0x00000011 0x000f140d 0x000fe400 +0x0e127211 0x00000010 0x078210ff 0x000fc400 +0x0e117210 0x00000010 0x07f1e0ff 0x040fe400 +0x0e137211 0x0000000d 0x008f140f 0x040fe400 +0x0e157210 0x00000012 0x07f3e0ff 0x000fe200 +0x0f147824 0x00000001 0x000e060d 0x040fe400 +0xff0c7224 0x000000ff 0x078e0010 0x000fe400 +0x0f167824 0x00000001 0x008e0613 0x000fe400 +0xff0e7224 0x000000ff 0x078e0011 0x000fc400 +0xff0f7224 0x000000ff 0x078e0014 0x000fe200 +0x00107202 0x00000015 0x00000f00 0x000fe200 +0xff117224 0x000000ff 0x078e0016 0x000fe200 +0x0c007385 0x00000000 0x0010e908 0x0001e200 +0x0c007385 0x00000008 0x0010e90a 0x0003e800 +0x0e007385 0x00000000 0x0010e909 0x0003e200 +0x0e007385 0x00000008 0x0010e90b 0x0003e200 +0x12007385 0x00000000 0x0010e904 0x0003e200 +0x12007385 0x00000008 0x0010e906 0x0003e200 +0x10007385 0x00000000 0x0010e905 0x0003e200 +0x10007385 0x00000008 0x0010e907 0x0003e200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x02087a10 0x80000800 0x07ffe0ff 0x001fd000 +0x00047805 0x00000000 0x00005000 0x002fd000 +0x04037824 0x00000001 0x078e0a03 0x000fd000 +0x08007387 0x00000003 0x00100800 0x0001e200 +0xff067224 0x000000ff 0x078e0002 0x000fe200 +0x00047802 0x00000000 0x00000f00 0x000fe200 +0xff077224 0x000000ff 0x078e0000 0x000fe200 +0x00057802 0x00000000 0x00000f00 0x000fe400 +0x00147802 0x00000000 0x00000f00 0x000fe400 +0x00157802 0x00000000 0x00000f00 0x000fd000 +0x00007943 0x00000000 0x03c00000 0x001fea00 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 + + +.section .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff REL +2272 $str R_CUDA_ABS32_LO_32 +2304 $str R_CUDA_ABS32_HI_32 +2352 vprintf R_CUDA_ABS47_34 + +.section .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff RELA +2320 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_LO_32 2368 +2336 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_HI_32 2368 + +.section .debug_frame +decodeDebugFrame, frameBuf 0xffffffff, total_length 224 +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x100 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 0 + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_advance_loc4 delta 52 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x970 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 2 + DW_CFA_def_cfa register R1, offset 8 + DW_CFA_advance_loc4 delta 586 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +.section .rel.debug_frame REL +72 _Z17convertFp32ToFp16P6__halfPfi R_NV_64 +184 _Z12wmma_exampleP6__halfS0_Pfiiiff R_NV_64 + diff --git a/cuda-kernels/_cuobjdump_2.sass b/cuda-kernels/_cuobjdump_2.sass new file mode 100644 index 0000000..1b50ed2 --- /dev/null +++ b/cuda-kernels/_cuobjdump_2.sass @@ -0,0 +1,348 @@ + code for sm_70 + Function : _Z17convertFp32ToFp16P6__halfPfi + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ MOV R1, c[0x0][0x28]; /* 0x00000a0000017a02 */ + /* 0x000fd00000000f00 */ + /*0020*/ S2R R4, SR_CTAID.X; /* 0x0000000000047919 */ + /* 0x000e220000002500 */ + /*0030*/ S2R R2, SR_TID.X; /* 0x0000000000027919 */ + /* 0x000e240000002100 */ + /*0040*/ IMAD R4, R4, c[0x0][0x0], R2; /* 0x0000000004047a24 */ + /* 0x001fca00078e0202 */ + /*0050*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT, !PT; /* 0x00005c0004007a0c */ + /* 0x000fd80003f062f0 */ + /*0060*/ @P0 EXIT; /* 0x000000000000094d */ + /* 0x000fea0003800000 */ + /*0070*/ MOV R2, 0x4; /* 0x0000000400027802 */ + /* 0x000fca0000000f00 */ + /*0080*/ IMAD.WIDE R2, R4, R2, c[0x0][0x168]; /* 0x00005a0004027625 */ + /* 0x000fd400078e0202 */ + /*0090*/ LDG.E.SYS R2, [R2]; /* 0x0000000002027381 */ + /* 0x000e2200001ee900 */ + /*00a0*/ MOV R5, 0x2; /* 0x0000000200057802 */ + /* 0x000fca0000000f00 */ + /*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160]; /* 0x0000580004047625 */ + /* 0x000fe200078e0205 */ + /*00c0*/ F2F.F16.F32 R6, R2; /* 0x0000000200067304 */ + /* 0x001e320000200800 */ + /*00d0*/ STG.E.U16.SYS [R4], R6; /* 0x0000000604007386 */ + /* 0x0011e2000010e500 */ + /*00e0*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + ........................................... + + + Function : _Z12wmma_exampleP6__halfS0_Pfiiiff + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ IMAD.U32 R1, RZ, RZ, c[0x0][0x28]; /* 0x00000a00ff017624 */ + /* 0x000fd000078e00ff */ + /*0020*/ IADD3 R1, R1, -0x8, RZ; /* 0xfffffff801017810 */ + /* 0x000fc80007ffe0ff */ + /*0030*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ; /* 0x0000080001027a10 */ + /* 0x000fca0007f1e0ff */ + /*0040*/ IMAD.X R0, RZ, RZ, c[0x0][0x24], P0; /* 0x00000900ff007624 */ + /* 0x000fd000000e06ff */ + /*0050*/ CS2R.32 R3, SR_CLOCKLO; /* 0x0000000000037805 */ + /* 0x000fd00000005000 */ + /*0060*/ I2F.U32.RP R7, 0x20; /* 0x0000002000077906 */ + /* 0x000e240000209000 */ + /*0070*/ MUFU.RCP R7, R7; /* 0x0000000700077308 */ + /* 0x001e220000001000 */ + /*0080*/ S2R R6, SR_CTAID.X; /* 0x0000000000067919 */ + /* 0x000e620000002500 */ + /*0090*/ S2R R9, SR_TID.X; /* 0x0000000000097919 */ + /* 0x000e620000002100 */ + /*00a0*/ IADD3 R8, R7, 0xffffffe, RZ; /* 0x0ffffffe07087810 */ + /* 0x001fcc0007ffe0ff */ + /*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R8; /* 0x0000000800057305 */ + /* 0x0000a2000021f000 */ + /*00c0*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*00d0*/ IMAD R6, R6, c[0x0][0x0], R9; /* 0x0000000006067a24 */ + /* 0x002fe400078e0209 */ + /*00e0*/ IMAD.U32 R10, R5, -0x20, RZ; /* 0xffffffe0050a7824 */ + /* 0x004fc800078e00ff */ + /*00f0*/ IMAD.WIDE.U32 R4, R5, R10, R4; /* 0x0000000a05047225 */ + /* 0x000fd000078e0004 */ + /*0100*/ IMAD.WIDE.U32 R4, R5, R6, RZ; /* 0x0000000605047225 */ + /* 0x000fcc00078e00ff */ + /*0110*/ IMAD R4, RZ, RZ, -R5; /* 0x000000ffff047224 */ + /* 0x000fc800078e0a05 */ + /*0120*/ IMAD R6, R4, 0x20, R6; /* 0x0000002004067824 */ + /* 0x000fca00078e0206 */ + /*0130*/ ISETP.GE.U32.AND P0, PT, R6.reuse, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x040fe20003f060f0 */ + /*0140*/ S2R R28, SR_CTAID.Y; /* 0x00000000001c7919 */ + /* 0x000e220000002600 */ + /*0150*/ S2R R7, SR_TID.Y; /* 0x0000000000077919 */ + /* 0x000e340000002200 */ + /*0160*/ @P0 IADD3 R6, R6, -0x20, RZ; /* 0xffffffe006060810 */ + /* 0x000fc80007ffe0ff */ + /*0170*/ ISETP.GE.U32.AND P1, PT, R6, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x000fe40003f260f0 */ + /*0180*/ @P0 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105050810 */ + /* 0x000fe40007ffe0ff */ + /*0190*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT, !PT; /* 0x00006000ff007a0c */ + /* 0x000fd00003f012f0 */ + /*01a0*/ @P1 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105051810 */ + /* 0x000fe20007ffe0ff */ + /*01b0*/ IMAD R28, R28, c[0x0][0x4], R7; /* 0x000001001c1c7a24 */ + /* 0x001fc600078e0207 */ + /*01c0*/ SHF.L.U32 R29, R5, 0x4, RZ; /* 0x00000004051d7819 */ + /* 0x000fe200000006ff */ + /*01d0*/ IMAD.U32 R28, R28, 0x10, RZ; /* 0x000000101c1c7824 */ + /* 0x000fc600078e00ff */ + /*01e0*/ ISETP.LT.AND P0, PT, R29, c[0x0][0x178], P0, !PT; /* 0x00005e001d007a0c */ + /* 0x000fc800007012f0 */ + /*01f0*/ ISETP.LT.AND P0, PT, R28, c[0x0][0x17c], P0, !PT; /* 0x00005f001c007a0c */ + /* 0x000fe200007012f0 */ + /*0200*/ BSSY B0, 0x5b0; /* 0x000003a000007945 */ + /* 0x000fe20003800000 */ + /*0210*/ IMAD.U32 R7, RZ, RZ, RZ; /* 0x000000ffff077224 */ + /* 0x000fe200078e00ff */ + /*0220*/ MOV R11, RZ; /* 0x000000ff000b7202 */ + /* 0x000fe20000000f00 */ + /*0230*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe400078e00ff */ + /*0240*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0250*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*0260*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fc400078e00ff */ + /*0270*/ IMAD.U32 R9, RZ, RZ, RZ; /* 0x000000ffff097224 */ + /* 0x000fe400078e00ff */ + /*0280*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0290*/ @!P0 BRA 0x5a0; /* 0x0000030000008947 */ + /* 0x000fee0003800000 */ + /*02a0*/ S2R R6, SR_LANEID; /* 0x0000000000067919 */ + /* 0x000e220000000000 */ + /*02b0*/ IMAD.U32 R10, RZ, RZ, 0x2; /* 0x00000002ff0a7424 */ + /* 0x000fc800078e00ff */ + /*02c0*/ IMAD.WIDE R16, R29, R10, c[0x0][0x160]; /* 0x000058001d107625 */ + /* 0x000fe200078e020a */ + /*02d0*/ SHF.R.U32.HI R4, RZ, 0x2, R6; /* 0x00000002ff047819 */ + /* 0x001fc80000011606 */ + /*02e0*/ LOP3.LUT R5, R4, 0x3, RZ, 0xc0, !PT; /* 0x0000000304057812 */ + /* 0x000fe400078ec0ff */ + /*02f0*/ LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT; /* 0x0000000306047812 */ + /* 0x000fe400078ec0ff */ + /*0300*/ LOP3.LUT R7, R5, 0x1, RZ, 0xc0, !PT; /* 0x0000000105077812 */ + /* 0x000fe400078ec0ff */ + /*0310*/ SHF.R.U32.HI R6, RZ, 0x4, R6; /* 0x00000004ff067819 */ + /* 0x000fe40000011606 */ + /*0320*/ SHF.R.U32.HI R5, RZ, 0x1, R5; /* 0x00000001ff057819 */ + /* 0x000fe20000011605 */ + /*0330*/ IMAD R7, R7, 0x8, R4; /* 0x0000000807077824 */ + /* 0x000fe200078e0204 */ + /*0340*/ LOP3.LUT R6, R6, 0x1, RZ, 0xc0, !PT; /* 0x0000000106067812 */ + /* 0x000fc400078ec0ff */ + /*0350*/ LEA R4, R5, R4, 0x3; /* 0x0000000405047211 */ + /* 0x000fe200078e18ff */ + /*0360*/ IMAD.WIDE R12, R28, R10, c[0x0][0x168]; /* 0x00005a001c0c7625 */ + /* 0x000fe400078e020a */ + /*0370*/ IMAD R7, R6.reuse, 0x4, R7; /* 0x0000000406077824 */ + /* 0x040fe400078e0207 */ + /*0380*/ IMAD R4, R6, 0x4, R4; /* 0x0000000406047824 */ + /* 0x000fe400078e0204 */ + /*0390*/ IMAD.U32 R7, R7, 0x2, RZ; /* 0x0000000207077824 */ + /* 0x000fe400078e00ff */ + /*03a0*/ IMAD.U32 R5, R4, 0x2, RZ; /* 0x0000000204057824 */ + /* 0x000fe400078e00ff */ + /*03b0*/ IMAD.WIDE.U32 R16, R7, c[0x0][0x178], R16; /* 0x00005e0007107a25 */ + /* 0x000fc400078e0010 */ + /*03c0*/ IMAD.WIDE.U32 R12, R5, c[0x0][0x180], R12; /* 0x00006000050c7a25 */ + /* 0x000fd000078e000c */ + /*03d0*/ LD.E.128.SYS R24, [R16]; /* 0x0000000010187980 */ + /* 0x000064000010ed00 */ + /*03e0*/ LD.E.128.SYS R20, [R12]; /* 0x000000000c147980 */ + /* 0x000462000010ed00 */ + /*03f0*/ LD.E.128.SYS R16, [R16+0x10]; /* 0x0000001010107980 */ + /* 0x001e22000010ed00 */ + /*0400*/ LD.E.128.SYS R12, [R12+0x10]; /* 0x000000100c0c7980 */ + /* 0x004e22000010ed00 */ + /*0410*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0420*/ MOV R9, RZ; /* 0x000000ff00097202 */ + /* 0x000fe20000000f00 */ + /*0430*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fe400078e00ff */ + /*0440*/ IMAD.U32 R11, RZ, RZ, RZ; /* 0x000000ffff0b7224 */ + /* 0x000fe200078e00ff */ + /*0450*/ MOV R7, RZ; /* 0x000000ff00077202 */ + /* 0x000fe20000000f00 */ + /*0460*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fc400078e00ff */ + /*0470*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0480*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe200078e00ff */ + /*0490*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*04a0*/ HMMA.884.F32.F32.STEP0 R8, R24.reuse, R20.reuse.T, R8; /* 0x0000001418087236 */ + /* 0x0c22640000005408 */ + /*04b0*/ HMMA.884.F32.F32.STEP1 R10, R24.reuse, R20.reuse.T, R10; /* 0x00000014180a7236 */ + /* 0x0c04a4000000d40a */ + /*04c0*/ HMMA.884.F32.F32.STEP2 R4, R24.reuse, R20.reuse.T, R4; /* 0x0000001418047236 */ + /* 0x0c06e40000015404 */ + /*04d0*/ HMMA.884.F32.F32.STEP3 R6, R24, R20.T, R6; /* 0x0000001418067236 */ + /* 0x000928000001d406 */ + /*04e0*/ HMMA.884.F32.F32.STEP0 R8, R26.reuse, R22.reuse.T, R8; /* 0x000000161a087236 */ + /* 0x0c20240000005408 */ + /*04f0*/ HMMA.884.F32.F32.STEP1 R10, R26.reuse, R22.reuse.T, R10; /* 0x000000161a0a7236 */ + /* 0x0c4264000000d40a */ + /*0500*/ HMMA.884.F32.F32.STEP2 R4, R26.reuse, R22.reuse.T, R4; /* 0x000000161a047236 */ + /* 0x0c84a40000015404 */ + /*0510*/ HMMA.884.F32.F32.STEP3 R6, R26, R22.T, R6; /* 0x000000161a067236 */ + /* 0x0106e8000001d406 */ + /*0520*/ HMMA.884.F32.F32.STEP0 R8, R16.reuse, R12.reuse.T, R8; /* 0x0000000c10087236 */ + /* 0x0c10240000005408 */ + /*0530*/ HMMA.884.F32.F32.STEP1 R10, R16.reuse, R12.reuse.T, R10; /* 0x0000000c100a7236 */ + /* 0x0c2264000000d40a */ + /*0540*/ HMMA.884.F32.F32.STEP2 R4, R16.reuse, R12.reuse.T, R4; /* 0x0000000c10047236 */ + /* 0x0c44a40000015404 */ + /*0550*/ HMMA.884.F32.F32.STEP3 R6, R16, R12.T, R6; /* 0x0000000c10067236 */ + /* 0x0086e8000001d406 */ + /*0560*/ HMMA.884.F32.F32.STEP0 R8, R18.reuse, R14.reuse.T, R8; /* 0x0000000e12087236 */ + /* 0x0c10240000005408 */ + /*0570*/ HMMA.884.F32.F32.STEP1 R10, R18.reuse, R14.reuse.T, R10; /* 0x0000000e120a7236 */ + /* 0x0c2024000000d40a */ + /*0580*/ HMMA.884.F32.F32.STEP2 R4, R18.reuse, R14.reuse.T, R4; /* 0x0000000e12047236 */ + /* 0x0c40240000015404 */ + /*0590*/ HMMA.884.F32.F32.STEP3 R6, R18, R14.T, R6; /* 0x0000000e12067236 */ + /* 0x008034000001d406 */ + /*05a0*/ BSYNC B0; /* 0x0000000000007941 */ + /* 0x001fea0003800000 */ + /*05b0*/ S2R R12, SR_LANEID; /* 0x00000000000c7919 */ + /* 0x000e220000000000 */ + /*05c0*/ IMAD R28, R28, c[0x0][0x178], RZ; /* 0x00005e001c1c7a24 */ + /* 0x000fe200078e02ff */ + /*05d0*/ SHF.R.U32.HI R14, RZ, 0x4, R12; /* 0x00000004ff0e7819 */ + /* 0x001fc4000001160c */ + /*05e0*/ SHF.R.U32.HI R13, RZ, 0x2, R12; /* 0x00000002ff0d7819 */ + /* 0x000fe4000001160c */ + /*05f0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT; /* 0x000000030c0c7812 */ + /* 0x000fe400078ec0ff */ + /*0600*/ LOP3.LUT R14, R14, 0x1, RZ, 0xc0, !PT; /* 0x000000010e0e7812 */ + /* 0x000fe400078ec0ff */ + /*0610*/ LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT; /* 0x000000030d0d7812 */ + /* 0x000fc600078ec0ff */ + /*0620*/ IMAD R12, R14, 0x4, R12; /* 0x000000040e0c7824 */ + /* 0x000fe200078e020c */ + /*0630*/ LOP3.LUT R15, R13, 0x1, RZ, 0xc0, !PT; /* 0x000000010d0f7812 */ + /* 0x000fe400078ec0ff */ + /*0640*/ SHF.R.U32.HI R16, RZ, 0x1, R13; /* 0x00000001ff107819 */ + /* 0x000fe4000001160d */ + /*0650*/ LOP3.LUT R13, R12.reuse, 0x5, RZ, 0xc0, !PT; /* 0x000000050c0d7812 */ + /* 0x040fe400078ec0ff */ + /*0660*/ LOP3.LUT R14, R12, 0x2, RZ, 0xc0, !PT; /* 0x000000020c0e7812 */ + /* 0x000fc600078ec0ff */ + /*0670*/ IMAD R12, R15, 0x8, R13; /* 0x000000080f0c7824 */ + /* 0x000fe200078e020d */ + /*0680*/ SHF.R.S32.HI R15, RZ, 0x1f, R29; /* 0x0000001fff0f7819 */ + /* 0x000fe2000001141d */ + /*0690*/ IMAD R14, R16, 0x8, R14; /* 0x00000008100e7824 */ + /* 0x000fe200078e020e */ + /*06a0*/ IADD3 R17, P0, R29, R28, RZ; /* 0x0000001c1d117210 */ + /* 0x000fe20007f1e0ff */ + /*06b0*/ IMAD.U32 R13, RZ, RZ, RZ; /* 0x000000ffff0d7224 */ + /* 0x000fc600078e00ff */ + /*06c0*/ LEA.HI.X.SX32 R15, R28, R15, 0x1, P0; /* 0x0000000f1c0f7211 */ + /* 0x000fe200000f0eff */ + /*06d0*/ IMAD.WIDE.U32 R12, R14, c[0x0][0x178], R12; /* 0x00005e000e0c7a25 */ + /* 0x000fe200078e000c */ + /*06e0*/ LEA R14, P0, R17, c[0x0][0x170], 0x2; /* 0x00005c00110e7a11 */ + /* 0x000fe200078010ff */ + /*06f0*/ IMAD.U32 R18, RZ, RZ, c[0x0][0x178]; /* 0x00005e00ff127624 */ + /* 0x000fc600078e00ff */ + /*0700*/ LEA.HI.X R17, R17, c[0x0][0x174], R15, 0x2, P0; /* 0x00005d0011117a11 */ + /* 0x000fe400000f140f */ + /*0710*/ LEA R16, P0, R12, R14, 0x2; /* 0x0000000e0c107211 */ + /* 0x000fe400078010ff */ + /*0720*/ SHF.L.U32 R14, R18, 0x2, RZ; /* 0x00000002120e7819 */ + /* 0x000fe400000006ff */ + /*0730*/ SHF.R.U32.HI R15, RZ, 0x1e, R18; /* 0x0000001eff0f7819 */ + /* 0x000fe40000011612 */ + /*0740*/ LEA.HI.X R13, R12, R17, R13, 0x2, P0; /* 0x000000110c0d7211 */ + /* 0x000fe400000f140d */ + /*0750*/ LEA R18, P1, R14, R16, 0x2; /* 0x000000100e127211 */ + /* 0x000fc400078210ff */ + /*0760*/ IADD3 R17, P0, R14.reuse, R16, RZ; /* 0x000000100e117210 */ + /* 0x040fe40007f1e0ff */ + /*0770*/ LEA.HI.X R19, R14.reuse, R13, R15, 0x2, P1; /* 0x0000000d0e137211 */ + /* 0x040fe400008f140f */ + /*0780*/ IADD3 R21, P1, R14, R18, RZ; /* 0x000000120e157210 */ + /* 0x000fe20007f3e0ff */ + /*0790*/ IMAD.X R20, R15.reuse, 0x1, R13, P0; /* 0x000000010f147824 */ + /* 0x040fe400000e060d */ + /*07a0*/ IMAD.U32 R12, RZ, RZ, R16; /* 0x000000ffff0c7224 */ + /* 0x000fe400078e0010 */ + /*07b0*/ IMAD.X R22, R15, 0x1, R19, P1; /* 0x000000010f167824 */ + /* 0x000fe400008e0613 */ + /*07c0*/ IMAD.U32 R14, RZ, RZ, R17; /* 0x000000ffff0e7224 */ + /* 0x000fc400078e0011 */ + /*07d0*/ IMAD.U32 R15, RZ, RZ, R20; /* 0x000000ffff0f7224 */ + /* 0x000fe200078e0014 */ + /*07e0*/ MOV R16, R21; /* 0x0000001500107202 */ + /* 0x000fe20000000f00 */ + /*07f0*/ IMAD.U32 R17, RZ, RZ, R22; /* 0x000000ffff117224 */ + /* 0x000fe200078e0016 */ + /*0800*/ ST.E.SYS [R12], R8; /* 0x000000000c007385 */ + /* 0x0001e2000010e908 */ + /*0810*/ ST.E.SYS [R12+0x8], R10; /* 0x000000080c007385 */ + /* 0x0003e8000010e90a */ + /*0820*/ ST.E.SYS [R14], R9; /* 0x000000000e007385 */ + /* 0x0003e2000010e909 */ + /*0830*/ ST.E.SYS [R14+0x8], R11; /* 0x000000080e007385 */ + /* 0x0003e2000010e90b */ + /*0840*/ ST.E.SYS [R18], R4; /* 0x0000000012007385 */ + /* 0x0003e2000010e904 */ + /*0850*/ ST.E.SYS [R18+0x8], R6; /* 0x0000000812007385 */ + /* 0x0003e2000010e906 */ + /*0860*/ ST.E.SYS [R16], R5; /* 0x0000000010007385 */ + /* 0x0003e2000010e905 */ + /*0870*/ ST.E.SYS [R16+0x8], R7; /* 0x0000000810007385 */ + /* 0x0003e2000010e907 */ + /*0880*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*0890*/ IADD3 R8, R2, -c[0x0][0x20], RZ; /* 0x8000080002087a10 */ + /* 0x001fd00007ffe0ff */ + /*08a0*/ CS2R.32 R4, SR_CLOCKLO; /* 0x0000000000047805 */ + /* 0x002fd00000005000 */ + /*08b0*/ IMAD R3, R4, 0x1, -R3; /* 0x0000000104037824 */ + /* 0x000fd000078e0a03 */ + /*08c0*/ STL [R8], R3; /* 0x0000000308007387 */ + /* 0x0001e20000100800 */ + /*08d0*/ IMAD.U32 R6, RZ, RZ, R2; /* 0x000000ffff067224 */ + /* 0x000fe200078e0002 */ + /*08e0*/ MOV R4, 0x0; /* 0x0000000000047802 */ + /* 0x000fe20000000f00 */ + /*08f0*/ IMAD.U32 R7, RZ, RZ, R0; /* 0x000000ffff077224 */ + /* 0x000fe200078e0000 */ + /*0900*/ MOV R5, 0x0; /* 0x0000000000057802 */ + /* 0x000fe40000000f00 */ + /*0910*/ MOV R20, 0x0; /* 0x0000000000147802 */ + /* 0x000fe40000000f00 */ + /*0920*/ MOV R21, 0x0; /* 0x0000000000157802 */ + /* 0x000fd00000000f00 */ + /*0930*/ CALL.ABS.NOINC 0x0; /* 0x0000000000007943 */ + /* 0x001fea0003c00000 */ + /*0940*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*0950*/ BRA 0x950; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + /*0960*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + /*0970*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + ............................................. + + + diff --git a/cuda-kernels/_cuobjdump_complete_output_EIGzTK b/cuda-kernels/_cuobjdump_complete_output_EIGzTK new file mode 100644 index 0000000..36999c0 --- /dev/null +++ b/cuda-kernels/_cuobjdump_complete_output_EIGzTK @@ -0,0 +1,1055 @@ + +Fatbin elf code: +================ +arch = sm_70 +code version = [1,7] +producer = +host = linux +compile_size = 64bit + +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 32 0 1 STRTAB 0 0 0 .shstrtab + 2 72 32 0 1 STRTAB 0 0 0 .strtab + 3 a8 18 18 8 SYMTAB 0 2 0 .symtab + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + + code for sm_70 + +Fatbin elf code: +================ +arch = sm_70 +code version = [1,7] +producer = cuda +host = linux +compile_size = 64bit + +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 21b 0 1 STRTAB 0 0 0 .shstrtab + 2 25b 273 0 1 STRTAB 0 0 0 .strtab + 3 4d0 108 18 8 SYMTAB 0 2 7 .symtab + 4 5d8 e0 0 1 PROGBITS 0 0 0 .debug_frame + 5 6b8 48 0 4 CUDA_INFO 0 3 0 .nv.info + 6 700 50 0 4 CUDA_INFO 0 3 d .nv.info._Z17convertFp32ToFp16P6__halfPfi + 7 750 ac 0 4 CUDA_INFO 0 3 e .nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + 8 800 30 10 8 REL 0 3 e .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff + 9 830 30 18 8 RELA 0 3 e .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff + a 860 20 10 8 REL 0 3 4 .rel.debug_frame + b 880 174 0 4 PROGBITS 2 0 d .nv.constant0._Z17convertFp32ToFp16P6__halfPfi + c 9f4 18c 0 4 PROGBITS 2 0 e .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff + d b80 100 0 80 PROGBITS 6 3 9000008 .text._Z17convertFp32ToFp16P6__halfPfi + e c80 980 0 80 PROGBITS 6 3 20000009 .text._Z12wmma_exampleP6__halfS0_Pfiiiff + f 1600 9 0 10 PROGBITS 3 0 0 .nv.global.init + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + 1 0 0 3 0 d .text._Z17convertFp32ToFp16P6__halfPfi + 2 0 0 3 0 f .nv.global.init + 3 0 9 1 0 f $str + 4 0 0 3 0 b .nv.constant0._Z17convertFp32ToFp16P6__halfPfi + 5 0 0 3 0 e .text._Z12wmma_exampleP6__halfS0_Pfiiiff + 6 0 0 3 0 c .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff + 7 0 0 3 0 4 .debug_frame + 8 0 256 12 10 d _Z17convertFp32ToFp16P6__halfPfi + 9 0 2432 12 10 e _Z12wmma_exampleP6__halfS0_Pfiiiff + 10 0 0 12 0 0 vprintf + + +.nv.constant0._Z17convertFp32ToFp16P6__halfPfi +0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 + + + +.nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff +0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 + + +.nv.global.init +0x636f6c63 0x64253d6b 0 + + +.nv.info + <0x1> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x9 0x0 + <0x2> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) min stack size: 0x8 + <0x3> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) frame size: 0x8 + <0x4> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x8 0x0 + <0x5> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) min stack size: 0x0 + <0x6> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) frame size: 0x0 + + +.nv.info._Z17convertFp32ToFp16P6__halfPfi + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x4 0x140160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x14 + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x7> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x60 0xe0 + + +.nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x6 0x2c0160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x2c + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x7 Offset : 0x28 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x6 Offset : 0x24 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x5 Offset : 0x20 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x4 Offset : 0x1c Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x7> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x3 Offset : 0x18 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x8> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x9> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x10> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x11> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x12> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x940 + <0x13> + Attribute: EIATTR_EXTERNS + Format: EIFMT_SVAL + Value: externs: vprintf(0xa) + <0x14> + Attribute: EIATTR_CRS_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x0 + + +.text._Z17convertFp32ToFp16P6__halfPfi +bar = 0 reg = 9 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0x00017a02 0x00000a00 0x00000f00 0x000fd000 +0x00047919 0x00000000 0x00002500 0x000e2200 +0x00027919 0x00000000 0x00002100 0x000e2400 +0x04047a24 0x00000000 0x078e0202 0x001fca00 +0x04007a0c 0x00005c00 0x03f062f0 0x000fd800 +0x0000094d 0x00000000 0x03800000 0x000fea00 +0x00027802 0x00000004 0x00000f00 0x000fca00 +0x04027625 0x00005a00 0x078e0202 0x000fd400 +0x02027381 0x00000000 0x001ee900 0x000e2200 +0x00057802 0x00000002 0x00000f00 0x000fca00 +0x04047625 0x00005800 0x078e0205 0x000fe200 +0x00067304 0x00000002 0x00200800 0x001e3200 +0x04007386 0x00000006 0x0010e500 0x0011e200 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 + + + +.text._Z12wmma_exampleP6__halfS0_Pfiiiff +bar = 0 reg = 32 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0xff017624 0x00000a00 0x078e00ff 0x000fd000 +0x01017810 0xfffffff8 0x07ffe0ff 0x000fc800 +0x01027a10 0x00000800 0x07f1e0ff 0x000fca00 +0xff007624 0x00000900 0x000e06ff 0x000fd000 +0x00037805 0x00000000 0x00005000 0x000fd000 +0x00077906 0x00000020 0x00209000 0x000e2400 +0x00077308 0x00000007 0x00001000 0x001e2200 +0x00067919 0x00000000 0x00002500 0x000e6200 +0x00097919 0x00000000 0x00002100 0x000e6200 +0x07087810 0x0ffffffe 0x07ffe0ff 0x001fcc00 +0x00057305 0x00000008 0x0021f000 0x0000a200 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0x06067a24 0x00000000 0x078e0209 0x002fe400 +0x050a7824 0xffffffe0 0x078e00ff 0x004fc800 +0x05047225 0x0000000a 0x078e0004 0x000fd000 +0x05047225 0x00000006 0x078e00ff 0x000fcc00 +0xff047224 0x000000ff 0x078e0a05 0x000fc800 +0x04067824 0x00000020 0x078e0206 0x000fca00 +0x0600780c 0x00000020 0x03f060f0 0x040fe200 +0x001c7919 0x00000000 0x00002600 0x000e2200 +0x00077919 0x00000000 0x00002200 0x000e3400 +0x06060810 0xffffffe0 0x07ffe0ff 0x000fc800 +0x0600780c 0x00000020 0x03f260f0 0x000fe400 +0x05050810 0x00000001 0x07ffe0ff 0x000fe400 +0xff007a0c 0x00006000 0x03f012f0 0x000fd000 +0x05051810 0x00000001 0x07ffe0ff 0x000fe200 +0x1c1c7a24 0x00000100 0x078e0207 0x001fc600 +0x051d7819 0x00000004 0x000006ff 0x000fe200 +0x1c1c7824 0x00000010 0x078e00ff 0x000fc600 +0x1d007a0c 0x00005e00 0x007012f0 0x000fc800 +0x1c007a0c 0x00005f00 0x007012f0 0x000fe200 +0x00007945 0x000003a0 0x03800000 0x000fe200 +0xff077224 0x000000ff 0x078e00ff 0x000fe200 +0x000b7202 0x000000ff 0x00000f00 0x000fe200 +0xff067224 0x000000ff 0x078e00ff 0x000fe400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0xff0a7224 0x000000ff 0x078e00ff 0x000fc400 +0xff097224 0x000000ff 0x078e00ff 0x000fe400 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00008947 0x00000300 0x03800000 0x000fee00 +0x00067919 0x00000000 0x00000000 0x000e2200 +0xff0a7424 0x00000002 0x078e00ff 0x000fc800 +0x1d107625 0x00005800 0x078e020a 0x000fe200 +0xff047819 0x00000002 0x00011606 0x001fc800 +0x04057812 0x00000003 0x078ec0ff 0x000fe400 +0x06047812 0x00000003 0x078ec0ff 0x000fe400 +0x05077812 0x00000001 0x078ec0ff 0x000fe400 +0xff067819 0x00000004 0x00011606 0x000fe400 +0xff057819 0x00000001 0x00011605 0x000fe200 +0x07077824 0x00000008 0x078e0204 0x000fe200 +0x06067812 0x00000001 0x078ec0ff 0x000fc400 +0x05047211 0x00000004 0x078e18ff 0x000fe200 +0x1c0c7625 0x00005a00 0x078e020a 0x000fe400 +0x06077824 0x00000004 0x078e0207 0x040fe400 +0x06047824 0x00000004 0x078e0204 0x000fe400 +0x07077824 0x00000002 0x078e00ff 0x000fe400 +0x04057824 0x00000002 0x078e00ff 0x000fe400 +0x07107a25 0x00005e00 0x078e0010 0x000fc400 +0x050c7a25 0x00006000 0x078e000c 0x000fd000 +0x10187980 0x00000000 0x0010ed00 0x00006400 +0x0c147980 0x00000000 0x0010ed00 0x00046200 +0x10107980 0x00000010 0x0010ed00 0x001e2200 +0x0c0c7980 0x00000010 0x0010ed00 0x004e2200 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00097202 0x000000ff 0x00000f00 0x000fe200 +0xff0a7224 0x000000ff 0x078e00ff 0x000fe400 +0xff0b7224 0x000000ff 0x078e00ff 0x000fe200 +0x00077202 0x000000ff 0x00000f00 0x000fe200 +0xff047224 0x000000ff 0x078e00ff 0x000fc400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff067224 0x000000ff 0x078e00ff 0x000fe200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x18087236 0x00000014 0x00005408 0x0c226400 +0x180a7236 0x00000014 0x0000d40a 0x0c04a400 +0x18047236 0x00000014 0x00015404 0x0c06e400 +0x18067236 0x00000014 0x0001d406 0x00092800 +0x1a087236 0x00000016 0x00005408 0x0c202400 +0x1a0a7236 0x00000016 0x0000d40a 0x0c426400 +0x1a047236 0x00000016 0x00015404 0x0c84a400 +0x1a067236 0x00000016 0x0001d406 0x0106e800 +0x10087236 0x0000000c 0x00005408 0x0c102400 +0x100a7236 0x0000000c 0x0000d40a 0x0c226400 +0x10047236 0x0000000c 0x00015404 0x0c44a400 +0x10067236 0x0000000c 0x0001d406 0x0086e800 +0x12087236 0x0000000e 0x00005408 0x0c102400 +0x120a7236 0x0000000e 0x0000d40a 0x0c202400 +0x12047236 0x0000000e 0x00015404 0x0c402400 +0x12067236 0x0000000e 0x0001d406 0x00803400 +0x00007941 0x00000000 0x03800000 0x001fea00 +0x000c7919 0x00000000 0x00000000 0x000e2200 +0x1c1c7a24 0x00005e00 0x078e02ff 0x000fe200 +0xff0e7819 0x00000004 0x0001160c 0x001fc400 +0xff0d7819 0x00000002 0x0001160c 0x000fe400 +0x0c0c7812 0x00000003 0x078ec0ff 0x000fe400 +0x0e0e7812 0x00000001 0x078ec0ff 0x000fe400 +0x0d0d7812 0x00000003 0x078ec0ff 0x000fc600 +0x0e0c7824 0x00000004 0x078e020c 0x000fe200 +0x0d0f7812 0x00000001 0x078ec0ff 0x000fe400 +0xff107819 0x00000001 0x0001160d 0x000fe400 +0x0c0d7812 0x00000005 0x078ec0ff 0x040fe400 +0x0c0e7812 0x00000002 0x078ec0ff 0x000fc600 +0x0f0c7824 0x00000008 0x078e020d 0x000fe200 +0xff0f7819 0x0000001f 0x0001141d 0x000fe200 +0x100e7824 0x00000008 0x078e020e 0x000fe200 +0x1d117210 0x0000001c 0x07f1e0ff 0x000fe200 +0xff0d7224 0x000000ff 0x078e00ff 0x000fc600 +0x1c0f7211 0x0000000f 0x000f0eff 0x000fe200 +0x0e0c7a25 0x00005e00 0x078e000c 0x000fe200 +0x110e7a11 0x00005c00 0x078010ff 0x000fe200 +0xff127624 0x00005e00 0x078e00ff 0x000fc600 +0x11117a11 0x00005d00 0x000f140f 0x000fe400 +0x0c107211 0x0000000e 0x078010ff 0x000fe400 +0x120e7819 0x00000002 0x000006ff 0x000fe400 +0xff0f7819 0x0000001e 0x00011612 0x000fe400 +0x0c0d7211 0x00000011 0x000f140d 0x000fe400 +0x0e127211 0x00000010 0x078210ff 0x000fc400 +0x0e117210 0x00000010 0x07f1e0ff 0x040fe400 +0x0e137211 0x0000000d 0x008f140f 0x040fe400 +0x0e157210 0x00000012 0x07f3e0ff 0x000fe200 +0x0f147824 0x00000001 0x000e060d 0x040fe400 +0xff0c7224 0x000000ff 0x078e0010 0x000fe400 +0x0f167824 0x00000001 0x008e0613 0x000fe400 +0xff0e7224 0x000000ff 0x078e0011 0x000fc400 +0xff0f7224 0x000000ff 0x078e0014 0x000fe200 +0x00107202 0x00000015 0x00000f00 0x000fe200 +0xff117224 0x000000ff 0x078e0016 0x000fe200 +0x0c007385 0x00000000 0x0010e908 0x0001e200 +0x0c007385 0x00000008 0x0010e90a 0x0003e800 +0x0e007385 0x00000000 0x0010e909 0x0003e200 +0x0e007385 0x00000008 0x0010e90b 0x0003e200 +0x12007385 0x00000000 0x0010e904 0x0003e200 +0x12007385 0x00000008 0x0010e906 0x0003e200 +0x10007385 0x00000000 0x0010e905 0x0003e200 +0x10007385 0x00000008 0x0010e907 0x0003e200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x02087a10 0x80000800 0x07ffe0ff 0x001fd000 +0x00047805 0x00000000 0x00005000 0x002fd000 +0x04037824 0x00000001 0x078e0a03 0x000fd000 +0x08007387 0x00000003 0x00100800 0x0001e200 +0xff067224 0x000000ff 0x078e0002 0x000fe200 +0x00047802 0x00000000 0x00000f00 0x000fe200 +0xff077224 0x000000ff 0x078e0000 0x000fe200 +0x00057802 0x00000000 0x00000f00 0x000fe400 +0x00147802 0x00000000 0x00000f00 0x000fe400 +0x00157802 0x00000000 0x00000f00 0x000fd000 +0x00007943 0x00000000 0x03c00000 0x001fea00 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 + + +.section .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff REL +2272 $str R_CUDA_ABS32_LO_32 +2304 $str R_CUDA_ABS32_HI_32 +2352 vprintf R_CUDA_ABS47_34 + +.section .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff RELA +2320 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_LO_32 2368 +2336 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_HI_32 2368 + +.section .debug_frame +decodeDebugFrame, frameBuf 0xffffffff, total_length 224 +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x100 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 0 + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_advance_loc4 delta 52 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x970 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 2 + DW_CFA_def_cfa register R1, offset 8 + DW_CFA_advance_loc4 delta 586 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +.section .rel.debug_frame REL +72 _Z17convertFp32ToFp16P6__halfPfi R_NV_64 +184 _Z12wmma_exampleP6__halfS0_Pfiiiff R_NV_64 + + code for sm_70 + Function : _Z17convertFp32ToFp16P6__halfPfi + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ MOV R1, c[0x0][0x28]; /* 0x00000a0000017a02 */ + /* 0x000fd00000000f00 */ + /*0020*/ S2R R4, SR_CTAID.X; /* 0x0000000000047919 */ + /* 0x000e220000002500 */ + /*0030*/ S2R R2, SR_TID.X; /* 0x0000000000027919 */ + /* 0x000e240000002100 */ + /*0040*/ IMAD R4, R4, c[0x0][0x0], R2; /* 0x0000000004047a24 */ + /* 0x001fca00078e0202 */ + /*0050*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT, !PT; /* 0x00005c0004007a0c */ + /* 0x000fd80003f062f0 */ + /*0060*/ @P0 EXIT; /* 0x000000000000094d */ + /* 0x000fea0003800000 */ + /*0070*/ MOV R2, 0x4; /* 0x0000000400027802 */ + /* 0x000fca0000000f00 */ + /*0080*/ IMAD.WIDE R2, R4, R2, c[0x0][0x168]; /* 0x00005a0004027625 */ + /* 0x000fd400078e0202 */ + /*0090*/ LDG.E.SYS R2, [R2]; /* 0x0000000002027381 */ + /* 0x000e2200001ee900 */ + /*00a0*/ MOV R5, 0x2; /* 0x0000000200057802 */ + /* 0x000fca0000000f00 */ + /*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160]; /* 0x0000580004047625 */ + /* 0x000fe200078e0205 */ + /*00c0*/ F2F.F16.F32 R6, R2; /* 0x0000000200067304 */ + /* 0x001e320000200800 */ + /*00d0*/ STG.E.U16.SYS [R4], R6; /* 0x0000000604007386 */ + /* 0x0011e2000010e500 */ + /*00e0*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + ........................................... + + + Function : _Z12wmma_exampleP6__halfS0_Pfiiiff + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ IMAD.U32 R1, RZ, RZ, c[0x0][0x28]; /* 0x00000a00ff017624 */ + /* 0x000fd000078e00ff */ + /*0020*/ IADD3 R1, R1, -0x8, RZ; /* 0xfffffff801017810 */ + /* 0x000fc80007ffe0ff */ + /*0030*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ; /* 0x0000080001027a10 */ + /* 0x000fca0007f1e0ff */ + /*0040*/ IMAD.X R0, RZ, RZ, c[0x0][0x24], P0; /* 0x00000900ff007624 */ + /* 0x000fd000000e06ff */ + /*0050*/ CS2R.32 R3, SR_CLOCKLO; /* 0x0000000000037805 */ + /* 0x000fd00000005000 */ + /*0060*/ I2F.U32.RP R7, 0x20; /* 0x0000002000077906 */ + /* 0x000e240000209000 */ + /*0070*/ MUFU.RCP R7, R7; /* 0x0000000700077308 */ + /* 0x001e220000001000 */ + /*0080*/ S2R R6, SR_CTAID.X; /* 0x0000000000067919 */ + /* 0x000e620000002500 */ + /*0090*/ S2R R9, SR_TID.X; /* 0x0000000000097919 */ + /* 0x000e620000002100 */ + /*00a0*/ IADD3 R8, R7, 0xffffffe, RZ; /* 0x0ffffffe07087810 */ + /* 0x001fcc0007ffe0ff */ + /*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R8; /* 0x0000000800057305 */ + /* 0x0000a2000021f000 */ + /*00c0*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*00d0*/ IMAD R6, R6, c[0x0][0x0], R9; /* 0x0000000006067a24 */ + /* 0x002fe400078e0209 */ + /*00e0*/ IMAD.U32 R10, R5, -0x20, RZ; /* 0xffffffe0050a7824 */ + /* 0x004fc800078e00ff */ + /*00f0*/ IMAD.WIDE.U32 R4, R5, R10, R4; /* 0x0000000a05047225 */ + /* 0x000fd000078e0004 */ + /*0100*/ IMAD.WIDE.U32 R4, R5, R6, RZ; /* 0x0000000605047225 */ + /* 0x000fcc00078e00ff */ + /*0110*/ IMAD R4, RZ, RZ, -R5; /* 0x000000ffff047224 */ + /* 0x000fc800078e0a05 */ + /*0120*/ IMAD R6, R4, 0x20, R6; /* 0x0000002004067824 */ + /* 0x000fca00078e0206 */ + /*0130*/ ISETP.GE.U32.AND P0, PT, R6.reuse, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x040fe20003f060f0 */ + /*0140*/ S2R R28, SR_CTAID.Y; /* 0x00000000001c7919 */ + /* 0x000e220000002600 */ + /*0150*/ S2R R7, SR_TID.Y; /* 0x0000000000077919 */ + /* 0x000e340000002200 */ + /*0160*/ @P0 IADD3 R6, R6, -0x20, RZ; /* 0xffffffe006060810 */ + /* 0x000fc80007ffe0ff */ + /*0170*/ ISETP.GE.U32.AND P1, PT, R6, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x000fe40003f260f0 */ + /*0180*/ @P0 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105050810 */ + /* 0x000fe40007ffe0ff */ + /*0190*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT, !PT; /* 0x00006000ff007a0c */ + /* 0x000fd00003f012f0 */ + /*01a0*/ @P1 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105051810 */ + /* 0x000fe20007ffe0ff */ + /*01b0*/ IMAD R28, R28, c[0x0][0x4], R7; /* 0x000001001c1c7a24 */ + /* 0x001fc600078e0207 */ + /*01c0*/ SHF.L.U32 R29, R5, 0x4, RZ; /* 0x00000004051d7819 */ + /* 0x000fe200000006ff */ + /*01d0*/ IMAD.U32 R28, R28, 0x10, RZ; /* 0x000000101c1c7824 */ + /* 0x000fc600078e00ff */ + /*01e0*/ ISETP.LT.AND P0, PT, R29, c[0x0][0x178], P0, !PT; /* 0x00005e001d007a0c */ + /* 0x000fc800007012f0 */ + /*01f0*/ ISETP.LT.AND P0, PT, R28, c[0x0][0x17c], P0, !PT; /* 0x00005f001c007a0c */ + /* 0x000fe200007012f0 */ + /*0200*/ BSSY B0, 0x5b0; /* 0x000003a000007945 */ + /* 0x000fe20003800000 */ + /*0210*/ IMAD.U32 R7, RZ, RZ, RZ; /* 0x000000ffff077224 */ + /* 0x000fe200078e00ff */ + /*0220*/ MOV R11, RZ; /* 0x000000ff000b7202 */ + /* 0x000fe20000000f00 */ + /*0230*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe400078e00ff */ + /*0240*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0250*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*0260*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fc400078e00ff */ + /*0270*/ IMAD.U32 R9, RZ, RZ, RZ; /* 0x000000ffff097224 */ + /* 0x000fe400078e00ff */ + /*0280*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0290*/ @!P0 BRA 0x5a0; /* 0x0000030000008947 */ + /* 0x000fee0003800000 */ + /*02a0*/ S2R R6, SR_LANEID; /* 0x0000000000067919 */ + /* 0x000e220000000000 */ + /*02b0*/ IMAD.U32 R10, RZ, RZ, 0x2; /* 0x00000002ff0a7424 */ + /* 0x000fc800078e00ff */ + /*02c0*/ IMAD.WIDE R16, R29, R10, c[0x0][0x160]; /* 0x000058001d107625 */ + /* 0x000fe200078e020a */ + /*02d0*/ SHF.R.U32.HI R4, RZ, 0x2, R6; /* 0x00000002ff047819 */ + /* 0x001fc80000011606 */ + /*02e0*/ LOP3.LUT R5, R4, 0x3, RZ, 0xc0, !PT; /* 0x0000000304057812 */ + /* 0x000fe400078ec0ff */ + /*02f0*/ LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT; /* 0x0000000306047812 */ + /* 0x000fe400078ec0ff */ + /*0300*/ LOP3.LUT R7, R5, 0x1, RZ, 0xc0, !PT; /* 0x0000000105077812 */ + /* 0x000fe400078ec0ff */ + /*0310*/ SHF.R.U32.HI R6, RZ, 0x4, R6; /* 0x00000004ff067819 */ + /* 0x000fe40000011606 */ + /*0320*/ SHF.R.U32.HI R5, RZ, 0x1, R5; /* 0x00000001ff057819 */ + /* 0x000fe20000011605 */ + /*0330*/ IMAD R7, R7, 0x8, R4; /* 0x0000000807077824 */ + /* 0x000fe200078e0204 */ + /*0340*/ LOP3.LUT R6, R6, 0x1, RZ, 0xc0, !PT; /* 0x0000000106067812 */ + /* 0x000fc400078ec0ff */ + /*0350*/ LEA R4, R5, R4, 0x3; /* 0x0000000405047211 */ + /* 0x000fe200078e18ff */ + /*0360*/ IMAD.WIDE R12, R28, R10, c[0x0][0x168]; /* 0x00005a001c0c7625 */ + /* 0x000fe400078e020a */ + /*0370*/ IMAD R7, R6.reuse, 0x4, R7; /* 0x0000000406077824 */ + /* 0x040fe400078e0207 */ + /*0380*/ IMAD R4, R6, 0x4, R4; /* 0x0000000406047824 */ + /* 0x000fe400078e0204 */ + /*0390*/ IMAD.U32 R7, R7, 0x2, RZ; /* 0x0000000207077824 */ + /* 0x000fe400078e00ff */ + /*03a0*/ IMAD.U32 R5, R4, 0x2, RZ; /* 0x0000000204057824 */ + /* 0x000fe400078e00ff */ + /*03b0*/ IMAD.WIDE.U32 R16, R7, c[0x0][0x178], R16; /* 0x00005e0007107a25 */ + /* 0x000fc400078e0010 */ + /*03c0*/ IMAD.WIDE.U32 R12, R5, c[0x0][0x180], R12; /* 0x00006000050c7a25 */ + /* 0x000fd000078e000c */ + /*03d0*/ LD.E.128.SYS R24, [R16]; /* 0x0000000010187980 */ + /* 0x000064000010ed00 */ + /*03e0*/ LD.E.128.SYS R20, [R12]; /* 0x000000000c147980 */ + /* 0x000462000010ed00 */ + /*03f0*/ LD.E.128.SYS R16, [R16+0x10]; /* 0x0000001010107980 */ + /* 0x001e22000010ed00 */ + /*0400*/ LD.E.128.SYS R12, [R12+0x10]; /* 0x000000100c0c7980 */ + /* 0x004e22000010ed00 */ + /*0410*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0420*/ MOV R9, RZ; /* 0x000000ff00097202 */ + /* 0x000fe20000000f00 */ + /*0430*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fe400078e00ff */ + /*0440*/ IMAD.U32 R11, RZ, RZ, RZ; /* 0x000000ffff0b7224 */ + /* 0x000fe200078e00ff */ + /*0450*/ MOV R7, RZ; /* 0x000000ff00077202 */ + /* 0x000fe20000000f00 */ + /*0460*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fc400078e00ff */ + /*0470*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0480*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe200078e00ff */ + /*0490*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*04a0*/ HMMA.884.F32.F32.STEP0 R8, R24.reuse, R20.reuse.T, R8; /* 0x0000001418087236 */ + /* 0x0c22640000005408 */ + /*04b0*/ HMMA.884.F32.F32.STEP1 R10, R24.reuse, R20.reuse.T, R10; /* 0x00000014180a7236 */ + /* 0x0c04a4000000d40a */ + /*04c0*/ HMMA.884.F32.F32.STEP2 R4, R24.reuse, R20.reuse.T, R4; /* 0x0000001418047236 */ + /* 0x0c06e40000015404 */ + /*04d0*/ HMMA.884.F32.F32.STEP3 R6, R24, R20.T, R6; /* 0x0000001418067236 */ + /* 0x000928000001d406 */ + /*04e0*/ HMMA.884.F32.F32.STEP0 R8, R26.reuse, R22.reuse.T, R8; /* 0x000000161a087236 */ + /* 0x0c20240000005408 */ + /*04f0*/ HMMA.884.F32.F32.STEP1 R10, R26.reuse, R22.reuse.T, R10; /* 0x000000161a0a7236 */ + /* 0x0c4264000000d40a */ + /*0500*/ HMMA.884.F32.F32.STEP2 R4, R26.reuse, R22.reuse.T, R4; /* 0x000000161a047236 */ + /* 0x0c84a40000015404 */ + /*0510*/ HMMA.884.F32.F32.STEP3 R6, R26, R22.T, R6; /* 0x000000161a067236 */ + /* 0x0106e8000001d406 */ + /*0520*/ HMMA.884.F32.F32.STEP0 R8, R16.reuse, R12.reuse.T, R8; /* 0x0000000c10087236 */ + /* 0x0c10240000005408 */ + /*0530*/ HMMA.884.F32.F32.STEP1 R10, R16.reuse, R12.reuse.T, R10; /* 0x0000000c100a7236 */ + /* 0x0c2264000000d40a */ + /*0540*/ HMMA.884.F32.F32.STEP2 R4, R16.reuse, R12.reuse.T, R4; /* 0x0000000c10047236 */ + /* 0x0c44a40000015404 */ + /*0550*/ HMMA.884.F32.F32.STEP3 R6, R16, R12.T, R6; /* 0x0000000c10067236 */ + /* 0x0086e8000001d406 */ + /*0560*/ HMMA.884.F32.F32.STEP0 R8, R18.reuse, R14.reuse.T, R8; /* 0x0000000e12087236 */ + /* 0x0c10240000005408 */ + /*0570*/ HMMA.884.F32.F32.STEP1 R10, R18.reuse, R14.reuse.T, R10; /* 0x0000000e120a7236 */ + /* 0x0c2024000000d40a */ + /*0580*/ HMMA.884.F32.F32.STEP2 R4, R18.reuse, R14.reuse.T, R4; /* 0x0000000e12047236 */ + /* 0x0c40240000015404 */ + /*0590*/ HMMA.884.F32.F32.STEP3 R6, R18, R14.T, R6; /* 0x0000000e12067236 */ + /* 0x008034000001d406 */ + /*05a0*/ BSYNC B0; /* 0x0000000000007941 */ + /* 0x001fea0003800000 */ + /*05b0*/ S2R R12, SR_LANEID; /* 0x00000000000c7919 */ + /* 0x000e220000000000 */ + /*05c0*/ IMAD R28, R28, c[0x0][0x178], RZ; /* 0x00005e001c1c7a24 */ + /* 0x000fe200078e02ff */ + /*05d0*/ SHF.R.U32.HI R14, RZ, 0x4, R12; /* 0x00000004ff0e7819 */ + /* 0x001fc4000001160c */ + /*05e0*/ SHF.R.U32.HI R13, RZ, 0x2, R12; /* 0x00000002ff0d7819 */ + /* 0x000fe4000001160c */ + /*05f0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT; /* 0x000000030c0c7812 */ + /* 0x000fe400078ec0ff */ + /*0600*/ LOP3.LUT R14, R14, 0x1, RZ, 0xc0, !PT; /* 0x000000010e0e7812 */ + /* 0x000fe400078ec0ff */ + /*0610*/ LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT; /* 0x000000030d0d7812 */ + /* 0x000fc600078ec0ff */ + /*0620*/ IMAD R12, R14, 0x4, R12; /* 0x000000040e0c7824 */ + /* 0x000fe200078e020c */ + /*0630*/ LOP3.LUT R15, R13, 0x1, RZ, 0xc0, !PT; /* 0x000000010d0f7812 */ + /* 0x000fe400078ec0ff */ + /*0640*/ SHF.R.U32.HI R16, RZ, 0x1, R13; /* 0x00000001ff107819 */ + /* 0x000fe4000001160d */ + /*0650*/ LOP3.LUT R13, R12.reuse, 0x5, RZ, 0xc0, !PT; /* 0x000000050c0d7812 */ + /* 0x040fe400078ec0ff */ + /*0660*/ LOP3.LUT R14, R12, 0x2, RZ, 0xc0, !PT; /* 0x000000020c0e7812 */ + /* 0x000fc600078ec0ff */ + /*0670*/ IMAD R12, R15, 0x8, R13; /* 0x000000080f0c7824 */ + /* 0x000fe200078e020d */ + /*0680*/ SHF.R.S32.HI R15, RZ, 0x1f, R29; /* 0x0000001fff0f7819 */ + /* 0x000fe2000001141d */ + /*0690*/ IMAD R14, R16, 0x8, R14; /* 0x00000008100e7824 */ + /* 0x000fe200078e020e */ + /*06a0*/ IADD3 R17, P0, R29, R28, RZ; /* 0x0000001c1d117210 */ + /* 0x000fe20007f1e0ff */ + /*06b0*/ IMAD.U32 R13, RZ, RZ, RZ; /* 0x000000ffff0d7224 */ + /* 0x000fc600078e00ff */ + /*06c0*/ LEA.HI.X.SX32 R15, R28, R15, 0x1, P0; /* 0x0000000f1c0f7211 */ + /* 0x000fe200000f0eff */ + /*06d0*/ IMAD.WIDE.U32 R12, R14, c[0x0][0x178], R12; /* 0x00005e000e0c7a25 */ + /* 0x000fe200078e000c */ + /*06e0*/ LEA R14, P0, R17, c[0x0][0x170], 0x2; /* 0x00005c00110e7a11 */ + /* 0x000fe200078010ff */ + /*06f0*/ IMAD.U32 R18, RZ, RZ, c[0x0][0x178]; /* 0x00005e00ff127624 */ + /* 0x000fc600078e00ff */ + /*0700*/ LEA.HI.X R17, R17, c[0x0][0x174], R15, 0x2, P0; /* 0x00005d0011117a11 */ + /* 0x000fe400000f140f */ + /*0710*/ LEA R16, P0, R12, R14, 0x2; /* 0x0000000e0c107211 */ + /* 0x000fe400078010ff */ + /*0720*/ SHF.L.U32 R14, R18, 0x2, RZ; /* 0x00000002120e7819 */ + /* 0x000fe400000006ff */ + /*0730*/ SHF.R.U32.HI R15, RZ, 0x1e, R18; /* 0x0000001eff0f7819 */ + /* 0x000fe40000011612 */ + /*0740*/ LEA.HI.X R13, R12, R17, R13, 0x2, P0; /* 0x000000110c0d7211 */ + /* 0x000fe400000f140d */ + /*0750*/ LEA R18, P1, R14, R16, 0x2; /* 0x000000100e127211 */ + /* 0x000fc400078210ff */ + /*0760*/ IADD3 R17, P0, R14.reuse, R16, RZ; /* 0x000000100e117210 */ + /* 0x040fe40007f1e0ff */ + /*0770*/ LEA.HI.X R19, R14.reuse, R13, R15, 0x2, P1; /* 0x0000000d0e137211 */ + /* 0x040fe400008f140f */ + /*0780*/ IADD3 R21, P1, R14, R18, RZ; /* 0x000000120e157210 */ + /* 0x000fe20007f3e0ff */ + /*0790*/ IMAD.X R20, R15.reuse, 0x1, R13, P0; /* 0x000000010f147824 */ + /* 0x040fe400000e060d */ + /*07a0*/ IMAD.U32 R12, RZ, RZ, R16; /* 0x000000ffff0c7224 */ + /* 0x000fe400078e0010 */ + /*07b0*/ IMAD.X R22, R15, 0x1, R19, P1; /* 0x000000010f167824 */ + /* 0x000fe400008e0613 */ + /*07c0*/ IMAD.U32 R14, RZ, RZ, R17; /* 0x000000ffff0e7224 */ + /* 0x000fc400078e0011 */ + /*07d0*/ IMAD.U32 R15, RZ, RZ, R20; /* 0x000000ffff0f7224 */ + /* 0x000fe200078e0014 */ + /*07e0*/ MOV R16, R21; /* 0x0000001500107202 */ + /* 0x000fe20000000f00 */ + /*07f0*/ IMAD.U32 R17, RZ, RZ, R22; /* 0x000000ffff117224 */ + /* 0x000fe200078e0016 */ + /*0800*/ ST.E.SYS [R12], R8; /* 0x000000000c007385 */ + /* 0x0001e2000010e908 */ + /*0810*/ ST.E.SYS [R12+0x8], R10; /* 0x000000080c007385 */ + /* 0x0003e8000010e90a */ + /*0820*/ ST.E.SYS [R14], R9; /* 0x000000000e007385 */ + /* 0x0003e2000010e909 */ + /*0830*/ ST.E.SYS [R14+0x8], R11; /* 0x000000080e007385 */ + /* 0x0003e2000010e90b */ + /*0840*/ ST.E.SYS [R18], R4; /* 0x0000000012007385 */ + /* 0x0003e2000010e904 */ + /*0850*/ ST.E.SYS [R18+0x8], R6; /* 0x0000000812007385 */ + /* 0x0003e2000010e906 */ + /*0860*/ ST.E.SYS [R16], R5; /* 0x0000000010007385 */ + /* 0x0003e2000010e905 */ + /*0870*/ ST.E.SYS [R16+0x8], R7; /* 0x0000000810007385 */ + /* 0x0003e2000010e907 */ + /*0880*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*0890*/ IADD3 R8, R2, -c[0x0][0x20], RZ; /* 0x8000080002087a10 */ + /* 0x001fd00007ffe0ff */ + /*08a0*/ CS2R.32 R4, SR_CLOCKLO; /* 0x0000000000047805 */ + /* 0x002fd00000005000 */ + /*08b0*/ IMAD R3, R4, 0x1, -R3; /* 0x0000000104037824 */ + /* 0x000fd000078e0a03 */ + /*08c0*/ STL [R8], R3; /* 0x0000000308007387 */ + /* 0x0001e20000100800 */ + /*08d0*/ IMAD.U32 R6, RZ, RZ, R2; /* 0x000000ffff067224 */ + /* 0x000fe200078e0002 */ + /*08e0*/ MOV R4, 0x0; /* 0x0000000000047802 */ + /* 0x000fe20000000f00 */ + /*08f0*/ IMAD.U32 R7, RZ, RZ, R0; /* 0x000000ffff077224 */ + /* 0x000fe200078e0000 */ + /*0900*/ MOV R5, 0x0; /* 0x0000000000057802 */ + /* 0x000fe40000000f00 */ + /*0910*/ MOV R20, 0x0; /* 0x0000000000147802 */ + /* 0x000fe40000000f00 */ + /*0920*/ MOV R21, 0x0; /* 0x0000000000157802 */ + /* 0x000fd00000000f00 */ + /*0930*/ CALL.ABS.NOINC 0x0; /* 0x0000000000007943 */ + /* 0x001fea0003c00000 */ + /*0940*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*0950*/ BRA 0x950; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + /*0960*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + /*0970*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + ............................................. + + + +Fatbin ptx code: +================ +arch = sm_70 +code version = [6,0] +producer = cuda +host = linux +compile_size = 64bit +compressed + + + + + + + + +.version 6.0 +.target sm_70 +.address_size 64 + + +.extern .func (.param .b32 func_retval0) vprintf +( +.param .b64 vprintf_param_0, +.param .b64 vprintf_param_1 +) +; +.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0}; + +.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff( +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7 +) +{ +.local .align 8 .b8 __local_depot0[8]; +.reg .b64 %SP; +.reg .b64 %SPL; +.reg .pred %p<6>; +.reg .f32 %f<34>; +.reg .b32 %r<38>; +.reg .b64 %rd<18>; + + +mov.u64 %rd17, __local_depot0; +cvta.local.u64 %SP, %rd17; +ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0]; +ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1]; +ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2]; +ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3]; +ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4]; +ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5]; + + mov.u32 %r6, %clock; + + mov.u32 %r8, %ntid.x; +mov.u32 %r9, %ctaid.x; +mov.u32 %r10, %tid.x; +mad.lo.s32 %r11, %r8, %r9, %r10; +mov.u32 %r12, WARP_SZ; +div.u32 %r13, %r11, %r12; +mov.u32 %r14, %ntid.y; +mov.u32 %r15, %ctaid.y; +mov.u32 %r16, %tid.y; +mad.lo.s32 %r17, %r14, %r15, %r16; +shl.b32 %r2, %r13, 4; +shl.b32 %r3, %r17, 4; +setp.lt.s32 %p1, %r2, %r4; +setp.gt.s32 %p2, %r5, 0; +and.pred %p3, %p1, %p2; +setp.lt.s32 %p4, %r3, %r7; +and.pred %p5, %p3, %p4; +mov.f32 %f26, 0f00000000; +mov.f32 %f27, %f26; +mov.f32 %f28, %f26; +mov.f32 %f29, %f26; +mov.f32 %f30, %f26; +mov.f32 %f31, %f26; +mov.f32 %f32, %f26; +mov.f32 %f33, %f26; +@!%p5 bra BB0_2; +bra.uni BB0_1; + +BB0_1: +mul.wide.s32 %rd4, %r2, 2; +add.s64 %rd5, %rd1, %rd4; +wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4; +mul.wide.s32 %rd6, %r3, 2; +add.s64 %rd7, %rd2, %rd6; +wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5; +mov.f32 %f25, 0f00000000; +wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25}; + +BB0_2: +add.u64 %rd8, %SP, 0; +cvta.to.local.u64 %rd9, %rd8; +mul.lo.s32 %r35, %r3, %r4; +cvt.s64.s32 %rd10, %r35; +cvt.s64.s32 %rd11, %r2; +add.s64 %rd12, %rd10, %rd11; +shl.b64 %rd13, %rd12, 2; +add.s64 %rd14, %rd3, %rd13; +wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4; + + mov.u32 %r34, %clock; + + sub.s32 %r36, %r34, %r6; +st.local.u32 [%rd9], %r36; +mov.u64 %rd15, $str; +cvta.global.u64 %rd16, %rd15; + + { +.reg .b32 temp_param_reg; + + .param .b64 param0; +st.param.b64 [param0+0], %rd16; +.param .b64 param1; +st.param.b64 [param1+0], %rd8; +.param .b32 retval0; +call.uni (retval0), +vprintf, +( +param0, +param1 +); +ld.param.b32 %r37, [retval0+0]; + + + } + ret; +} + + +.visible .entry _Z17convertFp32ToFp16P6__halfPfi( +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0, +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1, +.param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2 +) +{ +.reg .pred %p<2>; +.reg .b16 %rs<2>; +.reg .f32 %f<2>; +.reg .b32 %r<6>; +.reg .b64 %rd<9>; + + +ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0]; +ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1]; +ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2]; +mov.u32 %r3, %ntid.x; +mov.u32 %r4, %ctaid.x; +mov.u32 %r5, %tid.x; +mad.lo.s32 %r1, %r4, %r3, %r5; +setp.ge.s32 %p1, %r1, %r2; +@%p1 bra BB1_2; + +cvta.to.global.u64 %rd3, %rd2; +mul.wide.s32 %rd4, %r1, 4; +add.s64 %rd5, %rd3, %rd4; +ld.global.f32 %f1, [%rd5]; + + { cvt.rn.f16.f32 %rs1, %f1;} + + + cvta.to.global.u64 %rd6, %rd1; +mul.wide.s32 %rd7, %r1, 2; +add.s64 %rd8, %rd6, %rd7; +st.global.u16 [%rd8], %rs1; + +BB1_2: +ret; +} + + diff --git a/cuda-kernels/_cuobjdump_complete_output_rndQyq b/cuda-kernels/_cuobjdump_complete_output_rndQyq new file mode 100644 index 0000000..36999c0 --- /dev/null +++ b/cuda-kernels/_cuobjdump_complete_output_rndQyq @@ -0,0 +1,1055 @@ + +Fatbin elf code: +================ +arch = sm_70 +code version = [1,7] +producer = +host = linux +compile_size = 64bit + +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 32 0 1 STRTAB 0 0 0 .shstrtab + 2 72 32 0 1 STRTAB 0 0 0 .strtab + 3 a8 18 18 8 SYMTAB 0 2 0 .symtab + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + + code for sm_70 + +Fatbin elf code: +================ +arch = sm_70 +code version = [1,7] +producer = cuda +host = linux +compile_size = 64bit + +64bit elf: type=2, abi=7, sm=70, toolkit=90, flags = 0x460546 +Sections: +Index Offset Size ES Align Type Flags Link Info Name + 1 40 21b 0 1 STRTAB 0 0 0 .shstrtab + 2 25b 273 0 1 STRTAB 0 0 0 .strtab + 3 4d0 108 18 8 SYMTAB 0 2 7 .symtab + 4 5d8 e0 0 1 PROGBITS 0 0 0 .debug_frame + 5 6b8 48 0 4 CUDA_INFO 0 3 0 .nv.info + 6 700 50 0 4 CUDA_INFO 0 3 d .nv.info._Z17convertFp32ToFp16P6__halfPfi + 7 750 ac 0 4 CUDA_INFO 0 3 e .nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + 8 800 30 10 8 REL 0 3 e .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff + 9 830 30 18 8 RELA 0 3 e .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff + a 860 20 10 8 REL 0 3 4 .rel.debug_frame + b 880 174 0 4 PROGBITS 2 0 d .nv.constant0._Z17convertFp32ToFp16P6__halfPfi + c 9f4 18c 0 4 PROGBITS 2 0 e .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff + d b80 100 0 80 PROGBITS 6 3 9000008 .text._Z17convertFp32ToFp16P6__halfPfi + e c80 980 0 80 PROGBITS 6 3 20000009 .text._Z12wmma_exampleP6__halfS0_Pfiiiff + f 1600 9 0 10 PROGBITS 3 0 0 .nv.global.init + +.section .strtab + +.section .shstrtab + +.section .symtab + index value size info other shndx name + 0 0 0 0 0 0 (null) + 1 0 0 3 0 d .text._Z17convertFp32ToFp16P6__halfPfi + 2 0 0 3 0 f .nv.global.init + 3 0 9 1 0 f $str + 4 0 0 3 0 b .nv.constant0._Z17convertFp32ToFp16P6__halfPfi + 5 0 0 3 0 e .text._Z12wmma_exampleP6__halfS0_Pfiiiff + 6 0 0 3 0 c .nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff + 7 0 0 3 0 4 .debug_frame + 8 0 256 12 10 d _Z17convertFp32ToFp16P6__halfPfi + 9 0 2432 12 10 e _Z12wmma_exampleP6__halfS0_Pfiiiff + 10 0 0 12 0 0 vprintf + + +.nv.constant0._Z17convertFp32ToFp16P6__halfPfi +0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 + + + +.nv.constant0._Z12wmma_exampleP6__halfS0_Pfiiiff +0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 0x00000000 0x00000000 +0x00000000 0x00000000 + + +.nv.global.init +0x636f6c63 0x64253d6b 0 + + +.nv.info + <0x1> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x9 0x0 + <0x2> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) min stack size: 0x8 + <0x3> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z12wmma_exampleP6__halfS0_Pfiiiff(0x9) frame size: 0x8 + <0x4> + Attribute: EIATTR_MAX_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x8 0x0 + <0x5> + Attribute: EIATTR_MIN_STACK_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) min stack size: 0x0 + <0x6> + Attribute: EIATTR_FRAME_SIZE + Format: EIFMT_SVAL + Value: function: _Z17convertFp32ToFp16P6__halfPfi(0x8) frame size: 0x0 + + +.nv.info._Z17convertFp32ToFp16P6__halfPfi + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x4 0x140160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x14 + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x7> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x60 0xe0 + + +.nv.info._Z12wmma_exampleP6__halfS0_Pfiiiff + <0x1> + Attribute: EIATTR_PARAM_CBANK + Format: EIFMT_SVAL + Value: 0x6 0x2c0160 + <0x2> + Attribute: EIATTR_CBANK_PARAM_SIZE + Format: EIFMT_HVAL + Value: 0x2c + <0x3> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x7 Offset : 0x28 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x4> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x6 Offset : 0x24 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x5> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x5 Offset : 0x20 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x6> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x4 Offset : 0x1c Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x7> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x3 Offset : 0x18 Size : 0x4 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x8> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x2 Offset : 0x10 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x9> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x1 Offset : 0x8 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x10> + Attribute: EIATTR_KPARAM_INFO + Format: EIFMT_SVAL + Value: Index : 0x0 Ordinal : 0x0 Offset : 0x0 Size : 0x8 + Pointee's logAlignment : 0x0 Space : 0x0 cbank : 0x1f Parameter Space : CBANK + <0x11> + Attribute: EIATTR_MAXREG_COUNT + Format: EIFMT_HVAL + Value: 0xff + <0x12> + Attribute: EIATTR_EXIT_INSTR_OFFSETS + Format: EIFMT_SVAL + Value: 0x940 + <0x13> + Attribute: EIATTR_EXTERNS + Format: EIFMT_SVAL + Value: externs: vprintf(0xa) + <0x14> + Attribute: EIATTR_CRS_STACK_SIZE + Format: EIFMT_SVAL + Value: 0x0 + + +.text._Z17convertFp32ToFp16P6__halfPfi +bar = 0 reg = 9 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0x00017a02 0x00000a00 0x00000f00 0x000fd000 +0x00047919 0x00000000 0x00002500 0x000e2200 +0x00027919 0x00000000 0x00002100 0x000e2400 +0x04047a24 0x00000000 0x078e0202 0x001fca00 +0x04007a0c 0x00005c00 0x03f062f0 0x000fd800 +0x0000094d 0x00000000 0x03800000 0x000fea00 +0x00027802 0x00000004 0x00000f00 0x000fca00 +0x04027625 0x00005a00 0x078e0202 0x000fd400 +0x02027381 0x00000000 0x001ee900 0x000e2200 +0x00057802 0x00000002 0x00000f00 0x000fca00 +0x04047625 0x00005800 0x078e0205 0x000fe200 +0x00067304 0x00000002 0x00200800 0x001e3200 +0x04007386 0x00000006 0x0010e500 0x0011e200 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 + + + +.text._Z12wmma_exampleP6__halfS0_Pfiiiff +bar = 0 reg = 32 lmem=0 smem=0 +0xfffff389 0x000000ff 0x000e00ff 0x000fe200 +0xff017624 0x00000a00 0x078e00ff 0x000fd000 +0x01017810 0xfffffff8 0x07ffe0ff 0x000fc800 +0x01027a10 0x00000800 0x07f1e0ff 0x000fca00 +0xff007624 0x00000900 0x000e06ff 0x000fd000 +0x00037805 0x00000000 0x00005000 0x000fd000 +0x00077906 0x00000020 0x00209000 0x000e2400 +0x00077308 0x00000007 0x00001000 0x001e2200 +0x00067919 0x00000000 0x00002500 0x000e6200 +0x00097919 0x00000000 0x00002100 0x000e6200 +0x07087810 0x0ffffffe 0x07ffe0ff 0x001fcc00 +0x00057305 0x00000008 0x0021f000 0x0000a200 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0x06067a24 0x00000000 0x078e0209 0x002fe400 +0x050a7824 0xffffffe0 0x078e00ff 0x004fc800 +0x05047225 0x0000000a 0x078e0004 0x000fd000 +0x05047225 0x00000006 0x078e00ff 0x000fcc00 +0xff047224 0x000000ff 0x078e0a05 0x000fc800 +0x04067824 0x00000020 0x078e0206 0x000fca00 +0x0600780c 0x00000020 0x03f060f0 0x040fe200 +0x001c7919 0x00000000 0x00002600 0x000e2200 +0x00077919 0x00000000 0x00002200 0x000e3400 +0x06060810 0xffffffe0 0x07ffe0ff 0x000fc800 +0x0600780c 0x00000020 0x03f260f0 0x000fe400 +0x05050810 0x00000001 0x07ffe0ff 0x000fe400 +0xff007a0c 0x00006000 0x03f012f0 0x000fd000 +0x05051810 0x00000001 0x07ffe0ff 0x000fe200 +0x1c1c7a24 0x00000100 0x078e0207 0x001fc600 +0x051d7819 0x00000004 0x000006ff 0x000fe200 +0x1c1c7824 0x00000010 0x078e00ff 0x000fc600 +0x1d007a0c 0x00005e00 0x007012f0 0x000fc800 +0x1c007a0c 0x00005f00 0x007012f0 0x000fe200 +0x00007945 0x000003a0 0x03800000 0x000fe200 +0xff077224 0x000000ff 0x078e00ff 0x000fe200 +0x000b7202 0x000000ff 0x00000f00 0x000fe200 +0xff067224 0x000000ff 0x078e00ff 0x000fe400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff047224 0x000000ff 0x078e00ff 0x000fe400 +0xff0a7224 0x000000ff 0x078e00ff 0x000fc400 +0xff097224 0x000000ff 0x078e00ff 0x000fe400 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00008947 0x00000300 0x03800000 0x000fee00 +0x00067919 0x00000000 0x00000000 0x000e2200 +0xff0a7424 0x00000002 0x078e00ff 0x000fc800 +0x1d107625 0x00005800 0x078e020a 0x000fe200 +0xff047819 0x00000002 0x00011606 0x001fc800 +0x04057812 0x00000003 0x078ec0ff 0x000fe400 +0x06047812 0x00000003 0x078ec0ff 0x000fe400 +0x05077812 0x00000001 0x078ec0ff 0x000fe400 +0xff067819 0x00000004 0x00011606 0x000fe400 +0xff057819 0x00000001 0x00011605 0x000fe200 +0x07077824 0x00000008 0x078e0204 0x000fe200 +0x06067812 0x00000001 0x078ec0ff 0x000fc400 +0x05047211 0x00000004 0x078e18ff 0x000fe200 +0x1c0c7625 0x00005a00 0x078e020a 0x000fe400 +0x06077824 0x00000004 0x078e0207 0x040fe400 +0x06047824 0x00000004 0x078e0204 0x000fe400 +0x07077824 0x00000002 0x078e00ff 0x000fe400 +0x04057824 0x00000002 0x078e00ff 0x000fe400 +0x07107a25 0x00005e00 0x078e0010 0x000fc400 +0x050c7a25 0x00006000 0x078e000c 0x000fd000 +0x10187980 0x00000000 0x0010ed00 0x00006400 +0x0c147980 0x00000000 0x0010ed00 0x00046200 +0x10107980 0x00000010 0x0010ed00 0x001e2200 +0x0c0c7980 0x00000010 0x0010ed00 0x004e2200 +0xff087224 0x000000ff 0x078e00ff 0x000fe200 +0x00097202 0x000000ff 0x00000f00 0x000fe200 +0xff0a7224 0x000000ff 0x078e00ff 0x000fe400 +0xff0b7224 0x000000ff 0x078e00ff 0x000fe200 +0x00077202 0x000000ff 0x00000f00 0x000fe200 +0xff047224 0x000000ff 0x078e00ff 0x000fc400 +0xff057224 0x000000ff 0x078e00ff 0x000fe400 +0xff067224 0x000000ff 0x078e00ff 0x000fe200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x18087236 0x00000014 0x00005408 0x0c226400 +0x180a7236 0x00000014 0x0000d40a 0x0c04a400 +0x18047236 0x00000014 0x00015404 0x0c06e400 +0x18067236 0x00000014 0x0001d406 0x00092800 +0x1a087236 0x00000016 0x00005408 0x0c202400 +0x1a0a7236 0x00000016 0x0000d40a 0x0c426400 +0x1a047236 0x00000016 0x00015404 0x0c84a400 +0x1a067236 0x00000016 0x0001d406 0x0106e800 +0x10087236 0x0000000c 0x00005408 0x0c102400 +0x100a7236 0x0000000c 0x0000d40a 0x0c226400 +0x10047236 0x0000000c 0x00015404 0x0c44a400 +0x10067236 0x0000000c 0x0001d406 0x0086e800 +0x12087236 0x0000000e 0x00005408 0x0c102400 +0x120a7236 0x0000000e 0x0000d40a 0x0c202400 +0x12047236 0x0000000e 0x00015404 0x0c402400 +0x12067236 0x0000000e 0x0001d406 0x00803400 +0x00007941 0x00000000 0x03800000 0x001fea00 +0x000c7919 0x00000000 0x00000000 0x000e2200 +0x1c1c7a24 0x00005e00 0x078e02ff 0x000fe200 +0xff0e7819 0x00000004 0x0001160c 0x001fc400 +0xff0d7819 0x00000002 0x0001160c 0x000fe400 +0x0c0c7812 0x00000003 0x078ec0ff 0x000fe400 +0x0e0e7812 0x00000001 0x078ec0ff 0x000fe400 +0x0d0d7812 0x00000003 0x078ec0ff 0x000fc600 +0x0e0c7824 0x00000004 0x078e020c 0x000fe200 +0x0d0f7812 0x00000001 0x078ec0ff 0x000fe400 +0xff107819 0x00000001 0x0001160d 0x000fe400 +0x0c0d7812 0x00000005 0x078ec0ff 0x040fe400 +0x0c0e7812 0x00000002 0x078ec0ff 0x000fc600 +0x0f0c7824 0x00000008 0x078e020d 0x000fe200 +0xff0f7819 0x0000001f 0x0001141d 0x000fe200 +0x100e7824 0x00000008 0x078e020e 0x000fe200 +0x1d117210 0x0000001c 0x07f1e0ff 0x000fe200 +0xff0d7224 0x000000ff 0x078e00ff 0x000fc600 +0x1c0f7211 0x0000000f 0x000f0eff 0x000fe200 +0x0e0c7a25 0x00005e00 0x078e000c 0x000fe200 +0x110e7a11 0x00005c00 0x078010ff 0x000fe200 +0xff127624 0x00005e00 0x078e00ff 0x000fc600 +0x11117a11 0x00005d00 0x000f140f 0x000fe400 +0x0c107211 0x0000000e 0x078010ff 0x000fe400 +0x120e7819 0x00000002 0x000006ff 0x000fe400 +0xff0f7819 0x0000001e 0x00011612 0x000fe400 +0x0c0d7211 0x00000011 0x000f140d 0x000fe400 +0x0e127211 0x00000010 0x078210ff 0x000fc400 +0x0e117210 0x00000010 0x07f1e0ff 0x040fe400 +0x0e137211 0x0000000d 0x008f140f 0x040fe400 +0x0e157210 0x00000012 0x07f3e0ff 0x000fe200 +0x0f147824 0x00000001 0x000e060d 0x040fe400 +0xff0c7224 0x000000ff 0x078e0010 0x000fe400 +0x0f167824 0x00000001 0x008e0613 0x000fe400 +0xff0e7224 0x000000ff 0x078e0011 0x000fc400 +0xff0f7224 0x000000ff 0x078e0014 0x000fe200 +0x00107202 0x00000015 0x00000f00 0x000fe200 +0xff117224 0x000000ff 0x078e0016 0x000fe200 +0x0c007385 0x00000000 0x0010e908 0x0001e200 +0x0c007385 0x00000008 0x0010e90a 0x0003e800 +0x0e007385 0x00000000 0x0010e909 0x0003e200 +0x0e007385 0x00000008 0x0010e90b 0x0003e200 +0x12007385 0x00000000 0x0010e904 0x0003e200 +0x12007385 0x00000008 0x0010e906 0x0003e200 +0x10007385 0x00000000 0x0010e905 0x0003e200 +0x10007385 0x00000008 0x0010e907 0x0003e200 +0x00007948 0xffffffff 0x03800000 0x000fe200 +0x02087a10 0x80000800 0x07ffe0ff 0x001fd000 +0x00047805 0x00000000 0x00005000 0x002fd000 +0x04037824 0x00000001 0x078e0a03 0x000fd000 +0x08007387 0x00000003 0x00100800 0x0001e200 +0xff067224 0x000000ff 0x078e0002 0x000fe200 +0x00047802 0x00000000 0x00000f00 0x000fe200 +0xff077224 0x000000ff 0x078e0000 0x000fe200 +0x00057802 0x00000000 0x00000f00 0x000fe400 +0x00147802 0x00000000 0x00000f00 0x000fe400 +0x00157802 0x00000000 0x00000f00 0x000fd000 +0x00007943 0x00000000 0x03c00000 0x001fea00 +0x0000794d 0x00000000 0x03800000 0x000fea00 +0x00007947 0xfffffff0 0x0383ffff 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 +0x00007918 0x00000000 0x00000000 0x000fc000 + + +.section .rel.text._Z12wmma_exampleP6__halfS0_Pfiiiff REL +2272 $str R_CUDA_ABS32_LO_32 +2304 $str R_CUDA_ABS32_HI_32 +2352 vprintf R_CUDA_ABS47_34 + +.section .rela.text._Z12wmma_exampleP6__halfS0_Pfiiiff RELA +2320 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_LO_32 2368 +2336 _Z12wmma_exampleP6__halfS0_Pfiiiff R_CUDA_ABS32_HI_32 2368 + +.section .debug_frame +decodeDebugFrame, frameBuf 0xffffffff, total_length 224 +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x100 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 0 + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_advance_loc4 delta 52 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop +CIE length 40, cie_id -1 +version 3 +augmentation slen 1 +augmentation +code_align_factor slen 1 +data_align_factor slen 1 + Debug Frame Common Information Entry + length: 40 + CIE_id : -1 + version: 3 + augmentation: + code align factor: 4 + data align factor: -4 + return address register 16777215 + initial instructions: 23 bytes, ptr = 0x8080810c, frameBuf = 0xffffffff + DW_CFA_def_cfa register R1, offset 0 + DW_CFA_same_value R255 + DW_CFA_same_value R1 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + Debug Frame Description Entry + length: 48 + CIE_pointer: 0 + initial_location: 0x0 + address_range: 0x970 + instructions: 24 bytes + DW_CFA_advance_loc4 delta 4 + DW_CFA_advance_loc4 delta 2 + DW_CFA_def_cfa register R1, offset 8 + DW_CFA_advance_loc4 delta 586 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + +.section .rel.debug_frame REL +72 _Z17convertFp32ToFp16P6__halfPfi R_NV_64 +184 _Z12wmma_exampleP6__halfS0_Pfiiiff R_NV_64 + + code for sm_70 + Function : _Z17convertFp32ToFp16P6__halfPfi + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ MOV R1, c[0x0][0x28]; /* 0x00000a0000017a02 */ + /* 0x000fd00000000f00 */ + /*0020*/ S2R R4, SR_CTAID.X; /* 0x0000000000047919 */ + /* 0x000e220000002500 */ + /*0030*/ S2R R2, SR_TID.X; /* 0x0000000000027919 */ + /* 0x000e240000002100 */ + /*0040*/ IMAD R4, R4, c[0x0][0x0], R2; /* 0x0000000004047a24 */ + /* 0x001fca00078e0202 */ + /*0050*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT, !PT; /* 0x00005c0004007a0c */ + /* 0x000fd80003f062f0 */ + /*0060*/ @P0 EXIT; /* 0x000000000000094d */ + /* 0x000fea0003800000 */ + /*0070*/ MOV R2, 0x4; /* 0x0000000400027802 */ + /* 0x000fca0000000f00 */ + /*0080*/ IMAD.WIDE R2, R4, R2, c[0x0][0x168]; /* 0x00005a0004027625 */ + /* 0x000fd400078e0202 */ + /*0090*/ LDG.E.SYS R2, [R2]; /* 0x0000000002027381 */ + /* 0x000e2200001ee900 */ + /*00a0*/ MOV R5, 0x2; /* 0x0000000200057802 */ + /* 0x000fca0000000f00 */ + /*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160]; /* 0x0000580004047625 */ + /* 0x000fe200078e0205 */ + /*00c0*/ F2F.F16.F32 R6, R2; /* 0x0000000200067304 */ + /* 0x001e320000200800 */ + /*00d0*/ STG.E.U16.SYS [R4], R6; /* 0x0000000604007386 */ + /* 0x0011e2000010e500 */ + /*00e0*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + ........................................... + + + Function : _Z12wmma_exampleP6__halfS0_Pfiiiff + .headerflags @"EF_CUDA_SM70 EF_CUDA_PTX_SM(EF_CUDA_SM70)" + /*0000*/ @!PT SHFL.IDX PT, RZ, RZ, RZ, RZ; /* 0x000000fffffff389 */ + /* 0x000fe200000e00ff */ + /*0010*/ IMAD.U32 R1, RZ, RZ, c[0x0][0x28]; /* 0x00000a00ff017624 */ + /* 0x000fd000078e00ff */ + /*0020*/ IADD3 R1, R1, -0x8, RZ; /* 0xfffffff801017810 */ + /* 0x000fc80007ffe0ff */ + /*0030*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ; /* 0x0000080001027a10 */ + /* 0x000fca0007f1e0ff */ + /*0040*/ IMAD.X R0, RZ, RZ, c[0x0][0x24], P0; /* 0x00000900ff007624 */ + /* 0x000fd000000e06ff */ + /*0050*/ CS2R.32 R3, SR_CLOCKLO; /* 0x0000000000037805 */ + /* 0x000fd00000005000 */ + /*0060*/ I2F.U32.RP R7, 0x20; /* 0x0000002000077906 */ + /* 0x000e240000209000 */ + /*0070*/ MUFU.RCP R7, R7; /* 0x0000000700077308 */ + /* 0x001e220000001000 */ + /*0080*/ S2R R6, SR_CTAID.X; /* 0x0000000000067919 */ + /* 0x000e620000002500 */ + /*0090*/ S2R R9, SR_TID.X; /* 0x0000000000097919 */ + /* 0x000e620000002100 */ + /*00a0*/ IADD3 R8, R7, 0xffffffe, RZ; /* 0x0ffffffe07087810 */ + /* 0x001fcc0007ffe0ff */ + /*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R8; /* 0x0000000800057305 */ + /* 0x0000a2000021f000 */ + /*00c0*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*00d0*/ IMAD R6, R6, c[0x0][0x0], R9; /* 0x0000000006067a24 */ + /* 0x002fe400078e0209 */ + /*00e0*/ IMAD.U32 R10, R5, -0x20, RZ; /* 0xffffffe0050a7824 */ + /* 0x004fc800078e00ff */ + /*00f0*/ IMAD.WIDE.U32 R4, R5, R10, R4; /* 0x0000000a05047225 */ + /* 0x000fd000078e0004 */ + /*0100*/ IMAD.WIDE.U32 R4, R5, R6, RZ; /* 0x0000000605047225 */ + /* 0x000fcc00078e00ff */ + /*0110*/ IMAD R4, RZ, RZ, -R5; /* 0x000000ffff047224 */ + /* 0x000fc800078e0a05 */ + /*0120*/ IMAD R6, R4, 0x20, R6; /* 0x0000002004067824 */ + /* 0x000fca00078e0206 */ + /*0130*/ ISETP.GE.U32.AND P0, PT, R6.reuse, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x040fe20003f060f0 */ + /*0140*/ S2R R28, SR_CTAID.Y; /* 0x00000000001c7919 */ + /* 0x000e220000002600 */ + /*0150*/ S2R R7, SR_TID.Y; /* 0x0000000000077919 */ + /* 0x000e340000002200 */ + /*0160*/ @P0 IADD3 R6, R6, -0x20, RZ; /* 0xffffffe006060810 */ + /* 0x000fc80007ffe0ff */ + /*0170*/ ISETP.GE.U32.AND P1, PT, R6, 0x20, PT, !PT; /* 0x000000200600780c */ + /* 0x000fe40003f260f0 */ + /*0180*/ @P0 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105050810 */ + /* 0x000fe40007ffe0ff */ + /*0190*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT, !PT; /* 0x00006000ff007a0c */ + /* 0x000fd00003f012f0 */ + /*01a0*/ @P1 IADD3 R5, R5, 0x1, RZ; /* 0x0000000105051810 */ + /* 0x000fe20007ffe0ff */ + /*01b0*/ IMAD R28, R28, c[0x0][0x4], R7; /* 0x000001001c1c7a24 */ + /* 0x001fc600078e0207 */ + /*01c0*/ SHF.L.U32 R29, R5, 0x4, RZ; /* 0x00000004051d7819 */ + /* 0x000fe200000006ff */ + /*01d0*/ IMAD.U32 R28, R28, 0x10, RZ; /* 0x000000101c1c7824 */ + /* 0x000fc600078e00ff */ + /*01e0*/ ISETP.LT.AND P0, PT, R29, c[0x0][0x178], P0, !PT; /* 0x00005e001d007a0c */ + /* 0x000fc800007012f0 */ + /*01f0*/ ISETP.LT.AND P0, PT, R28, c[0x0][0x17c], P0, !PT; /* 0x00005f001c007a0c */ + /* 0x000fe200007012f0 */ + /*0200*/ BSSY B0, 0x5b0; /* 0x000003a000007945 */ + /* 0x000fe20003800000 */ + /*0210*/ IMAD.U32 R7, RZ, RZ, RZ; /* 0x000000ffff077224 */ + /* 0x000fe200078e00ff */ + /*0220*/ MOV R11, RZ; /* 0x000000ff000b7202 */ + /* 0x000fe20000000f00 */ + /*0230*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe400078e00ff */ + /*0240*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0250*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fe400078e00ff */ + /*0260*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fc400078e00ff */ + /*0270*/ IMAD.U32 R9, RZ, RZ, RZ; /* 0x000000ffff097224 */ + /* 0x000fe400078e00ff */ + /*0280*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0290*/ @!P0 BRA 0x5a0; /* 0x0000030000008947 */ + /* 0x000fee0003800000 */ + /*02a0*/ S2R R6, SR_LANEID; /* 0x0000000000067919 */ + /* 0x000e220000000000 */ + /*02b0*/ IMAD.U32 R10, RZ, RZ, 0x2; /* 0x00000002ff0a7424 */ + /* 0x000fc800078e00ff */ + /*02c0*/ IMAD.WIDE R16, R29, R10, c[0x0][0x160]; /* 0x000058001d107625 */ + /* 0x000fe200078e020a */ + /*02d0*/ SHF.R.U32.HI R4, RZ, 0x2, R6; /* 0x00000002ff047819 */ + /* 0x001fc80000011606 */ + /*02e0*/ LOP3.LUT R5, R4, 0x3, RZ, 0xc0, !PT; /* 0x0000000304057812 */ + /* 0x000fe400078ec0ff */ + /*02f0*/ LOP3.LUT R4, R6, 0x3, RZ, 0xc0, !PT; /* 0x0000000306047812 */ + /* 0x000fe400078ec0ff */ + /*0300*/ LOP3.LUT R7, R5, 0x1, RZ, 0xc0, !PT; /* 0x0000000105077812 */ + /* 0x000fe400078ec0ff */ + /*0310*/ SHF.R.U32.HI R6, RZ, 0x4, R6; /* 0x00000004ff067819 */ + /* 0x000fe40000011606 */ + /*0320*/ SHF.R.U32.HI R5, RZ, 0x1, R5; /* 0x00000001ff057819 */ + /* 0x000fe20000011605 */ + /*0330*/ IMAD R7, R7, 0x8, R4; /* 0x0000000807077824 */ + /* 0x000fe200078e0204 */ + /*0340*/ LOP3.LUT R6, R6, 0x1, RZ, 0xc0, !PT; /* 0x0000000106067812 */ + /* 0x000fc400078ec0ff */ + /*0350*/ LEA R4, R5, R4, 0x3; /* 0x0000000405047211 */ + /* 0x000fe200078e18ff */ + /*0360*/ IMAD.WIDE R12, R28, R10, c[0x0][0x168]; /* 0x00005a001c0c7625 */ + /* 0x000fe400078e020a */ + /*0370*/ IMAD R7, R6.reuse, 0x4, R7; /* 0x0000000406077824 */ + /* 0x040fe400078e0207 */ + /*0380*/ IMAD R4, R6, 0x4, R4; /* 0x0000000406047824 */ + /* 0x000fe400078e0204 */ + /*0390*/ IMAD.U32 R7, R7, 0x2, RZ; /* 0x0000000207077824 */ + /* 0x000fe400078e00ff */ + /*03a0*/ IMAD.U32 R5, R4, 0x2, RZ; /* 0x0000000204057824 */ + /* 0x000fe400078e00ff */ + /*03b0*/ IMAD.WIDE.U32 R16, R7, c[0x0][0x178], R16; /* 0x00005e0007107a25 */ + /* 0x000fc400078e0010 */ + /*03c0*/ IMAD.WIDE.U32 R12, R5, c[0x0][0x180], R12; /* 0x00006000050c7a25 */ + /* 0x000fd000078e000c */ + /*03d0*/ LD.E.128.SYS R24, [R16]; /* 0x0000000010187980 */ + /* 0x000064000010ed00 */ + /*03e0*/ LD.E.128.SYS R20, [R12]; /* 0x000000000c147980 */ + /* 0x000462000010ed00 */ + /*03f0*/ LD.E.128.SYS R16, [R16+0x10]; /* 0x0000001010107980 */ + /* 0x001e22000010ed00 */ + /*0400*/ LD.E.128.SYS R12, [R12+0x10]; /* 0x000000100c0c7980 */ + /* 0x004e22000010ed00 */ + /*0410*/ IMAD.U32 R8, RZ, RZ, RZ; /* 0x000000ffff087224 */ + /* 0x000fe200078e00ff */ + /*0420*/ MOV R9, RZ; /* 0x000000ff00097202 */ + /* 0x000fe20000000f00 */ + /*0430*/ IMAD.U32 R10, RZ, RZ, RZ; /* 0x000000ffff0a7224 */ + /* 0x000fe400078e00ff */ + /*0440*/ IMAD.U32 R11, RZ, RZ, RZ; /* 0x000000ffff0b7224 */ + /* 0x000fe200078e00ff */ + /*0450*/ MOV R7, RZ; /* 0x000000ff00077202 */ + /* 0x000fe20000000f00 */ + /*0460*/ IMAD.U32 R4, RZ, RZ, RZ; /* 0x000000ffff047224 */ + /* 0x000fc400078e00ff */ + /*0470*/ IMAD.U32 R5, RZ, RZ, RZ; /* 0x000000ffff057224 */ + /* 0x000fe400078e00ff */ + /*0480*/ IMAD.U32 R6, RZ, RZ, RZ; /* 0x000000ffff067224 */ + /* 0x000fe200078e00ff */ + /*0490*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*04a0*/ HMMA.884.F32.F32.STEP0 R8, R24.reuse, R20.reuse.T, R8; /* 0x0000001418087236 */ + /* 0x0c22640000005408 */ + /*04b0*/ HMMA.884.F32.F32.STEP1 R10, R24.reuse, R20.reuse.T, R10; /* 0x00000014180a7236 */ + /* 0x0c04a4000000d40a */ + /*04c0*/ HMMA.884.F32.F32.STEP2 R4, R24.reuse, R20.reuse.T, R4; /* 0x0000001418047236 */ + /* 0x0c06e40000015404 */ + /*04d0*/ HMMA.884.F32.F32.STEP3 R6, R24, R20.T, R6; /* 0x0000001418067236 */ + /* 0x000928000001d406 */ + /*04e0*/ HMMA.884.F32.F32.STEP0 R8, R26.reuse, R22.reuse.T, R8; /* 0x000000161a087236 */ + /* 0x0c20240000005408 */ + /*04f0*/ HMMA.884.F32.F32.STEP1 R10, R26.reuse, R22.reuse.T, R10; /* 0x000000161a0a7236 */ + /* 0x0c4264000000d40a */ + /*0500*/ HMMA.884.F32.F32.STEP2 R4, R26.reuse, R22.reuse.T, R4; /* 0x000000161a047236 */ + /* 0x0c84a40000015404 */ + /*0510*/ HMMA.884.F32.F32.STEP3 R6, R26, R22.T, R6; /* 0x000000161a067236 */ + /* 0x0106e8000001d406 */ + /*0520*/ HMMA.884.F32.F32.STEP0 R8, R16.reuse, R12.reuse.T, R8; /* 0x0000000c10087236 */ + /* 0x0c10240000005408 */ + /*0530*/ HMMA.884.F32.F32.STEP1 R10, R16.reuse, R12.reuse.T, R10; /* 0x0000000c100a7236 */ + /* 0x0c2264000000d40a */ + /*0540*/ HMMA.884.F32.F32.STEP2 R4, R16.reuse, R12.reuse.T, R4; /* 0x0000000c10047236 */ + /* 0x0c44a40000015404 */ + /*0550*/ HMMA.884.F32.F32.STEP3 R6, R16, R12.T, R6; /* 0x0000000c10067236 */ + /* 0x0086e8000001d406 */ + /*0560*/ HMMA.884.F32.F32.STEP0 R8, R18.reuse, R14.reuse.T, R8; /* 0x0000000e12087236 */ + /* 0x0c10240000005408 */ + /*0570*/ HMMA.884.F32.F32.STEP1 R10, R18.reuse, R14.reuse.T, R10; /* 0x0000000e120a7236 */ + /* 0x0c2024000000d40a */ + /*0580*/ HMMA.884.F32.F32.STEP2 R4, R18.reuse, R14.reuse.T, R4; /* 0x0000000e12047236 */ + /* 0x0c40240000015404 */ + /*0590*/ HMMA.884.F32.F32.STEP3 R6, R18, R14.T, R6; /* 0x0000000e12067236 */ + /* 0x008034000001d406 */ + /*05a0*/ BSYNC B0; /* 0x0000000000007941 */ + /* 0x001fea0003800000 */ + /*05b0*/ S2R R12, SR_LANEID; /* 0x00000000000c7919 */ + /* 0x000e220000000000 */ + /*05c0*/ IMAD R28, R28, c[0x0][0x178], RZ; /* 0x00005e001c1c7a24 */ + /* 0x000fe200078e02ff */ + /*05d0*/ SHF.R.U32.HI R14, RZ, 0x4, R12; /* 0x00000004ff0e7819 */ + /* 0x001fc4000001160c */ + /*05e0*/ SHF.R.U32.HI R13, RZ, 0x2, R12; /* 0x00000002ff0d7819 */ + /* 0x000fe4000001160c */ + /*05f0*/ LOP3.LUT R12, R12, 0x3, RZ, 0xc0, !PT; /* 0x000000030c0c7812 */ + /* 0x000fe400078ec0ff */ + /*0600*/ LOP3.LUT R14, R14, 0x1, RZ, 0xc0, !PT; /* 0x000000010e0e7812 */ + /* 0x000fe400078ec0ff */ + /*0610*/ LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT; /* 0x000000030d0d7812 */ + /* 0x000fc600078ec0ff */ + /*0620*/ IMAD R12, R14, 0x4, R12; /* 0x000000040e0c7824 */ + /* 0x000fe200078e020c */ + /*0630*/ LOP3.LUT R15, R13, 0x1, RZ, 0xc0, !PT; /* 0x000000010d0f7812 */ + /* 0x000fe400078ec0ff */ + /*0640*/ SHF.R.U32.HI R16, RZ, 0x1, R13; /* 0x00000001ff107819 */ + /* 0x000fe4000001160d */ + /*0650*/ LOP3.LUT R13, R12.reuse, 0x5, RZ, 0xc0, !PT; /* 0x000000050c0d7812 */ + /* 0x040fe400078ec0ff */ + /*0660*/ LOP3.LUT R14, R12, 0x2, RZ, 0xc0, !PT; /* 0x000000020c0e7812 */ + /* 0x000fc600078ec0ff */ + /*0670*/ IMAD R12, R15, 0x8, R13; /* 0x000000080f0c7824 */ + /* 0x000fe200078e020d */ + /*0680*/ SHF.R.S32.HI R15, RZ, 0x1f, R29; /* 0x0000001fff0f7819 */ + /* 0x000fe2000001141d */ + /*0690*/ IMAD R14, R16, 0x8, R14; /* 0x00000008100e7824 */ + /* 0x000fe200078e020e */ + /*06a0*/ IADD3 R17, P0, R29, R28, RZ; /* 0x0000001c1d117210 */ + /* 0x000fe20007f1e0ff */ + /*06b0*/ IMAD.U32 R13, RZ, RZ, RZ; /* 0x000000ffff0d7224 */ + /* 0x000fc600078e00ff */ + /*06c0*/ LEA.HI.X.SX32 R15, R28, R15, 0x1, P0; /* 0x0000000f1c0f7211 */ + /* 0x000fe200000f0eff */ + /*06d0*/ IMAD.WIDE.U32 R12, R14, c[0x0][0x178], R12; /* 0x00005e000e0c7a25 */ + /* 0x000fe200078e000c */ + /*06e0*/ LEA R14, P0, R17, c[0x0][0x170], 0x2; /* 0x00005c00110e7a11 */ + /* 0x000fe200078010ff */ + /*06f0*/ IMAD.U32 R18, RZ, RZ, c[0x0][0x178]; /* 0x00005e00ff127624 */ + /* 0x000fc600078e00ff */ + /*0700*/ LEA.HI.X R17, R17, c[0x0][0x174], R15, 0x2, P0; /* 0x00005d0011117a11 */ + /* 0x000fe400000f140f */ + /*0710*/ LEA R16, P0, R12, R14, 0x2; /* 0x0000000e0c107211 */ + /* 0x000fe400078010ff */ + /*0720*/ SHF.L.U32 R14, R18, 0x2, RZ; /* 0x00000002120e7819 */ + /* 0x000fe400000006ff */ + /*0730*/ SHF.R.U32.HI R15, RZ, 0x1e, R18; /* 0x0000001eff0f7819 */ + /* 0x000fe40000011612 */ + /*0740*/ LEA.HI.X R13, R12, R17, R13, 0x2, P0; /* 0x000000110c0d7211 */ + /* 0x000fe400000f140d */ + /*0750*/ LEA R18, P1, R14, R16, 0x2; /* 0x000000100e127211 */ + /* 0x000fc400078210ff */ + /*0760*/ IADD3 R17, P0, R14.reuse, R16, RZ; /* 0x000000100e117210 */ + /* 0x040fe40007f1e0ff */ + /*0770*/ LEA.HI.X R19, R14.reuse, R13, R15, 0x2, P1; /* 0x0000000d0e137211 */ + /* 0x040fe400008f140f */ + /*0780*/ IADD3 R21, P1, R14, R18, RZ; /* 0x000000120e157210 */ + /* 0x000fe20007f3e0ff */ + /*0790*/ IMAD.X R20, R15.reuse, 0x1, R13, P0; /* 0x000000010f147824 */ + /* 0x040fe400000e060d */ + /*07a0*/ IMAD.U32 R12, RZ, RZ, R16; /* 0x000000ffff0c7224 */ + /* 0x000fe400078e0010 */ + /*07b0*/ IMAD.X R22, R15, 0x1, R19, P1; /* 0x000000010f167824 */ + /* 0x000fe400008e0613 */ + /*07c0*/ IMAD.U32 R14, RZ, RZ, R17; /* 0x000000ffff0e7224 */ + /* 0x000fc400078e0011 */ + /*07d0*/ IMAD.U32 R15, RZ, RZ, R20; /* 0x000000ffff0f7224 */ + /* 0x000fe200078e0014 */ + /*07e0*/ MOV R16, R21; /* 0x0000001500107202 */ + /* 0x000fe20000000f00 */ + /*07f0*/ IMAD.U32 R17, RZ, RZ, R22; /* 0x000000ffff117224 */ + /* 0x000fe200078e0016 */ + /*0800*/ ST.E.SYS [R12], R8; /* 0x000000000c007385 */ + /* 0x0001e2000010e908 */ + /*0810*/ ST.E.SYS [R12+0x8], R10; /* 0x000000080c007385 */ + /* 0x0003e8000010e90a */ + /*0820*/ ST.E.SYS [R14], R9; /* 0x000000000e007385 */ + /* 0x0003e2000010e909 */ + /*0830*/ ST.E.SYS [R14+0x8], R11; /* 0x000000080e007385 */ + /* 0x0003e2000010e90b */ + /*0840*/ ST.E.SYS [R18], R4; /* 0x0000000012007385 */ + /* 0x0003e2000010e904 */ + /*0850*/ ST.E.SYS [R18+0x8], R6; /* 0x0000000812007385 */ + /* 0x0003e2000010e906 */ + /*0860*/ ST.E.SYS [R16], R5; /* 0x0000000010007385 */ + /* 0x0003e2000010e905 */ + /*0870*/ ST.E.SYS [R16+0x8], R7; /* 0x0000000810007385 */ + /* 0x0003e2000010e907 */ + /*0880*/ WARPSYNC 0xffffffff; /* 0xffffffff00007948 */ + /* 0x000fe20003800000 */ + /*0890*/ IADD3 R8, R2, -c[0x0][0x20], RZ; /* 0x8000080002087a10 */ + /* 0x001fd00007ffe0ff */ + /*08a0*/ CS2R.32 R4, SR_CLOCKLO; /* 0x0000000000047805 */ + /* 0x002fd00000005000 */ + /*08b0*/ IMAD R3, R4, 0x1, -R3; /* 0x0000000104037824 */ + /* 0x000fd000078e0a03 */ + /*08c0*/ STL [R8], R3; /* 0x0000000308007387 */ + /* 0x0001e20000100800 */ + /*08d0*/ IMAD.U32 R6, RZ, RZ, R2; /* 0x000000ffff067224 */ + /* 0x000fe200078e0002 */ + /*08e0*/ MOV R4, 0x0; /* 0x0000000000047802 */ + /* 0x000fe20000000f00 */ + /*08f0*/ IMAD.U32 R7, RZ, RZ, R0; /* 0x000000ffff077224 */ + /* 0x000fe200078e0000 */ + /*0900*/ MOV R5, 0x0; /* 0x0000000000057802 */ + /* 0x000fe40000000f00 */ + /*0910*/ MOV R20, 0x0; /* 0x0000000000147802 */ + /* 0x000fe40000000f00 */ + /*0920*/ MOV R21, 0x0; /* 0x0000000000157802 */ + /* 0x000fd00000000f00 */ + /*0930*/ CALL.ABS.NOINC 0x0; /* 0x0000000000007943 */ + /* 0x001fea0003c00000 */ + /*0940*/ EXIT; /* 0x000000000000794d */ + /* 0x000fea0003800000 */ + /*0950*/ BRA 0x950; /* 0xfffffff000007947 */ + /* 0x000fc0000383ffff */ + /*0960*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + /*0970*/ NOP; /* 0x0000000000007918 */ + /* 0x000fc00000000000 */ + ............................................. + + + +Fatbin ptx code: +================ +arch = sm_70 +code version = [6,0] +producer = cuda +host = linux +compile_size = 64bit +compressed + + + + + + + + +.version 6.0 +.target sm_70 +.address_size 64 + + +.extern .func (.param .b32 func_retval0) vprintf +( +.param .b64 vprintf_param_0, +.param .b64 vprintf_param_1 +) +; +.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0}; + +.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff( +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1, +.param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4, +.param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6, +.param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7 +) +{ +.local .align 8 .b8 __local_depot0[8]; +.reg .b64 %SP; +.reg .b64 %SPL; +.reg .pred %p<6>; +.reg .f32 %f<34>; +.reg .b32 %r<38>; +.reg .b64 %rd<18>; + + +mov.u64 %rd17, __local_depot0; +cvta.local.u64 %SP, %rd17; +ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0]; +ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1]; +ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2]; +ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3]; +ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4]; +ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5]; + + mov.u32 %r6, %clock; + + mov.u32 %r8, %ntid.x; +mov.u32 %r9, %ctaid.x; +mov.u32 %r10, %tid.x; +mad.lo.s32 %r11, %r8, %r9, %r10; +mov.u32 %r12, WARP_SZ; +div.u32 %r13, %r11, %r12; +mov.u32 %r14, %ntid.y; +mov.u32 %r15, %ctaid.y; +mov.u32 %r16, %tid.y; +mad.lo.s32 %r17, %r14, %r15, %r16; +shl.b32 %r2, %r13, 4; +shl.b32 %r3, %r17, 4; +setp.lt.s32 %p1, %r2, %r4; +setp.gt.s32 %p2, %r5, 0; +and.pred %p3, %p1, %p2; +setp.lt.s32 %p4, %r3, %r7; +and.pred %p5, %p3, %p4; +mov.f32 %f26, 0f00000000; +mov.f32 %f27, %f26; +mov.f32 %f28, %f26; +mov.f32 %f29, %f26; +mov.f32 %f30, %f26; +mov.f32 %f31, %f26; +mov.f32 %f32, %f26; +mov.f32 %f33, %f26; +@!%p5 bra BB0_2; +bra.uni BB0_1; + +BB0_1: +mul.wide.s32 %rd4, %r2, 2; +add.s64 %rd5, %rd1, %rd4; +wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4; +mul.wide.s32 %rd6, %r3, 2; +add.s64 %rd7, %rd2, %rd6; +wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5; +mov.f32 %f25, 0f00000000; +wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25}; + +BB0_2: +add.u64 %rd8, %SP, 0; +cvta.to.local.u64 %rd9, %rd8; +mul.lo.s32 %r35, %r3, %r4; +cvt.s64.s32 %rd10, %r35; +cvt.s64.s32 %rd11, %r2; +add.s64 %rd12, %rd10, %rd11; +shl.b64 %rd13, %rd12, 2; +add.s64 %rd14, %rd3, %rd13; +wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4; + + mov.u32 %r34, %clock; + + sub.s32 %r36, %r34, %r6; +st.local.u32 [%rd9], %r36; +mov.u64 %rd15, $str; +cvta.global.u64 %rd16, %rd15; + + { +.reg .b32 temp_param_reg; + + .param .b64 param0; +st.param.b64 [param0+0], %rd16; +.param .b64 param1; +st.param.b64 [param1+0], %rd8; +.param .b32 retval0; +call.uni (retval0), +vprintf, +( +param0, +param1 +); +ld.param.b32 %r37, [retval0+0]; + + + } + ret; +} + + +.visible .entry _Z17convertFp32ToFp16P6__halfPfi( +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0, +.param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1, +.param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2 +) +{ +.reg .pred %p<2>; +.reg .b16 %rs<2>; +.reg .f32 %f<2>; +.reg .b32 %r<6>; +.reg .b64 %rd<9>; + + +ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0]; +ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1]; +ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2]; +mov.u32 %r3, %ntid.x; +mov.u32 %r4, %ctaid.x; +mov.u32 %r5, %tid.x; +mad.lo.s32 %r1, %r4, %r3, %r5; +setp.ge.s32 %p1, %r1, %r2; +@%p1 bra BB1_2; + +cvta.to.global.u64 %rd3, %rd2; +mul.wide.s32 %rd4, %r1, 4; +add.s64 %rd5, %rd3, %rd4; +ld.global.f32 %f1, [%rd5]; + + { cvt.rn.f16.f32 %rs1, %f1;} + + + cvta.to.global.u64 %rd6, %rd1; +mul.wide.s32 %rd7, %r1, 2; +add.s64 %rd8, %rd6, %rd7; +st.global.u16 [%rd8], %rs1; + +BB1_2: +ret; +} + + diff --git a/cuda-kernels/config_fermi_islip.icnt b/cuda-kernels/config_fermi_islip.icnt new file mode 100755 index 0000000..a788090 --- /dev/null +++ b/cuda-kernels/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 62; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/cuda-kernels/gpgpu_inst_stats.txt b/cuda-kernels/gpgpu_inst_stats.txt new file mode 100755 index 0000000..acb1839 --- /dev/null +++ b/cuda-kernels/gpgpu_inst_stats.txt @@ -0,0 +1 @@ +kernel line : count latency dram_traffic smem_bk_conflicts smem_warp gmem_access_generated gmem_warp exposed_latency warp_divergence diff --git a/cuda-kernels/gpgpusim.config b/cuda-kernels/gpgpusim.config new file mode 100755 index 0000000..306d7f9 --- /dev/null +++ b/cuda-kernels/gpgpusim.config @@ -0,0 +1,149 @@ +# This config models the Pascal GP102 (GeForceGTX 1080Ti) + +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 70 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 40 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 11 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Pascal clock domains +#-gpgpu_clock_domains ::: +# Pascal NVIDIA TITAN X clock domains are adopted from +# https://en.wikipedia.org/wiki/GeForce_10_series +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 + +# shader core pipeline config +-gpgpu_shader_registers 65536 + +# This implies a maximum of 64 warps/SM +-gpgpu_shader_core_pipeline 2048:32 +-gpgpu_shader_cta 32 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +## Pascal GP102 has 4 SP SIMD units and 1 SFU unit +## we need to scale the number of pipeline registers to be equal to the number of SP units +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +# SFU is 32-width in pascal, then dp units initiation is 1 cycle +-ptx_opcode_latency_int 4,13,4,5,145,16,4 +-ptx_opcode_initiation_int 1,2,2,2,8,16,4 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 1,2,1,1,130 + +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +# Pascal GP102 has 96KB Shared memory +# Pascal GP102 has 64KB L1 cache +# The default is to disable the L1 cache, unless cache modifieres is used +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 +-gpgpu_shmem_size 98304 +-gmem_skip_L1D 1 + +# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4 +-gpgpu_cache:dl2_texture_only 0 + +# 4 KB Inst. +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +# 48 KB Tex +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +# 12 KB Const +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 + +# enable operand collector +## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units +-gpgpu_operand_collector_num_units_sp 20 +-gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_in_ports_sp 4 +-gpgpu_operand_collector_num_out_ports_sp 4 +-gpgpu_operand_collector_num_in_ports_sfu 1 +-gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_mem 1 +-gpgpu_operand_collector_num_out_ports_mem 1 +# gpgpu_num_reg_banks should be increased to 32, but it gives an error! +-gpgpu_num_reg_banks 32 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +## In Pascal, a warp scheduler can issue 2 insts per cycle +-gpgpu_max_insn_issue_per_warp 2 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 64 +-gpgpu_dram_return_queue_size 116 + +# for NVIDIA GeForceGTX 1080Ti, bus width is 352bits (11 DRAM chips x 32 bits) +# 11 memory paritions, 4 bytes (1 DRAM chip) per memory partition +# the atom size of GDDR5X (the smallest read request) is 32 bytes +-gpgpu_n_mem_per_ctrlr 1 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5X is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS + +# Use the same GDDR5 timing from hynix H5GQ1H24AFR +# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" + +# Pascal has four schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 + diff --git a/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log new file mode 100644 index 0000000..f754f0c --- /dev/null +++ b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-34-2018.log @@ -0,0 +1,324 @@ +kernel_name = +kernel_launch_uid = + +Kernel Average Power Data: +kernel_avg_power = 0 +gpu_avg_IBP, = -nan +gpu_avg_ICP, = -nan +gpu_avg_DCP, = -nan +gpu_avg_TCP, = -nan +gpu_avg_CCP, = -nan +gpu_avg_SHRDP, = -nan +gpu_avg_RFP, = -nan +gpu_avg_SPP, = -nan +gpu_avg_SFUP, = -nan +gpu_avg_FPUP, = -nan +gpu_avg_SCHEDP, = -nan +gpu_avg_L2CP, = -nan +gpu_avg_MCP, = -nan +gpu_avg_NOCP, = -nan +gpu_avg_DRAMP, = -nan +gpu_avg_PIPEP, = -nan +gpu_avg_IDLE_COREP, = -nan +gpu_avg_CONST_DYNAMICP = -nan +gpu_avg_TOT_INST, = -nan +gpu_avg_FP_INT, = -nan +gpu_avg_IC_H, = -nan +gpu_avg_IC_M, = -nan +gpu_avg_DC_RH, = -nan +gpu_avg_DC_RM, = -nan +gpu_avg_DC_WH, = -nan +gpu_avg_DC_WM, = -nan +gpu_avg_TC_H, = -nan +gpu_avg_TC_M, = -nan +gpu_avg_CC_H, = -nan +gpu_avg_CC_M, = -nan +gpu_avg_SHRD_ACC, = -nan +gpu_avg_REG_RD, = -nan +gpu_avg_REG_WR, = -nan +gpu_avg_NON_REG_OPs, = -nan +gpu_avg_SP_ACC, = -nan +gpu_avg_SFU_ACC, = -nan +gpu_avg_FPU_ACC, = -nan +gpu_avg_MEM_RD, = -nan +gpu_avg_MEM_WR, = -nan +gpu_avg_MEM_PRE, = -nan +gpu_avg_L2_RH, = -nan +gpu_avg_L2_RM, = -nan +gpu_avg_L2_WH, = -nan +gpu_avg_L2_WM, = -nan +gpu_avg_NOC_A, = -nan +gpu_avg_PIPE_A, = -nan +gpu_avg_IDLE_CORE_N, = -nan +gpu_avg_CONST_DYNAMICN = -nan + +Kernel Maximum Power Data: +kernel_max_power = 0 +gpu_max_IBP, = 0 +gpu_max_ICP, = 0 +gpu_max_DCP, = 0 +gpu_max_TCP, = 0 +gpu_max_CCP, = 0 +gpu_max_SHRDP, = 0 +gpu_max_RFP, = 0 +gpu_max_SPP, = 0 +gpu_max_SFUP, = 0 +gpu_max_FPUP, = 0 +gpu_max_SCHEDP, = 0 +gpu_max_L2CP, = 0 +gpu_max_MCP, = 0 +gpu_max_NOCP, = 0 +gpu_max_DRAMP, = 0 +gpu_max_PIPEP, = 0 +gpu_max_IDLE_COREP, = 0 +gpu_max_CONST_DYNAMICP = 0 +gpu_max_TOT_INST, = 0 +gpu_max_FP_INT, = 0 +gpu_max_IC_H, = 0 +gpu_max_IC_M, = 0 +gpu_max_DC_RH, = 0 +gpu_max_DC_RM, = 0 +gpu_max_DC_WH, = 0 +gpu_max_DC_WM, = 0 +gpu_max_TC_H, = 0 +gpu_max_TC_M, = 0 +gpu_max_CC_H, = 0 +gpu_max_CC_M, = 0 +gpu_max_SHRD_ACC, = 0 +gpu_max_REG_RD, = 0 +gpu_max_REG_WR, = 0 +gpu_max_NON_REG_OPs, = 0 +gpu_max_SP_ACC, = 0 +gpu_max_SFU_ACC, = 0 +gpu_max_FPU_ACC, = 0 +gpu_max_MEM_RD, = 0 +gpu_max_MEM_WR, = 0 +gpu_max_MEM_PRE, = 0 +gpu_max_L2_RH, = 0 +gpu_max_L2_RM, = 0 +gpu_max_L2_WH, = 0 +gpu_max_L2_WM, = 0 +gpu_max_NOC_A, = 0 +gpu_max_PIPE_A, = 0 +gpu_max_IDLE_CORE_N, = 0 +gpu_max_CONST_DYNAMICN = 0 + +Kernel Minimum Power Data: +kernel_min_power = 0 +gpu_min_IBP, = 0 +gpu_min_ICP, = 0 +gpu_min_DCP, = 0 +gpu_min_TCP, = 0 +gpu_min_CCP, = 0 +gpu_min_SHRDP, = 0 +gpu_min_RFP, = 0 +gpu_min_SPP, = 0 +gpu_min_SFUP, = 0 +gpu_min_FPUP, = 0 +gpu_min_SCHEDP, = 0 +gpu_min_L2CP, = 0 +gpu_min_MCP, = 0 +gpu_min_NOCP, = 0 +gpu_min_DRAMP, = 0 +gpu_min_PIPEP, = 0 +gpu_min_IDLE_COREP, = 0 +gpu_min_CONST_DYNAMICP = 0 +gpu_min_TOT_INST, = 0 +gpu_min_FP_INT, = 0 +gpu_min_IC_H, = 0 +gpu_min_IC_M, = 0 +gpu_min_DC_RH, = 0 +gpu_min_DC_RM, = 0 +gpu_min_DC_WH, = 0 +gpu_min_DC_WM, = 0 +gpu_min_TC_H, = 0 +gpu_min_TC_M, = 0 +gpu_min_CC_H, = 0 +gpu_min_CC_M, = 0 +gpu_min_SHRD_ACC, = 0 +gpu_min_REG_RD, = 0 +gpu_min_REG_WR, = 0 +gpu_min_NON_REG_OPs, = 0 +gpu_min_SP_ACC, = 0 +gpu_min_SFU_ACC, = 0 +gpu_min_FPU_ACC, = 0 +gpu_min_MEM_RD, = 0 +gpu_min_MEM_WR, = 0 +gpu_min_MEM_PRE, = 0 +gpu_min_L2_RH, = 0 +gpu_min_L2_RM, = 0 +gpu_min_L2_WH, = 0 +gpu_min_L2_WM, = 0 +gpu_min_NOC_A, = 0 +gpu_min_PIPE_A, = 0 +gpu_min_IDLE_CORE_N, = 0 +gpu_min_CONST_DYNAMICN = 0 + +Accumulative Power Statistics Over Previous Kernels: +gpu_tot_avg_power = -nan +gpu_tot_max_power = 0 +gpu_tot_min_power = 0 + + +kernel_name = +kernel_launch_uid = + +Kernel Average Power Data: +kernel_avg_power = 0 +gpu_avg_IBP, = -nan +gpu_avg_ICP, = -nan +gpu_avg_DCP, = -nan +gpu_avg_TCP, = -nan +gpu_avg_CCP, = -nan +gpu_avg_SHRDP, = -nan +gpu_avg_RFP, = -nan +gpu_avg_SPP, = -nan +gpu_avg_SFUP, = -nan +gpu_avg_FPUP, = -nan +gpu_avg_SCHEDP, = -nan +gpu_avg_L2CP, = -nan +gpu_avg_MCP, = -nan +gpu_avg_NOCP, = -nan +gpu_avg_DRAMP, = -nan +gpu_avg_PIPEP, = -nan +gpu_avg_IDLE_COREP, = -nan +gpu_avg_CONST_DYNAMICP = -nan +gpu_avg_TOT_INST, = -nan +gpu_avg_FP_INT, = -nan +gpu_avg_IC_H, = -nan +gpu_avg_IC_M, = -nan +gpu_avg_DC_RH, = -nan +gpu_avg_DC_RM, = -nan +gpu_avg_DC_WH, = -nan +gpu_avg_DC_WM, = -nan +gpu_avg_TC_H, = -nan +gpu_avg_TC_M, = -nan +gpu_avg_CC_H, = -nan +gpu_avg_CC_M, = -nan +gpu_avg_SHRD_ACC, = -nan +gpu_avg_REG_RD, = -nan +gpu_avg_REG_WR, = -nan +gpu_avg_NON_REG_OPs, = -nan +gpu_avg_SP_ACC, = -nan +gpu_avg_SFU_ACC, = -nan +gpu_avg_FPU_ACC, = -nan +gpu_avg_MEM_RD, = -nan +gpu_avg_MEM_WR, = -nan +gpu_avg_MEM_PRE, = -nan +gpu_avg_L2_RH, = -nan +gpu_avg_L2_RM, = -nan +gpu_avg_L2_WH, = -nan +gpu_avg_L2_WM, = -nan +gpu_avg_NOC_A, = -nan +gpu_avg_PIPE_A, = -nan +gpu_avg_IDLE_CORE_N, = -nan +gpu_avg_CONST_DYNAMICN = -nan + +Kernel Maximum Power Data: +kernel_max_power = 0 +gpu_max_IBP, = 0 +gpu_max_ICP, = 0 +gpu_max_DCP, = 0 +gpu_max_TCP, = 0 +gpu_max_CCP, = 0 +gpu_max_SHRDP, = 0 +gpu_max_RFP, = 0 +gpu_max_SPP, = 0 +gpu_max_SFUP, = 0 +gpu_max_FPUP, = 0 +gpu_max_SCHEDP, = 0 +gpu_max_L2CP, = 0 +gpu_max_MCP, = 0 +gpu_max_NOCP, = 0 +gpu_max_DRAMP, = 0 +gpu_max_PIPEP, = 0 +gpu_max_IDLE_COREP, = 0 +gpu_max_CONST_DYNAMICP = 0 +gpu_max_TOT_INST, = 0 +gpu_max_FP_INT, = 0 +gpu_max_IC_H, = 0 +gpu_max_IC_M, = 0 +gpu_max_DC_RH, = 0 +gpu_max_DC_RM, = 0 +gpu_max_DC_WH, = 0 +gpu_max_DC_WM, = 0 +gpu_max_TC_H, = 0 +gpu_max_TC_M, = 0 +gpu_max_CC_H, = 0 +gpu_max_CC_M, = 0 +gpu_max_SHRD_ACC, = 0 +gpu_max_REG_RD, = 0 +gpu_max_REG_WR, = 0 +gpu_max_NON_REG_OPs, = 0 +gpu_max_SP_ACC, = 0 +gpu_max_SFU_ACC, = 0 +gpu_max_FPU_ACC, = 0 +gpu_max_MEM_RD, = 0 +gpu_max_MEM_WR, = 0 +gpu_max_MEM_PRE, = 0 +gpu_max_L2_RH, = 0 +gpu_max_L2_RM, = 0 +gpu_max_L2_WH, = 0 +gpu_max_L2_WM, = 0 +gpu_max_NOC_A, = 0 +gpu_max_PIPE_A, = 0 +gpu_max_IDLE_CORE_N, = 0 +gpu_max_CONST_DYNAMICN = 0 + +Kernel Minimum Power Data: +kernel_min_power = 0 +gpu_min_IBP, = 0 +gpu_min_ICP, = 0 +gpu_min_DCP, = 0 +gpu_min_TCP, = 0 +gpu_min_CCP, = 0 +gpu_min_SHRDP, = 0 +gpu_min_RFP, = 0 +gpu_min_SPP, = 0 +gpu_min_SFUP, = 0 +gpu_min_FPUP, = 0 +gpu_min_SCHEDP, = 0 +gpu_min_L2CP, = 0 +gpu_min_MCP, = 0 +gpu_min_NOCP, = 0 +gpu_min_DRAMP, = 0 +gpu_min_PIPEP, = 0 +gpu_min_IDLE_COREP, = 0 +gpu_min_CONST_DYNAMICP = 0 +gpu_min_TOT_INST, = 0 +gpu_min_FP_INT, = 0 +gpu_min_IC_H, = 0 +gpu_min_IC_M, = 0 +gpu_min_DC_RH, = 0 +gpu_min_DC_RM, = 0 +gpu_min_DC_WH, = 0 +gpu_min_DC_WM, = 0 +gpu_min_TC_H, = 0 +gpu_min_TC_M, = 0 +gpu_min_CC_H, = 0 +gpu_min_CC_M, = 0 +gpu_min_SHRD_ACC, = 0 +gpu_min_REG_RD, = 0 +gpu_min_REG_WR, = 0 +gpu_min_NON_REG_OPs, = 0 +gpu_min_SP_ACC, = 0 +gpu_min_SFU_ACC, = 0 +gpu_min_FPU_ACC, = 0 +gpu_min_MEM_RD, = 0 +gpu_min_MEM_WR, = 0 +gpu_min_MEM_PRE, = 0 +gpu_min_L2_RH, = 0 +gpu_min_L2_RM, = 0 +gpu_min_L2_WH, = 0 +gpu_min_L2_WM, = 0 +gpu_min_NOC_A, = 0 +gpu_min_PIPE_A, = 0 +gpu_min_IDLE_CORE_N, = 0 +gpu_min_CONST_DYNAMICN = 0 + +Accumulative Power Statistics Over Previous Kernels: +gpu_tot_avg_power = -nan +gpu_tot_max_power = 0 +gpu_tot_min_power = 0 + + diff --git a/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log new file mode 100644 index 0000000..f754f0c --- /dev/null +++ b/cuda-kernels/gpgpusim_power_report__Sun-May-27-14-17-47-2018.log @@ -0,0 +1,324 @@ +kernel_name = +kernel_launch_uid = + +Kernel Average Power Data: +kernel_avg_power = 0 +gpu_avg_IBP, = -nan +gpu_avg_ICP, = -nan +gpu_avg_DCP, = -nan +gpu_avg_TCP, = -nan +gpu_avg_CCP, = -nan +gpu_avg_SHRDP, = -nan +gpu_avg_RFP, = -nan +gpu_avg_SPP, = -nan +gpu_avg_SFUP, = -nan +gpu_avg_FPUP, = -nan +gpu_avg_SCHEDP, = -nan +gpu_avg_L2CP, = -nan +gpu_avg_MCP, = -nan +gpu_avg_NOCP, = -nan +gpu_avg_DRAMP, = -nan +gpu_avg_PIPEP, = -nan +gpu_avg_IDLE_COREP, = -nan +gpu_avg_CONST_DYNAMICP = -nan +gpu_avg_TOT_INST, = -nan +gpu_avg_FP_INT, = -nan +gpu_avg_IC_H, = -nan +gpu_avg_IC_M, = -nan +gpu_avg_DC_RH, = -nan +gpu_avg_DC_RM, = -nan +gpu_avg_DC_WH, = -nan +gpu_avg_DC_WM, = -nan +gpu_avg_TC_H, = -nan +gpu_avg_TC_M, = -nan +gpu_avg_CC_H, = -nan +gpu_avg_CC_M, = -nan +gpu_avg_SHRD_ACC, = -nan +gpu_avg_REG_RD, = -nan +gpu_avg_REG_WR, = -nan +gpu_avg_NON_REG_OPs, = -nan +gpu_avg_SP_ACC, = -nan +gpu_avg_SFU_ACC, = -nan +gpu_avg_FPU_ACC, = -nan +gpu_avg_MEM_RD, = -nan +gpu_avg_MEM_WR, = -nan +gpu_avg_MEM_PRE, = -nan +gpu_avg_L2_RH, = -nan +gpu_avg_L2_RM, = -nan +gpu_avg_L2_WH, = -nan +gpu_avg_L2_WM, = -nan +gpu_avg_NOC_A, = -nan +gpu_avg_PIPE_A, = -nan +gpu_avg_IDLE_CORE_N, = -nan +gpu_avg_CONST_DYNAMICN = -nan + +Kernel Maximum Power Data: +kernel_max_power = 0 +gpu_max_IBP, = 0 +gpu_max_ICP, = 0 +gpu_max_DCP, = 0 +gpu_max_TCP, = 0 +gpu_max_CCP, = 0 +gpu_max_SHRDP, = 0 +gpu_max_RFP, = 0 +gpu_max_SPP, = 0 +gpu_max_SFUP, = 0 +gpu_max_FPUP, = 0 +gpu_max_SCHEDP, = 0 +gpu_max_L2CP, = 0 +gpu_max_MCP, = 0 +gpu_max_NOCP, = 0 +gpu_max_DRAMP, = 0 +gpu_max_PIPEP, = 0 +gpu_max_IDLE_COREP, = 0 +gpu_max_CONST_DYNAMICP = 0 +gpu_max_TOT_INST, = 0 +gpu_max_FP_INT, = 0 +gpu_max_IC_H, = 0 +gpu_max_IC_M, = 0 +gpu_max_DC_RH, = 0 +gpu_max_DC_RM, = 0 +gpu_max_DC_WH, = 0 +gpu_max_DC_WM, = 0 +gpu_max_TC_H, = 0 +gpu_max_TC_M, = 0 +gpu_max_CC_H, = 0 +gpu_max_CC_M, = 0 +gpu_max_SHRD_ACC, = 0 +gpu_max_REG_RD, = 0 +gpu_max_REG_WR, = 0 +gpu_max_NON_REG_OPs, = 0 +gpu_max_SP_ACC, = 0 +gpu_max_SFU_ACC, = 0 +gpu_max_FPU_ACC, = 0 +gpu_max_MEM_RD, = 0 +gpu_max_MEM_WR, = 0 +gpu_max_MEM_PRE, = 0 +gpu_max_L2_RH, = 0 +gpu_max_L2_RM, = 0 +gpu_max_L2_WH, = 0 +gpu_max_L2_WM, = 0 +gpu_max_NOC_A, = 0 +gpu_max_PIPE_A, = 0 +gpu_max_IDLE_CORE_N, = 0 +gpu_max_CONST_DYNAMICN = 0 + +Kernel Minimum Power Data: +kernel_min_power = 0 +gpu_min_IBP, = 0 +gpu_min_ICP, = 0 +gpu_min_DCP, = 0 +gpu_min_TCP, = 0 +gpu_min_CCP, = 0 +gpu_min_SHRDP, = 0 +gpu_min_RFP, = 0 +gpu_min_SPP, = 0 +gpu_min_SFUP, = 0 +gpu_min_FPUP, = 0 +gpu_min_SCHEDP, = 0 +gpu_min_L2CP, = 0 +gpu_min_MCP, = 0 +gpu_min_NOCP, = 0 +gpu_min_DRAMP, = 0 +gpu_min_PIPEP, = 0 +gpu_min_IDLE_COREP, = 0 +gpu_min_CONST_DYNAMICP = 0 +gpu_min_TOT_INST, = 0 +gpu_min_FP_INT, = 0 +gpu_min_IC_H, = 0 +gpu_min_IC_M, = 0 +gpu_min_DC_RH, = 0 +gpu_min_DC_RM, = 0 +gpu_min_DC_WH, = 0 +gpu_min_DC_WM, = 0 +gpu_min_TC_H, = 0 +gpu_min_TC_M, = 0 +gpu_min_CC_H, = 0 +gpu_min_CC_M, = 0 +gpu_min_SHRD_ACC, = 0 +gpu_min_REG_RD, = 0 +gpu_min_REG_WR, = 0 +gpu_min_NON_REG_OPs, = 0 +gpu_min_SP_ACC, = 0 +gpu_min_SFU_ACC, = 0 +gpu_min_FPU_ACC, = 0 +gpu_min_MEM_RD, = 0 +gpu_min_MEM_WR, = 0 +gpu_min_MEM_PRE, = 0 +gpu_min_L2_RH, = 0 +gpu_min_L2_RM, = 0 +gpu_min_L2_WH, = 0 +gpu_min_L2_WM, = 0 +gpu_min_NOC_A, = 0 +gpu_min_PIPE_A, = 0 +gpu_min_IDLE_CORE_N, = 0 +gpu_min_CONST_DYNAMICN = 0 + +Accumulative Power Statistics Over Previous Kernels: +gpu_tot_avg_power = -nan +gpu_tot_max_power = 0 +gpu_tot_min_power = 0 + + +kernel_name = +kernel_launch_uid = + +Kernel Average Power Data: +kernel_avg_power = 0 +gpu_avg_IBP, = -nan +gpu_avg_ICP, = -nan +gpu_avg_DCP, = -nan +gpu_avg_TCP, = -nan +gpu_avg_CCP, = -nan +gpu_avg_SHRDP, = -nan +gpu_avg_RFP, = -nan +gpu_avg_SPP, = -nan +gpu_avg_SFUP, = -nan +gpu_avg_FPUP, = -nan +gpu_avg_SCHEDP, = -nan +gpu_avg_L2CP, = -nan +gpu_avg_MCP, = -nan +gpu_avg_NOCP, = -nan +gpu_avg_DRAMP, = -nan +gpu_avg_PIPEP, = -nan +gpu_avg_IDLE_COREP, = -nan +gpu_avg_CONST_DYNAMICP = -nan +gpu_avg_TOT_INST, = -nan +gpu_avg_FP_INT, = -nan +gpu_avg_IC_H, = -nan +gpu_avg_IC_M, = -nan +gpu_avg_DC_RH, = -nan +gpu_avg_DC_RM, = -nan +gpu_avg_DC_WH, = -nan +gpu_avg_DC_WM, = -nan +gpu_avg_TC_H, = -nan +gpu_avg_TC_M, = -nan +gpu_avg_CC_H, = -nan +gpu_avg_CC_M, = -nan +gpu_avg_SHRD_ACC, = -nan +gpu_avg_REG_RD, = -nan +gpu_avg_REG_WR, = -nan +gpu_avg_NON_REG_OPs, = -nan +gpu_avg_SP_ACC, = -nan +gpu_avg_SFU_ACC, = -nan +gpu_avg_FPU_ACC, = -nan +gpu_avg_MEM_RD, = -nan +gpu_avg_MEM_WR, = -nan +gpu_avg_MEM_PRE, = -nan +gpu_avg_L2_RH, = -nan +gpu_avg_L2_RM, = -nan +gpu_avg_L2_WH, = -nan +gpu_avg_L2_WM, = -nan +gpu_avg_NOC_A, = -nan +gpu_avg_PIPE_A, = -nan +gpu_avg_IDLE_CORE_N, = -nan +gpu_avg_CONST_DYNAMICN = -nan + +Kernel Maximum Power Data: +kernel_max_power = 0 +gpu_max_IBP, = 0 +gpu_max_ICP, = 0 +gpu_max_DCP, = 0 +gpu_max_TCP, = 0 +gpu_max_CCP, = 0 +gpu_max_SHRDP, = 0 +gpu_max_RFP, = 0 +gpu_max_SPP, = 0 +gpu_max_SFUP, = 0 +gpu_max_FPUP, = 0 +gpu_max_SCHEDP, = 0 +gpu_max_L2CP, = 0 +gpu_max_MCP, = 0 +gpu_max_NOCP, = 0 +gpu_max_DRAMP, = 0 +gpu_max_PIPEP, = 0 +gpu_max_IDLE_COREP, = 0 +gpu_max_CONST_DYNAMICP = 0 +gpu_max_TOT_INST, = 0 +gpu_max_FP_INT, = 0 +gpu_max_IC_H, = 0 +gpu_max_IC_M, = 0 +gpu_max_DC_RH, = 0 +gpu_max_DC_RM, = 0 +gpu_max_DC_WH, = 0 +gpu_max_DC_WM, = 0 +gpu_max_TC_H, = 0 +gpu_max_TC_M, = 0 +gpu_max_CC_H, = 0 +gpu_max_CC_M, = 0 +gpu_max_SHRD_ACC, = 0 +gpu_max_REG_RD, = 0 +gpu_max_REG_WR, = 0 +gpu_max_NON_REG_OPs, = 0 +gpu_max_SP_ACC, = 0 +gpu_max_SFU_ACC, = 0 +gpu_max_FPU_ACC, = 0 +gpu_max_MEM_RD, = 0 +gpu_max_MEM_WR, = 0 +gpu_max_MEM_PRE, = 0 +gpu_max_L2_RH, = 0 +gpu_max_L2_RM, = 0 +gpu_max_L2_WH, = 0 +gpu_max_L2_WM, = 0 +gpu_max_NOC_A, = 0 +gpu_max_PIPE_A, = 0 +gpu_max_IDLE_CORE_N, = 0 +gpu_max_CONST_DYNAMICN = 0 + +Kernel Minimum Power Data: +kernel_min_power = 0 +gpu_min_IBP, = 0 +gpu_min_ICP, = 0 +gpu_min_DCP, = 0 +gpu_min_TCP, = 0 +gpu_min_CCP, = 0 +gpu_min_SHRDP, = 0 +gpu_min_RFP, = 0 +gpu_min_SPP, = 0 +gpu_min_SFUP, = 0 +gpu_min_FPUP, = 0 +gpu_min_SCHEDP, = 0 +gpu_min_L2CP, = 0 +gpu_min_MCP, = 0 +gpu_min_NOCP, = 0 +gpu_min_DRAMP, = 0 +gpu_min_PIPEP, = 0 +gpu_min_IDLE_COREP, = 0 +gpu_min_CONST_DYNAMICP = 0 +gpu_min_TOT_INST, = 0 +gpu_min_FP_INT, = 0 +gpu_min_IC_H, = 0 +gpu_min_IC_M, = 0 +gpu_min_DC_RH, = 0 +gpu_min_DC_RM, = 0 +gpu_min_DC_WH, = 0 +gpu_min_DC_WM, = 0 +gpu_min_TC_H, = 0 +gpu_min_TC_M, = 0 +gpu_min_CC_H, = 0 +gpu_min_CC_M, = 0 +gpu_min_SHRD_ACC, = 0 +gpu_min_REG_RD, = 0 +gpu_min_REG_WR, = 0 +gpu_min_NON_REG_OPs, = 0 +gpu_min_SP_ACC, = 0 +gpu_min_SFU_ACC, = 0 +gpu_min_FPU_ACC, = 0 +gpu_min_MEM_RD, = 0 +gpu_min_MEM_WR, = 0 +gpu_min_MEM_PRE, = 0 +gpu_min_L2_RH, = 0 +gpu_min_L2_RM, = 0 +gpu_min_L2_WH, = 0 +gpu_min_L2_WM, = 0 +gpu_min_NOC_A, = 0 +gpu_min_PIPE_A, = 0 +gpu_min_IDLE_CORE_N, = 0 +gpu_min_CONST_DYNAMICN = 0 + +Accumulative Power Statistics Over Previous Kernels: +gpu_tot_avg_power = -nan +gpu_tot_max_power = 0 +gpu_tot_min_power = 0 + + diff --git a/cuda-kernels/gpuwattch_gtx1080Ti.xml b/cuda-kernels/gpuwattch_gtx1080Ti.xml new file mode 100755 index 0000000..02619ff --- /dev/null +++ b/cuda-kernels/gpuwattch_gtx1080Ti.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/cuda-kernels/tensor_core b/cuda-kernels/tensor_core new file mode 100755 index 0000000..b25f3d9 Binary files /dev/null and b/cuda-kernels/tensor_core differ diff --git a/cuda-kernels/tensor_core.cu b/cuda-kernels/tensor_core.cu new file mode 100644 index 0000000..483a42b --- /dev/null +++ b/cuda-kernels/tensor_core.cu @@ -0,0 +1,250 @@ +/* Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of NVIDIA CORPORATION nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +// Define some error checking macros. +#define cudaErrCheck(stat) { cudaErrCheck_((stat), __FILE__, __LINE__); } +void cudaErrCheck_(cudaError_t stat, const char *file, int line) { + if (stat != cudaSuccess) { + fprintf(stderr, "CUDA Error: %s %s %d\n", cudaGetErrorString(stat), file, line); + } +} + + + + +#include +using namespace nvcuda; + +// Must be multiples of 16 for wmma code to work +#define MATRIX_M (16) +#define MATRIX_N (16) +#define MATRIX_K (16) + + + +// The only dimensions currently supported by WMMA +const int WMMA_M = 16; +const int WMMA_N = 16; +const int WMMA_K = 16; + + +// Performs an MxNxK GEMM (C=alpha*A*B + beta*C) assuming: +// 1) Matrices are packed in memory. +// 2) M, N and K are multiples of 16. +// 3) Neither A nor B are transposed. +// Note: This is NOT a high performance example but is for demonstration purposes only +// For a high performance code please use the GEMM provided in cuBLAS. +__global__ void wmma_example(half *a, half *b, float *c, int M, int N, int K, float alpha, float beta) { + unsigned int start_time=0,end_time=0; + // Leading dimensions. Packed with no transpositions. + start_time=clock(); + int lda = M; + int ldb = K; + int ldc = M; + + // Tile using a 2D grid/ + int warpM = (blockIdx.x * blockDim.x + threadIdx.x) / warpSize; + int warpN = (blockIdx.y * blockDim.y + threadIdx.y); + + // Declare the fragments + wmma::fragment a_frag; + wmma::fragment b_frag; + wmma::fragment acc_frag; + wmma::fragment c_frag; + + wmma::fill_fragment(c_frag, 0.0f); + + int i=0; + int aRow = warpM * WMMA_M; + int bCol = warpN * WMMA_N; + int aCol = i; + int bRow = i; + + + // Bounds checking + if (aRow < M && aCol < K && bRow < K && bCol < N) { + wmma::load_matrix_sync(a_frag, a+aRow+aCol*lda, lda); + wmma::load_matrix_sync(b_frag, b+bRow*ldb+bCol, ldb); + wmma::mma_sync(c_frag, a_frag, b_frag, c_frag); + //wmma::mma_sync(acc_frag, a_frag, b_frag, acc_frag); + } + int cRow = warpM * WMMA_M; + int cCol = warpN * WMMA_N; + wmma::store_matrix_sync(c + cRow + cCol * ldc, c_frag, ldc, wmma::mem_col_major); + end_time=clock(); + printf("clock=%d",end_time-start_time); +} + +__global__ void convertFp32ToFp16 (half *out, float *in, int n) { + int idx = blockDim.x * blockIdx.x + threadIdx.x; + if (idx < n) { + out[idx] = in[idx]; + } +} + +int main(int argc, char* argv[]) { + float *a_fp32; + float *b_fp32; + half *a_fp16; + half *b_fp16; + + float *c; + float *c_cublas; + float *c_wmma; + + float *c_host_cublas; + float *c_host_wmma; + float *a_host_wmma; + float *b_host_wmma; + float *c_init_host_wmma; + + + cudaEvent_t startWMMA; + cudaEvent_t stopWMMA; + + + cudaErrCheck(cudaEventCreate(&startWMMA)); + cudaErrCheck(cudaEventCreate(&stopWMMA)); + + + + + // Use tensor cores + + + cudaErrCheck(cudaMalloc((void**)&a_fp32, MATRIX_M * MATRIX_K * sizeof(float))); + cudaErrCheck(cudaMalloc((void**)&b_fp32, MATRIX_K * MATRIX_N * sizeof(float))); + cudaErrCheck(cudaMalloc((void**)&a_fp16, MATRIX_M * MATRIX_K * sizeof(half))); + cudaErrCheck(cudaMalloc((void**)&b_fp16, MATRIX_K * MATRIX_N * sizeof(half))); + + cudaErrCheck(cudaMalloc((void**)&c, MATRIX_M * MATRIX_N * sizeof(float))); + cudaErrCheck(cudaMalloc((void**)&c_wmma, MATRIX_M * MATRIX_N * sizeof(float))); + + c_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); + c_init_host_wmma = (float*)malloc(MATRIX_M * MATRIX_N * sizeof(float)); + a_host_wmma = (float*)malloc(MATRIX_M * MATRIX_K * sizeof(float)); + b_host_wmma = (float*)malloc(MATRIX_K * MATRIX_N * sizeof(float)); + + + +// printf("a_fp32\n"); + for(int m=0;m>> (a_fp16, a_fp32, MATRIX_M * MATRIX_K); + convertFp32ToFp16 <<< (MATRIX_K * MATRIX_N + 255) / 256, 256 >>> (b_fp16, b_fp32, MATRIX_K * MATRIX_N); + + for(int m=0;m>> (a_fp16, b_fp16, c_wmma, MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta); + // wmma_example <<< gridDim, blockDim >>> (a_fp16, b_fp16, c_wmma, MATRIX_M, MATRIX_N, MATRIX_K, alpha, beta); + cudaErrCheck(cudaEventRecord(stopWMMA)); + + + + + // Error checking + printf("\nChecking results...\n"); + cudaErrCheck(cudaMemcpy(c_host_wmma, c_wmma, MATRIX_M * MATRIX_N * sizeof(float), cudaMemcpyDeviceToHost)); + // printf("c_host\n"); + // for(int m=0;m{ +\.a\.sync TC; ptx_lval.int_value = LOAD_A; return WMMA_DIRECTIVE; +\.b\.sync TC; ptx_lval.int_value = LOAD_B; return WMMA_DIRECTIVE; +\.c\.sync TC; ptx_lval.int_value = LOAD_C; return WMMA_DIRECTIVE; +\.d\.sync TC; ptx_lval.int_value = STORE_D; return WMMA_DIRECTIVE; +\.sync TC;ptx_lval.int_value=MMA; return WMMA_DIRECTIVE; +\.row TC; ptx_lval.int_value = ROW; return LAYOUT; +\.col TC; ptx_lval.int_value = COL; return LAYOUT; +\.m16n16k16 TC; ptx_lval.int_value = M16N16K16; return CONFIGURATION; + \.align TC; return ALIGN_DIRECTIVE; \.branchtargets TC; return BRANCHTARGETS_DIRECTIVE; diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 3360c55..737657c 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -37,6 +37,9 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token STRING %token OPCODE +%token WMMA_DIRECTIVE +%token LAYOUT +%token CONFIGURATION %token ALIGN_DIRECTIVE %token BRANCHTARGETS_DIRECTIVE %token BYTE_DIRECTIVE @@ -428,6 +431,7 @@ option: type_spec | compare_spec | addressable_spec | rounding_mode + | wmma_spec | SYNC_OPTION { add_option(SYNC_OPTION); } | ARRIVE_OPTION { add_option(ARRIVE_OPTION); } | RED_OPTION { add_option(RED_OPTION); } @@ -483,6 +487,7 @@ atomic_operation_spec: ATOMIC_AND { add_option(ATOMIC_AND); } rounding_mode: floating_point_rounding_mode | integer_rounding_mode; + floating_point_rounding_mode: RN_OPTION { add_option(RN_OPTION); } | RZ_OPTION { add_option(RZ_OPTION); } | RM_OPTION { add_option(RM_OPTION); } @@ -515,6 +520,10 @@ compare_spec:EQ_OPTION { add_option(EQ_OPTION); } | NAN_OPTION { add_option(NAN_OPTION); } ; +wmma_spec: WMMA_DIRECTIVE LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2);add_wmma_option($3);} + | WMMA_DIRECTIVE LAYOUT LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2),add_wmma_option($3),add_wmma_option($4)} + ; + operand_list: operand | operand COMMA operand_list; @@ -543,6 +552,7 @@ operand: IDENTIFIER { add_scalar_operand( $1 ); } vector_operand: LEFT_BRACE IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_2vector_operand($2,$4); } | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_3vector_operand($2,$4,$6); } | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_4vector_operand($2,$4,$6,$8); } + | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_8vector_operand($2,$4,$6,$8,$10,$12,$14,$16); } | LEFT_BRACE IDENTIFIER RIGHT_BRACE { add_1vector_operand($2); } ; diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 8ebdcf8..9a4d8d3 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -995,7 +995,7 @@ static std::list check_operands( int opcode, const std::list &operands ) { static int g_warn_literal_operands_two_type_inst; - if( (opcode == CVT_OP) || (opcode == SET_OP) || (opcode == SLCT_OP) || (opcode == TEX_OP) ) { + if( (opcode == CVT_OP) || (opcode == SET_OP) || (opcode == SLCT_OP) || (opcode == TEX_OP) || (opcode==MMA_OP)) { // just make sure these do not have have const operands... if( !g_warn_literal_operands_two_type_inst ) { std::list::const_iterator o; @@ -1043,6 +1043,7 @@ ptx_instruction::ptx_instruction( int opcode, const std::list &operands, const operand_info &return_var, const std::list &options, + const std::list &wmma_options, const std::list &scalar_type, memory_space_t space_spec, const char *file, @@ -1061,6 +1062,7 @@ ptx_instruction::ptx_instruction( int opcode, m_operands.insert(m_operands.begin(), checked_operands.begin(), checked_operands.end() ); m_return_var = return_var; m_options = options; + m_wmma_options = wmma_options; m_wide = false; m_hi = false; m_lo = false; @@ -1078,7 +1080,7 @@ ptx_instruction::ptx_instruction( int opcode, m_atomic_spec = 0; m_membar_level = 0; m_inst_size = 8; // bytes - + int rr=0; std::list::const_iterator i; unsigned n=1; for ( i=options.begin(); i!= options.end(); i++, n++ ) { diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 0601b97..ff24a66 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -582,6 +582,34 @@ public: m_is_return_var = false; m_immediate_address=false; } + operand_info( const symbol *s1, const symbol *s2, const symbol *s3, const symbol *s4 ,const symbol *s5,const symbol *s6,const symbol *s7, const symbol *s8) + { + init(); + m_is_non_arch_reg = false; + m_addr_space = undefined_space; + m_operand_lohi = 0; + m_double_operand_type = 0; + m_operand_neg = false; + m_const_mem_offset = 0; + m_uid = get_uid(); + m_valid = true; + m_vector = true; + m_type = vector_t; + m_value.m_vector_symbolic = new const symbol*[8]; + m_value.m_vector_symbolic[0] = s1; + m_value.m_vector_symbolic[1] = s2; + m_value.m_vector_symbolic[2] = s3; + m_value.m_vector_symbolic[3] = s4; + m_value.m_vector_symbolic[4] = s5; + m_value.m_vector_symbolic[5] = s6; + m_value.m_vector_symbolic[6] = s7; + m_value.m_vector_symbolic[7] = s8; + m_addr_offset = 0; + m_neg_pred = false; + m_is_return_var = false; + m_immediate_address=false; + } + void init() { m_uid=(unsigned)-1; @@ -866,6 +894,7 @@ public: const std::list &operands, const operand_info &return_var, const std::list &options, + const std::list &wmma_options, const std::list &scalar_type, memory_space_t space_spec, const char *file, @@ -1087,6 +1116,7 @@ private: operand_info m_return_var; std::list m_options; + std::list m_wmma_options; bool m_wide; bool m_hi; bool m_lo; @@ -1096,6 +1126,9 @@ private: bool m_uni; //if branch instruction, this evaluates to true for uniform branches (ie jumps) bool m_to_option; unsigned m_cache_option; + unsigned m_wmma_type; + unsigned m_wmma_layout[2]; + unsigned m_wmma_configuration; unsigned m_rounding_mode; unsigned m_compare_op; unsigned m_saturation_mode; diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index 7fc54e9..6757091 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -72,6 +72,7 @@ symbol *g_label; int g_opcode = -1; std::list g_operands; std::list g_options; +std::list g_wmma_options; std::list g_scalar_type; #define PTX_PARSE_DPRINTF(...) \ @@ -162,6 +163,7 @@ void init_instruction_state() g_label = NULL; g_opcode = -1; g_options.clear(); + g_wmma_options.clear(); g_return_var = operand_info(); init_directive_state(); } @@ -300,6 +302,7 @@ void add_instruction() g_operands, g_return_var, g_options, + g_wmma_options, g_scalar_type, g_space_spec, g_filename, @@ -629,7 +632,7 @@ void add_scalar_type_spec( int type_spec ) g_scalar_type.push_back( type_spec ); if ( g_scalar_type.size() > 1 ) { parse_assert( (g_opcode == -1) || (g_opcode == CVT_OP) || (g_opcode == SET_OP) || (g_opcode == SLCT_OP) - || (g_opcode == TEX_OP), + || (g_opcode == TEX_OP)|| (g_opcode==MMA_OP), "only cvt, set, slct, and tex can have more than one type specifier."); } g_scalar_type_spec = type_spec; @@ -669,7 +672,11 @@ void add_option( int option ) PTX_PARSE_DPRINTF("add_option"); g_options.push_back( option ); } - +void add_wmma_option( int option ) +{ + PTX_PARSE_DPRINTF("add_option"); + g_wmma_options.push_back( option ); +} void add_double_operand( const char *d1, const char *d2 ) { //operands that access two variables. @@ -725,6 +732,28 @@ void add_4vector_operand( const char *d1, const char *d2, const char *d3, const if ( s4 == null_op ) s4 = NULL; g_operands.push_back( operand_info(s1,s2,s3,s4) ); } +void add_8vector_operand( const char *d1, const char *d2, const char *d3, const char *d4,const char *d5,const char *d6,const char *d7,const char *d8 ) +{ + PTX_PARSE_DPRINTF("add_8vector_operand"); + const symbol *s1 = g_current_symbol_table->lookup(d1); + const symbol *s2 = g_current_symbol_table->lookup(d2); + const symbol *s3 = g_current_symbol_table->lookup(d3); + const symbol *s4 = g_current_symbol_table->lookup(d4); + const symbol *s5 = g_current_symbol_table->lookup(d5); + const symbol *s6 = g_current_symbol_table->lookup(d6); + const symbol *s7 = g_current_symbol_table->lookup(d7); + const symbol *s8 = g_current_symbol_table->lookup(d8); + parse_assert( s1 != NULL && s2 != NULL && s3 != NULL && s4 != NULL && s5 !=NULL && s6 !=NULL && s7 !=NULL && s8 !=NULL, "v4 component(s) missing declarations."); + const symbol *null_op = g_current_symbol_table->lookup("_"); + if ( s2 == null_op ) s2 = NULL; + if ( s3 == null_op ) s3 = NULL; + if ( s4 == null_op ) s4 = NULL; + if ( s5 == null_op ) s5 = NULL; + if ( s6 == null_op ) s6 = NULL; + if ( s7 == null_op ) s7 = NULL; + if ( s8 == null_op ) s8 = NULL; + g_operands.push_back( operand_info(s1,s2,s3,s4,s5,s6,s7,s8) ); +} void add_builtin_operand( int builtin, int dim_modifier ) { diff --git a/src/cuda-sim/ptx_parser.h b/src/cuda-sim/ptx_parser.h index 32f3903..8094b43 100644 --- a/src/cuda-sim/ptx_parser.h +++ b/src/cuda-sim/ptx_parser.h @@ -57,7 +57,9 @@ void add_1vector_operand( const char *d1 ); void add_2vector_operand( const char *d1, const char *d2 ); void add_3vector_operand( const char *d1, const char *d2, const char *d3 ); void add_4vector_operand( const char *d1, const char *d2, const char *d3, const char *d4 ); +void add_8vector_operand( const char *d1, const char *d2, const char *d3, const char *d4 ,const char *d5,const char *d6,const char *d7,const char *d8); void add_option(int option ); +void add_wmma_option(int option ); void add_builtin_operand( int builtin, int dim_modifier ); void add_memory_operand( ); void add_literal_int( int value ); -- cgit v1.3 From 89177651e85312fbc841391121908a5e92280881 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Mon, 28 May 2018 14:40:19 -0700 Subject: better print statements for debugging stream_wait_event op --- src/stream_manager.cc | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 1b8ebb1..547e06b 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -188,16 +188,14 @@ bool stream_operation::do_operation( gpgpu_sim *gpu ) } break; case stream_event: { - if(g_debug_execution >= 3) - printf("event update\n"); + printf("event update\n"); time_t wallclock = time((time_t *)NULL); m_event->update( gpu_tot_sim_cycle, wallclock ); m_stream->record_next_done(); } break; case stream_wait_event: { - if(g_debug_execution >= 3) - printf("stream wait event\n"); + printf("stream wait event processing...\n"); if(m_event->done()) printf("stream wait event done\n"); m_stream->record_next_done(); -- cgit v1.3 From 21cce426d844c64dac5de7985b97857bb3724e88 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 29 May 2018 10:15:19 -0700 Subject: fixes seg fault on concurrentKernels, speeds up concurrent_streams_empty, adds check for null stream case on cudaStreamWaitEvent --- libcuda/cuda_runtime_api.cc | 4 ++++ src/gpgpusim_entrypoint.cc | 2 +- src/stream_manager.cc | 3 +++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index f130a37..33da17f 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1203,6 +1203,10 @@ __host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEven { CUevent_st *e = get_event(event); if( !e ) return g_last_cudaError = cudaErrorUnknown; + if (!stream){ + printf("GPGPU-Sim API: Warning: cudaStreamWaitEvent on NULL stream not currently supported.\n"); + return g_last_cudaError = cudaErrorInvalidValue; + } struct CUstream_st *s = (struct CUstream_st *)stream; stream_operation op(s,e,flags); g_stream_manager->push(op); diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index ede9f20..58d8c04 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -108,7 +108,7 @@ void *gpgpu_sim_thread_concurrent(void*) printf("GPGPU-Sim: *** simulation thread starting and spinning waiting for work ***\n"); fflush(stdout); } - while( g_stream_manager->empty() && !g_sim_done ) + while( g_stream_manager->empty_protected() && !g_sim_done ) ; if(g_debug_execution >= 3) { printf("GPGPU-Sim: ** START simulation thread (detected work) **\n"); diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 547e06b..697d6ec 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -375,6 +375,8 @@ void stream_manager::destroy_stream( CUstream_st *stream ) bool stream_manager::concurrent_streams_empty() { bool result = true; + if (m_streams.empty()) + return true; // called by gpu simulation thread std::list::iterator s; for( s=m_streams.begin(); s!=m_streams.end();++s ) { @@ -382,6 +384,7 @@ bool stream_manager::concurrent_streams_empty() if( !stream->empty() ) { //stream->print(stdout); result = false; + break; } } return result; -- cgit v1.3 From 4b19748d4b3f808d8a45039326673da8caf73186 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 29 May 2018 10:20:39 -0700 Subject: clarifying comments --- src/stream_manager.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 697d6ec..c6c17ac 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -195,6 +195,8 @@ bool stream_operation::do_operation( gpgpu_sim *gpu ) } break; case stream_wait_event: { + //only allows next op to go if event is done + //otherwise stays in the stream queue printf("stream wait event processing...\n"); if(m_event->done()) printf("stream wait event done\n"); -- cgit v1.3 From 80707e17c486f5628b280c3da7e84ba73f317157 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 29 May 2018 10:39:17 -0700 Subject: added must recordevent before waitevent call message --- libcuda/cuda_runtime_api.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 33da17f..b6fc6c8 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1202,9 +1202,12 @@ __host__ cudaError_t CUDARTAPI cudaEventRecord(cudaEvent_t event, cudaStream_t s __host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) { CUevent_st *e = get_event(event); - if( !e ) return g_last_cudaError = cudaErrorUnknown; + if( !e ){ + printf("GPGPU-Sim API: ERROR: Must call cudaEventRecord on event before calling cudaStreamWaitEvent.\n"); + return g_last_cudaError = cudaErrorInvalidValue; + } if (!stream){ - printf("GPGPU-Sim API: Warning: cudaStreamWaitEvent on NULL stream not currently supported.\n"); + printf("GPGPU-Sim API: ERROR: cudaStreamWaitEvent on NULL stream not currently supported.\n"); return g_last_cudaError = cudaErrorInvalidValue; } struct CUstream_st *s = (struct CUstream_st *)stream; -- cgit v1.3 From 99a7e032781ee2772cd86e4c1922851f101ec2c7 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Tue, 29 May 2018 11:40:51 -0700 Subject: implements null stream case on cudaStreamWaitEvent and updates warning on null event to reflect api reference --- libcuda/cuda_runtime_api.cc | 15 ++++++++------- src/stream_manager.cc | 7 +++++++ src/stream_manager.h | 1 + 3 files changed, 16 insertions(+), 7 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index b6fc6c8..dc92522 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1201,18 +1201,19 @@ __host__ cudaError_t CUDARTAPI cudaEventRecord(cudaEvent_t event, cudaStream_t s __host__ cudaError_t CUDARTAPI cudaStreamWaitEvent(cudaStream_t stream, cudaEvent_t event, unsigned int flags) { + //reference: https://www.cs.cmu.edu/afs/cs/academic/class/15668-s11/www/cuda-doc/html/group__CUDART__STREAM_gfe68d207dc965685d92d3f03d77b0876.html CUevent_st *e = get_event(event); if( !e ){ - printf("GPGPU-Sim API: ERROR: Must call cudaEventRecord on event before calling cudaStreamWaitEvent.\n"); - return g_last_cudaError = cudaErrorInvalidValue; + printf("GPGPU-Sim API: Warning: cudaEventRecord has not been called on event before calling cudaStreamWaitEvent.\nNothing to be done.\n"); + return g_last_cudaError = cudaSuccess; } if (!stream){ - printf("GPGPU-Sim API: ERROR: cudaStreamWaitEvent on NULL stream not currently supported.\n"); - return g_last_cudaError = cudaErrorInvalidValue; + g_stream_manager->pushCudaStreamWaitEventToAllStreams(e, flags); + } else { + struct CUstream_st *s = (struct CUstream_st *)stream; + stream_operation op(s,e,flags); + g_stream_manager->push(op); } - struct CUstream_st *s = (struct CUstream_st *)stream; - stream_operation op(s,e,flags); - g_stream_manager->push(op); return g_last_cudaError = cudaSuccess; } diff --git a/src/stream_manager.cc b/src/stream_manager.cc index c6c17ac..6cd62a2 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -478,3 +478,10 @@ void stream_manager::push( stream_operation op ) } } +void stream_manager::pushCudaStreamWaitEventToAllStreams( CUevent_st *e, unsigned int flags ){ + std::list::iterator s; + for( s=m_streams.begin(); s != m_streams.end(); s++ ) { + stream_operation op(*s,e,flags); + push(op); + } +} diff --git a/src/stream_manager.h b/src/stream_manager.h index edf2b24..1719ebd 100644 --- a/src/stream_manager.h +++ b/src/stream_manager.h @@ -255,6 +255,7 @@ public: bool empty(); void print( FILE *fp); void push( stream_operation op ); + void pushCudaStreamWaitEventToAllStreams( CUevent_st *e, unsigned int flags ); bool operation(bool * sim); void stop_all_running_kernels(); private: -- cgit v1.3 From 5b1ba75a3d5d02fbc12b5218abaaae4fcf2b5c2d Mon Sep 17 00:00:00 2001 From: aamir Date: Wed, 30 May 2018 17:34:14 -0700 Subject: changes for vector operands --- src/abstract_hardware_model.h | 2 +- src/cuda-sim/cuda-sim.cc | 24 +++++++++---- src/cuda-sim/instructions.cc | 80 +++++++++++++++++++++++++++++++++---------- src/cuda-sim/ptx_ir.h | 10 +++++- 4 files changed, 88 insertions(+), 28 deletions(-) diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 9dc58d4..e00c941 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -826,7 +826,7 @@ public: address_type reconvergence_pc; // -1 => not a branch, -2 => use function return address unsigned out[8]; - unsigned in[8]; + unsigned in[24]; unsigned char is_vectorin; unsigned char is_vectorout; int pred; // predicate register number diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 006738a..62077e6 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -852,8 +852,10 @@ void ptx_instruction::pre_decode() { pc = m_PC; isize = m_inst_size; - for( unsigned i=0; i<4; i++) { + for(unsigned i=0; i<8; i++) { out[i] = 0; + } + for(unsigned i=0; i<24; i++) { in[i] = 0; } is_vectorin = 0; @@ -922,6 +924,10 @@ void ptx_instruction::pre_decode() if( num_elem >= 2 ) out[1] = o.reg2_num(); if( num_elem >= 3 ) out[2] = o.reg3_num(); if( num_elem >= 4 ) out[3] = o.reg4_num(); + if( num_elem >= 5 ) out[4] = o.reg5_num(); + if( num_elem >= 6 ) out[5] = o.reg6_num(); + if( num_elem >= 7 ) out[6] = o.reg7_num(); + if( num_elem >= 8 ) out[7] = o.reg8_num(); for (int i = 0; i < num_elem; i++) arch_reg.dst[i] = o.arch_reg_num(i); } @@ -940,13 +946,17 @@ void ptx_instruction::pre_decode() //assert(m == 0); //only support 1 vector operand (for textures) right now is_vectorout = 1; unsigned num_elem = o.get_vect_nelem(); - if( num_elem >= 1 ) in[0] = o.reg1_num(); - if( num_elem >= 2 ) in[1] = o.reg2_num(); - if( num_elem >= 3 ) in[2] = o.reg3_num(); - if( num_elem >= 4 ) in[3] = o.reg4_num(); + if( num_elem >= 1 ) in[m+0] = o.reg1_num(); + if( num_elem >= 2 ) in[m+1] = o.reg2_num(); + if( num_elem >= 3 ) in[m+2] = o.reg3_num(); + if( num_elem >= 4 ) in[m+3] = o.reg4_num(); + if( num_elem >= 5 ) in[m+4] = o.reg5_num(); + if( num_elem >= 6 ) in[m+5] = o.reg6_num(); + if( num_elem >= 7 ) in[m+6] = o.reg7_num(); + if( num_elem >= 8 ) in[m+7] = o.reg8_num(); for (int i = 0; i < num_elem; i++) - arch_reg.src[i] = o.arch_reg_num(i); - m+=4; + arch_reg.src[m+i] = o.arch_reg_num(i); + m+=num_elem; } } } diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 7407269..446cdbf 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -748,7 +748,7 @@ void addp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) case U64_TYPE: data.s64 = src1_data.s64 + src2_data.s64 + (src3_data.pred & 0x4); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16=src1_data.f16+src2_data.f16; break;//assert(0); break; case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break; case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break; default: assert(0); break; @@ -826,7 +826,7 @@ void add_impl( const ptx_instruction *pI, ptx_thread_info *thread ) case U64_TYPE: data.u64 = src1_data.u64 + src2_data.u64; break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16=src1_data.f16+src2_data.f16; break;//assert(0); break; case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break; case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break; default: assert(0); break; @@ -1878,7 +1878,9 @@ ptx_reg_t f2x( ptx_reg_t x, unsigned from_width, unsigned to_width, int to_sign, } } else { switch ( to_width ) { - case 16: assert(0); break; + case 16: //assert(0); break; + y.f16 = x.f32; + break; case 32: assert(0); break; // handled by f2f case 64: y.f64 = x.f32; @@ -2140,7 +2142,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) case U32_TYPE: case U64_TYPE: printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16=truncf(data.f16);break;//assert(0); break; case F32_TYPE: data.f32 = truncf(data.f32); break; @@ -2163,7 +2165,13 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) case U32_TYPE: case U64_TYPE: printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE:// assert(0); break; +#if CUDART_VERSION >= 3000 + data.f16 = nearbyintf(data.f16); +#else + data.f16 = cuda_math::__cuda_nearbyintf(data.f16); +#endif + break; case F32_TYPE: #if CUDART_VERSION >= 3000 data.f32 = nearbyintf(data.f32); @@ -2186,7 +2194,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) case U32_TYPE: case U64_TYPE: printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16=floorf(data.f16);break;//assert(0); break; case F32_TYPE: data.f32 = floorf(data.f32); break; @@ -2205,7 +2213,7 @@ void ptx_round(ptx_reg_t& data, int rounding_mode, int type) case U32_TYPE: case U64_TYPE: printf("Trying to round an integer??\n"); assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16 = ceilf(data.f16); break; //assert(0); break; case F32_TYPE: data.f32 = ceilf(data.f32); break; case F64_TYPE: case FF64_TYPE: data.f64 = ceil(data.f64); break; default: assert(0); break; @@ -2246,7 +2254,10 @@ void ptx_saturate(ptx_reg_t& data, int saturation_mode, int type) case U32_TYPE: case U64_TYPE: printf("Trying to clamp an integer to 1??\n"); assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: //assert(0); break; + if (data.f16 > 1.0f) data.f16 = 1.0f; //negative + if (data.f16 < 0.0f) data.f16 = 0.0f; //positive + break; case F32_TYPE: if (data.f32 > 1.0f) data.f32 = 1.0f; //negative if (data.f32 < 0.0f) data.f32 = 0.0f; //positive @@ -2270,8 +2281,8 @@ void cvt_impl( const ptx_instruction *pI, ptx_thread_info *thread ) unsigned rounding_mode = pI->rounding_mode(); unsigned saturation_mode = pI->saturation_mode(); - if ( to_type == F16_TYPE || from_type == F16_TYPE ) - abort(); +// if ( to_type == F16_TYPE || from_type == F16_TYPE ) +// abort(); int to_sign, from_sign; size_t from_width, to_width; @@ -2406,7 +2417,7 @@ void div_impl( const ptx_instruction *pI, ptx_thread_info *thread ) data.u32 = src1_data.u32 / src2_data.u32; break; case B64_TYPE: data.u64 = src1_data.u64 / src2_data.u64; break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16 = src1_data.f16 / src2_data.f16; break;//assert(0); break; case F32_TYPE: data.f32 = src1_data.f32 / src2_data.f32; break; case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 / src2_data.f64; break; default: assert(0); break; @@ -2744,9 +2755,24 @@ void mad_def( const ptx_instruction *pI, ptx_thread_info *thread, bool use_carry if ( pI->is_lo() ) d.u64 = t.u64 + c.u64 + carry_bit.pred; else assert(0); break; - case F16_TYPE: - assert(0); - break; + case F16_TYPE:{ + // assert(0); + // break; + assert( use_carry == false); + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + d.f16 = a.f16 * b.f16 + c.f16; + if ( pI->saturation_mode() ) { + if ( d.f16 < 0 ) d.f16 = 0; + else if ( d.f16 > 1.0f ) d.f16 = 1.0f; + } + fesetround( orig_rm ); + break; + } case F32_TYPE: { assert( use_carry == false); int orig_rm = fegetround(); @@ -3046,9 +3072,25 @@ void mul_impl( const ptx_instruction *pI, ptx_thread_info *thread ) if ( pI->is_lo() ) d.u64 = t.u64; else assert(0); break; - case F16_TYPE: - assert(0); - break; + case F16_TYPE:{ + //assert(0); + //break; + int orig_rm = fegetround(); + switch ( rounding_mode ) { + case RN_OPTION: break; + case RZ_OPTION: fesetround( FE_TOWARDZERO ); break; + default: assert(0); break; + } + + d.f16 = a.f16 * b.f16; + + if ( pI->saturation_mode() ) { + if ( d.f16 < 0 ) d.f16 = 0; + else if ( d.f16 > 1.0f ) d.f16 = 1.0f; + } + fesetround( orig_rm ); + break; + } case F32_TYPE: { int orig_rm = fegetround(); switch ( rounding_mode ) { @@ -3111,7 +3153,7 @@ void neg_impl( const ptx_instruction *pI, ptx_thread_info *thread ) case U32_TYPE: case U64_TYPE: assert(0); break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16 =0.0f - src1_data.f16; break;//assert(0); break; case F32_TYPE: data.f32 = 0.0f - src1_data.f32; break; case F64_TYPE: case FF64_TYPE: data.f64 = 0.0f - src1_data.f64; break; default: assert(0); break; @@ -4165,7 +4207,7 @@ void sub_impl( const ptx_instruction *pI, ptx_thread_info *thread ) case B64_TYPE: case U64_TYPE: data.u64 = src1_data.u64 - src2_data.u64; break; - case F16_TYPE: assert(0); break; + case F16_TYPE: data.f16 = src1_data.f16 - src2_data.f16; break;//assert(0); break; case F32_TYPE: data.f32 = src1_data.f32 - src2_data.f32; break; case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 - src2_data.f64; break; default: assert(0); break; diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index ff24a66..833f175 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -656,7 +656,11 @@ public: if( !m_value.m_vector_symbolic[1] ) return 1; if( !m_value.m_vector_symbolic[2] ) return 2; if( !m_value.m_vector_symbolic[3] ) return 3; - return 4; + if( !m_value.m_vector_symbolic[4] ) return 4; + if( !m_value.m_vector_symbolic[5] ) return 5; + if( !m_value.m_vector_symbolic[6] ) return 6; + if( !m_value.m_vector_symbolic[7] ) return 7; + return 8; } const symbol* vec_symbol(int idx) const @@ -718,6 +722,10 @@ public: int reg2_num() const { return m_value.m_vector_symbolic[1]->reg_num();} int reg3_num() const { return m_value.m_vector_symbolic[2]?m_value.m_vector_symbolic[2]->reg_num():0; } int reg4_num() const { return m_value.m_vector_symbolic[3]?m_value.m_vector_symbolic[3]->reg_num():0; } + int reg5_num() const { return m_value.m_vector_symbolic[4]?m_value.m_vector_symbolic[4]->reg_num():0; } + int reg6_num() const { return m_value.m_vector_symbolic[5]?m_value.m_vector_symbolic[5]->reg_num():0; } + int reg7_num() const { return m_value.m_vector_symbolic[6]?m_value.m_vector_symbolic[6]->reg_num():0; } + int reg8_num() const { return m_value.m_vector_symbolic[7]?m_value.m_vector_symbolic[7]->reg_num():0; } int arch_reg_num() const { return m_value.m_symbolic->arch_reg_num(); } int arch_reg_num(unsigned n) const { return (m_value.m_vector_symbolic[n])? m_value.m_vector_symbolic[n]->arch_reg_num() : -1; } bool is_label() const { return m_type == label_t;} -- cgit v1.3 From fa0089a5d3a86ef348fae9a83a862f5219892bab Mon Sep 17 00:00:00 2001 From: aamir Date: Wed, 30 May 2018 23:07:44 -0700 Subject: adding code for wmma_ld_impl, error at decode space --- cuda-kernels/.tensor_core_ptx.swp | Bin 0 -> 16384 bytes cuda-kernels/Makefile | 3 +- cuda-kernels/tensor_core | Bin 48541 -> 2750968 bytes cuda-kernels/tensor_core_ptx | 171 +++++++++++ src/Makefile | 2 +- src/cuda-sim/.ptx.y.swp | Bin 0 -> 36864 bytes src/cuda-sim/Makefile | 2 +- src/cuda-sim/instructions.cc | 72 ++++- src/cuda-sim/ptx.y~ | 608 ++++++++++++++++++++++++++++++++++++++ src/cuda-sim/ptx_ir.h | 4 +- src/cuda-sim/ptx_sim.h | 9 + src/gpgpu-sim/Makefile | 2 +- src/intersim2/Makefile | 2 +- 13 files changed, 865 insertions(+), 10 deletions(-) create mode 100644 cuda-kernels/.tensor_core_ptx.swp create mode 100644 cuda-kernels/tensor_core_ptx create mode 100644 src/cuda-sim/.ptx.y.swp create mode 100644 src/cuda-sim/ptx.y~ diff --git a/cuda-kernels/.tensor_core_ptx.swp b/cuda-kernels/.tensor_core_ptx.swp new file mode 100644 index 0000000..6d7bad4 Binary files /dev/null and b/cuda-kernels/.tensor_core_ptx.swp differ diff --git a/cuda-kernels/Makefile b/cuda-kernels/Makefile index 51a7760..673460f 100755 --- a/cuda-kernels/Makefile +++ b/cuda-kernels/Makefile @@ -1,5 +1,6 @@ all: tensor_core.cu - nvcc -arch=sm_70 -lcudart -g -o tensor_core tensor_core.cu + nvcc --gpu-architecture=compute_70 --gpu-code=compute_70 -lcudart -g -o tensor_core tensor_core.cu +# nvcc -arch=sm_70 -lcudart -g -o tensor_core tensor_core.cu .PHONY: clean: diff --git a/cuda-kernels/tensor_core b/cuda-kernels/tensor_core index b25f3d9..cb53851 100755 Binary files a/cuda-kernels/tensor_core and b/cuda-kernels/tensor_core differ diff --git a/cuda-kernels/tensor_core_ptx b/cuda-kernels/tensor_core_ptx new file mode 100644 index 0000000..36074cb --- /dev/null +++ b/cuda-kernels/tensor_core_ptx @@ -0,0 +1,171 @@ +// +// Generated by NVIDIA NVVM Compiler +// +// Compiler Build ID: CL-22781540 +// Cuda compilation tools, release 9.0, V9.0.176 +// Based on LLVM 3.4svn +// + +.version 6.0 +.target sm_70 +.address_size 64 + + // .globl _Z12wmma_exampleP6__halfS0_Pfiiiff +.extern .func (.param .b32 func_retval0) vprintf +( + .param .b64 vprintf_param_0, + .param .b64 vprintf_param_1 +) +; +.global .align 16 .b8 $str[9] = {99, 108, 111, 99, 107, 61, 37, 100, 0}; + +.visible .entry _Z12wmma_exampleP6__halfS0_Pfiiiff( + .param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_0, + .param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_1, + .param .u64 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_2, + .param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_3, + .param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_4, + .param .u32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_5, + .param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_6, + .param .f32 _Z12wmma_exampleP6__halfS0_Pfiiiff_param_7 +) +{ + .local .align 8 .b8 __local_depot0[8]; + .reg .b64 %SP; + .reg .b64 %SPL; + .reg .pred %p<6>; + .reg .f32 %f<34>; + .reg .b32 %r<38>; + .reg .b64 %rd<18>; + + + mov.u64 %rd17, __local_depot0; + cvta.local.u64 %SP, %rd17; + ld.param.u64 %rd1, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0]; + ld.param.u64 %rd2, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1]; + ld.param.u64 %rd3, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2]; + ld.param.u32 %r4, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3]; + ld.param.u32 %r7, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4]; + ld.param.u32 %r5, [_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5]; + // inline asm + mov.u32 %r6, %clock; + // inline asm + mov.u32 %r8, %ntid.x; + mov.u32 %r9, %ctaid.x; + mov.u32 %r10, %tid.x; + mad.lo.s32 %r11, %r8, %r9, %r10; + mov.u32 %r12, WARP_SZ; + div.u32 %r13, %r11, %r12; + mov.u32 %r14, %ntid.y; + mov.u32 %r15, %ctaid.y; + mov.u32 %r16, %tid.y; + mad.lo.s32 %r17, %r14, %r15, %r16; + shl.b32 %r2, %r13, 4; + shl.b32 %r3, %r17, 4; + setp.lt.s32 %p1, %r2, %r4; + setp.gt.s32 %p2, %r5, 0; + and.pred %p3, %p1, %p2; + setp.lt.s32 %p4, %r3, %r7; + and.pred %p5, %p3, %p4; + mov.f32 %f26, 0f00000000; + mov.f32 %f27, %f26; + mov.f32 %f28, %f26; + mov.f32 %f29, %f26; + mov.f32 %f30, %f26; + mov.f32 %f31, %f26; + mov.f32 %f32, %f26; + mov.f32 %f33, %f26; + @!%p5 bra BB0_2; + bra.uni BB0_1; + +BB0_1: + mul.wide.s32 %rd4, %r2, 2; + add.s64 %rd5, %rd1, %rd4; + wmma.load.a.sync.row.m16n16k16.f16 {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, [%rd5], %r4; + mul.wide.s32 %rd6, %r3, 2; + add.s64 %rd7, %rd2, %rd6; + wmma.load.b.sync.col.m16n16k16.f16 {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, [%rd7], %r5; + mov.f32 %f25, 0f00000000; + wmma.mma.sync.row.col.m16n16k16.f32.f32 {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, {%r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25}, {%r26, %r27, %r28, %r29, %r30, %r31, %r32, %r33}, {%f25, %f25, %f25, %f25, %f25, %f25, %f25, %f25}; + +BB0_2: + add.u64 %rd8, %SP, 0; + cvta.to.local.u64 %rd9, %rd8; + mul.lo.s32 %r35, %r3, %r4; + cvt.s64.s32 %rd10, %r35; + cvt.s64.s32 %rd11, %r2; + add.s64 %rd12, %rd10, %rd11; + shl.b64 %rd13, %rd12, 2; + add.s64 %rd14, %rd3, %rd13; + wmma.store.d.sync.col.m16n16k16.f32 [%rd14], {%f33, %f32, %f31, %f30, %f29, %f28, %f27, %f26}, %r4; + // inline asm + mov.u32 %r34, %clock; + // inline asm + sub.s32 %r36, %r34, %r6; + st.local.u32 [%rd9], %r36; + mov.u64 %rd15, $str; + cvta.global.u64 %rd16, %rd15; + // Callseq Start 0 + { + .reg .b32 temp_param_reg; + // } + .param .b64 param0; + st.param.b64 [param0+0], %rd16; + .param .b64 param1; + st.param.b64 [param1+0], %rd8; + .param .b32 retval0; + call.uni (retval0), + vprintf, + ( + param0, + param1 + ); + ld.param.b32 %r37, [retval0+0]; + + //{ + }// Callseq End 0 + ret; +} + + // .globl _Z17convertFp32ToFp16P6__halfPfi +.visible .entry _Z17convertFp32ToFp16P6__halfPfi( + .param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_0, + .param .u64 _Z17convertFp32ToFp16P6__halfPfi_param_1, + .param .u32 _Z17convertFp32ToFp16P6__halfPfi_param_2 +) +{ + .reg .pred %p<2>; + .reg .b16 %rs<2>; + .reg .f32 %f<2>; + .reg .b32 %r<6>; + .reg .b64 %rd<9>; + + + ld.param.u64 %rd1, [_Z17convertFp32ToFp16P6__halfPfi_param_0]; + ld.param.u64 %rd2, [_Z17convertFp32ToFp16P6__halfPfi_param_1]; + ld.param.u32 %r2, [_Z17convertFp32ToFp16P6__halfPfi_param_2]; + mov.u32 %r3, %ntid.x; + mov.u32 %r4, %ctaid.x; + mov.u32 %r5, %tid.x; + mad.lo.s32 %r1, %r4, %r3, %r5; + setp.ge.s32 %p1, %r1, %r2; + @%p1 bra BB1_2; + + cvta.to.global.u64 %rd3, %rd2; + mul.wide.s32 %rd4, %r1, 4; + add.s64 %rd5, %rd3, %rd4; + ld.global.f32 %f1, [%rd5]; + // inline asm + { cvt.rn.f16.f32 %rs1, %f1;} + + // inline asm + cvta.to.global.u64 %rd6, %rd1; + mul.wide.s32 %rd7, %r1, 2; + add.s64 %rd8, %rd6, %rd7; + st.global.u16 [%rd8], %rs1; + +BB1_2: + ret; +} + + diff --git a/src/Makefile b/src/Makefile index 6001669..09194f3 100644 --- a/src/Makefile +++ b/src/Makefile @@ -46,7 +46,7 @@ ifeq ($(TRACE),1) endif ifneq ($(DEBUG),1) - OPTFLAGS += -O3 + OPTFLAGS += -O0 else CXXFLAGS += endif diff --git a/src/cuda-sim/.ptx.y.swp b/src/cuda-sim/.ptx.y.swp new file mode 100644 index 0000000..c8a83b5 Binary files /dev/null and b/src/cuda-sim/.ptx.y.swp differ diff --git a/src/cuda-sim/Makefile b/src/cuda-sim/Makefile index 999dad7..a65e8e1 100644 --- a/src/cuda-sim/Makefile +++ b/src/cuda-sim/Makefile @@ -42,7 +42,7 @@ include ../../version_detection.mk OUTPUT_DIR=$(SIM_OBJ_FILES_DIR)/cuda-sim -OPT := -O3 -g3 -Wall -Wno-unused-function -Wno-sign-compare +OPT := -O0 -g3 -Wall -Wno-unused-function -Wno-sign-compare ifeq ($(DEBUG),1) OPT := -g3 -Wall -Wno-unused-function -Wno-sign-compare endif diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index 446cdbf..16f33c6 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -643,6 +643,33 @@ void ptx_thread_info::set_vector_operand_values( const operand_info &dst, m_last_set_operand_value = data1; } +void ptx_thread_info::set_wmma_vector_operand_values( const operand_info &dst, + const ptx_reg_t &data1, + const ptx_reg_t &data2, + const ptx_reg_t &data3, + const ptx_reg_t &data4, + const ptx_reg_t &data5, + const ptx_reg_t &data6, + const ptx_reg_t &data7, + const ptx_reg_t &data8 ) +{ + unsigned num_elements = dst.get_vect_nelem(); + if (num_elements > 7) { + set_reg(dst.vec_symbol(0), data1); + set_reg(dst.vec_symbol(1), data2); + set_reg(dst.vec_symbol(2), data3); + set_reg(dst.vec_symbol(3), data4); + set_reg(dst.vec_symbol(4), data5); + set_reg(dst.vec_symbol(5), data6); + set_reg(dst.vec_symbol(6), data7); + set_reg(dst.vec_symbol(7), data8); + } + else{ + printf("error:set_wmma_vector_operands"); + } + + m_last_set_operand_value = data1; +} #define my_abs(a) (((a)<0)?(-a):(a)) @@ -1493,9 +1520,6 @@ unsigned trunc(unsigned num, unsigned precision) { } return num; } -void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) -{ -} void mma_st_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) { } @@ -2595,6 +2619,48 @@ void ldu_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { ld_exec(pI,thread); } +void mma_ld_impl( const ptx_instruction *pI, core_t *core, warp_inst_t inst ) +{ + const operand_info &dst = pI->dst(); + const operand_info &src1 = pI->src1(); + const operand_info &src2 = pI->src2(); + + unsigned type = pI->get_type(); + + int tid = inst.warp_id_func() * core->get_warp_size(); + int thrd; + ptx_thread_info *thread; + thread = core->get_thread_info()[tid]; + + ptx_reg_t src1_data = thread->get_operand_value(src1, dst, type, thread, 1); + + ptx_reg_t data; + memory_space_t space = pI->get_space(); + + memory_space *mem = NULL; + addr_t addr = src1_data.u32; + + decode_space(space,thread,src1,mem,addr); + + size_t size; + int t; + data.u64=0; + type_info_key::type_decode(type,size,t); + ptx_reg_t data1, data2, data3, data4; + ptx_reg_t data5, data6, data7, data8; + mem->read(addr,size/8,&data1.s64); + mem->read(addr+size/8,size/8,&data2.s64); + mem->read(addr+2*size/8,size/8,&data3.s64); + mem->read(addr+3*size/8,size/8,&data4.s64); + mem->read(addr+4*size/8,size/8,&data5.s64); + mem->read(addr+5*size/8,size/8,&data6.s64); + mem->read(addr+6*size/8,size/8,&data7.s64); + mem->read(addr+7*size/8,size/8,&data8.s64); + thread->set_wmma_vector_operand_values(dst,data1,data2,data3,data4,data5,data6,data7,data8); + + thread->m_last_effective_address = addr; + thread->m_last_memory_space = space; +} void lg2_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { diff --git a/src/cuda-sim/ptx.y~ b/src/cuda-sim/ptx.y~ new file mode 100644 index 0000000..0710ecd --- /dev/null +++ b/src/cuda-sim/ptx.y~ @@ -0,0 +1,608 @@ +/* +Copyright (c) 2009-2011, Tor M. Aamodt +The University of British Columbia +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. +Redistributions in binary form must reproduce the above copyright notice, this +list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. +Neither the name of The University of British Columbia nor the names of its +contributors may be used to endorse or promote products derived from this +software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +%union { + double double_value; + float float_value; + int int_value; + char * string_value; + void * ptr_value; +} + +%token STRING +%token OPCODE +%token WMMA_DIRECTIVE +%token LAYOUT +%token CONFIGURATION +%token ALIGN_DIRECTIVE +%token BRANCHTARGETS_DIRECTIVE +%token BYTE_DIRECTIVE +%token CALLPROTOTYPE_DIRECTIVE +%token CALLTARGETS_DIRECTIVE +%token CONST_DIRECTIVE +%token CONSTPTR_DIRECTIVE +%token PTR_DIRECTIVE +%token ENTRY_DIRECTIVE +%token EXTERN_DIRECTIVE +%token WEAK_DIRECTIVE +%token FILE_DIRECTIVE +%token FUNC_DIRECTIVE +%token GLOBAL_DIRECTIVE +%token LOCAL_DIRECTIVE +%token LOC_DIRECTIVE +%token MAXNCTAPERSM_DIRECTIVE +%token MAXNNREG_DIRECTIVE +%token MAXNTID_DIRECTIVE +%token MINNCTAPERSM_DIRECTIVE +%token PARAM_DIRECTIVE +%token PRAGMA_DIRECTIVE +%token REG_DIRECTIVE +%token REQNTID_DIRECTIVE +%token SECTION_DIRECTIVE +%token SHARED_DIRECTIVE +%token SREG_DIRECTIVE +%token SSTARR_DIRECTIVE +%token STRUCT_DIRECTIVE +%token SURF_DIRECTIVE +%token TARGET_DIRECTIVE +%token TEX_DIRECTIVE +%token UNION_DIRECTIVE +%token VERSION_DIRECTIVE +%token ADDRESS_SIZE_DIRECTIVE +%token VISIBLE_DIRECTIVE +%token WEAK_DIRECTIVE +%token IDENTIFIER +%token INT_OPERAND +%token FLOAT_OPERAND +%token DOUBLE_OPERAND +%token S8_TYPE +%token S16_TYPE +%token S32_TYPE +%token S64_TYPE +%token U8_TYPE +%token U16_TYPE +%token U32_TYPE +%token U64_TYPE +%token F16_TYPE +%token F32_TYPE +%token F64_TYPE +%token FF64_TYPE +%token B8_TYPE +%token B16_TYPE +%token B32_TYPE +%token B64_TYPE +%token BB64_TYPE +%token BB128_TYPE +%token PRED_TYPE +%token TEXREF_TYPE +%token SAMPLERREF_TYPE +%token SURFREF_TYPE +%token V2_TYPE +%token V3_TYPE +%token V4_TYPE +%token COMMA +%token PRED +%token HALF_OPTION +%token EXTP_OPTION +%token EQ_OPTION +%token NE_OPTION +%token LT_OPTION +%token LE_OPTION +%token GT_OPTION +%token GE_OPTION +%token LO_OPTION +%token LS_OPTION +%token HI_OPTION +%token HS_OPTION +%token EQU_OPTION +%token NEU_OPTION +%token LTU_OPTION +%token LEU_OPTION +%token GTU_OPTION +%token GEU_OPTION +%token NUM_OPTION +%token NAN_OPTION +%token CF_OPTION +%token SF_OPTION +%token NSF_OPTION +%token LEFT_SQUARE_BRACKET +%token RIGHT_SQUARE_BRACKET +%token WIDE_OPTION +%token SPECIAL_REGISTER +%token MINUS +%token PLUS +%token COLON +%token SEMI_COLON +%token EXCLAMATION +%token PIPE +%token RIGHT_BRACE +%token LEFT_BRACE +%token EQUALS +%token PERIOD +%token BACKSLASH +%token DIMENSION_MODIFIER +%token RN_OPTION +%token RZ_OPTION +%token RM_OPTION +%token RP_OPTION +%token RNI_OPTION +%token RZI_OPTION +%token RMI_OPTION +%token RPI_OPTION +%token UNI_OPTION +%token GEOM_MODIFIER_1D +%token GEOM_MODIFIER_2D +%token GEOM_MODIFIER_3D +%token SAT_OPTION +%token FTZ_OPTION +%token NEG_OPTION +%token SYNC_OPTION +%token RED_OPTION +%token ARRIVE_OPTION +%token ATOMIC_POPC +%token ATOMIC_AND +%token ATOMIC_OR +%token ATOMIC_XOR +%token ATOMIC_CAS +%token ATOMIC_EXCH +%token ATOMIC_ADD +%token ATOMIC_INC +%token ATOMIC_DEC +%token ATOMIC_MIN +%token ATOMIC_MAX +%token LEFT_ANGLE_BRACKET +%token RIGHT_ANGLE_BRACKET +%token LEFT_PAREN +%token RIGHT_PAREN +%token APPROX_OPTION +%token FULL_OPTION +%token ANY_OPTION +%token ALL_OPTION +%token BALLOT_OPTION +%token GLOBAL_OPTION +%token CTA_OPTION +%token SYS_OPTION +%token EXIT_OPTION +%token ABS_OPTION +%token TO_OPTION +%token CA_OPTION; +%token CG_OPTION; +%token CS_OPTION; +%token LU_OPTION; +%token CV_OPTION; +%token WB_OPTION; +%token WT_OPTION; +%token NC_OPTION; +%token UP_OPTION; +%token DOWN_OPTION; +%token BFLY_OPTION; +%token IDX_OPTION; + +%type function_decl_header +%type function_decl + +%{ + #include "ptx_parser.h" + #include + #include + #include + void syntax_not_implemented(); + extern int g_func_decl; + int ptx_lex(void); + int ptx_error(const char *); +%} + +%% + +input: /* empty */ + | input directive_statement + | input function_defn + | input function_decl + ; + +function_defn: function_decl { set_symtab($1); func_header(".skip"); } statement_block { end_function(); } + | function_decl { set_symtab($1); } block_spec_list { func_header(".skip"); } statement_block { end_function(); } + ; + +block_spec: MAXNTID_DIRECTIVE INT_OPERAND COMMA INT_OPERAND COMMA INT_OPERAND {func_header_info_int(".maxntid", $2); + func_header_info_int(",", $4); + func_header_info_int(",", $6); } + | MINNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".minnctapersm", $2); printf("GPGPU-Sim: Warning: .minnctapersm ignored. \n"); } + | MAXNCTAPERSM_DIRECTIVE INT_OPERAND { func_header_info_int(".maxnctapersm", $2); printf("GPGPU-Sim: Warning: .maxnctapersm ignored. \n"); } + ; + +block_spec_list: block_spec + | block_spec_list block_spec + ; + +function_decl: function_decl_header LEFT_PAREN { start_function($1); func_header_info("(");} param_entry RIGHT_PAREN {func_header_info(")");} function_ident_param { $$ = reset_symtab(); } + | function_decl_header { start_function($1); } function_ident_param { $$ = reset_symtab(); } + | function_decl_header { start_function($1); add_function_name(""); g_func_decl=0; $$ = reset_symtab(); } + ; + +function_ident_param: IDENTIFIER { add_function_name($1); } LEFT_PAREN {func_header_info("(");} param_list RIGHT_PAREN { g_func_decl=0; func_header_info(")"); } + | IDENTIFIER { add_function_name($1); g_func_decl=0; } + ; + +function_decl_header: ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } + | VISIBLE_DIRECTIVE ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } + | WEAK_DIRECTIVE ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } + | FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } + | VISIBLE_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } + | WEAK_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } + | EXTERN_DIRECTIVE FUNC_DIRECTIVE { $$ = 2; g_func_decl=1; func_header(".func"); } + | WEAK_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } + ; + +param_list: /*empty*/ + | param_entry { add_directive(); } + | param_list COMMA {func_header_info(",");} param_entry { add_directive(); } + +param_entry: PARAM_DIRECTIVE { add_space_spec(param_space_unclassified,0); } variable_spec ptr_spec identifier_spec { add_function_arg(); } + | REG_DIRECTIVE { add_space_spec(reg_space,0); } variable_spec identifier_spec { add_function_arg(); } + +ptr_spec: /*empty*/ + | PTR_DIRECTIVE ptr_space_spec ptr_align_spec + | PTR_DIRECTIVE ptr_align_spec + +ptr_space_spec: GLOBAL_DIRECTIVE { add_ptr_spec(global_space); } + | LOCAL_DIRECTIVE { add_ptr_spec(local_space); } + | SHARED_DIRECTIVE { add_ptr_spec(shared_space); } + +ptr_align_spec: ALIGN_DIRECTIVE INT_OPERAND + +statement_block: LEFT_BRACE statement_list RIGHT_BRACE + +statement_list: directive_statement { add_directive(); } + | instruction_statement { add_instruction(); } + | statement_list directive_statement { add_directive(); } + | statement_list instruction_statement { add_instruction(); } + | statement_list {start_inst_group();} statement_block {end_inst_group();} + | {start_inst_group();} statement_block {end_inst_group();} + ; + +directive_statement: variable_declaration SEMI_COLON + | VERSION_DIRECTIVE DOUBLE_OPERAND { add_version_info($2, 0); } + | VERSION_DIRECTIVE DOUBLE_OPERAND PLUS { add_version_info($2,1); } + | ADDRESS_SIZE_DIRECTIVE INT_OPERAND {/*Do nothing*/} + | TARGET_DIRECTIVE IDENTIFIER COMMA IDENTIFIER { target_header2($2,$4); } + | TARGET_DIRECTIVE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER { target_header3($2,$4,$6); } + | TARGET_DIRECTIVE IDENTIFIER { target_header($2); } + | FILE_DIRECTIVE INT_OPERAND STRING { add_file($2,$3); } + | FILE_DIRECTIVE INT_OPERAND STRING COMMA INT_OPERAND COMMA INT_OPERAND { add_file($2,$3); } + | LOC_DIRECTIVE INT_OPERAND INT_OPERAND INT_OPERAND + | PRAGMA_DIRECTIVE STRING SEMI_COLON { add_pragma($2); } + | function_decl SEMI_COLON {/*Do nothing*/} + ; + +variable_declaration: variable_spec identifier_list { add_variables(); } + | variable_spec identifier_spec EQUALS initializer_list { add_variables(); } + | variable_spec identifier_spec EQUALS literal_operand { add_variables(); } + | CONSTPTR_DIRECTIVE IDENTIFIER COMMA IDENTIFIER COMMA INT_OPERAND { add_constptr($2, $4, $6); } + ; + +variable_spec: var_spec_list { set_variable_type(); } + +identifier_list: identifier_spec + | identifier_list COMMA identifier_spec; + +identifier_spec: IDENTIFIER { add_identifier($1,0,NON_ARRAY_IDENTIFIER); func_header_info($1);} + | IDENTIFIER LEFT_ANGLE_BRACKET INT_OPERAND RIGHT_ANGLE_BRACKET { func_header_info($1); func_header_info_int("<", $3); func_header_info(">"); + int i,lbase,l; + char *id = NULL; + lbase = strlen($1); + for( i=0; i < $3; i++ ) { + l = lbase + (int)log10(i+1)+10; + id = (char*) malloc(l); + snprintf(id,l,"%s%u",$1,i); + add_identifier(id,0,NON_ARRAY_IDENTIFIER); + } + free($1); + } + | IDENTIFIER LEFT_SQUARE_BRACKET RIGHT_SQUARE_BRACKET { add_identifier($1,0,ARRAY_IDENTIFIER_NO_DIM); func_header_info($1); func_header_info("["); func_header_info("]");} + | IDENTIFIER LEFT_SQUARE_BRACKET INT_OPERAND RIGHT_SQUARE_BRACKET { add_identifier($1,$3,ARRAY_IDENTIFIER); func_header_info($1); func_header_info_int("[",$3); func_header_info("]");} + ; + +var_spec_list: var_spec + | var_spec_list var_spec; + +var_spec: space_spec + | type_spec + | align_spec + | EXTERN_DIRECTIVE { add_extern_spec(); } + | WEAK_DIRECTIVE + ; + +align_spec: ALIGN_DIRECTIVE INT_OPERAND { add_alignment_spec($2); } + +space_spec: REG_DIRECTIVE { add_space_spec(reg_space,0); } + | SREG_DIRECTIVE { add_space_spec(reg_space,0); } + | addressable_spec + ; + +addressable_spec: CONST_DIRECTIVE { add_space_spec(const_space,$1); } + | GLOBAL_DIRECTIVE { add_space_spec(global_space,0); } + | LOCAL_DIRECTIVE { add_space_spec(local_space,0); } + | PARAM_DIRECTIVE { add_space_spec(param_space_unclassified,0); } + | SHARED_DIRECTIVE { add_space_spec(shared_space,0); } + | SSTARR_DIRECTIVE { add_space_spec(sstarr_space,0); } + | SURF_DIRECTIVE { add_space_spec(surf_space,0); } + | TEX_DIRECTIVE { add_space_spec(tex_space,0); } + ; + +type_spec: scalar_type + | vector_spec scalar_type + ; + +vector_spec: V2_TYPE { add_option(V2_TYPE); func_header_info(".v2");} + | V3_TYPE { add_option(V3_TYPE); func_header_info(".v3");} + | V4_TYPE { add_option(V4_TYPE); func_header_info(".v4");} + ; + +scalar_type: S8_TYPE { add_scalar_type_spec( S8_TYPE ); } + | S16_TYPE { add_scalar_type_spec( S16_TYPE ); } + | S32_TYPE { add_scalar_type_spec( S32_TYPE ); } + | S64_TYPE { add_scalar_type_spec( S64_TYPE ); } + | U8_TYPE { add_scalar_type_spec( U8_TYPE ); } + | U16_TYPE { add_scalar_type_spec( U16_TYPE ); } + | U32_TYPE { add_scalar_type_spec( U32_TYPE ); } + | U64_TYPE { add_scalar_type_spec( U64_TYPE ); } + | F16_TYPE { add_scalar_type_spec( F16_TYPE ); } + | F32_TYPE { add_scalar_type_spec( F32_TYPE ); } + | F64_TYPE { add_scalar_type_spec( F64_TYPE ); } + | FF64_TYPE { add_scalar_type_spec( FF64_TYPE ); } + | B8_TYPE { add_scalar_type_spec( B8_TYPE ); } + | B16_TYPE { add_scalar_type_spec( B16_TYPE ); } + | B32_TYPE { add_scalar_type_spec( B32_TYPE ); } + | B64_TYPE { add_scalar_type_spec( B64_TYPE ); } + | BB64_TYPE { add_scalar_type_spec( BB64_TYPE ); } + | BB128_TYPE { add_scalar_type_spec( BB128_TYPE ); } + | PRED_TYPE { add_scalar_type_spec( PRED_TYPE ); } + | TEXREF_TYPE { add_scalar_type_spec( TEXREF_TYPE ); } + | SAMPLERREF_TYPE { add_scalar_type_spec( SAMPLERREF_TYPE ); } + | SURFREF_TYPE { add_scalar_type_spec( SURFREF_TYPE ); } + ; + +initializer_list: LEFT_BRACE literal_list RIGHT_BRACE { add_array_initializer(); } + | LEFT_BRACE initializer_list RIGHT_BRACE { syntax_not_implemented(); } + +literal_list: literal_operand + | literal_list COMMA literal_operand; + +instruction_statement: instruction SEMI_COLON + | IDENTIFIER COLON { add_label($1); } + | pred_spec instruction SEMI_COLON; + +instruction: opcode_spec LEFT_PAREN operand RIGHT_PAREN { set_return(); } COMMA operand COMMA LEFT_PAREN operand_list RIGHT_PAREN + | opcode_spec operand COMMA LEFT_PAREN operand_list RIGHT_PAREN + | opcode_spec operand COMMA LEFT_PAREN RIGHT_PAREN + | opcode_spec operand_list + | opcode_spec + ; + +opcode_spec: OPCODE { add_opcode($1); } option_list + | OPCODE { add_opcode($1); } + +pred_spec: PRED IDENTIFIER { add_pred($2,0, -1); } + | PRED EXCLAMATION IDENTIFIER { add_pred($3,1, -1); } + | PRED IDENTIFIER LT_OPTION { add_pred($2,0,1); } + | PRED IDENTIFIER EQ_OPTION { add_pred($2,0,2); } + | PRED IDENTIFIER LE_OPTION { add_pred($2,0,3); } + | PRED IDENTIFIER NE_OPTION { add_pred($2,0,5); } + | PRED IDENTIFIER GE_OPTION { add_pred($2,0,6); } + | PRED IDENTIFIER EQU_OPTION { add_pred($2,0,10); } + | PRED IDENTIFIER GTU_OPTION { add_pred($2,0,12); } + | PRED IDENTIFIER NEU_OPTION { add_pred($2,0,13); } + | PRED IDENTIFIER CF_OPTION { add_pred($2,0,17); } + | PRED IDENTIFIER SF_OPTION { add_pred($2,0,19); } + | PRED IDENTIFIER NSF_OPTION { add_pred($2,0,28); } + ; + +option_list: option + | option option_list ; + +option: type_spec + | compare_spec + | addressable_spec + | rounding_mode + | wmma_spec + | SYNC_OPTION { add_option(SYNC_OPTION); } + | ARRIVE_OPTION { add_option(ARRIVE_OPTION); } + | RED_OPTION { add_option(RED_OPTION); } + | UNI_OPTION { add_option(UNI_OPTION); } + | WIDE_OPTION { add_option(WIDE_OPTION); } + | ANY_OPTION { add_option(ANY_OPTION); } + | ALL_OPTION { add_option(ALL_OPTION); } + | BALLOT_OPTION { add_option(BALLOT_OPTION); } + | GLOBAL_OPTION { add_option(GLOBAL_OPTION); } + | CTA_OPTION { add_option(CTA_OPTION); } + | SYS_OPTION { add_option(SYS_OPTION); } + | GEOM_MODIFIER_1D { add_option(GEOM_MODIFIER_1D); } + | GEOM_MODIFIER_2D { add_option(GEOM_MODIFIER_2D); } + | GEOM_MODIFIER_3D { add_option(GEOM_MODIFIER_3D); } + | SAT_OPTION { add_option(SAT_OPTION); } + | FTZ_OPTION { add_option(FTZ_OPTION); } + | NEG_OPTION { add_option(NEG_OPTION); } + | APPROX_OPTION { add_option(APPROX_OPTION); } + | FULL_OPTION { add_option(FULL_OPTION); } + | EXIT_OPTION { add_option(EXIT_OPTION); } + | ABS_OPTION { add_option(ABS_OPTION); } + | atomic_operation_spec ; + | TO_OPTION { add_option(TO_OPTION); } + | HALF_OPTION { add_option(HALF_OPTION); } + | EXTP_OPTION { add_option(EXTP_OPTION); } + | CA_OPTION { add_option(CA_OPTION); } + | CG_OPTION { add_option(CG_OPTION); } + | CS_OPTION { add_option(CS_OPTION); } + | LU_OPTION { add_option(LU_OPTION); } + | CV_OPTION { add_option(CV_OPTION); } + | WB_OPTION { add_option(WB_OPTION); } + | WT_OPTION { add_option(WT_OPTION); } + | NC_OPTION { add_option(NC_OPTION); } + | UP_OPTION { add_option(UP_OPTION); } + | DOWN_OPTION { add_option(DOWN_OPTION); } + | BFLY_OPTION { add_option(BFLY_OPTION); } + | IDX_OPTION { add_option(IDX_OPTION); } + ; + +atomic_operation_spec: ATOMIC_AND { add_option(ATOMIC_AND); } + | ATOMIC_POPC { add_option(ATOMIC_POPC); } + | ATOMIC_OR { add_option(ATOMIC_OR); } + | ATOMIC_XOR { add_option(ATOMIC_XOR); } + | ATOMIC_CAS { add_option(ATOMIC_CAS); } + | ATOMIC_EXCH { add_option(ATOMIC_EXCH); } + | ATOMIC_ADD { add_option(ATOMIC_ADD); } + | ATOMIC_INC { add_option(ATOMIC_INC); } + | ATOMIC_DEC { add_option(ATOMIC_DEC); } + | ATOMIC_MIN { add_option(ATOMIC_MIN); } + | ATOMIC_MAX { add_option(ATOMIC_MAX); } + ; + +rounding_mode: floating_point_rounding_mode + | integer_rounding_mode; + + +floating_point_rounding_mode: RN_OPTION { add_option(RN_OPTION); } + | RZ_OPTION { add_option(RZ_OPTION); } + | RM_OPTION { add_option(RM_OPTION); } + | RP_OPTION { add_option(RP_OPTION); } + ; + +integer_rounding_mode: RNI_OPTION { add_option(RNI_OPTION); } + | RZI_OPTION { add_option(RZI_OPTION); } + | RMI_OPTION { add_option(RMI_OPTION); } + | RPI_OPTION { add_option(RPI_OPTION); } + ; + +compare_spec:EQ_OPTION { add_option(EQ_OPTION); } + | NE_OPTION { add_option(NE_OPTION); } + | LT_OPTION { add_option(LT_OPTION); } + | LE_OPTION { add_option(LE_OPTION); } + | GT_OPTION { add_option(GT_OPTION); } + | GE_OPTION { add_option(GE_OPTION); } + | LO_OPTION { add_option(LO_OPTION); } + | LS_OPTION { add_option(LS_OPTION); } + | HI_OPTION { add_option(HI_OPTION); } + | HS_OPTION { add_option(HS_OPTION); } + | EQU_OPTION { add_option(EQU_OPTION); } + | NEU_OPTION { add_option(NEU_OPTION); } + | LTU_OPTION { add_option(LTU_OPTION); } + | LEU_OPTION { add_option(LEU_OPTION); } + | GTU_OPTION { add_option(GTU_OPTION); } + | GEU_OPTION { add_option(GEU_OPTION); } + | NUM_OPTION { add_option(NUM_OPTION); } + | NAN_OPTION { add_option(NAN_OPTION); } + ; + +wmma_spec: WMMA_DIRECTIVE LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2);add_wmma_option($3);} + | WMMA_DIRECTIVE LAYOUT LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2),add_wmma_option($3),add_wmma_option($4)} + | WMMA_DIRECTIVE LAYOUT CONFIGURATION ptr_space_spec{add_wmma_option($1);add_wmma_option($2),add_wmma_option($3),add_wmma_option($4)} + | WMMA_DIRECTIVE LAYOUT LAYOUT CONFIGURATION ptr_space_spec{add_wmma_option($1);add_wmma_option($2),add_wmma_option($3),add_wmma_option($4)} + ; + +operand_list: operand + | operand COMMA operand_list; + +operand: IDENTIFIER { add_scalar_operand( $1 ); } + | EXCLAMATION IDENTIFIER { add_neg_pred_operand( $2 ); } + | MINUS IDENTIFIER { add_scalar_operand( $2 ); change_operand_neg(); } + | memory_operand + | literal_operand + | builtin_operand + | vector_operand + | MINUS vector_operand { change_operand_neg(); } + | tex_operand + | IDENTIFIER PLUS INT_OPERAND { add_address_operand($1,$3); } + | IDENTIFIER LO_OPTION { add_scalar_operand( $1 ); change_operand_lohi(1);} + | MINUS IDENTIFIER LO_OPTION { add_scalar_operand( $2 ); change_operand_lohi(1); change_operand_neg();} + | IDENTIFIER HI_OPTION { add_scalar_operand( $1 ); change_operand_lohi(2);} + | MINUS IDENTIFIER HI_OPTION { add_scalar_operand( $2 ); change_operand_lohi(2); change_operand_neg();} + | IDENTIFIER PIPE IDENTIFIER { add_2vector_operand($1,$3); change_double_operand_type(-1);} + | IDENTIFIER PIPE IDENTIFIER LO_OPTION { add_2vector_operand($1,$3); change_double_operand_type(-1); change_operand_lohi(1);} + | IDENTIFIER PIPE IDENTIFIER HI_OPTION { add_2vector_operand($1,$3); change_double_operand_type(-1); change_operand_lohi(2);} + | IDENTIFIER BACKSLASH IDENTIFIER { add_2vector_operand($1,$3); change_double_operand_type(-3);} + | IDENTIFIER BACKSLASH IDENTIFIER LO_OPTION { add_2vector_operand($1,$3); change_double_operand_type(-3); change_operand_lohi(1);} + | IDENTIFIER BACKSLASH IDENTIFIER HI_OPTION { add_2vector_operand($1,$3); change_double_operand_type(-3); change_operand_lohi(2);} + ; + +vector_operand: LEFT_BRACE IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_2vector_operand($2,$4); } + | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_3vector_operand($2,$4,$6); } + | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_4vector_operand($2,$4,$6,$8); } + | LEFT_BRACE IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER COMMA IDENTIFIER RIGHT_BRACE { add_8vector_operand($2,$4,$6,$8,$10,$12,$14,$16); } + | LEFT_BRACE IDENTIFIER RIGHT_BRACE { add_1vector_operand($2); } + ; + +tex_operand: LEFT_SQUARE_BRACKET IDENTIFIER COMMA { add_scalar_operand($2); } + vector_operand + RIGHT_SQUARE_BRACKET + ; + +builtin_operand: SPECIAL_REGISTER DIMENSION_MODIFIER { add_builtin_operand($1,$2); } + | SPECIAL_REGISTER { add_builtin_operand($1,-1); } + ; + +memory_operand : LEFT_SQUARE_BRACKET address_expression RIGHT_SQUARE_BRACKET { add_memory_operand(); } + | IDENTIFIER LEFT_SQUARE_BRACKET address_expression RIGHT_SQUARE_BRACKET { add_memory_operand(); change_memory_addr_space($1); } + | IDENTIFIER LEFT_SQUARE_BRACKET literal_operand RIGHT_SQUARE_BRACKET { change_memory_addr_space($1); } + | IDENTIFIER LEFT_SQUARE_BRACKET twin_operand RIGHT_SQUARE_BRACKET { change_memory_addr_space($1); add_memory_operand();} + | MINUS memory_operand { change_operand_neg(); } + ; + +twin_operand : IDENTIFIER PLUS IDENTIFIER { add_double_operand($1,$3); change_double_operand_type(1); } + | IDENTIFIER PLUS IDENTIFIER LO_OPTION { add_double_operand($1,$3); change_double_operand_type(1); change_operand_lohi(1); } + | IDENTIFIER PLUS IDENTIFIER HI_OPTION { add_double_operand($1,$3); change_double_operand_type(1); change_operand_lohi(2); } + | IDENTIFIER PLUS EQUALS IDENTIFIER { add_double_operand($1,$4); change_double_operand_type(2); } + | IDENTIFIER PLUS EQUALS IDENTIFIER LO_OPTION { add_double_operand($1,$4); change_double_operand_type(2); change_operand_lohi(1); } + | IDENTIFIER PLUS EQUALS IDENTIFIER HI_OPTION { add_double_operand($1,$4); change_double_operand_type(2); change_operand_lohi(2); } + | IDENTIFIER PLUS EQUALS INT_OPERAND { add_address_operand($1,$4); change_double_operand_type(3); } + ; + +literal_operand : INT_OPERAND { add_literal_int($1); } + | FLOAT_OPERAND { add_literal_float($1); } + | DOUBLE_OPERAND { add_literal_double($1); } + ; + +address_expression: IDENTIFIER { add_address_operand($1,0); } + | IDENTIFIER LO_OPTION { add_address_operand($1,0); change_operand_lohi(1);} + | IDENTIFIER HI_OPTION { add_address_operand($1,0); change_operand_lohi(2); } + | IDENTIFIER PLUS INT_OPERAND { add_address_operand($1,$3); } + | INT_OPERAND { add_address_operand2($1); } + ; + +%% + +extern int ptx_lineno; +extern const char *g_filename; + +void syntax_not_implemented() +{ + printf("Parse error (%s:%u): this syntax is not (yet) implemented:\n",g_filename,ptx_lineno); + ptx_error(NULL); + abort(); +} diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 833f175..16cc975 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -1078,7 +1078,7 @@ public: int membar_level() const { return m_membar_level; } bool has_memory_read() const { - if( m_opcode == LD_OP || m_opcode == LDU_OP || m_opcode == TEX_OP ) + if( m_opcode == LD_OP || m_opcode == LDU_OP || m_opcode == TEX_OP|| m_opcode==MMA_LD_OP) return true; // Check PTXPlus operand type below // Source operands are memory operands @@ -1090,7 +1090,7 @@ public: return false; } bool has_memory_write() const { - if( m_opcode == ST_OP ) return true; + if( m_opcode == ST_OP || m_opcode==MMA_ST_OP ) return true; // Check PTXPlus operand type below // Destination operand is a memory operand ptx_instruction::const_iterator op=op_iter_begin(); diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h index 05acf20..403ce5b 100644 --- a/src/cuda-sim/ptx_sim.h +++ b/src/cuda-sim/ptx_sim.h @@ -303,6 +303,15 @@ public: const ptx_reg_t &data2, const ptx_reg_t &data3, const ptx_reg_t &data4 ); + void set_wmma_vector_operand_values( const operand_info &dst, + const ptx_reg_t &data1, + const ptx_reg_t &data2, + const ptx_reg_t &data3, + const ptx_reg_t &data4, + const ptx_reg_t &data5, + const ptx_reg_t &data6, + const ptx_reg_t &data7, + const ptx_reg_t &data8 ); function_info *func_info() { diff --git a/src/gpgpu-sim/Makefile b/src/gpgpu-sim/Makefile index f10a8a4..4f77699 100644 --- a/src/gpgpu-sim/Makefile +++ b/src/gpgpu-sim/Makefile @@ -48,7 +48,7 @@ ifeq ($(GNUC_CPP0X), 1) endif ifneq ($(DEBUG),1) - OPTFLAGS += -O3 + OPTFLAGS += -O0 else CXXFLAGS += endif diff --git a/src/intersim2/Makefile b/src/intersim2/Makefile index bd42000..4ef21ac 100644 --- a/src/intersim2/Makefile +++ b/src/intersim2/Makefile @@ -44,7 +44,7 @@ endif CPPFLAGS += -Wall $(INCPATH) $(DEFINE) ifneq ($(DEBUG),1) -CPPFLAGS += -O3 +CPPFLAGS += -O0 endif CPPFLAGS += -g CPPFLAGS += -fPIC -- cgit v1.3 From 29b566108f2304e42e12ba5ab1d9e7f45117bd83 Mon Sep 17 00:00:00 2001 From: Jonathan Date: Wed, 30 May 2018 23:11:25 -0700 Subject: allows _1.ptx generation without cuobjdump_complete_output generation --- libcuda/cuda_runtime_api.cc | 130 ++++++++++++++++++++++++-------------------- 1 file changed, 70 insertions(+), 60 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index dc92522..fcb0808 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1611,61 +1611,70 @@ void extract_code_using_cuobjdump(){ printf("Parsing skipped for %s\n", fname); } - if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ - //Experimental library support - //Currently only for cufft - - std::stringstream cmd; - cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; - int result = system(cmd.str().c_str()); - if(result){ - std::cout << "Failed to execute: " << cmd.str() << std::endl; - exit(1); - } - std::ifstream libsf; - libsf.open("_tempfile_.txt"); - if(!libsf.is_open()) { - std::cout << "Failed to open: _tempfile_.txt" << std::endl; - exit(1); - } - - //Save the original section list - std::list tmpsl = cuobjdumpSectionList; - cuobjdumpSectionList.clear(); - - std::string line; - std::getline(libsf, line); - std::cout << "DOING: " << line << std::endl; - int cnt=1; - while(libsf.good()){ - std::stringstream libcodfn; - libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; - cmd.str(""); //resetting - cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; - cmd << line; - cmd << " > "; - cmd << libcodfn.str(); - std::cout << "Running cuobjdump on " << line << std::endl; - std::cout << "Using command: " << cmd.str() << std::endl; - result = system(cmd.str().c_str()); - if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} - std::cout << "Done" << std::endl; - - std::cout << "Trying to parse " << libcodfn.str() << std::endl; - cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); - cuobjdump_parse(); - fclose(cuobjdump_in); - std::getline(libsf, line); - } - libSectionList = cuobjdumpSectionList; - - //Restore the original section list - cuobjdumpSectionList = tmpsl; - } } else { printf("GPGPU-Sim PTX: overriding cuobjdump with '%s' (CUOBJDUMP_SIM_FILE is set)\n", override_cuobjdump); snprintf(fname,1024, "%s",override_cuobjdump); + + printf("Parsing file %s\n", override_cuobjdump); + cuobjdump_in = fopen(override_cuobjdump, "r"); + + cuobjdump_parse(); + fclose(cuobjdump_in); + printf("Done parsing!!!\n"); } + + if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ + //Experimental library support + //Currently only for cufft + + std::stringstream cmd; + cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; + int result = system(cmd.str().c_str()); + if(result){ + std::cout << "Failed to execute: " << cmd.str() << std::endl; + exit(1); + } + std::ifstream libsf; + libsf.open("_tempfile_.txt"); + if(!libsf.is_open()) { + std::cout << "Failed to open: _tempfile_.txt" << std::endl; + exit(1); + } + + //Save the original section list + std::list tmpsl = cuobjdumpSectionList; + cuobjdumpSectionList.clear(); + + std::string line; + std::getline(libsf, line); + std::cout << "DOING: " << line << std::endl; + int cnt=1; + while(libsf.good()){ + std::stringstream libcodfn; + libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; + cmd.str(""); //resetting + cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; + cmd << line; + cmd << " > "; + cmd << libcodfn.str(); + std::cout << "Running cuobjdump on " << line << std::endl; + std::cout << "Using command: " << cmd.str() << std::endl; + result = system(cmd.str().c_str()); + if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} + std::cout << "Done" << std::endl; + + std::cout << "Trying to parse " << libcodfn.str() << std::endl; + cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); + cuobjdump_parse(); + fclose(cuobjdump_in); + std::getline(libsf, line); + } + libSectionList = cuobjdumpSectionList; + + //Restore the original section list + cuobjdumpSectionList = tmpsl; + } + } //! Read file into char* @@ -1898,10 +1907,10 @@ void cuobjdumpInit(){ CUctx_st *context = GPGPUSim_Context(); extract_code_using_cuobjdump(); //extract all the output of cuobjdump to _cuobjdump_*.* const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); - if (pre_load ==NULL || strlen(pre_load)==0){ + //if (pre_load ==NULL || strlen(pre_load)==0){ cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); cuobjdumpSectionList = mergeSections(cuobjdumpSectionList); - } + //} } std::map fatbinmap; @@ -1939,17 +1948,18 @@ void cuobjdumpParseBinary(unsigned int handle){ cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); - if(pre_load==NULL || strlen(pre_load)==0) + //if(pre_load==NULL || strlen(pre_load)==0) ptx = findPTXSection(fname); symbol_table *symtab; char *ptxcode; - const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); - if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL or strlen(getenv("PTX_SIM_USE_PTX_FILE"))==0) { + //const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); + //if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL or strlen(getenv("PTX_SIM_USE_PTX_FILE"))==0) { ptxcode = readfile(ptx->getPTXfilename()); - } else { - printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); - ptxcode = readfile(override_ptx_name); - } +// } +// else { +// printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); +// ptxcode = readfile(override_ptx_name); +// } if(context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() ) { cuobjdumpELFSection* elfsection = findELFSection(ptx->getIdentifier()); assert (elfsection!= NULL); -- cgit v1.3 From 03de5ae03420ba5666d669c6f76faccf2704fa58 Mon Sep 17 00:00:00 2001 From: aamir Date: Thu, 31 May 2018 00:48:37 -0700 Subject: mma_ld_impl --- src/cuda-sim/ptx.y | 2 +- src/cuda-sim/ptx_ir.h | 2 +- src/cuda-sim/ptx_parser.cc | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 737657c..012451c 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -520,7 +520,7 @@ compare_spec:EQ_OPTION { add_option(EQ_OPTION); } | NAN_OPTION { add_option(NAN_OPTION); } ; -wmma_spec: WMMA_DIRECTIVE LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2);add_wmma_option($3);} +wmma_spec: WMMA_DIRECTIVE LAYOUT CONFIGURATION{add_space_spec(global_space,0);add_ptr_spec(global_space); add_wmma_option($1);add_wmma_option($2);add_wmma_option($3);} | WMMA_DIRECTIVE LAYOUT LAYOUT CONFIGURATION{add_wmma_option($1);add_wmma_option($2),add_wmma_option($3),add_wmma_option($4)} ; diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h index 16cc975..6bba717 100644 --- a/src/cuda-sim/ptx_ir.h +++ b/src/cuda-sim/ptx_ir.h @@ -665,7 +665,7 @@ public: const symbol* vec_symbol(int idx) const { - assert(idx < 4); + assert(idx < 8); const symbol *result = m_value.m_vector_symbolic[idx]; assert( result != NULL ); return result; diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc index 6757091..eb81961 100644 --- a/src/cuda-sim/ptx_parser.cc +++ b/src/cuda-sim/ptx_parser.cc @@ -39,7 +39,7 @@ void set_ptx_warp_size(const struct core_config * warp_size) g_shader_core_config=warp_size; } -static bool g_debug_ir_generation=false; +static bool g_debug_ir_generation=true; const char *g_filename; unsigned g_max_regs_per_thread = 0; -- cgit v1.3 From c175eeab56567165f4be72b87746439ad0837c6e Mon Sep 17 00:00:00 2001 From: Jonathan Date: Thu, 31 May 2018 11:23:02 -0700 Subject: Revert "allows _1.ptx generation without cuobjdump_complete_output generation" This reverts commit 29b566108f2304e42e12ba5ab1d9e7f45117bd83. --- libcuda/cuda_runtime_api.cc | 130 ++++++++++++++++++++------------------------ 1 file changed, 60 insertions(+), 70 deletions(-) diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index fcb0808..dc92522 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -1611,70 +1611,61 @@ void extract_code_using_cuobjdump(){ printf("Parsing skipped for %s\n", fname); } + if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ + //Experimental library support + //Currently only for cufft + + std::stringstream cmd; + cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; + int result = system(cmd.str().c_str()); + if(result){ + std::cout << "Failed to execute: " << cmd.str() << std::endl; + exit(1); + } + std::ifstream libsf; + libsf.open("_tempfile_.txt"); + if(!libsf.is_open()) { + std::cout << "Failed to open: _tempfile_.txt" << std::endl; + exit(1); + } + + //Save the original section list + std::list tmpsl = cuobjdumpSectionList; + cuobjdumpSectionList.clear(); + + std::string line; + std::getline(libsf, line); + std::cout << "DOING: " << line << std::endl; + int cnt=1; + while(libsf.good()){ + std::stringstream libcodfn; + libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; + cmd.str(""); //resetting + cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; + cmd << line; + cmd << " > "; + cmd << libcodfn.str(); + std::cout << "Running cuobjdump on " << line << std::endl; + std::cout << "Using command: " << cmd.str() << std::endl; + result = system(cmd.str().c_str()); + if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} + std::cout << "Done" << std::endl; + + std::cout << "Trying to parse " << libcodfn.str() << std::endl; + cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); + cuobjdump_parse(); + fclose(cuobjdump_in); + std::getline(libsf, line); + } + libSectionList = cuobjdumpSectionList; + + //Restore the original section list + cuobjdumpSectionList = tmpsl; + } } else { printf("GPGPU-Sim PTX: overriding cuobjdump with '%s' (CUOBJDUMP_SIM_FILE is set)\n", override_cuobjdump); snprintf(fname,1024, "%s",override_cuobjdump); - - printf("Parsing file %s\n", override_cuobjdump); - cuobjdump_in = fopen(override_cuobjdump, "r"); - - cuobjdump_parse(); - fclose(cuobjdump_in); - printf("Done parsing!!!\n"); } - - if (context->get_device()->get_gpgpu()->get_config().experimental_lib_support()){ - //Experimental library support - //Currently only for cufft - - std::stringstream cmd; - cmd << "ldd " << app_binary << " | grep $CUDA_INSTALL_PATH | awk \'{print $3}\' > _tempfile_.txt"; - int result = system(cmd.str().c_str()); - if(result){ - std::cout << "Failed to execute: " << cmd.str() << std::endl; - exit(1); - } - std::ifstream libsf; - libsf.open("_tempfile_.txt"); - if(!libsf.is_open()) { - std::cout << "Failed to open: _tempfile_.txt" << std::endl; - exit(1); - } - - //Save the original section list - std::list tmpsl = cuobjdumpSectionList; - cuobjdumpSectionList.clear(); - - std::string line; - std::getline(libsf, line); - std::cout << "DOING: " << line << std::endl; - int cnt=1; - while(libsf.good()){ - std::stringstream libcodfn; - libcodfn << "_cuobjdump_complete_lib_" << cnt << "_"; - cmd.str(""); //resetting - cmd << "$CUDA_INSTALL_PATH/bin/cuobjdump -ptx -elf -sass "; - cmd << line; - cmd << " > "; - cmd << libcodfn.str(); - std::cout << "Running cuobjdump on " << line << std::endl; - std::cout << "Using command: " << cmd.str() << std::endl; - result = system(cmd.str().c_str()); - if(result) {printf("ERROR: Failed to execute: %s\n", command); exit(1);} - std::cout << "Done" << std::endl; - - std::cout << "Trying to parse " << libcodfn.str() << std::endl; - cuobjdump_in = fopen(libcodfn.str().c_str(), "r"); - cuobjdump_parse(); - fclose(cuobjdump_in); - std::getline(libsf, line); - } - libSectionList = cuobjdumpSectionList; - - //Restore the original section list - cuobjdumpSectionList = tmpsl; - } - } //! Read file into char* @@ -1907,10 +1898,10 @@ void cuobjdumpInit(){ CUctx_st *context = GPGPUSim_Context(); extract_code_using_cuobjdump(); //extract all the output of cuobjdump to _cuobjdump_*.* const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); - //if (pre_load ==NULL || strlen(pre_load)==0){ + if (pre_load ==NULL || strlen(pre_load)==0){ cuobjdumpSectionList = pruneSectionList(cuobjdumpSectionList, context); cuobjdumpSectionList = mergeSections(cuobjdumpSectionList); - //} + } } std::map fatbinmap; @@ -1948,18 +1939,17 @@ void cuobjdumpParseBinary(unsigned int handle){ cuobjdumpPTXSection* ptx = NULL; const char* pre_load = getenv("CUOBJDUMP_SIM_FILE"); - //if(pre_load==NULL || strlen(pre_load)==0) + if(pre_load==NULL || strlen(pre_load)==0) ptx = findPTXSection(fname); symbol_table *symtab; char *ptxcode; - //const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); - //if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL or strlen(getenv("PTX_SIM_USE_PTX_FILE"))==0) { + const char *override_ptx_name = getenv("PTX_SIM_KERNELFILE"); + if (override_ptx_name == NULL or getenv("PTX_SIM_USE_PTX_FILE") == NULL or strlen(getenv("PTX_SIM_USE_PTX_FILE"))==0) { ptxcode = readfile(ptx->getPTXfilename()); -// } -// else { -// printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); -// ptxcode = readfile(override_ptx_name); -// } + } else { + printf("GPGPU-Sim PTX: overriding embedded ptx with '%s' (PTX_SIM_USE_PTX_FILE is set)\n", override_ptx_name); + ptxcode = readfile(override_ptx_name); + } if(context->get_device()->get_gpgpu()->get_config().convert_to_ptxplus() ) { cuobjdumpELFSection* elfsection = findELFSection(ptx->getIdentifier()); assert (elfsection!= NULL); -- cgit v1.3 From e5f532a3b65e17f49991ed08a275f87ac2d68d0a Mon Sep 17 00:00:00 2001 From: aamir Date: Fri, 1 Jun 2018 09:52:12 -0700 Subject: wmma load working --- cuda-kernels/gpgpu_inst_stats.txt | 19 + cuda-kernels/log | 6328 +++++++++++++++++++++++++++++++++++++ cuda-kernels/log1 | 512 +++ cuda-kernels/tensor_core | Bin 2750968 -> 2750968 bytes src/cuda-sim/Makefile | 2 +- src/cuda-sim/cuda-math.h | 1 + src/cuda-sim/cuda-sim.cc | 2 +- src/cuda-sim/half.hpp | 3067 ++++++++++++++++++ src/cuda-sim/instructions.cc | 96 +- src/cuda-sim/ptx_sim.h | 6 +- 10 files changed, 9988 insertions(+), 45 deletions(-) create mode 100644 cuda-kernels/log create mode 100644 cuda-kernels/log1 create mode 100644 src/cuda-sim/half.hpp diff --git a/cuda-kernels/gpgpu_inst_stats.txt b/cuda-kernels/gpgpu_inst_stats.txt index acb1839..41f06a4 100755 --- a/cuda-kernels/gpgpu_inst_stats.txt +++ b/cuda-kernels/gpgpu_inst_stats.txt @@ -1 +1,20 @@ kernel line : count latency dram_traffic smem_bk_conflicts smem_warp gmem_access_generated gmem_warp exposed_latency warp_divergence +_1.ptx 164 : 512 2560 1024 0 0 16 16 0 0 +_1.ptx 163 : 512 5696 0 0 0 0 0 0 0 +_1.ptx 162 : 512 5664 0 0 0 0 0 0 0 +_1.ptx 161 : 512 3616 0 0 0 0 0 0 0 +_1.ptx 158 : 512 3616 0 0 0 0 0 0 0 +_1.ptx 156 : 512 134048 2048 0 0 16 16 0 0 +_1.ptx 155 : 512 5632 0 0 0 0 0 0 0 +_1.ptx 154 : 512 5376 0 0 0 0 0 0 0 +_1.ptx 143 : 512 100864 128 0 0 0 0 0 0 +_1.ptx 167 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 144 : 512 100864 0 0 0 0 0 0 0 +_1.ptx 145 : 512 1536 0 0 0 0 0 0 0 +_1.ptx 146 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 147 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 148 : 512 3072 0 0 0 0 0 0 0 +_1.ptx 149 : 512 8384 0 0 0 0 0 0 0 +_1.ptx 150 : 512 4096 0 0 0 0 0 0 0 +_1.ptx 151 : 512 0 0 0 0 0 0 0 0 +_1.ptx 153 : 512 3968 0 0 0 0 0 0 0 diff --git a/cuda-kernels/log b/cuda-kernels/log new file mode 100644 index 0000000..98df26a --- /dev/null +++ b/cuda-kernels/log @@ -0,0 +1,6328 @@ + + + *** GPGPU-Sim Simulator Version 3.2.2 [build gpgpu-sim_git-commit-03de5ae03420ba5666d669c6f76faccf2704fa58_modified_17] *** + + +GPGPU-Sim PTX: simulation mode 0 (can change with PTX_SIM_MODE_FUNC environment variable: + 1=functional simulation only, 0=detailed performance simulator) +GPGPU-Sim: Configuration options: + +-network_mode 1 # Interconnection network mode +-inter_config_file config_fermi_islip.icnt # Interconnection network config file +-gpgpu_ptx_use_cuobjdump 1 # Use cuobjdump to extract ptx and sass from binaries +-gpgpu_experimental_lib_support 0 # Try to extract code from cuda libraries [Broken because of unknown cudaGetExportTable] +-gpgpu_ptx_convert_to_ptxplus 0 # Convert SASS (native ISA) to ptxplus and run ptxplus +-gpgpu_ptx_force_max_capability 70 # Force maximum compute capability +-gpgpu_ptx_inst_debug_to_file 0 # Dump executed instructions' debug information to file +-gpgpu_ptx_inst_debug_file inst_debug.txt # Executed instructions' debug output file +-gpgpu_ptx_inst_debug_thread_uid 1 # Thread UID for executed instructions' debug output +-gpgpu_simd_model 1 # 1 = post-dominator +-gpgpu_shader_core_pipeline 2048:32 # shader core pipeline config, i.e., {:} +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # per-shader L1 texture cache (READ-ONLY) config {::,:::,::,:} +-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 # per-shader L1 constant memory cache (READ-ONLY) config {::,:::,::,} +-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 # shader L1 instruction cache config {::,:::,::,} +-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,8 # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PrefL1 none # per-shader L1 data cache config {::,:::,::, | none} +-gpgpu_cache:dl1PreShared none # per-shader L1 data cache config {::,:::,::, | none} +-gmem_skip_L1D 1 # global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip) +-gpgpu_perfect_mem 0 # enable perfect memory mode (no cache miss) +-n_regfile_gating_group 4 # group of lanes that should be read/written together) +-gpgpu_clock_gated_reg_file 0 # enable clock gated reg file for power calculations +-gpgpu_clock_gated_lanes 0 # enable clock gated lanes for power calculations +-gpgpu_shader_registers 65536 # Number of registers per shader core. Limits number of concurrent CTAs. (default 8192) +-gpgpu_shader_cta 32 # Maximum number of concurrent CTAs in shader (default 8) +-gpgpu_num_cta_barriers 16 # Maximum number of named barriers per CTA (default 16) +-gpgpu_n_clusters 40 # number of processing clusters +-gpgpu_n_cores_per_cluster 1 # number of simd cores per cluster +-gpgpu_n_cluster_ejection_buffer_size 8 # number of packets in ejection buffer +-gpgpu_n_ldst_response_buffer_size 2 # number of response packets in ld/st unit ejection buffer +-gpgpu_shmem_size 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size 98304 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefL1 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_size_PrefShared 16384 # Size of shared memory per shader core (default 16kB) +-gpgpu_shmem_num_banks 32 # Number of banks in the shared memory in each shader core (default 16) +-gpgpu_shmem_limited_broadcast 0 # Limit shared memory to do one broadcast per cycle (default on) +-gpgpu_shmem_warp_parts 1 # Number of portions a warp is divided into for shared memory bank conflict check +-gpgpu_warpdistro_shader -1 # Specify which shader core to collect the warp size distribution from +-gpgpu_warp_issue_shader 0 # Specify which shader core to collect the warp issue distribution from +-gpgpu_local_mem_map 1 # Mapping from local memory space address to simulated GPU physical address space (default = enabled) +-gpgpu_num_reg_banks 32 # Number of register banks (default = 8) +-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping registers to banks (default = off) +-gpgpu_operand_collector_num_units_sp 20 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_sfu 4 # number of collector units (default = 4) +-gpgpu_operand_collector_num_units_mem 8 # number of collector units (default = 2) +-gpgpu_operand_collector_num_units_gen 0 # number of collector units (default = 0) +-gpgpu_operand_collector_num_in_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_in_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_operand_collector_num_out_ports_sp 4 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_sfu 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_mem 1 # number of collector unit in ports (default = 1) +-gpgpu_operand_collector_num_out_ports_gen 0 # number of collector unit in ports (default = 0) +-gpgpu_coalesce_arch 13 # Coalescing arch (default = 13, anything else is off for now) +-gpgpu_num_sched_per_core 2 # Number of warp schedulers per core +-gpgpu_max_insn_issue_per_warp 2 # Max number of instructions that can be issued per warp in one cycle by scheduler +-gpgpu_simt_core_sim_order 1 # Select the simulation order of cores in a cluster (0=Fix, 1=Round-Robin) +-gpgpu_pipeline_widths 4,1,1,4,1,1,6 # Pipeline widths ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_num_sp_units 4 # Number of SP units (default=1) +-gpgpu_num_sfu_units 1 # Number of SF units (default=1) +-gpgpu_num_mem_units 1 # Number if ldst units (default=1) WARNING: not hooked up to anything +-gpgpu_scheduler gto # Scheduler configuration: < lrr | gto | two_level_active > If two_level_active:::For complete list of prioritization values see shader.h enum scheduler_prioritization_typeDefault: gto +-gpgpu_concurrent_kernel_sm 0 # Support concurrent kernels on a SM (default = disabled) +-gpgpu_dram_scheduler 1 # 0 = fifo, 1 = FR-FCFS (defaul) +-gpgpu_dram_partition_queues 8:8:8:8 # i2$:$2d:d2$:$2i +-l2_ideal 0 # Use a ideal L2 cache that always hit +-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # unified banked L2 data cache config {::,:::,::,} +-gpgpu_cache:dl2_texture_only 0 # L2 cache used for texture only +-gpgpu_n_mem 11 # number of memory modules (e.g. memory controllers) in gpu +-gpgpu_n_sub_partition_per_mchannel 2 # number of memory subpartition in each memory module +-gpgpu_n_mem_per_ctrlr 1 # number of memory chips per memory controller +-gpgpu_memlatency_stat 14 # track and display latency statistics 0x2 enables MC, 0x4 enables queue logs +-gpgpu_frfcfs_dram_sched_queue_size 64 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_return_queue_size 116 # 0 = unlimited (default); # entries per chip +-gpgpu_dram_buswidth 4 # default = 4 bytes (8 bytes per cycle at DDR) +-gpgpu_dram_burst_length 8 # Burst length of each DRAM request (default = 4 data bus cycle) +-dram_data_command_freq_ratio 4 # Frequency ratio between DRAM data bus and command bus (default = 2 times, i.e. DDR) +-gpgpu_dram_timing_opt nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0 # DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL} +-rop_latency 120 # ROP queue latency (default 85) +-dram_latency 100 # DRAM latency (default 30) +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS # mapping memory address to dram model {dramid@;} +-gpgpu_mem_addr_test 0 # run sweep test to check address mapping for aliased address +-gpgpu_mem_address_mask 1 # 0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits +-gpuwattch_xml_file gpuwattch_gtx1080Ti.xml # GPUWattch XML file +-power_simulation_enabled 1 # Turn on power simulator (1=On, 0=Off) +-power_per_cycle_dump 0 # Dump detailed power output each cycle +-power_trace_enabled 0 # produce a file for the power trace (1=On, 0=Off) +-power_trace_zlevel 6 # Compression level of the power trace output log (0=no comp, 9=highest) +-steady_power_levels_enabled 0 # produce a file for the steady power levels (1=On, 0=Off) +-steady_state_definition 8:4 # allowed deviation:number of samples +-gpgpu_max_cycle 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_insn 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_max_cta 0 # terminates gpu simulation early (0 = no limit) +-gpgpu_runtime_stat 500 # display runtime statistics such as dram utilization {:} +-liveness_message_freq 1 # Minimum number of seconds between simulation liveness messages (0 = always print) +-gpgpu_flush_l1_cache 0 # Flush L1 cache at the end of each kernel call +-gpgpu_flush_l2_cache 0 # Flush L2 cache at the end of each kernel call +-gpgpu_deadlock_detect 1 # Stop the simulation at deadlock (1=on (default), 0=off) +-gpgpu_ptx_instruction_classification 0 # if enabled will classify ptx instruction types per kernel (Max 255 kernels now) +-gpgpu_ptx_sim_mode 0 # Select between Performance (default) or Functional simulation (1) +-gpgpu_clock_domains 1481.0:2962.0:1481.0:2750.0 # Clock Domain Frequencies in MhZ {:::} +-gpgpu_max_concurrent_kernel 8 # maximum kernels that can run concurrently on GPU +-gpgpu_cflog_interval 0 # Interval between each snapshot in control flow logger +-visualizer_enabled 0 # Turn on visualizer output (1=On, 0=Off) +-visualizer_outputfile NULL # Specifies the output log file for visualizer +-visualizer_zlevel 6 # Compression level of the visualizer output log (0=no comp, 9=highest) +-trace_enabled 0 # Turn on traces +-trace_components none # comma seperated list of traces to enable. Complete list found in trace_streams.tup. Default none +-trace_sampling_core 0 # The core which is printed using CORE_DPRINTF. Default 0 +-trace_sampling_memory_partition -1 # The memory partition which is printed using MEMPART_DPRINTF. Default -1 (i.e. all) +-enable_ptx_file_line_stats 1 # Turn on PTX source line statistic profiling. (1 = On) +-ptx_line_stats_filename gpgpu_inst_stats.txt # Output file for PTX source line statistics. +-gpgpu_kernel_launch_latency 0 # Kernel launch latency in cycles. Default: 0 +-gpgpu_cdp_enabled 0 # Turn on CDP +-save_embedded_ptx 0 # saves ptx files embedded in binary as .ptx +-keep 0 # keep intermediate files created by GPGPU-Sim when interfacing with external programs +-gpgpu_ptx_save_converted_ptxplus 0 # Saved converted ptxplus to a file +-ptx_opcode_latency_int 4,13,4,5,145,16,4 # Opcode latencies for integers Default 1,1,19,25,145,1,4 +-ptx_opcode_latency_fp 4,13,4,5,39 # Opcode latencies for single precision floating points Default 1,1,1,1,30 +-ptx_opcode_latency_dp 8,19,8,8,330 # Opcode latencies for double precision floating points Default 8,8,8,8,335 +-ptx_opcode_initiation_int 1,2,2,2,8,16,4 # Opcode initiation intervals for integers Default 1,1,4,4,32,1,1 +-ptx_opcode_initiation_fp 1,2,1,1,4 # Opcode initiation intervals for single precision floating points Default 1,1,1,1,5 +-ptx_opcode_initiation_dp 1,2,1,1,130 # Opcode initiation intervals for double precision floating points Default 8,8,8,8,130 +-cdp_latency 7200,8000,100,12000,1600 # CDP API latency Default 7200,8000,100,12000,1600 +DRAM Timing Options: +nbk 16 # number of banks +CCD 2 # column to column delay +RRD 6 # minimal delay between activation of rows in different banks +RCD 12 # row to column delay +RAS 28 # time needed to activate row +RP 12 # time needed to precharge (deactivate) row +RC 40 # row cycle time +CDLR 5 # switching from write to read (changes tWTR) +WR 12 # last data-in to row precharge +CL 12 # CAS latency +WL 4 # Write latency +nbkgrp 1 # number of bank groups +CCDL 0 # column to column delay between accesses to different bank groups +RTPL 0 # read to precharge delay between accesses to different bank groups +Total number of memory sub partition = 22 +addr_dec_mask[CHIP] = 0000000000000000 high:64 low:0 +addr_dec_mask[BK] = 0000000000007080 high:15 low:7 +addr_dec_mask[ROW] = 000000000fff8000 high:28 low:15 +addr_dec_mask[COL] = 0000000000000f7f high:12 low:0 +addr_dec_mask[BURST] = 000000000000001f high:5 low:0 +sub_partition_id_mask = 0000000000000080 +GPGPU-Sim uArch: clock freqs: 1481000000.000000:2962000000.000000:1481000000.000000:2750000000.000000 +GPGPU-Sim uArch: clock periods: 0.00000000067521944632:0.00000000033760972316:0.00000000067521944632:0.00000000036363636364 +*** Initializing Memory Statistics *** +GPGPU-Sim uArch: interconnect node map (shaderID+MemID to icntID) +GPGPU-Sim uArch: Memory nodes ID start from index: 40 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 50 51 52 53 54 55 +GPGPU-Sim uArch: 56 57 58 59 60 61 +GPGPU-Sim uArch: interconnect node reverse map (icntID to shaderID+MemID) +GPGPU-Sim uArch: Memory nodes start from ID: 40 +GPGPU-Sim uArch: 0 1 2 3 4 5 6 +GPGPU-Sim uArch: 7 8 9 10 11 12 13 +GPGPU-Sim uArch: 14 15 16 17 18 19 20 +GPGPU-Sim uArch: 21 22 23 24 25 26 27 +GPGPU-Sim uArch: 28 29 30 31 32 33 34 +GPGPU-Sim uArch: 35 36 37 38 39 40 41 +GPGPU-Sim uArch: 42 43 44 45 46 47 48 +GPGPU-Sim uArch: 49 50 51 52 53 54 55 +GPGPU-Sim uArch: 56 57 58 59 60 61 +a9478053306cbb4803bedf0d6ea12100 /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core +GPGPU-Sim uArch: performance model initialization complete. +GPGPU-Sim PTX: __cudaRegisterFatBinary, fat_cubin_handle = 1, filename=default +self exe links to: /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core +Running md5sum using "md5sum /home/araihan/gpgpusim-tensorcore/cuda-kernels/tensor_core " +Parsing file _cuobjdump_complete_output_c7ZC8M +######### cuobjdump parser ######## +## Adding new section PTX +Adding ptx filename: _cuobjdump_1.ptx +Adding arch: sm_70 +Adding identifier: default +Done parsing!!! +GPGPU-Sim PTX: __cudaRegisterFunction _Z17convertFp32ToFp16P6__halfPfi : hostFun 0x0x401dd7, fat_cubin_handle = 1 +WARNING: No guarantee that PTX will be parsed for SM version 70 + _1.ptx:13 => (ptx_parser.cc:175) start_function + _1.ptx:13 => (ptx_parser.cc:144) init_directive_state + _1.ptx:13 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:13 => (ptx_parser.cc:144) init_directive_state + _1.ptx:13 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:13 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:13 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B32_TYPE + _1.ptx:14 => (ptx_parser.cc:189) add_function_name vprintf (extern) + _1.ptx:14 => (ptx_parser.cc:381) add_identifier "func_retval0" (0) +GPGPU-Sim PTX: allocating stack frame region for .param "func_retval0" from 0x0 to 0x4 + _1.ptx:14 => (ptx_parser.cc:144) init_directive_state + _1.ptx:15 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:15 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:15 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B64_TYPE + _1.ptx:15 => (ptx_parser.cc:381) add_identifier "vprintf_param_0" (1) +GPGPU-Sim PTX: allocating stack frame region for .param "vprintf_param_0" from 0x4 to 0xc + _1.ptx:15 => (ptx_parser.cc:577) add_function_arg "vprintf_param_0" + _1.ptx:15 => (ptx_parser.cc:219) add_directive + _1.ptx:15 => (ptx_parser.cc:144) init_directive_state + _1.ptx:16 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:16 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:16 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_local scalar_type_spec=B64_TYPE + _1.ptx:17 => (ptx_parser.cc:381) add_identifier "vprintf_param_1" (2) +GPGPU-Sim PTX: allocating stack frame region for .param "vprintf_param_1" from 0xc to 0x14 + _1.ptx:17 => (ptx_parser.cc:577) add_function_arg "vprintf_param_1" + _1.ptx:17 => (ptx_parser.cc:219) add_directive + _1.ptx:17 => (ptx_parser.cc:144) init_directive_state + _1.ptx:19 => (ptx_parser.cc:605) add_space_spec "global_space" + _1.ptx:19 => (ptx_parser.cc:590) add_alignment_spec + _1.ptx:19 => (ptx_parser.cc:631) add_scalar_type_spec "B8_TYPE" + _1.ptx:19 => (ptx_parser.cc:331) set_variable_type space_spec=global_space scalar_type_spec=B8_TYPE + _1.ptx:19 => (ptx_parser.cc:381) add_identifier "$str" (3) +GPGPU-Sim PTX: allocating global region for "$str" from 0x100 to 0x109 (global memory space) + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:883) add_literal_int + _1.ptx:19 => (ptx_parser.cc:319) add_variables + _1.ptx:19 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:175) start_function + _1.ptx:21 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:21 => (ptx_parser.cc:144) init_directive_state + _1.ptx:21 => (ptx_parser.cc:189) add_function_name _Z12wmma_exampleP6__halfS0_Pfiiiff (entrypoint) + _1.ptx:22 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:22 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:22 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:22 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0" (4) + _1.ptx:22 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_0" + _1.ptx:22 => (ptx_parser.cc:219) add_directive + _1.ptx:22 => (ptx_parser.cc:144) init_directive_state + _1.ptx:23 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:23 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:23 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:23 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1" (5) + _1.ptx:23 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_1" + _1.ptx:23 => (ptx_parser.cc:219) add_directive + _1.ptx:23 => (ptx_parser.cc:144) init_directive_state + _1.ptx:24 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:24 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:24 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U64_TYPE + _1.ptx:24 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2" (6) + _1.ptx:24 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_2" + _1.ptx:24 => (ptx_parser.cc:219) add_directive + _1.ptx:24 => (ptx_parser.cc:144) init_directive_state + _1.ptx:25 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:25 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:25 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:25 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3" (7) + _1.ptx:25 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_3" + _1.ptx:25 => (ptx_parser.cc:219) add_directive + _1.ptx:25 => (ptx_parser.cc:144) init_directive_state + _1.ptx:26 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:26 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:26 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:26 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4" (8) + _1.ptx:26 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_4" + _1.ptx:26 => (ptx_parser.cc:219) add_directive + _1.ptx:26 => (ptx_parser.cc:144) init_directive_state + _1.ptx:27 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:27 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:27 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=U32_TYPE + _1.ptx:27 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5" (9) + _1.ptx:27 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_5" + _1.ptx:27 => (ptx_parser.cc:219) add_directive + _1.ptx:27 => (ptx_parser.cc:144) init_directive_state + _1.ptx:28 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:28 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:28 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=F32_TYPE + _1.ptx:28 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_6" (10) + _1.ptx:28 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_6" + _1.ptx:28 => (ptx_parser.cc:219) add_directive + _1.ptx:28 => (ptx_parser.cc:144) init_directive_state + _1.ptx:29 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:29 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:29 => (ptx_parser.cc:331) set_variable_type space_spec=param_space_kernel scalar_type_spec=F32_TYPE + _1.ptx:30 => (ptx_parser.cc:381) add_identifier "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_7" (11) + _1.ptx:30 => (ptx_parser.cc:577) add_function_arg "_Z12wmma_exampleP6__halfS0_Pfiiiff_param_7" + _1.ptx:30 => (ptx_parser.cc:219) add_directive + _1.ptx:30 => (ptx_parser.cc:144) init_directive_state + _1.ptx:32 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:32 => (ptx_parser.cc:590) add_alignment_spec + _1.ptx:32 => (ptx_parser.cc:631) add_scalar_type_spec "B8_TYPE" + _1.ptx:32 => (ptx_parser.cc:331) set_variable_type space_spec=local_space scalar_type_spec=B8_TYPE + _1.ptx:32 => (ptx_parser.cc:381) add_identifier "__local_depot0" (12) +GPGPU-Sim PTX: allocating stack frame region for .local "__local_depot0" from 0x0 to 0x8 + _1.ptx:32 => (ptx_parser.cc:319) add_variables + _1.ptx:32 => (ptx_parser.cc:144) init_directive_state + _1.ptx:32 => (ptx_parser.cc:219) add_directive + _1.ptx:32 => (ptx_parser.cc:144) init_directive_state + _1.ptx:33 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:33 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:33 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:33 => (ptx_parser.cc:381) add_identifier "%SP" (13) + _1.ptx:33 => (ptx_parser.cc:319) add_variables + _1.ptx:33 => (ptx_parser.cc:144) init_directive_state + _1.ptx:33 => (ptx_parser.cc:219) add_directive + _1.ptx:33 => (ptx_parser.cc:144) init_directive_state + _1.ptx:34 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:34 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:34 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:34 => (ptx_parser.cc:381) add_identifier "%SPL" (14) + _1.ptx:34 => (ptx_parser.cc:319) add_variables + _1.ptx:34 => (ptx_parser.cc:144) init_directive_state + _1.ptx:34 => (ptx_parser.cc:219) add_directive + _1.ptx:34 => (ptx_parser.cc:144) init_directive_state + _1.ptx:35 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:35 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:35 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=PRED_TYPE + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p0" (15) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p1" (16) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p2" (17) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p3" (18) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p4" (19) + _1.ptx:35 => (ptx_parser.cc:381) add_identifier "%p5" (20) + _1.ptx:35 => (ptx_parser.cc:319) add_variables + _1.ptx:35 => (ptx_parser.cc:144) init_directive_state + _1.ptx:35 => (ptx_parser.cc:219) add_directive + _1.ptx:35 => (ptx_parser.cc:144) init_directive_state + _1.ptx:36 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:36 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:36 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=F32_TYPE + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f0" (21) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f1" (22) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f2" (23) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f3" (24) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f4" (25) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f5" (26) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f6" (27) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f7" (28) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f8" (29) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f9" (30) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f10" (31) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f11" (32) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f12" (33) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f13" (34) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f14" (35) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f15" (36) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f16" (37) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f17" (38) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f18" (39) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f19" (40) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f20" (41) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f21" (42) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f22" (43) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f23" (44) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f24" (45) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f25" (46) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f26" (47) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f27" (48) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f28" (49) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f29" (50) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f30" (51) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f31" (52) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f32" (53) + _1.ptx:36 => (ptx_parser.cc:381) add_identifier "%f33" (54) + _1.ptx:36 => (ptx_parser.cc:319) add_variables + _1.ptx:36 => (ptx_parser.cc:144) init_directive_state + _1.ptx:36 => (ptx_parser.cc:219) add_directive + _1.ptx:36 => (ptx_parser.cc:144) init_directive_state + _1.ptx:37 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:37 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:37 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B32_TYPE + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r0" (55) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r1" (56) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r2" (57) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r3" (58) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r4" (59) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r5" (60) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r6" (61) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r7" (62) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r8" (63) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r9" (64) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r10" (65) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r11" (66) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r12" (67) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r13" (68) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r14" (69) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r15" (70) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r16" (71) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r17" (72) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r18" (73) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r19" (74) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r20" (75) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r21" (76) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r22" (77) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r23" (78) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r24" (79) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r25" (80) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r26" (81) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r27" (82) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r28" (83) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r29" (84) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r30" (85) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r31" (86) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r32" (87) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r33" (88) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r34" (89) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r35" (90) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r36" (91) + _1.ptx:37 => (ptx_parser.cc:381) add_identifier "%r37" (92) + _1.ptx:37 => (ptx_parser.cc:319) add_variables + _1.ptx:37 => (ptx_parser.cc:144) init_directive_state + _1.ptx:37 => (ptx_parser.cc:219) add_directive + _1.ptx:37 => (ptx_parser.cc:144) init_directive_state + _1.ptx:38 => (ptx_parser.cc:605) add_space_spec "reg_space" + _1.ptx:38 => (ptx_parser.cc:631) add_scalar_type_spec "B64_TYPE" + _1.ptx:38 => (ptx_parser.cc:331) set_variable_type space_spec=reg_space scalar_type_spec=B64_TYPE + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd0" (93) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd1" (94) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd2" (95) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd3" (96) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd4" (97) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd5" (98) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd6" (99) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd7" (100) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd8" (101) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd9" (102) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd10" (103) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd11" (104) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd12" (105) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd13" (106) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd14" (107) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd15" (108) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd16" (109) + _1.ptx:38 => (ptx_parser.cc:381) add_identifier "%rd17" (110) + _1.ptx:38 => (ptx_parser.cc:319) add_variables + _1.ptx:38 => (ptx_parser.cc:144) init_directive_state + _1.ptx:38 => (ptx_parser.cc:219) add_directive + _1.ptx:38 => (ptx_parser.cc:144) init_directive_state + _1.ptx:41 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:41 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:41 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:41 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:41 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:41 => (ptx_parser.cc:144) init_directive_state + _1.ptx:42 => (ptx_parser.cc:605) add_space_spec "local_space" + _1.ptx:42 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:42 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:42 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:42 => (ptx_parser.cc:295) add_instruction: cvta + _1.ptx:42 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:42 => (ptx_parser.cc:144) init_directive_state + _1.ptx:43 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:43 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:43 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:43 => (ptx_parser.cc:929) add_address_operand + _1.ptx:43 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:43 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:43 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:43 => (ptx_parser.cc:144) init_directive_state + _1.ptx:44 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:44 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:44 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:44 => (ptx_parser.cc:929) add_address_operand + _1.ptx:44 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:44 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:44 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:44 => (ptx_parser.cc:144) init_directive_state + _1.ptx:45 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:45 => (ptx_parser.cc:631) add_scalar_type_spec "U64_TYPE" + _1.ptx:45 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:45 => (ptx_parser.cc:929) add_address_operand + _1.ptx:45 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:45 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:45 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:45 => (ptx_parser.cc:144) init_directive_state + _1.ptx:46 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:46 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:46 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:46 => (ptx_parser.cc:929) add_address_operand + _1.ptx:46 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:46 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:46 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:46 => (ptx_parser.cc:144) init_directive_state + _1.ptx:47 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:47 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:47 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:47 => (ptx_parser.cc:929) add_address_operand + _1.ptx:47 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:47 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:47 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:47 => (ptx_parser.cc:144) init_directive_state + _1.ptx:48 => (ptx_parser.cc:605) add_space_spec "param_space_unclassified" + _1.ptx:48 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:48 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:48 => (ptx_parser.cc:929) add_address_operand + _1.ptx:48 => (ptx_parser.cc:766) add_memory_operand + _1.ptx:48 => (ptx_parser.cc:295) add_instruction: ld + _1.ptx:48 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:48 => (ptx_parser.cc:144) init_directive_state + _1.ptx:50 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:50 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:50 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:50 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:50 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:50 => (ptx_parser.cc:144) init_directive_state + _1.ptx:52 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:52 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:52 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:52 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:52 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:52 => (ptx_parser.cc:144) init_directive_state + _1.ptx:53 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:53 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:53 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:53 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:53 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:53 => (ptx_parser.cc:144) init_directive_state + _1.ptx:54 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:54 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:54 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:54 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:54 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:54 => (ptx_parser.cc:144) init_directive_state + _1.ptx:55 => (ptx_parser.cc:672) add_option + _1.ptx:55 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:55 => (ptx_parser.cc:295) add_instruction: mad + _1.ptx:55 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:55 => (ptx_parser.cc:144) init_directive_state + _1.ptx:56 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:56 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:56 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:56 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:56 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:56 => (ptx_parser.cc:144) init_directive_state + _1.ptx:57 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:57 => (ptx_parser.cc:295) add_instruction: div + _1.ptx:57 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:57 => (ptx_parser.cc:144) init_directive_state + _1.ptx:58 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:58 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:58 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:58 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:58 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:58 => (ptx_parser.cc:144) init_directive_state + _1.ptx:59 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:59 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:59 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:59 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:59 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:59 => (ptx_parser.cc:144) init_directive_state + _1.ptx:60 => (ptx_parser.cc:631) add_scalar_type_spec "U32_TYPE" + _1.ptx:60 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:60 => (ptx_parser.cc:760) add_builtin_operand + _1.ptx:60 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:60 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:60 => (ptx_parser.cc:144) init_directive_state + _1.ptx:61 => (ptx_parser.cc:672) add_option + _1.ptx:61 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:61 => (ptx_parser.cc:295) add_instruction: mad + _1.ptx:61 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:61 => (ptx_parser.cc:144) init_directive_state + _1.ptx:62 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:62 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:62 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:62 => (ptx_parser.cc:883) add_literal_int + _1.ptx:62 => (ptx_parser.cc:295) add_instruction: shl + _1.ptx:62 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:62 => (ptx_parser.cc:144) init_directive_state + _1.ptx:63 => (ptx_parser.cc:631) add_scalar_type_spec "B32_TYPE" + _1.ptx:63 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:63 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:63 => (ptx_parser.cc:883) add_literal_int + _1.ptx:63 => (ptx_parser.cc:295) add_instruction: shl + _1.ptx:63 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:63 => (ptx_parser.cc:144) init_directive_state + _1.ptx:64 => (ptx_parser.cc:672) add_option + _1.ptx:64 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:64 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:64 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:64 => (ptx_parser.cc:144) init_directive_state + _1.ptx:65 => (ptx_parser.cc:672) add_option + _1.ptx:65 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:65 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:65 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:65 => (ptx_parser.cc:883) add_literal_int + _1.ptx:65 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:65 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:65 => (ptx_parser.cc:144) init_directive_state + _1.ptx:66 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:66 => (ptx_parser.cc:295) add_instruction: and + _1.ptx:66 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:66 => (ptx_parser.cc:144) init_directive_state + _1.ptx:67 => (ptx_parser.cc:672) add_option + _1.ptx:67 => (ptx_parser.cc:631) add_scalar_type_spec "S32_TYPE" + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:67 => (ptx_parser.cc:295) add_instruction: setp + _1.ptx:67 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:67 => (ptx_parser.cc:144) init_directive_state + _1.ptx:68 => (ptx_parser.cc:631) add_scalar_type_spec "PRED_TYPE" + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:68 => (ptx_parser.cc:295) add_instruction: and + _1.ptx:68 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:68 => (ptx_parser.cc:144) init_directive_state + _1.ptx:69 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:69 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:69 => (ptx_parser.cc:889) add_literal_float + _1.ptx:69 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:69 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:69 => (ptx_parser.cc:144) init_directive_state + _1.ptx:70 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:70 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:70 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:70 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:70 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:70 => (ptx_parser.cc:144) init_directive_state + _1.ptx:71 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:71 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:71 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:71 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:71 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:71 => (ptx_parser.cc:144) init_directive_state + _1.ptx:72 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:72 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:72 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:72 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:72 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:72 => (ptx_parser.cc:144) init_directive_state + _1.ptx:73 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:73 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:73 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:73 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:73 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:73 => (ptx_parser.cc:144) init_directive_state + _1.ptx:74 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:74 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:74 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:74 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:74 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:74 => (ptx_parser.cc:144) init_directive_state + _1.ptx:75 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:75 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:75 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:75 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:75 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:75 => (ptx_parser.cc:144) init_directive_state + _1.ptx:76 => (ptx_parser.cc:631) add_scalar_type_spec "F32_TYPE" + _1.ptx:76 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:76 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:76 => (ptx_parser.cc:295) add_instruction: mov + _1.ptx:76 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:76 => (ptx_parser.cc:144) init_directive_state + _1.ptx:77 => (ptx_parser.cc:659) add_pred + _1.ptx:77 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:77 => (ptx_parser.cc:295) add_instruction: bra + _1.ptx:77 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:77 => (ptx_parser.cc:144) init_directive_state + _1.ptx:78 => (ptx_parser.cc:672) add_option + _1.ptx:78 => (ptx_parser.cc:901) add_scalar_operand + _1.ptx:78 => (ptx_parser.cc:295) add_instruction: bra + _1.ptx:78 => (ptx_parser.cc:159) init_instruction_state + _1.ptx:78 => (ptx_parser.cc:144) init_directive_state + _1.ptx:80 => (ptx_parser.cc:643) add_label + _1.ptx:80 => (ptx_parser.cc:295) add_instruction: