From 7baae0e937143e0acfc71382eb432bdc42d4ca41 Mon Sep 17 00:00:00 2001 From: Nick Date: Mon, 18 Feb 2019 11:21:14 -0500 Subject: Fix spelling from adpative -> adaptive for volta cache config --- configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 +- src/gpgpu-sim/gpu-sim.cc | 4 ++-- src/gpgpu-sim/shader.cc | 2 +- src/gpgpu-sim/shader.h | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 8ed4cd0..b283095 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -75,7 +75,7 @@ # if the assigned shd mem = 0, then L1 cache = 128KB # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x # disable this mode in case of multi kernels/apps execution --adpative_volta_cache_config 1 +-adaptive_volta_cache_config 1 # Volta unified cache has four ports -mem_unit_ports 4 -gpgpu_cache:dl1 S:4:128:64,L:L:s:N:L,A:256:8,16:0,32 diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index ec570bf..abc2dd6 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -315,8 +315,8 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size, "Size of shared memory per shader core (default 16kB)", "16384"); - option_parser_register(opp, "-adpative_volta_cache_config", OPT_BOOL, &adpative_volta_cache_config, - "adpative_volta_cache_config", + option_parser_register(opp, "-adaptive_volta_cache_config", OPT_BOOL, &adaptive_volta_cache_config, + "adaptive_volta_cache_config", "0"); option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_sizeDefault, "Size of shared memory per shader core (default 16kB)", diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 3db988b..2cecd0c 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -2949,7 +2949,7 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const abort(); } - if(adpative_volta_cache_config && !k.volta_cache_config_set) { + if(adaptive_volta_cache_config && !k.volta_cache_config_set) { //For Volta, we assign the remaining shared memory to L1 cache //For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x unsigned total_shmed = kernel_info->smem * result; diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 9abd223..473d6b0 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -1523,7 +1523,7 @@ struct shader_core_config : public core_config //Jin: concurrent kernel on sm bool gpgpu_concurrent_kernel_sm; - bool adpative_volta_cache_config; + bool adaptive_volta_cache_config; }; struct shader_core_stats_pod { -- cgit v1.3 From 15d3d23cd13913eea599b0d88f14a6f2925f6da9 Mon Sep 17 00:00:00 2001 From: Gyeonghwan Hong Date: Wed, 10 Apr 2019 18:12:19 +0900 Subject: Fix indentation bug of AerialVision --- aerialvision/organizedata.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/aerialvision/organizedata.py b/aerialvision/organizedata.py index 0d6cd91..090b90f 100644 --- a/aerialvision/organizedata.py +++ b/aerialvision/organizedata.py @@ -97,7 +97,7 @@ def organizedata(fileVars): 'sparse':OrganizeSparse, # Vector data with 2D index (used by DRAM access stats) 'custom':0 } - data_type_char = {int:'I', float:'f'} + data_type_char = {int:'I', float:'f'} print "Organizing data into internal format..." -- cgit v1.3