From a479efd869ebd1aac79aae3bd991012540bfb010 Mon Sep 17 00:00:00 2001 From: Inderpreet Singh Date: Wed, 28 Dec 2011 23:00:37 -0800 Subject: Fix for Bug 117 - Cannot disable L2 caches. Disabling L2 caches bypasses L2 cache. Note that memory partition is still clocked at the L2 frequency. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11235] --- src/gpgpu-sim/gpu-sim.cc | 4 ++-- src/gpgpu-sim/l2cache.cc | 37 ++++++++++++++++++++++++------------- 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 3b060a1..447c040 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -614,7 +614,7 @@ void gpgpu_sim::gpu_print_stat() const m_memory_stats->print(stdout); for (unsigned i=0;im_n_mem;i++) m_memory_partition_unit[i]->print(stdout); - if (m_memory_config->m_L2_config.get_num_lines()) + if (!m_memory_config->m_L2_config.disabled() && m_memory_config->m_L2_config.get_num_lines()) L2c_print_cache_stat(); if (m_config.gpgpu_cflog_interval != 0) { spill_log_to_file (stdout, 1, gpu_sim_cycle); @@ -862,7 +862,7 @@ void gpgpu_sim::cycle() else all_threads_complete = 0 ; } - if (all_threads_complete) { + if (all_threads_complete && !m_memory_config->m_L2_config.disabled() ) { printf("Flushed L2 caches...\n"); if (m_memory_config->m_L2_config.get_num_lines()) { int dlc = 0; diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index 914e449..9bee822 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -72,7 +72,9 @@ memory_partition_unit::memory_partition_unit( unsigned partition_id, snprintf(L2c_name, 32, "L2_bank_%03d", m_id); m_L2interface = new L2interface(this); m_mf_allocator = new partition_mf_allocator(config); - m_L2cache = new data_cache(L2c_name,m_config->m_L2_config,-1,-1,m_L2interface,m_mf_allocator,IN_PARTITION_L2_MISS_QUEUE); + + if(!m_config->m_L2_config.disabled()) + m_L2cache = new data_cache(L2c_name,m_config->m_L2_config,-1,-1,m_L2interface,m_mf_allocator,IN_PARTITION_L2_MISS_QUEUE); unsigned int icnt_L2; unsigned int L2_dram; @@ -99,17 +101,20 @@ memory_partition_unit::~memory_partition_unit() void memory_partition_unit::cache_cycle( unsigned cycle ) { - // L2 fill responses - if ( m_L2cache->access_ready() && !m_L2_icnt_queue->full() ) { - mem_fetch *mf = m_L2cache->next_access(); - mf->set_reply(); - mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); - m_L2_icnt_queue->push(mf); + // L2 fill responses + if( !m_config->m_L2_config.disabled()) { + if ( m_L2cache->access_ready() && !m_L2_icnt_queue->full() ) { + mem_fetch *mf = m_L2cache->next_access(); + mf->set_reply(); + mf->set_status(IN_PARTITION_L2_TO_ICNT_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); + m_L2_icnt_queue->push(mf); + } } + // DRAM to L2 (texture) and icnt (not texture) if ( !m_dram_L2_queue->empty() ) { mem_fetch *mf = m_dram_L2_queue->top(); - if ( m_L2cache->waiting_for_fill(mf) ) { + if ( !m_config->m_L2_config.disabled() && m_L2cache->waiting_for_fill(mf) ) { mf->set_status(IN_PARTITION_L2_FILL_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); m_L2cache->fill(mf,gpu_sim_cycle+gpu_tot_sim_cycle); m_dram_L2_queue->pop(); @@ -121,12 +126,16 @@ void memory_partition_unit::cache_cycle( unsigned cycle ) } // prior L2 misses inserted into m_L2_dram_queue here - m_L2cache->cycle(); + if( !m_config->m_L2_config.disabled() ) + m_L2cache->cycle(); // new L2 texture accesses and/or non-texture accesses if ( !m_L2_dram_queue->full() && !m_icnt_L2_queue->empty() ) { mem_fetch *mf = m_icnt_L2_queue->top(); - if ( (m_config->m_L2_texure_only && mf->istexture()) || (!m_config->m_L2_texure_only) ) { + if ( !m_config->m_L2_config.disabled() && + ( (m_config->m_L2_texure_only && mf->istexture()) || (!m_config->m_L2_texure_only) ) + ) { + // L2 is enabled and access is for L2 if ( !m_L2_icnt_queue->full() ) { std::list events; enum cache_request_status status = m_L2cache->access(mf->get_partition_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle,events); @@ -160,7 +169,7 @@ void memory_partition_unit::cache_cycle( unsigned cycle ) } } } else { - // non-texture access + // L2 is disabled or non-texture access to texture-only L2 mf->set_status(IN_PARTITION_L2_TO_DRAM_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); m_L2_dram_queue->push(mf); m_icnt_L2_queue->pop(); @@ -184,7 +193,8 @@ bool memory_partition_unit::full() const void memory_partition_unit::print_cache_stat(unsigned &accesses, unsigned &misses) const { FILE *fp = stdout; - m_L2cache->print(fp,accesses,misses); + if( !m_config->m_L2_config.disabled() ) + m_L2cache->print(fp,accesses,misses); } void memory_partition_unit::print( FILE *fp ) const @@ -199,7 +209,8 @@ void memory_partition_unit::print( FILE *fp ) const fprintf(fp," \n"); } } - m_L2cache->display_state(fp); + if( !m_config->m_L2_config.disabled() ) + m_L2cache->display_state(fp); m_dram->print(fp); } -- cgit v1.3