From b013499f5f490086c7a7c5c28b04346e79ab2635 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 29 Aug 2018 19:10:47 -0400
Subject: improving code quality 2

---
 src/gpgpu-sim/addrdec.cc | 28 +++++++++++++++++++---------
 src/gpgpu-sim/addrdec.h  |  1 +
 src/gpgpu-sim/dram.cc    | 35 ++++++++++++++++++++++++-----------
 src/gpgpu-sim/dram.h     | 11 +++++++++++
 4 files changed, 55 insertions(+), 20 deletions(-)

diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc
index e7e27b7..8651869 100644
--- a/src/gpgpu-sim/addrdec.cc
+++ b/src/gpgpu-sim/addrdec.cc
@@ -111,11 +111,14 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_
 			//Do nothing
 			break;
 		case BITWISE_PERMUTATION:
+		{
 			assert(!gap);
 			tlx->chip = (tlx->chip) ^ (tlx->row & (m_n_channel-1));
 			assert(tlx->chip < m_n_channel);
 			break;
+		}
 		case IPOLY:
+		{
 		    /*
 			* Set Indexing function from "Pseudo-randomly interleaved memory."
 			* Rau, B. R et al.
@@ -143,22 +146,29 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_
 			}
 			assert(tlx->chip < m_n_channel);
 			break;
-		case CUSTOM:
+		}
+		case PAE:
 		{
-			//random selected bits
-			//do you custom hashing function here, similar to
+			//Page Address Entropy
+			//random selected bits from the page and bank bits
+			//similar to
 			//Liu, Yuxi, et al. "Get Out of the Valley: Power-Efficient Address Mapping for GPUs." ISCA 2018
-			std::bitset<64> b(tlx->row);
+			std::bitset<64> a(tlx->row);
 			std::bitset<5> chip(tlx->chip);
-			chip[0] = b[13]^b[10]^b[9]^b[5]^b[0]^chip[0];
-			chip[1] = b[12]^b[11]^b[6]^b[1]^chip[1];
-			chip[2] = b[14]^b[9]^b[8]^b[7]^b[2]^chip[2];
-			chip[3] = b[11]^b[10]^b[8]^b[3]^chip[3];
-			chip[4] = b[12]^b[9]^b[8]^b[5]^b[4]^chip[4];
+			std::bitset<4> b(tlx->bk);
+			chip[0] = a[13]^a[10]^a[9]^a[5]^a[0]^b[3]^b[0]^chip[0];
+			chip[1] = a[12]^a[11]^a[6]^a[1]^b[3]^b[2]^b[1]^chip[1];
+			chip[2] = a[14]^a[9]^a[8]^a[7]^a[2]^b[1]^chip[2];
+			chip[3] = a[11]^a[10]^a[8]^a[3]^b[2]^b[3]^chip[3];
+			chip[4] = a[12]^a[9]^a[8]^a[5]^a[4]^b[1]^b[0]^chip[4];
 			tlx->chip = chip.to_ulong();
 			assert(tlx->chip < m_n_channel);
 			break;
 		}
+		case CUSTOM:
+			/* No custom set function implemented */
+			//Do you custom index here
+			break;
 		default:
 			 assert("\nUndefined set index function.\n" && 0);
 			 break;
diff --git a/src/gpgpu-sim/addrdec.h b/src/gpgpu-sim/addrdec.h
index a18ff63..bdc5fec 100644
--- a/src/gpgpu-sim/addrdec.h
+++ b/src/gpgpu-sim/addrdec.h
@@ -39,6 +39,7 @@ enum partition_index_function{
 	CONSECUTIVE = 0,
 	BITWISE_PERMUTATION,
 	IPOLY,
+	PAE,
     CUSTOM
 };
 
diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc
index ac63327..6c11b43 100644
--- a/src/gpgpu-sim/dram.cc
+++ b/src/gpgpu-sim/dram.cc
@@ -199,15 +199,28 @@ dram_req_t::dram_req_t( class mem_fetch *mf, unsigned banks, unsigned dram_bnk_i
 
    const addrdec_t &tlx = mf->get_tlx_addr();
 
-   if(dram_bnk_indexing_policy == 0) {
-	   bk = tlx.bk;
-   }
-    else if(dram_bnk_indexing_policy == 1) {
-    	 int lbank = log2(banks);
-    	 bk  = tlx.bk ^ (tlx.row & ((1<<lbank)-1));
-    }
-    else
-    	assert(1);
+    switch(dram_bnk_indexing_policy){
+		case LINEAR_BK_INDEX:
+		{
+			bk = tlx.bk;
+			break;
+		}
+		case BITWISE_XORING_BK_INDEX:
+		{
+			//xoring bank bits with lower bits of the page
+			int lbank = log2(banks);
+			bk  = tlx.bk ^ (tlx.row & ((1<<lbank)-1));
+			break;
+		}
+		case CUSTOM_BK_INDEX:
+	        /* No custom set function implemented */
+			//Do you custom index here
+			break;
+		default:
+			 assert("\nUndefined bank index function.\n" && 0);
+			 break;
+	}
+
 
    row = tlx.row; 
    col = tlx.col; 
@@ -883,10 +896,10 @@ void dram_t::set_dram_power_stats(	unsigned &cmd,
 
 unsigned dram_t::get_bankgrp_number(unsigned i)
 {
-	if(m_config->dram_bnkgrp_indexing_policy == 0) { //higher bits
+	if(m_config->dram_bnkgrp_indexing_policy == HIGHER_BITS) { //higher bits
 		return i>>m_config->bk_tag_length;
 	}
-	else if (m_config->dram_bnkgrp_indexing_policy == 1) { //lower bits
+	else if (m_config->dram_bnkgrp_indexing_policy == LOWER_BITS) { //lower bits
 		return i&((m_config->nbkgrp-1));
 	}
 	else {
diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h
index 0d4c0e7..965936b 100644
--- a/src/gpgpu-sim/dram.h
+++ b/src/gpgpu-sim/dram.h
@@ -93,6 +93,17 @@ struct bank_t
    unsigned int bkgrpindex;
 };
 
+enum bank_index_function{
+	LINEAR_BK_INDEX = 0,
+	BITWISE_XORING_BK_INDEX,
+    CUSTOM_BK_INDEX
+};
+
+enum bank_grp_bits_position{
+	HIGHER_BITS = 0,
+	LOWER_BITS
+};
+
 struct mem_fetch;
 
 class dram_t 
-- 
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