From bd14ce38470dfc54c690db09f00ee5c18b577575 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Fri, 23 Aug 2019 12:26:46 -0400 Subject: fixing CUDA 10 fail --- src/gpgpu-sim/gpu-sim.h | 3 --- src/gpgpu-sim/l2cache.cc | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index f841bf9..76c7a06 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -298,9 +298,6 @@ class memory_config { gpgpu_context* gpgpu_ctx; }; -// global counters and flags (please try not to add to this list!!!) -extern unsigned long long gpu_sim_cycle; -extern unsigned long long gpu_tot_sim_cycle; extern bool g_interactive_debugger_enabled; diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index f1672f9..39a5812 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -257,7 +257,7 @@ void memory_partition_unit::simple_dram_model_cycle() d.req = mf; d.ready_cycle = m_gpu->gpu_sim_cycle+m_gpu->gpu_tot_sim_cycle + m_config->dram_latency; m_dram_latency_queue.push_back(d); - mf->set_status(IN_PARTITION_DRAM_LATENCY_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle); + mf->set_status(IN_PARTITION_DRAM_LATENCY_QUEUE,m_gpu->gpu_sim_cycle+m_gpu->gpu_tot_sim_cycle); m_arbitration_metadata.borrow_credit(spid); break; // the DRAM should only accept one request per cycle } -- cgit v1.3