From c58ee08f0e7ec7c7ee6794d8ce2616ed1b0c10f2 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Wed, 10 Oct 2018 17:56:50 -0400
Subject: fixing freq of TITANV

---
 configs/3.x-cfgs/SM7_TITANV/gpgpusim.config | 4 ++--
 configs/4.x-cfgs/SM7_TITANV/gpgpusim.config | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
index 738c881..aefb04a 100644
--- a/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -27,9 +27,9 @@
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
 # Pascal NVIDIA GP100  clock domains are adopted from 
 # https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
 # boost mode
-# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0
+# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
index b4576dc..41757f8 100644
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -27,9 +27,9 @@
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
 # Volta NVIDIA GV100  clock domains are adopted from 
 # https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
+-gpgpu_clock_domains 1200.0:2000.0:1200.0:850.0
 # boost mode
-# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0
+# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
-- 
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