From d3316efe70f6007d15f81f828bb5fc82bc5c86d4 Mon Sep 17 00:00:00 2001
From: Mahmoud <abdallm@purdue.edu>
Date: Fri, 15 Nov 2019 20:03:18 -0500
Subject: invalidate l1 cache at membar

---
 src/gpgpu-sim/shader.cc | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 926453a..19f8e72 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -3470,6 +3470,14 @@ bool shader_core_ctx::warp_waiting_at_mem_barrier( unsigned warp_id )
       return false;
    if( !m_scoreboard->pendingWrites(warp_id) ) {
       m_warp[warp_id].clear_membar();
+      if (m_gpu->get_config().gpgpu_flush_l1_cache) {
+		  //invalidate L1 cache
+		  //Based on Nvidia Doc, at MEM barrier, we have to
+    	  //(1) wait for all pending writes till they are acked
+    	  //(2) invalidate L1 cache to ensure coherence and avoid reading stall data
+		  cache_invalidate();
+		  //TO DO: you need to stall the SM for 5k cycles.
+      }
       return false;
    }
    return true;
-- 
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