From 4232b85d1ecd2f73cfc9e4226468c4b369476ca9 Mon Sep 17 00:00:00 2001 From: Wilson Fung Date: Tue, 30 Jul 2013 16:05:03 -0800 Subject: Updated the Fermi configurations to have two L2 banks per memory partition, and the data port in each bank is limited to 32B/cycle. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16700] --- CHANGES | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'CHANGES') diff --git a/CHANGES b/CHANGES index d805f37..d8c65bf 100644 --- a/CHANGES +++ b/CHANGES @@ -43,6 +43,12 @@ Version 3.2.1+edits (development branch) versus 3.2.1 that exceed the data port width (but still fit within a cache line) will occupy the cache for multiple cycles. This allows us to decouple the L2 cache bandwidth from the interconnect network port bandwidth. +- Updated configurations for Geforce GTX 480 and Tesla C2050 to have two + sub-partitions in every memory partition. The L2 cache bank in each + sub-partition has half the capacity of the original L2 cache bank. Each L2 + cache bank is configured to access at most 32B/cycle. With twice the number + of connections to the memory partitions, the interconnection network now runs + at half of its original speed. - Bug Fixes: - Fixed the flit count sent to GPUWattch for atomic operations. - Fix for Bug 51 - Updated the function declaration of -- cgit v1.3