From 944f6dbf23d792dde360d3a4f2334de3b541de52 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 27 Aug 2018 20:28:24 -0400 Subject: fixing ead/write buffer and new configs files --- configs/3.x-cfgs/GTX480/gpgpusim.config | 133 ++++++++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 configs/3.x-cfgs/GTX480/gpgpusim.config (limited to 'configs/3.x-cfgs/GTX480/gpgpusim.config') diff --git a/configs/3.x-cfgs/GTX480/gpgpusim.config b/configs/3.x-cfgs/GTX480/gpgpusim.config new file mode 100644 index 0000000..436cb41 --- /dev/null +++ b/configs/3.x-cfgs/GTX480/gpgpusim.config @@ -0,0 +1,133 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 20 + + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 15 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 6 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Fermi clock domains +#-gpgpu_clock_domains ::: +# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided +# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 +-gpgpu_clock_domains 700.0:700.0:700.0:924.0 + +# shader core pipeline config +-gpgpu_shader_registers 32768 + +# This implies a maximum of 48 warps/SM +-gpgpu_shader_core_pipeline 1536:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 2,1,1,2,1,1,2 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,1,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,16,8,8,130 + + +# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_shmem_size 49152 + +# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected +#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 +#-gpgpu_shmem_size 16384 + +# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache +-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 + +-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_num_reg_banks 16 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +-gpgpu_max_insn_issue_per_warp 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 116 + +# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS + +# GDDR5 timing from hynix H5GQ1H24AFR +# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 -- cgit v1.3 From afb28556c4f08e4daca17525e7e377d9aaec0ee5 Mon Sep 17 00:00:00 2001 From: tgrogers Date: Sun, 7 Oct 2018 21:41:35 -0400 Subject: Unrolling Aksahy's stats - as they seem to be really screwing things up. --- configs/3.x-cfgs/GTX480/gpgpusim.config | 2 +- src/abstract_hardware_model.h | 7 ----- src/cuda-sim/cuda-sim.cc | 46 +++++++++++++++++---------------- src/cuda-sim/cuda-sim.h | 2 -- src/cuda-sim/opcodes.def | 2 -- src/gpgpu-sim/gpu-sim.cc | 10 +++---- src/gpgpu-sim/gpu-sim.h | 3 --- src/gpgpu-sim/l2cache.cc | 20 +++----------- src/gpgpu-sim/l2cache.h | 8 ++---- src/gpgpu-sim/shader.cc | 35 +------------------------ src/gpgpu-sim/shader.h | 22 +--------------- src/gpgpusim_entrypoint.cc | 3 --- src/stream_manager.cc | 2 +- 13 files changed, 38 insertions(+), 124 deletions(-) (limited to 'configs/3.x-cfgs/GTX480/gpgpusim.config') diff --git a/configs/3.x-cfgs/GTX480/gpgpusim.config b/configs/3.x-cfgs/GTX480/gpgpusim.config index eb25bc3..436cb41 100644 --- a/configs/3.x-cfgs/GTX480/gpgpusim.config +++ b/configs/3.x-cfgs/GTX480/gpgpusim.config @@ -1,5 +1,5 @@ # functional simulator specification --gpgpu_ptx_instruction_classification 1 +-gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 20 diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index 35f289c..e708fa7 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -808,7 +808,6 @@ public: arch_reg.dst[i] = -1; } isize=0; - op_classification = 0; } bool valid() const { return m_decoded; } virtual void print_insn( FILE *fp ) const @@ -827,7 +826,6 @@ public: address_type pc; // program counter address of instruction unsigned isize; // size of instruction in bytes op_type op; // opcode (uarch visible) - int op_classification; // classification of opcode for statistics purpopses barrier_type bar_type; reduction_type red_type; @@ -1035,11 +1033,6 @@ public: return cycles > 0; } - unsigned get_cycles() - { - return cycles; - } - void print( FILE *fout ) const; unsigned get_uid() const { return m_uid; } diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 02cd395..93bbc1d 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -52,10 +52,8 @@ int gpgpu_ptx_instruction_classification; void ** g_inst_classification_stat = NULL; -void ** g_inst_mem_classification_stat = NULL; void ** g_inst_op_classification_stat= NULL; int g_ptx_kernel_count = -1; // used for classification stat collection purposes -int g_ptx_kernel_count_prev = -1; // used for classification stat collection purposes int g_debug_execution = 0; int g_debug_thread_uid = 0; addr_t g_debug_pc = 0xBEEF1518; @@ -1243,16 +1241,12 @@ void init_inst_classification_stat() #define MAX_CLASS_KER 1024 char kernelname[MAX_CLASS_KER] =""; if (!g_inst_classification_stat) g_inst_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); - snprintf(kernelname, MAX_CLASS_KER, "Kernel %d INST Classification",g_ptx_kernel_count ); + snprintf(kernelname, MAX_CLASS_KER, "Kernel %d Classification\n",g_ptx_kernel_count ); assert( g_ptx_kernel_count < MAX_CLASS_KER ) ; // a static limit on number of kernels increase it if it fails! g_inst_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,20); - if (!g_inst_mem_classification_stat) g_inst_mem_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); - snprintf(kernelname, MAX_CLASS_KER, "Kernel %d MEM Classification",g_ptx_kernel_count ); - g_inst_mem_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,20); if (!g_inst_op_classification_stat) g_inst_op_classification_stat = (void**)calloc(MAX_CLASS_KER, sizeof(void*)); - snprintf(kernelname, MAX_CLASS_KER, "Kernel %d OP Classification",g_ptx_kernel_count ); + snprintf(kernelname, MAX_CLASS_KER, "Kernel %d OP Classification\n",g_ptx_kernel_count ); g_inst_op_classification_stat[g_ptx_kernel_count] = StatCreate(kernelname,1,100); - g_ptx_kernel_count_prev++; } static unsigned get_tex_datasize( const ptx_instruction *pI, ptx_thread_info *thread ) @@ -1330,17 +1324,6 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) delete pJ; pI = pI_saved; - if ( gpgpu_ptx_instruction_classification ) { - init_inst_classification_stat(); - if (op_classification) { - StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], op_classification); - inst.op_classification = op_classification; - } - if (pI->get_space().get_type()) - StatAddSample( g_inst_mem_classification_stat[g_ptx_kernel_count], ( int )pI->get_space().get_type()); - StatAddSample( g_inst_op_classification_stat[g_ptx_kernel_count], (int) pI->get_opcode() ); - } - // Run exit instruction if exit option included if(pI->is_exit()) exit_impl(pI,this); @@ -1426,6 +1409,27 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id) if(!(this->m_functionalSimulationMode)) ptx_file_line_stats_add_exec_count(pI); + if ( gpgpu_ptx_instruction_classification ) { + init_inst_classification_stat(); + unsigned space_type=0; + switch ( pI->get_space().get_type() ) { + case global_space: space_type = 10; break; + case local_space: space_type = 11; break; + case tex_space: space_type = 12; break; + case surf_space: space_type = 13; break; + case param_space_kernel: + case param_space_local: + space_type = 14; break; + case shared_space: space_type = 15; break; + case const_space: space_type = 16; break; + default: + space_type = 0 ; + break; + } + StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], op_classification); + if (space_type) StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], ( int )space_type); + StatAddSample( g_inst_op_classification_stat[g_ptx_kernel_count], (int) pI->get_opcode() ); + } if ( (g_ptx_sim_num_insn % 100000) == 0 ) { dim3 ctaid = get_ctaid(); dim3 tid = get_tid(); @@ -1845,10 +1849,8 @@ void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL ) //******PRINTING******* printf( "GPGPU-Sim: Done functional simulation (%u instructions simulated).\n", g_ptx_sim_num_insn ); - fflush(stdout); if ( gpgpu_ptx_instruction_classification ) { - StatDisp ( g_inst_classification_stat[g_ptx_kernel_count]); - StatDisp ( g_inst_mem_classification_stat[g_ptx_kernel_count]); + StatDisp( g_inst_classification_stat[g_ptx_kernel_count]); StatDisp ( g_inst_op_classification_stat[g_ptx_kernel_count]); } diff --git a/src/cuda-sim/cuda-sim.h b/src/cuda-sim/cuda-sim.h index ef9549f..958daba 100644 --- a/src/cuda-sim/cuda-sim.h +++ b/src/cuda-sim/cuda-sim.h @@ -44,10 +44,8 @@ extern int g_ptx_sim_mode; extern int g_debug_execution; extern int g_debug_thread_uid; extern void ** g_inst_classification_stat; -extern void ** g_inst_mem_classification_stat; extern void ** g_inst_op_classification_stat; extern int g_ptx_kernel_count; // used for classification stat collection purposes -extern int g_ptx_kernel_count_prev; // used for classification stat collection purposes void ptx_opcocde_latency_options (option_parser_t opp); extern class kernel_info_t *gpgpu_opencl_ptx_sim_init_grid(class function_info *entry, diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index ccf64d8..e1b1422 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -35,9 +35,7 @@ SFU 4 Mem(except Tex) 5 Tex 6 Nop 7 -Breakpoint 9 Other 10 -Scalar video 11 */ OP_DEF(ABS_OP,abs_impl,"abs",1,1) OP_DEF(ADD_OP,add_impl,"add",1,1) diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index e437c63..08d4525 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -463,7 +463,7 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) "1"); option_parser_register(opp, "-gpgpu_ptx_instruction_classification", OPT_INT32, &gpgpu_ptx_instruction_classification, - "if enabled will classify ptx instruction types per kernel (Max 1024 kernels now)", + "if enabled will classify ptx instruction types per kernel (Max 255 kernels now)", "0"); option_parser_register(opp, "-gpgpu_ptx_sim_mode", OPT_INT32, &g_ptx_sim_mode, "Select between Performance (default) or Functional simulation (1)", @@ -686,7 +686,7 @@ gpgpu_sim::gpgpu_sim( const gpgpu_sim_config &config ) m_memory_partition_unit = new memory_partition_unit*[m_memory_config->m_n_mem]; m_memory_sub_partition = new memory_sub_partition*[m_memory_config->m_n_mem_sub_partition]; for (unsigned i=0;im_n_mem;i++) { - m_memory_partition_unit[i] = new memory_partition_unit(i, m_memory_config, m_memory_stats, this); + m_memory_partition_unit[i] = new memory_partition_unit(i, m_memory_config, m_memory_stats); for (unsigned p = 0; p < m_memory_config->m_n_sub_partition_per_memory_channel; p++) { unsigned submpid = i * m_memory_config->m_n_sub_partition_per_memory_channel + p; m_memory_sub_partition[submpid] = m_memory_partition_unit[i]->get_sub_partition(p); @@ -1069,7 +1069,6 @@ void gpgpu_sim::gpu_print_stat() shader_print_scheduler_stat( stdout, false ); m_shader_stats->print(stdout); - m_power_stats->print(stdout); #ifdef GPGPUSIM_POWER_MODEL if(m_config.g_power_simulation_enabled){ m_gpgpusim_wrapper->print_power_kernel_stats(gpu_sim_cycle, gpu_tot_sim_cycle, gpu_tot_sim_insn + gpu_sim_insn, kernel_info_str, true ); @@ -1122,9 +1121,8 @@ void gpgpu_sim::gpu_print_stat() insn_warp_occ_print(stdout); } if ( gpgpu_ptx_instruction_classification ) { - StatDisp( g_inst_classification_stat[g_ptx_kernel_count_prev]); - StatDisp( g_inst_mem_classification_stat[g_ptx_kernel_count_prev]); - StatDisp( g_inst_op_classification_stat[g_ptx_kernel_count_prev]); + StatDisp( g_inst_classification_stat[g_ptx_kernel_count]); + StatDisp( g_inst_op_classification_stat[g_ptx_kernel_count]); } #ifdef GPGPUSIM_POWER_MODEL diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index f9b5dad..1778008 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -36,7 +36,6 @@ #include #include #include -#include #include @@ -429,8 +428,6 @@ public: void perf_memcpy_to_gpu( size_t dst_start_addr, size_t count ); - std::unordered_set data_footprint_stats; - //The next three functions added to be used by the functional simulation function //! Get shader core configuration diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc index 596e07c..25da107 100644 --- a/src/gpgpu-sim/l2cache.cc +++ b/src/gpgpu-sim/l2cache.cc @@ -62,16 +62,15 @@ mem_fetch * partition_mf_allocator::alloc(new_addr_type addr, mem_access_type ty memory_partition_unit::memory_partition_unit( unsigned partition_id, const struct memory_config *config, - class memory_stats_t *stats, - class gpgpu_sim *gpu) -: m_id(partition_id), m_config(config), m_stats(stats), m_arbitration_metadata(config), m_gpu(gpu) + class memory_stats_t *stats ) +: m_id(partition_id), m_config(config), m_stats(stats), m_arbitration_metadata(config) { m_dram = new dram_t(m_id,m_config,m_stats,this); m_sub_partition = new memory_sub_partition*[m_config->m_n_sub_partition_per_memory_channel]; for (unsigned p = 0; p < m_config->m_n_sub_partition_per_memory_channel; p++) { unsigned sub_partition_id = m_id * m_config->m_n_sub_partition_per_memory_channel + p; - m_sub_partition[p] = new memory_sub_partition(sub_partition_id, m_config, stats, m_gpu); + m_sub_partition[p] = new memory_sub_partition(sub_partition_id, m_config, stats); } } @@ -311,13 +310,11 @@ void memory_partition_unit::print( FILE *fp ) const memory_sub_partition::memory_sub_partition( unsigned sub_partition_id, const struct memory_config *config, - class memory_stats_t *stats , - class gpgpu_sim *gpu) + class memory_stats_t *stats ) { m_id = sub_partition_id; m_config=config; m_stats=stats; - m_gpu=gpu; m_memcpy_cycle_offset = 0; assert(m_id < m_config->m_n_mem_sub_partition); @@ -414,15 +411,6 @@ void memory_sub_partition::cache_cycle( unsigned cycle ) bool read_sent = was_read_sent(events); MEM_SUBPART_DPRINTF("Probing L2 cache Address=%llx, status=%u\n", mf->get_addr(), status); - if ( (mf->get_access_type() == GLOBAL_ACC_R) || - (mf->get_access_type() == GLOBAL_ACC_W) || - (mf->get_access_type() == LOCAL_ACC_R) || - (mf->get_access_type() == LOCAL_ACC_W) || - (mf->get_access_type() == CONST_ACC_R) ) { - if (!m_gpu->data_footprint_stats.count(mf->get_addr())) - m_gpu->data_footprint_stats.insert(mf->get_addr()); - } - if ( status == HIT ) { if( !write_sent ) { // L2 cache replies diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index 685b1d3..18c0a8b 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -58,7 +58,7 @@ private: class memory_partition_unit { public: - memory_partition_unit( unsigned partition_id, const struct memory_config *config, class memory_stats_t *stats , class gpgpu_sim *gpu); + memory_partition_unit( unsigned partition_id, const struct memory_config *config, class memory_stats_t *stats ); ~memory_partition_unit(); bool busy() const; @@ -93,8 +93,6 @@ public: unsigned get_mpid() const { return m_id; } - gpgpu_sim *m_gpu; - private: unsigned m_id; @@ -147,7 +145,7 @@ private: class memory_sub_partition { public: - memory_sub_partition( unsigned sub_partition_id, const struct memory_config *config, class memory_stats_t *stats, class gpgpu_sim *gpu); + memory_sub_partition( unsigned sub_partition_id, const struct memory_config *config, class memory_stats_t *stats ); ~memory_sub_partition(); unsigned get_id() const { return m_id; } @@ -188,8 +186,6 @@ public: m_memcpy_cycle_offset += 1; } - gpgpu_sim *m_gpu; - private: // data unsigned m_id; //< the global sub partition ID diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 80ac07e..0e2e1c2 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -438,22 +438,6 @@ void shader_core_stats::print( FILE* fout ) const fprintf(fout,"gpgpu_n_mem_texture = %d\n", gpgpu_n_mem_texture); fprintf(fout,"gpgpu_n_mem_const = %d\n", gpgpu_n_mem_const); - fprintf(fout,"gpgpu_mem_divergence_hist "); - gpgpu_mem_divergence_hist->fprint(fout); - fprintf(fout,"\n"); - fprintf(fout,"gpgpu_gmem_ld_divergence_hist "); - gpgpu_gmem_ld_divergence_hist->fprint(fout); - fprintf(fout,"\n"); - fprintf(fout,"gpgpu_gmem_st_divergence_hist "); - gpgpu_gmem_st_divergence_hist->fprint(fout); - fprintf(fout,"\n"); - fprintf(fout,"gpgpu_shmem_divergence_hist "); - gpgpu_shmem_divergence_hist->fprint(fout); - fprintf(fout,"\n"); - fprintf(fout,"warp_inst_classification "); - warp_inst_classification->fprint(fout); - fprintf(fout,"\n"); - fprintf(fout, "gpgpu_n_load_insn = %d\n", gpgpu_n_load_insn); fprintf(fout, "gpgpu_n_store_insn = %d\n", gpgpu_n_store_insn); fprintf(fout, "gpgpu_n_shmem_insn = %d\n", gpgpu_n_shmem_insn); @@ -756,26 +740,9 @@ void shader_core_ctx::fetch() void shader_core_ctx::func_exec_inst( warp_inst_t &inst ) { - unsigned starting_queue_size; execute_warp_inst_t(inst); - if (inst.op_classification) { - m_stats->warp_inst_classification->add2bin(inst.op_classification); - } - if( inst.is_load() || inst.is_store() ) { - starting_queue_size = inst.accessq_count(); + if( inst.is_load() || inst.is_store() ) inst.generate_mem_accesses(); - if ( inst.space.get_type() == global_space ) { - if (inst.is_load()) - m_stats->gpgpu_gmem_ld_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); - else if (inst.is_store()) - m_stats->gpgpu_gmem_st_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); - } - else if ( inst.space.get_type() == shared_space ) { - m_stats->gpgpu_shmem_divergence_hist->add2bin(inst.get_cycles()); - } - - m_stats->gpgpu_mem_divergence_hist->add2bin(inst.accessq_count() - starting_queue_size); - } } void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* next_inst, const active_mask_t &active_mask, unsigned warp_id ) diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 6a40aee..e07096e 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -53,8 +53,6 @@ #include "stats.h" #include "gpu-cache.h" #include "traffic_breakdown.h" -#include "histogram.h" - @@ -1480,15 +1478,7 @@ struct shader_core_stats_pod { int gpgpu_n_mem_read_global; int gpgpu_n_mem_write_global; int gpgpu_n_mem_read_inst; - - //warps combined memory divergence histogram - linear_histogram* gpgpu_mem_divergence_hist; - linear_histogram* gpgpu_gmem_ld_divergence_hist; - linear_histogram* gpgpu_gmem_st_divergence_hist; - linear_histogram* gpgpu_shmem_divergence_hist; - - linear_histogram* warp_inst_classification; - + int gpgpu_n_mem_l2_writeback; int gpgpu_n_mem_l1_write_allocate; int gpgpu_n_mem_l2_write_allocate; @@ -1557,12 +1547,6 @@ public: m_incoming_traffic_stats = new traffic_breakdown("memtocore"); gpgpu_n_shmem_bank_access = (unsigned *)calloc(config->num_shader(), sizeof(unsigned)); - gpgpu_mem_divergence_hist = new linear_histogram(1, "", config->warp_size+1); - gpgpu_gmem_ld_divergence_hist = new linear_histogram(1, "", config->warp_size+1); - gpgpu_gmem_st_divergence_hist = new linear_histogram(1, "", config->warp_size+1); - gpgpu_shmem_divergence_hist = new linear_histogram(1, "", config->warp_size+1); - - warp_inst_classification = new linear_histogram(1, "", 12); m_shader_dynamic_warp_issue_distro.resize( config->num_shader() ); m_shader_warp_slot_issue_distro.resize( config->num_shader() ); @@ -1577,10 +1561,6 @@ public: free(m_n_diverge); free(shader_cycle_distro); free(last_shader_cycle_distro); - free(gpgpu_mem_divergence_hist); - free(gpgpu_gmem_ld_divergence_hist); - free(gpgpu_gmem_st_divergence_hist); - free(warp_inst_classification); } void new_grid() diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc index a18e956..52e2f5e 100644 --- a/src/gpgpusim_entrypoint.cc +++ b/src/gpgpusim_entrypoint.cc @@ -163,8 +163,6 @@ void *gpgpu_sim_thread_concurrent(void*) printf("GPGPU-Sim: ** STOP simulation thread (no work) **\n"); fflush(stdout); } - //g_the_gpu->print_stats(); - if(sim_cycles) { g_the_gpu->print_stats(); g_the_gpu->update_stats(); @@ -272,7 +270,6 @@ void print_simulation_time() s = difference - 60*(m + 60*(h + 24*d)); fflush(stderr); - printf("gpgpu_data_footprint = %u requests at L2\n", g_the_gpu->data_footprint_stats.size()); printf("\n\ngpgpu_simulation_time = %u days, %u hrs, %u min, %u sec (%u sec)\n", (unsigned)d, (unsigned)h, (unsigned)m, (unsigned)s, (unsigned)difference ); printf("gpgpu_simulation_rate = %u (inst/sec)\n", (unsigned)(g_the_gpu->gpu_tot_sim_insn / difference) ); diff --git a/src/stream_manager.cc b/src/stream_manager.cc index 21115c6..3b6cbd5 100644 --- a/src/stream_manager.cc +++ b/src/stream_manager.cc @@ -230,7 +230,7 @@ bool stream_manager::operation( bool * sim) { bool check=check_finished_kernel(); pthread_mutex_lock(&m_lock); - if(check)m_gpu->print_stats(); +// if(check)m_gpu->print_stats(); stream_operation op =front(); if(!op.do_operation( m_gpu )) //not ready to execute { -- cgit v1.3