From 944f6dbf23d792dde360d3a4f2334de3b541de52 Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Mon, 27 Aug 2018 20:28:24 -0400 Subject: fixing ead/write buffer and new configs files --- configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt') diff --git a/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt b/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt index 7820e4e..d372b26 100644 --- a/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt +++ b/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt @@ -1,6 +1,6 @@ //21*1 fly with 32 flits per packet under gpgpusim injection mode use_map = 0; -flit_size = 32; +flit_size = 40; // currently we do not use this, see subnets below network_count = 2; @@ -17,7 +17,7 @@ routing_function = dest_tag; // Flow control num_vcs = 1; -vc_buf_size = 8; +vc_buf_size = 64; wait_for_tail_credit = 0; -- cgit v1.3 From 79a890fc4c22135a368504a5112a0f0a9982659e Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Thu, 20 Sep 2018 16:48:23 -0400 Subject: fixing some config file --- configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt | 4 ++-- configs/4.x-cfgs/SM2_GTX480/gpgpusim.config | 9 ++++++--- configs/4.x-cfgs/SM6_TITANX/gpgpusim.config | 6 +++--- 3 files changed, 11 insertions(+), 8 deletions(-) (limited to 'configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt') diff --git a/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt b/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt index d372b26..c399db9 100644 --- a/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt +++ b/configs/4.x-cfgs/SM2_GTX480/config_fermi_islip.icnt @@ -32,9 +32,9 @@ routing_delay = 0; vc_alloc_delay = 1; sw_alloc_delay = 1; -input_speedup = 2; +input_speedup = 1; output_speedup = 1; -internal_speedup = 1.0; +internal_speedup = 2.0; // Traffic, GPGPU-Sim does not use this diff --git a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config index 35341f7..c96432b 100644 --- a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config +++ b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config @@ -50,13 +50,16 @@ # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. --gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,S:128:8,8 +-gpgpu_cache:dl1 N:32:128:4,L:L:m:N:H,S:64:8,8 -gpgpu_shmem_size 49152 -icnt_flit_size 40 +-gmem_skip_L1D 0 -gpgpu_n_cluster_ejection_buffer_size 32 +-l1_latency 35 +-smem_latency 26 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected -#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,S:32:8,8 +#-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,S:64:8,8 #-gpgpu_shmem_size 16384 # 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache @@ -100,7 +103,7 @@ # To allow 100% DRAM utility, there should at least be enough buffer to sustain # the minimum DRAM latency (100 core cycles). I.e. # Total buffer space required = 100 x 924MHz / 700MHz = 132 --gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_frfcfs_dram_sched_queue_size 64 -gpgpu_dram_return_queue_size 116 # for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config index 8e93723..45a87cd 100644 --- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config @@ -65,9 +65,9 @@ # Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB # Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres are used --gpgpu_cache:dl1 S:48:128:4,L:L:s:N:L,A:256:8,16:0,32 --gpgpu_cache:dl1PrefL1 S:48:128:4,L:L:s:N:L,A:256:8,16:0,32 --gpgpu_cache:dl1PrefShared S:48:128:4,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefL1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 +-gpgpu_cache:dl1PrefShared S:4:128:48,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_shmem_size 49152 -gpgpu_shmem_size_PrefL1 49152 -gpgpu_shmem_size_PrefShared 49152 -- cgit v1.3