From fdbb4aef32a36ff625612c82c58039699af2b23b Mon Sep 17 00:00:00 2001 From: Mahmoud Date: Tue, 9 Oct 2018 12:07:25 -0400 Subject: flushing L1 cache --- configs/4.x-cfgs/SM7_TITANV/gpgpusim.config | 1 + 1 file changed, 1 insertion(+) (limited to 'configs/4.x-cfgs/SM7_TITANV') diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config index de3558a..cc4c931 100644 --- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config @@ -77,6 +77,7 @@ -gpgpu_n_cluster_ejection_buffer_size 32 -l1_latency 28 -smem_latency 19 +-gpgpu_flush_l1_cache 1 # 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache -gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32 -- cgit v1.3