From 4971546a72dff7626bf7ac4eee3d5485b9d380b9 Mon Sep 17 00:00:00 2001 From: Scott Peverelle Date: Tue, 24 May 2016 09:49:36 -0800 Subject: Branch of GTX480 configs for Maxwell board [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21797] --- configs/GeForceGTX750Ti/gpgpusim.config | 133 ++++++ configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml | 538 +++++++++++++++++++++++++ 2 files changed, 671 insertions(+) create mode 100644 configs/GeForceGTX750Ti/gpgpusim.config create mode 100755 configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml (limited to 'configs/GeForceGTX750Ti') diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config new file mode 100644 index 0000000..436cb41 --- /dev/null +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -0,0 +1,133 @@ +# functional simulator specification +-gpgpu_ptx_instruction_classification 0 +-gpgpu_ptx_sim_mode 0 +-gpgpu_ptx_force_max_capability 20 + + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + +# high level architecture configuration +-gpgpu_n_clusters 15 +-gpgpu_n_cores_per_cluster 1 +-gpgpu_n_mem 6 +-gpgpu_n_sub_partition_per_mchannel 2 + +# Fermi clock domains +#-gpgpu_clock_domains ::: +# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided +# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 +-gpgpu_clock_domains 700.0:700.0:700.0:924.0 + +# shader core pipeline config +-gpgpu_shader_registers 32768 + +# This implies a maximum of 48 warps/SM +-gpgpu_shader_core_pipeline 1536:32 +-gpgpu_shader_cta 8 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 2,1,1,2,1,1,2 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,1,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,16,8,8,130 + + +# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb +# ::,::::,::,:** +# ** Optional parameter - Required when mshr_type==Texture Fifo +# Note: Hashing set index function (H) only applies to a set size of 32 or 64. +-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_shmem_size 49152 + +# The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected +#-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 +#-gpgpu_shmem_size 16384 + +# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache +-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2_texture_only 0 + +-gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 +-gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 + +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 +-gpgpu_num_reg_banks 16 + +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 +-gpgpu_shmem_warp_parts 1 + +-gpgpu_max_insn_issue_per_warp 1 + +# interconnection +-network_mode 1 +-inter_config_file config_fermi_islip.icnt + +# memory partition latency config +-rop_latency 120 +-dram_latency 100 + +# dram model config +-gpgpu_dram_scheduler 1 +# The DRAM return queue and the scheduler queue together should provide buffer +# to sustain the memory level parallelism to tolerate DRAM latency +# To allow 100% DRAM utility, there should at least be enough buffer to sustain +# the minimum DRAM latency (100 core cycles). I.e. +# Total buffer space required = 100 x 924MHz / 700MHz = 132 +-gpgpu_frfcfs_dram_sched_queue_size 16 +-gpgpu_dram_return_queue_size 116 + +# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition +-gpgpu_n_mem_per_ctrlr 2 +-gpgpu_dram_buswidth 4 +-gpgpu_dram_burst_length 8 +-dram_data_command_freq_ratio 4 # GDDR5 is QDR +-gpgpu_mem_address_mask 1 +-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.BBBCCCCB.CCSSSSSS + +# GDDR5 timing from hynix H5GQ1H24AFR +# to disable bank groups, set nbkgrp to 1 and tCCDL and tRTPL to 0 +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: + CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" + +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 +# Two Level Scheduler with active and pending pools +#-gpgpu_scheduler two_level_active:6:0:1 +# Loose round robbin scheduler +#-gpgpu_scheduler lrr +# Greedy then oldest scheduler +-gpgpu_scheduler gto + +# stat collection +-gpgpu_memlatency_stat 14 +-gpgpu_runtime_stat 500 +-enable_ptx_file_line_stats 1 +-visualizer_enabled 0 + +# power model configs +-power_simulation_enabled 1 +-gpuwattch_xml_file gpuwattch_gtx480.xml + +# tracing functionality +#-trace_enabled 1 +#-trace_components WARP_SCHEDULER,SCOREBOARD +#-trace_sampling_core 0 diff --git a/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml b/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml new file mode 100755 index 0000000..304e0fd --- /dev/null +++ b/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml @@ -0,0 +1,538 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.3 From 104e6d5f802846f8758d35fa9123f6adc1a2470b Mon Sep 17 00:00:00 2001 From: Scott Peverelle Date: Tue, 24 May 2016 10:34:22 -0800 Subject: GeForceGTX750Ti correlation setup. Modified config file to reflect GTX750Ti architecture. Modified shader.h to allow for larger CTA per warp, to accomodate Maxwell specs. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21798] --- CHANGES | 9 ++-- configs/GeForceGTX750Ti/config_fermi_islip.icnt | 70 +++++++++++++++++++++++++ configs/GeForceGTX750Ti/gpgpusim.config | 35 +++++++------ src/gpgpu-sim/shader.h | 4 +- 4 files changed, 94 insertions(+), 24 deletions(-) create mode 100644 configs/GeForceGTX750Ti/config_fermi_islip.icnt (limited to 'configs/GeForceGTX750Ti') diff --git a/CHANGES b/CHANGES index 054ec9a..f58d10d 100644 --- a/CHANGES +++ b/CHANGES @@ -8,15 +8,14 @@ Version 3.2.3+edits (development branch) versus 3.2.3 - Initial support for CUDA 5.0,5.5,6.0 and 7.5 to get basic sdk running (e.g., template, vectorAdd, ...). The issues required for CUDA 5.5 support were identified by the loneStarGPU group at The University of Texas at Austin and Texas State University. - Removed intersim2 svn repository files - Changed the makefile for cuobjdump_toptxplus,libcuda,intersim2 so that it outputs temporary files into the build directory -- Bug fixes: - - Fixed a bug where sm_version was hard coded to sm_20. Now, it extracts the highest sm version that is lower than - the forced_max_capability configuration in GPGPUSim. - +- Branching config file for GeForceGTX750Ti +- Branching correlation script for GeForceGTX750Ti. Modified config to fit Maxwell architecture. Modified shader.h to allow larger CTA per warp. - Bug fixes: - Fixed bug #81, fix ordering of pushing branch entries to the stack - Fixed a bug where for each icache miss we also count a hit - Fixed bug #88, Ejection buffer and Boundary buffer in Intersim2 initialization with a wrong node number -- Branching config file for GeForceGTX750Ti + - Fixed a bug where sm_version was hard coded to sm_20. Now, it extracts the highest sm version that is lower than + the forced_max_capability configuration in GPGPUSim. Version 3.2.3 versus 3.2.2 - Bug fixes: diff --git a/configs/GeForceGTX750Ti/config_fermi_islip.icnt b/configs/GeForceGTX750Ti/config_fermi_islip.icnt new file mode 100644 index 0000000..7820e4e --- /dev/null +++ b/configs/GeForceGTX750Ti/config_fermi_islip.icnt @@ -0,0 +1,70 @@ +//21*1 fly with 32 flits per packet under gpgpusim injection mode +use_map = 0; +flit_size = 32; + +// currently we do not use this, see subnets below +network_count = 2; + +// Topology +topology = fly; +k = 27; +n = 1; + +// Routing + +routing_function = dest_tag; + +// Flow control + +num_vcs = 1; +vc_buf_size = 8; + +wait_for_tail_credit = 0; + +// Router architecture + +vc_allocator = islip; //separable_input_first; +sw_allocator = islip; //separable_input_first; +alloc_iters = 1; + +credit_delay = 0; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; + +input_speedup = 2; +output_speedup = 1; +internal_speedup = 1.0; + +// Traffic, GPGPU-Sim does not use this + +traffic = uniform; +packet_size ={{1,2,3,4},{10,20}}; +packet_size_rate={{1,1,1,1},{2,1}}; + +// Simulation - Don't change + +sim_type = gpgpusim; +//sim_type = latency; +injection_rate = 0.1; + +subnets = 2; + +// Always use read and write no matter following line +//use_read_write = 1; + + +read_request_subnet = 0; +read_reply_subnet = 1; +write_request_subnet = 0; +write_reply_subnet = 1; + +read_request_begin_vc = 0; +read_request_end_vc = 0; +write_request_begin_vc = 0; +write_request_end_vc = 0; +read_reply_begin_vc = 0; +read_reply_end_vc = 0; +write_reply_begin_vc = 0; +write_reply_end_vc = 0; + diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index 436cb41..5b5ee90 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -9,22 +9,22 @@ -gpgpu_ptx_save_converted_ptxplus 0 # high level architecture configuration --gpgpu_n_clusters 15 +-gpgpu_n_clusters 5 -gpgpu_n_cores_per_cluster 1 --gpgpu_n_mem 6 --gpgpu_n_sub_partition_per_mchannel 2 +-gpgpu_n_mem 2 +-gpgpu_n_sub_partition_per_mchannel 1 # Fermi clock domains #-gpgpu_clock_domains ::: # In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided # by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 700.0:700.0:700.0:924.0 +-gpgpu_clock_domains 1080.0:1080.0:1080.0:1335.0 # shader core pipeline config --gpgpu_shader_registers 32768 +-gpgpu_shader_registers 65536 # This implies a maximum of 48 warps/SM --gpgpu_shader_core_pipeline 1536:32 +-gpgpu_shader_core_pipeline 2048:32 -gpgpu_shader_cta 8 -gpgpu_simd_model 1 @@ -32,13 +32,13 @@ # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB -gpgpu_pipeline_widths 2,1,1,2,1,1,2 -gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 1 +-gpgpu_num_sfu_units 8 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_latency_int 6,12,13,13,210 -ptx_opcode_initiation_int 1,2,2,1,8 --ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_latency_fp 6,12,6,6,374 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,16,8,8,130 @@ -49,14 +49,15 @@ # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. -gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 --gpgpu_shmem_size 49152 +-gpgpu_shmem_size 65536 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected #-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 #-gpgpu_shmem_size 16384 # 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache --gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32 +# Ignore above. Maxwell has 2MB of L2 cache. Configuration is unknown, so making a guess. +-gpgpu_cache:dl2 256:128:16,L:B:m:W:L,A:32:4,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 @@ -82,8 +83,8 @@ -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 120 --dram_latency 100 +-rop_latency 80 +-dram_latency 60 # dram model config -gpgpu_dram_scheduler 1 @@ -96,7 +97,7 @@ -gpgpu_dram_return_queue_size 116 # for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition --gpgpu_n_mem_per_ctrlr 2 +-gpgpu_n_mem_per_ctrlr 4 -gpgpu_dram_buswidth 4 -gpgpu_dram_burst_length 8 -dram_data_command_freq_ratio 4 # GDDR5 is QDR @@ -108,8 +109,8 @@ -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 2 +# Maxwell has four schedulers per core +-gpgpu_num_sched_per_core 4 # Two Level Scheduler with active and pending pools #-gpgpu_scheduler two_level_active:6:0:1 # Loose round robbin scheduler @@ -124,7 +125,7 @@ -visualizer_enabled 0 # power model configs --power_simulation_enabled 1 +-power_simulation_enabled 0 -gpuwattch_xml_file gpuwattch_gtx480.xml # tracing functionality diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index 1aa468b..38d09e9 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -267,7 +267,7 @@ private: inline unsigned hw_tid_from_wid(unsigned wid, unsigned warp_size, unsigned i){return wid * warp_size + i;}; inline unsigned wid_from_hw_tid(unsigned tid, unsigned warp_size){return tid/warp_size;}; -const unsigned WARP_PER_CTA_MAX = 48; +const unsigned WARP_PER_CTA_MAX = 64; typedef std::bitset warp_set_t; int register_bank(int regnum, int wid, unsigned num_banks, unsigned bank_warp_shift); @@ -1331,7 +1331,7 @@ struct shader_core_config : public core_config struct shader_core_stats_pod { - void* shader_core_stats_pod_start[0]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure + void* shader_core_stats_pod_start[]; // DO NOT MOVE FROM THE TOP - spaceless pointer to the start of this structure unsigned long long *shader_cycles; unsigned *m_num_sim_insn; // number of scalar thread instructions committed by this shader core unsigned *m_num_sim_winsn; // number of warp instructions committed by this shader core -- cgit v1.3 From 5c62af183b1a7889e7f59725848fa592ca7cbcef Mon Sep 17 00:00:00 2001 From: Scott Peverelle Date: Tue, 24 May 2016 15:56:09 -0800 Subject: Modified config files to better represent Maxwell architecture; specifically, changed the number of clusters, controllers, and interconnect nodes. Also modified parse_and_compare to fix an occasional division by zero bug. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21812] --- CHANGES | 1 + configs/GeForceGTX750Ti/config_fermi_islip.icnt | 2 +- configs/GeForceGTX750Ti/gpgpusim.config | 29 ++++++++++++------------- 3 files changed, 16 insertions(+), 16 deletions(-) (limited to 'configs/GeForceGTX750Ti') diff --git a/CHANGES b/CHANGES index f58d10d..e3b3177 100644 --- a/CHANGES +++ b/CHANGES @@ -10,6 +10,7 @@ Version 3.2.3+edits (development branch) versus 3.2.3 - Changed the makefile for cuobjdump_toptxplus,libcuda,intersim2 so that it outputs temporary files into the build directory - Branching config file for GeForceGTX750Ti - Branching correlation script for GeForceGTX750Ti. Modified config to fit Maxwell architecture. Modified shader.h to allow larger CTA per warp. +- Additional changes to config file to reflect Maxwell uarch. - Bug fixes: - Fixed bug #81, fix ordering of pushing branch entries to the stack - Fixed a bug where for each icache miss we also count a hit diff --git a/configs/GeForceGTX750Ti/config_fermi_islip.icnt b/configs/GeForceGTX750Ti/config_fermi_islip.icnt index 7820e4e..069ca02 100644 --- a/configs/GeForceGTX750Ti/config_fermi_islip.icnt +++ b/configs/GeForceGTX750Ti/config_fermi_islip.icnt @@ -7,7 +7,7 @@ network_count = 2; // Topology topology = fly; -k = 27; +k = 7; n = 1; // Routing diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index 5b5ee90..0e69098 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -12,18 +12,18 @@ -gpgpu_n_clusters 5 -gpgpu_n_cores_per_cluster 1 -gpgpu_n_mem 2 --gpgpu_n_sub_partition_per_mchannel 1 +-gpgpu_n_sub_partition_per_mchannel 1 # Fermi clock domains #-gpgpu_clock_domains ::: # In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided # by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 1080.0:1080.0:1080.0:1335.0 +-gpgpu_clock_domains 1080.0:1080.0:1080.0:924.0 # shader core pipeline config --gpgpu_shader_registers 65536 +-gpgpu_shader_registers 32768 -# This implies a maximum of 48 warps/SM +# This implies a maximum of 64 warps/SM -gpgpu_shader_core_pipeline 2048:32 -gpgpu_shader_cta 8 -gpgpu_simd_model 1 @@ -32,13 +32,13 @@ # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB -gpgpu_pipeline_widths 2,1,1,2,1,1,2 -gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 8 +-gpgpu_num_sfu_units 1 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 6,12,13,13,210 +-ptx_opcode_latency_int 4,13,4,5,145 -ptx_opcode_initiation_int 1,2,2,1,8 --ptx_opcode_latency_fp 6,12,6,6,374 +-ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,16,8,8,130 @@ -49,15 +49,14 @@ # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. -gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 --gpgpu_shmem_size 65536 +-gpgpu_shmem_size 49152 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected #-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 #-gpgpu_shmem_size 16384 # 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache -# Ignore above. Maxwell has 2MB of L2 cache. Configuration is unknown, so making a guess. --gpgpu_cache:dl2 256:128:16,L:B:m:W:L,A:32:4,4:0,32 +-gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 @@ -83,8 +82,8 @@ -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 80 --dram_latency 60 +-rop_latency 120 +-dram_latency 100 # dram model config -gpgpu_dram_scheduler 1 @@ -97,7 +96,7 @@ -gpgpu_dram_return_queue_size 116 # for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition --gpgpu_n_mem_per_ctrlr 4 +-gpgpu_n_mem_per_ctrlr 2 -gpgpu_dram_buswidth 4 -gpgpu_dram_burst_length 8 -dram_data_command_freq_ratio 4 # GDDR5 is QDR @@ -109,8 +108,8 @@ -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" -# Maxwell has four schedulers per core --gpgpu_num_sched_per_core 4 +# Fermi has two schedulers per core +-gpgpu_num_sched_per_core 2 # Two Level Scheduler with active and pending pools #-gpgpu_scheduler two_level_active:6:0:1 # Loose round robbin scheduler -- cgit v1.3 From fb871c36a565bff2e25f457b8e7a0d5a6ffc4b7f Mon Sep 17 00:00:00 2001 From: Scott Peverelle Date: Wed, 25 May 2016 11:25:09 -0800 Subject: Tweaked Maxwell config to improve correspondence in a number of areas; clock speed, DRAM bus width, L2 cache size etc. Adjusted parse_and_compare to match new clock frequency as per config file. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21818] --- configs/GeForceGTX750Ti/gpgpusim.config | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) (limited to 'configs/GeForceGTX750Ti') diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index 0e69098..9a3d73b 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -18,10 +18,10 @@ #-gpgpu_clock_domains ::: # In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided # by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 --gpgpu_clock_domains 1080.0:1080.0:1080.0:924.0 +-gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0 # shader core pipeline config --gpgpu_shader_registers 32768 +-gpgpu_shader_registers 65536 # This implies a maximum of 64 warps/SM -gpgpu_shader_core_pipeline 2048:32 @@ -32,31 +32,30 @@ # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB -gpgpu_pipeline_widths 2,1,1,2,1,1,2 -gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 1 +-gpgpu_num_sfu_units 32 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" --ptx_opcode_latency_int 4,13,4,5,145 --ptx_opcode_initiation_int 1,2,2,1,8 --ptx_opcode_latency_fp 4,13,4,5,39 --ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_int 6,12,13,13,210 +-ptx_opcode_initiation_int 1,1,1,1,4 +-ptx_opcode_latency_fp 6,12,6,6,374 +-ptx_opcode_initiation_fp 1,1,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,16,8,8,130 - # In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. -gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 --gpgpu_shmem_size 49152 +-gpgpu_shmem_size 65536 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected #-gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:32:8,8 #-gpgpu_shmem_size 16384 -# 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache --gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32 +# 1024 sets, each 128 bytes 8-way for each memory sub partition. This gives 2MB L2 cache +-gpgpu_cache:dl2 1024:128:8,L:B:m:W:L,A:32:4,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 @@ -97,7 +96,7 @@ # for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition -gpgpu_n_mem_per_ctrlr 2 --gpgpu_dram_buswidth 4 +-gpgpu_dram_buswidth 32 -gpgpu_dram_burst_length 8 -dram_data_command_freq_ratio 4 # GDDR5 is QDR -gpgpu_mem_address_mask 1 @@ -108,8 +107,8 @@ -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2" -# Fermi has two schedulers per core --gpgpu_num_sched_per_core 2 +# Maxwell has four schedulers per core +-gpgpu_num_sched_per_core 4 # Two Level Scheduler with active and pending pools #-gpgpu_scheduler two_level_active:6:0:1 # Loose round robbin scheduler -- cgit v1.3 From 65577fdc18e5d9b1d93054a644029ab20c598440 Mon Sep 17 00:00:00 2001 From: Scott Peverelle Date: Thu, 26 May 2016 15:28:47 -0800 Subject: Made additional improvements to Maxwell correlation in config file such as merger of L1/Texture cache. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21837] --- configs/GeForceGTX750Ti/gpgpusim.config | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) (limited to 'configs/GeForceGTX750Ti') diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index 9a3d73b..afd3825 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -14,10 +14,9 @@ -gpgpu_n_mem 2 -gpgpu_n_sub_partition_per_mchannel 1 -# Fermi clock domains +# Maxwell clock domains #-gpgpu_clock_domains ::: -# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided -# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700 +# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number. -gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0 # shader core pipeline config @@ -31,7 +30,7 @@ # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB -gpgpu_pipeline_widths 2,1,1,2,1,1,2 --gpgpu_num_sp_units 2 +-gpgpu_num_sp_units 8 -gpgpu_num_sfu_units 32 # Instruction latencies and initiation intervals @@ -43,11 +42,8 @@ -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,16,8,8,130 -# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb -# ::,::::,::,:** -# ** Optional parameter - Required when mshr_type==Texture Fifo -# Note: Hashing set index function (H) only applies to a set size of 32 or 64. --gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_cache:dl1 none +# 32:128:4,L:L:m:N:H,A:32:8,8 -gpgpu_shmem_size 65536 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected @@ -59,7 +55,7 @@ -gpgpu_cache:dl2_texture_only 0 -gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4 --gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_tex_cache:l1 16:128:32,L:R:m:N:L,F:128:4,128:2 -gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4 # enable operand collector @@ -74,15 +70,15 @@ -gpgpu_shmem_limited_broadcast 0 -gpgpu_shmem_warp_parts 1 --gpgpu_max_insn_issue_per_warp 1 +-gpgpu_max_insn_issue_per_warp 2 # interconnection -network_mode 1 -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 120 --dram_latency 100 +-rop_latency 150 +-dram_latency 130 # dram model config -gpgpu_dram_scheduler 1 @@ -92,9 +88,9 @@ # the minimum DRAM latency (100 core cycles). I.e. # Total buffer space required = 100 x 924MHz / 700MHz = 132 -gpgpu_frfcfs_dram_sched_queue_size 16 --gpgpu_dram_return_queue_size 116 +-gpgpu_dram_return_queue_size 300 -# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition +# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition -gpgpu_n_mem_per_ctrlr 2 -gpgpu_dram_buswidth 32 -gpgpu_dram_burst_length 8 -- cgit v1.3 From 46aad91327a265c2fea2cfe629cc38eadb629200 Mon Sep 17 00:00:00 2001 From: speverel Date: Thu, 2 Jun 2016 11:28:15 -0700 Subject: Added handling of .cc option for arithmetic instructions. NOTE: Only made changes to parse instructions. Carry functionality NOT fully implemented; .cc instructions function like their unmodified ueqivelents. Also modified GTX750Ti config to model L1 data cache as simply not being used for global loads (instead of not existing at all). Changed ptxinfo parsing to avoid crashing when info includes texture information. --- configs/GeForceGTX750Ti/gpgpusim.config | 4 ++-- libcuda/cuda_runtime_api.cc | 8 +++++++- src/cuda-sim/cuda-sim.cc | 2 +- src/cuda-sim/instructions.cc | 2 +- src/cuda-sim/opcodes.def | 2 +- src/cuda-sim/ptx.l | 3 ++- src/cuda-sim/ptx.y | 2 ++ src/cuda-sim/ptx_ir.cc | 2 ++ src/cuda-sim/ptxinfo.l | 1 + src/cuda-sim/ptxinfo.y | 2 ++ 10 files changed, 21 insertions(+), 7 deletions(-) (limited to 'configs/GeForceGTX750Ti') diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index afd3825..be3ae3c 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -42,8 +42,8 @@ -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,16,8,8,130 --gpgpu_cache:dl1 none -# 32:128:4,L:L:m:N:H,A:32:8,8 +-gpgpu_cache:dl1 32:128:4,L:L:m:N:H,A:32:8,8 +-gmem_skip_L1D 1 -gpgpu_shmem_size 65536 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected diff --git a/libcuda/cuda_runtime_api.cc b/libcuda/cuda_runtime_api.cc index 910bebd..e2626d2 100644 --- a/libcuda/cuda_runtime_api.cc +++ b/libcuda/cuda_runtime_api.cc @@ -109,6 +109,7 @@ #include #include #include +#include #include #include #ifdef OPENGL_SUPPORT @@ -1816,10 +1817,15 @@ void __cudaRegisterTexture( int ext ) //passes in a newly created textureReference { + std::string devStr (deviceName); + #if (CUDART_VERSION > 4020) + if (devStr.size() > 2 && devStr.data()[0] == ':' && devStr.data()[1] == ':') + devStr = devStr.replace(0, 2, ""); + #endif CUctx_st *context = GPGPUSim_Context(); gpgpu_t *gpu = context->get_device()->get_gpgpu(); printf("GPGPU-Sim PTX: in __cudaRegisterTexture:\n"); - gpu->gpgpu_ptx_sim_bindNameToTexture(deviceName, hostVar, dim, norm, ext); + gpu->gpgpu_ptx_sim_bindNameToTexture(devStr.data(), hostVar, dim, norm, ext); printf("GPGPU-Sim PTX: int dim = %d\n", dim); printf("GPGPU-Sim PTX: int norm = %d\n", norm); printf("GPGPU-Sim PTX: int ext = %d\n", ext); diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 715be98..15417d1 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -719,7 +719,7 @@ void ptx_instruction::set_opcode_and_latency() break; } break; - case MAD_OP: case MADP_OP: + case MAD_OP: case MADC_OP: //MAD latency switch(get_type()){ case F32_TYPE: diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc index cf7f04a..4dd5ed8 100644 --- a/src/cuda-sim/instructions.cc +++ b/src/cuda-sim/instructions.cc @@ -2421,7 +2421,7 @@ void mad_impl( const ptx_instruction *pI, ptx_thread_info *thread ) mad_def(pI, thread, false); } -void madp_impl( const ptx_instruction *pI, ptx_thread_info *thread ) +void madc_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { mad_def(pI, thread, true); } diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def index 7aaa14f..874acc7 100644 --- a/src/cuda-sim/opcodes.def +++ b/src/cuda-sim/opcodes.def @@ -69,7 +69,7 @@ OP_DEF(LDU_OP,ldu_impl,"ldu",1,5) OP_DEF(LG2_OP,lg2_impl,"lg2",1,4) OP_DEF(MAD24_OP,mad24_impl,"mad24",1,2) OP_DEF(MAD_OP,mad_impl,"mad",1,2) -OP_DEF(MADP_OP,madp_impl,"madp",1,2) +OP_DEF(MADC_OP,madc_impl,"madc",1,2) OP_DEF(MAX_OP,max_impl,"max",1,1) OP_DEF(MEMBAR_OP,membar_impl,"membar",1,3) OP_DEF(MIN_OP,min_impl,"min",1,1) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index dfed936..95ab74c 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -86,7 +86,7 @@ ldu TC; ptx_lval.int_value = LDU_OP; return OPCODE; lg2 TC; ptx_lval.int_value = LG2_OP; return OPCODE; mad24 TC; ptx_lval.int_value = MAD24_OP; return OPCODE; mad TC; ptx_lval.int_value = MAD_OP; return OPCODE; -madp TC; ptx_lval.int_value = MADP_OP; return OPCODE; +madc TC; ptx_lval.int_value = MADC_OP; return OPCODE; max TC; ptx_lval.int_value = MAX_OP; return OPCODE; membar TC; ptx_lval.int_value = MEMBAR_OP; return OPCODE; min TC; ptx_lval.int_value = MIN_OP; return OPCODE; @@ -249,6 +249,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.v4 TC; return V4_TYPE; \.half TC; return HALF_OPTION; /* ptxplus */ +\.cc TC; return EXTP_OPTION; /* extended precision option */ \.equ TC; return EQU_OPTION; \.neu TC; return NEU_OPTION; diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 79faddf..82abcbb 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -103,6 +103,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token COMMA %token PRED %token HALF_OPTION +%token EXTP_OPTION %token EQ_OPTION %token NE_OPTION %token LT_OPTION @@ -438,6 +439,7 @@ option: type_spec | atomic_operation_spec ; | TO_OPTION { add_option(TO_OPTION); } | HALF_OPTION { add_option(HALF_OPTION); } + | EXTP_OPTION { add_option(EXTP_OPTION); } | CA_OPTION { add_option(CA_OPTION); } | CG_OPTION { add_option(CG_OPTION); } | CS_OPTION { add_option(CS_OPTION); } diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc index 751b3f4..8f9c3d2 100644 --- a/src/cuda-sim/ptx_ir.cc +++ b/src/cuda-sim/ptx_ir.cc @@ -1167,6 +1167,8 @@ ptx_instruction::ptx_instruction( int opcode, case HALF_OPTION: m_inst_size = 4; // bytes break; + case EXTP_OPTION: + break; default: assert(0); break; diff --git a/src/cuda-sim/ptxinfo.l b/src/cuda-sim/ptxinfo.l index 99ee1fc..f9b6846 100644 --- a/src/cuda-sim/ptxinfo.l +++ b/src/cuda-sim/ptxinfo.l @@ -59,6 +59,7 @@ unsigned ptxinfo_col = 0; "gmem" TC; return GMEM; "line" TC; return LINE; "for" TC; return FOR; +"textures" TC; return TEXTURES; [_A-Za-z$%][_0-9A-Za-z$]* TC; ptxinfo_lval.string_value = strdup(yytext); return IDENTIFIER; [-]{0,1}[0-9]+ TC; ptxinfo_lval.int_value = atoi(yytext); return INT_OPERAND; diff --git a/src/cuda-sim/ptxinfo.y b/src/cuda-sim/ptxinfo.y index 294412d..faa33eb 100644 --- a/src/cuda-sim/ptxinfo.y +++ b/src/cuda-sim/ptxinfo.y @@ -54,6 +54,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token LINE %token WARNING %token FOR +%token TEXTURES %{ #include @@ -104,6 +105,7 @@ info: USED INT_OPERAND REGS { ptxinfo_regs($2); } | INT_OPERAND BYTES SMEM { ptxinfo_smem($1,0); } | INT_OPERAND BYTES CMEM { ptxinfo_cmem($1,0); } | INT_OPERAND REGS { ptxinfo_regs($1); } + | INT_OPERAND TEXTURES {} ; tuple: INT_OPERAND PLUS INT_OPERAND BYTES { g_declared=$1; g_system=$3; } -- cgit v1.3 From 068e34728a0706cd8671b816eea466491ab2db06 Mon Sep 17 00:00:00 2001 From: speverel Date: Thu, 2 Jun 2016 13:29:46 -0700 Subject: Updated parser and config file to support compute versions up to 5.2. Full support is NOT claimed; however, it has been tested to work on a number of CUDA version 7.5 benchmarks such as matrix multiply and simpleMultiGPU. --- configs/GeForceGTX750Ti/gpgpusim.config | 2 +- src/cuda-sim/ptx.l | 1 + src/cuda-sim/ptx.y | 2 ++ 3 files changed, 4 insertions(+), 1 deletion(-) (limited to 'configs/GeForceGTX750Ti') diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index be3ae3c..7920763 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -1,7 +1,7 @@ # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 20 +-gpgpu_ptx_force_max_capability 52 # SASS execution (only supported with CUDA >= 4.0) diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l index 95ab74c..66ff48f 100644 --- a/src/cuda-sim/ptx.l +++ b/src/cuda-sim/ptx.l @@ -181,6 +181,7 @@ breakaddr TC; ptx_lval.int_value = BREAKADDR_OP; return OPCODE; \.version TC; return VERSION_DIRECTIVE; \.visible TC; return VISIBLE_DIRECTIVE; \.address_size TC; return ADDRESS_SIZE_DIRECTIVE; +\.weak TC; return WEAK_DIRECTIVE; \.constptr TC; return CONSTPTR_DIRECTIVE; /* Ptx plus directive for pointer to constant memory */ \.ptr TC; return PTR_DIRECTIVE; /* Added for new OpenCL genrated code */ diff --git a/src/cuda-sim/ptx.y b/src/cuda-sim/ptx.y index 82abcbb..fca94db 100644 --- a/src/cuda-sim/ptx.y +++ b/src/cuda-sim/ptx.y @@ -47,6 +47,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. %token PTR_DIRECTIVE %token ENTRY_DIRECTIVE %token EXTERN_DIRECTIVE +%token WEAK_DIRECTIVE %token FILE_DIRECTIVE %token FUNC_DIRECTIVE %token GLOBAL_DIRECTIVE @@ -243,6 +244,7 @@ function_decl_header: ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".ent | VISIBLE_DIRECTIVE ENTRY_DIRECTIVE { $$ = 1; g_func_decl=1; func_header(".entry"); } | FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } | VISIBLE_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } + | WEAK_DIRECTIVE FUNC_DIRECTIVE { $$ = 0; g_func_decl=1; func_header(".func"); } | EXTERN_DIRECTIVE FUNC_DIRECTIVE { $$ = 2; g_func_decl=1; func_header(".func"); } ; -- cgit v1.3 From 71ccce6074de5d7eef3fbe2cda1dbca008549f07 Mon Sep 17 00:00:00 2001 From: speverel Date: Fri, 3 Jun 2016 15:24:40 -0700 Subject: Added support for %laneid SFR. Also added a notice clarifying that power modeling for GTX750Ti is currently completely untested and should not be considered supported. --- configs/GeForceGTX750Ti/gpgpusim.config | 4 +++- configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml | 1 + src/cuda-sim/ptx_sim.cc | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) (limited to 'configs/GeForceGTX750Ti') diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config index 7920763..8b030b6 100644 --- a/configs/GeForceGTX750Ti/gpgpusim.config +++ b/configs/GeForceGTX750Ti/gpgpusim.config @@ -119,8 +119,10 @@ -visualizer_enabled 0 # power model configs +# power modeling is currently disabled for GTX750Ti. The gpuwattch_gtx750ti.xml file present is only a placeholder and has NOT been tested for accuracy. +# proper modeling of Maxwell power is planned, but should be considered completely unsupported at present. -power_simulation_enabled 0 --gpuwattch_xml_file gpuwattch_gtx480.xml +-gpuwattch_xml_file gpuwattch_gtx750Ti.xml # tracing functionality #-trace_enabled 1 diff --git a/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml b/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml index 304e0fd..e2b2324 100755 --- a/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml +++ b/configs/GeForceGTX750Ti/gpuwattch_gtx750Ti.xml @@ -1,3 +1,4 @@ + diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc index 9b32e68..09844ae 100644 --- a/src/cuda-sim/ptx_sim.cc +++ b/src/cuda-sim/ptx_sim.cc @@ -240,7 +240,7 @@ unsigned ptx_thread_info::get_builtin( int builtin_id, unsigned dim_mod ) } case GRIDID_REG: return m_gridid; - case LANEID_REG: feature_not_implemented( "%laneid" ); return 0; + case LANEID_REG: return get_hw_tid() % m_core->get_warp_size(); case LANEMASK_EQ_REG: feature_not_implemented( "%lanemask_eq" ); return 0; case LANEMASK_LE_REG: feature_not_implemented( "%lanemask_le" ); return 0; case LANEMASK_LT_REG: feature_not_implemented( "%lanemask_lt" ); return 0; -- cgit v1.3