From ff6c395da7b70d9cdbb72a8cfc3721a7f27a2a25 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Mon, 30 Oct 2017 17:08:07 -0400 Subject: Update gpgpusim.config --- configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 23 +++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) (limited to 'configs/PascalTitanX') diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 782edf6..2f09ab6 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -35,18 +35,23 @@ # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB ## Pascal GP102 has 4 SP SIMD units and 4 SFU units ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,1,4,4,1,8 --gpgpu_num_sp_units 4 --gpgpu_num_sfu_units 4 +-gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 2 +-gpgpu_num_dp_units 1 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" +# All Div operations are executed on SFU unit +# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2 -ptx_opcode_latency_int 4,13,4,5,145 -ptx_opcode_initiation_int 1,1,1,1,4 -ptx_opcode_latency_fp 4,13,4,5,39 -ptx_opcode_initiation_fp 1,2,1,1,4 -ptx_opcode_latency_dp 8,19,8,8,330 --ptx_opcode_initiation_dp 4,8,4,4,130 +-ptx_opcode_initiation_dp 8,8,8,8,130 +-ptx_opcode_initiation_sfu 4 +-ptx_opcode_latency_sfu 8 # ::,::::,::,:** # ** Optional parameter - Required when mshr_type==Texture Fifo @@ -54,21 +59,21 @@ # Pascal GP102 has 96KB Shared memory # Pascal GP102 has 64KB L1 cache # The defulat is to disable the L1 cache, unless cache modifieres is used --gpgpu_cache:dl1 64:128:6,L:L:m:N:H,A:128:8,16 +-gpgpu_cache:dl1 N:64:128:6,L:L:m:N:H,A:128:8,16 -gpgpu_shmem_size 98304 -gmem_skip_L1D 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32 +-gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:128:8,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 # 4 KB Inst. --gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4 +-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 # 48 KB Tex --gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 # 12 KB Const --gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4 +-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 # enable operand collector ## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units -- cgit v1.3 From 4aa3b5158f0e70e83cfe44dae79cd75110c52eb7 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Mon, 30 Oct 2017 17:08:45 -0400 Subject: Update gpgpusim.config --- configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'configs/PascalTitanX') diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 2f09ab6..7dfd6d5 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -36,8 +36,8 @@ ## Pascal GP102 has 4 SP SIMD units and 4 SFU units ## we need to scale the number of pipeline registers to be equal to the number of SP units -gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5 --gpgpu_num_sp_units 2 --gpgpu_num_sfu_units 2 +-gpgpu_num_sp_units 4 +-gpgpu_num_sfu_units 4 -gpgpu_num_dp_units 1 # Instruction latencies and initiation intervals -- cgit v1.3 From 178abb228229332c4717c5fd565a83875c3d5c9e Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Mon, 30 Oct 2017 18:51:10 -0400 Subject: Update gpgpusim.config --- configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'configs/PascalTitanX') diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 7dfd6d5..82dfa9a 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -32,10 +32,10 @@ -gpgpu_simd_model 1 # Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB ## Pascal GP102 has 4 SP SIMD units and 4 SFU units ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5 +-gpgpu_pipeline_widths 4,1,4,1,4,1,4,1,9 -gpgpu_num_sp_units 4 -gpgpu_num_sfu_units 4 -gpgpu_num_dp_units 1 @@ -77,15 +77,18 @@ # enable operand collector ## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units --gpgpu_operand_collector_num_units_sp 20 --gpgpu_operand_collector_num_units_sfu 4 +-gpgpu_operand_collector_num_units_sp 12 +-gpgpu_operand_collector_num_units_sfu 6 -gpgpu_operand_collector_num_units_mem 8 +-gpgpu_operand_collector_num_units_dp 6 -gpgpu_operand_collector_num_in_ports_sp 4 -gpgpu_operand_collector_num_out_ports_sp 4 --gpgpu_operand_collector_num_in_ports_sfu 1 --gpgpu_operand_collector_num_out_ports_sfu 1 +-gpgpu_operand_collector_num_in_ports_sfu 4 +-gpgpu_operand_collector_num_out_ports_sfu 4 -gpgpu_operand_collector_num_in_ports_mem 1 -gpgpu_operand_collector_num_out_ports_mem 1 +-gpgpu_operand_collector_num_in_ports_dp 1 +-gpgpu_operand_collector_num_out_ports_dp 1 # gpgpu_num_reg_banks should be increased to 32 -gpgpu_num_reg_banks 32 -- cgit v1.3 From 4df2f7d2499600fa0f0c5642c07fed6576aa5713 Mon Sep 17 00:00:00 2001 From: "Mahmoud Khairy A. Abdallah" Date: Mon, 30 Oct 2017 22:36:16 -0400 Subject: fixing TITANX config --- configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'configs/PascalTitanX') diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 82dfa9a..4191eb0 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -64,16 +64,16 @@ -gmem_skip_L1D 1 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache --gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:128:8,4:0,32 +-gpgpu_cache:dl2 N:64:128:16,L:B:m:W:L,A:128:8,4:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 32:32:32:32 # 4 KB Inst. --gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 +-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,A:2:48,4 # 48 KB Tex -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 # 12 KB Const --gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 +-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,A:2:64,4 # enable operand collector ## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units -- cgit v1.3 From 8719ea402730f6f429e32d63304f9af79bb83df0 Mon Sep 17 00:00:00 2001 From: Mahmoud Abdallah Date: Sun, 19 Nov 2017 00:29:29 -0500 Subject: improving the accuracy of titanX --- configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'configs/PascalTitanX') diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config index 4191eb0..4407870 100644 --- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config @@ -21,7 +21,7 @@ #-gpgpu_clock_domains ::: # Pascal NVIDIA TITAN X clock domains are adopted from # https://en.wikipedia.org/wiki/GeForce_10_series --gpgpu_clock_domains 1417.0:2834.0:1417.0:2500.0 +-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0 # shader core pipeline config -gpgpu_shader_registers 65536 @@ -105,7 +105,7 @@ -inter_config_file config_fermi_islip.icnt # memory partition latency config --rop_latency 120 +-rop_latency 100 -dram_latency 100 # dram model config @@ -130,8 +130,8 @@ # Use the same GDDR5 timing from hynix H5GQ1H24AFR # disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 --gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40: - CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0" +-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: + CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" # Pascal GP102 has four schedulers per core -gpgpu_num_sched_per_core 4 -- cgit v1.3